1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s 3 4--- 5name: fconstant_v_s32 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9 10body: | 11 bb.0: 12 ; GCN-LABEL: name: fconstant_v_s32 13 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec 14 ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec 15 ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec 16 ; GCN: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec 17 ; GCN: $vgpr0 = COPY [[V_MOV_B32_e32_]] 18 ; GCN: $vgpr1 = COPY [[V_MOV_B32_e32_1]] 19 ; GCN: S_ENDPGM 0, implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]] 20 %0:vgpr(s32) = G_FCONSTANT float 1.0 21 %1:vgpr(s32) = G_FCONSTANT float 8.0 22 %2:vgpr(s32) = G_FCONSTANT float 1.0 23 %3:vgpr(s32) = G_FCONSTANT float 8.0 24 $vgpr0 = COPY %0 25 $vgpr1 = COPY %1 26 S_ENDPGM 0, implicit %2 , implicit %3 27... 28 29--- 30name: fconstant_s_s32 31legalized: true 32regBankSelected: true 33tracksRegLiveness: true 34 35body: | 36 bb.0: 37 ; GCN-LABEL: name: fconstant_s_s32 38 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1065353216 39 ; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1090519040 40 ; GCN: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 3212836864 41 ; GCN: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 3238002688 42 ; GCN: $sgpr0 = COPY [[S_MOV_B32_]] 43 ; GCN: $sgpr1 = COPY [[S_MOV_B32_1]] 44 ; GCN: S_ENDPGM 0, implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]] 45 %0:sgpr(s32) = G_FCONSTANT float 1.0 46 %1:sgpr(s32) = G_FCONSTANT float 8.0 47 %2:sgpr(s32) = G_FCONSTANT float -1.0 48 %3:sgpr(s32) = G_FCONSTANT float -8.0 49 $sgpr0 = COPY %0 50 $sgpr1 = COPY %1 51 S_ENDPGM 0, implicit %2 , implicit %3 52 53... 54 55--- 56name: fconstant_v_s64 57legalized: true 58regBankSelected: true 59tracksRegLiveness: true 60 61body: | 62 bb.0: 63 ; GCN-LABEL: name: fconstant_v_s64 64 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 65 ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1072693248, implicit $exec 66 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 67 ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 68 ; GCN: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1075838976, implicit $exec 69 ; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_2]], %subreg.sub0, [[V_MOV_B32_e32_3]], %subreg.sub1 70 ; GCN: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 71 ; GCN: [[V_MOV_B32_e32_5:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1073741824, implicit $exec 72 ; GCN: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_4]], %subreg.sub0, [[V_MOV_B32_e32_5]], %subreg.sub1 73 ; GCN: [[V_MOV_B32_e32_6:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 74 ; GCN: [[V_MOV_B32_e32_7:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1076101120, implicit $exec 75 ; GCN: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_6]], %subreg.sub0, [[V_MOV_B32_e32_7]], %subreg.sub1 76 ; GCN: $vgpr0_vgpr1 = COPY [[REG_SEQUENCE]] 77 ; GCN: $vgpr2_vgpr3 = COPY [[REG_SEQUENCE1]] 78 ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE2]], implicit [[REG_SEQUENCE3]] 79 %0:vgpr(s64) = G_FCONSTANT double 1.0 80 %1:vgpr(s64) = G_FCONSTANT double 8.0 81 %2:vgpr(s64) = G_FCONSTANT double -2.0 82 %3:vgpr(s64) = G_FCONSTANT double 10.0 83 $vgpr0_vgpr1 = COPY %0 84 $vgpr2_vgpr3 = COPY %1 85 S_ENDPGM 0, implicit %2 , implicit %3 86 87... 88 89--- 90name: fconstant_s_s64 91legalized: true 92regBankSelected: true 93tracksRegLiveness: true 94 95body: | 96 bb.0: 97 ; GCN-LABEL: name: fconstant_s_s64 98 ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 4607182418800017408 99 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 100 ; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1075838976 101 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 102 ; GCN: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 -4611686018427387904 103 ; GCN: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 0 104 ; GCN: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 -1071382528 105 ; GCN: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_2]], %subreg.sub0, [[S_MOV_B32_3]], %subreg.sub1 106 ; GCN: $sgpr0_sgpr1 = COPY [[S_MOV_B64_]] 107 ; GCN: $sgpr2_sgpr3 = COPY [[REG_SEQUENCE]] 108 ; GCN: S_ENDPGM 0, implicit [[S_MOV_B64_]], implicit [[REG_SEQUENCE]], implicit [[S_MOV_B64_1]], implicit [[REG_SEQUENCE1]] 109 %0:sgpr(s64) = G_FCONSTANT double 1.0 110 %1:sgpr(s64) = G_FCONSTANT double 8.0 111 %2:sgpr(s64) = G_FCONSTANT double -2.0 112 %3:sgpr(s64) = G_FCONSTANT double -10.0 113 $sgpr0_sgpr1 = COPY %0 114 $sgpr2_sgpr3 = COPY %1 115 S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2 , implicit %3 116... 117 118--- 119name: fconstant_v_s16 120legalized: true 121regBankSelected: true 122tracksRegLiveness: true 123 124body: | 125 bb.0: 126 ; GCN-LABEL: name: fconstant_v_s16 127 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 15360, implicit $exec 128 ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 18432, implicit $exec 129 ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 15360, implicit $exec 130 ; GCN: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 18432, implicit $exec 131 ; GCN: $vgpr0 = COPY [[V_MOV_B32_e32_]] 132 ; GCN: $vgpr1 = COPY [[V_MOV_B32_e32_1]] 133 ; GCN: S_ENDPGM 0, implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]] 134 %0:vgpr(s16) = G_FCONSTANT half 1.0 135 %1:vgpr(s16) = G_FCONSTANT half 8.0 136 %2:vgpr(s32) = G_ANYEXT %0 137 %3:vgpr(s32) = G_ANYEXT %1 138 139 ; Test without already assigned register class 140 %4:vgpr(s16) = G_FCONSTANT half 1.0 141 %5:vgpr(s16) = G_FCONSTANT half 8.0 142 $vgpr0 = COPY %2 143 $vgpr1 = COPY %3 144 S_ENDPGM 0, implicit %4, implicit %5 145 146... 147 148--- 149name: fconstant_s_s16 150legalized: true 151regBankSelected: true 152tracksRegLiveness: true 153 154body: | 155 bb.0: 156 ; GCN-LABEL: name: fconstant_s_s16 157 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15360 158 ; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 18432 159 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] 160 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]] 161 ; GCN: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 15360 162 ; GCN: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 18432 163 ; GCN: $sgpr0 = COPY [[COPY]] 164 ; GCN: $sgpr1 = COPY [[COPY1]] 165 ; GCN: S_ENDPGM 0, implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]] 166 %0:sgpr(s16) = G_FCONSTANT half 1.0 167 %1:sgpr(s16) = G_FCONSTANT half 8.0 168 %2:vgpr(s32) = G_ANYEXT %0 169 %3:vgpr(s32) = G_ANYEXT %1 170 171 ; Test without already assigned register class 172 %4:sgpr(s16) = G_FCONSTANT half 1.0 173 %5:sgpr(s16) = G_FCONSTANT half 8.0 174 $sgpr0 = COPY %2 175 $sgpr1 = COPY %3 176 S_ENDPGM 0, implicit %4, implicit %5 177 178... 179