1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX6 %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX8 %s
4# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
5# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX10 %s
6
7---
8name: usubo_s32_s1_sss
9legalized: true
10regBankSelected: true
11
12body: |
13  bb.0:
14    liveins: $sgpr0, $sgpr1
15
16    ; GFX6-LABEL: name: usubo_s32_s1_sss
17    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
18    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
19    ; GFX6: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
20    ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
21    ; GFX6: $scc = COPY [[COPY2]]
22    ; GFX6: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
23    ; GFX6: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
24    ; GFX8-LABEL: name: usubo_s32_s1_sss
25    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
26    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
27    ; GFX8: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
28    ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
29    ; GFX8: $scc = COPY [[COPY2]]
30    ; GFX8: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
31    ; GFX8: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
32    ; GFX9-LABEL: name: usubo_s32_s1_sss
33    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
34    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
35    ; GFX9: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
36    ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
37    ; GFX9: $scc = COPY [[COPY2]]
38    ; GFX9: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
39    ; GFX9: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
40    ; GFX10-LABEL: name: usubo_s32_s1_sss
41    ; GFX10: $vcc_hi = IMPLICIT_DEF
42    ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
43    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
44    ; GFX10: [[S_SUB_U32_:%[0-9]+]]:sreg_32 = S_SUB_U32 [[COPY]], [[COPY1]], implicit-def $scc
45    ; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
46    ; GFX10: $scc = COPY [[COPY2]]
47    ; GFX10: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
48    ; GFX10: S_ENDPGM 0, implicit [[S_SUB_U32_]], implicit [[S_CSELECT_B32_]]
49    %0:sgpr(s32) = COPY $sgpr0
50    %1:sgpr(s32) = COPY $sgpr1
51    %2:sgpr(s32), %3:sgpr(s32) = G_USUBO %0, %1
52    %4:sgpr(s32) = G_SELECT %3, %0, %1
53    S_ENDPGM 0, implicit %2, implicit %4
54...
55
56---
57name: usubo_s32_s1_vvv
58legalized: true
59regBankSelected: true
60
61body: |
62  bb.0:
63    liveins: $vgpr0, $vgpr1
64
65    ; GFX6-LABEL: name: usubo_s32_s1_vvv
66    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
67    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
68    ; GFX6: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
69    ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_SUB_CO_U32_e64_1]], implicit $exec
70    ; GFX6: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
71    ; GFX8-LABEL: name: usubo_s32_s1_vvv
72    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
73    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
74    ; GFX8: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
75    ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_SUB_CO_U32_e64_1]], implicit $exec
76    ; GFX8: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
77    ; GFX9-LABEL: name: usubo_s32_s1_vvv
78    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
79    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
80    ; GFX9: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
81    ; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_SUB_CO_U32_e64_1]], implicit $exec
82    ; GFX9: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
83    ; GFX10-LABEL: name: usubo_s32_s1_vvv
84    ; GFX10: $vcc_hi = IMPLICIT_DEF
85    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
86    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
87    ; GFX10: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
88    ; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_SUB_CO_U32_e64_1]], implicit $exec
89    ; GFX10: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
90    %0:vgpr(s32) = COPY $vgpr0
91    %1:vgpr(s32) = COPY $vgpr1
92    %2:vgpr(s32), %3:vcc(s1) = G_USUBO %0, %1
93    %4:vgpr(s32) = G_SELECT %3, %0, %1
94    S_ENDPGM 0, implicit %2, implicit %4
95...
96
97---
98name: usubo_s32_s1_vsv
99legalized: true
100regBankSelected: true
101
102body: |
103  bb.0:
104    liveins: $sgpr0, $vgpr0
105
106    ; GFX6-LABEL: name: usubo_s32_s1_vsv
107    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
108    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
109    ; GFX6: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
110    ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
111    ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
112    ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_CO_U32_e64_1]], implicit $exec
113    ; GFX6: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
114    ; GFX8-LABEL: name: usubo_s32_s1_vsv
115    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
116    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
117    ; GFX8: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
118    ; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
119    ; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
120    ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_CO_U32_e64_1]], implicit $exec
121    ; GFX8: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
122    ; GFX9-LABEL: name: usubo_s32_s1_vsv
123    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
124    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
125    ; GFX9: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
126    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
127    ; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
128    ; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_CO_U32_e64_1]], implicit $exec
129    ; GFX9: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
130    ; GFX10-LABEL: name: usubo_s32_s1_vsv
131    ; GFX10: $vcc_hi = IMPLICIT_DEF
132    ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
133    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
134    ; GFX10: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
135    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
136    ; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
137    ; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_CO_U32_e64_1]], implicit $exec
138    ; GFX10: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
139    %0:sgpr(s32) = COPY $sgpr0
140    %1:vgpr(s32) = COPY $vgpr0
141    %2:vgpr(s32), %3:vcc(s1) = G_USUBO %0, %1
142    %4:vgpr(s32) = G_CONSTANT i32 0
143    %5:vgpr(s32) = G_CONSTANT i32 1
144    %6:vgpr(s32) = G_SELECT %3, %4, %5
145    S_ENDPGM 0, implicit %2, implicit %6
146...
147
148---
149name: usubo_s32_s1_vvs
150legalized: true
151regBankSelected: true
152
153body: |
154  bb.0:
155    liveins: $sgpr0, $vgpr0
156
157    ; GFX6-LABEL: name: usubo_s32_s1_vvs
158    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
159    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
160    ; GFX6: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
161    ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
162    ; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
163    ; GFX6: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_CO_U32_e64_1]], implicit $exec
164    ; GFX6: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
165    ; GFX8-LABEL: name: usubo_s32_s1_vvs
166    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
167    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
168    ; GFX8: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
169    ; GFX8: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
170    ; GFX8: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
171    ; GFX8: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_CO_U32_e64_1]], implicit $exec
172    ; GFX8: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
173    ; GFX9-LABEL: name: usubo_s32_s1_vvs
174    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
175    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
176    ; GFX9: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
177    ; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
178    ; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
179    ; GFX9: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_CO_U32_e64_1]], implicit $exec
180    ; GFX9: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
181    ; GFX10-LABEL: name: usubo_s32_s1_vvs
182    ; GFX10: $vcc_hi = IMPLICIT_DEF
183    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
184    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
185    ; GFX10: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_SUB_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
186    ; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
187    ; GFX10: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
188    ; GFX10: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_1]], 0, [[V_MOV_B32_e32_]], [[V_SUB_CO_U32_e64_1]], implicit $exec
189    ; GFX10: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
190    %0:vgpr(s32) = COPY $vgpr0
191    %1:sgpr(s32) = COPY $sgpr0
192    %2:vgpr(s32), %3:vcc(s1) = G_USUBO %0, %1
193    %4:vgpr(s32) = G_CONSTANT i32 0
194    %5:vgpr(s32) = G_CONSTANT i32 1
195    %6:vgpr(s32) = G_SELECT %3, %4, %5
196    S_ENDPGM 0, implicit %2, implicit %6
197...
198