1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
3
4---
5
6name: zext_sgpr_s1_to_sgpr_s32
7legalized:       true
8regBankSelected: true
9body: |
10  bb.0:
11    liveins: $sgpr0
12
13    ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32
14    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
15    ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
16    ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
17    %0:sgpr(s32) = COPY $sgpr0
18    %1:sgpr(s1) = G_TRUNC %0
19    %2:sgpr(s32) = G_ZEXT %1
20    $sgpr0 = COPY %2
21...
22
23---
24
25name: zext_sgpr_s1_to_sgpr_s64
26legalized:       true
27regBankSelected: true
28body: |
29  bb.0:
30    liveins: $sgpr0
31
32    ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s64
33    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
34    ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
35    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
36    ; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
37    ; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
38    %0:sgpr(s32) = COPY $sgpr0
39    %1:sgpr(s1) = G_TRUNC %0
40    %2:sgpr(s64) = G_ZEXT %1
41    $sgpr0_sgpr1 = COPY %2
42...
43
44---
45
46name: zext_sgpr_s16_to_sgpr_s32
47legalized:       true
48regBankSelected: true
49body: |
50  bb.0:
51    liveins: $sgpr0
52
53    ; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32
54    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
55    ; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
56    ; GCN: $sgpr0 = COPY [[S_BFE_U32_]]
57    %0:sgpr(s32) = COPY $sgpr0
58    %1:sgpr(s16) = G_TRUNC %0
59    %2:sgpr(s32) = G_ZEXT %1
60    $sgpr0 = COPY %2
61
62...
63
64---
65
66name: zext_sgpr_s16_to_sgpr_s64
67legalized:       true
68regBankSelected: true
69body: |
70  bb.0:
71    liveins: $sgpr0
72
73    ; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s64
74    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
75    ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
76    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
77    ; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
78    ; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
79    %0:sgpr(s32) = COPY $sgpr0
80    %1:sgpr(s16) = G_TRUNC %0
81    %2:sgpr(s64) = G_ZEXT %1
82    $sgpr0_sgpr1 = COPY %2
83
84...
85
86# ---
87
88# name: zext_vcc_s1_to_vgpr_s32
89# legalized:       true
90# regBankSelected: true
91# body: |
92#   bb.0:
93#     liveins: $vgpr0
94
95#     %0:vgpr(s32) = COPY $vgpr0
96#     %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
97#     %2:vgpr(s32) = G_ZEXT %1
98#     $vgpr0 = COPY %2
99# ...
100
101---
102
103name: zext_vgpr_s1_to_vgpr_s32
104legalized:       true
105regBankSelected: true
106body: |
107  bb.0:
108    liveins: $vgpr0
109
110    ; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s32
111    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
112    ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
113    ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
114    %0:vgpr(s32) = COPY $vgpr0
115    %1:vgpr(s1) = G_TRUNC %0
116    %2:vgpr(s32) = G_ZEXT %1
117    $vgpr0 = COPY %2
118...
119
120---
121
122name: zext_vgpr_s16_to_vgpr_s32
123legalized:       true
124regBankSelected: true
125body: |
126  bb.0:
127    liveins: $vgpr0
128
129    ; GCN-LABEL: name: zext_vgpr_s16_to_vgpr_s32
130    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
131    ; GCN: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[COPY]], 0, 16, implicit $exec
132    ; GCN: $vgpr0 = COPY [[V_BFE_U32_]]
133    %0:vgpr(s32) = COPY $vgpr0
134    %1:vgpr(s16) = G_TRUNC %0
135    %2:vgpr(s32) = G_ZEXT %1
136    $vgpr0 = COPY %2
137
138...
139
140---
141
142name: zext_sgpr_reg_class_s1_to_sgpr_s32
143legalized:       true
144regBankSelected: true
145body: |
146  bb.0:
147    liveins: $sgpr0
148
149    ; GCN-LABEL: name: zext_sgpr_reg_class_s1_to_sgpr_s32
150    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
151    ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
152    ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
153    %0:sgpr(s32) = COPY $sgpr0
154    %1:sreg_32(s1) = G_TRUNC %0
155    %2:sgpr(s32) = G_ZEXT %1
156    $sgpr0 = COPY %2
157...
158