1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
3
4define amdgpu_kernel void @udiv32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
5; GFX9-LABEL: udiv32_invariant_denom:
6; GFX9:       ; %bb.0: ; %bb
7; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
8; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
9; GFX9-NEXT:    s_mov_b64 s[4:5], 0
10; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
11; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
12; GFX9-NEXT:    s_sub_i32 s3, 0, s2
13; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
14; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
15; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
16; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
17; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
18; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
19; GFX9-NEXT:  BB0_1: ; %bb3
20; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
21; GFX9-NEXT:    v_mul_lo_u32 v3, s5, v0
22; GFX9-NEXT:    v_mul_hi_u32 v4, s4, v0
23; GFX9-NEXT:    v_mov_b32_e32 v2, s1
24; GFX9-NEXT:    v_mov_b32_e32 v1, s0
25; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
26; GFX9-NEXT:    v_mul_lo_u32 v4, s3, v3
27; GFX9-NEXT:    v_not_b32_e32 v6, v3
28; GFX9-NEXT:    v_mul_lo_u32 v6, s2, v6
29; GFX9-NEXT:    v_add_u32_e32 v5, 1, v3
30; GFX9-NEXT:    v_add_u32_e32 v4, s4, v4
31; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v4
32; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
33; GFX9-NEXT:    v_add_u32_e32 v5, s4, v6
34; GFX9-NEXT:    s_add_u32 s4, s4, 1
35; GFX9-NEXT:    s_addc_u32 s5, s5, 0
36; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
37; GFX9-NEXT:    s_add_u32 s0, s0, 4
38; GFX9-NEXT:    s_addc_u32 s1, s1, 0
39; GFX9-NEXT:    v_add_u32_e32 v5, 1, v3
40; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v4
41; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
42; GFX9-NEXT:    s_cmpk_eq_i32 s4, 0x400
43; GFX9-NEXT:    global_store_dword v[1:2], v3, off
44; GFX9-NEXT:    s_cbranch_scc0 BB0_1
45; GFX9-NEXT:  ; %bb.2: ; %bb2
46; GFX9-NEXT:    s_endpgm
47bb:
48  br label %bb3
49
50bb2:                                              ; preds = %bb3
51  ret void
52
53bb3:                                              ; preds = %bb3, %bb
54  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
55  %tmp4 = udiv i32 %tmp, %arg1
56  %tmp5 = zext i32 %tmp to i64
57  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
58  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
59  %tmp7 = add nuw nsw i32 %tmp, 1
60  %tmp8 = icmp eq i32 %tmp7, 1024
61  br i1 %tmp8, label %bb2, label %bb3
62}
63
64define amdgpu_kernel void @urem32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
65; GFX9-LABEL: urem32_invariant_denom:
66; GFX9:       ; %bb.0: ; %bb
67; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
68; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
69; GFX9-NEXT:    s_mov_b64 s[4:5], 0
70; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
71; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
72; GFX9-NEXT:    s_sub_i32 s3, 0, s2
73; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
74; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
75; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
76; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
77; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
78; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
79; GFX9-NEXT:  BB1_1: ; %bb3
80; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
81; GFX9-NEXT:    v_mul_lo_u32 v3, s5, v0
82; GFX9-NEXT:    v_mul_hi_u32 v4, s4, v0
83; GFX9-NEXT:    v_mov_b32_e32 v2, s1
84; GFX9-NEXT:    v_mov_b32_e32 v1, s0
85; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
86; GFX9-NEXT:    v_mul_lo_u32 v4, s3, v3
87; GFX9-NEXT:    v_not_b32_e32 v3, v3
88; GFX9-NEXT:    v_mul_lo_u32 v3, s2, v3
89; GFX9-NEXT:    v_add_u32_e32 v4, s4, v4
90; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v4
91; GFX9-NEXT:    v_add_u32_e32 v3, s4, v3
92; GFX9-NEXT:    s_add_u32 s4, s4, 1
93; GFX9-NEXT:    s_addc_u32 s5, s5, 0
94; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
95; GFX9-NEXT:    s_add_u32 s0, s0, 4
96; GFX9-NEXT:    s_addc_u32 s1, s1, 0
97; GFX9-NEXT:    v_subrev_u32_e32 v4, s2, v3
98; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
99; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
100; GFX9-NEXT:    s_cmpk_eq_i32 s4, 0x400
101; GFX9-NEXT:    global_store_dword v[1:2], v3, off
102; GFX9-NEXT:    s_cbranch_scc0 BB1_1
103; GFX9-NEXT:  ; %bb.2: ; %bb2
104; GFX9-NEXT:    s_endpgm
105bb:
106  br label %bb3
107
108bb2:                                              ; preds = %bb3
109  ret void
110
111bb3:                                              ; preds = %bb3, %bb
112  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
113  %tmp4 = urem i32 %tmp, %arg1
114  %tmp5 = zext i32 %tmp to i64
115  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
116  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
117  %tmp7 = add nuw nsw i32 %tmp, 1
118  %tmp8 = icmp eq i32 %tmp7, 1024
119  br i1 %tmp8, label %bb2, label %bb3
120}
121
122define amdgpu_kernel void @sdiv32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
123; GFX9-LABEL: sdiv32_invariant_denom:
124; GFX9:       ; %bb.0: ; %bb
125; GFX9-NEXT:    s_load_dword s3, s[0:1], 0x2c
126; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
127; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
128; GFX9-NEXT:    s_ashr_i32 s2, s3, 31
129; GFX9-NEXT:    s_add_i32 s3, s3, s2
130; GFX9-NEXT:    s_xor_b32 s3, s3, s2
131; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
132; GFX9-NEXT:    s_sub_i32 s4, 0, s3
133; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
134; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
135; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
136; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
137; GFX9-NEXT:    s_mov_b32 s4, 0
138; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
139; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
140; GFX9-NEXT:  BB2_1: ; %bb3
141; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
142; GFX9-NEXT:    v_mul_hi_u32 v3, s4, v0
143; GFX9-NEXT:    v_mov_b32_e32 v2, s1
144; GFX9-NEXT:    v_mov_b32_e32 v1, s0
145; GFX9-NEXT:    v_mul_lo_u32 v4, v3, s3
146; GFX9-NEXT:    v_add_u32_e32 v5, 1, v3
147; GFX9-NEXT:    v_sub_u32_e32 v4, s4, v4
148; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v4
149; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
150; GFX9-NEXT:    v_subrev_u32_e32 v5, s3, v4
151; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
152; GFX9-NEXT:    s_add_i32 s4, s4, 1
153; GFX9-NEXT:    v_add_u32_e32 v5, 1, v3
154; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v4
155; GFX9-NEXT:    s_add_u32 s0, s0, 4
156; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
157; GFX9-NEXT:    s_addc_u32 s1, s1, 0
158; GFX9-NEXT:    v_xor_b32_e32 v3, s2, v3
159; GFX9-NEXT:    s_cmpk_eq_i32 s4, 0x400
160; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v3
161; GFX9-NEXT:    global_store_dword v[1:2], v3, off
162; GFX9-NEXT:    s_cbranch_scc0 BB2_1
163; GFX9-NEXT:  ; %bb.2: ; %bb2
164; GFX9-NEXT:    s_endpgm
165bb:
166  br label %bb3
167
168bb2:                                              ; preds = %bb3
169  ret void
170
171bb3:                                              ; preds = %bb3, %bb
172  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
173  %tmp4 = sdiv i32 %tmp, %arg1
174  %tmp5 = zext i32 %tmp to i64
175  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
176  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
177  %tmp7 = add nuw nsw i32 %tmp, 1
178  %tmp8 = icmp eq i32 %tmp7, 1024
179  br i1 %tmp8, label %bb2, label %bb3
180}
181
182define amdgpu_kernel void @srem32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
183; GFX9-LABEL: srem32_invariant_denom:
184; GFX9:       ; %bb.0: ; %bb
185; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
186; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
187; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
188; GFX9-NEXT:    s_ashr_i32 s3, s2, 31
189; GFX9-NEXT:    s_add_i32 s2, s2, s3
190; GFX9-NEXT:    s_xor_b32 s2, s2, s3
191; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
192; GFX9-NEXT:    s_sub_i32 s3, 0, s2
193; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
194; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
195; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
196; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
197; GFX9-NEXT:    s_mov_b32 s3, 0
198; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
199; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
200; GFX9-NEXT:  BB3_1: ; %bb3
201; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
202; GFX9-NEXT:    v_mul_hi_u32 v3, s3, v0
203; GFX9-NEXT:    v_mov_b32_e32 v2, s1
204; GFX9-NEXT:    v_mov_b32_e32 v1, s0
205; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s2
206; GFX9-NEXT:    v_sub_u32_e32 v3, s3, v3
207; GFX9-NEXT:    s_add_i32 s3, s3, 1
208; GFX9-NEXT:    v_subrev_u32_e32 v4, s2, v3
209; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
210; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
211; GFX9-NEXT:    s_add_u32 s0, s0, 4
212; GFX9-NEXT:    s_addc_u32 s1, s1, 0
213; GFX9-NEXT:    v_subrev_u32_e32 v4, s2, v3
214; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
215; GFX9-NEXT:    s_cmpk_eq_i32 s3, 0x400
216; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
217; GFX9-NEXT:    global_store_dword v[1:2], v3, off
218; GFX9-NEXT:    s_cbranch_scc0 BB3_1
219; GFX9-NEXT:  ; %bb.2: ; %bb2
220; GFX9-NEXT:    s_endpgm
221bb:
222  br label %bb3
223
224bb2:                                              ; preds = %bb3
225  ret void
226
227bb3:                                              ; preds = %bb3, %bb
228  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
229  %tmp4 = srem i32 %tmp, %arg1
230  %tmp5 = zext i32 %tmp to i64
231  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
232  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
233  %tmp7 = add nuw nsw i32 %tmp, 1
234  %tmp8 = icmp eq i32 %tmp7, 1024
235  br i1 %tmp8, label %bb2, label %bb3
236}
237
238define amdgpu_kernel void @udiv16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
239; GFX9-LABEL: udiv16_invariant_denom:
240; GFX9:       ; %bb.0: ; %bb
241; GFX9-NEXT:    s_load_dword s3, s[0:1], 0x2c
242; GFX9-NEXT:    s_mov_b32 s2, 0xffff
243; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
244; GFX9-NEXT:    v_mov_b32_e32 v3, 0
245; GFX9-NEXT:    v_mov_b32_e32 v4, 0
246; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
247; GFX9-NEXT:    s_and_b32 s3, s2, s3
248; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
249; GFX9-NEXT:    s_movk_i32 s3, 0x400
250; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
251; GFX9-NEXT:  BB4_1: ; %bb3
252; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
253; GFX9-NEXT:    v_and_b32_e32 v2, s2, v4
254; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v2
255; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
256; GFX9-NEXT:    v_mov_b32_e32 v7, s5
257; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s4, v5
258; GFX9-NEXT:    v_mul_f32_e32 v2, v8, v1
259; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
260; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
261; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v2
262; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
263; GFX9-NEXT:    v_mad_f32 v2, -v2, v0, v8
264; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v2|, v0
265; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s3, v4
266; GFX9-NEXT:    v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1]
267; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
268; GFX9-NEXT:    global_store_short v[5:6], v2, off
269; GFX9-NEXT:    s_cbranch_vccz BB4_1
270; GFX9-NEXT:  ; %bb.2: ; %bb2
271; GFX9-NEXT:    s_endpgm
272bb:
273  br label %bb3
274
275bb2:                                              ; preds = %bb3
276  ret void
277
278bb3:                                              ; preds = %bb3, %bb
279  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
280  %tmp4 = udiv i16 %tmp, %arg1
281  %tmp5 = zext i16 %tmp to i64
282  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
283  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
284  %tmp7 = add nuw nsw i16 %tmp, 1
285  %tmp8 = icmp eq i16 %tmp7, 1024
286  br i1 %tmp8, label %bb2, label %bb3
287}
288
289define amdgpu_kernel void @urem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
290; GFX9-LABEL: urem16_invariant_denom:
291; GFX9:       ; %bb.0: ; %bb
292; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
293; GFX9-NEXT:    s_mov_b32 s4, 0xffff
294; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x24
295; GFX9-NEXT:    v_mov_b32_e32 v3, 0
296; GFX9-NEXT:    s_movk_i32 s8, 0x400
297; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
298; GFX9-NEXT:    s_and_b32 s5, s4, s2
299; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s5
300; GFX9-NEXT:    v_mov_b32_e32 v4, 0
301; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
302; GFX9-NEXT:  BB5_1: ; %bb3
303; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
304; GFX9-NEXT:    v_and_b32_e32 v2, s4, v4
305; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v2
306; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
307; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
308; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s8, v4
309; GFX9-NEXT:    v_mul_f32_e32 v9, v8, v1
310; GFX9-NEXT:    v_trunc_f32_e32 v9, v9
311; GFX9-NEXT:    v_cvt_u32_f32_e32 v10, v9
312; GFX9-NEXT:    v_mad_f32 v8, -v9, v0, v8
313; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v8|, v0
314; GFX9-NEXT:    v_mov_b32_e32 v7, s7
315; GFX9-NEXT:    v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3]
316; GFX9-NEXT:    v_mul_lo_u32 v8, v8, s5
317; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s6, v5
318; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
319; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
320; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v8
321; GFX9-NEXT:    global_store_short v[5:6], v2, off
322; GFX9-NEXT:    s_cbranch_vccz BB5_1
323; GFX9-NEXT:  ; %bb.2: ; %bb2
324; GFX9-NEXT:    s_endpgm
325bb:
326  br label %bb3
327
328bb2:                                              ; preds = %bb3
329  ret void
330
331bb3:                                              ; preds = %bb3, %bb
332  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
333  %tmp4 = urem i16 %tmp, %arg1
334  %tmp5 = zext i16 %tmp to i64
335  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
336  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
337  %tmp7 = add nuw nsw i16 %tmp, 1
338  %tmp8 = icmp eq i16 %tmp7, 1024
339  br i1 %tmp8, label %bb2, label %bb3
340}
341
342define amdgpu_kernel void @sdiv16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
343; GFX9-LABEL: sdiv16_invariant_denom:
344; GFX9:       ; %bb.0: ; %bb
345; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
346; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
347; GFX9-NEXT:    v_mov_b32_e32 v3, 0
348; GFX9-NEXT:    s_movk_i32 s3, 0x400
349; GFX9-NEXT:    v_mov_b32_e32 v4, 0
350; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
351; GFX9-NEXT:    s_sext_i32_i16 s2, s2
352; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s2
353; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
354; GFX9-NEXT:  BB6_1: ; %bb3
355; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
356; GFX9-NEXT:    v_bfe_i32 v5, v4, 0, 16
357; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v4
358; GFX9-NEXT:    v_cvt_f32_i32_e32 v9, v5
359; GFX9-NEXT:    v_xor_b32_e32 v8, s2, v5
360; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
361; GFX9-NEXT:    v_mov_b32_e32 v7, s5
362; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s4, v5
363; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
364; GFX9-NEXT:    v_mul_f32_e32 v7, v9, v1
365; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
366; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 30, v8
367; GFX9-NEXT:    v_cvt_i32_f32_e32 v8, v7
368; GFX9-NEXT:    v_mad_f32 v7, -v7, v0, v9
369; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
370; GFX9-NEXT:    v_or_b32_e32 v2, 1, v2
371; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v7|, |v0|
372; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s3, v4
373; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[0:1]
374; GFX9-NEXT:    v_add_u32_e32 v2, v8, v2
375; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
376; GFX9-NEXT:    global_store_short v[5:6], v2, off
377; GFX9-NEXT:    s_cbranch_vccz BB6_1
378; GFX9-NEXT:  ; %bb.2: ; %bb2
379; GFX9-NEXT:    s_endpgm
380bb:
381  br label %bb3
382
383bb2:                                              ; preds = %bb3
384  ret void
385
386bb3:                                              ; preds = %bb3, %bb
387  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
388  %tmp4 = sdiv i16 %tmp, %arg1
389  %tmp5 = zext i16 %tmp to i64
390  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
391  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
392  %tmp7 = add nuw nsw i16 %tmp, 1
393  %tmp8 = icmp eq i16 %tmp7, 1024
394  br i1 %tmp8, label %bb2, label %bb3
395}
396
397define amdgpu_kernel void @srem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
398; GFX9-LABEL: srem16_invariant_denom:
399; GFX9:       ; %bb.0: ; %bb
400; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
401; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x24
402; GFX9-NEXT:    v_mov_b32_e32 v3, 0
403; GFX9-NEXT:    s_movk_i32 s5, 0x400
404; GFX9-NEXT:    v_mov_b32_e32 v4, 0
405; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
406; GFX9-NEXT:    s_sext_i32_i16 s4, s2
407; GFX9-NEXT:    v_cvt_f32_i32_e32 v0, s4
408; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
409; GFX9-NEXT:  BB7_1: ; %bb3
410; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
411; GFX9-NEXT:    v_bfe_i32 v7, v4, 0, 16
412; GFX9-NEXT:    v_cvt_f32_i32_e32 v10, v7
413; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v4
414; GFX9-NEXT:    v_xor_b32_e32 v9, s4, v7
415; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
416; GFX9-NEXT:    v_ashrrev_i32_e32 v2, 30, v9
417; GFX9-NEXT:    v_mul_f32_e32 v9, v10, v1
418; GFX9-NEXT:    v_trunc_f32_e32 v9, v9
419; GFX9-NEXT:    v_cvt_i32_f32_e32 v11, v9
420; GFX9-NEXT:    v_mad_f32 v9, -v9, v0, v10
421; GFX9-NEXT:    v_or_b32_e32 v2, 1, v2
422; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v9|, |v0|
423; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, v2, s[2:3]
424; GFX9-NEXT:    v_add_u32_e32 v2, v11, v2
425; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s4
426; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
427; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s5, v4
428; GFX9-NEXT:    v_mov_b32_e32 v8, s7
429; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s6, v5
430; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
431; GFX9-NEXT:    v_sub_u32_e32 v2, v7, v2
432; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
433; GFX9-NEXT:    global_store_short v[5:6], v2, off
434; GFX9-NEXT:    s_cbranch_vccz BB7_1
435; GFX9-NEXT:  ; %bb.2: ; %bb2
436; GFX9-NEXT:    s_endpgm
437bb:
438  br label %bb3
439
440bb2:                                              ; preds = %bb3
441  ret void
442
443bb3:                                              ; preds = %bb3, %bb
444  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
445  %tmp4 = srem i16 %tmp, %arg1
446  %tmp5 = zext i16 %tmp to i64
447  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
448  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
449  %tmp7 = add nuw nsw i16 %tmp, 1
450  %tmp8 = icmp eq i16 %tmp7, 1024
451  br i1 %tmp8, label %bb2, label %bb3
452}
453