1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
3; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP,GFX8 %s
4; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
5; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,GFX10 %s
6
7; GCN-LABEL: {{^}}gws_sema_p_offset0:
8; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
9; NOLOOP: ds_gws_sema_p gds{{$}}
10
11; LOOP: s_mov_b32 m0, 0{{$}}
12; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]:
13; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
14; LOOP-NEXT: ds_gws_sema_p gds
15; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
17; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
18; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
19define amdgpu_kernel void @gws_sema_p_offset0(i32 %val) #0 {
20  call void @llvm.amdgcn.ds.gws.sema.p(i32 0)
21  ret void
22}
23
24declare void @llvm.amdgcn.ds.gws.sema.p(i32) #0
25
26attributes #0 = { convergent inaccessiblememonly nounwind }
27