1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=tahiti -amdgpu-dce-in-ra=0 -o - %s | FileCheck %s
3; Don't crash when the use of an undefined value is only detected by the
4; register coalescer because it is hidden with subregister insert/extract.
5target triple="amdgcn--"
6
7define amdgpu_kernel void @foobar(float %a0, float %a1, float addrspace(1)* %out) nounwind {
8; CHECK-LABEL: foobar:
9; CHECK:       ; %bb.0: ; %entry
10; CHECK-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
11; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
12; CHECK-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, -1, 0
13; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
14; CHECK-NEXT:    s_mov_b32 s2, -1
15; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
16; CHECK-NEXT:    v_mov_b32_e32 v0, s4
17; CHECK-NEXT:    v_mov_b32_e32 v1, s5
18; CHECK-NEXT:    v_mov_b32_e32 v2, s6
19; CHECK-NEXT:    v_mov_b32_e32 v3, s7
20; CHECK-NEXT:    s_and_saveexec_b64 s[6:7], vcc
21; CHECK-NEXT:  ; %bb.1: ; %ift
22; CHECK-NEXT:    s_mov_b32 s4, s5
23; CHECK-NEXT:    v_mov_b32_e32 v0, s4
24; CHECK-NEXT:    v_mov_b32_e32 v1, s5
25; CHECK-NEXT:    v_mov_b32_e32 v2, s6
26; CHECK-NEXT:    v_mov_b32_e32 v3, s7
27; CHECK-NEXT:  ; %bb.2: ; %ife
28; CHECK-NEXT:    s_or_b64 exec, exec, s[6:7]
29; CHECK-NEXT:    s_mov_b32 s3, 0xf000
30; CHECK-NEXT:    buffer_store_dword v1, off, s[0:3], 0
31; CHECK-NEXT:    s_endpgm
32
33; FIXME: The change related to the fact that
34; DetectDeadLanes pass hit "Copy across incompatible class" SGPR -> VGPR in analysis
35; and hence it cannot derive the fact that the vector element in the "ift" block is unused.
36; Such a copies appear because the float4 vectors and their elements in the test are uniform
37; but the PHI node in "ife" block is divergent because of the CF dependency (divergent branch in bb0)
38entry:
39  %v0 = insertelement <4 x float> undef, float %a0, i32 0
40  %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
41  %cnd = icmp eq i32 %tid, 0
42  br i1 %cnd, label %ift, label %ife
43
44ift:
45  %v1 = insertelement <4 x float> undef, float %a1, i32 0
46  br label %ife
47
48ife:
49  %val = phi <4 x float> [ %v1, %ift ], [ %v0, %entry ]
50  %v2 = extractelement <4 x float> %val, i32 1
51  store float %v2, float addrspace(1)* %out, align 4
52  ret void
53}
54
55declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
56
57attributes #0 = { nounwind readnone }
58