1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; Check the vctlz* instructions that were added in P8 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 4; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX 5 6declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>) nounwind readnone 7declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>) nounwind readnone 8declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>) nounwind readnone 9declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>) nounwind readnone 10 11define <16 x i8> @test_v16i8(<16 x i8> %x) nounwind readnone { 12; CHECK-LABEL: test_v16i8: 13; CHECK: # %bb.0: 14; CHECK-NEXT: vclzb 2, 2 15; CHECK-NEXT: blr 16; 17; CHECK-NOVSX-LABEL: test_v16i8: 18; CHECK-NOVSX: # %bb.0: 19; CHECK-NOVSX-NEXT: vclzb 2, 2 20; CHECK-NOVSX-NEXT: blr 21 %vcnt = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x) 22 ret <16 x i8> %vcnt 23} 24 25define <8 x i16> @test_v8i16(<8 x i16> %x) nounwind readnone { 26; CHECK-LABEL: test_v8i16: 27; CHECK: # %bb.0: 28; CHECK-NEXT: vclzh 2, 2 29; CHECK-NEXT: blr 30; 31; CHECK-NOVSX-LABEL: test_v8i16: 32; CHECK-NOVSX: # %bb.0: 33; CHECK-NOVSX-NEXT: vclzh 2, 2 34; CHECK-NOVSX-NEXT: blr 35 %vcnt = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %x) 36 ret <8 x i16> %vcnt 37} 38 39define <4 x i32> @test_v4i32(<4 x i32> %x) nounwind readnone { 40; CHECK-LABEL: test_v4i32: 41; CHECK: # %bb.0: 42; CHECK-NEXT: vclzw 2, 2 43; CHECK-NEXT: blr 44; 45; CHECK-NOVSX-LABEL: test_v4i32: 46; CHECK-NOVSX: # %bb.0: 47; CHECK-NOVSX-NEXT: vclzw 2, 2 48; CHECK-NOVSX-NEXT: blr 49 %vcnt = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x) 50 ret <4 x i32> %vcnt 51} 52 53define <2 x i64> @test_v2i64(<2 x i64> %x) nounwind readnone { 54; CHECK-LABEL: test_v2i64: 55; CHECK: # %bb.0: 56; CHECK-NEXT: vclzd 2, 2 57; CHECK-NEXT: blr 58; 59; CHECK-NOVSX-LABEL: test_v2i64: 60; CHECK-NOVSX: # %bb.0: 61; CHECK-NOVSX-NEXT: vclzd 2, 2 62; CHECK-NOVSX-NEXT: blr 63 %vcnt = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %x) 64 ret <2 x i64> %vcnt 65} 66 67declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1 immarg) 68 69define <2 x i32> @illegal_ctlz(<2 x i32> %v1) { 70; CHECK-LABEL: illegal_ctlz: 71; CHECK: # %bb.0: 72; CHECK-NEXT: vclzw 2, 2 73; CHECK-NEXT: blr 74; 75; CHECK-NOVSX-LABEL: illegal_ctlz: 76; CHECK-NOVSX: # %bb.0: 77; CHECK-NOVSX-NEXT: vclzw 2, 2 78; CHECK-NOVSX-NEXT: blr 79 %v2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %v1, i1 true) 80 ret <2 x i32> %v2 81} 82 83declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1 immarg) 84 85define <2 x i32> @illegal_cttz(<2 x i32> %v1) { 86; CHECK-LABEL: illegal_cttz: 87; CHECK: # %bb.0: 88; CHECK-NEXT: vspltisw 3, 1 89; CHECK-NEXT: vsubuwm 3, 2, 3 90; CHECK-NEXT: xxlandc 34, 35, 34 91; CHECK-NEXT: vpopcntw 2, 2 92; CHECK-NEXT: blr 93; 94; CHECK-NOVSX-LABEL: illegal_cttz: 95; CHECK-NOVSX: # %bb.0: 96; CHECK-NOVSX-NEXT: vspltisw 3, 1 97; CHECK-NOVSX-NEXT: vsubuwm 3, 2, 3 98; CHECK-NOVSX-NEXT: vandc 2, 3, 2 99; CHECK-NOVSX-NEXT: vpopcntw 2, 2 100; CHECK-NOVSX-NEXT: blr 101 %v2 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %v1, i1 true) 102 ret <2 x i32> %v2 103} 104