1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -slp-threshold=-6 -slp-vectorizer -instcombine -mattr=+sse2 -S | FileCheck %s --check-prefixes=CHECK,SSE 3; RUN: opt < %s -slp-threshold=-6 -slp-vectorizer -instcombine -mattr=+avx -S | FileCheck %s --check-prefixes=CHECK,AVX 4; RUN: opt < %s -slp-threshold=-6 -slp-vectorizer -instcombine -mattr=+avx2 -S | FileCheck %s --check-prefixes=CHECK,AVX 5 6target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 7target triple = "x86_64-unknown-linux-gnu" 8 9; These tests ensure that we do not regress due to PR31243. Note that we set 10; the SLP threshold to force vectorization even when not profitable. 11 12; When computing minimum sizes, if we can prove the sign bit is zero, we can 13; zero-extend the roots back to their original sizes. 14; 15define i8 @PR31243_zext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, i8* %ptr) { 16; CHECK-LABEL: @PR31243_zext( 17; CHECK-NEXT: entry: 18; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> undef, i8 [[V0:%.*]], i32 0 19; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[V1:%.*]], i32 1 20; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i8> [[TMP1]], <i8 1, i8 1> 21; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i8> [[TMP2]], i32 0 22; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 23; CHECK-NEXT: [[TMPE4:%.*]] = getelementptr inbounds i8, i8* [[PTR:%.*]], i64 [[TMP4]] 24; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i8> [[TMP2]], i32 1 25; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i64 26; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, i8* [[PTR]], i64 [[TMP6]] 27; CHECK-NEXT: [[TMP6:%.*]] = load i8, i8* [[TMPE4]], align 1 28; CHECK-NEXT: [[TMP7:%.*]] = load i8, i8* [[TMP5]], align 1 29; CHECK-NEXT: [[TMP8:%.*]] = add i8 [[TMP6]], [[TMP7]] 30; CHECK-NEXT: ret i8 [[TMP8]] 31; 32entry: 33 %tmp0 = zext i8 %v0 to i32 34 %tmp1 = zext i8 %v1 to i32 35 %tmp2 = or i32 %tmp0, 1 36 %tmp3 = or i32 %tmp1, 1 37 %tmp4 = getelementptr inbounds i8, i8* %ptr, i32 %tmp2 38 %tmp5 = getelementptr inbounds i8, i8* %ptr, i32 %tmp3 39 %tmp6 = load i8, i8* %tmp4 40 %tmp7 = load i8, i8* %tmp5 41 %tmp8 = add i8 %tmp6, %tmp7 42 ret i8 %tmp8 43} 44 45; When computing minimum sizes, if we cannot prove the sign bit is zero, we 46; have to include one extra bit for signedness since we will sign-extend the 47; roots. 48; 49; FIXME: This test is suboptimal since the compuation can be performed in i8. 50; In general, we need to add an extra bit to the maximum bit width only 51; if we can't prove that the upper bit of the original type is equal to 52; the upper bit of the proposed smaller type. If these two bits are the 53; same (either zero or one) we know that sign-extending from the smaller 54; type will result in the same value. Since we don't yet perform this 55; optimization, we make the proposed smaller type (i8) larger (i16) to 56; ensure correctness. 57; 58define i8 @PR31243_sext(i8 %v0, i8 %v1, i8 %v2, i8 %v3, i8* %ptr) { 59; SSE-LABEL: @PR31243_sext( 60; SSE-NEXT: entry: 61; SSE-NEXT: [[TMP0:%.*]] = or i8 [[V0:%.*]], 1 62; SSE-NEXT: [[TMP1:%.*]] = or i8 [[V1:%.*]], 1 63; SSE-NEXT: [[TMP2:%.*]] = sext i8 [[TMP0]] to i64 64; SSE-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, i8* [[PTR:%.*]], i64 [[TMP2]] 65; SSE-NEXT: [[TMP3:%.*]] = sext i8 [[TMP1]] to i64 66; SSE-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, i8* [[PTR]], i64 [[TMP3]] 67; SSE-NEXT: [[TMP6:%.*]] = load i8, i8* [[TMP4]], align 1 68; SSE-NEXT: [[TMP7:%.*]] = load i8, i8* [[TMP5]], align 1 69; SSE-NEXT: [[TMP8:%.*]] = add i8 [[TMP6]], [[TMP7]] 70; SSE-NEXT: ret i8 [[TMP8]] 71; 72; AVX-LABEL: @PR31243_sext( 73; AVX-NEXT: entry: 74; AVX-NEXT: [[TMP0:%.*]] = insertelement <2 x i8> undef, i8 [[V0:%.*]], i32 0 75; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> [[TMP0]], i8 [[V1:%.*]], i32 1 76; AVX-NEXT: [[TMP2:%.*]] = or <2 x i8> [[TMP1]], <i8 1, i8 1> 77; AVX-NEXT: [[TMP3:%.*]] = sext <2 x i8> [[TMP2]] to <2 x i16> 78; AVX-NEXT: [[TMP4:%.*]] = extractelement <2 x i16> [[TMP3]], i32 0 79; AVX-NEXT: [[TMP5:%.*]] = sext i16 [[TMP4]] to i64 80; AVX-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, i8* [[PTR:%.*]], i64 [[TMP5]] 81; AVX-NEXT: [[TMP6:%.*]] = extractelement <2 x i16> [[TMP3]], i32 1 82; AVX-NEXT: [[TMP7:%.*]] = sext i16 [[TMP6]] to i64 83; AVX-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, i8* [[PTR]], i64 [[TMP7]] 84; AVX-NEXT: [[TMP6:%.*]] = load i8, i8* [[TMP4]], align 1 85; AVX-NEXT: [[TMP7:%.*]] = load i8, i8* [[TMP5]], align 1 86; AVX-NEXT: [[TMP8:%.*]] = add i8 [[TMP6]], [[TMP7]] 87; AVX-NEXT: ret i8 [[TMP8]] 88; 89entry: 90 %tmp0 = sext i8 %v0 to i32 91 %tmp1 = sext i8 %v1 to i32 92 %tmp2 = or i32 %tmp0, 1 93 %tmp3 = or i32 %tmp1, 1 94 %tmp4 = getelementptr inbounds i8, i8* %ptr, i32 %tmp2 95 %tmp5 = getelementptr inbounds i8, i8* %ptr, i32 %tmp3 96 %tmp6 = load i8, i8* %tmp4 97 %tmp7 = load i8, i8* %tmp5 98 %tmp8 = add i8 %tmp6, %tmp7 99 ret i8 %tmp8 100} 101