1; relaxed encodings for FPU instructions, which NASM should support 2; ----------------------------------------------------------------- 3 4%define void 5%define reg_fpu0 st0 6%define reg_fpu st1 7 8; no operands instead of one operand: 9 10 ; F(U)COM(P), FCOM2, FCOMP3, FCOMP5 11 12 FCOM void 13 FCOMP void 14 FUCOM void 15 FUCOMP void 16; FCOM2 void 17; FCOMP3 void 18; FCOMP5 void 19 20 ; FLD, FST, FSTP, FSTP1, FSTP8, FSTP9 21 22 FLD void 23 FST void 24 FSTP void 25; FSTP1 void 26; FSTP8 void 27; FSTP9 void 28 29 ; FXCH, FXCH4, FXCH7, FFREE, FFREEP 30 31 FXCH void 32; FXCH4 void 33; FXCH7 void 34 FFREE void 35 FFREEP void 36 37; no operands instead of two operands: 38 39 ; FADD(P), FMUL(P), FSUBR(P), FSUB(P), FDIVR(P), FDIV(P) 40 41 FADD void 42 FADDP void 43 FMUL void 44 FMULP void 45 FSUBR void 46 FSUBRP void 47 FSUB void 48 FSUBP void 49 FDIVR void 50 FDIVRP void 51 FDIV void 52 FDIVP void 53 54; one operand instead of two operands: 55 56 ; FADD, FMUL, FSUB, FSUBR, FDIV, FDIVR 57 58 FADD reg_fpu 59 FMUL reg_fpu 60 FSUB reg_fpu 61 FSUBR reg_fpu 62 FDIV reg_fpu 63 FDIVR reg_fpu 64 65 ; FADD, FMUL, FSUBR, FSUB, FDIVR, FDIV (with TO qualifier) 66 67 FADD to reg_fpu 68 FMUL to reg_fpu 69 FSUBR to reg_fpu 70 FSUB to reg_fpu 71 FDIVR to reg_fpu 72 FDIV to reg_fpu 73 74 ; FADDP, FMULP, FSUBRP, FSUBP, FDIVRP, FDIVP 75 76 FADDP reg_fpu 77 FMULP reg_fpu 78 FSUBRP reg_fpu 79 FSUBP reg_fpu 80 FDIVRP reg_fpu 81 FDIVP reg_fpu 82 83 ; FCMOV(N)B, FCMOV(N)E, FCMOV(N)BE, FCMOV(N)U, and F(U)COMI(P) 84 85 FCMOVB reg_fpu 86 FCMOVNB reg_fpu 87 FCMOVE reg_fpu 88 FCMOVNE reg_fpu 89 FCMOVBE reg_fpu 90 FCMOVNBE reg_fpu 91 FCMOVU reg_fpu 92 FCMOVNU reg_fpu 93 FCOMI reg_fpu 94 FCOMIP reg_fpu 95 FUCOMI reg_fpu 96 FUCOMIP reg_fpu 97 98; two operands instead of one operand: 99 100 ; these don't really exist, and thus are _NOT_ supported: 101 102; FCOM reg_fpu,reg_fpu0 103; FCOM reg_fpu0,reg_fpu 104; FUCOM reg_fpu,reg_fpu0 105; FUCOM reg_fpu0,reg_fpu 106; FCOMP reg_fpu,reg_fpu0 107; FCOMP reg_fpu0,reg_fpu 108; FUCOMP reg_fpu,reg_fpu0 109; FUCOMP reg_fpu0,reg_fpu 110 111; FCOM2 reg_fpu,reg_fpu0 112; FCOM2 reg_fpu0,reg_fpu 113; FCOMP3 reg_fpu,reg_fpu0 114; FCOMP3 reg_fpu0,reg_fpu 115; FCOMP5 reg_fpu,reg_fpu0 116; FCOMP5 reg_fpu0,reg_fpu 117 118; FXCH reg_fpu,reg_fpu0 119; FXCH reg_fpu0,reg_fpu 120; FXCH4 reg_fpu,reg_fpu0 121; FXCH4 reg_fpu0,reg_fpu 122; FXCH7 reg_fpu,reg_fpu0 123; FXCH7 reg_fpu0,reg_fpu 124 125; EOF 126