1//=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12/// General Purpose Registers: W, X.
13def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
14
15/// Floating Point/Vector Registers: B, H, S, D, Q.
16def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
17
18/// Conditional register: NZCV.
19def CCRegBank : RegisterBank<"CC", [CCR]>;
20