1 /*
2  * Copyright 2016 Google Inc.
3  *
4  * Use of this source code is governed by a BSD-style license that can be
5  * found in the LICENSE file.
6  */
7 
8 #include "include/core/SkStream.h"
9 #include "include/core/SkString.h"
10 #include "include/private/SkOnce.h"
11 #include "src/core/SkCpu.h"
12 
13 #if defined(SK_CPU_X86)
14     #if defined(SK_BUILD_FOR_WIN) && !defined(__MINGW32__)
15         #include <intrin.h>
cpuid(uint32_t abcd[4])16         static void cpuid (uint32_t abcd[4]) { __cpuid  ((int*)abcd, 1);    }
cpuid7(uint32_t abcd[4])17         static void cpuid7(uint32_t abcd[4]) { __cpuidex((int*)abcd, 7, 0); }
xgetbv(uint32_t xcr)18         static uint64_t xgetbv(uint32_t xcr) { return _xgetbv(xcr); }
19     #else
20         #include <cpuid.h>
21         #if !defined(__cpuid_count)  // Old Mac Clang doesn't have this defined.
22             #define  __cpuid_count(eax, ecx, a, b, c, d) \
23                 __asm__("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "0"(eax), "2"(ecx))
24         #endif
cpuid(uint32_t abcd[4])25         static void cpuid (uint32_t abcd[4]) { __get_cpuid(1, abcd+0, abcd+1, abcd+2, abcd+3); }
cpuid7(uint32_t abcd[4])26         static void cpuid7(uint32_t abcd[4]) {
27             __cpuid_count(7, 0, abcd[0], abcd[1], abcd[2], abcd[3]);
28         }
xgetbv(uint32_t xcr)29         static uint64_t xgetbv(uint32_t xcr) {
30             uint32_t eax, edx;
31             __asm__ __volatile__ ( "xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
32             return (uint64_t)(edx) << 32 | eax;
33         }
34     #endif
35 
read_cpu_features()36     static uint32_t read_cpu_features() {
37         uint32_t features = 0;
38         uint32_t abcd[4] = {0,0,0,0};
39 
40         // You might want to refer to http://www.sandpile.org/x86/cpuid.htm
41 
42         cpuid(abcd);
43         if (abcd[3] & (1<<25)) { features |= SkCpu:: SSE1; }
44         if (abcd[3] & (1<<26)) { features |= SkCpu:: SSE2; }
45         if (abcd[2] & (1<< 0)) { features |= SkCpu:: SSE3; }
46         if (abcd[2] & (1<< 9)) { features |= SkCpu::SSSE3; }
47         if (abcd[2] & (1<<19)) { features |= SkCpu::SSE41; }
48         if (abcd[2] & (1<<20)) { features |= SkCpu::SSE42; }
49 
50         if ((abcd[2] & (3<<26)) == (3<<26)         // XSAVE + OSXSAVE
51              && (xgetbv(0) & (3<<1)) == (3<<1)) {  // XMM and YMM state enabled.
52             if (abcd[2] & (1<<28)) { features |= SkCpu:: AVX; }
53             if (abcd[2] & (1<<29)) { features |= SkCpu::F16C; }
54             if (abcd[2] & (1<<12)) { features |= SkCpu:: FMA; }
55 
56             cpuid7(abcd);
57             if (abcd[1] & (1<<5)) { features |= SkCpu::AVX2; }
58             if (abcd[1] & (1<<3)) { features |= SkCpu::BMI1; }
59             if (abcd[1] & (1<<8)) { features |= SkCpu::BMI2; }
60 
61             if ((xgetbv(0) & (7<<5)) == (7<<5)) {  // All ZMM state bits enabled too.
62                 if (abcd[1] & (1<<16)) { features |= SkCpu::AVX512F; }
63                 if (abcd[1] & (1<<17)) { features |= SkCpu::AVX512DQ; }
64                 if (abcd[1] & (1<<21)) { features |= SkCpu::AVX512IFMA; }
65                 if (abcd[1] & (1<<26)) { features |= SkCpu::AVX512PF; }
66                 if (abcd[1] & (1<<27)) { features |= SkCpu::AVX512ER; }
67                 if (abcd[1] & (1<<28)) { features |= SkCpu::AVX512CD; }
68                 if (abcd[1] & (1<<30)) { features |= SkCpu::AVX512BW; }
69                 if (abcd[1] & (1<<31)) { features |= SkCpu::AVX512VL; }
70             }
71         }
72         return features;
73     }
74 
75 #elif defined(SK_CPU_ARM64) && defined(__FreeBSD__)
76     #include <machine/armreg.h>
77     #ifndef ID_AA64ISAR0_CRC32_VAL
78     #define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
79     #endif
80 
read_cpu_features()81     static uint32_t read_cpu_features() {
82         uint32_t features = 0;
83         uint64_t id_aa64isar0;
84 
85         id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
86         if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) {
87             features |= SkCpu::CRC32;
88         }
89         return features;
90     }
91 
92 #elif defined(SK_CPU_ARM64) && __has_include(<sys/auxv.h>)
93     #include <sys/auxv.h>
94 
read_cpu_features()95     static uint32_t read_cpu_features() {
96         const uint32_t kHWCAP_CRC32   = (1<< 7),
97                        kHWCAP_ASIMDHP = (1<<10);
98 
99         uint32_t features = 0;
100         uint32_t hwcaps = getauxval(AT_HWCAP);
101         if (hwcaps & kHWCAP_CRC32  ) { features |= SkCpu::CRC32; }
102         if (hwcaps & kHWCAP_ASIMDHP) { features |= SkCpu::ASIMDHP; }
103 
104         // The Samsung Mongoose 3 core sets the ASIMDHP bit but doesn't support it.
105         for (int core = 0; features & SkCpu::ASIMDHP; core++) {
106             // These /sys files contain the core's MIDR_EL1 register, the source of
107             // CPU {implementer, variant, part, revision} you'd see in /proc/cpuinfo.
108             SkString path =
109                 SkStringPrintf("/sys/devices/system/cpu/cpu%d/regs/identification/midr_el1", core);
110 
111             // Can't use SkData::MakeFromFileName() here, I think because /sys can't be mmap()'d.
112             SkFILEStream midr_el1(path.c_str());
113             if (!midr_el1.isValid()) {
114                 // This is our ordinary exit path.
115                 // If we ask for MIDR_EL1 from a core that doesn't exist, we've checked all cores.
116                 if (core == 0) {
117                     // On the other hand, if we can't read MIDR_EL1 from any core, assume the worst.
118                     features &= ~(SkCpu::ASIMDHP);
119                 }
120                 break;
121             }
122 
123             const char kMongoose3[] = "0x00000000531f0020";  // 53 == Samsung.
124             char buf[SK_ARRAY_COUNT(kMongoose3) - 1];  // No need for the terminating \0.
125 
126             if (SK_ARRAY_COUNT(buf) != midr_el1.read(buf, SK_ARRAY_COUNT(buf))
127                           || 0 == memcmp(kMongoose3, buf, SK_ARRAY_COUNT(buf))) {
128                 features &= ~(SkCpu::ASIMDHP);
129             }
130         }
131         return features;
132     }
133 
134 #elif defined(SK_CPU_ARM32) && __has_include(<sys/auxv.h>) && \
135     (!defined(__ANDROID_API__) || __ANDROID_API__ >= 18)
136     // sys/auxv.h will always be present in the Android NDK due to unified
137     //headers, but getauxval is only defined for API >= 18.
138     #include <sys/auxv.h>
139 
read_cpu_features()140     static uint32_t read_cpu_features() {
141         const uint32_t kHWCAP_NEON  = (1<<12);
142         const uint32_t kHWCAP_VFPv4 = (1<<16);
143 
144         uint32_t features = 0;
145         uint32_t hwcaps = getauxval(AT_HWCAP);
146         if (hwcaps & kHWCAP_NEON ) {
147             features |= SkCpu::NEON;
148             if (hwcaps & kHWCAP_VFPv4) { features |= SkCpu::NEON_FMA|SkCpu::VFP_FP16; }
149         }
150         return features;
151     }
152 
153 #elif defined(SK_CPU_ARM32) && __has_include(<cpu-features.h>)
154     #include <cpu-features.h>
155 
read_cpu_features()156     static uint32_t read_cpu_features() {
157         uint32_t features = 0;
158         uint64_t cpu_features = android_getCpuFeatures();
159         if (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON)     { features |= SkCpu::NEON; }
160         if (cpu_features & ANDROID_CPU_ARM_FEATURE_NEON_FMA) { features |= SkCpu::NEON_FMA; }
161         if (cpu_features & ANDROID_CPU_ARM_FEATURE_VFP_FP16) { features |= SkCpu::VFP_FP16; }
162         return features;
163     }
164 
165 #else
read_cpu_features()166     static uint32_t read_cpu_features() {
167         return 0;
168     }
169 
170 #endif
171 
172 uint32_t SkCpu::gCachedFeatures = 0;
173 
CacheRuntimeFeatures()174 void SkCpu::CacheRuntimeFeatures() {
175     static SkOnce once;
176     once([] { gCachedFeatures = read_cpu_features(); });
177 }
178