1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
6 // met:
7 //
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
10 //
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution.
14 //
15 // - Neither the name of Sun Microsystems or the names of contributors may
16 // be used to endorse or promote products derived from this software without
17 // specific prior written permission.
18 //
19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
34
35 #include "src/codegen/mips64/assembler-mips64.h"
36
37 #if V8_TARGET_ARCH_MIPS64
38
39 #include "src/base/cpu.h"
40 #include "src/codegen/mips64/assembler-mips64-inl.h"
41 #include "src/codegen/safepoint-table.h"
42 #include "src/codegen/string-constants.h"
43 #include "src/deoptimizer/deoptimizer.h"
44 #include "src/objects/heap-number-inl.h"
45
46 namespace v8 {
47 namespace internal {
48
49 // Get the CPU features enabled by the build. For cross compilation the
50 // preprocessor symbols CAN_USE_FPU_INSTRUCTIONS
51 // can be defined to enable FPU instructions when building the
52 // snapshot.
CpuFeaturesImpliedByCompiler()53 static unsigned CpuFeaturesImpliedByCompiler() {
54 unsigned answer = 0;
55 #ifdef CAN_USE_FPU_INSTRUCTIONS
56 answer |= 1u << FPU;
57 #endif // def CAN_USE_FPU_INSTRUCTIONS
58
59 // If the compiler is allowed to use FPU then we can use FPU too in our code
60 // generation even when generating snapshots. This won't work for cross
61 // compilation.
62 #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0
63 answer |= 1u << FPU;
64 #endif
65
66 return answer;
67 }
68
ProbeImpl(bool cross_compile)69 void CpuFeatures::ProbeImpl(bool cross_compile) {
70 supported_ |= CpuFeaturesImpliedByCompiler();
71
72 // Only use statically determined features for cross compile (snapshot).
73 if (cross_compile) return;
74
75 // If the compiler is allowed to use fpu then we can use fpu too in our
76 // code generation.
77 #ifndef __mips__
78 // For the simulator build, use FPU.
79 supported_ |= 1u << FPU;
80 #if defined(_MIPS_ARCH_MIPS64R6) && defined(_MIPS_MSA)
81 supported_ |= 1u << MIPS_SIMD;
82 #endif
83 #else
84 // Probe for additional features at runtime.
85 base::CPU cpu;
86 if (cpu.has_fpu()) supported_ |= 1u << FPU;
87 #if defined(_MIPS_ARCH_MIPS64R6)
88 #if defined(_MIPS_MSA)
89 supported_ |= 1u << MIPS_SIMD;
90 #else
91 if (cpu.has_msa()) supported_ |= 1u << MIPS_SIMD;
92 #endif
93 #endif
94 #endif
95 }
96
PrintTarget()97 void CpuFeatures::PrintTarget() {}
PrintFeatures()98 void CpuFeatures::PrintFeatures() {}
99
ToNumber(Register reg)100 int ToNumber(Register reg) {
101 DCHECK(reg.is_valid());
102 const int kNumbers[] = {
103 0, // zero_reg
104 1, // at
105 2, // v0
106 3, // v1
107 4, // a0
108 5, // a1
109 6, // a2
110 7, // a3
111 8, // a4
112 9, // a5
113 10, // a6
114 11, // a7
115 12, // t0
116 13, // t1
117 14, // t2
118 15, // t3
119 16, // s0
120 17, // s1
121 18, // s2
122 19, // s3
123 20, // s4
124 21, // s5
125 22, // s6
126 23, // s7
127 24, // t8
128 25, // t9
129 26, // k0
130 27, // k1
131 28, // gp
132 29, // sp
133 30, // fp
134 31, // ra
135 };
136 return kNumbers[reg.code()];
137 }
138
ToRegister(int num)139 Register ToRegister(int num) {
140 DCHECK(num >= 0 && num < kNumRegisters);
141 const Register kRegisters[] = {
142 zero_reg, at, v0, v1, a0, a1, a2, a3, a4, a5, a6, a7, t0, t1, t2, t3,
143 s0, s1, s2, s3, s4, s5, s6, s7, t8, t9, k0, k1, gp, sp, fp, ra};
144 return kRegisters[num];
145 }
146
147 // -----------------------------------------------------------------------------
148 // Implementation of RelocInfo.
149
150 const int RelocInfo::kApplyMask =
151 RelocInfo::ModeMask(RelocInfo::INTERNAL_REFERENCE) |
152 RelocInfo::ModeMask(RelocInfo::INTERNAL_REFERENCE_ENCODED);
153
IsCodedSpecially()154 bool RelocInfo::IsCodedSpecially() {
155 // The deserializer needs to know whether a pointer is specially coded. Being
156 // specially coded on MIPS means that it is a lui/ori instruction, and that is
157 // always the case inside code objects.
158 return true;
159 }
160
IsInConstantPool()161 bool RelocInfo::IsInConstantPool() { return false; }
162
wasm_call_tag() const163 uint32_t RelocInfo::wasm_call_tag() const {
164 DCHECK(rmode_ == WASM_CALL || rmode_ == WASM_STUB_CALL);
165 return static_cast<uint32_t>(
166 Assembler::target_address_at(pc_, constant_pool_));
167 }
168
169 // -----------------------------------------------------------------------------
170 // Implementation of Operand and MemOperand.
171 // See assembler-mips-inl.h for inlined constructors.
172
Operand(Handle<HeapObject> handle)173 Operand::Operand(Handle<HeapObject> handle)
174 : rm_(no_reg), rmode_(RelocInfo::FULL_EMBEDDED_OBJECT) {
175 value_.immediate = static_cast<intptr_t>(handle.address());
176 }
177
EmbeddedNumber(double value)178 Operand Operand::EmbeddedNumber(double value) {
179 int32_t smi;
180 if (DoubleToSmiInteger(value, &smi)) return Operand(Smi::FromInt(smi));
181 Operand result(0, RelocInfo::FULL_EMBEDDED_OBJECT);
182 result.is_heap_object_request_ = true;
183 result.value_.heap_object_request = HeapObjectRequest(value);
184 return result;
185 }
186
EmbeddedStringConstant(const StringConstantBase * str)187 Operand Operand::EmbeddedStringConstant(const StringConstantBase* str) {
188 Operand result(0, RelocInfo::FULL_EMBEDDED_OBJECT);
189 result.is_heap_object_request_ = true;
190 result.value_.heap_object_request = HeapObjectRequest(str);
191 return result;
192 }
193
MemOperand(Register rm,int32_t offset)194 MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) {
195 offset_ = offset;
196 }
197
MemOperand(Register rm,int32_t unit,int32_t multiplier,OffsetAddend offset_addend)198 MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier,
199 OffsetAddend offset_addend)
200 : Operand(rm) {
201 offset_ = unit * multiplier + offset_addend;
202 }
203
AllocateAndInstallRequestedHeapObjects(Isolate * isolate)204 void Assembler::AllocateAndInstallRequestedHeapObjects(Isolate* isolate) {
205 DCHECK_IMPLIES(isolate == nullptr, heap_object_requests_.empty());
206 for (auto& request : heap_object_requests_) {
207 Handle<HeapObject> object;
208 switch (request.kind()) {
209 case HeapObjectRequest::kHeapNumber:
210 object = isolate->factory()->NewHeapNumber<AllocationType::kOld>(
211 request.heap_number());
212 break;
213 case HeapObjectRequest::kStringConstant:
214 const StringConstantBase* str = request.string();
215 CHECK_NOT_NULL(str);
216 object = str->AllocateStringConstant(isolate);
217 break;
218 }
219 Address pc = reinterpret_cast<Address>(buffer_start_) + request.offset();
220 set_target_value_at(pc, reinterpret_cast<uint64_t>(object.location()));
221 }
222 }
223
224 // -----------------------------------------------------------------------------
225 // Specific instructions, constants, and masks.
226
227 // daddiu(sp, sp, 8) aka Pop() operation or part of Pop(r)
228 // operations as post-increment of sp.
229 const Instr kPopInstruction = DADDIU | (sp.code() << kRsShift) |
230 (sp.code() << kRtShift) |
231 (kPointerSize & kImm16Mask); // NOLINT
232 // daddiu(sp, sp, -8) part of Push(r) operation as pre-decrement of sp.
233 const Instr kPushInstruction = DADDIU | (sp.code() << kRsShift) |
234 (sp.code() << kRtShift) |
235 (-kPointerSize & kImm16Mask); // NOLINT
236 // Sd(r, MemOperand(sp, 0))
237 const Instr kPushRegPattern =
238 SD | (sp.code() << kRsShift) | (0 & kImm16Mask); // NOLINT
239 // Ld(r, MemOperand(sp, 0))
240 const Instr kPopRegPattern =
241 LD | (sp.code() << kRsShift) | (0 & kImm16Mask); // NOLINT
242
243 const Instr kLwRegFpOffsetPattern =
244 LW | (fp.code() << kRsShift) | (0 & kImm16Mask); // NOLINT
245
246 const Instr kSwRegFpOffsetPattern =
247 SW | (fp.code() << kRsShift) | (0 & kImm16Mask); // NOLINT
248
249 const Instr kLwRegFpNegOffsetPattern =
250 LW | (fp.code() << kRsShift) | (kNegOffset & kImm16Mask); // NOLINT
251
252 const Instr kSwRegFpNegOffsetPattern =
253 SW | (fp.code() << kRsShift) | (kNegOffset & kImm16Mask); // NOLINT
254 // A mask for the Rt register for push, pop, lw, sw instructions.
255 const Instr kRtMask = kRtFieldMask;
256 const Instr kLwSwInstrTypeMask = 0xFFE00000;
257 const Instr kLwSwInstrArgumentMask = ~kLwSwInstrTypeMask;
258 const Instr kLwSwOffsetMask = kImm16Mask;
259
Assembler(const AssemblerOptions & options,std::unique_ptr<AssemblerBuffer> buffer)260 Assembler::Assembler(const AssemblerOptions& options,
261 std::unique_ptr<AssemblerBuffer> buffer)
262 : AssemblerBase(options, std::move(buffer)),
263 scratch_register_list_(at.bit()) {
264 reloc_info_writer.Reposition(buffer_start_ + buffer_->size(), pc_);
265
266 last_trampoline_pool_end_ = 0;
267 no_trampoline_pool_before_ = 0;
268 trampoline_pool_blocked_nesting_ = 0;
269 // We leave space (16 * kTrampolineSlotsSize)
270 // for BlockTrampolinePoolScope buffer.
271 next_buffer_check_ = FLAG_force_long_branches
272 ? kMaxInt
273 : kMaxBranchOffset - kTrampolineSlotsSize * 16;
274 internal_trampoline_exception_ = false;
275 last_bound_pos_ = 0;
276
277 trampoline_emitted_ = FLAG_force_long_branches;
278 unbound_labels_count_ = 0;
279 block_buffer_growth_ = false;
280 }
281
GetCode(Isolate * isolate,CodeDesc * desc,SafepointTableBuilder * safepoint_table_builder,int handler_table_offset)282 void Assembler::GetCode(Isolate* isolate, CodeDesc* desc,
283 SafepointTableBuilder* safepoint_table_builder,
284 int handler_table_offset) {
285 EmitForbiddenSlotInstruction();
286
287 int code_comments_size = WriteCodeComments();
288
289 DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
290
291 AllocateAndInstallRequestedHeapObjects(isolate);
292
293 // Set up code descriptor.
294 // TODO(jgruber): Reconsider how these offsets and sizes are maintained up to
295 // this point to make CodeDesc initialization less fiddly.
296
297 static constexpr int kConstantPoolSize = 0;
298 const int instruction_size = pc_offset();
299 const int code_comments_offset = instruction_size - code_comments_size;
300 const int constant_pool_offset = code_comments_offset - kConstantPoolSize;
301 const int handler_table_offset2 = (handler_table_offset == kNoHandlerTable)
302 ? constant_pool_offset
303 : handler_table_offset;
304 const int safepoint_table_offset =
305 (safepoint_table_builder == kNoSafepointTable)
306 ? handler_table_offset2
307 : safepoint_table_builder->GetCodeOffset();
308 const int reloc_info_offset =
309 static_cast<int>(reloc_info_writer.pos() - buffer_->start());
310 CodeDesc::Initialize(desc, this, safepoint_table_offset,
311 handler_table_offset2, constant_pool_offset,
312 code_comments_offset, reloc_info_offset);
313 }
314
Align(int m)315 void Assembler::Align(int m) {
316 DCHECK(m >= 4 && base::bits::IsPowerOfTwo(m));
317 EmitForbiddenSlotInstruction();
318 while ((pc_offset() & (m - 1)) != 0) {
319 nop();
320 }
321 }
322
CodeTargetAlign()323 void Assembler::CodeTargetAlign() {
324 // No advantage to aligning branch/call targets to more than
325 // single instruction, that I am aware of.
326 Align(4);
327 }
328
GetRtReg(Instr instr)329 Register Assembler::GetRtReg(Instr instr) {
330 return Register::from_code((instr & kRtFieldMask) >> kRtShift);
331 }
332
GetRsReg(Instr instr)333 Register Assembler::GetRsReg(Instr instr) {
334 return Register::from_code((instr & kRsFieldMask) >> kRsShift);
335 }
336
GetRdReg(Instr instr)337 Register Assembler::GetRdReg(Instr instr) {
338 return Register::from_code((instr & kRdFieldMask) >> kRdShift);
339 }
340
GetRt(Instr instr)341 uint32_t Assembler::GetRt(Instr instr) {
342 return (instr & kRtFieldMask) >> kRtShift;
343 }
344
GetRtField(Instr instr)345 uint32_t Assembler::GetRtField(Instr instr) { return instr & kRtFieldMask; }
346
GetRs(Instr instr)347 uint32_t Assembler::GetRs(Instr instr) {
348 return (instr & kRsFieldMask) >> kRsShift;
349 }
350
GetRsField(Instr instr)351 uint32_t Assembler::GetRsField(Instr instr) { return instr & kRsFieldMask; }
352
GetRd(Instr instr)353 uint32_t Assembler::GetRd(Instr instr) {
354 return (instr & kRdFieldMask) >> kRdShift;
355 }
356
GetRdField(Instr instr)357 uint32_t Assembler::GetRdField(Instr instr) { return instr & kRdFieldMask; }
358
GetSa(Instr instr)359 uint32_t Assembler::GetSa(Instr instr) {
360 return (instr & kSaFieldMask) >> kSaShift;
361 }
362
GetSaField(Instr instr)363 uint32_t Assembler::GetSaField(Instr instr) { return instr & kSaFieldMask; }
364
GetOpcodeField(Instr instr)365 uint32_t Assembler::GetOpcodeField(Instr instr) { return instr & kOpcodeMask; }
366
GetFunction(Instr instr)367 uint32_t Assembler::GetFunction(Instr instr) {
368 return (instr & kFunctionFieldMask) >> kFunctionShift;
369 }
370
GetFunctionField(Instr instr)371 uint32_t Assembler::GetFunctionField(Instr instr) {
372 return instr & kFunctionFieldMask;
373 }
374
GetImmediate16(Instr instr)375 uint32_t Assembler::GetImmediate16(Instr instr) { return instr & kImm16Mask; }
376
GetLabelConst(Instr instr)377 uint32_t Assembler::GetLabelConst(Instr instr) { return instr & ~kImm16Mask; }
378
IsPop(Instr instr)379 bool Assembler::IsPop(Instr instr) {
380 return (instr & ~kRtMask) == kPopRegPattern;
381 }
382
IsPush(Instr instr)383 bool Assembler::IsPush(Instr instr) {
384 return (instr & ~kRtMask) == kPushRegPattern;
385 }
386
IsSwRegFpOffset(Instr instr)387 bool Assembler::IsSwRegFpOffset(Instr instr) {
388 return ((instr & kLwSwInstrTypeMask) == kSwRegFpOffsetPattern);
389 }
390
IsLwRegFpOffset(Instr instr)391 bool Assembler::IsLwRegFpOffset(Instr instr) {
392 return ((instr & kLwSwInstrTypeMask) == kLwRegFpOffsetPattern);
393 }
394
IsSwRegFpNegOffset(Instr instr)395 bool Assembler::IsSwRegFpNegOffset(Instr instr) {
396 return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
397 kSwRegFpNegOffsetPattern);
398 }
399
IsLwRegFpNegOffset(Instr instr)400 bool Assembler::IsLwRegFpNegOffset(Instr instr) {
401 return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
402 kLwRegFpNegOffsetPattern);
403 }
404
405 // Labels refer to positions in the (to be) generated code.
406 // There are bound, linked, and unused labels.
407 //
408 // Bound labels refer to known positions in the already
409 // generated code. pos() is the position the label refers to.
410 //
411 // Linked labels refer to unknown positions in the code
412 // to be generated; pos() is the position of the last
413 // instruction using the label.
414
415 // The link chain is terminated by a value in the instruction of -1,
416 // which is an otherwise illegal value (branch -1 is inf loop).
417 // The instruction 16-bit offset field addresses 32-bit words, but in
418 // code is conv to an 18-bit value addressing bytes, hence the -4 value.
419
420 const int kEndOfChain = -4;
421 // Determines the end of the Jump chain (a subset of the label link chain).
422 const int kEndOfJumpChain = 0;
423
IsMsaBranch(Instr instr)424 bool Assembler::IsMsaBranch(Instr instr) {
425 uint32_t opcode = GetOpcodeField(instr);
426 uint32_t rs_field = GetRsField(instr);
427 if (opcode == COP1) {
428 switch (rs_field) {
429 case BZ_V:
430 case BZ_B:
431 case BZ_H:
432 case BZ_W:
433 case BZ_D:
434 case BNZ_V:
435 case BNZ_B:
436 case BNZ_H:
437 case BNZ_W:
438 case BNZ_D:
439 return true;
440 default:
441 return false;
442 }
443 } else {
444 return false;
445 }
446 }
447
IsBranch(Instr instr)448 bool Assembler::IsBranch(Instr instr) {
449 uint32_t opcode = GetOpcodeField(instr);
450 uint32_t rt_field = GetRtField(instr);
451 uint32_t rs_field = GetRsField(instr);
452 // Checks if the instruction is a branch.
453 bool isBranch =
454 opcode == BEQ || opcode == BNE || opcode == BLEZ || opcode == BGTZ ||
455 opcode == BEQL || opcode == BNEL || opcode == BLEZL || opcode == BGTZL ||
456 (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ ||
457 rt_field == BLTZAL || rt_field == BGEZAL)) ||
458 (opcode == COP1 && rs_field == BC1) || // Coprocessor branch.
459 (opcode == COP1 && rs_field == BC1EQZ) ||
460 (opcode == COP1 && rs_field == BC1NEZ) || IsMsaBranch(instr);
461 if (!isBranch && kArchVariant == kMips64r6) {
462 // All the 3 variants of POP10 (BOVC, BEQC, BEQZALC) and
463 // POP30 (BNVC, BNEC, BNEZALC) are branch ops.
464 isBranch |= opcode == POP10 || opcode == POP30 || opcode == BC ||
465 opcode == BALC ||
466 (opcode == POP66 && rs_field != 0) || // BEQZC
467 (opcode == POP76 && rs_field != 0); // BNEZC
468 }
469 return isBranch;
470 }
471
IsBc(Instr instr)472 bool Assembler::IsBc(Instr instr) {
473 uint32_t opcode = GetOpcodeField(instr);
474 // Checks if the instruction is a BC or BALC.
475 return opcode == BC || opcode == BALC;
476 }
477
IsNal(Instr instr)478 bool Assembler::IsNal(Instr instr) {
479 uint32_t opcode = GetOpcodeField(instr);
480 uint32_t rt_field = GetRtField(instr);
481 uint32_t rs_field = GetRsField(instr);
482 return opcode == REGIMM && rt_field == BLTZAL && rs_field == 0;
483 }
484
IsBzc(Instr instr)485 bool Assembler::IsBzc(Instr instr) {
486 uint32_t opcode = GetOpcodeField(instr);
487 // Checks if the instruction is BEQZC or BNEZC.
488 return (opcode == POP66 && GetRsField(instr) != 0) ||
489 (opcode == POP76 && GetRsField(instr) != 0);
490 }
491
IsEmittedConstant(Instr instr)492 bool Assembler::IsEmittedConstant(Instr instr) {
493 uint32_t label_constant = GetLabelConst(instr);
494 return label_constant == 0; // Emitted label const in reg-exp engine.
495 }
496
IsBeq(Instr instr)497 bool Assembler::IsBeq(Instr instr) { return GetOpcodeField(instr) == BEQ; }
498
IsBne(Instr instr)499 bool Assembler::IsBne(Instr instr) { return GetOpcodeField(instr) == BNE; }
500
IsBeqzc(Instr instr)501 bool Assembler::IsBeqzc(Instr instr) {
502 uint32_t opcode = GetOpcodeField(instr);
503 return opcode == POP66 && GetRsField(instr) != 0;
504 }
505
IsBnezc(Instr instr)506 bool Assembler::IsBnezc(Instr instr) {
507 uint32_t opcode = GetOpcodeField(instr);
508 return opcode == POP76 && GetRsField(instr) != 0;
509 }
510
IsBeqc(Instr instr)511 bool Assembler::IsBeqc(Instr instr) {
512 uint32_t opcode = GetOpcodeField(instr);
513 uint32_t rs = GetRsField(instr);
514 uint32_t rt = GetRtField(instr);
515 return opcode == POP10 && rs != 0 && rs < rt; // && rt != 0
516 }
517
IsBnec(Instr instr)518 bool Assembler::IsBnec(Instr instr) {
519 uint32_t opcode = GetOpcodeField(instr);
520 uint32_t rs = GetRsField(instr);
521 uint32_t rt = GetRtField(instr);
522 return opcode == POP30 && rs != 0 && rs < rt; // && rt != 0
523 }
524
IsMov(Instr instr,Register rd,Register rs)525 bool Assembler::IsMov(Instr instr, Register rd, Register rs) {
526 uint32_t opcode = GetOpcodeField(instr);
527 uint32_t rd_field = GetRd(instr);
528 uint32_t rs_field = GetRs(instr);
529 uint32_t rt_field = GetRt(instr);
530 uint32_t rd_reg = static_cast<uint32_t>(rd.code());
531 uint32_t rs_reg = static_cast<uint32_t>(rs.code());
532 uint32_t function_field = GetFunctionField(instr);
533 // Checks if the instruction is a OR with zero_reg argument (aka MOV).
534 bool res = opcode == SPECIAL && function_field == OR && rd_field == rd_reg &&
535 rs_field == rs_reg && rt_field == 0;
536 return res;
537 }
538
IsJump(Instr instr)539 bool Assembler::IsJump(Instr instr) {
540 uint32_t opcode = GetOpcodeField(instr);
541 uint32_t rt_field = GetRtField(instr);
542 uint32_t rd_field = GetRdField(instr);
543 uint32_t function_field = GetFunctionField(instr);
544 // Checks if the instruction is a jump.
545 return opcode == J || opcode == JAL ||
546 (opcode == SPECIAL && rt_field == 0 &&
547 ((function_field == JALR) ||
548 (rd_field == 0 && (function_field == JR))));
549 }
550
IsJ(Instr instr)551 bool Assembler::IsJ(Instr instr) {
552 uint32_t opcode = GetOpcodeField(instr);
553 // Checks if the instruction is a jump.
554 return opcode == J;
555 }
556
IsJal(Instr instr)557 bool Assembler::IsJal(Instr instr) { return GetOpcodeField(instr) == JAL; }
558
IsJr(Instr instr)559 bool Assembler::IsJr(Instr instr) {
560 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JR;
561 }
562
IsJalr(Instr instr)563 bool Assembler::IsJalr(Instr instr) {
564 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JALR;
565 }
566
IsLui(Instr instr)567 bool Assembler::IsLui(Instr instr) {
568 uint32_t opcode = GetOpcodeField(instr);
569 // Checks if the instruction is a load upper immediate.
570 return opcode == LUI;
571 }
572
IsOri(Instr instr)573 bool Assembler::IsOri(Instr instr) {
574 uint32_t opcode = GetOpcodeField(instr);
575 // Checks if the instruction is a load upper immediate.
576 return opcode == ORI;
577 }
578
IsNop(Instr instr,unsigned int type)579 bool Assembler::IsNop(Instr instr, unsigned int type) {
580 // See Assembler::nop(type).
581 DCHECK_LT(type, 32);
582 uint32_t opcode = GetOpcodeField(instr);
583 uint32_t function = GetFunctionField(instr);
584 uint32_t rt = GetRt(instr);
585 uint32_t rd = GetRd(instr);
586 uint32_t sa = GetSa(instr);
587
588 // Traditional mips nop == sll(zero_reg, zero_reg, 0)
589 // When marking non-zero type, use sll(zero_reg, at, type)
590 // to avoid use of mips ssnop and ehb special encodings
591 // of the sll instruction.
592
593 Register nop_rt_reg = (type == 0) ? zero_reg : at;
594 bool ret = (opcode == SPECIAL && function == SLL &&
595 rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
596 rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) && sa == type);
597
598 return ret;
599 }
600
GetBranchOffset(Instr instr)601 int32_t Assembler::GetBranchOffset(Instr instr) {
602 DCHECK(IsBranch(instr));
603 return (static_cast<int16_t>(instr & kImm16Mask)) << 2;
604 }
605
IsLw(Instr instr)606 bool Assembler::IsLw(Instr instr) {
607 return (static_cast<uint32_t>(instr & kOpcodeMask) == LW);
608 }
609
GetLwOffset(Instr instr)610 int16_t Assembler::GetLwOffset(Instr instr) {
611 DCHECK(IsLw(instr));
612 return ((instr & kImm16Mask));
613 }
614
SetLwOffset(Instr instr,int16_t offset)615 Instr Assembler::SetLwOffset(Instr instr, int16_t offset) {
616 DCHECK(IsLw(instr));
617
618 // We actually create a new lw instruction based on the original one.
619 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask) |
620 (offset & kImm16Mask);
621
622 return temp_instr;
623 }
624
IsSw(Instr instr)625 bool Assembler::IsSw(Instr instr) {
626 return (static_cast<uint32_t>(instr & kOpcodeMask) == SW);
627 }
628
SetSwOffset(Instr instr,int16_t offset)629 Instr Assembler::SetSwOffset(Instr instr, int16_t offset) {
630 DCHECK(IsSw(instr));
631 return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
632 }
633
IsAddImmediate(Instr instr)634 bool Assembler::IsAddImmediate(Instr instr) {
635 return ((instr & kOpcodeMask) == ADDIU || (instr & kOpcodeMask) == DADDIU);
636 }
637
SetAddImmediateOffset(Instr instr,int16_t offset)638 Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) {
639 DCHECK(IsAddImmediate(instr));
640 return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
641 }
642
IsAndImmediate(Instr instr)643 bool Assembler::IsAndImmediate(Instr instr) {
644 return GetOpcodeField(instr) == ANDI;
645 }
646
OffsetSizeInBits(Instr instr)647 static Assembler::OffsetSize OffsetSizeInBits(Instr instr) {
648 if (kArchVariant == kMips64r6) {
649 if (Assembler::IsBc(instr)) {
650 return Assembler::OffsetSize::kOffset26;
651 } else if (Assembler::IsBzc(instr)) {
652 return Assembler::OffsetSize::kOffset21;
653 }
654 }
655 return Assembler::OffsetSize::kOffset16;
656 }
657
AddBranchOffset(int pos,Instr instr)658 static inline int32_t AddBranchOffset(int pos, Instr instr) {
659 int bits = OffsetSizeInBits(instr);
660 const int32_t mask = (1 << bits) - 1;
661 bits = 32 - bits;
662
663 // Do NOT change this to <<2. We rely on arithmetic shifts here, assuming
664 // the compiler uses arithmetic shifts for signed integers.
665 int32_t imm = ((instr & mask) << bits) >> (bits - 2);
666
667 if (imm == kEndOfChain) {
668 // EndOfChain sentinel is returned directly, not relative to pc or pos.
669 return kEndOfChain;
670 } else {
671 return pos + Assembler::kBranchPCOffset + imm;
672 }
673 }
674
target_at(int pos,bool is_internal)675 int Assembler::target_at(int pos, bool is_internal) {
676 if (is_internal) {
677 int64_t* p = reinterpret_cast<int64_t*>(buffer_start_ + pos);
678 int64_t address = *p;
679 if (address == kEndOfJumpChain) {
680 return kEndOfChain;
681 } else {
682 int64_t instr_address = reinterpret_cast<int64_t>(p);
683 DCHECK(instr_address - address < INT_MAX);
684 int delta = static_cast<int>(instr_address - address);
685 DCHECK(pos > delta);
686 return pos - delta;
687 }
688 }
689 Instr instr = instr_at(pos);
690 if ((instr & ~kImm16Mask) == 0) {
691 // Emitted label constant, not part of a branch.
692 if (instr == 0) {
693 return kEndOfChain;
694 } else {
695 int32_t imm18 = ((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
696 return (imm18 + pos);
697 }
698 }
699 // Check we have a branch or jump instruction.
700 DCHECK(IsBranch(instr) || IsJ(instr) || IsJal(instr) || IsLui(instr) ||
701 IsMov(instr, t8, ra));
702 // Do NOT change this to <<2. We rely on arithmetic shifts here, assuming
703 // the compiler uses arithmetic shifts for signed integers.
704 if (IsBranch(instr)) {
705 return AddBranchOffset(pos, instr);
706 } else if (IsMov(instr, t8, ra)) {
707 int32_t imm32;
708 Instr instr_lui = instr_at(pos + 2 * kInstrSize);
709 Instr instr_ori = instr_at(pos + 3 * kInstrSize);
710 DCHECK(IsLui(instr_lui));
711 DCHECK(IsOri(instr_ori));
712 imm32 = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift;
713 imm32 |= (instr_ori & static_cast<int32_t>(kImm16Mask));
714 if (imm32 == kEndOfJumpChain) {
715 // EndOfChain sentinel is returned directly, not relative to pc or pos.
716 return kEndOfChain;
717 }
718 return pos + Assembler::kLongBranchPCOffset + imm32;
719 } else if (IsLui(instr)) {
720 if (IsNal(instr_at(pos + kInstrSize))) {
721 int32_t imm32;
722 Instr instr_lui = instr_at(pos + 0 * kInstrSize);
723 Instr instr_ori = instr_at(pos + 2 * kInstrSize);
724 DCHECK(IsLui(instr_lui));
725 DCHECK(IsOri(instr_ori));
726 imm32 = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift;
727 imm32 |= (instr_ori & static_cast<int32_t>(kImm16Mask));
728 if (imm32 == kEndOfJumpChain) {
729 // EndOfChain sentinel is returned directly, not relative to pc or pos.
730 return kEndOfChain;
731 }
732 return pos + Assembler::kLongBranchPCOffset + imm32;
733 } else {
734 Instr instr_lui = instr_at(pos + 0 * kInstrSize);
735 Instr instr_ori = instr_at(pos + 1 * kInstrSize);
736 Instr instr_ori2 = instr_at(pos + 3 * kInstrSize);
737 DCHECK(IsOri(instr_ori));
738 DCHECK(IsOri(instr_ori2));
739
740 // TODO(plind) create named constants for shift values.
741 int64_t imm = static_cast<int64_t>(instr_lui & kImm16Mask) << 48;
742 imm |= static_cast<int64_t>(instr_ori & kImm16Mask) << 32;
743 imm |= static_cast<int64_t>(instr_ori2 & kImm16Mask) << 16;
744 // Sign extend address;
745 imm >>= 16;
746
747 if (imm == kEndOfJumpChain) {
748 // EndOfChain sentinel is returned directly, not relative to pc or pos.
749 return kEndOfChain;
750 } else {
751 uint64_t instr_address = reinterpret_cast<int64_t>(buffer_start_ + pos);
752 DCHECK(instr_address - imm < INT_MAX);
753 int delta = static_cast<int>(instr_address - imm);
754 DCHECK(pos > delta);
755 return pos - delta;
756 }
757 }
758 } else {
759 DCHECK(IsJ(instr) || IsJal(instr));
760 int32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2;
761 if (imm28 == kEndOfJumpChain) {
762 // EndOfChain sentinel is returned directly, not relative to pc or pos.
763 return kEndOfChain;
764 } else {
765 // Sign extend 28-bit offset.
766 int32_t delta = static_cast<int32_t>((imm28 << 4) >> 4);
767 return pos + delta;
768 }
769 }
770 }
771
SetBranchOffset(int32_t pos,int32_t target_pos,Instr instr)772 static inline Instr SetBranchOffset(int32_t pos, int32_t target_pos,
773 Instr instr) {
774 int32_t bits = OffsetSizeInBits(instr);
775 int32_t imm = target_pos - (pos + Assembler::kBranchPCOffset);
776 DCHECK_EQ(imm & 3, 0);
777 imm >>= 2;
778
779 const int32_t mask = (1 << bits) - 1;
780 instr &= ~mask;
781 DCHECK(is_intn(imm, bits));
782
783 return instr | (imm & mask);
784 }
785
target_at_put(int pos,int target_pos,bool is_internal)786 void Assembler::target_at_put(int pos, int target_pos, bool is_internal) {
787 if (is_internal) {
788 uint64_t imm = reinterpret_cast<uint64_t>(buffer_start_) + target_pos;
789 *reinterpret_cast<uint64_t*>(buffer_start_ + pos) = imm;
790 return;
791 }
792 Instr instr = instr_at(pos);
793 if ((instr & ~kImm16Mask) == 0) {
794 DCHECK(target_pos == kEndOfChain || target_pos >= 0);
795 // Emitted label constant, not part of a branch.
796 // Make label relative to Code pointer of generated Code object.
797 instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));
798 return;
799 }
800
801 if (IsBranch(instr)) {
802 instr = SetBranchOffset(pos, target_pos, instr);
803 instr_at_put(pos, instr);
804 } else if (IsLui(instr)) {
805 if (IsNal(instr_at(pos + kInstrSize))) {
806 Instr instr_lui = instr_at(pos + 0 * kInstrSize);
807 Instr instr_ori = instr_at(pos + 2 * kInstrSize);
808 DCHECK(IsLui(instr_lui));
809 DCHECK(IsOri(instr_ori));
810 int32_t imm = target_pos - (pos + Assembler::kLongBranchPCOffset);
811 DCHECK_EQ(imm & 3, 0);
812 if (is_int16(imm + Assembler::kLongBranchPCOffset -
813 Assembler::kBranchPCOffset)) {
814 // Optimize by converting to regular branch and link with 16-bit
815 // offset.
816 Instr instr_b = REGIMM | BGEZAL; // Branch and link.
817 instr_b = SetBranchOffset(pos, target_pos, instr_b);
818 // Correct ra register to point to one instruction after jalr from
819 // TurboAssembler::BranchAndLinkLong.
820 Instr instr_a = DADDIU | ra.code() << kRsShift | ra.code() << kRtShift |
821 kOptimizedBranchAndLinkLongReturnOffset;
822
823 instr_at_put(pos, instr_b);
824 instr_at_put(pos + 1 * kInstrSize, instr_a);
825 } else {
826 instr_lui &= ~kImm16Mask;
827 instr_ori &= ~kImm16Mask;
828
829 instr_at_put(pos + 0 * kInstrSize,
830 instr_lui | ((imm >> kLuiShift) & kImm16Mask));
831 instr_at_put(pos + 2 * kInstrSize, instr_ori | (imm & kImm16Mask));
832 }
833 } else {
834 Instr instr_lui = instr_at(pos + 0 * kInstrSize);
835 Instr instr_ori = instr_at(pos + 1 * kInstrSize);
836 Instr instr_ori2 = instr_at(pos + 3 * kInstrSize);
837 DCHECK(IsOri(instr_ori));
838 DCHECK(IsOri(instr_ori2));
839
840 uint64_t imm = reinterpret_cast<uint64_t>(buffer_start_) + target_pos;
841 DCHECK_EQ(imm & 3, 0);
842
843 instr_lui &= ~kImm16Mask;
844 instr_ori &= ~kImm16Mask;
845 instr_ori2 &= ~kImm16Mask;
846
847 instr_at_put(pos + 0 * kInstrSize,
848 instr_lui | ((imm >> 32) & kImm16Mask));
849 instr_at_put(pos + 1 * kInstrSize,
850 instr_ori | ((imm >> 16) & kImm16Mask));
851 instr_at_put(pos + 3 * kInstrSize, instr_ori2 | (imm & kImm16Mask));
852 }
853 } else if (IsMov(instr, t8, ra)) {
854 Instr instr_lui = instr_at(pos + 2 * kInstrSize);
855 Instr instr_ori = instr_at(pos + 3 * kInstrSize);
856 DCHECK(IsLui(instr_lui));
857 DCHECK(IsOri(instr_ori));
858
859 int32_t imm_short = target_pos - (pos + Assembler::kBranchPCOffset);
860
861 if (is_int16(imm_short)) {
862 // Optimize by converting to regular branch with 16-bit
863 // offset
864 Instr instr_b = BEQ;
865 instr_b = SetBranchOffset(pos, target_pos, instr_b);
866
867 Instr instr_j = instr_at(pos + 5 * kInstrSize);
868 Instr instr_branch_delay;
869
870 if (IsJump(instr_j)) {
871 instr_branch_delay = instr_at(pos + 6 * kInstrSize);
872 } else {
873 instr_branch_delay = instr_at(pos + 7 * kInstrSize);
874 }
875 instr_at_put(pos, instr_b);
876 instr_at_put(pos + 1 * kInstrSize, instr_branch_delay);
877 } else {
878 int32_t imm = target_pos - (pos + Assembler::kLongBranchPCOffset);
879 DCHECK_EQ(imm & 3, 0);
880
881 instr_lui &= ~kImm16Mask;
882 instr_ori &= ~kImm16Mask;
883
884 instr_at_put(pos + 2 * kInstrSize,
885 instr_lui | ((imm >> kLuiShift) & kImm16Mask));
886 instr_at_put(pos + 3 * kInstrSize, instr_ori | (imm & kImm16Mask));
887 }
888 } else if (IsJ(instr) || IsJal(instr)) {
889 int32_t imm28 = target_pos - pos;
890 DCHECK_EQ(imm28 & 3, 0);
891
892 uint32_t imm26 = static_cast<uint32_t>(imm28 >> 2);
893 DCHECK(is_uint26(imm26));
894 // Place 26-bit signed offset with markings.
895 // When code is committed it will be resolved to j/jal.
896 int32_t mark = IsJ(instr) ? kJRawMark : kJalRawMark;
897 instr_at_put(pos, mark | (imm26 & kImm26Mask));
898 } else {
899 int32_t imm28 = target_pos - pos;
900 DCHECK_EQ(imm28 & 3, 0);
901
902 uint32_t imm26 = static_cast<uint32_t>(imm28 >> 2);
903 DCHECK(is_uint26(imm26));
904 // Place raw 26-bit signed offset.
905 // When code is committed it will be resolved to j/jal.
906 instr &= ~kImm26Mask;
907 instr_at_put(pos, instr | (imm26 & kImm26Mask));
908 }
909 }
910
print(const Label * L)911 void Assembler::print(const Label* L) {
912 if (L->is_unused()) {
913 PrintF("unused label\n");
914 } else if (L->is_bound()) {
915 PrintF("bound label to %d\n", L->pos());
916 } else if (L->is_linked()) {
917 Label l;
918 l.link_to(L->pos());
919 PrintF("unbound label");
920 while (l.is_linked()) {
921 PrintF("@ %d ", l.pos());
922 Instr instr = instr_at(l.pos());
923 if ((instr & ~kImm16Mask) == 0) {
924 PrintF("value\n");
925 } else {
926 PrintF("%d\n", instr);
927 }
928 next(&l, is_internal_reference(&l));
929 }
930 } else {
931 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
932 }
933 }
934
bind_to(Label * L,int pos)935 void Assembler::bind_to(Label* L, int pos) {
936 DCHECK(0 <= pos && pos <= pc_offset()); // Must have valid binding position.
937 int trampoline_pos = kInvalidSlotPos;
938 bool is_internal = false;
939 if (L->is_linked() && !trampoline_emitted_) {
940 unbound_labels_count_--;
941 if (!is_internal_reference(L)) {
942 next_buffer_check_ += kTrampolineSlotsSize;
943 }
944 }
945
946 while (L->is_linked()) {
947 int fixup_pos = L->pos();
948 int dist = pos - fixup_pos;
949 is_internal = is_internal_reference(L);
950 next(L, is_internal); // Call next before overwriting link with target at
951 // fixup_pos.
952 Instr instr = instr_at(fixup_pos);
953 if (is_internal) {
954 target_at_put(fixup_pos, pos, is_internal);
955 } else {
956 if (IsBranch(instr)) {
957 int branch_offset = BranchOffset(instr);
958 if (dist > branch_offset) {
959 if (trampoline_pos == kInvalidSlotPos) {
960 trampoline_pos = get_trampoline_entry(fixup_pos);
961 CHECK_NE(trampoline_pos, kInvalidSlotPos);
962 }
963 CHECK((trampoline_pos - fixup_pos) <= branch_offset);
964 target_at_put(fixup_pos, trampoline_pos, false);
965 fixup_pos = trampoline_pos;
966 }
967 target_at_put(fixup_pos, pos, false);
968 } else {
969 DCHECK(IsJ(instr) || IsJal(instr) || IsLui(instr) ||
970 IsEmittedConstant(instr) || IsMov(instr, t8, ra));
971 target_at_put(fixup_pos, pos, false);
972 }
973 }
974 }
975 L->bind_to(pos);
976
977 // Keep track of the last bound label so we don't eliminate any instructions
978 // before a bound label.
979 if (pos > last_bound_pos_) last_bound_pos_ = pos;
980 }
981
bind(Label * L)982 void Assembler::bind(Label* L) {
983 DCHECK(!L->is_bound()); // Label can only be bound once.
984 bind_to(L, pc_offset());
985 }
986
next(Label * L,bool is_internal)987 void Assembler::next(Label* L, bool is_internal) {
988 DCHECK(L->is_linked());
989 int link = target_at(L->pos(), is_internal);
990 if (link == kEndOfChain) {
991 L->Unuse();
992 } else {
993 DCHECK_GE(link, 0);
994 L->link_to(link);
995 }
996 }
997
is_near(Label * L)998 bool Assembler::is_near(Label* L) {
999 DCHECK(L->is_bound());
1000 return pc_offset() - L->pos() < kMaxBranchOffset - 4 * kInstrSize;
1001 }
1002
is_near(Label * L,OffsetSize bits)1003 bool Assembler::is_near(Label* L, OffsetSize bits) {
1004 if (L == nullptr || !L->is_bound()) return true;
1005 return ((pc_offset() - L->pos()) <
1006 (1 << (bits + 2 - 1)) - 1 - 5 * kInstrSize);
1007 }
1008
is_near_branch(Label * L)1009 bool Assembler::is_near_branch(Label* L) {
1010 DCHECK(L->is_bound());
1011 return kArchVariant == kMips64r6 ? is_near_r6(L) : is_near_pre_r6(L);
1012 }
1013
BranchOffset(Instr instr)1014 int Assembler::BranchOffset(Instr instr) {
1015 // At pre-R6 and for other R6 branches the offset is 16 bits.
1016 int bits = OffsetSize::kOffset16;
1017
1018 if (kArchVariant == kMips64r6) {
1019 uint32_t opcode = GetOpcodeField(instr);
1020 switch (opcode) {
1021 // Checks BC or BALC.
1022 case BC:
1023 case BALC:
1024 bits = OffsetSize::kOffset26;
1025 break;
1026
1027 // Checks BEQZC or BNEZC.
1028 case POP66:
1029 case POP76:
1030 if (GetRsField(instr) != 0) bits = OffsetSize::kOffset21;
1031 break;
1032 default:
1033 break;
1034 }
1035 }
1036
1037 return (1 << (bits + 2 - 1)) - 1;
1038 }
1039
1040 // We have to use a temporary register for things that can be relocated even
1041 // if they can be encoded in the MIPS's 16 bits of immediate-offset instruction
1042 // space. There is no guarantee that the relocated location can be similarly
1043 // encoded.
MustUseReg(RelocInfo::Mode rmode)1044 bool Assembler::MustUseReg(RelocInfo::Mode rmode) {
1045 return !RelocInfo::IsNone(rmode);
1046 }
1047
GenInstrRegister(Opcode opcode,Register rs,Register rt,Register rd,uint16_t sa,SecondaryField func)1048 void Assembler::GenInstrRegister(Opcode opcode, Register rs, Register rt,
1049 Register rd, uint16_t sa,
1050 SecondaryField func) {
1051 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
1052 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1053 (rd.code() << kRdShift) | (sa << kSaShift) | func;
1054 emit(instr);
1055 }
1056
GenInstrRegister(Opcode opcode,Register rs,Register rt,uint16_t msb,uint16_t lsb,SecondaryField func)1057 void Assembler::GenInstrRegister(Opcode opcode, Register rs, Register rt,
1058 uint16_t msb, uint16_t lsb,
1059 SecondaryField func) {
1060 DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb));
1061 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1062 (msb << kRdShift) | (lsb << kSaShift) | func;
1063 emit(instr);
1064 }
1065
GenInstrRegister(Opcode opcode,SecondaryField fmt,FPURegister ft,FPURegister fs,FPURegister fd,SecondaryField func)1066 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt,
1067 FPURegister ft, FPURegister fs, FPURegister fd,
1068 SecondaryField func) {
1069 DCHECK(fd.is_valid() && fs.is_valid() && ft.is_valid());
1070 Instr instr = opcode | fmt | (ft.code() << kFtShift) |
1071 (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
1072 emit(instr);
1073 }
1074
GenInstrRegister(Opcode opcode,FPURegister fr,FPURegister ft,FPURegister fs,FPURegister fd,SecondaryField func)1075 void Assembler::GenInstrRegister(Opcode opcode, FPURegister fr, FPURegister ft,
1076 FPURegister fs, FPURegister fd,
1077 SecondaryField func) {
1078 DCHECK(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid());
1079 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) |
1080 (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
1081 emit(instr);
1082 }
1083
GenInstrRegister(Opcode opcode,SecondaryField fmt,Register rt,FPURegister fs,FPURegister fd,SecondaryField func)1084 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt,
1085 FPURegister fs, FPURegister fd,
1086 SecondaryField func) {
1087 DCHECK(fd.is_valid() && fs.is_valid() && rt.is_valid());
1088 Instr instr = opcode | fmt | (rt.code() << kRtShift) |
1089 (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
1090 emit(instr);
1091 }
1092
GenInstrRegister(Opcode opcode,SecondaryField fmt,Register rt,FPUControlRegister fs,SecondaryField func)1093 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt,
1094 FPUControlRegister fs, SecondaryField func) {
1095 DCHECK(fs.is_valid() && rt.is_valid());
1096 Instr instr =
1097 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;
1098 emit(instr);
1099 }
1100
1101 // Instructions with immediate value.
1102 // Registers are in the order of the instruction encoding, from left to right.
GenInstrImmediate(Opcode opcode,Register rs,Register rt,int32_t j,CompactBranchType is_compact_branch)1103 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, Register rt,
1104 int32_t j,
1105 CompactBranchType is_compact_branch) {
1106 DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j)));
1107 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1108 (j & kImm16Mask);
1109 emit(instr, is_compact_branch);
1110 }
1111
GenInstrImmediate(Opcode opcode,Register base,Register rt,int32_t offset9,int bit6,SecondaryField func)1112 void Assembler::GenInstrImmediate(Opcode opcode, Register base, Register rt,
1113 int32_t offset9, int bit6,
1114 SecondaryField func) {
1115 DCHECK(base.is_valid() && rt.is_valid() && is_int9(offset9) &&
1116 is_uint1(bit6));
1117 Instr instr = opcode | (base.code() << kBaseShift) | (rt.code() << kRtShift) |
1118 ((offset9 << kImm9Shift) & kImm9Mask) | bit6 << kBit6Shift |
1119 func;
1120 emit(instr);
1121 }
1122
GenInstrImmediate(Opcode opcode,Register rs,SecondaryField SF,int32_t j,CompactBranchType is_compact_branch)1123 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF,
1124 int32_t j,
1125 CompactBranchType is_compact_branch) {
1126 DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j)));
1127 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
1128 emit(instr, is_compact_branch);
1129 }
1130
GenInstrImmediate(Opcode opcode,Register rs,FPURegister ft,int32_t j,CompactBranchType is_compact_branch)1131 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft,
1132 int32_t j,
1133 CompactBranchType is_compact_branch) {
1134 DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j)));
1135 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) |
1136 (j & kImm16Mask);
1137 emit(instr, is_compact_branch);
1138 }
1139
GenInstrImmediate(Opcode opcode,Register rs,int32_t offset21,CompactBranchType is_compact_branch)1140 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, int32_t offset21,
1141 CompactBranchType is_compact_branch) {
1142 DCHECK(rs.is_valid() && (is_int21(offset21)));
1143 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1144 emit(instr, is_compact_branch);
1145 }
1146
GenInstrImmediate(Opcode opcode,Register rs,uint32_t offset21)1147 void Assembler::GenInstrImmediate(Opcode opcode, Register rs,
1148 uint32_t offset21) {
1149 DCHECK(rs.is_valid() && (is_uint21(offset21)));
1150 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1151 emit(instr);
1152 }
1153
GenInstrImmediate(Opcode opcode,int32_t offset26,CompactBranchType is_compact_branch)1154 void Assembler::GenInstrImmediate(Opcode opcode, int32_t offset26,
1155 CompactBranchType is_compact_branch) {
1156 DCHECK(is_int26(offset26));
1157 Instr instr = opcode | (offset26 & kImm26Mask);
1158 emit(instr, is_compact_branch);
1159 }
1160
GenInstrJump(Opcode opcode,uint32_t address)1161 void Assembler::GenInstrJump(Opcode opcode, uint32_t address) {
1162 BlockTrampolinePoolScope block_trampoline_pool(this);
1163 DCHECK(is_uint26(address));
1164 Instr instr = opcode | address;
1165 emit(instr);
1166 BlockTrampolinePoolFor(1); // For associated delay slot.
1167 }
1168
1169 // MSA instructions
GenInstrMsaI8(SecondaryField operation,uint32_t imm8,MSARegister ws,MSARegister wd)1170 void Assembler::GenInstrMsaI8(SecondaryField operation, uint32_t imm8,
1171 MSARegister ws, MSARegister wd) {
1172 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1173 DCHECK(ws.is_valid() && wd.is_valid() && is_uint8(imm8));
1174 Instr instr = MSA | operation | ((imm8 & kImm8Mask) << kWtShift) |
1175 (ws.code() << kWsShift) | (wd.code() << kWdShift);
1176 emit(instr);
1177 }
1178
GenInstrMsaI5(SecondaryField operation,SecondaryField df,int32_t imm5,MSARegister ws,MSARegister wd)1179 void Assembler::GenInstrMsaI5(SecondaryField operation, SecondaryField df,
1180 int32_t imm5, MSARegister ws, MSARegister wd) {
1181 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1182 DCHECK(ws.is_valid() && wd.is_valid());
1183 DCHECK((operation == MAXI_S) || (operation == MINI_S) ||
1184 (operation == CEQI) || (operation == CLTI_S) ||
1185 (operation == CLEI_S)
1186 ? is_int5(imm5)
1187 : is_uint5(imm5));
1188 Instr instr = MSA | operation | df | ((imm5 & kImm5Mask) << kWtShift) |
1189 (ws.code() << kWsShift) | (wd.code() << kWdShift);
1190 emit(instr);
1191 }
1192
GenInstrMsaBit(SecondaryField operation,SecondaryField df,uint32_t m,MSARegister ws,MSARegister wd)1193 void Assembler::GenInstrMsaBit(SecondaryField operation, SecondaryField df,
1194 uint32_t m, MSARegister ws, MSARegister wd) {
1195 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1196 DCHECK(ws.is_valid() && wd.is_valid() && is_valid_msa_df_m(df, m));
1197 Instr instr = MSA | operation | df | (m << kWtShift) |
1198 (ws.code() << kWsShift) | (wd.code() << kWdShift);
1199 emit(instr);
1200 }
1201
GenInstrMsaI10(SecondaryField operation,SecondaryField df,int32_t imm10,MSARegister wd)1202 void Assembler::GenInstrMsaI10(SecondaryField operation, SecondaryField df,
1203 int32_t imm10, MSARegister wd) {
1204 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1205 DCHECK(wd.is_valid() && is_int10(imm10));
1206 Instr instr = MSA | operation | df | ((imm10 & kImm10Mask) << kWsShift) |
1207 (wd.code() << kWdShift);
1208 emit(instr);
1209 }
1210
1211 template <typename RegType>
GenInstrMsa3R(SecondaryField operation,SecondaryField df,RegType t,MSARegister ws,MSARegister wd)1212 void Assembler::GenInstrMsa3R(SecondaryField operation, SecondaryField df,
1213 RegType t, MSARegister ws, MSARegister wd) {
1214 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1215 DCHECK(t.is_valid() && ws.is_valid() && wd.is_valid());
1216 Instr instr = MSA | operation | df | (t.code() << kWtShift) |
1217 (ws.code() << kWsShift) | (wd.code() << kWdShift);
1218 emit(instr);
1219 }
1220
1221 template <typename DstType, typename SrcType>
GenInstrMsaElm(SecondaryField operation,SecondaryField df,uint32_t n,SrcType src,DstType dst)1222 void Assembler::GenInstrMsaElm(SecondaryField operation, SecondaryField df,
1223 uint32_t n, SrcType src, DstType dst) {
1224 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1225 DCHECK(src.is_valid() && dst.is_valid() && is_valid_msa_df_n(df, n));
1226 Instr instr = MSA | operation | df | (n << kWtShift) |
1227 (src.code() << kWsShift) | (dst.code() << kWdShift) |
1228 MSA_ELM_MINOR;
1229 emit(instr);
1230 }
1231
GenInstrMsa3RF(SecondaryField operation,uint32_t df,MSARegister wt,MSARegister ws,MSARegister wd)1232 void Assembler::GenInstrMsa3RF(SecondaryField operation, uint32_t df,
1233 MSARegister wt, MSARegister ws, MSARegister wd) {
1234 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1235 DCHECK(wt.is_valid() && ws.is_valid() && wd.is_valid());
1236 DCHECK_LT(df, 2);
1237 Instr instr = MSA | operation | (df << 21) | (wt.code() << kWtShift) |
1238 (ws.code() << kWsShift) | (wd.code() << kWdShift);
1239 emit(instr);
1240 }
1241
GenInstrMsaVec(SecondaryField operation,MSARegister wt,MSARegister ws,MSARegister wd)1242 void Assembler::GenInstrMsaVec(SecondaryField operation, MSARegister wt,
1243 MSARegister ws, MSARegister wd) {
1244 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1245 DCHECK(wt.is_valid() && ws.is_valid() && wd.is_valid());
1246 Instr instr = MSA | operation | (wt.code() << kWtShift) |
1247 (ws.code() << kWsShift) | (wd.code() << kWdShift) |
1248 MSA_VEC_2R_2RF_MINOR;
1249 emit(instr);
1250 }
1251
GenInstrMsaMI10(SecondaryField operation,int32_t s10,Register rs,MSARegister wd)1252 void Assembler::GenInstrMsaMI10(SecondaryField operation, int32_t s10,
1253 Register rs, MSARegister wd) {
1254 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1255 DCHECK(rs.is_valid() && wd.is_valid() && is_int10(s10));
1256 Instr instr = MSA | operation | ((s10 & kImm10Mask) << kWtShift) |
1257 (rs.code() << kWsShift) | (wd.code() << kWdShift);
1258 emit(instr);
1259 }
1260
GenInstrMsa2R(SecondaryField operation,SecondaryField df,MSARegister ws,MSARegister wd)1261 void Assembler::GenInstrMsa2R(SecondaryField operation, SecondaryField df,
1262 MSARegister ws, MSARegister wd) {
1263 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1264 DCHECK(ws.is_valid() && wd.is_valid());
1265 Instr instr = MSA | MSA_2R_FORMAT | operation | df | (ws.code() << kWsShift) |
1266 (wd.code() << kWdShift) | MSA_VEC_2R_2RF_MINOR;
1267 emit(instr);
1268 }
1269
GenInstrMsa2RF(SecondaryField operation,SecondaryField df,MSARegister ws,MSARegister wd)1270 void Assembler::GenInstrMsa2RF(SecondaryField operation, SecondaryField df,
1271 MSARegister ws, MSARegister wd) {
1272 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1273 DCHECK(ws.is_valid() && wd.is_valid());
1274 Instr instr = MSA | MSA_2RF_FORMAT | operation | df |
1275 (ws.code() << kWsShift) | (wd.code() << kWdShift) |
1276 MSA_VEC_2R_2RF_MINOR;
1277 emit(instr);
1278 }
1279
GenInstrMsaBranch(SecondaryField operation,MSARegister wt,int32_t offset16)1280 void Assembler::GenInstrMsaBranch(SecondaryField operation, MSARegister wt,
1281 int32_t offset16) {
1282 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
1283 DCHECK(wt.is_valid() && is_int16(offset16));
1284 BlockTrampolinePoolScope block_trampoline_pool(this);
1285 Instr instr =
1286 COP1 | operation | (wt.code() << kWtShift) | (offset16 & kImm16Mask);
1287 emit(instr);
1288 BlockTrampolinePoolFor(1); // For associated delay slot.
1289 }
1290
1291 // Returns the next free trampoline entry.
get_trampoline_entry(int32_t pos)1292 int32_t Assembler::get_trampoline_entry(int32_t pos) {
1293 int32_t trampoline_entry = kInvalidSlotPos;
1294 if (!internal_trampoline_exception_) {
1295 if (trampoline_.start() > pos) {
1296 trampoline_entry = trampoline_.take_slot();
1297 }
1298
1299 if (kInvalidSlotPos == trampoline_entry) {
1300 internal_trampoline_exception_ = true;
1301 }
1302 }
1303 return trampoline_entry;
1304 }
1305
jump_address(Label * L)1306 uint64_t Assembler::jump_address(Label* L) {
1307 int64_t target_pos;
1308 if (L->is_bound()) {
1309 target_pos = L->pos();
1310 } else {
1311 if (L->is_linked()) {
1312 target_pos = L->pos(); // L's link.
1313 L->link_to(pc_offset());
1314 } else {
1315 L->link_to(pc_offset());
1316 return kEndOfJumpChain;
1317 }
1318 }
1319 uint64_t imm = reinterpret_cast<uint64_t>(buffer_start_) + target_pos;
1320 DCHECK_EQ(imm & 3, 0);
1321
1322 return imm;
1323 }
1324
jump_offset(Label * L)1325 uint64_t Assembler::jump_offset(Label* L) {
1326 int64_t target_pos;
1327 int32_t pad = IsPrevInstrCompactBranch() ? kInstrSize : 0;
1328
1329 if (L->is_bound()) {
1330 target_pos = L->pos();
1331 } else {
1332 if (L->is_linked()) {
1333 target_pos = L->pos(); // L's link.
1334 L->link_to(pc_offset() + pad);
1335 } else {
1336 L->link_to(pc_offset() + pad);
1337 return kEndOfJumpChain;
1338 }
1339 }
1340 int64_t imm = target_pos - (pc_offset() + pad);
1341 DCHECK_EQ(imm & 3, 0);
1342
1343 return static_cast<uint64_t>(imm);
1344 }
1345
branch_long_offset(Label * L)1346 uint64_t Assembler::branch_long_offset(Label* L) {
1347 int64_t target_pos;
1348
1349 if (L->is_bound()) {
1350 target_pos = L->pos();
1351 } else {
1352 if (L->is_linked()) {
1353 target_pos = L->pos(); // L's link.
1354 L->link_to(pc_offset());
1355 } else {
1356 L->link_to(pc_offset());
1357 return kEndOfJumpChain;
1358 }
1359 }
1360 int64_t offset = target_pos - (pc_offset() + kLongBranchPCOffset);
1361 DCHECK_EQ(offset & 3, 0);
1362
1363 return static_cast<uint64_t>(offset);
1364 }
1365
branch_offset_helper(Label * L,OffsetSize bits)1366 int32_t Assembler::branch_offset_helper(Label* L, OffsetSize bits) {
1367 int32_t target_pos;
1368 int32_t pad = IsPrevInstrCompactBranch() ? kInstrSize : 0;
1369
1370 if (L->is_bound()) {
1371 target_pos = L->pos();
1372 } else {
1373 if (L->is_linked()) {
1374 target_pos = L->pos();
1375 L->link_to(pc_offset() + pad);
1376 } else {
1377 L->link_to(pc_offset() + pad);
1378 if (!trampoline_emitted_) {
1379 unbound_labels_count_++;
1380 next_buffer_check_ -= kTrampolineSlotsSize;
1381 }
1382 return kEndOfChain;
1383 }
1384 }
1385
1386 int32_t offset = target_pos - (pc_offset() + kBranchPCOffset + pad);
1387 DCHECK(is_intn(offset, bits + 2));
1388 DCHECK_EQ(offset & 3, 0);
1389
1390 return offset;
1391 }
1392
label_at_put(Label * L,int at_offset)1393 void Assembler::label_at_put(Label* L, int at_offset) {
1394 int target_pos;
1395 if (L->is_bound()) {
1396 target_pos = L->pos();
1397 instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag));
1398 } else {
1399 if (L->is_linked()) {
1400 target_pos = L->pos(); // L's link.
1401 int32_t imm18 = target_pos - at_offset;
1402 DCHECK_EQ(imm18 & 3, 0);
1403 int32_t imm16 = imm18 >> 2;
1404 DCHECK(is_int16(imm16));
1405 instr_at_put(at_offset, (imm16 & kImm16Mask));
1406 } else {
1407 target_pos = kEndOfChain;
1408 instr_at_put(at_offset, 0);
1409 if (!trampoline_emitted_) {
1410 unbound_labels_count_++;
1411 next_buffer_check_ -= kTrampolineSlotsSize;
1412 }
1413 }
1414 L->link_to(at_offset);
1415 }
1416 }
1417
1418 //------- Branch and jump instructions --------
1419
b(int16_t offset)1420 void Assembler::b(int16_t offset) { beq(zero_reg, zero_reg, offset); }
1421
bal(int16_t offset)1422 void Assembler::bal(int16_t offset) { bgezal(zero_reg, offset); }
1423
bc(int32_t offset)1424 void Assembler::bc(int32_t offset) {
1425 DCHECK_EQ(kArchVariant, kMips64r6);
1426 GenInstrImmediate(BC, offset, CompactBranchType::COMPACT_BRANCH);
1427 }
1428
balc(int32_t offset)1429 void Assembler::balc(int32_t offset) {
1430 DCHECK_EQ(kArchVariant, kMips64r6);
1431 GenInstrImmediate(BALC, offset, CompactBranchType::COMPACT_BRANCH);
1432 }
1433
beq(Register rs,Register rt,int16_t offset)1434 void Assembler::beq(Register rs, Register rt, int16_t offset) {
1435 BlockTrampolinePoolScope block_trampoline_pool(this);
1436 GenInstrImmediate(BEQ, rs, rt, offset);
1437 BlockTrampolinePoolFor(1); // For associated delay slot.
1438 }
1439
bgez(Register rs,int16_t offset)1440 void Assembler::bgez(Register rs, int16_t offset) {
1441 BlockTrampolinePoolScope block_trampoline_pool(this);
1442 GenInstrImmediate(REGIMM, rs, BGEZ, offset);
1443 BlockTrampolinePoolFor(1); // For associated delay slot.
1444 }
1445
bgezc(Register rt,int16_t offset)1446 void Assembler::bgezc(Register rt, int16_t offset) {
1447 DCHECK_EQ(kArchVariant, kMips64r6);
1448 DCHECK(rt != zero_reg);
1449 GenInstrImmediate(BLEZL, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
1450 }
1451
bgeuc(Register rs,Register rt,int16_t offset)1452 void Assembler::bgeuc(Register rs, Register rt, int16_t offset) {
1453 DCHECK_EQ(kArchVariant, kMips64r6);
1454 DCHECK(rs != zero_reg);
1455 DCHECK(rt != zero_reg);
1456 DCHECK(rs.code() != rt.code());
1457 GenInstrImmediate(BLEZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1458 }
1459
bgec(Register rs,Register rt,int16_t offset)1460 void Assembler::bgec(Register rs, Register rt, int16_t offset) {
1461 DCHECK_EQ(kArchVariant, kMips64r6);
1462 DCHECK(rs != zero_reg);
1463 DCHECK(rt != zero_reg);
1464 DCHECK(rs.code() != rt.code());
1465 GenInstrImmediate(BLEZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1466 }
1467
bgezal(Register rs,int16_t offset)1468 void Assembler::bgezal(Register rs, int16_t offset) {
1469 DCHECK(kArchVariant != kMips64r6 || rs == zero_reg);
1470 DCHECK(rs != ra);
1471 BlockTrampolinePoolScope block_trampoline_pool(this);
1472 GenInstrImmediate(REGIMM, rs, BGEZAL, offset);
1473 BlockTrampolinePoolFor(1); // For associated delay slot.
1474 }
1475
bgtz(Register rs,int16_t offset)1476 void Assembler::bgtz(Register rs, int16_t offset) {
1477 BlockTrampolinePoolScope block_trampoline_pool(this);
1478 GenInstrImmediate(BGTZ, rs, zero_reg, offset);
1479 BlockTrampolinePoolFor(1); // For associated delay slot.
1480 }
1481
bgtzc(Register rt,int16_t offset)1482 void Assembler::bgtzc(Register rt, int16_t offset) {
1483 DCHECK_EQ(kArchVariant, kMips64r6);
1484 DCHECK(rt != zero_reg);
1485 GenInstrImmediate(BGTZL, zero_reg, rt, offset,
1486 CompactBranchType::COMPACT_BRANCH);
1487 }
1488
blez(Register rs,int16_t offset)1489 void Assembler::blez(Register rs, int16_t offset) {
1490 BlockTrampolinePoolScope block_trampoline_pool(this);
1491 GenInstrImmediate(BLEZ, rs, zero_reg, offset);
1492 BlockTrampolinePoolFor(1); // For associated delay slot.
1493 }
1494
blezc(Register rt,int16_t offset)1495 void Assembler::blezc(Register rt, int16_t offset) {
1496 DCHECK_EQ(kArchVariant, kMips64r6);
1497 DCHECK(rt != zero_reg);
1498 GenInstrImmediate(BLEZL, zero_reg, rt, offset,
1499 CompactBranchType::COMPACT_BRANCH);
1500 }
1501
bltzc(Register rt,int16_t offset)1502 void Assembler::bltzc(Register rt, int16_t offset) {
1503 DCHECK_EQ(kArchVariant, kMips64r6);
1504 DCHECK(rt != zero_reg);
1505 GenInstrImmediate(BGTZL, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
1506 }
1507
bltuc(Register rs,Register rt,int16_t offset)1508 void Assembler::bltuc(Register rs, Register rt, int16_t offset) {
1509 DCHECK_EQ(kArchVariant, kMips64r6);
1510 DCHECK(rs != zero_reg);
1511 DCHECK(rt != zero_reg);
1512 DCHECK(rs.code() != rt.code());
1513 GenInstrImmediate(BGTZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1514 }
1515
bltc(Register rs,Register rt,int16_t offset)1516 void Assembler::bltc(Register rs, Register rt, int16_t offset) {
1517 DCHECK_EQ(kArchVariant, kMips64r6);
1518 DCHECK(rs != zero_reg);
1519 DCHECK(rt != zero_reg);
1520 DCHECK(rs.code() != rt.code());
1521 GenInstrImmediate(BGTZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1522 }
1523
bltz(Register rs,int16_t offset)1524 void Assembler::bltz(Register rs, int16_t offset) {
1525 BlockTrampolinePoolScope block_trampoline_pool(this);
1526 GenInstrImmediate(REGIMM, rs, BLTZ, offset);
1527 BlockTrampolinePoolFor(1); // For associated delay slot.
1528 }
1529
bltzal(Register rs,int16_t offset)1530 void Assembler::bltzal(Register rs, int16_t offset) {
1531 DCHECK(kArchVariant != kMips64r6 || rs == zero_reg);
1532 DCHECK(rs != ra);
1533 BlockTrampolinePoolScope block_trampoline_pool(this);
1534 GenInstrImmediate(REGIMM, rs, BLTZAL, offset);
1535 BlockTrampolinePoolFor(1); // For associated delay slot.
1536 }
1537
bne(Register rs,Register rt,int16_t offset)1538 void Assembler::bne(Register rs, Register rt, int16_t offset) {
1539 BlockTrampolinePoolScope block_trampoline_pool(this);
1540 GenInstrImmediate(BNE, rs, rt, offset);
1541 BlockTrampolinePoolFor(1); // For associated delay slot.
1542 }
1543
bovc(Register rs,Register rt,int16_t offset)1544 void Assembler::bovc(Register rs, Register rt, int16_t offset) {
1545 DCHECK_EQ(kArchVariant, kMips64r6);
1546 if (rs.code() >= rt.code()) {
1547 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1548 } else {
1549 GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
1550 }
1551 }
1552
bnvc(Register rs,Register rt,int16_t offset)1553 void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
1554 DCHECK_EQ(kArchVariant, kMips64r6);
1555 if (rs.code() >= rt.code()) {
1556 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1557 } else {
1558 GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
1559 }
1560 }
1561
blezalc(Register rt,int16_t offset)1562 void Assembler::blezalc(Register rt, int16_t offset) {
1563 DCHECK_EQ(kArchVariant, kMips64r6);
1564 DCHECK(rt != zero_reg);
1565 DCHECK(rt != ra);
1566 GenInstrImmediate(BLEZ, zero_reg, rt, offset,
1567 CompactBranchType::COMPACT_BRANCH);
1568 }
1569
bgezalc(Register rt,int16_t offset)1570 void Assembler::bgezalc(Register rt, int16_t offset) {
1571 DCHECK_EQ(kArchVariant, kMips64r6);
1572 DCHECK(rt != zero_reg);
1573 DCHECK(rt != ra);
1574 GenInstrImmediate(BLEZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
1575 }
1576
bgezall(Register rs,int16_t offset)1577 void Assembler::bgezall(Register rs, int16_t offset) {
1578 DCHECK_NE(kArchVariant, kMips64r6);
1579 DCHECK(rs != zero_reg);
1580 DCHECK(rs != ra);
1581 BlockTrampolinePoolScope block_trampoline_pool(this);
1582 GenInstrImmediate(REGIMM, rs, BGEZALL, offset);
1583 BlockTrampolinePoolFor(1); // For associated delay slot.
1584 }
1585
bltzalc(Register rt,int16_t offset)1586 void Assembler::bltzalc(Register rt, int16_t offset) {
1587 DCHECK_EQ(kArchVariant, kMips64r6);
1588 DCHECK(rt != zero_reg);
1589 DCHECK(rt != ra);
1590 GenInstrImmediate(BGTZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
1591 }
1592
bgtzalc(Register rt,int16_t offset)1593 void Assembler::bgtzalc(Register rt, int16_t offset) {
1594 DCHECK_EQ(kArchVariant, kMips64r6);
1595 DCHECK(rt != zero_reg);
1596 DCHECK(rt != ra);
1597 GenInstrImmediate(BGTZ, zero_reg, rt, offset,
1598 CompactBranchType::COMPACT_BRANCH);
1599 }
1600
beqzalc(Register rt,int16_t offset)1601 void Assembler::beqzalc(Register rt, int16_t offset) {
1602 DCHECK_EQ(kArchVariant, kMips64r6);
1603 DCHECK(rt != zero_reg);
1604 DCHECK(rt != ra);
1605 GenInstrImmediate(ADDI, zero_reg, rt, offset,
1606 CompactBranchType::COMPACT_BRANCH);
1607 }
1608
bnezalc(Register rt,int16_t offset)1609 void Assembler::bnezalc(Register rt, int16_t offset) {
1610 DCHECK_EQ(kArchVariant, kMips64r6);
1611 DCHECK(rt != zero_reg);
1612 DCHECK(rt != ra);
1613 GenInstrImmediate(DADDI, zero_reg, rt, offset,
1614 CompactBranchType::COMPACT_BRANCH);
1615 }
1616
beqc(Register rs,Register rt,int16_t offset)1617 void Assembler::beqc(Register rs, Register rt, int16_t offset) {
1618 DCHECK_EQ(kArchVariant, kMips64r6);
1619 DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0);
1620 if (rs.code() < rt.code()) {
1621 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1622 } else {
1623 GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
1624 }
1625 }
1626
beqzc(Register rs,int32_t offset)1627 void Assembler::beqzc(Register rs, int32_t offset) {
1628 DCHECK_EQ(kArchVariant, kMips64r6);
1629 DCHECK(rs != zero_reg);
1630 GenInstrImmediate(POP66, rs, offset, CompactBranchType::COMPACT_BRANCH);
1631 }
1632
bnec(Register rs,Register rt,int16_t offset)1633 void Assembler::bnec(Register rs, Register rt, int16_t offset) {
1634 DCHECK_EQ(kArchVariant, kMips64r6);
1635 DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0);
1636 if (rs.code() < rt.code()) {
1637 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1638 } else {
1639 GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
1640 }
1641 }
1642
bnezc(Register rs,int32_t offset)1643 void Assembler::bnezc(Register rs, int32_t offset) {
1644 DCHECK_EQ(kArchVariant, kMips64r6);
1645 DCHECK(rs != zero_reg);
1646 GenInstrImmediate(POP76, rs, offset, CompactBranchType::COMPACT_BRANCH);
1647 }
1648
j(int64_t target)1649 void Assembler::j(int64_t target) {
1650 // Deprecated. Use PC-relative jumps instead.
1651 UNREACHABLE();
1652 }
1653
j(Label * target)1654 void Assembler::j(Label* target) {
1655 // Deprecated. Use PC-relative jumps instead.
1656 UNREACHABLE();
1657 }
1658
jal(Label * target)1659 void Assembler::jal(Label* target) {
1660 // Deprecated. Use PC-relative jumps instead.
1661 UNREACHABLE();
1662 }
1663
jal(int64_t target)1664 void Assembler::jal(int64_t target) {
1665 // Deprecated. Use PC-relative jumps instead.
1666 UNREACHABLE();
1667 }
1668
jr(Register rs)1669 void Assembler::jr(Register rs) {
1670 if (kArchVariant != kMips64r6) {
1671 BlockTrampolinePoolScope block_trampoline_pool(this);
1672 GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
1673 BlockTrampolinePoolFor(1); // For associated delay slot.
1674 } else {
1675 jalr(rs, zero_reg);
1676 }
1677 }
1678
jalr(Register rs,Register rd)1679 void Assembler::jalr(Register rs, Register rd) {
1680 DCHECK(rs.code() != rd.code());
1681 BlockTrampolinePoolScope block_trampoline_pool(this);
1682 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
1683 BlockTrampolinePoolFor(1); // For associated delay slot.
1684 }
1685
jic(Register rt,int16_t offset)1686 void Assembler::jic(Register rt, int16_t offset) {
1687 DCHECK_EQ(kArchVariant, kMips64r6);
1688 GenInstrImmediate(POP66, zero_reg, rt, offset);
1689 }
1690
jialc(Register rt,int16_t offset)1691 void Assembler::jialc(Register rt, int16_t offset) {
1692 DCHECK_EQ(kArchVariant, kMips64r6);
1693 GenInstrImmediate(POP76, zero_reg, rt, offset);
1694 }
1695
1696 // -------Data-processing-instructions---------
1697
1698 // Arithmetic.
1699
addu(Register rd,Register rs,Register rt)1700 void Assembler::addu(Register rd, Register rs, Register rt) {
1701 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
1702 }
1703
addiu(Register rd,Register rs,int32_t j)1704 void Assembler::addiu(Register rd, Register rs, int32_t j) {
1705 GenInstrImmediate(ADDIU, rs, rd, j);
1706 }
1707
subu(Register rd,Register rs,Register rt)1708 void Assembler::subu(Register rd, Register rs, Register rt) {
1709 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
1710 }
1711
mul(Register rd,Register rs,Register rt)1712 void Assembler::mul(Register rd, Register rs, Register rt) {
1713 if (kArchVariant == kMips64r6) {
1714 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH);
1715 } else {
1716 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
1717 }
1718 }
1719
muh(Register rd,Register rs,Register rt)1720 void Assembler::muh(Register rd, Register rs, Register rt) {
1721 DCHECK_EQ(kArchVariant, kMips64r6);
1722 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH);
1723 }
1724
mulu(Register rd,Register rs,Register rt)1725 void Assembler::mulu(Register rd, Register rs, Register rt) {
1726 DCHECK_EQ(kArchVariant, kMips64r6);
1727 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U);
1728 }
1729
muhu(Register rd,Register rs,Register rt)1730 void Assembler::muhu(Register rd, Register rs, Register rt) {
1731 DCHECK_EQ(kArchVariant, kMips64r6);
1732 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U);
1733 }
1734
dmul(Register rd,Register rs,Register rt)1735 void Assembler::dmul(Register rd, Register rs, Register rt) {
1736 DCHECK_EQ(kArchVariant, kMips64r6);
1737 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH);
1738 }
1739
dmuh(Register rd,Register rs,Register rt)1740 void Assembler::dmuh(Register rd, Register rs, Register rt) {
1741 DCHECK_EQ(kArchVariant, kMips64r6);
1742 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH);
1743 }
1744
dmulu(Register rd,Register rs,Register rt)1745 void Assembler::dmulu(Register rd, Register rs, Register rt) {
1746 DCHECK_EQ(kArchVariant, kMips64r6);
1747 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH_U);
1748 }
1749
dmuhu(Register rd,Register rs,Register rt)1750 void Assembler::dmuhu(Register rd, Register rs, Register rt) {
1751 DCHECK_EQ(kArchVariant, kMips64r6);
1752 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH_U);
1753 }
1754
mult(Register rs,Register rt)1755 void Assembler::mult(Register rs, Register rt) {
1756 DCHECK_NE(kArchVariant, kMips64r6);
1757 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT);
1758 }
1759
multu(Register rs,Register rt)1760 void Assembler::multu(Register rs, Register rt) {
1761 DCHECK_NE(kArchVariant, kMips64r6);
1762 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU);
1763 }
1764
daddiu(Register rd,Register rs,int32_t j)1765 void Assembler::daddiu(Register rd, Register rs, int32_t j) {
1766 GenInstrImmediate(DADDIU, rs, rd, j);
1767 }
1768
div(Register rs,Register rt)1769 void Assembler::div(Register rs, Register rt) {
1770 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV);
1771 }
1772
div(Register rd,Register rs,Register rt)1773 void Assembler::div(Register rd, Register rs, Register rt) {
1774 DCHECK_EQ(kArchVariant, kMips64r6);
1775 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD);
1776 }
1777
mod(Register rd,Register rs,Register rt)1778 void Assembler::mod(Register rd, Register rs, Register rt) {
1779 DCHECK_EQ(kArchVariant, kMips64r6);
1780 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD);
1781 }
1782
divu(Register rs,Register rt)1783 void Assembler::divu(Register rs, Register rt) {
1784 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU);
1785 }
1786
divu(Register rd,Register rs,Register rt)1787 void Assembler::divu(Register rd, Register rs, Register rt) {
1788 DCHECK_EQ(kArchVariant, kMips64r6);
1789 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U);
1790 }
1791
modu(Register rd,Register rs,Register rt)1792 void Assembler::modu(Register rd, Register rs, Register rt) {
1793 DCHECK_EQ(kArchVariant, kMips64r6);
1794 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U);
1795 }
1796
daddu(Register rd,Register rs,Register rt)1797 void Assembler::daddu(Register rd, Register rs, Register rt) {
1798 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DADDU);
1799 }
1800
dsubu(Register rd,Register rs,Register rt)1801 void Assembler::dsubu(Register rd, Register rs, Register rt) {
1802 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSUBU);
1803 }
1804
dmult(Register rs,Register rt)1805 void Assembler::dmult(Register rs, Register rt) {
1806 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULT);
1807 }
1808
dmultu(Register rs,Register rt)1809 void Assembler::dmultu(Register rs, Register rt) {
1810 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULTU);
1811 }
1812
ddiv(Register rs,Register rt)1813 void Assembler::ddiv(Register rs, Register rt) {
1814 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIV);
1815 }
1816
ddiv(Register rd,Register rs,Register rt)1817 void Assembler::ddiv(Register rd, Register rs, Register rt) {
1818 DCHECK_EQ(kArchVariant, kMips64r6);
1819 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD);
1820 }
1821
dmod(Register rd,Register rs,Register rt)1822 void Assembler::dmod(Register rd, Register rs, Register rt) {
1823 DCHECK_EQ(kArchVariant, kMips64r6);
1824 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD);
1825 }
1826
ddivu(Register rs,Register rt)1827 void Assembler::ddivu(Register rs, Register rt) {
1828 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIVU);
1829 }
1830
ddivu(Register rd,Register rs,Register rt)1831 void Assembler::ddivu(Register rd, Register rs, Register rt) {
1832 DCHECK_EQ(kArchVariant, kMips64r6);
1833 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U);
1834 }
1835
dmodu(Register rd,Register rs,Register rt)1836 void Assembler::dmodu(Register rd, Register rs, Register rt) {
1837 DCHECK_EQ(kArchVariant, kMips64r6);
1838 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD_U);
1839 }
1840
1841 // Logical.
1842
and_(Register rd,Register rs,Register rt)1843 void Assembler::and_(Register rd, Register rs, Register rt) {
1844 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
1845 }
1846
andi(Register rt,Register rs,int32_t j)1847 void Assembler::andi(Register rt, Register rs, int32_t j) {
1848 DCHECK(is_uint16(j));
1849 GenInstrImmediate(ANDI, rs, rt, j);
1850 }
1851
or_(Register rd,Register rs,Register rt)1852 void Assembler::or_(Register rd, Register rs, Register rt) {
1853 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
1854 }
1855
ori(Register rt,Register rs,int32_t j)1856 void Assembler::ori(Register rt, Register rs, int32_t j) {
1857 DCHECK(is_uint16(j));
1858 GenInstrImmediate(ORI, rs, rt, j);
1859 }
1860
xor_(Register rd,Register rs,Register rt)1861 void Assembler::xor_(Register rd, Register rs, Register rt) {
1862 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
1863 }
1864
xori(Register rt,Register rs,int32_t j)1865 void Assembler::xori(Register rt, Register rs, int32_t j) {
1866 DCHECK(is_uint16(j));
1867 GenInstrImmediate(XORI, rs, rt, j);
1868 }
1869
nor(Register rd,Register rs,Register rt)1870 void Assembler::nor(Register rd, Register rs, Register rt) {
1871 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
1872 }
1873
1874 // Shifts.
sll(Register rd,Register rt,uint16_t sa,bool coming_from_nop)1875 void Assembler::sll(Register rd, Register rt, uint16_t sa,
1876 bool coming_from_nop) {
1877 // Don't allow nop instructions in the form sll zero_reg, zero_reg to be
1878 // generated using the sll instruction. They must be generated using
1879 // nop(int/NopMarkerTypes).
1880 DCHECK(coming_from_nop || (rd != zero_reg && rt != zero_reg));
1881 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SLL);
1882 }
1883
sllv(Register rd,Register rt,Register rs)1884 void Assembler::sllv(Register rd, Register rt, Register rs) {
1885 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
1886 }
1887
srl(Register rd,Register rt,uint16_t sa)1888 void Assembler::srl(Register rd, Register rt, uint16_t sa) {
1889 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRL);
1890 }
1891
srlv(Register rd,Register rt,Register rs)1892 void Assembler::srlv(Register rd, Register rt, Register rs) {
1893 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
1894 }
1895
sra(Register rd,Register rt,uint16_t sa)1896 void Assembler::sra(Register rd, Register rt, uint16_t sa) {
1897 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRA);
1898 }
1899
srav(Register rd,Register rt,Register rs)1900 void Assembler::srav(Register rd, Register rt, Register rs) {
1901 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
1902 }
1903
rotr(Register rd,Register rt,uint16_t sa)1904 void Assembler::rotr(Register rd, Register rt, uint16_t sa) {
1905 // Should be called via MacroAssembler::Ror.
1906 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1907 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
1908 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) |
1909 (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
1910 emit(instr);
1911 }
1912
rotrv(Register rd,Register rt,Register rs)1913 void Assembler::rotrv(Register rd, Register rt, Register rs) {
1914 // Should be called via MacroAssembler::Ror.
1915 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
1916 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
1917 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1918 (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
1919 emit(instr);
1920 }
1921
dsll(Register rd,Register rt,uint16_t sa)1922 void Assembler::dsll(Register rd, Register rt, uint16_t sa) {
1923 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL);
1924 }
1925
dsllv(Register rd,Register rt,Register rs)1926 void Assembler::dsllv(Register rd, Register rt, Register rs) {
1927 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSLLV);
1928 }
1929
dsrl(Register rd,Register rt,uint16_t sa)1930 void Assembler::dsrl(Register rd, Register rt, uint16_t sa) {
1931 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL);
1932 }
1933
dsrlv(Register rd,Register rt,Register rs)1934 void Assembler::dsrlv(Register rd, Register rt, Register rs) {
1935 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRLV);
1936 }
1937
drotr(Register rd,Register rt,uint16_t sa)1938 void Assembler::drotr(Register rd, Register rt, uint16_t sa) {
1939 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1940 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) |
1941 (rd.code() << kRdShift) | (sa << kSaShift) | DSRL;
1942 emit(instr);
1943 }
1944
drotr32(Register rd,Register rt,uint16_t sa)1945 void Assembler::drotr32(Register rd, Register rt, uint16_t sa) {
1946 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1947 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) |
1948 (rd.code() << kRdShift) | (sa << kSaShift) | DSRL32;
1949 emit(instr);
1950 }
1951
drotrv(Register rd,Register rt,Register rs)1952 void Assembler::drotrv(Register rd, Register rt, Register rs) {
1953 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
1954 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1955 (rd.code() << kRdShift) | (1 << kSaShift) | DSRLV;
1956 emit(instr);
1957 }
1958
dsra(Register rd,Register rt,uint16_t sa)1959 void Assembler::dsra(Register rd, Register rt, uint16_t sa) {
1960 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRA);
1961 }
1962
dsrav(Register rd,Register rt,Register rs)1963 void Assembler::dsrav(Register rd, Register rt, Register rs) {
1964 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRAV);
1965 }
1966
dsll32(Register rd,Register rt,uint16_t sa)1967 void Assembler::dsll32(Register rd, Register rt, uint16_t sa) {
1968 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL32);
1969 }
1970
dsrl32(Register rd,Register rt,uint16_t sa)1971 void Assembler::dsrl32(Register rd, Register rt, uint16_t sa) {
1972 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL32);
1973 }
1974
dsra32(Register rd,Register rt,uint16_t sa)1975 void Assembler::dsra32(Register rd, Register rt, uint16_t sa) {
1976 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRA32);
1977 }
1978
lsa(Register rd,Register rt,Register rs,uint8_t sa)1979 void Assembler::lsa(Register rd, Register rt, Register rs, uint8_t sa) {
1980 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
1981 DCHECK_LE(sa, 3);
1982 DCHECK_EQ(kArchVariant, kMips64r6);
1983 Instr instr = SPECIAL | rs.code() << kRsShift | rt.code() << kRtShift |
1984 rd.code() << kRdShift | sa << kSaShift | LSA;
1985 emit(instr);
1986 }
1987
dlsa(Register rd,Register rt,Register rs,uint8_t sa)1988 void Assembler::dlsa(Register rd, Register rt, Register rs, uint8_t sa) {
1989 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
1990 DCHECK_LE(sa, 3);
1991 DCHECK_EQ(kArchVariant, kMips64r6);
1992 Instr instr = SPECIAL | rs.code() << kRsShift | rt.code() << kRtShift |
1993 rd.code() << kRdShift | sa << kSaShift | DLSA;
1994 emit(instr);
1995 }
1996
1997 // ------------Memory-instructions-------------
1998
AdjustBaseAndOffset(MemOperand * src,OffsetAccessType access_type,int second_access_add_to_offset)1999 void Assembler::AdjustBaseAndOffset(MemOperand* src,
2000 OffsetAccessType access_type,
2001 int second_access_add_to_offset) {
2002 // This method is used to adjust the base register and offset pair
2003 // for a load/store when the offset doesn't fit into int16_t.
2004 // It is assumed that 'base + offset' is sufficiently aligned for memory
2005 // operands that are machine word in size or smaller. For doubleword-sized
2006 // operands it's assumed that 'base' is a multiple of 8, while 'offset'
2007 // may be a multiple of 4 (e.g. 4-byte-aligned long and double arguments
2008 // and spilled variables on the stack accessed relative to the stack
2009 // pointer register).
2010 // We preserve the "alignment" of 'offset' by adjusting it by a multiple of 8.
2011
2012 bool doubleword_aligned = (src->offset() & (kDoubleSize - 1)) == 0;
2013 bool two_accesses = static_cast<bool>(access_type) || !doubleword_aligned;
2014 DCHECK_LE(second_access_add_to_offset, 7); // Must be <= 7.
2015
2016 // is_int16 must be passed a signed value, hence the static cast below.
2017 if (is_int16(src->offset()) &&
2018 (!two_accesses || is_int16(static_cast<int32_t>(
2019 src->offset() + second_access_add_to_offset)))) {
2020 // Nothing to do: 'offset' (and, if needed, 'offset + 4', or other specified
2021 // value) fits into int16_t.
2022 return;
2023 }
2024
2025 DCHECK(src->rm() !=
2026 at); // Must not overwrite the register 'base' while loading 'offset'.
2027
2028 #ifdef DEBUG
2029 // Remember the "(mis)alignment" of 'offset', it will be checked at the end.
2030 uint32_t misalignment = src->offset() & (kDoubleSize - 1);
2031 #endif
2032
2033 // Do not load the whole 32-bit 'offset' if it can be represented as
2034 // a sum of two 16-bit signed offsets. This can save an instruction or two.
2035 // To simplify matters, only do this for a symmetric range of offsets from
2036 // about -64KB to about +64KB, allowing further addition of 4 when accessing
2037 // 64-bit variables with two 32-bit accesses.
2038 constexpr int32_t kMinOffsetForSimpleAdjustment =
2039 0x7FF8; // Max int16_t that's a multiple of 8.
2040 constexpr int32_t kMaxOffsetForSimpleAdjustment =
2041 2 * kMinOffsetForSimpleAdjustment;
2042
2043 UseScratchRegisterScope temps(this);
2044 Register scratch = temps.Acquire();
2045 if (0 <= src->offset() && src->offset() <= kMaxOffsetForSimpleAdjustment) {
2046 daddiu(scratch, src->rm(), kMinOffsetForSimpleAdjustment);
2047 src->offset_ -= kMinOffsetForSimpleAdjustment;
2048 } else if (-kMaxOffsetForSimpleAdjustment <= src->offset() &&
2049 src->offset() < 0) {
2050 daddiu(scratch, src->rm(), -kMinOffsetForSimpleAdjustment);
2051 src->offset_ += kMinOffsetForSimpleAdjustment;
2052 } else if (kArchVariant == kMips64r6) {
2053 // On r6 take advantage of the daui instruction, e.g.:
2054 // daui at, base, offset_high
2055 // [dahi at, 1] // When `offset` is close to +2GB.
2056 // lw reg_lo, offset_low(at)
2057 // [lw reg_hi, (offset_low+4)(at)] // If misaligned 64-bit load.
2058 // or when offset_low+4 overflows int16_t:
2059 // daui at, base, offset_high
2060 // daddiu at, at, 8
2061 // lw reg_lo, (offset_low-8)(at)
2062 // lw reg_hi, (offset_low-4)(at)
2063 int16_t offset_low = static_cast<uint16_t>(src->offset());
2064 int32_t offset_low32 = offset_low;
2065 int16_t offset_high = static_cast<uint16_t>(src->offset() >> 16);
2066 bool increment_hi16 = offset_low < 0;
2067 bool overflow_hi16 = false;
2068
2069 if (increment_hi16) {
2070 offset_high++;
2071 overflow_hi16 = (offset_high == -32768);
2072 }
2073 daui(scratch, src->rm(), static_cast<uint16_t>(offset_high));
2074
2075 if (overflow_hi16) {
2076 dahi(scratch, 1);
2077 }
2078
2079 if (two_accesses && !is_int16(static_cast<int32_t>(
2080 offset_low32 + second_access_add_to_offset))) {
2081 // Avoid overflow in the 16-bit offset of the load/store instruction when
2082 // adding 4.
2083 daddiu(scratch, scratch, kDoubleSize);
2084 offset_low32 -= kDoubleSize;
2085 }
2086
2087 src->offset_ = offset_low32;
2088 } else {
2089 // Do not load the whole 32-bit 'offset' if it can be represented as
2090 // a sum of three 16-bit signed offsets. This can save an instruction.
2091 // To simplify matters, only do this for a symmetric range of offsets from
2092 // about -96KB to about +96KB, allowing further addition of 4 when accessing
2093 // 64-bit variables with two 32-bit accesses.
2094 constexpr int32_t kMinOffsetForMediumAdjustment =
2095 2 * kMinOffsetForSimpleAdjustment;
2096 constexpr int32_t kMaxOffsetForMediumAdjustment =
2097 3 * kMinOffsetForSimpleAdjustment;
2098 if (0 <= src->offset() && src->offset() <= kMaxOffsetForMediumAdjustment) {
2099 daddiu(scratch, src->rm(), kMinOffsetForMediumAdjustment / 2);
2100 daddiu(scratch, scratch, kMinOffsetForMediumAdjustment / 2);
2101 src->offset_ -= kMinOffsetForMediumAdjustment;
2102 } else if (-kMaxOffsetForMediumAdjustment <= src->offset() &&
2103 src->offset() < 0) {
2104 daddiu(scratch, src->rm(), -kMinOffsetForMediumAdjustment / 2);
2105 daddiu(scratch, scratch, -kMinOffsetForMediumAdjustment / 2);
2106 src->offset_ += kMinOffsetForMediumAdjustment;
2107 } else {
2108 // Now that all shorter options have been exhausted, load the full 32-bit
2109 // offset.
2110 int32_t loaded_offset = RoundDown(src->offset(), kDoubleSize);
2111 lui(scratch, (loaded_offset >> kLuiShift) & kImm16Mask);
2112 ori(scratch, scratch, loaded_offset & kImm16Mask); // Load 32-bit offset.
2113 daddu(scratch, scratch, src->rm());
2114 src->offset_ -= loaded_offset;
2115 }
2116 }
2117 src->rm_ = scratch;
2118
2119 DCHECK(is_int16(src->offset()));
2120 if (two_accesses) {
2121 DCHECK(is_int16(
2122 static_cast<int32_t>(src->offset() + second_access_add_to_offset)));
2123 }
2124 DCHECK(misalignment == (src->offset() & (kDoubleSize - 1)));
2125 }
2126
lb(Register rd,const MemOperand & rs)2127 void Assembler::lb(Register rd, const MemOperand& rs) {
2128 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
2129 }
2130
lbu(Register rd,const MemOperand & rs)2131 void Assembler::lbu(Register rd, const MemOperand& rs) {
2132 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_);
2133 }
2134
lh(Register rd,const MemOperand & rs)2135 void Assembler::lh(Register rd, const MemOperand& rs) {
2136 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_);
2137 }
2138
lhu(Register rd,const MemOperand & rs)2139 void Assembler::lhu(Register rd, const MemOperand& rs) {
2140 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_);
2141 }
2142
lw(Register rd,const MemOperand & rs)2143 void Assembler::lw(Register rd, const MemOperand& rs) {
2144 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
2145 }
2146
lwu(Register rd,const MemOperand & rs)2147 void Assembler::lwu(Register rd, const MemOperand& rs) {
2148 GenInstrImmediate(LWU, rs.rm(), rd, rs.offset_);
2149 }
2150
lwl(Register rd,const MemOperand & rs)2151 void Assembler::lwl(Register rd, const MemOperand& rs) {
2152 DCHECK(is_int16(rs.offset_));
2153 DCHECK_EQ(kArchVariant, kMips64r2);
2154 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
2155 }
2156
lwr(Register rd,const MemOperand & rs)2157 void Assembler::lwr(Register rd, const MemOperand& rs) {
2158 DCHECK(is_int16(rs.offset_));
2159 DCHECK_EQ(kArchVariant, kMips64r2);
2160 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
2161 }
2162
sb(Register rd,const MemOperand & rs)2163 void Assembler::sb(Register rd, const MemOperand& rs) {
2164 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_);
2165 }
2166
sh(Register rd,const MemOperand & rs)2167 void Assembler::sh(Register rd, const MemOperand& rs) {
2168 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_);
2169 }
2170
sw(Register rd,const MemOperand & rs)2171 void Assembler::sw(Register rd, const MemOperand& rs) {
2172 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_);
2173 }
2174
swl(Register rd,const MemOperand & rs)2175 void Assembler::swl(Register rd, const MemOperand& rs) {
2176 DCHECK(is_int16(rs.offset_));
2177 DCHECK_EQ(kArchVariant, kMips64r2);
2178 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
2179 }
2180
swr(Register rd,const MemOperand & rs)2181 void Assembler::swr(Register rd, const MemOperand& rs) {
2182 DCHECK(is_int16(rs.offset_));
2183 DCHECK_EQ(kArchVariant, kMips64r2);
2184 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
2185 }
2186
ll(Register rd,const MemOperand & rs)2187 void Assembler::ll(Register rd, const MemOperand& rs) {
2188 if (kArchVariant == kMips64r6) {
2189 DCHECK(is_int9(rs.offset_));
2190 GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, LL_R6);
2191 } else {
2192 DCHECK_EQ(kArchVariant, kMips64r2);
2193 DCHECK(is_int16(rs.offset_));
2194 GenInstrImmediate(LL, rs.rm(), rd, rs.offset_);
2195 }
2196 }
2197
lld(Register rd,const MemOperand & rs)2198 void Assembler::lld(Register rd, const MemOperand& rs) {
2199 if (kArchVariant == kMips64r6) {
2200 DCHECK(is_int9(rs.offset_));
2201 GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, LLD_R6);
2202 } else {
2203 DCHECK_EQ(kArchVariant, kMips64r2);
2204 DCHECK(is_int16(rs.offset_));
2205 GenInstrImmediate(LLD, rs.rm(), rd, rs.offset_);
2206 }
2207 }
2208
sc(Register rd,const MemOperand & rs)2209 void Assembler::sc(Register rd, const MemOperand& rs) {
2210 if (kArchVariant == kMips64r6) {
2211 DCHECK(is_int9(rs.offset_));
2212 GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, SC_R6);
2213 } else {
2214 DCHECK_EQ(kArchVariant, kMips64r2);
2215 GenInstrImmediate(SC, rs.rm(), rd, rs.offset_);
2216 }
2217 }
2218
scd(Register rd,const MemOperand & rs)2219 void Assembler::scd(Register rd, const MemOperand& rs) {
2220 if (kArchVariant == kMips64r6) {
2221 DCHECK(is_int9(rs.offset_));
2222 GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, SCD_R6);
2223 } else {
2224 DCHECK_EQ(kArchVariant, kMips64r2);
2225 GenInstrImmediate(SCD, rs.rm(), rd, rs.offset_);
2226 }
2227 }
2228
lui(Register rd,int32_t j)2229 void Assembler::lui(Register rd, int32_t j) {
2230 DCHECK(is_uint16(j) || is_int16(j));
2231 GenInstrImmediate(LUI, zero_reg, rd, j);
2232 }
2233
aui(Register rt,Register rs,int32_t j)2234 void Assembler::aui(Register rt, Register rs, int32_t j) {
2235 // This instruction uses same opcode as 'lui'. The difference in encoding is
2236 // 'lui' has zero reg. for rs field.
2237 DCHECK(is_uint16(j));
2238 GenInstrImmediate(LUI, rs, rt, j);
2239 }
2240
daui(Register rt,Register rs,int32_t j)2241 void Assembler::daui(Register rt, Register rs, int32_t j) {
2242 DCHECK(is_uint16(j));
2243 DCHECK(rs != zero_reg);
2244 GenInstrImmediate(DAUI, rs, rt, j);
2245 }
2246
dahi(Register rs,int32_t j)2247 void Assembler::dahi(Register rs, int32_t j) {
2248 DCHECK(is_uint16(j));
2249 GenInstrImmediate(REGIMM, rs, DAHI, j);
2250 }
2251
dati(Register rs,int32_t j)2252 void Assembler::dati(Register rs, int32_t j) {
2253 DCHECK(is_uint16(j));
2254 GenInstrImmediate(REGIMM, rs, DATI, j);
2255 }
2256
ldl(Register rd,const MemOperand & rs)2257 void Assembler::ldl(Register rd, const MemOperand& rs) {
2258 DCHECK(is_int16(rs.offset_));
2259 DCHECK_EQ(kArchVariant, kMips64r2);
2260 GenInstrImmediate(LDL, rs.rm(), rd, rs.offset_);
2261 }
2262
ldr(Register rd,const MemOperand & rs)2263 void Assembler::ldr(Register rd, const MemOperand& rs) {
2264 DCHECK(is_int16(rs.offset_));
2265 DCHECK_EQ(kArchVariant, kMips64r2);
2266 GenInstrImmediate(LDR, rs.rm(), rd, rs.offset_);
2267 }
2268
sdl(Register rd,const MemOperand & rs)2269 void Assembler::sdl(Register rd, const MemOperand& rs) {
2270 DCHECK(is_int16(rs.offset_));
2271 DCHECK_EQ(kArchVariant, kMips64r2);
2272 GenInstrImmediate(SDL, rs.rm(), rd, rs.offset_);
2273 }
2274
sdr(Register rd,const MemOperand & rs)2275 void Assembler::sdr(Register rd, const MemOperand& rs) {
2276 DCHECK(is_int16(rs.offset_));
2277 DCHECK_EQ(kArchVariant, kMips64r2);
2278 GenInstrImmediate(SDR, rs.rm(), rd, rs.offset_);
2279 }
2280
ld(Register rd,const MemOperand & rs)2281 void Assembler::ld(Register rd, const MemOperand& rs) {
2282 GenInstrImmediate(LD, rs.rm(), rd, rs.offset_);
2283 }
2284
sd(Register rd,const MemOperand & rs)2285 void Assembler::sd(Register rd, const MemOperand& rs) {
2286 GenInstrImmediate(SD, rs.rm(), rd, rs.offset_);
2287 }
2288
2289 // ---------PC-Relative instructions-----------
2290
addiupc(Register rs,int32_t imm19)2291 void Assembler::addiupc(Register rs, int32_t imm19) {
2292 DCHECK_EQ(kArchVariant, kMips64r6);
2293 DCHECK(rs.is_valid() && is_int19(imm19));
2294 uint32_t imm21 = ADDIUPC << kImm19Bits | (imm19 & kImm19Mask);
2295 GenInstrImmediate(PCREL, rs, imm21);
2296 }
2297
lwpc(Register rs,int32_t offset19)2298 void Assembler::lwpc(Register rs, int32_t offset19) {
2299 DCHECK_EQ(kArchVariant, kMips64r6);
2300 DCHECK(rs.is_valid() && is_int19(offset19));
2301 uint32_t imm21 = LWPC << kImm19Bits | (offset19 & kImm19Mask);
2302 GenInstrImmediate(PCREL, rs, imm21);
2303 }
2304
lwupc(Register rs,int32_t offset19)2305 void Assembler::lwupc(Register rs, int32_t offset19) {
2306 DCHECK_EQ(kArchVariant, kMips64r6);
2307 DCHECK(rs.is_valid() && is_int19(offset19));
2308 uint32_t imm21 = LWUPC << kImm19Bits | (offset19 & kImm19Mask);
2309 GenInstrImmediate(PCREL, rs, imm21);
2310 }
2311
ldpc(Register rs,int32_t offset18)2312 void Assembler::ldpc(Register rs, int32_t offset18) {
2313 DCHECK_EQ(kArchVariant, kMips64r6);
2314 DCHECK(rs.is_valid() && is_int18(offset18));
2315 uint32_t imm21 = LDPC << kImm18Bits | (offset18 & kImm18Mask);
2316 GenInstrImmediate(PCREL, rs, imm21);
2317 }
2318
auipc(Register rs,int16_t imm16)2319 void Assembler::auipc(Register rs, int16_t imm16) {
2320 DCHECK_EQ(kArchVariant, kMips64r6);
2321 DCHECK(rs.is_valid());
2322 uint32_t imm21 = AUIPC << kImm16Bits | (imm16 & kImm16Mask);
2323 GenInstrImmediate(PCREL, rs, imm21);
2324 }
2325
aluipc(Register rs,int16_t imm16)2326 void Assembler::aluipc(Register rs, int16_t imm16) {
2327 DCHECK_EQ(kArchVariant, kMips64r6);
2328 DCHECK(rs.is_valid());
2329 uint32_t imm21 = ALUIPC << kImm16Bits | (imm16 & kImm16Mask);
2330 GenInstrImmediate(PCREL, rs, imm21);
2331 }
2332
2333 // -------------Misc-instructions--------------
2334
2335 // Break / Trap instructions.
break_(uint32_t code,bool break_as_stop)2336 void Assembler::break_(uint32_t code, bool break_as_stop) {
2337 DCHECK_EQ(code & ~0xFFFFF, 0);
2338 // We need to invalidate breaks that could be stops as well because the
2339 // simulator expects a char pointer after the stop instruction.
2340 // See constants-mips.h for explanation.
2341 DCHECK(
2342 (break_as_stop && code <= kMaxStopCode && code > kMaxWatchpointCode) ||
2343 (!break_as_stop && (code > kMaxStopCode || code <= kMaxWatchpointCode)));
2344 Instr break_instr = SPECIAL | BREAK | (code << 6);
2345 emit(break_instr);
2346 }
2347
stop(uint32_t code)2348 void Assembler::stop(uint32_t code) {
2349 DCHECK_GT(code, kMaxWatchpointCode);
2350 DCHECK_LE(code, kMaxStopCode);
2351 #if defined(V8_HOST_ARCH_MIPS) || defined(V8_HOST_ARCH_MIPS64)
2352 break_(0x54321);
2353 #else // V8_HOST_ARCH_MIPS
2354 break_(code, true);
2355 #endif
2356 }
2357
tge(Register rs,Register rt,uint16_t code)2358 void Assembler::tge(Register rs, Register rt, uint16_t code) {
2359 DCHECK(is_uint10(code));
2360 Instr instr =
2361 SPECIAL | TGE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2362 emit(instr);
2363 }
2364
tgeu(Register rs,Register rt,uint16_t code)2365 void Assembler::tgeu(Register rs, Register rt, uint16_t code) {
2366 DCHECK(is_uint10(code));
2367 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift | rt.code() << kRtShift |
2368 code << 6;
2369 emit(instr);
2370 }
2371
tlt(Register rs,Register rt,uint16_t code)2372 void Assembler::tlt(Register rs, Register rt, uint16_t code) {
2373 DCHECK(is_uint10(code));
2374 Instr instr =
2375 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2376 emit(instr);
2377 }
2378
tltu(Register rs,Register rt,uint16_t code)2379 void Assembler::tltu(Register rs, Register rt, uint16_t code) {
2380 DCHECK(is_uint10(code));
2381 Instr instr = SPECIAL | TLTU | rs.code() << kRsShift | rt.code() << kRtShift |
2382 code << 6;
2383 emit(instr);
2384 }
2385
teq(Register rs,Register rt,uint16_t code)2386 void Assembler::teq(Register rs, Register rt, uint16_t code) {
2387 DCHECK(is_uint10(code));
2388 Instr instr =
2389 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2390 emit(instr);
2391 }
2392
tne(Register rs,Register rt,uint16_t code)2393 void Assembler::tne(Register rs, Register rt, uint16_t code) {
2394 DCHECK(is_uint10(code));
2395 Instr instr =
2396 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2397 emit(instr);
2398 }
2399
sync()2400 void Assembler::sync() {
2401 Instr sync_instr = SPECIAL | SYNC;
2402 emit(sync_instr);
2403 }
2404
2405 // Move from HI/LO register.
2406
mfhi(Register rd)2407 void Assembler::mfhi(Register rd) {
2408 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
2409 }
2410
mflo(Register rd)2411 void Assembler::mflo(Register rd) {
2412 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
2413 }
2414
2415 // Set on less than instructions.
slt(Register rd,Register rs,Register rt)2416 void Assembler::slt(Register rd, Register rs, Register rt) {
2417 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
2418 }
2419
sltu(Register rd,Register rs,Register rt)2420 void Assembler::sltu(Register rd, Register rs, Register rt) {
2421 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
2422 }
2423
slti(Register rt,Register rs,int32_t j)2424 void Assembler::slti(Register rt, Register rs, int32_t j) {
2425 GenInstrImmediate(SLTI, rs, rt, j);
2426 }
2427
sltiu(Register rt,Register rs,int32_t j)2428 void Assembler::sltiu(Register rt, Register rs, int32_t j) {
2429 GenInstrImmediate(SLTIU, rs, rt, j);
2430 }
2431
2432 // Conditional move.
movz(Register rd,Register rs,Register rt)2433 void Assembler::movz(Register rd, Register rs, Register rt) {
2434 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ);
2435 }
2436
movn(Register rd,Register rs,Register rt)2437 void Assembler::movn(Register rd, Register rs, Register rt) {
2438 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
2439 }
2440
movt(Register rd,Register rs,uint16_t cc)2441 void Assembler::movt(Register rd, Register rs, uint16_t cc) {
2442 Register rt = Register::from_code((cc & 0x0007) << 2 | 1);
2443 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
2444 }
2445
movf(Register rd,Register rs,uint16_t cc)2446 void Assembler::movf(Register rd, Register rs, uint16_t cc) {
2447 Register rt = Register::from_code((cc & 0x0007) << 2 | 0);
2448 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
2449 }
2450
min_s(FPURegister fd,FPURegister fs,FPURegister ft)2451 void Assembler::min_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2452 min(S, fd, fs, ft);
2453 }
2454
min_d(FPURegister fd,FPURegister fs,FPURegister ft)2455 void Assembler::min_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2456 min(D, fd, fs, ft);
2457 }
2458
max_s(FPURegister fd,FPURegister fs,FPURegister ft)2459 void Assembler::max_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2460 max(S, fd, fs, ft);
2461 }
2462
max_d(FPURegister fd,FPURegister fs,FPURegister ft)2463 void Assembler::max_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2464 max(D, fd, fs, ft);
2465 }
2466
mina_s(FPURegister fd,FPURegister fs,FPURegister ft)2467 void Assembler::mina_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2468 mina(S, fd, fs, ft);
2469 }
2470
mina_d(FPURegister fd,FPURegister fs,FPURegister ft)2471 void Assembler::mina_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2472 mina(D, fd, fs, ft);
2473 }
2474
maxa_s(FPURegister fd,FPURegister fs,FPURegister ft)2475 void Assembler::maxa_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2476 maxa(S, fd, fs, ft);
2477 }
2478
maxa_d(FPURegister fd,FPURegister fs,FPURegister ft)2479 void Assembler::maxa_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2480 maxa(D, fd, fs, ft);
2481 }
2482
max(SecondaryField fmt,FPURegister fd,FPURegister fs,FPURegister ft)2483 void Assembler::max(SecondaryField fmt, FPURegister fd, FPURegister fs,
2484 FPURegister ft) {
2485 DCHECK_EQ(kArchVariant, kMips64r6);
2486 DCHECK((fmt == D) || (fmt == S));
2487 GenInstrRegister(COP1, fmt, ft, fs, fd, MAX);
2488 }
2489
min(SecondaryField fmt,FPURegister fd,FPURegister fs,FPURegister ft)2490 void Assembler::min(SecondaryField fmt, FPURegister fd, FPURegister fs,
2491 FPURegister ft) {
2492 DCHECK_EQ(kArchVariant, kMips64r6);
2493 DCHECK((fmt == D) || (fmt == S));
2494 GenInstrRegister(COP1, fmt, ft, fs, fd, MIN);
2495 }
2496
2497 // GPR.
seleqz(Register rd,Register rs,Register rt)2498 void Assembler::seleqz(Register rd, Register rs, Register rt) {
2499 DCHECK_EQ(kArchVariant, kMips64r6);
2500 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S);
2501 }
2502
2503 // GPR.
selnez(Register rd,Register rs,Register rt)2504 void Assembler::selnez(Register rd, Register rs, Register rt) {
2505 DCHECK_EQ(kArchVariant, kMips64r6);
2506 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S);
2507 }
2508
2509 // Bit twiddling.
clz(Register rd,Register rs)2510 void Assembler::clz(Register rd, Register rs) {
2511 if (kArchVariant != kMips64r6) {
2512 // clz instr requires same GPR number in 'rd' and 'rt' fields.
2513 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ);
2514 } else {
2515 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6);
2516 }
2517 }
2518
dclz(Register rd,Register rs)2519 void Assembler::dclz(Register rd, Register rs) {
2520 if (kArchVariant != kMips64r6) {
2521 // dclz instr requires same GPR number in 'rd' and 'rt' fields.
2522 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, DCLZ);
2523 } else {
2524 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, DCLZ_R6);
2525 }
2526 }
2527
ins_(Register rt,Register rs,uint16_t pos,uint16_t size)2528 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2529 // Should be called via MacroAssembler::Ins.
2530 // ins instr has 'rt' field as dest, and two uint5: msb, lsb.
2531 DCHECK((kArchVariant == kMips64r2) || (kArchVariant == kMips64r6));
2532 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS);
2533 }
2534
dins_(Register rt,Register rs,uint16_t pos,uint16_t size)2535 void Assembler::dins_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2536 // Should be called via MacroAssembler::Dins.
2537 // dins instr has 'rt' field as dest, and two uint5: msb, lsb.
2538 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2539 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, DINS);
2540 }
2541
dinsm_(Register rt,Register rs,uint16_t pos,uint16_t size)2542 void Assembler::dinsm_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2543 // Should be called via MacroAssembler::Dins.
2544 // dinsm instr has 'rt' field as dest, and two uint5: msbminus32, lsb.
2545 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2546 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1 - 32, pos, DINSM);
2547 }
2548
dinsu_(Register rt,Register rs,uint16_t pos,uint16_t size)2549 void Assembler::dinsu_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2550 // Should be called via MacroAssembler::Dins.
2551 // dinsu instr has 'rt' field as dest, and two uint5: msbminus32, lsbminus32.
2552 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2553 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1 - 32, pos - 32, DINSU);
2554 }
2555
ext_(Register rt,Register rs,uint16_t pos,uint16_t size)2556 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2557 // Should be called via MacroAssembler::Ext.
2558 // ext instr has 'rt' field as dest, and two uint5: msbd, lsb.
2559 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2560 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT);
2561 }
2562
dext_(Register rt,Register rs,uint16_t pos,uint16_t size)2563 void Assembler::dext_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2564 // Should be called via MacroAssembler::Dext.
2565 // dext instr has 'rt' field as dest, and two uint5: msbd, lsb.
2566 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2567 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, DEXT);
2568 }
2569
dextm_(Register rt,Register rs,uint16_t pos,uint16_t size)2570 void Assembler::dextm_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2571 // Should be called via MacroAssembler::Dextm.
2572 // dextm instr has 'rt' field as dest, and two uint5: msbdminus32, lsb.
2573 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2574 GenInstrRegister(SPECIAL3, rs, rt, size - 1 - 32, pos, DEXTM);
2575 }
2576
dextu_(Register rt,Register rs,uint16_t pos,uint16_t size)2577 void Assembler::dextu_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2578 // Should be called via MacroAssembler::Dextu.
2579 // dextu instr has 'rt' field as dest, and two uint5: msbd, lsbminus32.
2580 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2581 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos - 32, DEXTU);
2582 }
2583
bitswap(Register rd,Register rt)2584 void Assembler::bitswap(Register rd, Register rt) {
2585 DCHECK_EQ(kArchVariant, kMips64r6);
2586 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, BSHFL);
2587 }
2588
dbitswap(Register rd,Register rt)2589 void Assembler::dbitswap(Register rd, Register rt) {
2590 DCHECK_EQ(kArchVariant, kMips64r6);
2591 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, DBSHFL);
2592 }
2593
pref(int32_t hint,const MemOperand & rs)2594 void Assembler::pref(int32_t hint, const MemOperand& rs) {
2595 DCHECK(is_uint5(hint) && is_uint16(rs.offset_));
2596 Instr instr =
2597 PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) | (rs.offset_);
2598 emit(instr);
2599 }
2600
align(Register rd,Register rs,Register rt,uint8_t bp)2601 void Assembler::align(Register rd, Register rs, Register rt, uint8_t bp) {
2602 DCHECK_EQ(kArchVariant, kMips64r6);
2603 DCHECK(is_uint3(bp));
2604 uint16_t sa = (ALIGN << kBp2Bits) | bp;
2605 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, BSHFL);
2606 }
2607
dalign(Register rd,Register rs,Register rt,uint8_t bp)2608 void Assembler::dalign(Register rd, Register rs, Register rt, uint8_t bp) {
2609 DCHECK_EQ(kArchVariant, kMips64r6);
2610 DCHECK(is_uint3(bp));
2611 uint16_t sa = (DALIGN << kBp3Bits) | bp;
2612 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, DBSHFL);
2613 }
2614
wsbh(Register rd,Register rt)2615 void Assembler::wsbh(Register rd, Register rt) {
2616 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2617 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, WSBH, BSHFL);
2618 }
2619
dsbh(Register rd,Register rt)2620 void Assembler::dsbh(Register rd, Register rt) {
2621 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2622 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, DSBH, DBSHFL);
2623 }
2624
dshd(Register rd,Register rt)2625 void Assembler::dshd(Register rd, Register rt) {
2626 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2627 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, DSHD, DBSHFL);
2628 }
2629
seh(Register rd,Register rt)2630 void Assembler::seh(Register rd, Register rt) {
2631 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2632 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEH, BSHFL);
2633 }
2634
seb(Register rd,Register rt)2635 void Assembler::seb(Register rd, Register rt) {
2636 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2637 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEB, BSHFL);
2638 }
2639
2640 // --------Coprocessor-instructions----------------
2641
2642 // Load, store, move.
lwc1(FPURegister fd,const MemOperand & src)2643 void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
2644 GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
2645 }
2646
ldc1(FPURegister fd,const MemOperand & src)2647 void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
2648 GenInstrImmediate(LDC1, src.rm(), fd, src.offset_);
2649 }
2650
swc1(FPURegister fs,const MemOperand & src)2651 void Assembler::swc1(FPURegister fs, const MemOperand& src) {
2652 GenInstrImmediate(SWC1, src.rm(), fs, src.offset_);
2653 }
2654
sdc1(FPURegister fs,const MemOperand & src)2655 void Assembler::sdc1(FPURegister fs, const MemOperand& src) {
2656 GenInstrImmediate(SDC1, src.rm(), fs, src.offset_);
2657 }
2658
mtc1(Register rt,FPURegister fs)2659 void Assembler::mtc1(Register rt, FPURegister fs) {
2660 GenInstrRegister(COP1, MTC1, rt, fs, f0);
2661 }
2662
mthc1(Register rt,FPURegister fs)2663 void Assembler::mthc1(Register rt, FPURegister fs) {
2664 GenInstrRegister(COP1, MTHC1, rt, fs, f0);
2665 }
2666
dmtc1(Register rt,FPURegister fs)2667 void Assembler::dmtc1(Register rt, FPURegister fs) {
2668 GenInstrRegister(COP1, DMTC1, rt, fs, f0);
2669 }
2670
mfc1(Register rt,FPURegister fs)2671 void Assembler::mfc1(Register rt, FPURegister fs) {
2672 GenInstrRegister(COP1, MFC1, rt, fs, f0);
2673 }
2674
mfhc1(Register rt,FPURegister fs)2675 void Assembler::mfhc1(Register rt, FPURegister fs) {
2676 GenInstrRegister(COP1, MFHC1, rt, fs, f0);
2677 }
2678
dmfc1(Register rt,FPURegister fs)2679 void Assembler::dmfc1(Register rt, FPURegister fs) {
2680 GenInstrRegister(COP1, DMFC1, rt, fs, f0);
2681 }
2682
ctc1(Register rt,FPUControlRegister fs)2683 void Assembler::ctc1(Register rt, FPUControlRegister fs) {
2684 GenInstrRegister(COP1, CTC1, rt, fs);
2685 }
2686
cfc1(Register rt,FPUControlRegister fs)2687 void Assembler::cfc1(Register rt, FPUControlRegister fs) {
2688 GenInstrRegister(COP1, CFC1, rt, fs);
2689 }
2690
sel(SecondaryField fmt,FPURegister fd,FPURegister fs,FPURegister ft)2691 void Assembler::sel(SecondaryField fmt, FPURegister fd, FPURegister fs,
2692 FPURegister ft) {
2693 DCHECK_EQ(kArchVariant, kMips64r6);
2694 DCHECK((fmt == D) || (fmt == S));
2695
2696 GenInstrRegister(COP1, fmt, ft, fs, fd, SEL);
2697 }
2698
sel_s(FPURegister fd,FPURegister fs,FPURegister ft)2699 void Assembler::sel_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2700 sel(S, fd, fs, ft);
2701 }
2702
sel_d(FPURegister fd,FPURegister fs,FPURegister ft)2703 void Assembler::sel_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2704 sel(D, fd, fs, ft);
2705 }
2706
2707 // FPR.
seleqz(SecondaryField fmt,FPURegister fd,FPURegister fs,FPURegister ft)2708 void Assembler::seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs,
2709 FPURegister ft) {
2710 DCHECK((fmt == D) || (fmt == S));
2711 GenInstrRegister(COP1, fmt, ft, fs, fd, SELEQZ_C);
2712 }
2713
seleqz_d(FPURegister fd,FPURegister fs,FPURegister ft)2714 void Assembler::seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2715 seleqz(D, fd, fs, ft);
2716 }
2717
seleqz_s(FPURegister fd,FPURegister fs,FPURegister ft)2718 void Assembler::seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2719 seleqz(S, fd, fs, ft);
2720 }
2721
selnez_d(FPURegister fd,FPURegister fs,FPURegister ft)2722 void Assembler::selnez_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2723 selnez(D, fd, fs, ft);
2724 }
2725
selnez_s(FPURegister fd,FPURegister fs,FPURegister ft)2726 void Assembler::selnez_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2727 selnez(S, fd, fs, ft);
2728 }
2729
movz_s(FPURegister fd,FPURegister fs,Register rt)2730 void Assembler::movz_s(FPURegister fd, FPURegister fs, Register rt) {
2731 DCHECK_EQ(kArchVariant, kMips64r2);
2732 GenInstrRegister(COP1, S, rt, fs, fd, MOVZ_C);
2733 }
2734
movz_d(FPURegister fd,FPURegister fs,Register rt)2735 void Assembler::movz_d(FPURegister fd, FPURegister fs, Register rt) {
2736 DCHECK_EQ(kArchVariant, kMips64r2);
2737 GenInstrRegister(COP1, D, rt, fs, fd, MOVZ_C);
2738 }
2739
movt_s(FPURegister fd,FPURegister fs,uint16_t cc)2740 void Assembler::movt_s(FPURegister fd, FPURegister fs, uint16_t cc) {
2741 DCHECK_EQ(kArchVariant, kMips64r2);
2742 FPURegister ft = FPURegister::from_code((cc & 0x0007) << 2 | 1);
2743 GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
2744 }
2745
movt_d(FPURegister fd,FPURegister fs,uint16_t cc)2746 void Assembler::movt_d(FPURegister fd, FPURegister fs, uint16_t cc) {
2747 DCHECK_EQ(kArchVariant, kMips64r2);
2748 FPURegister ft = FPURegister::from_code((cc & 0x0007) << 2 | 1);
2749 GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
2750 }
2751
movf_s(FPURegister fd,FPURegister fs,uint16_t cc)2752 void Assembler::movf_s(FPURegister fd, FPURegister fs, uint16_t cc) {
2753 DCHECK_EQ(kArchVariant, kMips64r2);
2754 FPURegister ft = FPURegister::from_code((cc & 0x0007) << 2 | 0);
2755 GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
2756 }
2757
movf_d(FPURegister fd,FPURegister fs,uint16_t cc)2758 void Assembler::movf_d(FPURegister fd, FPURegister fs, uint16_t cc) {
2759 DCHECK_EQ(kArchVariant, kMips64r2);
2760 FPURegister ft = FPURegister::from_code((cc & 0x0007) << 2 | 0);
2761 GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
2762 }
2763
movn_s(FPURegister fd,FPURegister fs,Register rt)2764 void Assembler::movn_s(FPURegister fd, FPURegister fs, Register rt) {
2765 DCHECK_EQ(kArchVariant, kMips64r2);
2766 GenInstrRegister(COP1, S, rt, fs, fd, MOVN_C);
2767 }
2768
movn_d(FPURegister fd,FPURegister fs,Register rt)2769 void Assembler::movn_d(FPURegister fd, FPURegister fs, Register rt) {
2770 DCHECK_EQ(kArchVariant, kMips64r2);
2771 GenInstrRegister(COP1, D, rt, fs, fd, MOVN_C);
2772 }
2773
2774 // FPR.
selnez(SecondaryField fmt,FPURegister fd,FPURegister fs,FPURegister ft)2775 void Assembler::selnez(SecondaryField fmt, FPURegister fd, FPURegister fs,
2776 FPURegister ft) {
2777 DCHECK_EQ(kArchVariant, kMips64r6);
2778 DCHECK((fmt == D) || (fmt == S));
2779 GenInstrRegister(COP1, fmt, ft, fs, fd, SELNEZ_C);
2780 }
2781
2782 // Arithmetic.
2783
add_s(FPURegister fd,FPURegister fs,FPURegister ft)2784 void Assembler::add_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2785 GenInstrRegister(COP1, S, ft, fs, fd, ADD_D);
2786 }
2787
add_d(FPURegister fd,FPURegister fs,FPURegister ft)2788 void Assembler::add_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2789 GenInstrRegister(COP1, D, ft, fs, fd, ADD_D);
2790 }
2791
sub_s(FPURegister fd,FPURegister fs,FPURegister ft)2792 void Assembler::sub_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2793 GenInstrRegister(COP1, S, ft, fs, fd, SUB_D);
2794 }
2795
sub_d(FPURegister fd,FPURegister fs,FPURegister ft)2796 void Assembler::sub_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2797 GenInstrRegister(COP1, D, ft, fs, fd, SUB_D);
2798 }
2799
mul_s(FPURegister fd,FPURegister fs,FPURegister ft)2800 void Assembler::mul_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2801 GenInstrRegister(COP1, S, ft, fs, fd, MUL_D);
2802 }
2803
mul_d(FPURegister fd,FPURegister fs,FPURegister ft)2804 void Assembler::mul_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2805 GenInstrRegister(COP1, D, ft, fs, fd, MUL_D);
2806 }
2807
madd_s(FPURegister fd,FPURegister fr,FPURegister fs,FPURegister ft)2808 void Assembler::madd_s(FPURegister fd, FPURegister fr, FPURegister fs,
2809 FPURegister ft) {
2810 // On Loongson 3A (MIPS64R2), MADD.S instruction is actually fused MADD.S and
2811 // this causes failure in some of the tests. Since this optimization is rarely
2812 // used, and not used at all on MIPS64R6, this isntruction is removed.
2813 UNREACHABLE();
2814 }
2815
madd_d(FPURegister fd,FPURegister fr,FPURegister fs,FPURegister ft)2816 void Assembler::madd_d(FPURegister fd, FPURegister fr, FPURegister fs,
2817 FPURegister ft) {
2818 // On Loongson 3A (MIPS64R2), MADD.D instruction is actually fused MADD.D and
2819 // this causes failure in some of the tests. Since this optimization is rarely
2820 // used, and not used at all on MIPS64R6, this isntruction is removed.
2821 UNREACHABLE();
2822 }
2823
msub_s(FPURegister fd,FPURegister fr,FPURegister fs,FPURegister ft)2824 void Assembler::msub_s(FPURegister fd, FPURegister fr, FPURegister fs,
2825 FPURegister ft) {
2826 // See explanation for instruction madd_s.
2827 UNREACHABLE();
2828 }
2829
msub_d(FPURegister fd,FPURegister fr,FPURegister fs,FPURegister ft)2830 void Assembler::msub_d(FPURegister fd, FPURegister fr, FPURegister fs,
2831 FPURegister ft) {
2832 // See explanation for instruction madd_d.
2833 UNREACHABLE();
2834 }
2835
maddf_s(FPURegister fd,FPURegister fs,FPURegister ft)2836 void Assembler::maddf_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2837 DCHECK_EQ(kArchVariant, kMips64r6);
2838 GenInstrRegister(COP1, S, ft, fs, fd, MADDF_S);
2839 }
2840
maddf_d(FPURegister fd,FPURegister fs,FPURegister ft)2841 void Assembler::maddf_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2842 DCHECK_EQ(kArchVariant, kMips64r6);
2843 GenInstrRegister(COP1, D, ft, fs, fd, MADDF_D);
2844 }
2845
msubf_s(FPURegister fd,FPURegister fs,FPURegister ft)2846 void Assembler::msubf_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2847 DCHECK_EQ(kArchVariant, kMips64r6);
2848 GenInstrRegister(COP1, S, ft, fs, fd, MSUBF_S);
2849 }
2850
msubf_d(FPURegister fd,FPURegister fs,FPURegister ft)2851 void Assembler::msubf_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2852 DCHECK_EQ(kArchVariant, kMips64r6);
2853 GenInstrRegister(COP1, D, ft, fs, fd, MSUBF_D);
2854 }
2855
div_s(FPURegister fd,FPURegister fs,FPURegister ft)2856 void Assembler::div_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2857 GenInstrRegister(COP1, S, ft, fs, fd, DIV_D);
2858 }
2859
div_d(FPURegister fd,FPURegister fs,FPURegister ft)2860 void Assembler::div_d(FPURegister fd, FPURegister fs, FPURegister ft) {
2861 GenInstrRegister(COP1, D, ft, fs, fd, DIV_D);
2862 }
2863
abs_s(FPURegister fd,FPURegister fs)2864 void Assembler::abs_s(FPURegister fd, FPURegister fs) {
2865 GenInstrRegister(COP1, S, f0, fs, fd, ABS_D);
2866 }
2867
abs_d(FPURegister fd,FPURegister fs)2868 void Assembler::abs_d(FPURegister fd, FPURegister fs) {
2869 GenInstrRegister(COP1, D, f0, fs, fd, ABS_D);
2870 }
2871
mov_d(FPURegister fd,FPURegister fs)2872 void Assembler::mov_d(FPURegister fd, FPURegister fs) {
2873 GenInstrRegister(COP1, D, f0, fs, fd, MOV_D);
2874 }
2875
mov_s(FPURegister fd,FPURegister fs)2876 void Assembler::mov_s(FPURegister fd, FPURegister fs) {
2877 GenInstrRegister(COP1, S, f0, fs, fd, MOV_S);
2878 }
2879
neg_s(FPURegister fd,FPURegister fs)2880 void Assembler::neg_s(FPURegister fd, FPURegister fs) {
2881 GenInstrRegister(COP1, S, f0, fs, fd, NEG_D);
2882 }
2883
neg_d(FPURegister fd,FPURegister fs)2884 void Assembler::neg_d(FPURegister fd, FPURegister fs) {
2885 GenInstrRegister(COP1, D, f0, fs, fd, NEG_D);
2886 }
2887
sqrt_s(FPURegister fd,FPURegister fs)2888 void Assembler::sqrt_s(FPURegister fd, FPURegister fs) {
2889 GenInstrRegister(COP1, S, f0, fs, fd, SQRT_D);
2890 }
2891
sqrt_d(FPURegister fd,FPURegister fs)2892 void Assembler::sqrt_d(FPURegister fd, FPURegister fs) {
2893 GenInstrRegister(COP1, D, f0, fs, fd, SQRT_D);
2894 }
2895
rsqrt_s(FPURegister fd,FPURegister fs)2896 void Assembler::rsqrt_s(FPURegister fd, FPURegister fs) {
2897 GenInstrRegister(COP1, S, f0, fs, fd, RSQRT_S);
2898 }
2899
rsqrt_d(FPURegister fd,FPURegister fs)2900 void Assembler::rsqrt_d(FPURegister fd, FPURegister fs) {
2901 GenInstrRegister(COP1, D, f0, fs, fd, RSQRT_D);
2902 }
2903
recip_d(FPURegister fd,FPURegister fs)2904 void Assembler::recip_d(FPURegister fd, FPURegister fs) {
2905 GenInstrRegister(COP1, D, f0, fs, fd, RECIP_D);
2906 }
2907
recip_s(FPURegister fd,FPURegister fs)2908 void Assembler::recip_s(FPURegister fd, FPURegister fs) {
2909 GenInstrRegister(COP1, S, f0, fs, fd, RECIP_S);
2910 }
2911
2912 // Conversions.
cvt_w_s(FPURegister fd,FPURegister fs)2913 void Assembler::cvt_w_s(FPURegister fd, FPURegister fs) {
2914 GenInstrRegister(COP1, S, f0, fs, fd, CVT_W_S);
2915 }
2916
cvt_w_d(FPURegister fd,FPURegister fs)2917 void Assembler::cvt_w_d(FPURegister fd, FPURegister fs) {
2918 GenInstrRegister(COP1, D, f0, fs, fd, CVT_W_D);
2919 }
2920
trunc_w_s(FPURegister fd,FPURegister fs)2921 void Assembler::trunc_w_s(FPURegister fd, FPURegister fs) {
2922 GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_W_S);
2923 }
2924
trunc_w_d(FPURegister fd,FPURegister fs)2925 void Assembler::trunc_w_d(FPURegister fd, FPURegister fs) {
2926 GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_W_D);
2927 }
2928
round_w_s(FPURegister fd,FPURegister fs)2929 void Assembler::round_w_s(FPURegister fd, FPURegister fs) {
2930 GenInstrRegister(COP1, S, f0, fs, fd, ROUND_W_S);
2931 }
2932
round_w_d(FPURegister fd,FPURegister fs)2933 void Assembler::round_w_d(FPURegister fd, FPURegister fs) {
2934 GenInstrRegister(COP1, D, f0, fs, fd, ROUND_W_D);
2935 }
2936
floor_w_s(FPURegister fd,FPURegister fs)2937 void Assembler::floor_w_s(FPURegister fd, FPURegister fs) {
2938 GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_W_S);
2939 }
2940
floor_w_d(FPURegister fd,FPURegister fs)2941 void Assembler::floor_w_d(FPURegister fd, FPURegister fs) {
2942 GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_W_D);
2943 }
2944
ceil_w_s(FPURegister fd,FPURegister fs)2945 void Assembler::ceil_w_s(FPURegister fd, FPURegister fs) {
2946 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S);
2947 }
2948
ceil_w_d(FPURegister fd,FPURegister fs)2949 void Assembler::ceil_w_d(FPURegister fd, FPURegister fs) {
2950 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_W_D);
2951 }
2952
rint_s(FPURegister fd,FPURegister fs)2953 void Assembler::rint_s(FPURegister fd, FPURegister fs) { rint(S, fd, fs); }
2954
rint_d(FPURegister fd,FPURegister fs)2955 void Assembler::rint_d(FPURegister fd, FPURegister fs) { rint(D, fd, fs); }
2956
rint(SecondaryField fmt,FPURegister fd,FPURegister fs)2957 void Assembler::rint(SecondaryField fmt, FPURegister fd, FPURegister fs) {
2958 DCHECK_EQ(kArchVariant, kMips64r6);
2959 GenInstrRegister(COP1, fmt, f0, fs, fd, RINT);
2960 }
2961
cvt_l_s(FPURegister fd,FPURegister fs)2962 void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) {
2963 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2964 GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S);
2965 }
2966
cvt_l_d(FPURegister fd,FPURegister fs)2967 void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) {
2968 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2969 GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D);
2970 }
2971
trunc_l_s(FPURegister fd,FPURegister fs)2972 void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) {
2973 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2974 GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S);
2975 }
2976
trunc_l_d(FPURegister fd,FPURegister fs)2977 void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) {
2978 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
2979 GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D);
2980 }
2981
round_l_s(FPURegister fd,FPURegister fs)2982 void Assembler::round_l_s(FPURegister fd, FPURegister fs) {
2983 GenInstrRegister(COP1, S, f0, fs, fd, ROUND_L_S);
2984 }
2985
round_l_d(FPURegister fd,FPURegister fs)2986 void Assembler::round_l_d(FPURegister fd, FPURegister fs) {
2987 GenInstrRegister(COP1, D, f0, fs, fd, ROUND_L_D);
2988 }
2989
floor_l_s(FPURegister fd,FPURegister fs)2990 void Assembler::floor_l_s(FPURegister fd, FPURegister fs) {
2991 GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_L_S);
2992 }
2993
floor_l_d(FPURegister fd,FPURegister fs)2994 void Assembler::floor_l_d(FPURegister fd, FPURegister fs) {
2995 GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_L_D);
2996 }
2997
ceil_l_s(FPURegister fd,FPURegister fs)2998 void Assembler::ceil_l_s(FPURegister fd, FPURegister fs) {
2999 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_L_S);
3000 }
3001
ceil_l_d(FPURegister fd,FPURegister fs)3002 void Assembler::ceil_l_d(FPURegister fd, FPURegister fs) {
3003 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D);
3004 }
3005
class_s(FPURegister fd,FPURegister fs)3006 void Assembler::class_s(FPURegister fd, FPURegister fs) {
3007 DCHECK_EQ(kArchVariant, kMips64r6);
3008 GenInstrRegister(COP1, S, f0, fs, fd, CLASS_S);
3009 }
3010
class_d(FPURegister fd,FPURegister fs)3011 void Assembler::class_d(FPURegister fd, FPURegister fs) {
3012 DCHECK_EQ(kArchVariant, kMips64r6);
3013 GenInstrRegister(COP1, D, f0, fs, fd, CLASS_D);
3014 }
3015
mina(SecondaryField fmt,FPURegister fd,FPURegister fs,FPURegister ft)3016 void Assembler::mina(SecondaryField fmt, FPURegister fd, FPURegister fs,
3017 FPURegister ft) {
3018 DCHECK_EQ(kArchVariant, kMips64r6);
3019 DCHECK((fmt == D) || (fmt == S));
3020 GenInstrRegister(COP1, fmt, ft, fs, fd, MINA);
3021 }
3022
maxa(SecondaryField fmt,FPURegister fd,FPURegister fs,FPURegister ft)3023 void Assembler::maxa(SecondaryField fmt, FPURegister fd, FPURegister fs,
3024 FPURegister ft) {
3025 DCHECK_EQ(kArchVariant, kMips64r6);
3026 DCHECK((fmt == D) || (fmt == S));
3027 GenInstrRegister(COP1, fmt, ft, fs, fd, MAXA);
3028 }
3029
cvt_s_w(FPURegister fd,FPURegister fs)3030 void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) {
3031 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W);
3032 }
3033
cvt_s_l(FPURegister fd,FPURegister fs)3034 void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) {
3035 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
3036 GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L);
3037 }
3038
cvt_s_d(FPURegister fd,FPURegister fs)3039 void Assembler::cvt_s_d(FPURegister fd, FPURegister fs) {
3040 GenInstrRegister(COP1, D, f0, fs, fd, CVT_S_D);
3041 }
3042
cvt_d_w(FPURegister fd,FPURegister fs)3043 void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) {
3044 GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W);
3045 }
3046
cvt_d_l(FPURegister fd,FPURegister fs)3047 void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) {
3048 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6);
3049 GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L);
3050 }
3051
cvt_d_s(FPURegister fd,FPURegister fs)3052 void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) {
3053 GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S);
3054 }
3055
3056 // Conditions for >= MIPSr6.
cmp(FPUCondition cond,SecondaryField fmt,FPURegister fd,FPURegister fs,FPURegister ft)3057 void Assembler::cmp(FPUCondition cond, SecondaryField fmt, FPURegister fd,
3058 FPURegister fs, FPURegister ft) {
3059 DCHECK_EQ(kArchVariant, kMips64r6);
3060 DCHECK_EQ(fmt & ~(31 << kRsShift), 0);
3061 Instr instr = COP1 | fmt | ft.code() << kFtShift | fs.code() << kFsShift |
3062 fd.code() << kFdShift | (0 << 5) | cond;
3063 emit(instr);
3064 }
3065
cmp_s(FPUCondition cond,FPURegister fd,FPURegister fs,FPURegister ft)3066 void Assembler::cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs,
3067 FPURegister ft) {
3068 cmp(cond, W, fd, fs, ft);
3069 }
3070
cmp_d(FPUCondition cond,FPURegister fd,FPURegister fs,FPURegister ft)3071 void Assembler::cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs,
3072 FPURegister ft) {
3073 cmp(cond, L, fd, fs, ft);
3074 }
3075
bc1eqz(int16_t offset,FPURegister ft)3076 void Assembler::bc1eqz(int16_t offset, FPURegister ft) {
3077 DCHECK_EQ(kArchVariant, kMips64r6);
3078 BlockTrampolinePoolScope block_trampoline_pool(this);
3079 Instr instr = COP1 | BC1EQZ | ft.code() << kFtShift | (offset & kImm16Mask);
3080 emit(instr);
3081 BlockTrampolinePoolFor(1); // For associated delay slot.
3082 }
3083
bc1nez(int16_t offset,FPURegister ft)3084 void Assembler::bc1nez(int16_t offset, FPURegister ft) {
3085 DCHECK_EQ(kArchVariant, kMips64r6);
3086 BlockTrampolinePoolScope block_trampoline_pool(this);
3087 Instr instr = COP1 | BC1NEZ | ft.code() << kFtShift | (offset & kImm16Mask);
3088 emit(instr);
3089 BlockTrampolinePoolFor(1); // For associated delay slot.
3090 }
3091
3092 // Conditions for < MIPSr6.
c(FPUCondition cond,SecondaryField fmt,FPURegister fs,FPURegister ft,uint16_t cc)3093 void Assembler::c(FPUCondition cond, SecondaryField fmt, FPURegister fs,
3094 FPURegister ft, uint16_t cc) {
3095 DCHECK_NE(kArchVariant, kMips64r6);
3096 DCHECK(is_uint3(cc));
3097 DCHECK(fmt == S || fmt == D);
3098 DCHECK_EQ(fmt & ~(31 << kRsShift), 0);
3099 Instr instr = COP1 | fmt | ft.code() << kFtShift | fs.code() << kFsShift |
3100 cc << 8 | 3 << 4 | cond;
3101 emit(instr);
3102 }
3103
c_s(FPUCondition cond,FPURegister fs,FPURegister ft,uint16_t cc)3104 void Assembler::c_s(FPUCondition cond, FPURegister fs, FPURegister ft,
3105 uint16_t cc) {
3106 c(cond, S, fs, ft, cc);
3107 }
3108
c_d(FPUCondition cond,FPURegister fs,FPURegister ft,uint16_t cc)3109 void Assembler::c_d(FPUCondition cond, FPURegister fs, FPURegister ft,
3110 uint16_t cc) {
3111 c(cond, D, fs, ft, cc);
3112 }
3113
fcmp(FPURegister src1,const double src2,FPUCondition cond)3114 void Assembler::fcmp(FPURegister src1, const double src2, FPUCondition cond) {
3115 DCHECK_EQ(src2, 0.0);
3116 mtc1(zero_reg, f14);
3117 cvt_d_w(f14, f14);
3118 c(cond, D, src1, f14, 0);
3119 }
3120
bc1f(int16_t offset,uint16_t cc)3121 void Assembler::bc1f(int16_t offset, uint16_t cc) {
3122 BlockTrampolinePoolScope block_trampoline_pool(this);
3123 DCHECK(is_uint3(cc));
3124 Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask);
3125 emit(instr);
3126 BlockTrampolinePoolFor(1); // For associated delay slot.
3127 }
3128
bc1t(int16_t offset,uint16_t cc)3129 void Assembler::bc1t(int16_t offset, uint16_t cc) {
3130 BlockTrampolinePoolScope block_trampoline_pool(this);
3131 DCHECK(is_uint3(cc));
3132 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask);
3133 emit(instr);
3134 BlockTrampolinePoolFor(1); // For associated delay slot.
3135 }
3136
3137 // ---------- MSA instructions ------------
3138 #define MSA_BRANCH_LIST(V) \
3139 V(bz_v, BZ_V) \
3140 V(bz_b, BZ_B) \
3141 V(bz_h, BZ_H) \
3142 V(bz_w, BZ_W) \
3143 V(bz_d, BZ_D) \
3144 V(bnz_v, BNZ_V) \
3145 V(bnz_b, BNZ_B) \
3146 V(bnz_h, BNZ_H) \
3147 V(bnz_w, BNZ_W) \
3148 V(bnz_d, BNZ_D)
3149
3150 #define MSA_BRANCH(name, opcode) \
3151 void Assembler::name(MSARegister wt, int16_t offset) { \
3152 GenInstrMsaBranch(opcode, wt, offset); \
3153 }
3154
3155 MSA_BRANCH_LIST(MSA_BRANCH)
3156 #undef MSA_BRANCH
3157 #undef MSA_BRANCH_LIST
3158
3159 #define MSA_LD_ST_LIST(V) \
3160 V(ld_b, LD_B) \
3161 V(ld_h, LD_H) \
3162 V(ld_w, LD_W) \
3163 V(ld_d, LD_D) \
3164 V(st_b, ST_B) \
3165 V(st_h, ST_H) \
3166 V(st_w, ST_W) \
3167 V(st_d, ST_D)
3168
3169 #define MSA_LD_ST(name, opcode) \
3170 void Assembler::name(MSARegister wd, const MemOperand& rs) { \
3171 MemOperand source = rs; \
3172 AdjustBaseAndOffset(&source); \
3173 if (is_int10(source.offset())) { \
3174 GenInstrMsaMI10(opcode, source.offset(), source.rm(), wd); \
3175 } else { \
3176 UseScratchRegisterScope temps(this); \
3177 Register scratch = temps.Acquire(); \
3178 DCHECK(rs.rm() != scratch); \
3179 daddiu(scratch, source.rm(), source.offset()); \
3180 GenInstrMsaMI10(opcode, 0, scratch, wd); \
3181 } \
3182 }
3183
MSA_LD_ST_LIST(MSA_LD_ST)3184 MSA_LD_ST_LIST(MSA_LD_ST)
3185 #undef MSA_LD_ST
3186 #undef MSA_LD_ST_LIST
3187
3188 #define MSA_I10_LIST(V) \
3189 V(ldi_b, I5_DF_b) \
3190 V(ldi_h, I5_DF_h) \
3191 V(ldi_w, I5_DF_w) \
3192 V(ldi_d, I5_DF_d)
3193
3194 #define MSA_I10(name, format) \
3195 void Assembler::name(MSARegister wd, int32_t imm10) { \
3196 GenInstrMsaI10(LDI, format, imm10, wd); \
3197 }
3198 MSA_I10_LIST(MSA_I10)
3199 #undef MSA_I10
3200 #undef MSA_I10_LIST
3201
3202 #define MSA_I5_LIST(V) \
3203 V(addvi, ADDVI) \
3204 V(subvi, SUBVI) \
3205 V(maxi_s, MAXI_S) \
3206 V(maxi_u, MAXI_U) \
3207 V(mini_s, MINI_S) \
3208 V(mini_u, MINI_U) \
3209 V(ceqi, CEQI) \
3210 V(clti_s, CLTI_S) \
3211 V(clti_u, CLTI_U) \
3212 V(clei_s, CLEI_S) \
3213 V(clei_u, CLEI_U)
3214
3215 #define MSA_I5_FORMAT(name, opcode, format) \
3216 void Assembler::name##_##format(MSARegister wd, MSARegister ws, \
3217 uint32_t imm5) { \
3218 GenInstrMsaI5(opcode, I5_DF_##format, imm5, ws, wd); \
3219 }
3220
3221 #define MSA_I5(name, opcode) \
3222 MSA_I5_FORMAT(name, opcode, b) \
3223 MSA_I5_FORMAT(name, opcode, h) \
3224 MSA_I5_FORMAT(name, opcode, w) \
3225 MSA_I5_FORMAT(name, opcode, d)
3226
3227 MSA_I5_LIST(MSA_I5)
3228 #undef MSA_I5
3229 #undef MSA_I5_FORMAT
3230 #undef MSA_I5_LIST
3231
3232 #define MSA_I8_LIST(V) \
3233 V(andi_b, ANDI_B) \
3234 V(ori_b, ORI_B) \
3235 V(nori_b, NORI_B) \
3236 V(xori_b, XORI_B) \
3237 V(bmnzi_b, BMNZI_B) \
3238 V(bmzi_b, BMZI_B) \
3239 V(bseli_b, BSELI_B) \
3240 V(shf_b, SHF_B) \
3241 V(shf_h, SHF_H) \
3242 V(shf_w, SHF_W)
3243
3244 #define MSA_I8(name, opcode) \
3245 void Assembler::name(MSARegister wd, MSARegister ws, uint32_t imm8) { \
3246 GenInstrMsaI8(opcode, imm8, ws, wd); \
3247 }
3248
3249 MSA_I8_LIST(MSA_I8)
3250 #undef MSA_I8
3251 #undef MSA_I8_LIST
3252
3253 #define MSA_VEC_LIST(V) \
3254 V(and_v, AND_V) \
3255 V(or_v, OR_V) \
3256 V(nor_v, NOR_V) \
3257 V(xor_v, XOR_V) \
3258 V(bmnz_v, BMNZ_V) \
3259 V(bmz_v, BMZ_V) \
3260 V(bsel_v, BSEL_V)
3261
3262 #define MSA_VEC(name, opcode) \
3263 void Assembler::name(MSARegister wd, MSARegister ws, MSARegister wt) { \
3264 GenInstrMsaVec(opcode, wt, ws, wd); \
3265 }
3266
3267 MSA_VEC_LIST(MSA_VEC)
3268 #undef MSA_VEC
3269 #undef MSA_VEC_LIST
3270
3271 #define MSA_2R_LIST(V) \
3272 V(pcnt, PCNT) \
3273 V(nloc, NLOC) \
3274 V(nlzc, NLZC)
3275
3276 #define MSA_2R_FORMAT(name, opcode, format) \
3277 void Assembler::name##_##format(MSARegister wd, MSARegister ws) { \
3278 GenInstrMsa2R(opcode, MSA_2R_DF_##format, ws, wd); \
3279 }
3280
3281 #define MSA_2R(name, opcode) \
3282 MSA_2R_FORMAT(name, opcode, b) \
3283 MSA_2R_FORMAT(name, opcode, h) \
3284 MSA_2R_FORMAT(name, opcode, w) \
3285 MSA_2R_FORMAT(name, opcode, d)
3286
3287 MSA_2R_LIST(MSA_2R)
3288 #undef MSA_2R
3289 #undef MSA_2R_FORMAT
3290 #undef MSA_2R_LIST
3291
3292 #define MSA_FILL(format) \
3293 void Assembler::fill_##format(MSARegister wd, Register rs) { \
3294 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD)); \
3295 DCHECK(rs.is_valid() && wd.is_valid()); \
3296 Instr instr = MSA | MSA_2R_FORMAT | FILL | MSA_2R_DF_##format | \
3297 (rs.code() << kWsShift) | (wd.code() << kWdShift) | \
3298 MSA_VEC_2R_2RF_MINOR; \
3299 emit(instr); \
3300 }
3301
3302 MSA_FILL(b)
3303 MSA_FILL(h)
3304 MSA_FILL(w)
3305 MSA_FILL(d)
3306 #undef MSA_FILL
3307
3308 #define MSA_2RF_LIST(V) \
3309 V(fclass, FCLASS) \
3310 V(ftrunc_s, FTRUNC_S) \
3311 V(ftrunc_u, FTRUNC_U) \
3312 V(fsqrt, FSQRT) \
3313 V(frsqrt, FRSQRT) \
3314 V(frcp, FRCP) \
3315 V(frint, FRINT) \
3316 V(flog2, FLOG2) \
3317 V(fexupl, FEXUPL) \
3318 V(fexupr, FEXUPR) \
3319 V(ffql, FFQL) \
3320 V(ffqr, FFQR) \
3321 V(ftint_s, FTINT_S) \
3322 V(ftint_u, FTINT_U) \
3323 V(ffint_s, FFINT_S) \
3324 V(ffint_u, FFINT_U)
3325
3326 #define MSA_2RF_FORMAT(name, opcode, format) \
3327 void Assembler::name##_##format(MSARegister wd, MSARegister ws) { \
3328 GenInstrMsa2RF(opcode, MSA_2RF_DF_##format, ws, wd); \
3329 }
3330
3331 #define MSA_2RF(name, opcode) \
3332 MSA_2RF_FORMAT(name, opcode, w) \
3333 MSA_2RF_FORMAT(name, opcode, d)
3334
3335 MSA_2RF_LIST(MSA_2RF)
3336 #undef MSA_2RF
3337 #undef MSA_2RF_FORMAT
3338 #undef MSA_2RF_LIST
3339
3340 #define MSA_3R_LIST(V) \
3341 V(sll, SLL_MSA) \
3342 V(sra, SRA_MSA) \
3343 V(srl, SRL_MSA) \
3344 V(bclr, BCLR) \
3345 V(bset, BSET) \
3346 V(bneg, BNEG) \
3347 V(binsl, BINSL) \
3348 V(binsr, BINSR) \
3349 V(addv, ADDV) \
3350 V(subv, SUBV) \
3351 V(max_s, MAX_S) \
3352 V(max_u, MAX_U) \
3353 V(min_s, MIN_S) \
3354 V(min_u, MIN_U) \
3355 V(max_a, MAX_A) \
3356 V(min_a, MIN_A) \
3357 V(ceq, CEQ) \
3358 V(clt_s, CLT_S) \
3359 V(clt_u, CLT_U) \
3360 V(cle_s, CLE_S) \
3361 V(cle_u, CLE_U) \
3362 V(add_a, ADD_A) \
3363 V(adds_a, ADDS_A) \
3364 V(adds_s, ADDS_S) \
3365 V(adds_u, ADDS_U) \
3366 V(ave_s, AVE_S) \
3367 V(ave_u, AVE_U) \
3368 V(aver_s, AVER_S) \
3369 V(aver_u, AVER_U) \
3370 V(subs_s, SUBS_S) \
3371 V(subs_u, SUBS_U) \
3372 V(subsus_u, SUBSUS_U) \
3373 V(subsuu_s, SUBSUU_S) \
3374 V(asub_s, ASUB_S) \
3375 V(asub_u, ASUB_U) \
3376 V(mulv, MULV) \
3377 V(maddv, MADDV) \
3378 V(msubv, MSUBV) \
3379 V(div_s, DIV_S_MSA) \
3380 V(div_u, DIV_U) \
3381 V(mod_s, MOD_S) \
3382 V(mod_u, MOD_U) \
3383 V(dotp_s, DOTP_S) \
3384 V(dotp_u, DOTP_U) \
3385 V(dpadd_s, DPADD_S) \
3386 V(dpadd_u, DPADD_U) \
3387 V(dpsub_s, DPSUB_S) \
3388 V(dpsub_u, DPSUB_U) \
3389 V(pckev, PCKEV) \
3390 V(pckod, PCKOD) \
3391 V(ilvl, ILVL) \
3392 V(ilvr, ILVR) \
3393 V(ilvev, ILVEV) \
3394 V(ilvod, ILVOD) \
3395 V(vshf, VSHF) \
3396 V(srar, SRAR) \
3397 V(srlr, SRLR) \
3398 V(hadd_s, HADD_S) \
3399 V(hadd_u, HADD_U) \
3400 V(hsub_s, HSUB_S) \
3401 V(hsub_u, HSUB_U)
3402
3403 #define MSA_3R_FORMAT(name, opcode, format) \
3404 void Assembler::name##_##format(MSARegister wd, MSARegister ws, \
3405 MSARegister wt) { \
3406 GenInstrMsa3R<MSARegister>(opcode, MSA_3R_DF_##format, wt, ws, wd); \
3407 }
3408
3409 #define MSA_3R_FORMAT_SLD_SPLAT(name, opcode, format) \
3410 void Assembler::name##_##format(MSARegister wd, MSARegister ws, \
3411 Register rt) { \
3412 GenInstrMsa3R<Register>(opcode, MSA_3R_DF_##format, rt, ws, wd); \
3413 }
3414
3415 #define MSA_3R(name, opcode) \
3416 MSA_3R_FORMAT(name, opcode, b) \
3417 MSA_3R_FORMAT(name, opcode, h) \
3418 MSA_3R_FORMAT(name, opcode, w) \
3419 MSA_3R_FORMAT(name, opcode, d)
3420
3421 #define MSA_3R_SLD_SPLAT(name, opcode) \
3422 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, b) \
3423 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, h) \
3424 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, w) \
3425 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, d)
3426
3427 MSA_3R_LIST(MSA_3R)
3428 MSA_3R_SLD_SPLAT(sld, SLD)
3429 MSA_3R_SLD_SPLAT(splat, SPLAT)
3430
3431 #undef MSA_3R
3432 #undef MSA_3R_FORMAT
3433 #undef MSA_3R_FORMAT_SLD_SPLAT
3434 #undef MSA_3R_SLD_SPLAT
3435 #undef MSA_3R_LIST
3436
3437 #define MSA_3RF_LIST1(V) \
3438 V(fcaf, FCAF) \
3439 V(fcun, FCUN) \
3440 V(fceq, FCEQ) \
3441 V(fcueq, FCUEQ) \
3442 V(fclt, FCLT) \
3443 V(fcult, FCULT) \
3444 V(fcle, FCLE) \
3445 V(fcule, FCULE) \
3446 V(fsaf, FSAF) \
3447 V(fsun, FSUN) \
3448 V(fseq, FSEQ) \
3449 V(fsueq, FSUEQ) \
3450 V(fslt, FSLT) \
3451 V(fsult, FSULT) \
3452 V(fsle, FSLE) \
3453 V(fsule, FSULE) \
3454 V(fadd, FADD) \
3455 V(fsub, FSUB) \
3456 V(fmul, FMUL) \
3457 V(fdiv, FDIV) \
3458 V(fmadd, FMADD) \
3459 V(fmsub, FMSUB) \
3460 V(fexp2, FEXP2) \
3461 V(fmin, FMIN) \
3462 V(fmin_a, FMIN_A) \
3463 V(fmax, FMAX) \
3464 V(fmax_a, FMAX_A) \
3465 V(fcor, FCOR) \
3466 V(fcune, FCUNE) \
3467 V(fcne, FCNE) \
3468 V(fsor, FSOR) \
3469 V(fsune, FSUNE) \
3470 V(fsne, FSNE)
3471
3472 #define MSA_3RF_LIST2(V) \
3473 V(fexdo, FEXDO) \
3474 V(ftq, FTQ) \
3475 V(mul_q, MUL_Q) \
3476 V(madd_q, MADD_Q) \
3477 V(msub_q, MSUB_Q) \
3478 V(mulr_q, MULR_Q) \
3479 V(maddr_q, MADDR_Q) \
3480 V(msubr_q, MSUBR_Q)
3481
3482 #define MSA_3RF_FORMAT(name, opcode, df, df_c) \
3483 void Assembler::name##_##df(MSARegister wd, MSARegister ws, \
3484 MSARegister wt) { \
3485 GenInstrMsa3RF(opcode, df_c, wt, ws, wd); \
3486 }
3487
3488 #define MSA_3RF_1(name, opcode) \
3489 MSA_3RF_FORMAT(name, opcode, w, 0) \
3490 MSA_3RF_FORMAT(name, opcode, d, 1)
3491
3492 #define MSA_3RF_2(name, opcode) \
3493 MSA_3RF_FORMAT(name, opcode, h, 0) \
3494 MSA_3RF_FORMAT(name, opcode, w, 1)
3495
3496 MSA_3RF_LIST1(MSA_3RF_1)
3497 MSA_3RF_LIST2(MSA_3RF_2)
3498 #undef MSA_3RF_1
3499 #undef MSA_3RF_2
3500 #undef MSA_3RF_FORMAT
3501 #undef MSA_3RF_LIST1
3502 #undef MSA_3RF_LIST2
3503
3504 void Assembler::sldi_b(MSARegister wd, MSARegister ws, uint32_t n) {
3505 GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_B, n, ws, wd);
3506 }
3507
sldi_h(MSARegister wd,MSARegister ws,uint32_t n)3508 void Assembler::sldi_h(MSARegister wd, MSARegister ws, uint32_t n) {
3509 GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_H, n, ws, wd);
3510 }
3511
sldi_w(MSARegister wd,MSARegister ws,uint32_t n)3512 void Assembler::sldi_w(MSARegister wd, MSARegister ws, uint32_t n) {
3513 GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_W, n, ws, wd);
3514 }
3515
sldi_d(MSARegister wd,MSARegister ws,uint32_t n)3516 void Assembler::sldi_d(MSARegister wd, MSARegister ws, uint32_t n) {
3517 GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_D, n, ws, wd);
3518 }
3519
splati_b(MSARegister wd,MSARegister ws,uint32_t n)3520 void Assembler::splati_b(MSARegister wd, MSARegister ws, uint32_t n) {
3521 GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_B, n, ws, wd);
3522 }
3523
splati_h(MSARegister wd,MSARegister ws,uint32_t n)3524 void Assembler::splati_h(MSARegister wd, MSARegister ws, uint32_t n) {
3525 GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_H, n, ws, wd);
3526 }
3527
splati_w(MSARegister wd,MSARegister ws,uint32_t n)3528 void Assembler::splati_w(MSARegister wd, MSARegister ws, uint32_t n) {
3529 GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_W, n, ws, wd);
3530 }
3531
splati_d(MSARegister wd,MSARegister ws,uint32_t n)3532 void Assembler::splati_d(MSARegister wd, MSARegister ws, uint32_t n) {
3533 GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_D, n, ws, wd);
3534 }
3535
copy_s_b(Register rd,MSARegister ws,uint32_t n)3536 void Assembler::copy_s_b(Register rd, MSARegister ws, uint32_t n) {
3537 GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_B, n, ws, rd);
3538 }
3539
copy_s_h(Register rd,MSARegister ws,uint32_t n)3540 void Assembler::copy_s_h(Register rd, MSARegister ws, uint32_t n) {
3541 GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_H, n, ws, rd);
3542 }
3543
copy_s_w(Register rd,MSARegister ws,uint32_t n)3544 void Assembler::copy_s_w(Register rd, MSARegister ws, uint32_t n) {
3545 GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_W, n, ws, rd);
3546 }
3547
copy_s_d(Register rd,MSARegister ws,uint32_t n)3548 void Assembler::copy_s_d(Register rd, MSARegister ws, uint32_t n) {
3549 GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_D, n, ws, rd);
3550 }
3551
copy_u_b(Register rd,MSARegister ws,uint32_t n)3552 void Assembler::copy_u_b(Register rd, MSARegister ws, uint32_t n) {
3553 GenInstrMsaElm<Register, MSARegister>(COPY_U, ELM_DF_B, n, ws, rd);
3554 }
3555
copy_u_h(Register rd,MSARegister ws,uint32_t n)3556 void Assembler::copy_u_h(Register rd, MSARegister ws, uint32_t n) {
3557 GenInstrMsaElm<Register, MSARegister>(COPY_U, ELM_DF_H, n, ws, rd);
3558 }
3559
copy_u_w(Register rd,MSARegister ws,uint32_t n)3560 void Assembler::copy_u_w(Register rd, MSARegister ws, uint32_t n) {
3561 GenInstrMsaElm<Register, MSARegister>(COPY_U, ELM_DF_W, n, ws, rd);
3562 }
3563
insert_b(MSARegister wd,uint32_t n,Register rs)3564 void Assembler::insert_b(MSARegister wd, uint32_t n, Register rs) {
3565 GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_B, n, rs, wd);
3566 }
3567
insert_h(MSARegister wd,uint32_t n,Register rs)3568 void Assembler::insert_h(MSARegister wd, uint32_t n, Register rs) {
3569 GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_H, n, rs, wd);
3570 }
3571
insert_w(MSARegister wd,uint32_t n,Register rs)3572 void Assembler::insert_w(MSARegister wd, uint32_t n, Register rs) {
3573 GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_W, n, rs, wd);
3574 }
3575
insert_d(MSARegister wd,uint32_t n,Register rs)3576 void Assembler::insert_d(MSARegister wd, uint32_t n, Register rs) {
3577 GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_D, n, rs, wd);
3578 }
3579
insve_b(MSARegister wd,uint32_t n,MSARegister ws)3580 void Assembler::insve_b(MSARegister wd, uint32_t n, MSARegister ws) {
3581 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_B, n, ws, wd);
3582 }
3583
insve_h(MSARegister wd,uint32_t n,MSARegister ws)3584 void Assembler::insve_h(MSARegister wd, uint32_t n, MSARegister ws) {
3585 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_H, n, ws, wd);
3586 }
3587
insve_w(MSARegister wd,uint32_t n,MSARegister ws)3588 void Assembler::insve_w(MSARegister wd, uint32_t n, MSARegister ws) {
3589 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_W, n, ws, wd);
3590 }
3591
insve_d(MSARegister wd,uint32_t n,MSARegister ws)3592 void Assembler::insve_d(MSARegister wd, uint32_t n, MSARegister ws) {
3593 GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_D, n, ws, wd);
3594 }
3595
move_v(MSARegister wd,MSARegister ws)3596 void Assembler::move_v(MSARegister wd, MSARegister ws) {
3597 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
3598 DCHECK(ws.is_valid() && wd.is_valid());
3599 Instr instr = MSA | MOVE_V | (ws.code() << kWsShift) |
3600 (wd.code() << kWdShift) | MSA_ELM_MINOR;
3601 emit(instr);
3602 }
3603
ctcmsa(MSAControlRegister cd,Register rs)3604 void Assembler::ctcmsa(MSAControlRegister cd, Register rs) {
3605 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
3606 DCHECK(cd.is_valid() && rs.is_valid());
3607 Instr instr = MSA | CTCMSA | (rs.code() << kWsShift) |
3608 (cd.code() << kWdShift) | MSA_ELM_MINOR;
3609 emit(instr);
3610 }
3611
cfcmsa(Register rd,MSAControlRegister cs)3612 void Assembler::cfcmsa(Register rd, MSAControlRegister cs) {
3613 DCHECK((kArchVariant == kMips64r6) && IsEnabled(MIPS_SIMD));
3614 DCHECK(rd.is_valid() && cs.is_valid());
3615 Instr instr = MSA | CFCMSA | (cs.code() << kWsShift) |
3616 (rd.code() << kWdShift) | MSA_ELM_MINOR;
3617 emit(instr);
3618 }
3619
3620 #define MSA_BIT_LIST(V) \
3621 V(slli, SLLI) \
3622 V(srai, SRAI) \
3623 V(srli, SRLI) \
3624 V(bclri, BCLRI) \
3625 V(bseti, BSETI) \
3626 V(bnegi, BNEGI) \
3627 V(binsli, BINSLI) \
3628 V(binsri, BINSRI) \
3629 V(sat_s, SAT_S) \
3630 V(sat_u, SAT_U) \
3631 V(srari, SRARI) \
3632 V(srlri, SRLRI)
3633
3634 #define MSA_BIT_FORMAT(name, opcode, format) \
3635 void Assembler::name##_##format(MSARegister wd, MSARegister ws, \
3636 uint32_t m) { \
3637 GenInstrMsaBit(opcode, BIT_DF_##format, m, ws, wd); \
3638 }
3639
3640 #define MSA_BIT(name, opcode) \
3641 MSA_BIT_FORMAT(name, opcode, b) \
3642 MSA_BIT_FORMAT(name, opcode, h) \
3643 MSA_BIT_FORMAT(name, opcode, w) \
3644 MSA_BIT_FORMAT(name, opcode, d)
3645
MSA_BIT_LIST(MSA_BIT)3646 MSA_BIT_LIST(MSA_BIT)
3647 #undef MSA_BIT
3648 #undef MSA_BIT_FORMAT
3649 #undef MSA_BIT_LIST
3650
3651 int Assembler::RelocateInternalReference(RelocInfo::Mode rmode, Address pc,
3652 intptr_t pc_delta) {
3653 if (RelocInfo::IsInternalReference(rmode)) {
3654 int64_t* p = reinterpret_cast<int64_t*>(pc);
3655 if (*p == kEndOfJumpChain) {
3656 return 0; // Number of instructions patched.
3657 }
3658 *p += pc_delta;
3659 return 2; // Number of instructions patched.
3660 }
3661 Instr instr = instr_at(pc);
3662 DCHECK(RelocInfo::IsInternalReferenceEncoded(rmode));
3663 if (IsLui(instr)) {
3664 Instr instr_lui = instr_at(pc + 0 * kInstrSize);
3665 Instr instr_ori = instr_at(pc + 1 * kInstrSize);
3666 Instr instr_ori2 = instr_at(pc + 3 * kInstrSize);
3667 DCHECK(IsOri(instr_ori));
3668 DCHECK(IsOri(instr_ori2));
3669 // TODO(plind): symbolic names for the shifts.
3670 int64_t imm = (instr_lui & static_cast<int64_t>(kImm16Mask)) << 48;
3671 imm |= (instr_ori & static_cast<int64_t>(kImm16Mask)) << 32;
3672 imm |= (instr_ori2 & static_cast<int64_t>(kImm16Mask)) << 16;
3673 // Sign extend address.
3674 imm >>= 16;
3675
3676 if (imm == kEndOfJumpChain) {
3677 return 0; // Number of instructions patched.
3678 }
3679 imm += pc_delta;
3680 DCHECK_EQ(imm & 3, 0);
3681
3682 instr_lui &= ~kImm16Mask;
3683 instr_ori &= ~kImm16Mask;
3684 instr_ori2 &= ~kImm16Mask;
3685
3686 instr_at_put(pc + 0 * kInstrSize, instr_lui | ((imm >> 32) & kImm16Mask));
3687 instr_at_put(pc + 1 * kInstrSize, instr_ori | (imm >> 16 & kImm16Mask));
3688 instr_at_put(pc + 3 * kInstrSize, instr_ori2 | (imm & kImm16Mask));
3689 return 4; // Number of instructions patched.
3690 } else if (IsJ(instr) || IsJal(instr)) {
3691 // Regular j/jal relocation.
3692 uint32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2;
3693 imm28 += pc_delta;
3694 imm28 &= kImm28Mask;
3695 instr &= ~kImm26Mask;
3696 DCHECK_EQ(imm28 & 3, 0);
3697 uint32_t imm26 = static_cast<uint32_t>(imm28 >> 2);
3698 instr_at_put(pc, instr | (imm26 & kImm26Mask));
3699 return 1; // Number of instructions patched.
3700 } else {
3701 DCHECK(((instr & kJumpRawMask) == kJRawMark) ||
3702 ((instr & kJumpRawMask) == kJalRawMark));
3703 // Unbox raw offset and emit j/jal.
3704 int32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2;
3705 // Sign extend 28-bit offset to 32-bit.
3706 imm28 = (imm28 << 4) >> 4;
3707 uint64_t target =
3708 static_cast<int64_t>(imm28) + reinterpret_cast<uint64_t>(pc);
3709 target &= kImm28Mask;
3710 DCHECK_EQ(imm28 & 3, 0);
3711 uint32_t imm26 = static_cast<uint32_t>(target >> 2);
3712 // Check markings whether to emit j or jal.
3713 uint32_t unbox = (instr & kJRawMark) ? J : JAL;
3714 instr_at_put(pc, unbox | (imm26 & kImm26Mask));
3715 return 1; // Number of instructions patched.
3716 }
3717 }
3718
GrowBuffer()3719 void Assembler::GrowBuffer() {
3720 // Compute new buffer size.
3721 int old_size = buffer_->size();
3722 int new_size = std::min(2 * old_size, old_size + 1 * MB);
3723
3724 // Some internal data structures overflow for very large buffers,
3725 // they must ensure that kMaximalBufferSize is not too large.
3726 if (new_size > kMaximalBufferSize) {
3727 V8::FatalProcessOutOfMemory(nullptr, "Assembler::GrowBuffer");
3728 }
3729
3730 // Set up new buffer.
3731 std::unique_ptr<AssemblerBuffer> new_buffer = buffer_->Grow(new_size);
3732 DCHECK_EQ(new_size, new_buffer->size());
3733 byte* new_start = new_buffer->start();
3734
3735 // Copy the data.
3736 intptr_t pc_delta = new_start - buffer_start_;
3737 intptr_t rc_delta = (new_start + new_size) - (buffer_start_ + old_size);
3738 size_t reloc_size = (buffer_start_ + old_size) - reloc_info_writer.pos();
3739 MemMove(new_start, buffer_start_, pc_offset());
3740 MemMove(reloc_info_writer.pos() + rc_delta, reloc_info_writer.pos(),
3741 reloc_size);
3742
3743 // Switch buffers.
3744 buffer_ = std::move(new_buffer);
3745 buffer_start_ = new_start;
3746 pc_ += pc_delta;
3747 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
3748 reloc_info_writer.last_pc() + pc_delta);
3749
3750 // Relocate runtime entries.
3751 Vector<byte> instructions{buffer_start_, pc_offset()};
3752 Vector<const byte> reloc_info{reloc_info_writer.pos(), reloc_size};
3753 for (RelocIterator it(instructions, reloc_info, 0); !it.done(); it.next()) {
3754 RelocInfo::Mode rmode = it.rinfo()->rmode();
3755 if (rmode == RelocInfo::INTERNAL_REFERENCE) {
3756 RelocateInternalReference(rmode, it.rinfo()->pc(), pc_delta);
3757 }
3758 }
3759 DCHECK(!overflow());
3760 }
3761
db(uint8_t data)3762 void Assembler::db(uint8_t data) {
3763 CheckForEmitInForbiddenSlot();
3764 EmitHelper(data);
3765 }
3766
dd(uint32_t data)3767 void Assembler::dd(uint32_t data) {
3768 CheckForEmitInForbiddenSlot();
3769 EmitHelper(data);
3770 }
3771
dq(uint64_t data)3772 void Assembler::dq(uint64_t data) {
3773 CheckForEmitInForbiddenSlot();
3774 EmitHelper(data);
3775 }
3776
dd(Label * label)3777 void Assembler::dd(Label* label) {
3778 uint64_t data;
3779 CheckForEmitInForbiddenSlot();
3780 if (label->is_bound()) {
3781 data = reinterpret_cast<uint64_t>(buffer_start_ + label->pos());
3782 } else {
3783 data = jump_address(label);
3784 unbound_labels_count_++;
3785 internal_reference_positions_.insert(label->pos());
3786 }
3787 RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
3788 EmitHelper(data);
3789 }
3790
RecordRelocInfo(RelocInfo::Mode rmode,intptr_t data)3791 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
3792 if (!ShouldRecordRelocInfo(rmode)) return;
3793 // We do not try to reuse pool constants.
3794 RelocInfo rinfo(reinterpret_cast<Address>(pc_), rmode, data, Code());
3795 DCHECK_GE(buffer_space(), kMaxRelocSize); // Too late to grow buffer here.
3796 reloc_info_writer.Write(&rinfo);
3797 }
3798
BlockTrampolinePoolFor(int instructions)3799 void Assembler::BlockTrampolinePoolFor(int instructions) {
3800 CheckTrampolinePoolQuick(instructions);
3801 BlockTrampolinePoolBefore(pc_offset() + instructions * kInstrSize);
3802 }
3803
CheckTrampolinePool()3804 void Assembler::CheckTrampolinePool() {
3805 // Some small sequences of instructions must not be broken up by the
3806 // insertion of a trampoline pool; such sequences are protected by setting
3807 // either trampoline_pool_blocked_nesting_ or no_trampoline_pool_before_,
3808 // which are both checked here. Also, recursive calls to CheckTrampolinePool
3809 // are blocked by trampoline_pool_blocked_nesting_.
3810 if ((trampoline_pool_blocked_nesting_ > 0) ||
3811 (pc_offset() < no_trampoline_pool_before_)) {
3812 // Emission is currently blocked; make sure we try again as soon as
3813 // possible.
3814 if (trampoline_pool_blocked_nesting_ > 0) {
3815 next_buffer_check_ = pc_offset() + kInstrSize;
3816 } else {
3817 next_buffer_check_ = no_trampoline_pool_before_;
3818 }
3819 return;
3820 }
3821
3822 DCHECK(!trampoline_emitted_);
3823 DCHECK_GE(unbound_labels_count_, 0);
3824 if (unbound_labels_count_ > 0) {
3825 // First we emit jump (2 instructions), then we emit trampoline pool.
3826 {
3827 BlockTrampolinePoolScope block_trampoline_pool(this);
3828 Label after_pool;
3829 if (kArchVariant == kMips64r6) {
3830 bc(&after_pool);
3831 } else {
3832 b(&after_pool);
3833 }
3834 nop();
3835
3836 int pool_start = pc_offset();
3837 for (int i = 0; i < unbound_labels_count_; i++) {
3838 {
3839 if (kArchVariant == kMips64r6) {
3840 bc(&after_pool);
3841 nop();
3842 } else {
3843 or_(t8, ra, zero_reg);
3844 nal(); // Read PC into ra register.
3845 lui(t9, 0); // Branch delay slot.
3846 ori(t9, t9, 0);
3847 daddu(t9, ra, t9);
3848 or_(ra, t8, zero_reg);
3849 // Instruction jr will take or_ from the next trampoline.
3850 // in its branch delay slot. This is the expected behavior
3851 // in order to decrease size of trampoline pool.
3852 jr(t9);
3853 }
3854 }
3855 }
3856 nop();
3857 bind(&after_pool);
3858 trampoline_ = Trampoline(pool_start, unbound_labels_count_);
3859
3860 trampoline_emitted_ = true;
3861 // As we are only going to emit trampoline once, we need to prevent any
3862 // further emission.
3863 next_buffer_check_ = kMaxInt;
3864 }
3865 } else {
3866 // Number of branches to unbound label at this point is zero, so we can
3867 // move next buffer check to maximum.
3868 next_buffer_check_ =
3869 pc_offset() + kMaxBranchOffset - kTrampolineSlotsSize * 16;
3870 }
3871 return;
3872 }
3873
target_address_at(Address pc)3874 Address Assembler::target_address_at(Address pc) {
3875 Instr instr0 = instr_at(pc);
3876 Instr instr1 = instr_at(pc + 1 * kInstrSize);
3877 Instr instr3 = instr_at(pc + 3 * kInstrSize);
3878
3879 // Interpret 4 instructions for address generated by li: See listing in
3880 // Assembler::set_target_address_at() just below.
3881 if ((GetOpcodeField(instr0) == LUI) && (GetOpcodeField(instr1) == ORI) &&
3882 (GetOpcodeField(instr3) == ORI)) {
3883 // Assemble the 48 bit value.
3884 int64_t addr =
3885 static_cast<int64_t>(((uint64_t)(GetImmediate16(instr0)) << 32) |
3886 ((uint64_t)(GetImmediate16(instr1)) << 16) |
3887 ((uint64_t)(GetImmediate16(instr3))));
3888
3889 // Sign extend to get canonical address.
3890 addr = (addr << 16) >> 16;
3891 return static_cast<Address>(addr);
3892 }
3893 // We should never get here, force a bad address if we do.
3894 UNREACHABLE();
3895 }
3896
3897 // On Mips64, a target address is stored in a 4-instruction sequence:
3898 // 0: lui(rd, (j.imm64_ >> 32) & kImm16Mask);
3899 // 1: ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask);
3900 // 2: dsll(rd, rd, 16);
3901 // 3: ori(rd, rd, j.imm32_ & kImm16Mask);
3902 //
3903 // Patching the address must replace all the lui & ori instructions,
3904 // and flush the i-cache.
3905 //
3906 // There is an optimization below, which emits a nop when the address
3907 // fits in just 16 bits. This is unlikely to help, and should be benchmarked,
3908 // and possibly removed.
set_target_value_at(Address pc,uint64_t target,ICacheFlushMode icache_flush_mode)3909 void Assembler::set_target_value_at(Address pc, uint64_t target,
3910 ICacheFlushMode icache_flush_mode) {
3911 // There is an optimization where only 4 instructions are used to load address
3912 // in code on MIP64 because only 48-bits of address is effectively used.
3913 // It relies on fact the upper [63:48] bits are not used for virtual address
3914 // translation and they have to be set according to value of bit 47 in order
3915 // get canonical address.
3916 Instr instr1 = instr_at(pc + kInstrSize);
3917 uint32_t rt_code = GetRt(instr1);
3918 uint32_t* p = reinterpret_cast<uint32_t*>(pc);
3919
3920 #ifdef DEBUG
3921 // Check we have the result from a li macro-instruction.
3922 Instr instr0 = instr_at(pc);
3923 Instr instr3 = instr_at(pc + kInstrSize * 3);
3924 DCHECK((GetOpcodeField(instr0) == LUI && GetOpcodeField(instr1) == ORI &&
3925 GetOpcodeField(instr3) == ORI));
3926 #endif
3927
3928 // Must use 4 instructions to insure patchable code.
3929 // lui rt, upper-16.
3930 // ori rt, rt, lower-16.
3931 // dsll rt, rt, 16.
3932 // ori rt rt, lower-16.
3933 *p = LUI | (rt_code << kRtShift) | ((target >> 32) & kImm16Mask);
3934 *(p + 1) = ORI | (rt_code << kRtShift) | (rt_code << kRsShift) |
3935 ((target >> 16) & kImm16Mask);
3936 *(p + 3) = ORI | (rt_code << kRsShift) | (rt_code << kRtShift) |
3937 (target & kImm16Mask);
3938
3939 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
3940 FlushInstructionCache(pc, 4 * kInstrSize);
3941 }
3942 }
3943
UseScratchRegisterScope(Assembler * assembler)3944 UseScratchRegisterScope::UseScratchRegisterScope(Assembler* assembler)
3945 : available_(assembler->GetScratchRegisterList()),
3946 old_available_(*available_) {}
3947
~UseScratchRegisterScope()3948 UseScratchRegisterScope::~UseScratchRegisterScope() {
3949 *available_ = old_available_;
3950 }
3951
Acquire()3952 Register UseScratchRegisterScope::Acquire() {
3953 DCHECK_NOT_NULL(available_);
3954 DCHECK_NE(*available_, 0);
3955 int index = static_cast<int>(base::bits::CountTrailingZeros32(*available_));
3956 *available_ &= ~(1UL << index);
3957
3958 return Register::from_code(index);
3959 }
3960
hasAvailable() const3961 bool UseScratchRegisterScope::hasAvailable() const { return *available_ != 0; }
3962
3963 } // namespace internal
3964 } // namespace v8
3965
3966 #endif // V8_TARGET_ARCH_MIPS64
3967