1 /* 2 * Evergeen Register documentation 3 * 4 * Copyright (C) 2010 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _EVERGREEN_REG_H_ 25 #define _EVERGREEN_REG_H_ 26 27 /* 28 * Register definitions 29 */ 30 31 #include "evergreen_reg_auto.h" 32 33 enum { 34 SHADER_TYPE_PS, 35 SHADER_TYPE_VS, 36 SHADER_TYPE_GS, 37 SHADER_TYPE_HS, 38 SHADER_TYPE_LS, 39 SHADER_TYPE_CS, 40 SHADER_TYPE_FS, 41 }; 42 43 44 /* SET_*_REG offsets + ends */ 45 #define SET_CONFIG_REG_offset 0x00008000 46 #define SET_CONFIG_REG_end 0x0000ac00 47 #define SET_CONTEXT_REG_offset 0x00028000 48 #define SET_CONTEXT_REG_end 0x00029000 49 #define SET_RESOURCE_offset 0x00030000 50 #define SET_RESOURCE_end 0x00038000 51 #define SET_SAMPLER_offset 0x0003c000 52 #define SET_SAMPLER_end 0x0003c600 53 #define SET_CTL_CONST_offset 0x0003cff0 54 #define SET_CTL_CONST_end 0x0003ff0c 55 #define SET_LOOP_CONST_offset 0x0003a200 56 #define SET_LOOP_CONST_end 0x0003a500 57 #define SET_BOOL_CONST_offset 0x0003a500 58 #define SET_BOOL_CONST_end 0x0003a518 59 60 61 /* Packet3 commands */ 62 enum { 63 IT_NOP = 0x10, 64 IT_INDIRECT_BUFFER_END = 0x17, 65 IT_SET_PREDICATION = 0x20, 66 IT_COND_EXEC = 0x22, 67 IT_PRED_EXEC = 0x23, 68 IT_DRAW_INDEX_2 = 0x27, 69 IT_CONTEXT_CONTROL = 0x28, 70 IT_DRAW_INDEX_OFFSET = 0x29, 71 IT_INDEX_TYPE = 0x2A, 72 IT_DRAW_INDEX = 0x2B, 73 IT_DRAW_INDEX_AUTO = 0x2D, 74 IT_DRAW_INDEX_IMMD = 0x2E, 75 IT_NUM_INSTANCES = 0x2F, 76 IT_INDIRECT_BUFFER = 0x32, 77 IT_STRMOUT_BUFFER_UPDATE = 0x34, 78 IT_MEM_SEMAPHORE = 0x39, 79 IT_MPEG_INDEX = 0x3A, 80 IT_WAIT_REG_MEM = 0x3C, 81 IT_MEM_WRITE = 0x3D, 82 IT_SURFACE_SYNC = 0x43, 83 IT_ME_INITIALIZE = 0x44, 84 IT_COND_WRITE = 0x45, 85 IT_EVENT_WRITE = 0x46, 86 IT_EVENT_WRITE_EOP = 0x47, 87 IT_EVENT_WRITE_EOS = 0x48, 88 IT_SET_CONFIG_REG = 0x68, 89 IT_SET_CONTEXT_REG = 0x69, 90 IT_SET_ALU_CONST = 0x6A, 91 IT_SET_BOOL_CONST = 0x6B, 92 IT_SET_LOOP_CONST = 0x6C, 93 IT_SET_RESOURCE = 0x6D, 94 IT_SET_SAMPLER = 0x6E, 95 IT_SET_CTL_CONST = 0x6F, 96 }; 97 98 /* IT_WAIT_REG_MEM operation encoding */ 99 100 #define IT_WAIT_ALWAYS (0 << 0) 101 #define IT_WAIT_LT (1 << 0) 102 #define IT_WAIT_LE (2 << 0) 103 #define IT_WAIT_EQ (3 << 0) 104 #define IT_WAIT_NE (4 << 0) 105 #define IT_WAIT_GE (5 << 0) 106 #define IT_WAIT_GT (6 << 0) 107 #define IT_WAIT_REG (0 << 4) 108 #define IT_WAIT_MEM (1 << 4) 109 110 #define IT_WAIT_ADDR(x) ((x) >> 2) 111 112 /* IT_INDEX_TYPE */ 113 #define IT_INDEX_TYPE_SWAP_MODE(x) ((x) << 2) 114 115 enum { 116 117 SQ_LDS_ALLOC_PS = 0x288ec, 118 SQ_DYN_GPR_RESOURCE_LIMIT_1 = 0x28838, 119 SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x8d8c, 120 SQ_LDS_RESOURCE_MGMT = 0x8e2c, 121 122 WAIT_UNTIL = 0x8040, 123 WAIT_CP_DMA_IDLE_bit = 1 << 8, 124 WAIT_CMDFIFO_bit = 1 << 10, 125 WAIT_3D_IDLE_bit = 1 << 15, 126 WAIT_3D_IDLECLEAN_bit = 1 << 17, 127 WAIT_EXTERN_SIG_bit = 1 << 19, 128 CMDFIFO_ENTRIES_mask = 0xf << 20, 129 CMDFIFO_ENTRIES_shift = 20, 130 131 CP_COHER_CNTL = 0x85f0, 132 DEST_BASE_0_ENA_bit = 1 << 0, 133 DEST_BASE_1_ENA_bit = 1 << 1, 134 SO0_DEST_BASE_ENA_bit = 1 << 2, 135 SO1_DEST_BASE_ENA_bit = 1 << 3, 136 SO2_DEST_BASE_ENA_bit = 1 << 4, 137 SO3_DEST_BASE_ENA_bit = 1 << 5, 138 CB0_DEST_BASE_ENA_bit = 1 << 6, 139 CB1_DEST_BASE_ENA_bit = 1 << 7, 140 CB2_DEST_BASE_ENA_bit = 1 << 8, 141 CB3_DEST_BASE_ENA_bit = 1 << 9, 142 CB4_DEST_BASE_ENA_bit = 1 << 10, 143 CB5_DEST_BASE_ENA_bit = 1 << 11, 144 CB6_DEST_BASE_ENA_bit = 1 << 12, 145 CB7_DEST_BASE_ENA_bit = 1 << 13, 146 DB_DEST_BASE_ENA_bit = 1 << 14, 147 CB8_DEST_BASE_ENA_bit = 1 << 15, 148 CB9_DEST_BASE_ENA_bit = 1 << 16, 149 CB10_DEST_BASE_ENA_bit = 1 << 17, 150 CB11_DEST_BASE_ENA_bit = 1 << 18, 151 FULL_CACHE_ENA_bit = 1 << 20, 152 TC_ACTION_ENA_bit = 1 << 23, 153 VC_ACTION_ENA_bit = 1 << 24, 154 CB_ACTION_ENA_bit = 1 << 25, 155 DB_ACTION_ENA_bit = 1 << 26, 156 SH_ACTION_ENA_bit = 1 << 27, 157 SX_ACTION_ENA_bit = 1 << 28, 158 CP_COHER_SIZE = 0x85f4, 159 CP_COHER_BASE = 0x85f8, 160 CP_COHER_STATUS = 0x85fc, 161 MATCHING_GFX_CNTX_mask = 0xff << 0, 162 MATCHING_GFX_CNTX_shift = 0, 163 STATUS_bit = 1 << 31, 164 165 // SQ_VTX_CONSTANT_WORD2_0 = 0x00030008, 166 // SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, 167 FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, 168 FMT_16=5, FMT_16_FLOAT, FMT_8_8, 169 FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, 170 FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, 171 FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, 172 FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, 173 FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, 174 FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, 175 FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, 176 FMT_1 = 37, FMT_GB_GR=39, 177 FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, 178 FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, 179 FMT_32_32_32_FLOAT=48, 180 181 // High level register file lengths 182 SQ_FETCH_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, 183 SQ_FETCH_RESOURCE_ps_num = 176, 184 SQ_FETCH_RESOURCE_vs_num = 160, 185 SQ_FETCH_RESOURCE_gs_num = 160, 186 SQ_FETCH_RESOURCE_hs_num = 160, 187 SQ_FETCH_RESOURCE_ls_num = 160, 188 SQ_FETCH_RESOURCE_cs_num = 176, 189 SQ_FETCH_RESOURCE_fs_num = 32, 190 SQ_FETCH_RESOURCE_all_num = 1024, 191 SQ_FETCH_RESOURCE_offset = 32, 192 SQ_FETCH_RESOURCE_ps = 0, // 0...175 193 SQ_FETCH_RESOURCE_vs = SQ_FETCH_RESOURCE_ps + SQ_FETCH_RESOURCE_ps_num, // 176...335 194 SQ_FETCH_RESOURCE_gs = SQ_FETCH_RESOURCE_vs + SQ_FETCH_RESOURCE_vs_num, // 336...495 195 SQ_FETCH_RESOURCE_hs = SQ_FETCH_RESOURCE_gs + SQ_FETCH_RESOURCE_gs_num, // 496...655 196 SQ_FETCH_RESOURCE_ls = SQ_FETCH_RESOURCE_hs + SQ_FETCH_RESOURCE_hs_num, // 656...815 197 SQ_FETCH_RESOURCE_cs = SQ_FETCH_RESOURCE_ls + SQ_FETCH_RESOURCE_ls_num, // 816...991 198 SQ_FETCH_RESOURCE_fs = SQ_FETCH_RESOURCE_cs + SQ_FETCH_RESOURCE_cs_num, // 992...1023 199 200 SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, 201 SQ_TEX_SAMPLER_WORD_ps_num = 18, 202 SQ_TEX_SAMPLER_WORD_vs_num = 18, 203 SQ_TEX_SAMPLER_WORD_gs_num = 18, 204 SQ_TEX_SAMPLER_WORD_hs_num = 18, 205 SQ_TEX_SAMPLER_WORD_ls_num = 18, 206 SQ_TEX_SAMPLER_WORD_cs_num = 18, 207 SQ_TEX_SAMPLER_WORD_all_num = 108, 208 SQ_TEX_SAMPLER_WORD_offset = 12, 209 SQ_TEX_SAMPLER_WORD_ps = 0, // 0...17 210 SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, // 18...35 211 SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, // 36...53 212 SQ_TEX_SAMPLER_WORD_hs = SQ_TEX_SAMPLER_WORD_gs + SQ_TEX_SAMPLER_WORD_gs_num, // 54...71 213 SQ_TEX_SAMPLER_WORD_ls = SQ_TEX_SAMPLER_WORD_hs + SQ_TEX_SAMPLER_WORD_hs_num, // 72...89 214 SQ_TEX_SAMPLER_WORD_cs = SQ_TEX_SAMPLER_WORD_ls + SQ_TEX_SAMPLER_WORD_ls_num, // 90...107 215 216 SQ_LOOP_CONST = SQ_LOOP_CONST_0, 217 SQ_LOOP_CONST_ps_num = 32, 218 SQ_LOOP_CONST_vs_num = 32, 219 SQ_LOOP_CONST_gs_num = 32, 220 SQ_LOOP_CONST_hs_num = 32, 221 SQ_LOOP_CONST_ls_num = 32, 222 SQ_LOOP_CONST_cs_num = 32, 223 SQ_LOOP_CONST_all_num = 192, 224 SQ_LOOP_CONST_offset = 4, 225 SQ_LOOP_CONST_ps = 0, // 0...31 226 SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, // 32...63 227 SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, // 64...95 228 SQ_LOOP_CONST_hs = SQ_LOOP_CONST_gs + SQ_LOOP_CONST_gs_num, // 96...127 229 SQ_LOOP_CONST_ls = SQ_LOOP_CONST_hs + SQ_LOOP_CONST_hs_num, // 128...159 230 SQ_LOOP_CONST_cs = SQ_LOOP_CONST_ls + SQ_LOOP_CONST_ls_num, // 160...191 231 232 SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits each */ 233 SQ_BOOL_CONST_ps_num = 1, 234 SQ_BOOL_CONST_vs_num = 1, 235 SQ_BOOL_CONST_gs_num = 1, 236 SQ_BOOL_CONST_hs_num = 1, 237 SQ_BOOL_CONST_ls_num = 1, 238 SQ_BOOL_CONST_cs_num = 1, 239 SQ_BOOL_CONST_all_num = 6, 240 SQ_BOOL_CONST_offset = 4, 241 SQ_BOOL_CONST_ps = 0, 242 SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, 243 SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, 244 SQ_BOOL_CONST_hs = SQ_BOOL_CONST_gs + SQ_BOOL_CONST_gs_num, 245 SQ_BOOL_CONST_ls = SQ_BOOL_CONST_hs + SQ_BOOL_CONST_hs_num, 246 SQ_BOOL_CONST_cs = SQ_BOOL_CONST_ls + SQ_BOOL_CONST_ls_num, 247 248 }; 249 250 #endif 251