1@c Copyright (C) 2009-2016 Free Software Foundation, Inc. 2@c Contributed by ARM Ltd. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5@c man end 6 7@ifset GENERIC 8@page 9@node AArch64-Dependent 10@chapter AArch64 Dependent Features 11@end ifset 12 13@ifclear GENERIC 14@node Machine Dependencies 15@chapter AArch64 Dependent Features 16@end ifclear 17 18@cindex AArch64 support 19@menu 20* AArch64 Options:: Options 21* AArch64 Extensions:: Extensions 22* AArch64 Syntax:: Syntax 23* AArch64 Floating Point:: Floating Point 24* AArch64 Directives:: AArch64 Machine Directives 25* AArch64 Opcodes:: Opcodes 26* AArch64 Mapping Symbols:: Mapping Symbols 27@end menu 28 29@node AArch64 Options 30@section Options 31@cindex AArch64 options (none) 32@cindex options for AArch64 (none) 33 34@c man begin OPTIONS 35@table @gcctabopt 36 37@cindex @option{-EB} command line option, AArch64 38@item -EB 39This option specifies that the output generated by the assembler should 40be marked as being encoded for a big-endian processor. 41 42@cindex @option{-EL} command line option, AArch64 43@item -EL 44This option specifies that the output generated by the assembler should 45be marked as being encoded for a little-endian processor. 46 47@cindex @option{-mabi=} command line option, AArch64 48@item -mabi=@var{abi} 49Specify which ABI the source code uses. The recognized arguments 50are: @code{ilp32} and @code{lp64}, which decides the generated object 51file in ELF32 and ELF64 format respectively. The default is @code{lp64}. 52 53@cindex @option{-mcpu=} command line option, AArch64 54@item -mcpu=@var{processor}[+@var{extension}@dots{}] 55This option specifies the target processor. The assembler will issue an error 56message if an attempt is made to assemble an instruction which will not execute 57on the target processor. The following processor names are recognized: 58@code{cortex-a35}, 59@code{cortex-a53}, 60@code{cortex-a57}, 61@code{cortex-a72}, 62@code{cortex-a73}, 63@code{exynos-m1}, 64@code{qdf24xx}, 65@code{thunderx}, 66@code{vulcan}, 67@code{xgene1} 68and 69@code{xgene2}. 70The special name @code{all} may be used to allow the assembler to accept 71instructions valid for any supported processor, including all optional 72extensions. 73 74In addition to the basic instruction set, the assembler can be told to 75accept, or restrict, various extension mnemonics that extend the 76processor. @xref{AArch64 Extensions}. 77 78If some implementations of a particular processor can have an 79extension, then then those extensions are automatically enabled. 80Consequently, you will not normally have to specify any additional 81extensions. 82 83@cindex @option{-march=} command line option, AArch64 84@item -march=@var{architecture}[+@var{extension}@dots{}] 85This option specifies the target architecture. The assembler will 86issue an error message if an attempt is made to assemble an 87instruction which will not execute on the target architecture. The 88following architecture names are recognized: @code{armv8-a}, 89@code{armv8.1-a} and @code{armv8.2-a}. 90 91If both @option{-mcpu} and @option{-march} are specified, the 92assembler will use the setting for @option{-mcpu}. If neither are 93specified, the assembler will default to @option{-mcpu=all}. 94 95The architecture option can be extended with the same instruction set 96extension options as the @option{-mcpu} option. Unlike 97@option{-mcpu}, extensions are not always enabled by default, 98@xref{AArch64 Extensions}. 99 100@cindex @code{-mverbose-error} command line option, AArch64 101@item -mverbose-error 102This option enables verbose error messages for AArch64 gas. This option 103is enabled by default. 104 105@cindex @code{-mno-verbose-error} command line option, AArch64 106@item -mno-verbose-error 107This option disables verbose error messages in AArch64 gas. 108 109@end table 110@c man end 111 112@node AArch64 Extensions 113@section Architecture Extensions 114 115The table below lists the permitted architecture extensions that are 116supported by the assembler and the conditions under which they are 117automatically enabled. 118 119Multiple extensions may be specified, separated by a @code{+}. 120Extension mnemonics may also be removed from those the assembler 121accepts. This is done by prepending @code{no} to the option that adds 122the extension. Extensions that are removed must be listed after all 123extensions that have been added. 124 125Enabling an extension that requires other extensions will 126automatically cause those extensions to be enabled. Similarly, 127disabling an extension that is required by other extensions will 128automatically cause those extensions to be disabled. 129 130@multitable @columnfractions .12 .17 .17 .54 131@headitem Extension @tab Minimum Architecture @tab Enabled by default 132 @tab Description 133@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later 134 @tab Enable CRC instructions. 135@item @code{crypto} @tab ARMv8-A @tab No 136 @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}. 137@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later 138 @tab Enable floating-point extensions. 139@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later 140 @tab Enable ARMv8.2 16-bit floating-point support. This implies 141 @code{fp}. 142@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later 143 @tab Enable Limited Ordering Regions extensions. 144@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later 145 @tab Enable Large System extensions. 146@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later 147 @tab Enable Privileged Access Never support. 148@item @code{profile} @tab ARMv8.2-A @tab No 149 @tab Enable statistical profiling extensions. 150@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later 151 @tab Enable the Reliability, Availability and Serviceability 152 extension. 153@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later 154 @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}. 155@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later 156 @tab Enable Advanced SIMD extensions. This implies @code{fp}. 157@end multitable 158 159@node AArch64 Syntax 160@section Syntax 161@menu 162* AArch64-Chars:: Special Characters 163* AArch64-Regs:: Register Names 164* AArch64-Relocations:: Relocations 165@end menu 166 167@node AArch64-Chars 168@subsection Special Characters 169 170@cindex line comment character, AArch64 171@cindex AArch64 line comment character 172The presence of a @samp{//} on a line indicates the start of a comment 173that extends to the end of the current line. If a @samp{#} appears as 174the first character of a line, the whole line is treated as a comment. 175 176@cindex line separator, AArch64 177@cindex statement separator, AArch64 178@cindex AArch64 line separator 179The @samp{;} character can be used instead of a newline to separate 180statements. 181 182@cindex immediate character, AArch64 183@cindex AArch64 immediate character 184The @samp{#} can be optionally used to indicate immediate operands. 185 186@node AArch64-Regs 187@subsection Register Names 188 189@cindex AArch64 register names 190@cindex register names, AArch64 191Please refer to the section @samp{4.4 Register Names} of 192@samp{ARMv8 Instruction Set Overview}, which is available at 193@uref{http://infocenter.arm.com}. 194 195@node AArch64-Relocations 196@subsection Relocations 197 198@cindex relocations, AArch64 199@cindex AArch64 relocations 200@cindex MOVN, MOVZ and MOVK group relocations, AArch64 201Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated 202by prefixing the label with @samp{#:abs_g2:} etc. 203For example to load the 48-bit absolute address of @var{foo} into x0: 204 205@smallexample 206 movz x0, #:abs_g2:foo // bits 32-47, overflow check 207 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check 208 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check 209@end smallexample 210 211@cindex ADRP, ADD, LDR/STR group relocations, AArch64 212Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} 213instructions can be generated by prefixing the label with 214@samp{:pg_hi21:} and @samp{#:lo12:} respectively. 215 216For example to use 33-bit (+/-4GB) pc-relative addressing to 217load the address of @var{foo} into x0: 218 219@smallexample 220 adrp x0, :pg_hi21:foo 221 add x0, x0, #:lo12:foo 222@end smallexample 223 224Or to load the value of @var{foo} into x0: 225 226@smallexample 227 adrp x0, :pg_hi21:foo 228 ldr x0, [x0, #:lo12:foo] 229@end smallexample 230 231Note that @samp{:pg_hi21:} is optional. 232 233@smallexample 234 adrp x0, foo 235@end smallexample 236 237is equivalent to 238 239@smallexample 240 adrp x0, :pg_hi21:foo 241@end smallexample 242 243@node AArch64 Floating Point 244@section Floating Point 245 246@cindex floating point, AArch64 (@sc{ieee}) 247@cindex AArch64 floating point (@sc{ieee}) 248The AArch64 architecture uses @sc{ieee} floating-point numbers. 249 250@node AArch64 Directives 251@section AArch64 Machine Directives 252 253@cindex machine directives, AArch64 254@cindex AArch64 machine directives 255@table @code 256 257@c AAAAAAAAAAAAAAAAAAAAAAAAA 258 259@cindex @code{.arch} directive, AArch64 260@item .arch @var{name} 261Select the target architecture. Valid values for @var{name} are the same as 262for the @option{-march} commandline option. 263 264Specifying @code{.arch} clears any previously selected architecture 265extensions. 266 267@cindex @code{.arch_extension} directive, AArch64 268@item .arch_extension @var{name} 269Add or remove an architecture extension to the target architecture. Valid 270values for @var{name} are the same as those accepted as architectural 271extensions by the @option{-mcpu} commandline option. 272 273@code{.arch_extension} may be used multiple times to add or remove extensions 274incrementally to the architecture being compiled for. 275 276@c BBBBBBBBBBBBBBBBBBBBBBBBBB 277 278@cindex @code{.bss} directive, AArch64 279@item .bss 280This directive switches to the @code{.bss} section. 281 282@c CCCCCCCCCCCCCCCCCCCCCCCCCC 283 284@cindex @code{.cpu} directive, AArch64 285@item .cpu @var{name} 286Set the target processor. Valid values for @var{name} are the same as 287those accepted by the @option{-mcpu=} command line option. 288 289@c DDDDDDDDDDDDDDDDDDDDDDDDDD 290 291@cindex @code{.dword} directive, AArch64 292@item .dword @var{expressions} 293The @code{.dword} directive produces 64 bit values. 294 295@c EEEEEEEEEEEEEEEEEEEEEEEEEE 296 297@cindex @code{.even} directive, AArch64 298@item .even 299The @code{.even} directive aligns the output on the next even byte 300boundary. 301 302@c FFFFFFFFFFFFFFFFFFFFFFFFFF 303@c GGGGGGGGGGGGGGGGGGGGGGGGGG 304@c HHHHHHHHHHHHHHHHHHHHHHHHHH 305@c IIIIIIIIIIIIIIIIIIIIIIIIII 306 307@cindex @code{.inst} directive, AArch64 308@item .inst @var{expressions} 309Inserts the expressions into the output as if they were instructions, 310rather than data. 311 312@c JJJJJJJJJJJJJJJJJJJJJJJJJJ 313@c KKKKKKKKKKKKKKKKKKKKKKKKKK 314@c LLLLLLLLLLLLLLLLLLLLLLLLLL 315 316@cindex @code{.ltorg} directive, AArch64 317@item .ltorg 318This directive causes the current contents of the literal pool to be 319dumped into the current section (which is assumed to be the .text 320section) at the current location (aligned to a word boundary). 321GAS maintains a separate literal pool for each section and each 322sub-section. The @code{.ltorg} directive will only affect the literal 323pool of the current section and sub-section. At the end of assembly 324all remaining, un-empty literal pools will automatically be dumped. 325 326Note - older versions of GAS would dump the current literal 327pool any time a section change occurred. This is no longer done, since 328it prevents accurate control of the placement of literal pools. 329 330@c MMMMMMMMMMMMMMMMMMMMMMMMMM 331 332@c NNNNNNNNNNNNNNNNNNNNNNNNNN 333@c OOOOOOOOOOOOOOOOOOOOOOOOOO 334 335@c PPPPPPPPPPPPPPPPPPPPPPPPPP 336 337@cindex @code{.pool} directive, AArch64 338@item .pool 339This is a synonym for .ltorg. 340 341@c QQQQQQQQQQQQQQQQQQQQQQQQQQ 342@c RRRRRRRRRRRRRRRRRRRRRRRRRR 343 344@cindex @code{.req} directive, AArch64 345@item @var{name} .req @var{register name} 346This creates an alias for @var{register name} called @var{name}. For 347example: 348 349@smallexample 350 foo .req w0 351@end smallexample 352 353@c SSSSSSSSSSSSSSSSSSSSSSSSSS 354 355@c TTTTTTTTTTTTTTTTTTTTTTTTTT 356 357@cindex @code{.tlsdescadd} directive, AArch64 358@item @code{.tlsdescadd} 359Emits a TLSDESC_ADD reloc on the next instruction. 360 361@cindex @code{.tlsdesccall} directive, AArch64 362@item @code{.tlsdesccall} 363Emits a TLSDESC_CALL reloc on the next instruction. 364 365@cindex @code{.tlsdescldr} directive, AArch64 366@item @code{.tlsdescldr} 367Emits a TLSDESC_LDR reloc on the next instruction. 368 369@c UUUUUUUUUUUUUUUUUUUUUUUUUU 370 371@cindex @code{.unreq} directive, AArch64 372@item .unreq @var{alias-name} 373This undefines a register alias which was previously defined using the 374@code{req} directive. For example: 375 376@smallexample 377 foo .req w0 378 .unreq foo 379@end smallexample 380 381An error occurs if the name is undefined. Note - this pseudo op can 382be used to delete builtin in register name aliases (eg 'w0'). This 383should only be done if it is really necessary. 384 385@c VVVVVVVVVVVVVVVVVVVVVVVVVV 386 387@c WWWWWWWWWWWWWWWWWWWWWWWWWW 388@c XXXXXXXXXXXXXXXXXXXXXXXXXX 389 390@cindex @code{.xword} directive, AArch64 391@item .xword @var{expressions} 392The @code{.xword} directive produces 64 bit values. This is the same 393as the @code{.dword} directive. 394 395@c YYYYYYYYYYYYYYYYYYYYYYYYYY 396@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ 397 398@end table 399 400@node AArch64 Opcodes 401@section Opcodes 402 403@cindex AArch64 opcodes 404@cindex opcodes for AArch64 405GAS implements all the standard AArch64 opcodes. It also 406implements several pseudo opcodes, including several synthetic load 407instructions. 408 409@table @code 410 411@cindex @code{LDR reg,=<expr>} pseudo op, AArch64 412@item LDR = 413@smallexample 414 ldr <register> , =<expression> 415@end smallexample 416 417The constant expression will be placed into the nearest literal pool (if it not 418already there) and a PC-relative LDR instruction will be generated. 419 420@end table 421 422For more information on the AArch64 instruction set and assembly language 423notation, see @samp{ARMv8 Instruction Set Overview} available at 424@uref{http://infocenter.arm.com}. 425 426 427@node AArch64 Mapping Symbols 428@section Mapping Symbols 429 430The AArch64 ELF specification requires that special symbols be inserted 431into object files to mark certain features: 432 433@table @code 434 435@cindex @code{$x} 436@item $x 437At the start of a region of code containing AArch64 instructions. 438 439@cindex @code{$d} 440@item $d 441At the start of a region of data. 442 443@end table 444