1@c Copyright (C) 1997-2016 Free Software Foundation, Inc.
2@c This is part of the GAS manual.
3@c For copying conditions, see the file as.texinfo.
4@ifset GENERIC
5@page
6@node D30V-Dependent
7@chapter D30V Dependent Features
8@end ifset
9@ifclear GENERIC
10@node Machine Dependencies
11@chapter D30V Dependent Features
12@end ifclear
13
14@cindex D30V support
15@menu
16* D30V-Opts::                   D30V Options
17* D30V-Syntax::                 Syntax
18* D30V-Float::                  Floating Point
19* D30V-Opcodes::                Opcodes
20@end menu
21
22@node D30V-Opts
23@section D30V Options
24@cindex options, D30V
25@cindex D30V options
26The Mitsubishi D30V version of @code{@value{AS}} has a few machine
27dependent options.
28
29@table @samp
30@item -O
31The D30V can often execute two sub-instructions in parallel. When this option
32is used, @code{@value{AS}} will attempt to optimize its output by detecting when
33instructions can be executed in parallel.
34
35@item -n
36When this option is used, @code{@value{AS}} will issue a warning every
37time it adds a nop instruction.
38
39@item -N
40When this option is used, @code{@value{AS}} will issue a warning if it
41needs to insert a nop after a 32-bit multiply before a load or 16-bit
42multiply instruction.
43@end table
44
45@node D30V-Syntax
46@section Syntax
47@cindex D30V syntax
48@cindex syntax, D30V
49
50The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual.
51The differences are detailed below.
52
53@menu
54* D30V-Size::                 Size Modifiers
55* D30V-Subs::                 Sub-Instructions
56* D30V-Chars::                Special Characters
57* D30V-Guarded::              Guarded Execution
58* D30V-Regs::                 Register Names
59* D30V-Addressing::           Addressing Modes
60@end menu
61
62
63@node D30V-Size
64@subsection Size Modifiers
65@cindex D30V size modifiers
66@cindex size modifiers, D30V
67The D30V version of @code{@value{AS}} uses the instruction names in the D30V
68Architecture Manual.  However, the names in the manual are sometimes ambiguous.
69There are instruction names that can assemble to a short or long form opcode.
70How does the assembler pick the correct form?  @code{@value{AS}} will always pick the
71smallest form if it can.  When dealing with a symbol that is not defined yet when a
72line is being assembled, it will always use the long form.  If you need to force the
73assembler to use either the short or long form of the instruction, you can append
74either @samp{.s} (short) or @samp{.l} (long) to it.  For example, if you are writing
75an assembly program and you want to do a branch to a symbol that is defined later
76in your program, you can write @samp{bra.s foo}.
77Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
78have both short and long forms.
79
80@node D30V-Subs
81@subsection Sub-Instructions
82@cindex D30V sub-instructions
83@cindex sub-instructions, D30V
84The D30V assembler takes as input a series of instructions, either one-per-line,
85or in the special two-per-line format described in the next section.  Some of these
86instructions will be short-form or sub-instructions.  These sub-instructions can be packed
87into a single instruction.  The assembler will do this automatically.  It will also detect
88when it should not pack instructions.  For example, when a label is defined, the next
89instruction will never be packaged with the previous one.  Whenever a branch and link
90instruction is called, it will not be packaged with the next instruction so the return
91address will be valid.  Nops are automatically inserted when necessary.
92
93If you do not want the assembler automatically making these decisions, you can control
94the packaging and execution type (parallel or sequential) with the special execution
95symbols described in the next section.
96
97@node D30V-Chars
98@subsection Special Characters
99@cindex line comment character, D30V
100@cindex D30V line comment character
101A semicolon (@samp{;}) can be used anywhere on a line to start a
102comment that extends to the end of the line.
103
104If a @samp{#} appears as the first character of a line, the whole line
105is treated as a comment, but in this case the line could also be a
106logical line number directive (@pxref{Comments}) or a preprocessor
107control command (@pxref{Preprocessing}).
108
109@cindex sub-instruction ordering, D30V
110@cindex D30V sub-instruction ordering
111Sub-instructions may be executed in order, in reverse-order, or in parallel.
112Instructions listed in the standard one-per-line format will be executed
113sequentially unless you use the @samp{-O} option.
114
115To specify the executing order, use the following symbols:
116@table @samp
117@item ->
118Sequential with instruction on the left first.
119
120@item <-
121Sequential with instruction on the right first.
122
123@item ||
124Parallel
125@end table
126
127The D30V syntax allows either one instruction per line, one instruction per line with
128the execution symbol, or two instructions per line.  For example
129@table @code
130@item abs r2,r3 -> abs r4,r5
131Execute these sequentially.  The instruction on the right is in the right
132container and is executed second.
133
134@item abs r2,r3 <- abs r4,r5
135Execute these reverse-sequentially.  The instruction on the right is in the right
136container, and is executed first.
137
138@item abs r2,r3 || abs r4,r5
139Execute these in parallel.
140
141@item ldw r2,@@(r3,r4) ||
142@itemx mulx r6,r8,r9
143Two-line format. Execute these in parallel.
144
145@item mulx a0,r8,r9
146@itemx stw r2,@@(r3,r4)
147Two-line format. Execute these sequentially unless @samp{-O} option is
148used.  If the @samp{-O} option is used, the assembler will determine if
149the instructions could be done in parallel (the above two instructions
150can be done in parallel), and if so, emit them as parallel instructions.
151The assembler will put them in the proper containers.  In the above
152example, the assembler will put the @samp{stw} instruction in left
153container and the @samp{mulx} instruction in the right container.
154
155@item stw r2,@@(r3,r4) ->
156@itemx mulx a0,r8,r9
157Two-line format.  Execute the @samp{stw} instruction followed by the
158@samp{mulx} instruction sequentially.  The first instruction goes in the
159left container and the second instruction goes into right container.
160The assembler will give an error if the machine ordering constraints are
161violated.
162
163@item stw r2,@@(r3,r4) <-
164@itemx mulx a0,r8,r9
165Same as previous example, except that the @samp{mulx} instruction is
166executed before the @samp{stw} instruction.
167@end table
168
169@cindex symbol names, @samp{$} in
170@cindex @code{$} in symbol names
171Since @samp{$} has no special meaning, you may use it in symbol names.
172
173@node D30V-Guarded
174@subsection Guarded Execution
175@cindex D30V Guarded Execution
176@code{@value{AS}} supports the full range of guarded execution
177directives for each instruction.  Just append the directive after the
178instruction proper.  The directives are:
179
180@table @samp
181@item /tx
182Execute the instruction if flag f0 is true.
183@item /fx
184Execute the instruction if flag f0 is false.
185@item /xt
186Execute the instruction if flag f1 is true.
187@item /xf
188Execute the instruction if flag f1 is false.
189@item /tt
190Execute the instruction if both flags f0 and f1 are true.
191@item /tf
192Execute the instruction if flag f0 is true and flag f1 is false.
193@end table
194
195@node D30V-Regs
196@subsection Register Names
197@cindex D30V registers
198@cindex registers, D30V
199You can use the predefined symbols @samp{r0} through @samp{r63} to refer
200to the D30V registers.  You can also use @samp{sp} as an alias for
201@samp{r63} and @samp{link} as an alias for @samp{r62}.  The accumulators
202are @samp{a0} and @samp{a1}.
203
204The D30V also has predefined symbols for these control registers and status bits:
205@table @code
206@item psw
207Processor Status Word
208@item bpsw
209Backup Processor Status Word
210@item pc
211Program Counter
212@item bpc
213Backup Program Counter
214@item rpt_c
215Repeat Count
216@item rpt_s
217Repeat Start address
218@item rpt_e
219Repeat End address
220@item mod_s
221Modulo Start address
222@item mod_e
223Modulo End address
224@item iba
225Instruction Break Address
226@item f0
227Flag 0
228@item f1
229Flag 1
230@item f2
231Flag 2
232@item f3
233Flag 3
234@item f4
235Flag 4
236@item f5
237Flag 5
238@item f6
239Flag 6
240@item f7
241Flag 7
242@item s
243Same as flag 4 (saturation flag)
244@item v
245Same as flag 5 (overflow flag)
246@item va
247Same as flag 6 (sticky overflow flag)
248@item c
249Same as flag 7 (carry/borrow flag)
250@item b
251Same as flag 7 (carry/borrow flag)
252@end table
253
254@node D30V-Addressing
255@subsection Addressing Modes
256@cindex addressing modes, D30V
257@cindex D30V addressing modes
258@code{@value{AS}} understands the following addressing modes for the D30V.
259@code{R@var{n}} in the following refers to any of the numbered
260registers, but @emph{not} the control registers.
261@table @code
262@item R@var{n}
263Register direct
264@item @@R@var{n}
265Register indirect
266@item @@R@var{n}+
267Register indirect with post-increment
268@item @@R@var{n}-
269Register indirect with post-decrement
270@item @@-SP
271Register indirect with pre-decrement
272@item @@(@var{disp}, R@var{n})
273Register indirect with displacement
274@item @var{addr}
275PC relative address (for branch or rep).
276@item #@var{imm}
277Immediate data (the @samp{#} is optional and ignored)
278@end table
279
280@node D30V-Float
281@section Floating Point
282@cindex floating point, D30V
283@cindex D30V floating point
284The D30V has no hardware floating point, but the @code{.float} and @code{.double}
285directives generates @sc{ieee} floating-point numbers for compatibility
286with other development tools.
287
288@node D30V-Opcodes
289@section Opcodes
290@cindex D30V opcode summary
291@cindex opcode summary, D30V
292@cindex mnemonics, D30V
293@cindex instruction summary, D30V
294For detailed information on the D30V machine instruction set, see
295@cite{D30V Architecture: A VLIW Microprocessor for Multimedia Applications}
296(Mitsubishi Electric Corp.).
297@code{@value{AS}} implements all the standard D30V opcodes.  The only changes are those
298described in the section on size modifiers
299
300