1*a9fa9459Szrj@c Copyright (C) 1991-2016 Free Software Foundation, Inc. 2*a9fa9459Szrj@c This is part of the GAS manual. 3*a9fa9459Szrj@c For copying conditions, see the file as.texinfo. 4*a9fa9459Szrj@c man end 5*a9fa9459Szrj 6*a9fa9459Szrj@ifset GENERIC 7*a9fa9459Szrj@page 8*a9fa9459Szrj@node i386-Dependent 9*a9fa9459Szrj@chapter 80386 Dependent Features 10*a9fa9459Szrj@end ifset 11*a9fa9459Szrj@ifclear GENERIC 12*a9fa9459Szrj@node Machine Dependencies 13*a9fa9459Szrj@chapter 80386 Dependent Features 14*a9fa9459Szrj@end ifclear 15*a9fa9459Szrj 16*a9fa9459Szrj@cindex i386 support 17*a9fa9459Szrj@cindex i80386 support 18*a9fa9459Szrj@cindex x86-64 support 19*a9fa9459Szrj 20*a9fa9459SzrjThe i386 version @code{@value{AS}} supports both the original Intel 386 21*a9fa9459Szrjarchitecture in both 16 and 32-bit mode as well as AMD x86-64 architecture 22*a9fa9459Szrjextending the Intel architecture to 64-bits. 23*a9fa9459Szrj 24*a9fa9459Szrj@menu 25*a9fa9459Szrj* i386-Options:: Options 26*a9fa9459Szrj* i386-Directives:: X86 specific directives 27*a9fa9459Szrj* i386-Syntax:: Syntactical considerations 28*a9fa9459Szrj* i386-Mnemonics:: Instruction Naming 29*a9fa9459Szrj* i386-Regs:: Register Naming 30*a9fa9459Szrj* i386-Prefixes:: Instruction Prefixes 31*a9fa9459Szrj* i386-Memory:: Memory References 32*a9fa9459Szrj* i386-Jumps:: Handling of Jump Instructions 33*a9fa9459Szrj* i386-Float:: Floating Point 34*a9fa9459Szrj* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 35*a9fa9459Szrj* i386-LWP:: AMD's Lightweight Profiling Instructions 36*a9fa9459Szrj* i386-BMI:: Bit Manipulation Instruction 37*a9fa9459Szrj* i386-TBM:: AMD's Trailing Bit Manipulation Instructions 38*a9fa9459Szrj* i386-16bit:: Writing 16-bit Code 39*a9fa9459Szrj* i386-Arch:: Specifying an x86 CPU architecture 40*a9fa9459Szrj* i386-Bugs:: AT&T Syntax bugs 41*a9fa9459Szrj* i386-Notes:: Notes 42*a9fa9459Szrj@end menu 43*a9fa9459Szrj 44*a9fa9459Szrj@node i386-Options 45*a9fa9459Szrj@section Options 46*a9fa9459Szrj 47*a9fa9459Szrj@cindex options for i386 48*a9fa9459Szrj@cindex options for x86-64 49*a9fa9459Szrj@cindex i386 options 50*a9fa9459Szrj@cindex x86-64 options 51*a9fa9459Szrj 52*a9fa9459SzrjThe i386 version of @code{@value{AS}} has a few machine 53*a9fa9459Szrjdependent options: 54*a9fa9459Szrj 55*a9fa9459Szrj@c man begin OPTIONS 56*a9fa9459Szrj@table @gcctabopt 57*a9fa9459Szrj@cindex @samp{--32} option, i386 58*a9fa9459Szrj@cindex @samp{--32} option, x86-64 59*a9fa9459Szrj@cindex @samp{--x32} option, i386 60*a9fa9459Szrj@cindex @samp{--x32} option, x86-64 61*a9fa9459Szrj@cindex @samp{--64} option, i386 62*a9fa9459Szrj@cindex @samp{--64} option, x86-64 63*a9fa9459Szrj@item --32 | --x32 | --64 64*a9fa9459SzrjSelect the word size, either 32 bits or 64 bits. @samp{--32} 65*a9fa9459Szrjimplies Intel i386 architecture, while @samp{--x32} and @samp{--64} 66*a9fa9459Szrjimply AMD x86-64 architecture with 32-bit or 64-bit word-size 67*a9fa9459Szrjrespectively. 68*a9fa9459Szrj 69*a9fa9459SzrjThese options are only available with the ELF object file format, and 70*a9fa9459Szrjrequire that the necessary BFD support has been included (on a 32-bit 71*a9fa9459Szrjplatform you have to add --enable-64-bit-bfd to configure enable 64-bit 72*a9fa9459Szrjusage and use x86-64 as target platform). 73*a9fa9459Szrj 74*a9fa9459Szrj@item -n 75*a9fa9459SzrjBy default, x86 GAS replaces multiple nop instructions used for 76*a9fa9459Szrjalignment within code sections with multi-byte nop instructions such 77*a9fa9459Szrjas leal 0(%esi,1),%esi. This switch disables the optimization. 78*a9fa9459Szrj 79*a9fa9459Szrj@cindex @samp{--divide} option, i386 80*a9fa9459Szrj@item --divide 81*a9fa9459SzrjOn SVR4-derived platforms, the character @samp{/} is treated as a comment 82*a9fa9459Szrjcharacter, which means that it cannot be used in expressions. The 83*a9fa9459Szrj@samp{--divide} option turns @samp{/} into a normal character. This does 84*a9fa9459Szrjnot disable @samp{/} at the beginning of a line starting a comment, or 85*a9fa9459Szrjaffect using @samp{#} for starting a comment. 86*a9fa9459Szrj 87*a9fa9459Szrj@cindex @samp{-march=} option, i386 88*a9fa9459Szrj@cindex @samp{-march=} option, x86-64 89*a9fa9459Szrj@item -march=@var{CPU}[+@var{EXTENSION}@dots{}] 90*a9fa9459SzrjThis option specifies the target processor. The assembler will 91*a9fa9459Szrjissue an error message if an attempt is made to assemble an instruction 92*a9fa9459Szrjwhich will not execute on the target processor. The following 93*a9fa9459Szrjprocessor names are recognized: 94*a9fa9459Szrj@code{i8086}, 95*a9fa9459Szrj@code{i186}, 96*a9fa9459Szrj@code{i286}, 97*a9fa9459Szrj@code{i386}, 98*a9fa9459Szrj@code{i486}, 99*a9fa9459Szrj@code{i586}, 100*a9fa9459Szrj@code{i686}, 101*a9fa9459Szrj@code{pentium}, 102*a9fa9459Szrj@code{pentiumpro}, 103*a9fa9459Szrj@code{pentiumii}, 104*a9fa9459Szrj@code{pentiumiii}, 105*a9fa9459Szrj@code{pentium4}, 106*a9fa9459Szrj@code{prescott}, 107*a9fa9459Szrj@code{nocona}, 108*a9fa9459Szrj@code{core}, 109*a9fa9459Szrj@code{core2}, 110*a9fa9459Szrj@code{corei7}, 111*a9fa9459Szrj@code{l1om}, 112*a9fa9459Szrj@code{k1om}, 113*a9fa9459Szrj@code{iamcu}, 114*a9fa9459Szrj@code{k6}, 115*a9fa9459Szrj@code{k6_2}, 116*a9fa9459Szrj@code{athlon}, 117*a9fa9459Szrj@code{opteron}, 118*a9fa9459Szrj@code{k8}, 119*a9fa9459Szrj@code{amdfam10}, 120*a9fa9459Szrj@code{bdver1}, 121*a9fa9459Szrj@code{bdver2}, 122*a9fa9459Szrj@code{bdver3}, 123*a9fa9459Szrj@code{bdver4}, 124*a9fa9459Szrj@code{znver1}, 125*a9fa9459Szrj@code{btver1}, 126*a9fa9459Szrj@code{btver2}, 127*a9fa9459Szrj@code{generic32} and 128*a9fa9459Szrj@code{generic64}. 129*a9fa9459Szrj 130*a9fa9459SzrjIn addition to the basic instruction set, the assembler can be told to 131*a9fa9459Szrjaccept various extension mnemonics. For example, 132*a9fa9459Szrj@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and 133*a9fa9459Szrj@var{vmx}. The following extensions are currently supported: 134*a9fa9459Szrj@code{8087}, 135*a9fa9459Szrj@code{287}, 136*a9fa9459Szrj@code{387}, 137*a9fa9459Szrj@code{687}, 138*a9fa9459Szrj@code{no87}, 139*a9fa9459Szrj@code{no287}, 140*a9fa9459Szrj@code{no387}, 141*a9fa9459Szrj@code{no687}, 142*a9fa9459Szrj@code{mmx}, 143*a9fa9459Szrj@code{nommx}, 144*a9fa9459Szrj@code{sse}, 145*a9fa9459Szrj@code{sse2}, 146*a9fa9459Szrj@code{sse3}, 147*a9fa9459Szrj@code{ssse3}, 148*a9fa9459Szrj@code{sse4.1}, 149*a9fa9459Szrj@code{sse4.2}, 150*a9fa9459Szrj@code{sse4}, 151*a9fa9459Szrj@code{nosse}, 152*a9fa9459Szrj@code{nosse2}, 153*a9fa9459Szrj@code{nosse3}, 154*a9fa9459Szrj@code{nossse3}, 155*a9fa9459Szrj@code{nosse4.1}, 156*a9fa9459Szrj@code{nosse4.2}, 157*a9fa9459Szrj@code{nosse4}, 158*a9fa9459Szrj@code{avx}, 159*a9fa9459Szrj@code{avx2}, 160*a9fa9459Szrj@code{noavx}, 161*a9fa9459Szrj@code{noavx2}, 162*a9fa9459Szrj@code{adx}, 163*a9fa9459Szrj@code{rdseed}, 164*a9fa9459Szrj@code{prfchw}, 165*a9fa9459Szrj@code{smap}, 166*a9fa9459Szrj@code{mpx}, 167*a9fa9459Szrj@code{sha}, 168*a9fa9459Szrj@code{rdpid}, 169*a9fa9459Szrj@code{prefetchwt1}, 170*a9fa9459Szrj@code{clflushopt}, 171*a9fa9459Szrj@code{se1}, 172*a9fa9459Szrj@code{clwb}, 173*a9fa9459Szrj@code{pcommit}, 174*a9fa9459Szrj@code{avx512f}, 175*a9fa9459Szrj@code{avx512cd}, 176*a9fa9459Szrj@code{avx512er}, 177*a9fa9459Szrj@code{avx512pf}, 178*a9fa9459Szrj@code{avx512vl}, 179*a9fa9459Szrj@code{avx512bw}, 180*a9fa9459Szrj@code{avx512dq}, 181*a9fa9459Szrj@code{avx512ifma}, 182*a9fa9459Szrj@code{avx512vbmi}, 183*a9fa9459Szrj@code{noavx512f}, 184*a9fa9459Szrj@code{noavx512cd}, 185*a9fa9459Szrj@code{noavx512er}, 186*a9fa9459Szrj@code{noavx512pf}, 187*a9fa9459Szrj@code{noavx512vl}, 188*a9fa9459Szrj@code{noavx512bw}, 189*a9fa9459Szrj@code{noavx512dq}, 190*a9fa9459Szrj@code{noavx512ifma}, 191*a9fa9459Szrj@code{noavx512vbmi}, 192*a9fa9459Szrj@code{vmx}, 193*a9fa9459Szrj@code{vmfunc}, 194*a9fa9459Szrj@code{smx}, 195*a9fa9459Szrj@code{xsave}, 196*a9fa9459Szrj@code{xsaveopt}, 197*a9fa9459Szrj@code{xsavec}, 198*a9fa9459Szrj@code{xsaves}, 199*a9fa9459Szrj@code{aes}, 200*a9fa9459Szrj@code{pclmul}, 201*a9fa9459Szrj@code{fsgsbase}, 202*a9fa9459Szrj@code{rdrnd}, 203*a9fa9459Szrj@code{f16c}, 204*a9fa9459Szrj@code{bmi2}, 205*a9fa9459Szrj@code{fma}, 206*a9fa9459Szrj@code{movbe}, 207*a9fa9459Szrj@code{ept}, 208*a9fa9459Szrj@code{lzcnt}, 209*a9fa9459Szrj@code{hle}, 210*a9fa9459Szrj@code{rtm}, 211*a9fa9459Szrj@code{invpcid}, 212*a9fa9459Szrj@code{clflush}, 213*a9fa9459Szrj@code{mwaitx}, 214*a9fa9459Szrj@code{clzero}, 215*a9fa9459Szrj@code{lwp}, 216*a9fa9459Szrj@code{fma4}, 217*a9fa9459Szrj@code{xop}, 218*a9fa9459Szrj@code{cx16}, 219*a9fa9459Szrj@code{syscall}, 220*a9fa9459Szrj@code{rdtscp}, 221*a9fa9459Szrj@code{3dnow}, 222*a9fa9459Szrj@code{3dnowa}, 223*a9fa9459Szrj@code{sse4a}, 224*a9fa9459Szrj@code{sse5}, 225*a9fa9459Szrj@code{svme}, 226*a9fa9459Szrj@code{abm} and 227*a9fa9459Szrj@code{padlock}. 228*a9fa9459SzrjNote that rather than extending a basic instruction set, the extension 229*a9fa9459Szrjmnemonics starting with @code{no} revoke the respective functionality. 230*a9fa9459Szrj 231*a9fa9459SzrjWhen the @code{.arch} directive is used with @option{-march}, the 232*a9fa9459Szrj@code{.arch} directive will take precedent. 233*a9fa9459Szrj 234*a9fa9459Szrj@cindex @samp{-mtune=} option, i386 235*a9fa9459Szrj@cindex @samp{-mtune=} option, x86-64 236*a9fa9459Szrj@item -mtune=@var{CPU} 237*a9fa9459SzrjThis option specifies a processor to optimize for. When used in 238*a9fa9459Szrjconjunction with the @option{-march} option, only instructions 239*a9fa9459Szrjof the processor specified by the @option{-march} option will be 240*a9fa9459Szrjgenerated. 241*a9fa9459Szrj 242*a9fa9459SzrjValid @var{CPU} values are identical to the processor list of 243*a9fa9459Szrj@option{-march=@var{CPU}}. 244*a9fa9459Szrj 245*a9fa9459Szrj@cindex @samp{-msse2avx} option, i386 246*a9fa9459Szrj@cindex @samp{-msse2avx} option, x86-64 247*a9fa9459Szrj@item -msse2avx 248*a9fa9459SzrjThis option specifies that the assembler should encode SSE instructions 249*a9fa9459Szrjwith VEX prefix. 250*a9fa9459Szrj 251*a9fa9459Szrj@cindex @samp{-msse-check=} option, i386 252*a9fa9459Szrj@cindex @samp{-msse-check=} option, x86-64 253*a9fa9459Szrj@item -msse-check=@var{none} 254*a9fa9459Szrj@itemx -msse-check=@var{warning} 255*a9fa9459Szrj@itemx -msse-check=@var{error} 256*a9fa9459SzrjThese options control if the assembler should check SSE instructions. 257*a9fa9459Szrj@option{-msse-check=@var{none}} will make the assembler not to check SSE 258*a9fa9459Szrjinstructions, which is the default. @option{-msse-check=@var{warning}} 259*a9fa9459Szrjwill make the assembler issue a warning for any SSE instruction. 260*a9fa9459Szrj@option{-msse-check=@var{error}} will make the assembler issue an error 261*a9fa9459Szrjfor any SSE instruction. 262*a9fa9459Szrj 263*a9fa9459Szrj@cindex @samp{-mavxscalar=} option, i386 264*a9fa9459Szrj@cindex @samp{-mavxscalar=} option, x86-64 265*a9fa9459Szrj@item -mavxscalar=@var{128} 266*a9fa9459Szrj@itemx -mavxscalar=@var{256} 267*a9fa9459SzrjThese options control how the assembler should encode scalar AVX 268*a9fa9459Szrjinstructions. @option{-mavxscalar=@var{128}} will encode scalar 269*a9fa9459SzrjAVX instructions with 128bit vector length, which is the default. 270*a9fa9459Szrj@option{-mavxscalar=@var{256}} will encode scalar AVX instructions 271*a9fa9459Szrjwith 256bit vector length. 272*a9fa9459Szrj 273*a9fa9459Szrj@cindex @samp{-mevexlig=} option, i386 274*a9fa9459Szrj@cindex @samp{-mevexlig=} option, x86-64 275*a9fa9459Szrj@item -mevexlig=@var{128} 276*a9fa9459Szrj@itemx -mevexlig=@var{256} 277*a9fa9459Szrj@itemx -mevexlig=@var{512} 278*a9fa9459SzrjThese options control how the assembler should encode length-ignored 279*a9fa9459Szrj(LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG 280*a9fa9459SzrjEVEX instructions with 128bit vector length, which is the default. 281*a9fa9459Szrj@option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will 282*a9fa9459Szrjencode LIG EVEX instructions with 256bit and 512bit vector length, 283*a9fa9459Szrjrespectively. 284*a9fa9459Szrj 285*a9fa9459Szrj@cindex @samp{-mevexwig=} option, i386 286*a9fa9459Szrj@cindex @samp{-mevexwig=} option, x86-64 287*a9fa9459Szrj@item -mevexwig=@var{0} 288*a9fa9459Szrj@itemx -mevexwig=@var{1} 289*a9fa9459SzrjThese options control how the assembler should encode w-ignored (WIG) 290*a9fa9459SzrjEVEX instructions. @option{-mevexwig=@var{0}} will encode WIG 291*a9fa9459SzrjEVEX instructions with evex.w = 0, which is the default. 292*a9fa9459Szrj@option{-mevexwig=@var{1}} will encode WIG EVEX instructions with 293*a9fa9459Szrjevex.w = 1. 294*a9fa9459Szrj 295*a9fa9459Szrj@cindex @samp{-mmnemonic=} option, i386 296*a9fa9459Szrj@cindex @samp{-mmnemonic=} option, x86-64 297*a9fa9459Szrj@item -mmnemonic=@var{att} 298*a9fa9459Szrj@itemx -mmnemonic=@var{intel} 299*a9fa9459SzrjThis option specifies instruction mnemonic for matching instructions. 300*a9fa9459SzrjThe @code{.att_mnemonic} and @code{.intel_mnemonic} directives will 301*a9fa9459Szrjtake precedent. 302*a9fa9459Szrj 303*a9fa9459Szrj@cindex @samp{-msyntax=} option, i386 304*a9fa9459Szrj@cindex @samp{-msyntax=} option, x86-64 305*a9fa9459Szrj@item -msyntax=@var{att} 306*a9fa9459Szrj@itemx -msyntax=@var{intel} 307*a9fa9459SzrjThis option specifies instruction syntax when processing instructions. 308*a9fa9459SzrjThe @code{.att_syntax} and @code{.intel_syntax} directives will 309*a9fa9459Szrjtake precedent. 310*a9fa9459Szrj 311*a9fa9459Szrj@cindex @samp{-mnaked-reg} option, i386 312*a9fa9459Szrj@cindex @samp{-mnaked-reg} option, x86-64 313*a9fa9459Szrj@item -mnaked-reg 314*a9fa9459SzrjThis opetion specifies that registers don't require a @samp{%} prefix. 315*a9fa9459SzrjThe @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. 316*a9fa9459Szrj 317*a9fa9459Szrj@cindex @samp{-madd-bnd-prefix} option, i386 318*a9fa9459Szrj@cindex @samp{-madd-bnd-prefix} option, x86-64 319*a9fa9459Szrj@item -madd-bnd-prefix 320*a9fa9459SzrjThis option forces the assembler to add BND prefix to all branches, even 321*a9fa9459Szrjif such prefix was not explicitly specified in the source code. 322*a9fa9459Szrj 323*a9fa9459Szrj@cindex @samp{-mshared} option, i386 324*a9fa9459Szrj@cindex @samp{-mshared} option, x86-64 325*a9fa9459Szrj@item -mno-shared 326*a9fa9459SzrjOn ELF target, the assembler normally optimizes out non-PLT relocations 327*a9fa9459Szrjagainst defined non-weak global branch targets with default visibility. 328*a9fa9459SzrjThe @samp{-mshared} option tells the assembler to generate code which 329*a9fa9459Szrjmay go into a shared library where all non-weak global branch targets 330*a9fa9459Szrjwith default visibility can be preempted. The resulting code is 331*a9fa9459Szrjslightly bigger. This option only affects the handling of branch 332*a9fa9459Szrjinstructions. 333*a9fa9459Szrj 334*a9fa9459Szrj@cindex @samp{-mbig-obj} option, x86-64 335*a9fa9459Szrj@item -mbig-obj 336*a9fa9459SzrjOn x86-64 PE/COFF target this option forces the use of big object file 337*a9fa9459Szrjformat, which allows more than 32768 sections. 338*a9fa9459Szrj 339*a9fa9459Szrj@cindex @samp{-momit-lock-prefix=} option, i386 340*a9fa9459Szrj@cindex @samp{-momit-lock-prefix=} option, x86-64 341*a9fa9459Szrj@item -momit-lock-prefix=@var{no} 342*a9fa9459Szrj@itemx -momit-lock-prefix=@var{yes} 343*a9fa9459SzrjThese options control how the assembler should encode lock prefix. 344*a9fa9459SzrjThis option is intended as a workaround for processors, that fail on 345*a9fa9459Szrjlock prefix. This option can only be safely used with single-core, 346*a9fa9459Szrjsingle-thread computers 347*a9fa9459Szrj@option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. 348*a9fa9459Szrj@option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, 349*a9fa9459Szrjwhich is the default. 350*a9fa9459Szrj 351*a9fa9459Szrj@cindex @samp{-mfence-as-lock-add=} option, i386 352*a9fa9459Szrj@cindex @samp{-mfence-as-lock-add=} option, x86-64 353*a9fa9459Szrj@item -mfence-as-lock-add=@var{no} 354*a9fa9459Szrj@itemx -mfence-as-lock-add=@var{yes} 355*a9fa9459SzrjThese options control how the assembler should encode lfence, mfence and 356*a9fa9459Szrjsfence. 357*a9fa9459Szrj@option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and 358*a9fa9459Szrjsfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and 359*a9fa9459Szrj@samp{lock addl $0x0, (%esp)} in 32-bit mode. 360*a9fa9459Szrj@option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and 361*a9fa9459Szrjsfence as usual, which is the default. 362*a9fa9459Szrj 363*a9fa9459Szrj@cindex @samp{-mrelax-relocations=} option, i386 364*a9fa9459Szrj@cindex @samp{-mrelax-relocations=} option, x86-64 365*a9fa9459Szrj@item -mrelax-relocations=@var{no} 366*a9fa9459Szrj@itemx -mrelax-relocations=@var{yes} 367*a9fa9459SzrjThese options control whether the assembler should generate relax 368*a9fa9459Szrjrelocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and 369*a9fa9459SzrjR_X86_64_REX_GOTPCRELX, in 64-bit mode. 370*a9fa9459Szrj@option{-mrelax-relocations=@var{yes}} will generate relax relocations. 371*a9fa9459Szrj@option{-mrelax-relocations=@var{no}} will not generate relax 372*a9fa9459Szrjrelocations. The default can be controlled by a configure option 373*a9fa9459Szrj@option{--enable-x86-relax-relocations}. 374*a9fa9459Szrj 375*a9fa9459Szrj@cindex @samp{-mevexrcig=} option, i386 376*a9fa9459Szrj@cindex @samp{-mevexrcig=} option, x86-64 377*a9fa9459Szrj@item -mevexrcig=@var{rne} 378*a9fa9459Szrj@itemx -mevexrcig=@var{rd} 379*a9fa9459Szrj@itemx -mevexrcig=@var{ru} 380*a9fa9459Szrj@itemx -mevexrcig=@var{rz} 381*a9fa9459SzrjThese options control how the assembler should encode SAE-only 382*a9fa9459SzrjEVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits 383*a9fa9459Szrjof EVEX instruction with 00, which is the default. 384*a9fa9459Szrj@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} 385*a9fa9459Szrjand @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions 386*a9fa9459Szrjwith 01, 10 and 11 RC bits, respectively. 387*a9fa9459Szrj 388*a9fa9459Szrj@cindex @samp{-mamd64} option, x86-64 389*a9fa9459Szrj@cindex @samp{-mintel64} option, x86-64 390*a9fa9459Szrj@item -mamd64 391*a9fa9459Szrj@itemx -mintel64 392*a9fa9459SzrjThis option specifies that the assembler should accept only AMD64 or 393*a9fa9459SzrjIntel64 ISA in 64-bit mode. The default is to accept both. 394*a9fa9459Szrj 395*a9fa9459Szrj@end table 396*a9fa9459Szrj@c man end 397*a9fa9459Szrj 398*a9fa9459Szrj@node i386-Directives 399*a9fa9459Szrj@section x86 specific Directives 400*a9fa9459Szrj 401*a9fa9459Szrj@cindex machine directives, x86 402*a9fa9459Szrj@cindex x86 machine directives 403*a9fa9459Szrj@table @code 404*a9fa9459Szrj 405*a9fa9459Szrj@cindex @code{lcomm} directive, COFF 406*a9fa9459Szrj@item .lcomm @var{symbol} , @var{length}[, @var{alignment}] 407*a9fa9459SzrjReserve @var{length} (an absolute expression) bytes for a local common 408*a9fa9459Szrjdenoted by @var{symbol}. The section and value of @var{symbol} are 409*a9fa9459Szrjthose of the new local common. The addresses are allocated in the bss 410*a9fa9459Szrjsection, so that at run-time the bytes start off zeroed. Since 411*a9fa9459Szrj@var{symbol} is not declared global, it is normally not visible to 412*a9fa9459Szrj@code{@value{LD}}. The optional third parameter, @var{alignment}, 413*a9fa9459Szrjspecifies the desired alignment of the symbol in the bss section. 414*a9fa9459Szrj 415*a9fa9459SzrjThis directive is only available for COFF based x86 targets. 416*a9fa9459Szrj 417*a9fa9459Szrj@c FIXME: Document other x86 specific directives ? Eg: .code16gcc, 418*a9fa9459Szrj@c .largecomm 419*a9fa9459Szrj 420*a9fa9459Szrj@end table 421*a9fa9459Szrj 422*a9fa9459Szrj@node i386-Syntax 423*a9fa9459Szrj@section i386 Syntactical Considerations 424*a9fa9459Szrj@menu 425*a9fa9459Szrj* i386-Variations:: AT&T Syntax versus Intel Syntax 426*a9fa9459Szrj* i386-Chars:: Special Characters 427*a9fa9459Szrj@end menu 428*a9fa9459Szrj 429*a9fa9459Szrj@node i386-Variations 430*a9fa9459Szrj@subsection AT&T Syntax versus Intel Syntax 431*a9fa9459Szrj 432*a9fa9459Szrj@cindex i386 intel_syntax pseudo op 433*a9fa9459Szrj@cindex intel_syntax pseudo op, i386 434*a9fa9459Szrj@cindex i386 att_syntax pseudo op 435*a9fa9459Szrj@cindex att_syntax pseudo op, i386 436*a9fa9459Szrj@cindex i386 syntax compatibility 437*a9fa9459Szrj@cindex syntax compatibility, i386 438*a9fa9459Szrj@cindex x86-64 intel_syntax pseudo op 439*a9fa9459Szrj@cindex intel_syntax pseudo op, x86-64 440*a9fa9459Szrj@cindex x86-64 att_syntax pseudo op 441*a9fa9459Szrj@cindex att_syntax pseudo op, x86-64 442*a9fa9459Szrj@cindex x86-64 syntax compatibility 443*a9fa9459Szrj@cindex syntax compatibility, x86-64 444*a9fa9459Szrj 445*a9fa9459Szrj@code{@value{AS}} now supports assembly using Intel assembler syntax. 446*a9fa9459Szrj@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches 447*a9fa9459Szrjback to the usual AT&T mode for compatibility with the output of 448*a9fa9459Szrj@code{@value{GCC}}. Either of these directives may have an optional 449*a9fa9459Szrjargument, @code{prefix}, or @code{noprefix} specifying whether registers 450*a9fa9459Szrjrequire a @samp{%} prefix. AT&T System V/386 assembler syntax is quite 451*a9fa9459Szrjdifferent from Intel syntax. We mention these differences because 452*a9fa9459Szrjalmost all 80386 documents use Intel syntax. Notable differences 453*a9fa9459Szrjbetween the two syntaxes are: 454*a9fa9459Szrj 455*a9fa9459Szrj@cindex immediate operands, i386 456*a9fa9459Szrj@cindex i386 immediate operands 457*a9fa9459Szrj@cindex register operands, i386 458*a9fa9459Szrj@cindex i386 register operands 459*a9fa9459Szrj@cindex jump/call operands, i386 460*a9fa9459Szrj@cindex i386 jump/call operands 461*a9fa9459Szrj@cindex operand delimiters, i386 462*a9fa9459Szrj 463*a9fa9459Szrj@cindex immediate operands, x86-64 464*a9fa9459Szrj@cindex x86-64 immediate operands 465*a9fa9459Szrj@cindex register operands, x86-64 466*a9fa9459Szrj@cindex x86-64 register operands 467*a9fa9459Szrj@cindex jump/call operands, x86-64 468*a9fa9459Szrj@cindex x86-64 jump/call operands 469*a9fa9459Szrj@cindex operand delimiters, x86-64 470*a9fa9459Szrj@itemize @bullet 471*a9fa9459Szrj@item 472*a9fa9459SzrjAT&T immediate operands are preceded by @samp{$}; Intel immediate 473*a9fa9459Szrjoperands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). 474*a9fa9459SzrjAT&T register operands are preceded by @samp{%}; Intel register operands 475*a9fa9459Szrjare undelimited. AT&T absolute (as opposed to PC relative) jump/call 476*a9fa9459Szrjoperands are prefixed by @samp{*}; they are undelimited in Intel syntax. 477*a9fa9459Szrj 478*a9fa9459Szrj@cindex i386 source, destination operands 479*a9fa9459Szrj@cindex source, destination operands; i386 480*a9fa9459Szrj@cindex x86-64 source, destination operands 481*a9fa9459Szrj@cindex source, destination operands; x86-64 482*a9fa9459Szrj@item 483*a9fa9459SzrjAT&T and Intel syntax use the opposite order for source and destination 484*a9fa9459Szrjoperands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The 485*a9fa9459Szrj@samp{source, dest} convention is maintained for compatibility with 486*a9fa9459Szrjprevious Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and 487*a9fa9459Szrjinstructions with 2 immediate operands, such as the @samp{enter} 488*a9fa9459Szrjinstruction, do @emph{not} have reversed order. @ref{i386-Bugs}. 489*a9fa9459Szrj 490*a9fa9459Szrj@cindex mnemonic suffixes, i386 491*a9fa9459Szrj@cindex sizes operands, i386 492*a9fa9459Szrj@cindex i386 size suffixes 493*a9fa9459Szrj@cindex mnemonic suffixes, x86-64 494*a9fa9459Szrj@cindex sizes operands, x86-64 495*a9fa9459Szrj@cindex x86-64 size suffixes 496*a9fa9459Szrj@item 497*a9fa9459SzrjIn AT&T syntax the size of memory operands is determined from the last 498*a9fa9459Szrjcharacter of the instruction mnemonic. Mnemonic suffixes of @samp{b}, 499*a9fa9459Szrj@samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long 500*a9fa9459Szrj(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes 501*a9fa9459Szrjthis by prefixing memory operands (@emph{not} the instruction mnemonics) with 502*a9fa9459Szrj@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus, 503*a9fa9459SzrjIntel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T 504*a9fa9459Szrjsyntax. 505*a9fa9459Szrj 506*a9fa9459SzrjIn 64-bit code, @samp{movabs} can be used to encode the @samp{mov} 507*a9fa9459Szrjinstruction with the 64-bit displacement or immediate operand. 508*a9fa9459Szrj 509*a9fa9459Szrj@cindex return instructions, i386 510*a9fa9459Szrj@cindex i386 jump, call, return 511*a9fa9459Szrj@cindex return instructions, x86-64 512*a9fa9459Szrj@cindex x86-64 jump, call, return 513*a9fa9459Szrj@item 514*a9fa9459SzrjImmediate form long jumps and calls are 515*a9fa9459Szrj@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the 516*a9fa9459SzrjIntel syntax is 517*a9fa9459Szrj@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return 518*a9fa9459Szrjinstruction 519*a9fa9459Szrjis @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is 520*a9fa9459Szrj@samp{ret far @var{stack-adjust}}. 521*a9fa9459Szrj 522*a9fa9459Szrj@cindex sections, i386 523*a9fa9459Szrj@cindex i386 sections 524*a9fa9459Szrj@cindex sections, x86-64 525*a9fa9459Szrj@cindex x86-64 sections 526*a9fa9459Szrj@item 527*a9fa9459SzrjThe AT&T assembler does not provide support for multiple section 528*a9fa9459Szrjprograms. Unix style systems expect all programs to be single sections. 529*a9fa9459Szrj@end itemize 530*a9fa9459Szrj 531*a9fa9459Szrj@node i386-Chars 532*a9fa9459Szrj@subsection Special Characters 533*a9fa9459Szrj 534*a9fa9459Szrj@cindex line comment character, i386 535*a9fa9459Szrj@cindex i386 line comment character 536*a9fa9459SzrjThe presence of a @samp{#} appearing anywhere on a line indicates the 537*a9fa9459Szrjstart of a comment that extends to the end of that line. 538*a9fa9459Szrj 539*a9fa9459SzrjIf a @samp{#} appears as the first character of a line then the whole 540*a9fa9459Szrjline is treated as a comment, but in this case the line can also be a 541*a9fa9459Szrjlogical line number directive (@pxref{Comments}) or a preprocessor 542*a9fa9459Szrjcontrol command (@pxref{Preprocessing}). 543*a9fa9459Szrj 544*a9fa9459SzrjIf the @option{--divide} command line option has not been specified 545*a9fa9459Szrjthen the @samp{/} character appearing anywhere on a line also 546*a9fa9459Szrjintroduces a line comment. 547*a9fa9459Szrj 548*a9fa9459Szrj@cindex line separator, i386 549*a9fa9459Szrj@cindex statement separator, i386 550*a9fa9459Szrj@cindex i386 line separator 551*a9fa9459SzrjThe @samp{;} character can be used to separate statements on the same 552*a9fa9459Szrjline. 553*a9fa9459Szrj 554*a9fa9459Szrj@node i386-Mnemonics 555*a9fa9459Szrj@section i386-Mnemonics 556*a9fa9459Szrj@subsection Instruction Naming 557*a9fa9459Szrj 558*a9fa9459Szrj@cindex i386 instruction naming 559*a9fa9459Szrj@cindex instruction naming, i386 560*a9fa9459Szrj@cindex x86-64 instruction naming 561*a9fa9459Szrj@cindex instruction naming, x86-64 562*a9fa9459Szrj 563*a9fa9459SzrjInstruction mnemonics are suffixed with one character modifiers which 564*a9fa9459Szrjspecify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} 565*a9fa9459Szrjand @samp{q} specify byte, word, long and quadruple word operands. If 566*a9fa9459Szrjno suffix is specified by an instruction then @code{@value{AS}} tries to 567*a9fa9459Szrjfill in the missing suffix based on the destination register operand 568*a9fa9459Szrj(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent 569*a9fa9459Szrjto @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to 570*a9fa9459Szrj@samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix 571*a9fa9459Szrjassembler which assumes that a missing mnemonic suffix implies long 572*a9fa9459Szrjoperand size. (This incompatibility does not affect compiler output 573*a9fa9459Szrjsince compilers always explicitly specify the mnemonic suffix.) 574*a9fa9459Szrj 575*a9fa9459SzrjAlmost all instructions have the same names in AT&T and Intel format. 576*a9fa9459SzrjThere are a few exceptions. The sign extend and zero extend 577*a9fa9459Szrjinstructions need two sizes to specify them. They need a size to 578*a9fa9459Szrjsign/zero extend @emph{from} and a size to zero extend @emph{to}. This 579*a9fa9459Szrjis accomplished by using two instruction mnemonic suffixes in AT&T 580*a9fa9459Szrjsyntax. Base names for sign extend and zero extend are 581*a9fa9459Szrj@samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} 582*a9fa9459Szrjand @samp{movzx} in Intel syntax). The instruction mnemonic suffixes 583*a9fa9459Szrjare tacked on to this base name, the @emph{from} suffix before the 584*a9fa9459Szrj@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for 585*a9fa9459Szrj``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, 586*a9fa9459Szrjthus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), 587*a9fa9459Szrj@samp{wl} (from word to long), @samp{bq} (from byte to quadruple word), 588*a9fa9459Szrj@samp{wq} (from word to quadruple word), and @samp{lq} (from long to 589*a9fa9459Szrjquadruple word). 590*a9fa9459Szrj 591*a9fa9459Szrj@cindex encoding options, i386 592*a9fa9459Szrj@cindex encoding options, x86-64 593*a9fa9459Szrj 594*a9fa9459SzrjDifferent encoding options can be specified via optional mnemonic 595*a9fa9459Szrjsuffix. @samp{.s} suffix swaps 2 register operands in encoding when 596*a9fa9459Szrjmoving from one register to another. @samp{.d8} or @samp{.d32} suffix 597*a9fa9459Szrjprefers 8bit or 32bit displacement in encoding. 598*a9fa9459Szrj 599*a9fa9459Szrj@cindex conversion instructions, i386 600*a9fa9459Szrj@cindex i386 conversion instructions 601*a9fa9459Szrj@cindex conversion instructions, x86-64 602*a9fa9459Szrj@cindex x86-64 conversion instructions 603*a9fa9459SzrjThe Intel-syntax conversion instructions 604*a9fa9459Szrj 605*a9fa9459Szrj@itemize @bullet 606*a9fa9459Szrj@item 607*a9fa9459Szrj@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, 608*a9fa9459Szrj 609*a9fa9459Szrj@item 610*a9fa9459Szrj@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, 611*a9fa9459Szrj 612*a9fa9459Szrj@item 613*a9fa9459Szrj@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, 614*a9fa9459Szrj 615*a9fa9459Szrj@item 616*a9fa9459Szrj@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, 617*a9fa9459Szrj 618*a9fa9459Szrj@item 619*a9fa9459Szrj@samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} 620*a9fa9459Szrj(x86-64 only), 621*a9fa9459Szrj 622*a9fa9459Szrj@item 623*a9fa9459Szrj@samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in 624*a9fa9459Szrj@samp{%rdx:%rax} (x86-64 only), 625*a9fa9459Szrj@end itemize 626*a9fa9459Szrj 627*a9fa9459Szrj@noindent 628*a9fa9459Szrjare called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and 629*a9fa9459Szrj@samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these 630*a9fa9459Szrjinstructions. 631*a9fa9459Szrj 632*a9fa9459Szrj@cindex jump instructions, i386 633*a9fa9459Szrj@cindex call instructions, i386 634*a9fa9459Szrj@cindex jump instructions, x86-64 635*a9fa9459Szrj@cindex call instructions, x86-64 636*a9fa9459SzrjFar call/jump instructions are @samp{lcall} and @samp{ljmp} in 637*a9fa9459SzrjAT&T syntax, but are @samp{call far} and @samp{jump far} in Intel 638*a9fa9459Szrjconvention. 639*a9fa9459Szrj 640*a9fa9459Szrj@subsection AT&T Mnemonic versus Intel Mnemonic 641*a9fa9459Szrj 642*a9fa9459Szrj@cindex i386 mnemonic compatibility 643*a9fa9459Szrj@cindex mnemonic compatibility, i386 644*a9fa9459Szrj 645*a9fa9459Szrj@code{@value{AS}} supports assembly using Intel mnemonic. 646*a9fa9459Szrj@code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and 647*a9fa9459Szrj@code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T 648*a9fa9459Szrjsyntax for compatibility with the output of @code{@value{GCC}}. 649*a9fa9459SzrjSeveral x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, 650*a9fa9459Szrj@samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, 651*a9fa9459Szrj@samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 652*a9fa9459Szrjassembler with different mnemonics from those in Intel IA32 specification. 653*a9fa9459Szrj@code{@value{GCC}} generates those instructions with AT&T mnemonic. 654*a9fa9459Szrj 655*a9fa9459Szrj@node i386-Regs 656*a9fa9459Szrj@section Register Naming 657*a9fa9459Szrj 658*a9fa9459Szrj@cindex i386 registers 659*a9fa9459Szrj@cindex registers, i386 660*a9fa9459Szrj@cindex x86-64 registers 661*a9fa9459Szrj@cindex registers, x86-64 662*a9fa9459SzrjRegister operands are always prefixed with @samp{%}. The 80386 registers 663*a9fa9459Szrjconsist of 664*a9fa9459Szrj 665*a9fa9459Szrj@itemize @bullet 666*a9fa9459Szrj@item 667*a9fa9459Szrjthe 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, 668*a9fa9459Szrj@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the 669*a9fa9459Szrjframe pointer), and @samp{%esp} (the stack pointer). 670*a9fa9459Szrj 671*a9fa9459Szrj@item 672*a9fa9459Szrjthe 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, 673*a9fa9459Szrj@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. 674*a9fa9459Szrj 675*a9fa9459Szrj@item 676*a9fa9459Szrjthe 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, 677*a9fa9459Szrj@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These 678*a9fa9459Szrjare the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, 679*a9fa9459Szrj@samp{%cx}, and @samp{%dx}) 680*a9fa9459Szrj 681*a9fa9459Szrj@item 682*a9fa9459Szrjthe 6 section registers @samp{%cs} (code section), @samp{%ds} 683*a9fa9459Szrj(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, 684*a9fa9459Szrjand @samp{%gs}. 685*a9fa9459Szrj 686*a9fa9459Szrj@item 687*a9fa9459Szrjthe 5 processor control registers @samp{%cr0}, @samp{%cr2}, 688*a9fa9459Szrj@samp{%cr3}, @samp{%cr4}, and @samp{%cr8}. 689*a9fa9459Szrj 690*a9fa9459Szrj@item 691*a9fa9459Szrjthe 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, 692*a9fa9459Szrj@samp{%db3}, @samp{%db6}, and @samp{%db7}. 693*a9fa9459Szrj 694*a9fa9459Szrj@item 695*a9fa9459Szrjthe 2 test registers @samp{%tr6} and @samp{%tr7}. 696*a9fa9459Szrj 697*a9fa9459Szrj@item 698*a9fa9459Szrjthe 8 floating point register stack @samp{%st} or equivalently 699*a9fa9459Szrj@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, 700*a9fa9459Szrj@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. 701*a9fa9459SzrjThese registers are overloaded by 8 MMX registers @samp{%mm0}, 702*a9fa9459Szrj@samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, 703*a9fa9459Szrj@samp{%mm6} and @samp{%mm7}. 704*a9fa9459Szrj 705*a9fa9459Szrj@item 706*a9fa9459Szrjthe 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, 707*a9fa9459Szrj@samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. 708*a9fa9459Szrj@end itemize 709*a9fa9459Szrj 710*a9fa9459SzrjThe AMD x86-64 architecture extends the register set by: 711*a9fa9459Szrj 712*a9fa9459Szrj@itemize @bullet 713*a9fa9459Szrj@item 714*a9fa9459Szrjenhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the 715*a9fa9459Szrjaccumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, 716*a9fa9459Szrj@samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack 717*a9fa9459Szrjpointer) 718*a9fa9459Szrj 719*a9fa9459Szrj@item 720*a9fa9459Szrjthe 8 extended registers @samp{%r8}--@samp{%r15}. 721*a9fa9459Szrj 722*a9fa9459Szrj@item 723*a9fa9459Szrjthe 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}. 724*a9fa9459Szrj 725*a9fa9459Szrj@item 726*a9fa9459Szrjthe 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}. 727*a9fa9459Szrj 728*a9fa9459Szrj@item 729*a9fa9459Szrjthe 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}. 730*a9fa9459Szrj 731*a9fa9459Szrj@item 732*a9fa9459Szrjthe 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. 733*a9fa9459Szrj 734*a9fa9459Szrj@item 735*a9fa9459Szrjthe 8 debug registers: @samp{%db8}--@samp{%db15}. 736*a9fa9459Szrj 737*a9fa9459Szrj@item 738*a9fa9459Szrjthe 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}. 739*a9fa9459Szrj@end itemize 740*a9fa9459Szrj 741*a9fa9459SzrjWith the AVX extensions more registers were made available: 742*a9fa9459Szrj 743*a9fa9459Szrj@itemize @bullet 744*a9fa9459Szrj 745*a9fa9459Szrj@item 746*a9fa9459Szrjthe 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8 747*a9fa9459Szrjavailable in 32-bit mode). The bottom 128 bits are overlaid with the 748*a9fa9459Szrj@samp{xmm0}--@samp{xmm15} registers. 749*a9fa9459Szrj 750*a9fa9459Szrj@end itemize 751*a9fa9459Szrj 752*a9fa9459SzrjThe AVX2 extensions made in 64-bit mode more registers available: 753*a9fa9459Szrj 754*a9fa9459Szrj@itemize @bullet 755*a9fa9459Szrj 756*a9fa9459Szrj@item 757*a9fa9459Szrjthe 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit 758*a9fa9459Szrjregisters @samp{%ymm16}--@samp{%ymm31}. 759*a9fa9459Szrj 760*a9fa9459Szrj@end itemize 761*a9fa9459Szrj 762*a9fa9459SzrjThe AVX512 extensions added the following registers: 763*a9fa9459Szrj 764*a9fa9459Szrj@itemize @bullet 765*a9fa9459Szrj 766*a9fa9459Szrj@item 767*a9fa9459Szrjthe 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8 768*a9fa9459Szrjavailable in 32-bit mode). The bottom 128 bits are overlaid with the 769*a9fa9459Szrj@samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are 770*a9fa9459Szrjoverlaid with the @samp{%ymm0}--@samp{%ymm31} registers. 771*a9fa9459Szrj 772*a9fa9459Szrj@item 773*a9fa9459Szrjthe 8 mask registers @samp{%k0}--@samp{%k7}. 774*a9fa9459Szrj 775*a9fa9459Szrj@end itemize 776*a9fa9459Szrj 777*a9fa9459Szrj@node i386-Prefixes 778*a9fa9459Szrj@section Instruction Prefixes 779*a9fa9459Szrj 780*a9fa9459Szrj@cindex i386 instruction prefixes 781*a9fa9459Szrj@cindex instruction prefixes, i386 782*a9fa9459Szrj@cindex prefixes, i386 783*a9fa9459SzrjInstruction prefixes are used to modify the following instruction. They 784*a9fa9459Szrjare used to repeat string instructions, to provide section overrides, to 785*a9fa9459Szrjperform bus lock operations, and to change operand and address sizes. 786*a9fa9459Szrj(Most instructions that normally operate on 32-bit operands will use 787*a9fa9459Szrj16-bit operands if the instruction has an ``operand size'' prefix.) 788*a9fa9459SzrjInstruction prefixes are best written on the same line as the instruction 789*a9fa9459Szrjthey act upon. For example, the @samp{scas} (scan string) instruction is 790*a9fa9459Szrjrepeated with: 791*a9fa9459Szrj 792*a9fa9459Szrj@smallexample 793*a9fa9459Szrj repne scas %es:(%edi),%al 794*a9fa9459Szrj@end smallexample 795*a9fa9459Szrj 796*a9fa9459SzrjYou may also place prefixes on the lines immediately preceding the 797*a9fa9459Szrjinstruction, but this circumvents checks that @code{@value{AS}} does 798*a9fa9459Szrjwith prefixes, and will not work with all prefixes. 799*a9fa9459Szrj 800*a9fa9459SzrjHere is a list of instruction prefixes: 801*a9fa9459Szrj 802*a9fa9459Szrj@cindex section override prefixes, i386 803*a9fa9459Szrj@itemize @bullet 804*a9fa9459Szrj@item 805*a9fa9459SzrjSection override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, 806*a9fa9459Szrj@samp{fs}, @samp{gs}. These are automatically added by specifying 807*a9fa9459Szrjusing the @var{section}:@var{memory-operand} form for memory references. 808*a9fa9459Szrj 809*a9fa9459Szrj@cindex size prefixes, i386 810*a9fa9459Szrj@item 811*a9fa9459SzrjOperand/Address size prefixes @samp{data16} and @samp{addr16} 812*a9fa9459Szrjchange 32-bit operands/addresses into 16-bit operands/addresses, 813*a9fa9459Szrjwhile @samp{data32} and @samp{addr32} change 16-bit ones (in a 814*a9fa9459Szrj@code{.code16} section) into 32-bit operands/addresses. These prefixes 815*a9fa9459Szrj@emph{must} appear on the same line of code as the instruction they 816*a9fa9459Szrjmodify. For example, in a 16-bit @code{.code16} section, you might 817*a9fa9459Szrjwrite: 818*a9fa9459Szrj 819*a9fa9459Szrj@smallexample 820*a9fa9459Szrj addr32 jmpl *(%ebx) 821*a9fa9459Szrj@end smallexample 822*a9fa9459Szrj 823*a9fa9459Szrj@cindex bus lock prefixes, i386 824*a9fa9459Szrj@cindex inhibiting interrupts, i386 825*a9fa9459Szrj@item 826*a9fa9459SzrjThe bus lock prefix @samp{lock} inhibits interrupts during execution of 827*a9fa9459Szrjthe instruction it precedes. (This is only valid with certain 828*a9fa9459Szrjinstructions; see a 80386 manual for details). 829*a9fa9459Szrj 830*a9fa9459Szrj@cindex coprocessor wait, i386 831*a9fa9459Szrj@item 832*a9fa9459SzrjThe wait for coprocessor prefix @samp{wait} waits for the coprocessor to 833*a9fa9459Szrjcomplete the current instruction. This should never be needed for the 834*a9fa9459Szrj80386/80387 combination. 835*a9fa9459Szrj 836*a9fa9459Szrj@cindex repeat prefixes, i386 837*a9fa9459Szrj@item 838*a9fa9459SzrjThe @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added 839*a9fa9459Szrjto string instructions to make them repeat @samp{%ecx} times (@samp{%cx} 840*a9fa9459Szrjtimes if the current address size is 16-bits). 841*a9fa9459Szrj@cindex REX prefixes, i386 842*a9fa9459Szrj@item 843*a9fa9459SzrjThe @samp{rex} family of prefixes is used by x86-64 to encode 844*a9fa9459Szrjextensions to i386 instruction set. The @samp{rex} prefix has four 845*a9fa9459Szrjbits --- an operand size overwrite (@code{64}) used to change operand size 846*a9fa9459Szrjfrom 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 847*a9fa9459Szrjregister set. 848*a9fa9459Szrj 849*a9fa9459SzrjYou may write the @samp{rex} prefixes directly. The @samp{rex64xyz} 850*a9fa9459Szrjinstruction emits @samp{rex} prefix with all the bits set. By omitting 851*a9fa9459Szrjthe @code{64}, @code{x}, @code{y} or @code{z} you may write other 852*a9fa9459Szrjprefixes as well. Normally, there is no need to write the prefixes 853*a9fa9459Szrjexplicitly, since gas will automatically generate them based on the 854*a9fa9459Szrjinstruction operands. 855*a9fa9459Szrj@end itemize 856*a9fa9459Szrj 857*a9fa9459Szrj@node i386-Memory 858*a9fa9459Szrj@section Memory References 859*a9fa9459Szrj 860*a9fa9459Szrj@cindex i386 memory references 861*a9fa9459Szrj@cindex memory references, i386 862*a9fa9459Szrj@cindex x86-64 memory references 863*a9fa9459Szrj@cindex memory references, x86-64 864*a9fa9459SzrjAn Intel syntax indirect memory reference of the form 865*a9fa9459Szrj 866*a9fa9459Szrj@smallexample 867*a9fa9459Szrj@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] 868*a9fa9459Szrj@end smallexample 869*a9fa9459Szrj 870*a9fa9459Szrj@noindent 871*a9fa9459Szrjis translated into the AT&T syntax 872*a9fa9459Szrj 873*a9fa9459Szrj@smallexample 874*a9fa9459Szrj@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) 875*a9fa9459Szrj@end smallexample 876*a9fa9459Szrj 877*a9fa9459Szrj@noindent 878*a9fa9459Szrjwhere @var{base} and @var{index} are the optional 32-bit base and 879*a9fa9459Szrjindex registers, @var{disp} is the optional displacement, and 880*a9fa9459Szrj@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} 881*a9fa9459Szrjto calculate the address of the operand. If no @var{scale} is 882*a9fa9459Szrjspecified, @var{scale} is taken to be 1. @var{section} specifies the 883*a9fa9459Szrjoptional section register for the memory operand, and may override the 884*a9fa9459Szrjdefault section register (see a 80386 manual for section register 885*a9fa9459Szrjdefaults). Note that section overrides in AT&T syntax @emph{must} 886*a9fa9459Szrjbe preceded by a @samp{%}. If you specify a section override which 887*a9fa9459Szrjcoincides with the default section register, @code{@value{AS}} does @emph{not} 888*a9fa9459Szrjoutput any section register override prefixes to assemble the given 889*a9fa9459Szrjinstruction. Thus, section overrides can be specified to emphasize which 890*a9fa9459Szrjsection register is used for a given memory operand. 891*a9fa9459Szrj 892*a9fa9459SzrjHere are some examples of Intel and AT&T style memory references: 893*a9fa9459Szrj 894*a9fa9459Szrj@table @asis 895*a9fa9459Szrj@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} 896*a9fa9459Szrj@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is 897*a9fa9459Szrjmissing, and the default section is used (@samp{%ss} for addressing with 898*a9fa9459Szrj@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. 899*a9fa9459Szrj 900*a9fa9459Szrj@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} 901*a9fa9459Szrj@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is 902*a9fa9459Szrj@samp{foo}. All other fields are missing. The section register here 903*a9fa9459Szrjdefaults to @samp{%ds}. 904*a9fa9459Szrj 905*a9fa9459Szrj@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} 906*a9fa9459SzrjThis uses the value pointed to by @samp{foo} as a memory operand. 907*a9fa9459SzrjNote that @var{base} and @var{index} are both missing, but there is only 908*a9fa9459Szrj@emph{one} @samp{,}. This is a syntactic exception. 909*a9fa9459Szrj 910*a9fa9459Szrj@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} 911*a9fa9459SzrjThis selects the contents of the variable @samp{foo} with section 912*a9fa9459Szrjregister @var{section} being @samp{%gs}. 913*a9fa9459Szrj@end table 914*a9fa9459Szrj 915*a9fa9459SzrjAbsolute (as opposed to PC relative) call and jump operands must be 916*a9fa9459Szrjprefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} 917*a9fa9459Szrjalways chooses PC relative addressing for jump/call labels. 918*a9fa9459Szrj 919*a9fa9459SzrjAny instruction that has a memory operand, but no register operand, 920*a9fa9459Szrj@emph{must} specify its size (byte, word, long, or quadruple) with an 921*a9fa9459Szrjinstruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, 922*a9fa9459Szrjrespectively). 923*a9fa9459Szrj 924*a9fa9459SzrjThe x86-64 architecture adds an RIP (instruction pointer relative) 925*a9fa9459Szrjaddressing. This addressing mode is specified by using @samp{rip} as a 926*a9fa9459Szrjbase register. Only constant offsets are valid. For example: 927*a9fa9459Szrj 928*a9fa9459Szrj@table @asis 929*a9fa9459Szrj@item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} 930*a9fa9459SzrjPoints to the address 1234 bytes past the end of the current 931*a9fa9459Szrjinstruction. 932*a9fa9459Szrj 933*a9fa9459Szrj@item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} 934*a9fa9459SzrjPoints to the @code{symbol} in RIP relative way, this is shorter than 935*a9fa9459Szrjthe default absolute addressing. 936*a9fa9459Szrj@end table 937*a9fa9459Szrj 938*a9fa9459SzrjOther addressing modes remain unchanged in x86-64 architecture, except 939*a9fa9459Szrjregisters used are 64-bit instead of 32-bit. 940*a9fa9459Szrj 941*a9fa9459Szrj@node i386-Jumps 942*a9fa9459Szrj@section Handling of Jump Instructions 943*a9fa9459Szrj 944*a9fa9459Szrj@cindex jump optimization, i386 945*a9fa9459Szrj@cindex i386 jump optimization 946*a9fa9459Szrj@cindex jump optimization, x86-64 947*a9fa9459Szrj@cindex x86-64 jump optimization 948*a9fa9459SzrjJump instructions are always optimized to use the smallest possible 949*a9fa9459Szrjdisplacements. This is accomplished by using byte (8-bit) displacement 950*a9fa9459Szrjjumps whenever the target is sufficiently close. If a byte displacement 951*a9fa9459Szrjis insufficient a long displacement is used. We do not support 952*a9fa9459Szrjword (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 953*a9fa9459Szrjinstruction with the @samp{data16} instruction prefix), since the 80386 954*a9fa9459Szrjinsists upon masking @samp{%eip} to 16 bits after the word displacement 955*a9fa9459Szrjis added. (See also @pxref{i386-Arch}) 956*a9fa9459Szrj 957*a9fa9459SzrjNote that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, 958*a9fa9459Szrj@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte 959*a9fa9459Szrjdisplacements, so that if you use these instructions (@code{@value{GCC}} does 960*a9fa9459Szrjnot use them) you may get an error message (and incorrect code). The AT&T 961*a9fa9459Szrj80386 assembler tries to get around this problem by expanding @samp{jcxz foo} 962*a9fa9459Szrjto 963*a9fa9459Szrj 964*a9fa9459Szrj@smallexample 965*a9fa9459Szrj jcxz cx_zero 966*a9fa9459Szrj jmp cx_nonzero 967*a9fa9459Szrjcx_zero: jmp foo 968*a9fa9459Szrjcx_nonzero: 969*a9fa9459Szrj@end smallexample 970*a9fa9459Szrj 971*a9fa9459Szrj@node i386-Float 972*a9fa9459Szrj@section Floating Point 973*a9fa9459Szrj 974*a9fa9459Szrj@cindex i386 floating point 975*a9fa9459Szrj@cindex floating point, i386 976*a9fa9459Szrj@cindex x86-64 floating point 977*a9fa9459Szrj@cindex floating point, x86-64 978*a9fa9459SzrjAll 80387 floating point types except packed BCD are supported. 979*a9fa9459Szrj(BCD support may be added without much difficulty). These data 980*a9fa9459Szrjtypes are 16-, 32-, and 64- bit integers, and single (32-bit), 981*a9fa9459Szrjdouble (64-bit), and extended (80-bit) precision floating point. 982*a9fa9459SzrjEach supported type has an instruction mnemonic suffix and a constructor 983*a9fa9459Szrjassociated with it. Instruction mnemonic suffixes specify the operand's 984*a9fa9459Szrjdata type. Constructors build these data types into memory. 985*a9fa9459Szrj 986*a9fa9459Szrj@cindex @code{float} directive, i386 987*a9fa9459Szrj@cindex @code{single} directive, i386 988*a9fa9459Szrj@cindex @code{double} directive, i386 989*a9fa9459Szrj@cindex @code{tfloat} directive, i386 990*a9fa9459Szrj@cindex @code{float} directive, x86-64 991*a9fa9459Szrj@cindex @code{single} directive, x86-64 992*a9fa9459Szrj@cindex @code{double} directive, x86-64 993*a9fa9459Szrj@cindex @code{tfloat} directive, x86-64 994*a9fa9459Szrj@itemize @bullet 995*a9fa9459Szrj@item 996*a9fa9459SzrjFloating point constructors are @samp{.float} or @samp{.single}, 997*a9fa9459Szrj@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. 998*a9fa9459SzrjThese correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, 999*a9fa9459Szrjand @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 1000*a9fa9459Szrjonly supports this format via the @samp{fldt} (load 80-bit real to stack 1001*a9fa9459Szrjtop) and @samp{fstpt} (store 80-bit real and pop stack) instructions. 1002*a9fa9459Szrj 1003*a9fa9459Szrj@cindex @code{word} directive, i386 1004*a9fa9459Szrj@cindex @code{long} directive, i386 1005*a9fa9459Szrj@cindex @code{int} directive, i386 1006*a9fa9459Szrj@cindex @code{quad} directive, i386 1007*a9fa9459Szrj@cindex @code{word} directive, x86-64 1008*a9fa9459Szrj@cindex @code{long} directive, x86-64 1009*a9fa9459Szrj@cindex @code{int} directive, x86-64 1010*a9fa9459Szrj@cindex @code{quad} directive, x86-64 1011*a9fa9459Szrj@item 1012*a9fa9459SzrjInteger constructors are @samp{.word}, @samp{.long} or @samp{.int}, and 1013*a9fa9459Szrj@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The 1014*a9fa9459Szrjcorresponding instruction mnemonic suffixes are @samp{s} (single), 1015*a9fa9459Szrj@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, 1016*a9fa9459Szrjthe 64-bit @samp{q} format is only present in the @samp{fildq} (load 1017*a9fa9459Szrjquad integer to stack top) and @samp{fistpq} (store quad integer and pop 1018*a9fa9459Szrjstack) instructions. 1019*a9fa9459Szrj@end itemize 1020*a9fa9459Szrj 1021*a9fa9459SzrjRegister to register operations should not use instruction mnemonic suffixes. 1022*a9fa9459Szrj@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you 1023*a9fa9459Szrjwrote @samp{fst %st, %st(1)}, since all register to register operations 1024*a9fa9459Szrjuse 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, 1025*a9fa9459Szrjwhich converts @samp{%st} from 80-bit to 64-bit floating point format, 1026*a9fa9459Szrjthen stores the result in the 4 byte location @samp{mem}) 1027*a9fa9459Szrj 1028*a9fa9459Szrj@node i386-SIMD 1029*a9fa9459Szrj@section Intel's MMX and AMD's 3DNow! SIMD Operations 1030*a9fa9459Szrj 1031*a9fa9459Szrj@cindex MMX, i386 1032*a9fa9459Szrj@cindex 3DNow!, i386 1033*a9fa9459Szrj@cindex SIMD, i386 1034*a9fa9459Szrj@cindex MMX, x86-64 1035*a9fa9459Szrj@cindex 3DNow!, x86-64 1036*a9fa9459Szrj@cindex SIMD, x86-64 1037*a9fa9459Szrj 1038*a9fa9459Szrj@code{@value{AS}} supports Intel's MMX instruction set (SIMD 1039*a9fa9459Szrjinstructions for integer data), available on Intel's Pentium MMX 1040*a9fa9459Szrjprocessors and Pentium II processors, AMD's K6 and K6-2 processors, 1041*a9fa9459SzrjCyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: 1042*a9fa9459Szrjinstruction set (SIMD instructions for 32-bit floating point data) 1043*a9fa9459Szrjavailable on AMD's K6-2 processor and possibly others in the future. 1044*a9fa9459Szrj 1045*a9fa9459SzrjCurrently, @code{@value{AS}} does not support Intel's floating point 1046*a9fa9459SzrjSIMD, Katmai (KNI). 1047*a9fa9459Szrj 1048*a9fa9459SzrjThe eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, 1049*a9fa9459Szrj@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four 1050*a9fa9459Szrj16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 1051*a9fa9459Szrjfloating point values. The MMX registers cannot be used at the same time 1052*a9fa9459Szrjas the floating point stack. 1053*a9fa9459Szrj 1054*a9fa9459SzrjSee Intel and AMD documentation, keeping in mind that the operand order in 1055*a9fa9459Szrjinstructions is reversed from the Intel syntax. 1056*a9fa9459Szrj 1057*a9fa9459Szrj@node i386-LWP 1058*a9fa9459Szrj@section AMD's Lightweight Profiling Instructions 1059*a9fa9459Szrj 1060*a9fa9459Szrj@cindex LWP, i386 1061*a9fa9459Szrj@cindex LWP, x86-64 1062*a9fa9459Szrj 1063*a9fa9459Szrj@code{@value{AS}} supports AMD's Lightweight Profiling (LWP) 1064*a9fa9459Szrjinstruction set, available on AMD's Family 15h (Orochi) processors. 1065*a9fa9459Szrj 1066*a9fa9459SzrjLWP enables applications to collect and manage performance data, and 1067*a9fa9459Szrjreact to performance events. The collection of performance data 1068*a9fa9459Szrjrequires no context switches. LWP runs in the context of a thread and 1069*a9fa9459Szrjso several counters can be used independently across multiple threads. 1070*a9fa9459SzrjLWP can be used in both 64-bit and legacy 32-bit modes. 1071*a9fa9459Szrj 1072*a9fa9459SzrjFor detailed information on the LWP instruction set, see the 1073*a9fa9459Szrj@cite{AMD Lightweight Profiling Specification} available at 1074*a9fa9459Szrj@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. 1075*a9fa9459Szrj 1076*a9fa9459Szrj@node i386-BMI 1077*a9fa9459Szrj@section Bit Manipulation Instructions 1078*a9fa9459Szrj 1079*a9fa9459Szrj@cindex BMI, i386 1080*a9fa9459Szrj@cindex BMI, x86-64 1081*a9fa9459Szrj 1082*a9fa9459Szrj@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set. 1083*a9fa9459Szrj 1084*a9fa9459SzrjBMI instructions provide several instructions implementing individual 1085*a9fa9459Szrjbit manipulation operations such as isolation, masking, setting, or 1086*a9fa9459Szrjresetting. 1087*a9fa9459Szrj 1088*a9fa9459Szrj@c Need to add a specification citation here when available. 1089*a9fa9459Szrj 1090*a9fa9459Szrj@node i386-TBM 1091*a9fa9459Szrj@section AMD's Trailing Bit Manipulation Instructions 1092*a9fa9459Szrj 1093*a9fa9459Szrj@cindex TBM, i386 1094*a9fa9459Szrj@cindex TBM, x86-64 1095*a9fa9459Szrj 1096*a9fa9459Szrj@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM) 1097*a9fa9459Szrjinstruction set, available on AMD's BDVER2 processors (Trinity and 1098*a9fa9459SzrjViperfish). 1099*a9fa9459Szrj 1100*a9fa9459SzrjTBM instructions provide instructions implementing individual bit 1101*a9fa9459Szrjmanipulation operations such as isolating, masking, setting, resetting, 1102*a9fa9459Szrjcomplementing, and operations on trailing zeros and ones. 1103*a9fa9459Szrj 1104*a9fa9459Szrj@c Need to add a specification citation here when available. 1105*a9fa9459Szrj 1106*a9fa9459Szrj@node i386-16bit 1107*a9fa9459Szrj@section Writing 16-bit Code 1108*a9fa9459Szrj 1109*a9fa9459Szrj@cindex i386 16-bit code 1110*a9fa9459Szrj@cindex 16-bit code, i386 1111*a9fa9459Szrj@cindex real-mode code, i386 1112*a9fa9459Szrj@cindex @code{code16gcc} directive, i386 1113*a9fa9459Szrj@cindex @code{code16} directive, i386 1114*a9fa9459Szrj@cindex @code{code32} directive, i386 1115*a9fa9459Szrj@cindex @code{code64} directive, i386 1116*a9fa9459Szrj@cindex @code{code64} directive, x86-64 1117*a9fa9459SzrjWhile @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code 1118*a9fa9459Szrjor 64-bit x86-64 code depending on the default configuration, 1119*a9fa9459Szrjit also supports writing code to run in real mode or in 16-bit protected 1120*a9fa9459Szrjmode code segments. To do this, put a @samp{.code16} or 1121*a9fa9459Szrj@samp{.code16gcc} directive before the assembly language instructions to 1122*a9fa9459Szrjbe run in 16-bit mode. You can switch @code{@value{AS}} to writing 1123*a9fa9459Szrj32-bit code with the @samp{.code32} directive or 64-bit code with the 1124*a9fa9459Szrj@samp{.code64} directive. 1125*a9fa9459Szrj 1126*a9fa9459Szrj@samp{.code16gcc} provides experimental support for generating 16-bit 1127*a9fa9459Szrjcode from gcc, and differs from @samp{.code16} in that @samp{call}, 1128*a9fa9459Szrj@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, 1129*a9fa9459Szrj@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions 1130*a9fa9459Szrjdefault to 32-bit size. This is so that the stack pointer is 1131*a9fa9459Szrjmanipulated in the same way over function calls, allowing access to 1132*a9fa9459Szrjfunction parameters at the same stack offsets as in 32-bit mode. 1133*a9fa9459Szrj@samp{.code16gcc} also automatically adds address size prefixes where 1134*a9fa9459Szrjnecessary to use the 32-bit addressing modes that gcc generates. 1135*a9fa9459Szrj 1136*a9fa9459SzrjThe code which @code{@value{AS}} generates in 16-bit mode will not 1137*a9fa9459Szrjnecessarily run on a 16-bit pre-80386 processor. To write code that 1138*a9fa9459Szrjruns on such a processor, you must refrain from using @emph{any} 32-bit 1139*a9fa9459Szrjconstructs which require @code{@value{AS}} to output address or operand 1140*a9fa9459Szrjsize prefixes. 1141*a9fa9459Szrj 1142*a9fa9459SzrjNote that writing 16-bit code instructions by explicitly specifying a 1143*a9fa9459Szrjprefix or an instruction mnemonic suffix within a 32-bit code section 1144*a9fa9459Szrjgenerates different machine instructions than those generated for a 1145*a9fa9459Szrj16-bit code segment. In a 32-bit code section, the following code 1146*a9fa9459Szrjgenerates the machine opcode bytes @samp{66 6a 04}, which pushes the 1147*a9fa9459Szrjvalue @samp{4} onto the stack, decrementing @samp{%esp} by 2. 1148*a9fa9459Szrj 1149*a9fa9459Szrj@smallexample 1150*a9fa9459Szrj pushw $4 1151*a9fa9459Szrj@end smallexample 1152*a9fa9459Szrj 1153*a9fa9459SzrjThe same code in a 16-bit code section would generate the machine 1154*a9fa9459Szrjopcode bytes @samp{6a 04} (i.e., without the operand size prefix), which 1155*a9fa9459Szrjis correct since the processor default operand size is assumed to be 16 1156*a9fa9459Szrjbits in a 16-bit code section. 1157*a9fa9459Szrj 1158*a9fa9459Szrj@node i386-Arch 1159*a9fa9459Szrj@section Specifying CPU Architecture 1160*a9fa9459Szrj 1161*a9fa9459Szrj@cindex arch directive, i386 1162*a9fa9459Szrj@cindex i386 arch directive 1163*a9fa9459Szrj@cindex arch directive, x86-64 1164*a9fa9459Szrj@cindex x86-64 arch directive 1165*a9fa9459Szrj 1166*a9fa9459Szrj@code{@value{AS}} may be told to assemble for a particular CPU 1167*a9fa9459Szrj(sub-)architecture with the @code{.arch @var{cpu_type}} directive. This 1168*a9fa9459Szrjdirective enables a warning when gas detects an instruction that is not 1169*a9fa9459Szrjsupported on the CPU specified. The choices for @var{cpu_type} are: 1170*a9fa9459Szrj 1171*a9fa9459Szrj@multitable @columnfractions .20 .20 .20 .20 1172*a9fa9459Szrj@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} 1173*a9fa9459Szrj@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} 1174*a9fa9459Szrj@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} 1175*a9fa9459Szrj@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} 1176*a9fa9459Szrj@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu} 1177*a9fa9459Szrj@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} 1178*a9fa9459Szrj@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} 1179*a9fa9459Szrj@item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2} 1180*a9fa9459Szrj@item @samp{generic32} @tab @samp{generic64} 1181*a9fa9459Szrj@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} 1182*a9fa9459Szrj@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} 1183*a9fa9459Szrj@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} 1184*a9fa9459Szrj@item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} 1185*a9fa9459Szrj@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase} 1186*a9fa9459Szrj@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} 1187*a9fa9459Szrj@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle} 1188*a9fa9459Szrj@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} 1189*a9fa9459Szrj@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} 1190*a9fa9459Szrj@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} 1191*a9fa9459Szrj@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} 1192*a9fa9459Szrj@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} 1193*a9fa9459Szrj@item @samp{.avx512vbmi} @tab @samp{.clwb} @tab @samp{.pcommit} 1194*a9fa9459Szrj@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} 1195*a9fa9459Szrj@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} 1196*a9fa9459Szrj@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} 1197*a9fa9459Szrj@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpid} 1198*a9fa9459Szrj@end multitable 1199*a9fa9459Szrj 1200*a9fa9459SzrjApart from the warning, there are only two other effects on 1201*a9fa9459Szrj@code{@value{AS}} operation; Firstly, if you specify a CPU other than 1202*a9fa9459Szrj@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} 1203*a9fa9459Szrjwill automatically use a two byte opcode sequence. The larger three 1204*a9fa9459Szrjbyte opcode sequence is used on the 486 (and when no architecture is 1205*a9fa9459Szrjspecified) because it executes faster on the 486. Note that you can 1206*a9fa9459Szrjexplicitly request the two byte opcode by writing @samp{sarl %eax}. 1207*a9fa9459SzrjSecondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, 1208*a9fa9459Szrj@emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset 1209*a9fa9459Szrjconditional jumps will be promoted when necessary to a two instruction 1210*a9fa9459Szrjsequence consisting of a conditional jump of the opposite sense around 1211*a9fa9459Szrjan unconditional jump to the target. 1212*a9fa9459Szrj 1213*a9fa9459SzrjFollowing the CPU architecture (but not a sub-architecture, which are those 1214*a9fa9459Szrjstarting with a dot), you may specify @samp{jumps} or @samp{nojumps} to 1215*a9fa9459Szrjcontrol automatic promotion of conditional jumps. @samp{jumps} is the 1216*a9fa9459Szrjdefault, and enables jump promotion; All external jumps will be of the long 1217*a9fa9459Szrjvariety, and file-local jumps will be promoted as necessary. 1218*a9fa9459Szrj(@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as 1219*a9fa9459Szrjbyte offset jumps, and warns about file-local conditional jumps that 1220*a9fa9459Szrj@code{@value{AS}} promotes. 1221*a9fa9459SzrjUnconditional jumps are treated as for @samp{jumps}. 1222*a9fa9459Szrj 1223*a9fa9459SzrjFor example 1224*a9fa9459Szrj 1225*a9fa9459Szrj@smallexample 1226*a9fa9459Szrj .arch i8086,nojumps 1227*a9fa9459Szrj@end smallexample 1228*a9fa9459Szrj 1229*a9fa9459Szrj@node i386-Bugs 1230*a9fa9459Szrj@section AT&T Syntax bugs 1231*a9fa9459Szrj 1232*a9fa9459SzrjThe UnixWare assembler, and probably other AT&T derived ix86 Unix 1233*a9fa9459Szrjassemblers, generate floating point instructions with reversed source 1234*a9fa9459Szrjand destination registers in certain cases. Unfortunately, gcc and 1235*a9fa9459Szrjpossibly many other programs use this reversed syntax, so we're stuck 1236*a9fa9459Szrjwith it. 1237*a9fa9459Szrj 1238*a9fa9459SzrjFor example 1239*a9fa9459Szrj 1240*a9fa9459Szrj@smallexample 1241*a9fa9459Szrj fsub %st,%st(3) 1242*a9fa9459Szrj@end smallexample 1243*a9fa9459Szrj@noindent 1244*a9fa9459Szrjresults in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather 1245*a9fa9459Szrjthan the expected @samp{%st(3) - %st}. This happens with all the 1246*a9fa9459Szrjnon-commutative arithmetic floating point operations with two register 1247*a9fa9459Szrjoperands where the source register is @samp{%st} and the destination 1248*a9fa9459Szrjregister is @samp{%st(i)}. 1249*a9fa9459Szrj 1250*a9fa9459Szrj@node i386-Notes 1251*a9fa9459Szrj@section Notes 1252*a9fa9459Szrj 1253*a9fa9459Szrj@cindex i386 @code{mul}, @code{imul} instructions 1254*a9fa9459Szrj@cindex @code{mul} instruction, i386 1255*a9fa9459Szrj@cindex @code{imul} instruction, i386 1256*a9fa9459Szrj@cindex @code{mul} instruction, x86-64 1257*a9fa9459Szrj@cindex @code{imul} instruction, x86-64 1258*a9fa9459SzrjThere is some trickery concerning the @samp{mul} and @samp{imul} 1259*a9fa9459Szrjinstructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding 1260*a9fa9459Szrjmultiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 1261*a9fa9459Szrjfor @samp{imul}) can be output only in the one operand form. Thus, 1262*a9fa9459Szrj@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; 1263*a9fa9459Szrjthe expanding multiply would clobber the @samp{%edx} register, and this 1264*a9fa9459Szrjwould confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the 1265*a9fa9459Szrj64-bit product in @samp{%edx:%eax}. 1266*a9fa9459Szrj 1267*a9fa9459SzrjWe have added a two operand form of @samp{imul} when the first operand 1268*a9fa9459Szrjis an immediate mode expression and the second operand is a register. 1269*a9fa9459SzrjThis is just a shorthand, so that, multiplying @samp{%eax} by 69, for 1270*a9fa9459Szrjexample, can be done with @samp{imul $69, %eax} rather than @samp{imul 1271*a9fa9459Szrj$69, %eax, %eax}. 1272*a9fa9459Szrj 1273