1@c Copyright (C) 1991-2016 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@c man end 5 6@ifset GENERIC 7@page 8@node i386-Dependent 9@chapter 80386 Dependent Features 10@end ifset 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter 80386 Dependent Features 14@end ifclear 15 16@cindex i386 support 17@cindex i80386 support 18@cindex x86-64 support 19 20The i386 version @code{@value{AS}} supports both the original Intel 386 21architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture 22extending the Intel architecture to 64-bits. 23 24@menu 25* i386-Options:: Options 26* i386-Directives:: X86 specific directives 27* i386-Syntax:: Syntactical considerations 28* i386-Mnemonics:: Instruction Naming 29* i386-Regs:: Register Naming 30* i386-Prefixes:: Instruction Prefixes 31* i386-Memory:: Memory References 32* i386-Jumps:: Handling of Jump Instructions 33* i386-Float:: Floating Point 34* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 35* i386-LWP:: AMD's Lightweight Profiling Instructions 36* i386-BMI:: Bit Manipulation Instruction 37* i386-TBM:: AMD's Trailing Bit Manipulation Instructions 38* i386-16bit:: Writing 16-bit Code 39* i386-Arch:: Specifying an x86 CPU architecture 40* i386-Bugs:: AT&T Syntax bugs 41* i386-Notes:: Notes 42@end menu 43 44@node i386-Options 45@section Options 46 47@cindex options for i386 48@cindex options for x86-64 49@cindex i386 options 50@cindex x86-64 options 51 52The i386 version of @code{@value{AS}} has a few machine 53dependent options: 54 55@c man begin OPTIONS 56@table @gcctabopt 57@cindex @samp{--32} option, i386 58@cindex @samp{--32} option, x86-64 59@cindex @samp{--x32} option, i386 60@cindex @samp{--x32} option, x86-64 61@cindex @samp{--64} option, i386 62@cindex @samp{--64} option, x86-64 63@item --32 | --x32 | --64 64Select the word size, either 32 bits or 64 bits. @samp{--32} 65implies Intel i386 architecture, while @samp{--x32} and @samp{--64} 66imply AMD x86-64 architecture with 32-bit or 64-bit word-size 67respectively. 68 69These options are only available with the ELF object file format, and 70require that the necessary BFD support has been included (on a 32-bit 71platform you have to add --enable-64-bit-bfd to configure enable 64-bit 72usage and use x86-64 as target platform). 73 74@item -n 75By default, x86 GAS replaces multiple nop instructions used for 76alignment within code sections with multi-byte nop instructions such 77as leal 0(%esi,1),%esi. This switch disables the optimization. 78 79@cindex @samp{--divide} option, i386 80@item --divide 81On SVR4-derived platforms, the character @samp{/} is treated as a comment 82character, which means that it cannot be used in expressions. The 83@samp{--divide} option turns @samp{/} into a normal character. This does 84not disable @samp{/} at the beginning of a line starting a comment, or 85affect using @samp{#} for starting a comment. 86 87@cindex @samp{-march=} option, i386 88@cindex @samp{-march=} option, x86-64 89@item -march=@var{CPU}[+@var{EXTENSION}@dots{}] 90This option specifies the target processor. The assembler will 91issue an error message if an attempt is made to assemble an instruction 92which will not execute on the target processor. The following 93processor names are recognized: 94@code{i8086}, 95@code{i186}, 96@code{i286}, 97@code{i386}, 98@code{i486}, 99@code{i586}, 100@code{i686}, 101@code{pentium}, 102@code{pentiumpro}, 103@code{pentiumii}, 104@code{pentiumiii}, 105@code{pentium4}, 106@code{prescott}, 107@code{nocona}, 108@code{core}, 109@code{core2}, 110@code{corei7}, 111@code{l1om}, 112@code{k1om}, 113@code{iamcu}, 114@code{k6}, 115@code{k6_2}, 116@code{athlon}, 117@code{opteron}, 118@code{k8}, 119@code{amdfam10}, 120@code{bdver1}, 121@code{bdver2}, 122@code{bdver3}, 123@code{bdver4}, 124@code{znver1}, 125@code{btver1}, 126@code{btver2}, 127@code{generic32} and 128@code{generic64}. 129 130In addition to the basic instruction set, the assembler can be told to 131accept various extension mnemonics. For example, 132@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and 133@var{vmx}. The following extensions are currently supported: 134@code{8087}, 135@code{287}, 136@code{387}, 137@code{687}, 138@code{no87}, 139@code{no287}, 140@code{no387}, 141@code{no687}, 142@code{mmx}, 143@code{nommx}, 144@code{sse}, 145@code{sse2}, 146@code{sse3}, 147@code{ssse3}, 148@code{sse4.1}, 149@code{sse4.2}, 150@code{sse4}, 151@code{nosse}, 152@code{nosse2}, 153@code{nosse3}, 154@code{nossse3}, 155@code{nosse4.1}, 156@code{nosse4.2}, 157@code{nosse4}, 158@code{avx}, 159@code{avx2}, 160@code{noavx}, 161@code{noavx2}, 162@code{adx}, 163@code{rdseed}, 164@code{prfchw}, 165@code{smap}, 166@code{mpx}, 167@code{sha}, 168@code{rdpid}, 169@code{prefetchwt1}, 170@code{clflushopt}, 171@code{se1}, 172@code{clwb}, 173@code{pcommit}, 174@code{avx512f}, 175@code{avx512cd}, 176@code{avx512er}, 177@code{avx512pf}, 178@code{avx512vl}, 179@code{avx512bw}, 180@code{avx512dq}, 181@code{avx512ifma}, 182@code{avx512vbmi}, 183@code{noavx512f}, 184@code{noavx512cd}, 185@code{noavx512er}, 186@code{noavx512pf}, 187@code{noavx512vl}, 188@code{noavx512bw}, 189@code{noavx512dq}, 190@code{noavx512ifma}, 191@code{noavx512vbmi}, 192@code{vmx}, 193@code{vmfunc}, 194@code{smx}, 195@code{xsave}, 196@code{xsaveopt}, 197@code{xsavec}, 198@code{xsaves}, 199@code{aes}, 200@code{pclmul}, 201@code{fsgsbase}, 202@code{rdrnd}, 203@code{f16c}, 204@code{bmi2}, 205@code{fma}, 206@code{movbe}, 207@code{ept}, 208@code{lzcnt}, 209@code{hle}, 210@code{rtm}, 211@code{invpcid}, 212@code{clflush}, 213@code{mwaitx}, 214@code{clzero}, 215@code{lwp}, 216@code{fma4}, 217@code{xop}, 218@code{cx16}, 219@code{syscall}, 220@code{rdtscp}, 221@code{3dnow}, 222@code{3dnowa}, 223@code{sse4a}, 224@code{sse5}, 225@code{svme}, 226@code{abm} and 227@code{padlock}. 228Note that rather than extending a basic instruction set, the extension 229mnemonics starting with @code{no} revoke the respective functionality. 230 231When the @code{.arch} directive is used with @option{-march}, the 232@code{.arch} directive will take precedent. 233 234@cindex @samp{-mtune=} option, i386 235@cindex @samp{-mtune=} option, x86-64 236@item -mtune=@var{CPU} 237This option specifies a processor to optimize for. When used in 238conjunction with the @option{-march} option, only instructions 239of the processor specified by the @option{-march} option will be 240generated. 241 242Valid @var{CPU} values are identical to the processor list of 243@option{-march=@var{CPU}}. 244 245@cindex @samp{-msse2avx} option, i386 246@cindex @samp{-msse2avx} option, x86-64 247@item -msse2avx 248This option specifies that the assembler should encode SSE instructions 249with VEX prefix. 250 251@cindex @samp{-msse-check=} option, i386 252@cindex @samp{-msse-check=} option, x86-64 253@item -msse-check=@var{none} 254@itemx -msse-check=@var{warning} 255@itemx -msse-check=@var{error} 256These options control if the assembler should check SSE instructions. 257@option{-msse-check=@var{none}} will make the assembler not to check SSE 258instructions, which is the default. @option{-msse-check=@var{warning}} 259will make the assembler issue a warning for any SSE instruction. 260@option{-msse-check=@var{error}} will make the assembler issue an error 261for any SSE instruction. 262 263@cindex @samp{-mavxscalar=} option, i386 264@cindex @samp{-mavxscalar=} option, x86-64 265@item -mavxscalar=@var{128} 266@itemx -mavxscalar=@var{256} 267These options control how the assembler should encode scalar AVX 268instructions. @option{-mavxscalar=@var{128}} will encode scalar 269AVX instructions with 128bit vector length, which is the default. 270@option{-mavxscalar=@var{256}} will encode scalar AVX instructions 271with 256bit vector length. 272 273@cindex @samp{-mevexlig=} option, i386 274@cindex @samp{-mevexlig=} option, x86-64 275@item -mevexlig=@var{128} 276@itemx -mevexlig=@var{256} 277@itemx -mevexlig=@var{512} 278These options control how the assembler should encode length-ignored 279(LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG 280EVEX instructions with 128bit vector length, which is the default. 281@option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will 282encode LIG EVEX instructions with 256bit and 512bit vector length, 283respectively. 284 285@cindex @samp{-mevexwig=} option, i386 286@cindex @samp{-mevexwig=} option, x86-64 287@item -mevexwig=@var{0} 288@itemx -mevexwig=@var{1} 289These options control how the assembler should encode w-ignored (WIG) 290EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG 291EVEX instructions with evex.w = 0, which is the default. 292@option{-mevexwig=@var{1}} will encode WIG EVEX instructions with 293evex.w = 1. 294 295@cindex @samp{-mmnemonic=} option, i386 296@cindex @samp{-mmnemonic=} option, x86-64 297@item -mmnemonic=@var{att} 298@itemx -mmnemonic=@var{intel} 299This option specifies instruction mnemonic for matching instructions. 300The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will 301take precedent. 302 303@cindex @samp{-msyntax=} option, i386 304@cindex @samp{-msyntax=} option, x86-64 305@item -msyntax=@var{att} 306@itemx -msyntax=@var{intel} 307This option specifies instruction syntax when processing instructions. 308The @code{.att_syntax} and @code{.intel_syntax} directives will 309take precedent. 310 311@cindex @samp{-mnaked-reg} option, i386 312@cindex @samp{-mnaked-reg} option, x86-64 313@item -mnaked-reg 314This opetion specifies that registers don't require a @samp{%} prefix. 315The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. 316 317@cindex @samp{-madd-bnd-prefix} option, i386 318@cindex @samp{-madd-bnd-prefix} option, x86-64 319@item -madd-bnd-prefix 320This option forces the assembler to add BND prefix to all branches, even 321if such prefix was not explicitly specified in the source code. 322 323@cindex @samp{-mshared} option, i386 324@cindex @samp{-mshared} option, x86-64 325@item -mno-shared 326On ELF target, the assembler normally optimizes out non-PLT relocations 327against defined non-weak global branch targets with default visibility. 328The @samp{-mshared} option tells the assembler to generate code which 329may go into a shared library where all non-weak global branch targets 330with default visibility can be preempted. The resulting code is 331slightly bigger. This option only affects the handling of branch 332instructions. 333 334@cindex @samp{-mbig-obj} option, x86-64 335@item -mbig-obj 336On x86-64 PE/COFF target this option forces the use of big object file 337format, which allows more than 32768 sections. 338 339@cindex @samp{-momit-lock-prefix=} option, i386 340@cindex @samp{-momit-lock-prefix=} option, x86-64 341@item -momit-lock-prefix=@var{no} 342@itemx -momit-lock-prefix=@var{yes} 343These options control how the assembler should encode lock prefix. 344This option is intended as a workaround for processors, that fail on 345lock prefix. This option can only be safely used with single-core, 346single-thread computers 347@option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. 348@option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, 349which is the default. 350 351@cindex @samp{-mfence-as-lock-add=} option, i386 352@cindex @samp{-mfence-as-lock-add=} option, x86-64 353@item -mfence-as-lock-add=@var{no} 354@itemx -mfence-as-lock-add=@var{yes} 355These options control how the assembler should encode lfence, mfence and 356sfence. 357@option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and 358sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and 359@samp{lock addl $0x0, (%esp)} in 32-bit mode. 360@option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and 361sfence as usual, which is the default. 362 363@cindex @samp{-mrelax-relocations=} option, i386 364@cindex @samp{-mrelax-relocations=} option, x86-64 365@item -mrelax-relocations=@var{no} 366@itemx -mrelax-relocations=@var{yes} 367These options control whether the assembler should generate relax 368relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and 369R_X86_64_REX_GOTPCRELX, in 64-bit mode. 370@option{-mrelax-relocations=@var{yes}} will generate relax relocations. 371@option{-mrelax-relocations=@var{no}} will not generate relax 372relocations. The default can be controlled by a configure option 373@option{--enable-x86-relax-relocations}. 374 375@cindex @samp{-mevexrcig=} option, i386 376@cindex @samp{-mevexrcig=} option, x86-64 377@item -mevexrcig=@var{rne} 378@itemx -mevexrcig=@var{rd} 379@itemx -mevexrcig=@var{ru} 380@itemx -mevexrcig=@var{rz} 381These options control how the assembler should encode SAE-only 382EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits 383of EVEX instruction with 00, which is the default. 384@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} 385and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions 386with 01, 10 and 11 RC bits, respectively. 387 388@cindex @samp{-mamd64} option, x86-64 389@cindex @samp{-mintel64} option, x86-64 390@item -mamd64 391@itemx -mintel64 392This option specifies that the assembler should accept only AMD64 or 393Intel64 ISA in 64-bit mode. The default is to accept both. 394 395@end table 396@c man end 397 398@node i386-Directives 399@section x86 specific Directives 400 401@cindex machine directives, x86 402@cindex x86 machine directives 403@table @code 404 405@cindex @code{lcomm} directive, COFF 406@item .lcomm @var{symbol} , @var{length}[, @var{alignment}] 407Reserve @var{length} (an absolute expression) bytes for a local common 408denoted by @var{symbol}. The section and value of @var{symbol} are 409those of the new local common. The addresses are allocated in the bss 410section, so that at run-time the bytes start off zeroed. Since 411@var{symbol} is not declared global, it is normally not visible to 412@code{@value{LD}}. The optional third parameter, @var{alignment}, 413specifies the desired alignment of the symbol in the bss section. 414 415This directive is only available for COFF based x86 targets. 416 417@c FIXME: Document other x86 specific directives ? Eg: .code16gcc, 418@c .largecomm 419 420@end table 421 422@node i386-Syntax 423@section i386 Syntactical Considerations 424@menu 425* i386-Variations:: AT&T Syntax versus Intel Syntax 426* i386-Chars:: Special Characters 427@end menu 428 429@node i386-Variations 430@subsection AT&T Syntax versus Intel Syntax 431 432@cindex i386 intel_syntax pseudo op 433@cindex intel_syntax pseudo op, i386 434@cindex i386 att_syntax pseudo op 435@cindex att_syntax pseudo op, i386 436@cindex i386 syntax compatibility 437@cindex syntax compatibility, i386 438@cindex x86-64 intel_syntax pseudo op 439@cindex intel_syntax pseudo op, x86-64 440@cindex x86-64 att_syntax pseudo op 441@cindex att_syntax pseudo op, x86-64 442@cindex x86-64 syntax compatibility 443@cindex syntax compatibility, x86-64 444 445@code{@value{AS}} now supports assembly using Intel assembler syntax. 446@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches 447back to the usual AT&T mode for compatibility with the output of 448@code{@value{GCC}}. Either of these directives may have an optional 449argument, @code{prefix}, or @code{noprefix} specifying whether registers 450require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite 451different from Intel syntax. We mention these differences because 452almost all 80386 documents use Intel syntax. Notable differences 453between the two syntaxes are: 454 455@cindex immediate operands, i386 456@cindex i386 immediate operands 457@cindex register operands, i386 458@cindex i386 register operands 459@cindex jump/call operands, i386 460@cindex i386 jump/call operands 461@cindex operand delimiters, i386 462 463@cindex immediate operands, x86-64 464@cindex x86-64 immediate operands 465@cindex register operands, x86-64 466@cindex x86-64 register operands 467@cindex jump/call operands, x86-64 468@cindex x86-64 jump/call operands 469@cindex operand delimiters, x86-64 470@itemize @bullet 471@item 472AT&T immediate operands are preceded by @samp{$}; Intel immediate 473operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). 474AT&T register operands are preceded by @samp{%}; Intel register operands 475are undelimited. AT&T absolute (as opposed to PC relative) jump/call 476operands are prefixed by @samp{*}; they are undelimited in Intel syntax. 477 478@cindex i386 source, destination operands 479@cindex source, destination operands; i386 480@cindex x86-64 source, destination operands 481@cindex source, destination operands; x86-64 482@item 483AT&T and Intel syntax use the opposite order for source and destination 484operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The 485@samp{source, dest} convention is maintained for compatibility with 486previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and 487instructions with 2 immediate operands, such as the @samp{enter} 488instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. 489 490@cindex mnemonic suffixes, i386 491@cindex sizes operands, i386 492@cindex i386 size suffixes 493@cindex mnemonic suffixes, x86-64 494@cindex sizes operands, x86-64 495@cindex x86-64 size suffixes 496@item 497In AT&T syntax the size of memory operands is determined from the last 498character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, 499@samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long 500(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes 501this by prefixing memory operands (@emph{not} the instruction mnemonics) with 502@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus, 503Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T 504syntax. 505 506In 64-bit code, @samp{movabs} can be used to encode the @samp{mov} 507instruction with the 64-bit displacement or immediate operand. 508 509@cindex return instructions, i386 510@cindex i386 jump, call, return 511@cindex return instructions, x86-64 512@cindex x86-64 jump, call, return 513@item 514Immediate form long jumps and calls are 515@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the 516Intel syntax is 517@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return 518instruction 519is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is 520@samp{ret far @var{stack-adjust}}. 521 522@cindex sections, i386 523@cindex i386 sections 524@cindex sections, x86-64 525@cindex x86-64 sections 526@item 527The AT&T assembler does not provide support for multiple section 528programs. Unix style systems expect all programs to be single sections. 529@end itemize 530 531@node i386-Chars 532@subsection Special Characters 533 534@cindex line comment character, i386 535@cindex i386 line comment character 536The presence of a @samp{#} appearing anywhere on a line indicates the 537start of a comment that extends to the end of that line. 538 539If a @samp{#} appears as the first character of a line then the whole 540line is treated as a comment, but in this case the line can also be a 541logical line number directive (@pxref{Comments}) or a preprocessor 542control command (@pxref{Preprocessing}). 543 544If the @option{--divide} command line option has not been specified 545then the @samp{/} character appearing anywhere on a line also 546introduces a line comment. 547 548@cindex line separator, i386 549@cindex statement separator, i386 550@cindex i386 line separator 551The @samp{;} character can be used to separate statements on the same 552line. 553 554@node i386-Mnemonics 555@section i386-Mnemonics 556@subsection Instruction Naming 557 558@cindex i386 instruction naming 559@cindex instruction naming, i386 560@cindex x86-64 instruction naming 561@cindex instruction naming, x86-64 562 563Instruction mnemonics are suffixed with one character modifiers which 564specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} 565and @samp{q} specify byte, word, long and quadruple word operands. If 566no suffix is specified by an instruction then @code{@value{AS}} tries to 567fill in the missing suffix based on the destination register operand 568(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent 569to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to 570@samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix 571assembler which assumes that a missing mnemonic suffix implies long 572operand size. (This incompatibility does not affect compiler output 573since compilers always explicitly specify the mnemonic suffix.) 574 575Almost all instructions have the same names in AT&T and Intel format. 576There are a few exceptions. The sign extend and zero extend 577instructions need two sizes to specify them. They need a size to 578sign/zero extend @emph{from} and a size to zero extend @emph{to}. This 579is accomplished by using two instruction mnemonic suffixes in AT&T 580syntax. Base names for sign extend and zero extend are 581@samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} 582and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes 583are tacked on to this base name, the @emph{from} suffix before the 584@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for 585``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, 586thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), 587@samp{wl} (from word to long), @samp{bq} (from byte to quadruple word), 588@samp{wq} (from word to quadruple word), and @samp{lq} (from long to 589quadruple word). 590 591@cindex encoding options, i386 592@cindex encoding options, x86-64 593 594Different encoding options can be specified via optional mnemonic 595suffix. @samp{.s} suffix swaps 2 register operands in encoding when 596moving from one register to another. @samp{.d8} or @samp{.d32} suffix 597prefers 8bit or 32bit displacement in encoding. 598 599@cindex conversion instructions, i386 600@cindex i386 conversion instructions 601@cindex conversion instructions, x86-64 602@cindex x86-64 conversion instructions 603The Intel-syntax conversion instructions 604 605@itemize @bullet 606@item 607@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, 608 609@item 610@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, 611 612@item 613@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, 614 615@item 616@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, 617 618@item 619@samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} 620(x86-64 only), 621 622@item 623@samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in 624@samp{%rdx:%rax} (x86-64 only), 625@end itemize 626 627@noindent 628are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and 629@samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these 630instructions. 631 632@cindex jump instructions, i386 633@cindex call instructions, i386 634@cindex jump instructions, x86-64 635@cindex call instructions, x86-64 636Far call/jump instructions are @samp{lcall} and @samp{ljmp} in 637AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel 638convention. 639 640@subsection AT&T Mnemonic versus Intel Mnemonic 641 642@cindex i386 mnemonic compatibility 643@cindex mnemonic compatibility, i386 644 645@code{@value{AS}} supports assembly using Intel mnemonic. 646@code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and 647@code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T 648syntax for compatibility with the output of @code{@value{GCC}}. 649Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, 650@samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, 651@samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 652assembler with different mnemonics from those in Intel IA32 specification. 653@code{@value{GCC}} generates those instructions with AT&T mnemonic. 654 655@node i386-Regs 656@section Register Naming 657 658@cindex i386 registers 659@cindex registers, i386 660@cindex x86-64 registers 661@cindex registers, x86-64 662Register operands are always prefixed with @samp{%}. The 80386 registers 663consist of 664 665@itemize @bullet 666@item 667the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, 668@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the 669frame pointer), and @samp{%esp} (the stack pointer). 670 671@item 672the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, 673@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. 674 675@item 676the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, 677@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These 678are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, 679@samp{%cx}, and @samp{%dx}) 680 681@item 682the 6 section registers @samp{%cs} (code section), @samp{%ds} 683(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, 684and @samp{%gs}. 685 686@item 687the 5 processor control registers @samp{%cr0}, @samp{%cr2}, 688@samp{%cr3}, @samp{%cr4}, and @samp{%cr8}. 689 690@item 691the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, 692@samp{%db3}, @samp{%db6}, and @samp{%db7}. 693 694@item 695the 2 test registers @samp{%tr6} and @samp{%tr7}. 696 697@item 698the 8 floating point register stack @samp{%st} or equivalently 699@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, 700@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. 701These registers are overloaded by 8 MMX registers @samp{%mm0}, 702@samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, 703@samp{%mm6} and @samp{%mm7}. 704 705@item 706the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, 707@samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. 708@end itemize 709 710The AMD x86-64 architecture extends the register set by: 711 712@itemize @bullet 713@item 714enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the 715accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, 716@samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack 717pointer) 718 719@item 720the 8 extended registers @samp{%r8}--@samp{%r15}. 721 722@item 723the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}. 724 725@item 726the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}. 727 728@item 729the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}. 730 731@item 732the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. 733 734@item 735the 8 debug registers: @samp{%db8}--@samp{%db15}. 736 737@item 738the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}. 739@end itemize 740 741With the AVX extensions more registers were made available: 742 743@itemize @bullet 744 745@item 746the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8 747available in 32-bit mode). The bottom 128 bits are overlaid with the 748@samp{xmm0}--@samp{xmm15} registers. 749 750@end itemize 751 752The AVX2 extensions made in 64-bit mode more registers available: 753 754@itemize @bullet 755 756@item 757the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit 758registers @samp{%ymm16}--@samp{%ymm31}. 759 760@end itemize 761 762The AVX512 extensions added the following registers: 763 764@itemize @bullet 765 766@item 767the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8 768available in 32-bit mode). The bottom 128 bits are overlaid with the 769@samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are 770overlaid with the @samp{%ymm0}--@samp{%ymm31} registers. 771 772@item 773the 8 mask registers @samp{%k0}--@samp{%k7}. 774 775@end itemize 776 777@node i386-Prefixes 778@section Instruction Prefixes 779 780@cindex i386 instruction prefixes 781@cindex instruction prefixes, i386 782@cindex prefixes, i386 783Instruction prefixes are used to modify the following instruction. They 784are used to repeat string instructions, to provide section overrides, to 785perform bus lock operations, and to change operand and address sizes. 786(Most instructions that normally operate on 32-bit operands will use 78716-bit operands if the instruction has an ``operand size'' prefix.) 788Instruction prefixes are best written on the same line as the instruction 789they act upon. For example, the @samp{scas} (scan string) instruction is 790repeated with: 791 792@smallexample 793 repne scas %es:(%edi),%al 794@end smallexample 795 796You may also place prefixes on the lines immediately preceding the 797instruction, but this circumvents checks that @code{@value{AS}} does 798with prefixes, and will not work with all prefixes. 799 800Here is a list of instruction prefixes: 801 802@cindex section override prefixes, i386 803@itemize @bullet 804@item 805Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, 806@samp{fs}, @samp{gs}. These are automatically added by specifying 807using the @var{section}:@var{memory-operand} form for memory references. 808 809@cindex size prefixes, i386 810@item 811Operand/Address size prefixes @samp{data16} and @samp{addr16} 812change 32-bit operands/addresses into 16-bit operands/addresses, 813while @samp{data32} and @samp{addr32} change 16-bit ones (in a 814@code{.code16} section) into 32-bit operands/addresses. These prefixes 815@emph{must} appear on the same line of code as the instruction they 816modify. For example, in a 16-bit @code{.code16} section, you might 817write: 818 819@smallexample 820 addr32 jmpl *(%ebx) 821@end smallexample 822 823@cindex bus lock prefixes, i386 824@cindex inhibiting interrupts, i386 825@item 826The bus lock prefix @samp{lock} inhibits interrupts during execution of 827the instruction it precedes. (This is only valid with certain 828instructions; see a 80386 manual for details). 829 830@cindex coprocessor wait, i386 831@item 832The wait for coprocessor prefix @samp{wait} waits for the coprocessor to 833complete the current instruction. This should never be needed for the 83480386/80387 combination. 835 836@cindex repeat prefixes, i386 837@item 838The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added 839to string instructions to make them repeat @samp{%ecx} times (@samp{%cx} 840times if the current address size is 16-bits). 841@cindex REX prefixes, i386 842@item 843The @samp{rex} family of prefixes is used by x86-64 to encode 844extensions to i386 instruction set. The @samp{rex} prefix has four 845bits --- an operand size overwrite (@code{64}) used to change operand size 846from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 847register set. 848 849You may write the @samp{rex} prefixes directly. The @samp{rex64xyz} 850instruction emits @samp{rex} prefix with all the bits set. By omitting 851the @code{64}, @code{x}, @code{y} or @code{z} you may write other 852prefixes as well. Normally, there is no need to write the prefixes 853explicitly, since gas will automatically generate them based on the 854instruction operands. 855@end itemize 856 857@node i386-Memory 858@section Memory References 859 860@cindex i386 memory references 861@cindex memory references, i386 862@cindex x86-64 memory references 863@cindex memory references, x86-64 864An Intel syntax indirect memory reference of the form 865 866@smallexample 867@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] 868@end smallexample 869 870@noindent 871is translated into the AT&T syntax 872 873@smallexample 874@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) 875@end smallexample 876 877@noindent 878where @var{base} and @var{index} are the optional 32-bit base and 879index registers, @var{disp} is the optional displacement, and 880@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} 881to calculate the address of the operand. If no @var{scale} is 882specified, @var{scale} is taken to be 1. @var{section} specifies the 883optional section register for the memory operand, and may override the 884default section register (see a 80386 manual for section register 885defaults). Note that section overrides in AT&T syntax @emph{must} 886be preceded by a @samp{%}. If you specify a section override which 887coincides with the default section register, @code{@value{AS}} does @emph{not} 888output any section register override prefixes to assemble the given 889instruction. Thus, section overrides can be specified to emphasize which 890section register is used for a given memory operand. 891 892Here are some examples of Intel and AT&T style memory references: 893 894@table @asis 895@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} 896@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is 897missing, and the default section is used (@samp{%ss} for addressing with 898@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. 899 900@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} 901@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is 902@samp{foo}. All other fields are missing. The section register here 903defaults to @samp{%ds}. 904 905@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} 906This uses the value pointed to by @samp{foo} as a memory operand. 907Note that @var{base} and @var{index} are both missing, but there is only 908@emph{one} @samp{,}. This is a syntactic exception. 909 910@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} 911This selects the contents of the variable @samp{foo} with section 912register @var{section} being @samp{%gs}. 913@end table 914 915Absolute (as opposed to PC relative) call and jump operands must be 916prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} 917always chooses PC relative addressing for jump/call labels. 918 919Any instruction that has a memory operand, but no register operand, 920@emph{must} specify its size (byte, word, long, or quadruple) with an 921instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, 922respectively). 923 924The x86-64 architecture adds an RIP (instruction pointer relative) 925addressing. This addressing mode is specified by using @samp{rip} as a 926base register. Only constant offsets are valid. For example: 927 928@table @asis 929@item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} 930Points to the address 1234 bytes past the end of the current 931instruction. 932 933@item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} 934Points to the @code{symbol} in RIP relative way, this is shorter than 935the default absolute addressing. 936@end table 937 938Other addressing modes remain unchanged in x86-64 architecture, except 939registers used are 64-bit instead of 32-bit. 940 941@node i386-Jumps 942@section Handling of Jump Instructions 943 944@cindex jump optimization, i386 945@cindex i386 jump optimization 946@cindex jump optimization, x86-64 947@cindex x86-64 jump optimization 948Jump instructions are always optimized to use the smallest possible 949displacements. This is accomplished by using byte (8-bit) displacement 950jumps whenever the target is sufficiently close. If a byte displacement 951is insufficient a long displacement is used. We do not support 952word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 953instruction with the @samp{data16} instruction prefix), since the 80386 954insists upon masking @samp{%eip} to 16 bits after the word displacement 955is added. (See also @pxref{i386-Arch}) 956 957Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, 958@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte 959displacements, so that if you use these instructions (@code{@value{GCC}} does 960not use them) you may get an error message (and incorrect code). The AT&T 96180386 assembler tries to get around this problem by expanding @samp{jcxz foo} 962to 963 964@smallexample 965 jcxz cx_zero 966 jmp cx_nonzero 967cx_zero: jmp foo 968cx_nonzero: 969@end smallexample 970 971@node i386-Float 972@section Floating Point 973 974@cindex i386 floating point 975@cindex floating point, i386 976@cindex x86-64 floating point 977@cindex floating point, x86-64 978All 80387 floating point types except packed BCD are supported. 979(BCD support may be added without much difficulty). These data 980types are 16-, 32-, and 64- bit integers, and single (32-bit), 981double (64-bit), and extended (80-bit) precision floating point. 982Each supported type has an instruction mnemonic suffix and a constructor 983associated with it. Instruction mnemonic suffixes specify the operand's 984data type. Constructors build these data types into memory. 985 986@cindex @code{float} directive, i386 987@cindex @code{single} directive, i386 988@cindex @code{double} directive, i386 989@cindex @code{tfloat} directive, i386 990@cindex @code{float} directive, x86-64 991@cindex @code{single} directive, x86-64 992@cindex @code{double} directive, x86-64 993@cindex @code{tfloat} directive, x86-64 994@itemize @bullet 995@item 996Floating point constructors are @samp{.float} or @samp{.single}, 997@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. 998These correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, 999and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 1000only supports this format via the @samp{fldt} (load 80-bit real to stack 1001top) and @samp{fstpt} (store 80-bit real and pop stack) instructions. 1002 1003@cindex @code{word} directive, i386 1004@cindex @code{long} directive, i386 1005@cindex @code{int} directive, i386 1006@cindex @code{quad} directive, i386 1007@cindex @code{word} directive, x86-64 1008@cindex @code{long} directive, x86-64 1009@cindex @code{int} directive, x86-64 1010@cindex @code{quad} directive, x86-64 1011@item 1012Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and 1013@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The 1014corresponding instruction mnemonic suffixes are @samp{s} (single), 1015@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, 1016the 64-bit @samp{q} format is only present in the @samp{fildq} (load 1017quad integer to stack top) and @samp{fistpq} (store quad integer and pop 1018stack) instructions. 1019@end itemize 1020 1021Register to register operations should not use instruction mnemonic suffixes. 1022@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you 1023wrote @samp{fst %st, %st(1)}, since all register to register operations 1024use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, 1025which converts @samp{%st} from 80-bit to 64-bit floating point format, 1026then stores the result in the 4 byte location @samp{mem}) 1027 1028@node i386-SIMD 1029@section Intel's MMX and AMD's 3DNow! SIMD Operations 1030 1031@cindex MMX, i386 1032@cindex 3DNow!, i386 1033@cindex SIMD, i386 1034@cindex MMX, x86-64 1035@cindex 3DNow!, x86-64 1036@cindex SIMD, x86-64 1037 1038@code{@value{AS}} supports Intel's MMX instruction set (SIMD 1039instructions for integer data), available on Intel's Pentium MMX 1040processors and Pentium II processors, AMD's K6 and K6-2 processors, 1041Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: 1042instruction set (SIMD instructions for 32-bit floating point data) 1043available on AMD's K6-2 processor and possibly others in the future. 1044 1045Currently, @code{@value{AS}} does not support Intel's floating point 1046SIMD, Katmai (KNI). 1047 1048The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, 1049@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four 105016-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 1051floating point values. The MMX registers cannot be used at the same time 1052as the floating point stack. 1053 1054See Intel and AMD documentation, keeping in mind that the operand order in 1055instructions is reversed from the Intel syntax. 1056 1057@node i386-LWP 1058@section AMD's Lightweight Profiling Instructions 1059 1060@cindex LWP, i386 1061@cindex LWP, x86-64 1062 1063@code{@value{AS}} supports AMD's Lightweight Profiling (LWP) 1064instruction set, available on AMD's Family 15h (Orochi) processors. 1065 1066LWP enables applications to collect and manage performance data, and 1067react to performance events. The collection of performance data 1068requires no context switches. LWP runs in the context of a thread and 1069so several counters can be used independently across multiple threads. 1070LWP can be used in both 64-bit and legacy 32-bit modes. 1071 1072For detailed information on the LWP instruction set, see the 1073@cite{AMD Lightweight Profiling Specification} available at 1074@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. 1075 1076@node i386-BMI 1077@section Bit Manipulation Instructions 1078 1079@cindex BMI, i386 1080@cindex BMI, x86-64 1081 1082@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set. 1083 1084BMI instructions provide several instructions implementing individual 1085bit manipulation operations such as isolation, masking, setting, or 1086resetting. 1087 1088@c Need to add a specification citation here when available. 1089 1090@node i386-TBM 1091@section AMD's Trailing Bit Manipulation Instructions 1092 1093@cindex TBM, i386 1094@cindex TBM, x86-64 1095 1096@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM) 1097instruction set, available on AMD's BDVER2 processors (Trinity and 1098Viperfish). 1099 1100TBM instructions provide instructions implementing individual bit 1101manipulation operations such as isolating, masking, setting, resetting, 1102complementing, and operations on trailing zeros and ones. 1103 1104@c Need to add a specification citation here when available. 1105 1106@node i386-16bit 1107@section Writing 16-bit Code 1108 1109@cindex i386 16-bit code 1110@cindex 16-bit code, i386 1111@cindex real-mode code, i386 1112@cindex @code{code16gcc} directive, i386 1113@cindex @code{code16} directive, i386 1114@cindex @code{code32} directive, i386 1115@cindex @code{code64} directive, i386 1116@cindex @code{code64} directive, x86-64 1117While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code 1118or 64-bit x86-64 code depending on the default configuration, 1119it also supports writing code to run in real mode or in 16-bit protected 1120mode code segments. To do this, put a @samp{.code16} or 1121@samp{.code16gcc} directive before the assembly language instructions to 1122be run in 16-bit mode. You can switch @code{@value{AS}} to writing 112332-bit code with the @samp{.code32} directive or 64-bit code with the 1124@samp{.code64} directive. 1125 1126@samp{.code16gcc} provides experimental support for generating 16-bit 1127code from gcc, and differs from @samp{.code16} in that @samp{call}, 1128@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, 1129@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions 1130default to 32-bit size. This is so that the stack pointer is 1131manipulated in the same way over function calls, allowing access to 1132function parameters at the same stack offsets as in 32-bit mode. 1133@samp{.code16gcc} also automatically adds address size prefixes where 1134necessary to use the 32-bit addressing modes that gcc generates. 1135 1136The code which @code{@value{AS}} generates in 16-bit mode will not 1137necessarily run on a 16-bit pre-80386 processor. To write code that 1138runs on such a processor, you must refrain from using @emph{any} 32-bit 1139constructs which require @code{@value{AS}} to output address or operand 1140size prefixes. 1141 1142Note that writing 16-bit code instructions by explicitly specifying a 1143prefix or an instruction mnemonic suffix within a 32-bit code section 1144generates different machine instructions than those generated for a 114516-bit code segment. In a 32-bit code section, the following code 1146generates the machine opcode bytes @samp{66 6a 04}, which pushes the 1147value @samp{4} onto the stack, decrementing @samp{%esp} by 2. 1148 1149@smallexample 1150 pushw $4 1151@end smallexample 1152 1153The same code in a 16-bit code section would generate the machine 1154opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which 1155is correct since the processor default operand size is assumed to be 16 1156bits in a 16-bit code section. 1157 1158@node i386-Arch 1159@section Specifying CPU Architecture 1160 1161@cindex arch directive, i386 1162@cindex i386 arch directive 1163@cindex arch directive, x86-64 1164@cindex x86-64 arch directive 1165 1166@code{@value{AS}} may be told to assemble for a particular CPU 1167(sub-)architecture with the @code{.arch @var{cpu_type}} directive. This 1168directive enables a warning when gas detects an instruction that is not 1169supported on the CPU specified. The choices for @var{cpu_type} are: 1170 1171@multitable @columnfractions .20 .20 .20 .20 1172@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} 1173@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} 1174@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} 1175@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} 1176@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu} 1177@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} 1178@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} 1179@item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2} 1180@item @samp{generic32} @tab @samp{generic64} 1181@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} 1182@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} 1183@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} 1184@item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} 1185@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase} 1186@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} 1187@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle} 1188@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} 1189@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} 1190@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} 1191@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} 1192@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} 1193@item @samp{.avx512vbmi} @tab @samp{.clwb} @tab @samp{.pcommit} 1194@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} 1195@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} 1196@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} 1197@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpid} 1198@end multitable 1199 1200Apart from the warning, there are only two other effects on 1201@code{@value{AS}} operation; Firstly, if you specify a CPU other than 1202@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} 1203will automatically use a two byte opcode sequence. The larger three 1204byte opcode sequence is used on the 486 (and when no architecture is 1205specified) because it executes faster on the 486. Note that you can 1206explicitly request the two byte opcode by writing @samp{sarl %eax}. 1207Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, 1208@emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset 1209conditional jumps will be promoted when necessary to a two instruction 1210sequence consisting of a conditional jump of the opposite sense around 1211an unconditional jump to the target. 1212 1213Following the CPU architecture (but not a sub-architecture, which are those 1214starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to 1215control automatic promotion of conditional jumps. @samp{jumps} is the 1216default, and enables jump promotion; All external jumps will be of the long 1217variety, and file-local jumps will be promoted as necessary. 1218(@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as 1219byte offset jumps, and warns about file-local conditional jumps that 1220@code{@value{AS}} promotes. 1221Unconditional jumps are treated as for @samp{jumps}. 1222 1223For example 1224 1225@smallexample 1226 .arch i8086,nojumps 1227@end smallexample 1228 1229@node i386-Bugs 1230@section AT&T Syntax bugs 1231 1232The UnixWare assembler, and probably other AT&T derived ix86 Unix 1233assemblers, generate floating point instructions with reversed source 1234and destination registers in certain cases. Unfortunately, gcc and 1235possibly many other programs use this reversed syntax, so we're stuck 1236with it. 1237 1238For example 1239 1240@smallexample 1241 fsub %st,%st(3) 1242@end smallexample 1243@noindent 1244results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather 1245than the expected @samp{%st(3) - %st}. This happens with all the 1246non-commutative arithmetic floating point operations with two register 1247operands where the source register is @samp{%st} and the destination 1248register is @samp{%st(i)}. 1249 1250@node i386-Notes 1251@section Notes 1252 1253@cindex i386 @code{mul}, @code{imul} instructions 1254@cindex @code{mul} instruction, i386 1255@cindex @code{imul} instruction, i386 1256@cindex @code{mul} instruction, x86-64 1257@cindex @code{imul} instruction, x86-64 1258There is some trickery concerning the @samp{mul} and @samp{imul} 1259instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding 1260multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 1261for @samp{imul}) can be output only in the one operand form. Thus, 1262@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; 1263the expanding multiply would clobber the @samp{%edx} register, and this 1264would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the 126564-bit product in @samp{%edx:%eax}. 1266 1267We have added a two operand form of @samp{imul} when the first operand 1268is an immediate mode expression and the second operand is a register. 1269This is just a shorthand, so that, multiplying @samp{%eax} by 69, for 1270example, can be done with @samp{imul $69, %eax} rather than @samp{imul 1271$69, %eax, %eax}. 1272 1273