1*a9fa9459Szrj@c Copyright (C) 2000-2016 Free Software Foundation, Inc. 2*a9fa9459Szrj@c This is part of the GAS manual. 3*a9fa9459Szrj@c For copying conditions, see the file as.texinfo. 4*a9fa9459Szrj@ifset GENERIC 5*a9fa9459Szrj@page 6*a9fa9459Szrj@node i860-Dependent 7*a9fa9459Szrj@chapter Intel i860 Dependent Features 8*a9fa9459Szrj@end ifset 9*a9fa9459Szrj@ifclear GENERIC 10*a9fa9459Szrj@node Machine Dependencies 11*a9fa9459Szrj@chapter Intel i860 Dependent Features 12*a9fa9459Szrj@end ifclear 13*a9fa9459Szrj 14*a9fa9459Szrj@ignore 15*a9fa9459Szrj@c FIXME: This is basically a stub for i860. There is tons more information 16*a9fa9459Szrjthat I will add later (jle@cygnus.com). 17*a9fa9459Szrj@end ignore 18*a9fa9459Szrj 19*a9fa9459Szrj@cindex i860 support 20*a9fa9459Szrj@menu 21*a9fa9459Szrj* Notes-i860:: i860 Notes 22*a9fa9459Szrj* Options-i860:: i860 Command-line Options 23*a9fa9459Szrj* Directives-i860:: i860 Machine Directives 24*a9fa9459Szrj* Opcodes for i860:: i860 Opcodes 25*a9fa9459Szrj* Syntax of i860:: i860 Syntax 26*a9fa9459Szrj@end menu 27*a9fa9459Szrj 28*a9fa9459Szrj@node Notes-i860 29*a9fa9459Szrj@section i860 Notes 30*a9fa9459SzrjThis is a fairly complete i860 assembler which is compatible with the 31*a9fa9459SzrjUNIX System V/860 Release 4 assembler. However, it does not currently 32*a9fa9459Szrjsupport SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}). 33*a9fa9459Szrj 34*a9fa9459SzrjLike the SVR4/860 assembler, the output object format is ELF32. Currently, 35*a9fa9459Szrjthis is the only supported object format. If there is sufficient interest, 36*a9fa9459Szrjother formats such as COFF may be implemented. 37*a9fa9459Szrj 38*a9fa9459SzrjBoth the Intel and AT&T/SVR4 syntaxes are supported, with the latter 39*a9fa9459Szrjbeing the default. One difference is that AT&T syntax requires the '%' 40*a9fa9459Szrjprefix on register names while Intel syntax does not. Another difference 41*a9fa9459Szrjis in the specification of relocatable expressions. The Intel syntax 42*a9fa9459Szrjis @code{ha%expression} whereas the SVR4 syntax is @code{[expression]@@ha} 43*a9fa9459Szrj(and similarly for the "l" and "h" selectors). 44*a9fa9459Szrj@node Options-i860 45*a9fa9459Szrj@section i860 Command-line Options 46*a9fa9459Szrj@subsection SVR4 compatibility options 47*a9fa9459Szrj@table @code 48*a9fa9459Szrj@item -V 49*a9fa9459SzrjPrint assembler version. 50*a9fa9459Szrj@item -Qy 51*a9fa9459SzrjIgnored. 52*a9fa9459Szrj@item -Qn 53*a9fa9459SzrjIgnored. 54*a9fa9459Szrj@end table 55*a9fa9459Szrj@subsection Other options 56*a9fa9459Szrj@table @code 57*a9fa9459Szrj@item -EL 58*a9fa9459SzrjSelect little endian output (this is the default). 59*a9fa9459Szrj@item -EB 60*a9fa9459SzrjSelect big endian output. Note that the i860 always reads instructions 61*a9fa9459Szrjas little endian data, so this option only effects data and not 62*a9fa9459Szrjinstructions. 63*a9fa9459Szrj@item -mwarn-expand 64*a9fa9459SzrjEmit a warning message if any pseudo-instruction expansions occurred. 65*a9fa9459SzrjFor example, a @code{or} instruction with an immediate larger than 16-bits 66*a9fa9459Szrjwill be expanded into two instructions. This is a very undesirable feature to 67*a9fa9459Szrjrely on, so this flag can help detect any code where it happens. One 68*a9fa9459Szrjuse of it, for instance, has been to find and eliminate any place 69*a9fa9459Szrjwhere @code{gcc} may emit these pseudo-instructions. 70*a9fa9459Szrj@item -mxp 71*a9fa9459SzrjEnable support for the i860XP instructions and control registers. By default, 72*a9fa9459Szrjthis option is disabled so that only the base instruction set (i.e., i860XR) 73*a9fa9459Szrjis supported. 74*a9fa9459Szrj@item -mintel-syntax 75*a9fa9459SzrjThe i860 assembler defaults to AT&T/SVR4 syntax. This option enables the 76*a9fa9459SzrjIntel syntax. 77*a9fa9459Szrj@end table 78*a9fa9459Szrj 79*a9fa9459Szrj@node Directives-i860 80*a9fa9459Szrj@section i860 Machine Directives 81*a9fa9459Szrj 82*a9fa9459Szrj@cindex machine directives, i860 83*a9fa9459Szrj@cindex i860 machine directives 84*a9fa9459Szrj 85*a9fa9459Szrj@table @code 86*a9fa9459Szrj@cindex @code{dual} directive, i860 87*a9fa9459Szrj@item .dual 88*a9fa9459SzrjEnter dual instruction mode. While this directive is supported, the 89*a9fa9459Szrjpreferred way to use dual instruction mode is to explicitly code 90*a9fa9459Szrjthe dual bit with the @code{d.} prefix. 91*a9fa9459Szrj@end table 92*a9fa9459Szrj 93*a9fa9459Szrj@table @code 94*a9fa9459Szrj@cindex @code{enddual} directive, i860 95*a9fa9459Szrj@item .enddual 96*a9fa9459SzrjExit dual instruction mode. While this directive is supported, the 97*a9fa9459Szrjpreferred way to use dual instruction mode is to explicitly code 98*a9fa9459Szrjthe dual bit with the @code{d.} prefix. 99*a9fa9459Szrj@end table 100*a9fa9459Szrj 101*a9fa9459Szrj@table @code 102*a9fa9459Szrj@cindex @code{atmp} directive, i860 103*a9fa9459Szrj@item .atmp 104*a9fa9459SzrjChange the temporary register used when expanding pseudo operations. The 105*a9fa9459Szrjdefault register is @code{r31}. 106*a9fa9459Szrj@end table 107*a9fa9459Szrj 108*a9fa9459SzrjThe @code{.dual}, @code{.enddual}, and @code{.atmp} directives are available only in the Intel syntax mode. 109*a9fa9459Szrj 110*a9fa9459SzrjBoth syntaxes allow for the standard @code{.align} directive. However, 111*a9fa9459Szrjthe Intel syntax additionally allows keywords for the alignment 112*a9fa9459Szrjparameter: "@code{.align type}", where `type' is one of @code{.short}, @code{.long}, 113*a9fa9459Szrj@code{.quad}, @code{.single}, @code{.double} representing alignments of 2, 4, 114*a9fa9459Szrj16, 4, and 8, respectively. 115*a9fa9459Szrj 116*a9fa9459Szrj@node Opcodes for i860 117*a9fa9459Szrj@section i860 Opcodes 118*a9fa9459Szrj 119*a9fa9459Szrj@cindex opcodes, i860 120*a9fa9459Szrj@cindex i860 opcodes 121*a9fa9459SzrjAll of the Intel i860XR and i860XP machine instructions are supported. Please see 122*a9fa9459Szrjeither @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information. 123*a9fa9459Szrj@subsection Other instruction support (pseudo-instructions) 124*a9fa9459SzrjFor compatibility with some other i860 assemblers, a number of 125*a9fa9459Szrjpseudo-instructions are supported. While these are supported, they are 126*a9fa9459Szrja very undesirable feature that should be avoided -- in particular, when 127*a9fa9459Szrjthey result in an expansion to multiple actual i860 instructions. Below 128*a9fa9459Szrjare the pseudo-instructions that result in expansions. 129*a9fa9459Szrj@itemize @bullet 130*a9fa9459Szrj@item Load large immediate into general register: 131*a9fa9459Szrj 132*a9fa9459SzrjThe pseudo-instruction @code{mov imm,%rn} (where the immediate does 133*a9fa9459Szrjnot fit within a signed 16-bit field) will be expanded into: 134*a9fa9459Szrj@smallexample 135*a9fa9459Szrjorh large_imm@@h,%r0,%rn 136*a9fa9459Szrjor large_imm@@l,%rn,%rn 137*a9fa9459Szrj@end smallexample 138*a9fa9459Szrj@item Load/store with relocatable address expression: 139*a9fa9459Szrj 140*a9fa9459SzrjFor example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn} 141*a9fa9459Szrjwill be expanded into: 142*a9fa9459Szrj@smallexample 143*a9fa9459Szrjorh addr_exp@@ha,%rx,%r31 144*a9fa9459Szrjld.l addr_exp@@l(%r31),%rn 145*a9fa9459Szrj@end smallexample 146*a9fa9459Szrj 147*a9fa9459SzrjThe analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well. 148*a9fa9459Szrj@item Signed large immediate with add/subtract: 149*a9fa9459Szrj 150*a9fa9459SzrjIf any of the arithmetic operations @code{adds, addu, subs, subu} are used 151*a9fa9459Szrjwith an immediate larger than 16-bits (signed), then they will be expanded. 152*a9fa9459SzrjFor instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to: 153*a9fa9459Szrj@smallexample 154*a9fa9459Szrjorh large_imm@@h,%r0,%r31 155*a9fa9459Szrjor large_imm@@l,%r31,%r31 156*a9fa9459Szrjadds %r31,%rx,%rn 157*a9fa9459Szrj@end smallexample 158*a9fa9459Szrj@item Unsigned large immediate with logical operations: 159*a9fa9459Szrj 160*a9fa9459SzrjLogical operations (@code{or, andnot, or, xor}) also result in expansions. 161*a9fa9459SzrjThe pseudo-instruction @code{or large_imm,%rx,%rn} results in: 162*a9fa9459Szrj@smallexample 163*a9fa9459Szrjorh large_imm@@h,%rx,%r31 164*a9fa9459Szrjor large_imm@@l,%r31,%rn 165*a9fa9459Szrj@end smallexample 166*a9fa9459Szrj 167*a9fa9459SzrjSimilarly for the others, except for @code{and} which expands to: 168*a9fa9459Szrj@smallexample 169*a9fa9459Szrjandnot (-1 - large_imm)@@h,%rx,%r31 170*a9fa9459Szrjandnot (-1 - large_imm)@@l,%r31,%rn 171*a9fa9459Szrj@end smallexample 172*a9fa9459Szrj@end itemize 173*a9fa9459Szrj 174*a9fa9459Szrj@node Syntax of i860 175*a9fa9459Szrj@section i860 Syntax 176*a9fa9459Szrj@menu 177*a9fa9459Szrj* i860-Chars:: Special Characters 178*a9fa9459Szrj@end menu 179*a9fa9459Szrj 180*a9fa9459Szrj@node i860-Chars 181*a9fa9459Szrj@subsection Special Characters 182*a9fa9459Szrj 183*a9fa9459Szrj@cindex line comment character, i860 184*a9fa9459Szrj@cindex i860 line comment character 185*a9fa9459SzrjThe presence of a @samp{#} appearing anywhere on a line indicates the 186*a9fa9459Szrjstart of a comment that extends to the end of that line. 187*a9fa9459Szrj 188*a9fa9459SzrjIf a @samp{#} appears as the first character of a line then the whole 189*a9fa9459Szrjline is treated as a comment, but in this case the line can also be a 190*a9fa9459Szrjlogical line number directive (@pxref{Comments}) or a preprocessor 191*a9fa9459Szrjcontrol command (@pxref{Preprocessing}). 192*a9fa9459Szrj 193*a9fa9459Szrj@cindex line separator, i860 194*a9fa9459Szrj@cindex statement separator, i860 195*a9fa9459Szrj@cindex i860 line separator 196*a9fa9459SzrjThe @samp{;} character can be used to separate statements on the same 197*a9fa9459Szrjline. 198