1@c Copyright (C) 2000-2016 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@ifset GENERIC 5@page 6@node i860-Dependent 7@chapter Intel i860 Dependent Features 8@end ifset 9@ifclear GENERIC 10@node Machine Dependencies 11@chapter Intel i860 Dependent Features 12@end ifclear 13 14@ignore 15@c FIXME: This is basically a stub for i860. There is tons more information 16that I will add later (jle@cygnus.com). 17@end ignore 18 19@cindex i860 support 20@menu 21* Notes-i860:: i860 Notes 22* Options-i860:: i860 Command-line Options 23* Directives-i860:: i860 Machine Directives 24* Opcodes for i860:: i860 Opcodes 25* Syntax of i860:: i860 Syntax 26@end menu 27 28@node Notes-i860 29@section i860 Notes 30This is a fairly complete i860 assembler which is compatible with the 31UNIX System V/860 Release 4 assembler. However, it does not currently 32support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}). 33 34Like the SVR4/860 assembler, the output object format is ELF32. Currently, 35this is the only supported object format. If there is sufficient interest, 36other formats such as COFF may be implemented. 37 38Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter 39being the default. One difference is that AT&T syntax requires the '%' 40prefix on register names while Intel syntax does not. Another difference 41is in the specification of relocatable expressions. The Intel syntax 42is @code{ha%expression} whereas the SVR4 syntax is @code{[expression]@@ha} 43(and similarly for the "l" and "h" selectors). 44@node Options-i860 45@section i860 Command-line Options 46@subsection SVR4 compatibility options 47@table @code 48@item -V 49Print assembler version. 50@item -Qy 51Ignored. 52@item -Qn 53Ignored. 54@end table 55@subsection Other options 56@table @code 57@item -EL 58Select little endian output (this is the default). 59@item -EB 60Select big endian output. Note that the i860 always reads instructions 61as little endian data, so this option only effects data and not 62instructions. 63@item -mwarn-expand 64Emit a warning message if any pseudo-instruction expansions occurred. 65For example, a @code{or} instruction with an immediate larger than 16-bits 66will be expanded into two instructions. This is a very undesirable feature to 67rely on, so this flag can help detect any code where it happens. One 68use of it, for instance, has been to find and eliminate any place 69where @code{gcc} may emit these pseudo-instructions. 70@item -mxp 71Enable support for the i860XP instructions and control registers. By default, 72this option is disabled so that only the base instruction set (i.e., i860XR) 73is supported. 74@item -mintel-syntax 75The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the 76Intel syntax. 77@end table 78 79@node Directives-i860 80@section i860 Machine Directives 81 82@cindex machine directives, i860 83@cindex i860 machine directives 84 85@table @code 86@cindex @code{dual} directive, i860 87@item .dual 88Enter dual instruction mode. While this directive is supported, the 89preferred way to use dual instruction mode is to explicitly code 90the dual bit with the @code{d.} prefix. 91@end table 92 93@table @code 94@cindex @code{enddual} directive, i860 95@item .enddual 96Exit dual instruction mode. While this directive is supported, the 97preferred way to use dual instruction mode is to explicitly code 98the dual bit with the @code{d.} prefix. 99@end table 100 101@table @code 102@cindex @code{atmp} directive, i860 103@item .atmp 104Change the temporary register used when expanding pseudo operations. The 105default register is @code{r31}. 106@end table 107 108The @code{.dual}, @code{.enddual}, and @code{.atmp} directives are available only in the Intel syntax mode. 109 110Both syntaxes allow for the standard @code{.align} directive. However, 111the Intel syntax additionally allows keywords for the alignment 112parameter: "@code{.align type}", where `type' is one of @code{.short}, @code{.long}, 113@code{.quad}, @code{.single}, @code{.double} representing alignments of 2, 4, 11416, 4, and 8, respectively. 115 116@node Opcodes for i860 117@section i860 Opcodes 118 119@cindex opcodes, i860 120@cindex i860 opcodes 121All of the Intel i860XR and i860XP machine instructions are supported. Please see 122either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information. 123@subsection Other instruction support (pseudo-instructions) 124For compatibility with some other i860 assemblers, a number of 125pseudo-instructions are supported. While these are supported, they are 126a very undesirable feature that should be avoided -- in particular, when 127they result in an expansion to multiple actual i860 instructions. Below 128are the pseudo-instructions that result in expansions. 129@itemize @bullet 130@item Load large immediate into general register: 131 132The pseudo-instruction @code{mov imm,%rn} (where the immediate does 133not fit within a signed 16-bit field) will be expanded into: 134@smallexample 135orh large_imm@@h,%r0,%rn 136or large_imm@@l,%rn,%rn 137@end smallexample 138@item Load/store with relocatable address expression: 139 140For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn} 141will be expanded into: 142@smallexample 143orh addr_exp@@ha,%rx,%r31 144ld.l addr_exp@@l(%r31),%rn 145@end smallexample 146 147The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well. 148@item Signed large immediate with add/subtract: 149 150If any of the arithmetic operations @code{adds, addu, subs, subu} are used 151with an immediate larger than 16-bits (signed), then they will be expanded. 152For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to: 153@smallexample 154orh large_imm@@h,%r0,%r31 155or large_imm@@l,%r31,%r31 156adds %r31,%rx,%rn 157@end smallexample 158@item Unsigned large immediate with logical operations: 159 160Logical operations (@code{or, andnot, or, xor}) also result in expansions. 161The pseudo-instruction @code{or large_imm,%rx,%rn} results in: 162@smallexample 163orh large_imm@@h,%rx,%r31 164or large_imm@@l,%r31,%rn 165@end smallexample 166 167Similarly for the others, except for @code{and} which expands to: 168@smallexample 169andnot (-1 - large_imm)@@h,%rx,%r31 170andnot (-1 - large_imm)@@l,%r31,%rn 171@end smallexample 172@end itemize 173 174@node Syntax of i860 175@section i860 Syntax 176@menu 177* i860-Chars:: Special Characters 178@end menu 179 180@node i860-Chars 181@subsection Special Characters 182 183@cindex line comment character, i860 184@cindex i860 line comment character 185The presence of a @samp{#} appearing anywhere on a line indicates the 186start of a comment that extends to the end of that line. 187 188If a @samp{#} appears as the first character of a line then the whole 189line is treated as a comment, but in this case the line can also be a 190logical line number directive (@pxref{Comments}) or a preprocessor 191control command (@pxref{Preprocessing}). 192 193@cindex line separator, i860 194@cindex statement separator, i860 195@cindex i860 line separator 196The @samp{;} character can be used to separate statements on the same 197line. 198