1*a9fa9459Szrj@c Copyright (C) 2002-2016 Free Software Foundation, Inc. 2*a9fa9459Szrj@c Contributed by David Mosberger-Tang <davidm@hpl.hp.com> 3*a9fa9459Szrj@c This is part of the GAS manual. 4*a9fa9459Szrj@c For copying conditions, see the file as.texinfo. 5*a9fa9459Szrj 6*a9fa9459Szrj@ifset GENERIC 7*a9fa9459Szrj@page 8*a9fa9459Szrj@node IA-64-Dependent 9*a9fa9459Szrj@chapter IA-64 Dependent Features 10*a9fa9459Szrj@end ifset 11*a9fa9459Szrj 12*a9fa9459Szrj@ifclear GENERIC 13*a9fa9459Szrj@node Machine Dependencies 14*a9fa9459Szrj@chapter IA-64 Dependent Features 15*a9fa9459Szrj@end ifclear 16*a9fa9459Szrj 17*a9fa9459Szrj@cindex IA-64 support 18*a9fa9459Szrj@menu 19*a9fa9459Szrj* IA-64 Options:: Options 20*a9fa9459Szrj* IA-64 Syntax:: Syntax 21*a9fa9459Szrj@c * IA-64 Floating Point:: Floating Point // to be written 22*a9fa9459Szrj@c * IA-64 Directives:: IA-64 Machine Directives // to be written 23*a9fa9459Szrj* IA-64 Opcodes:: Opcodes 24*a9fa9459Szrj@end menu 25*a9fa9459Szrj 26*a9fa9459Szrj@node IA-64 Options 27*a9fa9459Szrj@section Options 28*a9fa9459Szrj@cindex IA-64 options 29*a9fa9459Szrj@cindex options for IA-64 30*a9fa9459Szrj 31*a9fa9459Szrj@table @option 32*a9fa9459Szrj@cindex @code{-mconstant-gp} command line option, IA-64 33*a9fa9459Szrj 34*a9fa9459Szrj@item -mconstant-gp 35*a9fa9459SzrjThis option instructs the assembler to mark the resulting object file 36*a9fa9459Szrjas using the ``constant GP'' model. With this model, it is assumed 37*a9fa9459Szrjthat the entire program uses a single global pointer (GP) value. Note 38*a9fa9459Szrjthat this option does not in any fashion affect the machine code 39*a9fa9459Szrjemitted by the assembler. All it does is turn on the EF_IA_64_CONS_GP 40*a9fa9459Szrjflag in the ELF file header. 41*a9fa9459Szrj 42*a9fa9459Szrj@item -mauto-pic 43*a9fa9459SzrjThis option instructs the assembler to mark the resulting object file 44*a9fa9459Szrjas using the ``constant GP without function descriptor'' data model. 45*a9fa9459SzrjThis model is like the ``constant GP'' model, except that it 46*a9fa9459Szrjadditionally does away with function descriptors. What this means is 47*a9fa9459Szrjthat the address of a function refers directly to the function's code 48*a9fa9459Szrjentry-point. Normally, such an address would refer to a function 49*a9fa9459Szrjdescriptor, which contains both the code entry-point and the GP-value 50*a9fa9459Szrjneeded by the function. Note that this option does not in any fashion 51*a9fa9459Szrjaffect the machine code emitted by the assembler. All it does is 52*a9fa9459Szrjturn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. 53*a9fa9459Szrj 54*a9fa9459Szrj@item -milp32 55*a9fa9459Szrj@itemx -milp64 56*a9fa9459Szrj@itemx -mlp64 57*a9fa9459Szrj@itemx -mp64 58*a9fa9459SzrjThese options select the data model. The assembler defaults to @code{-mlp64} 59*a9fa9459Szrj(LP64 data model). 60*a9fa9459Szrj 61*a9fa9459Szrj@item -mle 62*a9fa9459Szrj@itemx -mbe 63*a9fa9459SzrjThese options select the byte order. The @code{-mle} option selects little-endian 64*a9fa9459Szrjbyte order (default) and @code{-mbe} selects big-endian byte order. Note that 65*a9fa9459SzrjIA-64 machine code always uses little-endian byte order. 66*a9fa9459Szrj 67*a9fa9459Szrj@item -mtune=itanium1 68*a9fa9459Szrj@itemx -mtune=itanium2 69*a9fa9459SzrjTune for a particular IA-64 CPU, @var{itanium1} or @var{itanium2}. The 70*a9fa9459Szrjdefault is @var{itanium2}. 71*a9fa9459Szrj 72*a9fa9459Szrj@item -munwind-check=warning 73*a9fa9459Szrj@itemx -munwind-check=error 74*a9fa9459SzrjThese options control what the assembler will do when performing 75*a9fa9459Szrjconsistency checks on unwind directives. @code{-munwind-check=warning} 76*a9fa9459Szrjwill make the assembler issue a warning when an unwind directive check 77*a9fa9459Szrjfails. This is the default. @code{-munwind-check=error} will make the 78*a9fa9459Szrjassembler issue an error when an unwind directive check fails. 79*a9fa9459Szrj 80*a9fa9459Szrj@item -mhint.b=ok 81*a9fa9459Szrj@itemx -mhint.b=warning 82*a9fa9459Szrj@itemx -mhint.b=error 83*a9fa9459SzrjThese options control what the assembler will do when the @samp{hint.b} 84*a9fa9459Szrjinstruction is used. @code{-mhint.b=ok} will make the assembler accept 85*a9fa9459Szrj@samp{hint.b}. @code{-mint.b=warning} will make the assembler issue a 86*a9fa9459Szrjwarning when @samp{hint.b} is used. @code{-mhint.b=error} will make 87*a9fa9459Szrjthe assembler treat @samp{hint.b} as an error, which is the default. 88*a9fa9459Szrj 89*a9fa9459Szrj@item -x 90*a9fa9459Szrj@itemx -xexplicit 91*a9fa9459SzrjThese options turn on dependency violation checking. 92*a9fa9459Szrj 93*a9fa9459Szrj@item -xauto 94*a9fa9459SzrjThis option instructs the assembler to automatically insert stop bits where necessary 95*a9fa9459Szrjto remove dependency violations. This is the default mode. 96*a9fa9459Szrj 97*a9fa9459Szrj@item -xnone 98*a9fa9459SzrjThis option turns off dependency violation checking. 99*a9fa9459Szrj 100*a9fa9459Szrj@item -xdebug 101*a9fa9459SzrjThis turns on debug output intended to help tracking down bugs in the dependency 102*a9fa9459Szrjviolation checker. 103*a9fa9459Szrj 104*a9fa9459Szrj@item -xdebugn 105*a9fa9459SzrjThis is a shortcut for -xnone -xdebug. 106*a9fa9459Szrj 107*a9fa9459Szrj@item -xdebugx 108*a9fa9459SzrjThis is a shortcut for -xexplicit -xdebug. 109*a9fa9459Szrj 110*a9fa9459Szrj@end table 111*a9fa9459Szrj 112*a9fa9459Szrj@cindex IA-64 Syntax 113*a9fa9459Szrj@node IA-64 Syntax 114*a9fa9459Szrj@section Syntax 115*a9fa9459SzrjThe assembler syntax closely follows the IA-64 Assembly Language 116*a9fa9459SzrjReference Guide. 117*a9fa9459Szrj 118*a9fa9459Szrj@menu 119*a9fa9459Szrj* IA-64-Chars:: Special Characters 120*a9fa9459Szrj* IA-64-Regs:: Register Names 121*a9fa9459Szrj* IA-64-Bits:: Bit Names 122*a9fa9459Szrj* IA-64-Relocs:: Relocations 123*a9fa9459Szrj@end menu 124*a9fa9459Szrj 125*a9fa9459Szrj@node IA-64-Chars 126*a9fa9459Szrj@subsection Special Characters 127*a9fa9459Szrj 128*a9fa9459Szrj@cindex line comment character, IA-64 129*a9fa9459Szrj@cindex IA-64 line comment character 130*a9fa9459Szrj@samp{//} is the line comment token. 131*a9fa9459Szrj 132*a9fa9459Szrj@cindex line separator, IA-64 133*a9fa9459Szrj@cindex statement separator, IA-64 134*a9fa9459Szrj@cindex IA-64 line separator 135*a9fa9459Szrj@samp{;} can be used instead of a newline to separate statements. 136*a9fa9459Szrj 137*a9fa9459Szrj@node IA-64-Regs 138*a9fa9459Szrj@subsection Register Names 139*a9fa9459Szrj@cindex IA-64 registers 140*a9fa9459Szrj@cindex register names, IA-64 141*a9fa9459Szrj 142*a9fa9459SzrjThe 128 integer registers are referred to as @samp{r@var{n}}. 143*a9fa9459SzrjThe 128 floating-point registers are referred to as @samp{f@var{n}}. 144*a9fa9459SzrjThe 128 application registers are referred to as @samp{ar@var{n}}. 145*a9fa9459SzrjThe 128 control registers are referred to as @samp{cr@var{n}}. 146*a9fa9459SzrjThe 64 one-bit predicate registers are referred to as @samp{p@var{n}}. 147*a9fa9459SzrjThe 8 branch registers are referred to as @samp{b@var{n}}. 148*a9fa9459SzrjIn addition, the assembler defines a number of aliases: 149*a9fa9459Szrj@samp{gp} (@samp{r1}), @samp{sp} (@samp{r12}), @samp{rp} (@samp{b0}), 150*a9fa9459Szrj@samp{ret0} (@samp{r8}), @samp{ret1} (@samp{r9}), @samp{ret2} (@samp{r10}), 151*a9fa9459Szrj@samp{ret3} (@samp{r9}), @samp{farg@var{n}} (@samp{f8+@var{n}}), and 152*a9fa9459Szrj@samp{fret@var{n}} (@samp{f8+@var{n}}). 153*a9fa9459Szrj 154*a9fa9459SzrjFor convenience, the assembler also defines aliases for all named application 155*a9fa9459Szrjand control registers. For example, @samp{ar.bsp} refers to the register 156*a9fa9459Szrjbacking store pointer (@samp{ar17}). Similarly, @samp{cr.eoi} refers to 157*a9fa9459Szrjthe end-of-interrupt register (@samp{cr67}). 158*a9fa9459Szrj 159*a9fa9459Szrj@node IA-64-Bits 160*a9fa9459Szrj@subsection IA-64 Processor-Status-Register (PSR) Bit Names 161*a9fa9459Szrj@cindex IA-64 Processor-status-Register bit names 162*a9fa9459Szrj@cindex PSR bits 163*a9fa9459Szrj@cindex bit names, IA-64 164*a9fa9459Szrj 165*a9fa9459SzrjThe assembler defines bit masks for each of the bits in the IA-64 166*a9fa9459Szrjprocessor status register. For example, @samp{psr.ic} corresponds to 167*a9fa9459Szrja value of 0x2000. These masks are primarily intended for use with 168*a9fa9459Szrjthe @samp{ssm}/@samp{sum} and @samp{rsm}/@samp{rum} 169*a9fa9459Szrjinstructions, but they can be used anywhere else where an integer 170*a9fa9459Szrjconstant is expected. 171*a9fa9459Szrj 172*a9fa9459Szrj@node IA-64-Relocs 173*a9fa9459Szrj@subsection Relocations 174*a9fa9459Szrj@cindex IA-64 relocations 175*a9fa9459Szrj 176*a9fa9459SzrjIn addition to the standard IA-64 relocations, the following relocations are 177*a9fa9459Szrjimplemented by @code{@value{AS}}: 178*a9fa9459Szrj 179*a9fa9459Szrj@table @code 180*a9fa9459Szrj@item @@slotcount(@var{V}) 181*a9fa9459SzrjConvert the address offset @var{V} into a slot count. This pseudo 182*a9fa9459Szrjfunction is available only on VMS. The expression @var{V} must be 183*a9fa9459Szrjknown at assembly time: it can't reference undefined symbols or symbols in 184*a9fa9459Szrjdifferent sections. 185*a9fa9459Szrj@end table 186*a9fa9459Szrj 187*a9fa9459Szrj@node IA-64 Opcodes 188*a9fa9459Szrj@section Opcodes 189*a9fa9459SzrjFor detailed information on the IA-64 machine instruction set, see the 190*a9fa9459Szrj@c Attempt to work around a very overfull hbox. 191*a9fa9459Szrj@iftex 192*a9fa9459SzrjIA-64 Assembly Language Reference Guide available at 193*a9fa9459Szrj@smallfonts 194*a9fa9459Szrj@example 195*a9fa9459Szrjhttp://developer.intel.com/design/itanium/arch_spec.htm 196*a9fa9459Szrj@end example 197*a9fa9459Szrj@textfonts 198*a9fa9459Szrj@end iftex 199*a9fa9459Szrj@ifnottex 200*a9fa9459Szrj@uref{http://developer.intel.com/design/itanium/arch_spec.htm,IA-64 Architecture Handbook}. 201*a9fa9459Szrj@end ifnottex 202