1*a9fa9459Szrj@c Copyright (C) 1991-2016 Free Software Foundation, Inc. 2*a9fa9459Szrj@c This is part of the GAS manual. 3*a9fa9459Szrj@c For copying conditions, see the file as.texinfo. 4*a9fa9459Szrj@ifset GENERIC 5*a9fa9459Szrj@page 6*a9fa9459Szrj@node MIPS-Dependent 7*a9fa9459Szrj@chapter MIPS Dependent Features 8*a9fa9459Szrj@end ifset 9*a9fa9459Szrj@ifclear GENERIC 10*a9fa9459Szrj@node Machine Dependencies 11*a9fa9459Szrj@chapter MIPS Dependent Features 12*a9fa9459Szrj@end ifclear 13*a9fa9459Szrj 14*a9fa9459Szrj@cindex MIPS processor 15*a9fa9459Szrj@sc{gnu} @code{@value{AS}} for MIPS architectures supports several 16*a9fa9459Szrjdifferent MIPS processors, and MIPS ISA levels I through V, MIPS32, 17*a9fa9459Szrjand MIPS64. For information about the MIPS instruction set, see 18*a9fa9459Szrj@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). 19*a9fa9459SzrjFor an overview of MIPS assembly conventions, see ``Appendix D: 20*a9fa9459SzrjAssembly Language Programming'' in the same work. 21*a9fa9459Szrj 22*a9fa9459Szrj@menu 23*a9fa9459Szrj* MIPS Options:: Assembler options 24*a9fa9459Szrj* MIPS Macros:: High-level assembly macros 25*a9fa9459Szrj* MIPS Symbol Sizes:: Directives to override the size of symbols 26*a9fa9459Szrj* MIPS Small Data:: Controlling the use of small data accesses 27*a9fa9459Szrj* MIPS ISA:: Directives to override the ISA level 28*a9fa9459Szrj* MIPS assembly options:: Directives to control code generation 29*a9fa9459Szrj* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 30*a9fa9459Szrj* MIPS insn:: Directive to mark data as an instruction 31*a9fa9459Szrj* MIPS FP ABIs:: Marking which FP ABI is in use 32*a9fa9459Szrj* MIPS NaN Encodings:: Directives to record which NaN encoding is being used 33*a9fa9459Szrj* MIPS Option Stack:: Directives to save and restore options 34*a9fa9459Szrj* MIPS ASE Instruction Generation Overrides:: Directives to control 35*a9fa9459Szrj generation of MIPS ASE instructions 36*a9fa9459Szrj* MIPS Floating-Point:: Directives to override floating-point options 37*a9fa9459Szrj* MIPS Syntax:: MIPS specific syntactical considerations 38*a9fa9459Szrj@end menu 39*a9fa9459Szrj 40*a9fa9459Szrj@node MIPS Options 41*a9fa9459Szrj@section Assembler options 42*a9fa9459Szrj 43*a9fa9459SzrjThe MIPS configurations of @sc{gnu} @code{@value{AS}} support these 44*a9fa9459Szrjspecial options: 45*a9fa9459Szrj 46*a9fa9459Szrj@table @code 47*a9fa9459Szrj@cindex @code{-G} option (MIPS) 48*a9fa9459Szrj@item -G @var{num} 49*a9fa9459SzrjSet the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes. 50*a9fa9459Szrj@xref{MIPS Small Data,, Controlling the use of small data accesses}. 51*a9fa9459Szrj 52*a9fa9459Szrj@cindex @code{-EB} option (MIPS) 53*a9fa9459Szrj@cindex @code{-EL} option (MIPS) 54*a9fa9459Szrj@cindex MIPS big-endian output 55*a9fa9459Szrj@cindex MIPS little-endian output 56*a9fa9459Szrj@cindex big-endian output, MIPS 57*a9fa9459Szrj@cindex little-endian output, MIPS 58*a9fa9459Szrj@item -EB 59*a9fa9459Szrj@itemx -EL 60*a9fa9459SzrjAny MIPS configuration of @code{@value{AS}} can select big-endian or 61*a9fa9459Szrjlittle-endian output at run time (unlike the other @sc{gnu} development 62*a9fa9459Szrjtools, which must be configured for one or the other). Use @samp{-EB} 63*a9fa9459Szrjto select big-endian output, and @samp{-EL} for little-endian. 64*a9fa9459Szrj 65*a9fa9459Szrj@item -KPIC 66*a9fa9459Szrj@cindex PIC selection, MIPS 67*a9fa9459Szrj@cindex @option{-KPIC} option, MIPS 68*a9fa9459SzrjGenerate SVR4-style PIC. This option tells the assembler to generate 69*a9fa9459SzrjSVR4-style position-independent macro expansions. It also tells the 70*a9fa9459Szrjassembler to mark the output file as PIC. 71*a9fa9459Szrj 72*a9fa9459Szrj@item -mvxworks-pic 73*a9fa9459Szrj@cindex @option{-mvxworks-pic} option, MIPS 74*a9fa9459SzrjGenerate VxWorks PIC. This option tells the assembler to generate 75*a9fa9459SzrjVxWorks-style position-independent macro expansions. 76*a9fa9459Szrj 77*a9fa9459Szrj@cindex MIPS architecture options 78*a9fa9459Szrj@item -mips1 79*a9fa9459Szrj@itemx -mips2 80*a9fa9459Szrj@itemx -mips3 81*a9fa9459Szrj@itemx -mips4 82*a9fa9459Szrj@itemx -mips5 83*a9fa9459Szrj@itemx -mips32 84*a9fa9459Szrj@itemx -mips32r2 85*a9fa9459Szrj@itemx -mips32r3 86*a9fa9459Szrj@itemx -mips32r5 87*a9fa9459Szrj@itemx -mips32r6 88*a9fa9459Szrj@itemx -mips64 89*a9fa9459Szrj@itemx -mips64r2 90*a9fa9459Szrj@itemx -mips64r3 91*a9fa9459Szrj@itemx -mips64r5 92*a9fa9459Szrj@itemx -mips64r6 93*a9fa9459SzrjGenerate code for a particular MIPS Instruction Set Architecture level. 94*a9fa9459Szrj@samp{-mips1} corresponds to the R2000 and R3000 processors, 95*a9fa9459Szrj@samp{-mips2} to the R6000 processor, @samp{-mips3} to the 96*a9fa9459SzrjR4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. 97*a9fa9459Szrj@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, 98*a9fa9459Szrj@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, 99*a9fa9459Szrj@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to 100*a9fa9459Szrjgeneric MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 101*a9fa9459SzrjRelease 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 102*a9fa9459SzrjRelease 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, 103*a9fa9459Szrjrespectively. You can also switch instruction sets during the assembly; 104*a9fa9459Szrjsee @ref{MIPS ISA, Directives to override the ISA level}. 105*a9fa9459Szrj 106*a9fa9459Szrj@item -mgp32 107*a9fa9459Szrj@itemx -mfp32 108*a9fa9459SzrjSome macros have different expansions for 32-bit and 64-bit registers. 109*a9fa9459SzrjThe register sizes are normally inferred from the ISA and ABI, but these 110*a9fa9459Szrjflags force a certain group of registers to be treated as 32 bits wide at 111*a9fa9459Szrjall times. @samp{-mgp32} controls the size of general-purpose registers 112*a9fa9459Szrjand @samp{-mfp32} controls the size of floating-point registers. 113*a9fa9459Szrj 114*a9fa9459SzrjThe @code{.set gp=32} and @code{.set fp=32} directives allow the size 115*a9fa9459Szrjof registers to be changed for parts of an object. The default value is 116*a9fa9459Szrjrestored by @code{.set gp=default} and @code{.set fp=default}. 117*a9fa9459Szrj 118*a9fa9459SzrjOn some MIPS variants there is a 32-bit mode flag; when this flag is 119*a9fa9459Szrjset, 64-bit instructions generate a trap. Also, some 32-bit OSes only 120*a9fa9459Szrjsave the 32-bit registers on a context switch, so it is essential never 121*a9fa9459Szrjto use the 64-bit registers. 122*a9fa9459Szrj 123*a9fa9459Szrj@item -mgp64 124*a9fa9459Szrj@itemx -mfp64 125*a9fa9459SzrjAssume that 64-bit registers are available. This is provided in the 126*a9fa9459Szrjinterests of symmetry with @samp{-mgp32} and @samp{-mfp32}. 127*a9fa9459Szrj 128*a9fa9459SzrjThe @code{.set gp=64} and @code{.set fp=64} directives allow the size 129*a9fa9459Szrjof registers to be changed for parts of an object. The default value is 130*a9fa9459Szrjrestored by @code{.set gp=default} and @code{.set fp=default}. 131*a9fa9459Szrj 132*a9fa9459Szrj@item -mfpxx 133*a9fa9459SzrjMake no assumptions about whether 32-bit or 64-bit floating-point 134*a9fa9459Szrjregisters are available. This is provided to support having modules 135*a9fa9459Szrjcompatible with either @samp{-mfp32} or @samp{-mfp64}. This option can 136*a9fa9459Szrjonly be used with MIPS II and above. 137*a9fa9459Szrj 138*a9fa9459SzrjThe @code{.set fp=xx} directive allows a part of an object to be marked 139*a9fa9459Szrjas not making assumptions about 32-bit or 64-bit FP registers. The 140*a9fa9459Szrjdefault value is restored by @code{.set fp=default}. 141*a9fa9459Szrj 142*a9fa9459Szrj@item -modd-spreg 143*a9fa9459Szrj@itemx -mno-odd-spreg 144*a9fa9459SzrjEnable use of floating-point operations on odd-numbered single-precision 145*a9fa9459Szrjregisters when supported by the ISA. @samp{-mfpxx} implies 146*a9fa9459Szrj@samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg} 147*a9fa9459Szrj 148*a9fa9459Szrj@item -mips16 149*a9fa9459Szrj@itemx -no-mips16 150*a9fa9459SzrjGenerate code for the MIPS 16 processor. This is equivalent to putting 151*a9fa9459Szrj@code{.set mips16} at the start of the assembly file. @samp{-no-mips16} 152*a9fa9459Szrjturns off this option. 153*a9fa9459Szrj 154*a9fa9459Szrj@item -mmicromips 155*a9fa9459Szrj@itemx -mno-micromips 156*a9fa9459SzrjGenerate code for the microMIPS processor. This is equivalent to putting 157*a9fa9459Szrj@code{.set micromips} at the start of the assembly file. @samp{-mno-micromips} 158*a9fa9459Szrjturns off this option. This is equivalent to putting @code{.set nomicromips} 159*a9fa9459Szrjat the start of the assembly file. 160*a9fa9459Szrj 161*a9fa9459Szrj@item -msmartmips 162*a9fa9459Szrj@itemx -mno-smartmips 163*a9fa9459SzrjEnables the SmartMIPS extensions to the MIPS32 instruction set, which 164*a9fa9459Szrjprovides a number of new instructions which target smartcard and 165*a9fa9459Szrjcryptographic applications. This is equivalent to putting 166*a9fa9459Szrj@code{.set smartmips} at the start of the assembly file. 167*a9fa9459Szrj@samp{-mno-smartmips} turns off this option. 168*a9fa9459Szrj 169*a9fa9459Szrj@item -mips3d 170*a9fa9459Szrj@itemx -no-mips3d 171*a9fa9459SzrjGenerate code for the MIPS-3D Application Specific Extension. 172*a9fa9459SzrjThis tells the assembler to accept MIPS-3D instructions. 173*a9fa9459Szrj@samp{-no-mips3d} turns off this option. 174*a9fa9459Szrj 175*a9fa9459Szrj@item -mdmx 176*a9fa9459Szrj@itemx -no-mdmx 177*a9fa9459SzrjGenerate code for the MDMX Application Specific Extension. 178*a9fa9459SzrjThis tells the assembler to accept MDMX instructions. 179*a9fa9459Szrj@samp{-no-mdmx} turns off this option. 180*a9fa9459Szrj 181*a9fa9459Szrj@item -mdsp 182*a9fa9459Szrj@itemx -mno-dsp 183*a9fa9459SzrjGenerate code for the DSP Release 1 Application Specific Extension. 184*a9fa9459SzrjThis tells the assembler to accept DSP Release 1 instructions. 185*a9fa9459Szrj@samp{-mno-dsp} turns off this option. 186*a9fa9459Szrj 187*a9fa9459Szrj@item -mdspr2 188*a9fa9459Szrj@itemx -mno-dspr2 189*a9fa9459SzrjGenerate code for the DSP Release 2 Application Specific Extension. 190*a9fa9459SzrjThis option implies @samp{-mdsp}. 191*a9fa9459SzrjThis tells the assembler to accept DSP Release 2 instructions. 192*a9fa9459Szrj@samp{-mno-dspr2} turns off this option. 193*a9fa9459Szrj 194*a9fa9459Szrj@item -mdspr3 195*a9fa9459Szrj@itemx -mno-dspr3 196*a9fa9459SzrjGenerate code for the DSP Release 3 Application Specific Extension. 197*a9fa9459SzrjThis option implies @samp{-mdsp} and @samp{-mdspr2}. 198*a9fa9459SzrjThis tells the assembler to accept DSP Release 3 instructions. 199*a9fa9459Szrj@samp{-mno-dspr3} turns off this option. 200*a9fa9459Szrj 201*a9fa9459Szrj@item -mmt 202*a9fa9459Szrj@itemx -mno-mt 203*a9fa9459SzrjGenerate code for the MT Application Specific Extension. 204*a9fa9459SzrjThis tells the assembler to accept MT instructions. 205*a9fa9459Szrj@samp{-mno-mt} turns off this option. 206*a9fa9459Szrj 207*a9fa9459Szrj@item -mmcu 208*a9fa9459Szrj@itemx -mno-mcu 209*a9fa9459SzrjGenerate code for the MCU Application Specific Extension. 210*a9fa9459SzrjThis tells the assembler to accept MCU instructions. 211*a9fa9459Szrj@samp{-mno-mcu} turns off this option. 212*a9fa9459Szrj 213*a9fa9459Szrj@item -mmsa 214*a9fa9459Szrj@itemx -mno-msa 215*a9fa9459SzrjGenerate code for the MIPS SIMD Architecture Extension. 216*a9fa9459SzrjThis tells the assembler to accept MSA instructions. 217*a9fa9459Szrj@samp{-mno-msa} turns off this option. 218*a9fa9459Szrj 219*a9fa9459Szrj@item -mxpa 220*a9fa9459Szrj@itemx -mno-xpa 221*a9fa9459SzrjGenerate code for the MIPS eXtended Physical Address (XPA) Extension. 222*a9fa9459SzrjThis tells the assembler to accept XPA instructions. 223*a9fa9459Szrj@samp{-mno-xpa} turns off this option. 224*a9fa9459Szrj 225*a9fa9459Szrj@item -mvirt 226*a9fa9459Szrj@itemx -mno-virt 227*a9fa9459SzrjGenerate code for the Virtualization Application Specific Extension. 228*a9fa9459SzrjThis tells the assembler to accept Virtualization instructions. 229*a9fa9459Szrj@samp{-mno-virt} turns off this option. 230*a9fa9459Szrj 231*a9fa9459Szrj@item -minsn32 232*a9fa9459Szrj@itemx -mno-insn32 233*a9fa9459SzrjOnly use 32-bit instruction encodings when generating code for the 234*a9fa9459SzrjmicroMIPS processor. This option inhibits the use of any 16-bit 235*a9fa9459Szrjinstructions. This is equivalent to putting @code{.set insn32} at 236*a9fa9459Szrjthe start of the assembly file. @samp{-mno-insn32} turns off this 237*a9fa9459Szrjoption. This is equivalent to putting @code{.set noinsn32} at the 238*a9fa9459Szrjstart of the assembly file. By default @samp{-mno-insn32} is 239*a9fa9459Szrjselected, allowing all instructions to be used. 240*a9fa9459Szrj 241*a9fa9459Szrj@item -mfix7000 242*a9fa9459Szrj@itemx -mno-fix7000 243*a9fa9459SzrjCause nops to be inserted if the read of the destination register 244*a9fa9459Szrjof an mfhi or mflo instruction occurs in the following two instructions. 245*a9fa9459Szrj 246*a9fa9459Szrj@item -mfix-rm7000 247*a9fa9459Szrj@itemx -mno-fix-rm7000 248*a9fa9459SzrjCause nops to be inserted if a dmult or dmultu instruction is 249*a9fa9459Szrjfollowed by a load instruction. 250*a9fa9459Szrj 251*a9fa9459Szrj@item -mfix-loongson2f-jump 252*a9fa9459Szrj@itemx -mno-fix-loongson2f-jump 253*a9fa9459SzrjEliminate instruction fetch from outside 256M region to work around the 254*a9fa9459SzrjLoongson2F @samp{jump} instructions. Without it, under extreme cases, 255*a9fa9459Szrjthe kernel may crash. The issue has been solved in latest processor 256*a9fa9459Szrjbatches, but this fix has no side effect to them. 257*a9fa9459Szrj 258*a9fa9459Szrj@item -mfix-loongson2f-nop 259*a9fa9459Szrj@itemx -mno-fix-loongson2f-nop 260*a9fa9459SzrjReplace nops by @code{or at,at,zero} to work around the Loongson2F 261*a9fa9459Szrj@samp{nop} errata. Without it, under extreme cases, the CPU might 262*a9fa9459Szrjdeadlock. The issue has been solved in later Loongson2F batches, but 263*a9fa9459Szrjthis fix has no side effect to them. 264*a9fa9459Szrj 265*a9fa9459Szrj@item -mfix-vr4120 266*a9fa9459Szrj@itemx -mno-fix-vr4120 267*a9fa9459SzrjInsert nops to work around certain VR4120 errata. This option is 268*a9fa9459Szrjintended to be used on GCC-generated code: it is not designed to catch 269*a9fa9459Szrjall problems in hand-written assembler code. 270*a9fa9459Szrj 271*a9fa9459Szrj@item -mfix-vr4130 272*a9fa9459Szrj@itemx -mno-fix-vr4130 273*a9fa9459SzrjInsert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. 274*a9fa9459Szrj 275*a9fa9459Szrj@item -mfix-24k 276*a9fa9459Szrj@itemx -mno-fix-24k 277*a9fa9459SzrjInsert nops to work around the 24K @samp{eret}/@samp{deret} errata. 278*a9fa9459Szrj 279*a9fa9459Szrj@item -mfix-cn63xxp1 280*a9fa9459Szrj@itemx -mno-fix-cn63xxp1 281*a9fa9459SzrjReplace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around 282*a9fa9459Szrjcertain CN63XXP1 errata. 283*a9fa9459Szrj 284*a9fa9459Szrj@item -m4010 285*a9fa9459Szrj@itemx -no-m4010 286*a9fa9459SzrjGenerate code for the LSI R4010 chip. This tells the assembler to 287*a9fa9459Szrjaccept the R4010-specific instructions (@samp{addciu}, @samp{ffc}, 288*a9fa9459Szrjetc.), and to not schedule @samp{nop} instructions around accesses to 289*a9fa9459Szrjthe @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this 290*a9fa9459Szrjoption. 291*a9fa9459Szrj 292*a9fa9459Szrj@item -m4650 293*a9fa9459Szrj@itemx -no-m4650 294*a9fa9459SzrjGenerate code for the MIPS R4650 chip. This tells the assembler to accept 295*a9fa9459Szrjthe @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} 296*a9fa9459Szrjinstructions around accesses to the @samp{HI} and @samp{LO} registers. 297*a9fa9459Szrj@samp{-no-m4650} turns off this option. 298*a9fa9459Szrj 299*a9fa9459Szrj@item -m3900 300*a9fa9459Szrj@itemx -no-m3900 301*a9fa9459Szrj@itemx -m4100 302*a9fa9459Szrj@itemx -no-m4100 303*a9fa9459SzrjFor each option @samp{-m@var{nnnn}}, generate code for the MIPS 304*a9fa9459SzrjR@var{nnnn} chip. This tells the assembler to accept instructions 305*a9fa9459Szrjspecific to that chip, and to schedule for that chip's hazards. 306*a9fa9459Szrj 307*a9fa9459Szrj@item -march=@var{cpu} 308*a9fa9459SzrjGenerate code for a particular MIPS CPU. It is exactly equivalent to 309*a9fa9459Szrj@samp{-m@var{cpu}}, except that there are more value of @var{cpu} 310*a9fa9459Szrjunderstood. Valid @var{cpu} value are: 311*a9fa9459Szrj 312*a9fa9459Szrj@quotation 313*a9fa9459Szrj2000, 314*a9fa9459Szrj3000, 315*a9fa9459Szrj3900, 316*a9fa9459Szrj4000, 317*a9fa9459Szrj4010, 318*a9fa9459Szrj4100, 319*a9fa9459Szrj4111, 320*a9fa9459Szrjvr4120, 321*a9fa9459Szrjvr4130, 322*a9fa9459Szrjvr4181, 323*a9fa9459Szrj4300, 324*a9fa9459Szrj4400, 325*a9fa9459Szrj4600, 326*a9fa9459Szrj4650, 327*a9fa9459Szrj5000, 328*a9fa9459Szrjrm5200, 329*a9fa9459Szrjrm5230, 330*a9fa9459Szrjrm5231, 331*a9fa9459Szrjrm5261, 332*a9fa9459Szrjrm5721, 333*a9fa9459Szrjvr5400, 334*a9fa9459Szrjvr5500, 335*a9fa9459Szrj6000, 336*a9fa9459Szrjrm7000, 337*a9fa9459Szrj8000, 338*a9fa9459Szrjrm9000, 339*a9fa9459Szrj10000, 340*a9fa9459Szrj12000, 341*a9fa9459Szrj14000, 342*a9fa9459Szrj16000, 343*a9fa9459Szrj4kc, 344*a9fa9459Szrj4km, 345*a9fa9459Szrj4kp, 346*a9fa9459Szrj4ksc, 347*a9fa9459Szrj4kec, 348*a9fa9459Szrj4kem, 349*a9fa9459Szrj4kep, 350*a9fa9459Szrj4ksd, 351*a9fa9459Szrjm4k, 352*a9fa9459Szrjm4kp, 353*a9fa9459Szrjm14k, 354*a9fa9459Szrjm14kc, 355*a9fa9459Szrjm14ke, 356*a9fa9459Szrjm14kec, 357*a9fa9459Szrj24kc, 358*a9fa9459Szrj24kf2_1, 359*a9fa9459Szrj24kf, 360*a9fa9459Szrj24kf1_1, 361*a9fa9459Szrj24kec, 362*a9fa9459Szrj24kef2_1, 363*a9fa9459Szrj24kef, 364*a9fa9459Szrj24kef1_1, 365*a9fa9459Szrj34kc, 366*a9fa9459Szrj34kf2_1, 367*a9fa9459Szrj34kf, 368*a9fa9459Szrj34kf1_1, 369*a9fa9459Szrj34kn, 370*a9fa9459Szrj74kc, 371*a9fa9459Szrj74kf2_1, 372*a9fa9459Szrj74kf, 373*a9fa9459Szrj74kf1_1, 374*a9fa9459Szrj74kf3_2, 375*a9fa9459Szrj1004kc, 376*a9fa9459Szrj1004kf2_1, 377*a9fa9459Szrj1004kf, 378*a9fa9459Szrj1004kf1_1, 379*a9fa9459Szrjinteraptiv, 380*a9fa9459Szrjm5100, 381*a9fa9459Szrjm5101, 382*a9fa9459Szrjp5600, 383*a9fa9459Szrj5kc, 384*a9fa9459Szrj5kf, 385*a9fa9459Szrj20kc, 386*a9fa9459Szrj25kf, 387*a9fa9459Szrjsb1, 388*a9fa9459Szrjsb1a, 389*a9fa9459Szrji6400, 390*a9fa9459Szrjp6600, 391*a9fa9459Szrjloongson2e, 392*a9fa9459Szrjloongson2f, 393*a9fa9459Szrjloongson3a, 394*a9fa9459Szrjocteon, 395*a9fa9459Szrjocteon+, 396*a9fa9459Szrjocteon2, 397*a9fa9459Szrjocteon3, 398*a9fa9459Szrjxlr, 399*a9fa9459Szrjxlp 400*a9fa9459Szrj@end quotation 401*a9fa9459Szrj 402*a9fa9459SzrjFor compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are 403*a9fa9459Szrjaccepted as synonyms for @samp{@var{n}f1_1}. These values are 404*a9fa9459Szrjdeprecated. 405*a9fa9459Szrj 406*a9fa9459Szrj@item -mtune=@var{cpu} 407*a9fa9459SzrjSchedule and tune for a particular MIPS CPU. Valid @var{cpu} values are 408*a9fa9459Szrjidentical to @samp{-march=@var{cpu}}. 409*a9fa9459Szrj 410*a9fa9459Szrj@item -mabi=@var{abi} 411*a9fa9459SzrjRecord which ABI the source code uses. The recognized arguments 412*a9fa9459Szrjare: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. 413*a9fa9459Szrj 414*a9fa9459Szrj@item -msym32 415*a9fa9459Szrj@itemx -mno-sym32 416*a9fa9459Szrj@cindex -msym32 417*a9fa9459Szrj@cindex -mno-sym32 418*a9fa9459SzrjEquivalent to adding @code{.set sym32} or @code{.set nosym32} to 419*a9fa9459Szrjthe beginning of the assembler input. @xref{MIPS Symbol Sizes}. 420*a9fa9459Szrj 421*a9fa9459Szrj@cindex @code{-nocpp} ignored (MIPS) 422*a9fa9459Szrj@item -nocpp 423*a9fa9459SzrjThis option is ignored. It is accepted for command-line compatibility with 424*a9fa9459Szrjother assemblers, which use it to turn off C style preprocessing. With 425*a9fa9459Szrj@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the 426*a9fa9459Szrj@sc{gnu} assembler itself never runs the C preprocessor. 427*a9fa9459Szrj 428*a9fa9459Szrj@item -msoft-float 429*a9fa9459Szrj@itemx -mhard-float 430*a9fa9459SzrjDisable or enable floating-point instructions. Note that by default 431*a9fa9459Szrjfloating-point instructions are always allowed even with CPU targets 432*a9fa9459Szrjthat don't have support for these instructions. 433*a9fa9459Szrj 434*a9fa9459Szrj@item -msingle-float 435*a9fa9459Szrj@itemx -mdouble-float 436*a9fa9459SzrjDisable or enable double-precision floating-point operations. Note 437*a9fa9459Szrjthat by default double-precision floating-point operations are always 438*a9fa9459Szrjallowed even with CPU targets that don't have support for these 439*a9fa9459Szrjoperations. 440*a9fa9459Szrj 441*a9fa9459Szrj@item --construct-floats 442*a9fa9459Szrj@itemx --no-construct-floats 443*a9fa9459SzrjThe @code{--no-construct-floats} option disables the construction of 444*a9fa9459Szrjdouble width floating point constants by loading the two halves of the 445*a9fa9459Szrjvalue into the two single width floating point registers that make up 446*a9fa9459Szrjthe double width register. This feature is useful if the processor 447*a9fa9459Szrjsupport the FR bit in its status register, and this bit is known (by 448*a9fa9459Szrjthe programmer) to be set. This bit prevents the aliasing of the double 449*a9fa9459Szrjwidth register by the single width registers. 450*a9fa9459Szrj 451*a9fa9459SzrjBy default @code{--construct-floats} is selected, allowing construction 452*a9fa9459Szrjof these floating point constants. 453*a9fa9459Szrj 454*a9fa9459Szrj@item --relax-branch 455*a9fa9459Szrj@itemx --no-relax-branch 456*a9fa9459SzrjThe @samp{--relax-branch} option enables the relaxation of out-of-range 457*a9fa9459Szrjbranches. Any branches whose target cannot be reached directly are 458*a9fa9459Szrjconverted to a small instruction sequence including an inverse-condition 459*a9fa9459Szrjbranch to the physically next instruction, and a jump to the original 460*a9fa9459Szrjtarget is inserted between the two instructions. In PIC code the jump 461*a9fa9459Szrjwill involve further instructions for address calculation. 462*a9fa9459Szrj 463*a9fa9459SzrjThe @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T}, 464*a9fa9459Szrj@code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from 465*a9fa9459Szrjrelaxation, because they have no complementing counterparts. They could 466*a9fa9459Szrjbe relaxed with the use of a longer sequence involving another branch, 467*a9fa9459Szrjhowever this has not been implemented and if their target turns out of 468*a9fa9459Szrjreach, they produce an error even if branch relaxation is enabled. 469*a9fa9459Szrj 470*a9fa9459SzrjAlso no MIPS16 branches are ever relaxed. 471*a9fa9459Szrj 472*a9fa9459SzrjBy default @samp{--no-relax-branch} is selected, causing any out-of-range 473*a9fa9459Szrjbranches to produce an error. 474*a9fa9459Szrj 475*a9fa9459Szrj@cindex @option{-mnan=} command line option, MIPS 476*a9fa9459Szrj@item -mnan=@var{encoding} 477*a9fa9459SzrjThis option indicates whether the source code uses the IEEE 2008 478*a9fa9459SzrjNaN encoding (@option{-mnan=2008}) or the original MIPS encoding 479*a9fa9459Szrj(@option{-mnan=legacy}). It is equivalent to adding a @code{.nan} 480*a9fa9459Szrjdirective to the beginning of the source file. @xref{MIPS NaN Encodings}. 481*a9fa9459Szrj 482*a9fa9459Szrj@option{-mnan=legacy} is the default if no @option{-mnan} option or 483*a9fa9459Szrj@code{.nan} directive is used. 484*a9fa9459Szrj 485*a9fa9459Szrj@item --trap 486*a9fa9459Szrj@itemx --no-break 487*a9fa9459Szrj@c FIXME! (1) reflect these options (next item too) in option summaries; 488*a9fa9459Szrj@c (2) stop teasing, say _which_ instructions expanded _how_. 489*a9fa9459Szrj@code{@value{AS}} automatically macro expands certain division and 490*a9fa9459Szrjmultiplication instructions to check for overflow and division by zero. This 491*a9fa9459Szrjoption causes @code{@value{AS}} to generate code to take a trap exception 492*a9fa9459Szrjrather than a break exception when an error is detected. The trap instructions 493*a9fa9459Szrjare only supported at Instruction Set Architecture level 2 and higher. 494*a9fa9459Szrj 495*a9fa9459Szrj@item --break 496*a9fa9459Szrj@itemx --no-trap 497*a9fa9459SzrjGenerate code to take a break exception rather than a trap exception when an 498*a9fa9459Szrjerror is detected. This is the default. 499*a9fa9459Szrj 500*a9fa9459Szrj@item -mpdr 501*a9fa9459Szrj@itemx -mno-pdr 502*a9fa9459SzrjControl generation of @code{.pdr} sections. Off by default on IRIX, on 503*a9fa9459Szrjelsewhere. 504*a9fa9459Szrj 505*a9fa9459Szrj@item -mshared 506*a9fa9459Szrj@itemx -mno-shared 507*a9fa9459SzrjWhen generating code using the Unix calling conventions (selected by 508*a9fa9459Szrj@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code 509*a9fa9459Szrjwhich can go into a shared library. The @samp{-mno-shared} option 510*a9fa9459Szrjtells gas to generate code which uses the calling convention, but can 511*a9fa9459Szrjnot go into a shared library. The resulting code is slightly more 512*a9fa9459Szrjefficient. This option only affects the handling of the 513*a9fa9459Szrj@samp{.cpload} and @samp{.cpsetup} pseudo-ops. 514*a9fa9459Szrj@end table 515*a9fa9459Szrj 516*a9fa9459Szrj@node MIPS Macros 517*a9fa9459Szrj@section High-level assembly macros 518*a9fa9459Szrj 519*a9fa9459SzrjMIPS assemblers have traditionally provided a wider range of 520*a9fa9459Szrjinstructions than the MIPS architecture itself. These extra 521*a9fa9459Szrjinstructions are usually referred to as ``macro'' instructions 522*a9fa9459Szrj@footnote{The term ``macro'' is somewhat overloaded here, since 523*a9fa9459Szrjthese macros have no relation to those defined by @code{.macro}, 524*a9fa9459Szrj@pxref{Macro,, @code{.macro}}.}. 525*a9fa9459Szrj 526*a9fa9459SzrjSome MIPS macro instructions extend an underlying architectural instruction 527*a9fa9459Szrjwhile others are entirely new. An example of the former type is @code{and}, 528*a9fa9459Szrjwhich allows the third operand to be either a register or an arbitrary 529*a9fa9459Szrjimmediate value. Examples of the latter type include @code{bgt}, which 530*a9fa9459Szrjbranches to the third operand when the first operand is greater than 531*a9fa9459Szrjthe second operand, and @code{ulh}, which implements an unaligned 532*a9fa9459Szrj2-byte load. 533*a9fa9459Szrj 534*a9fa9459SzrjOne of the most common extensions provided by macros is to expand 535*a9fa9459Szrjmemory offsets to the full address range (32 or 64 bits) and to allow 536*a9fa9459Szrjsymbolic offsets such as @samp{my_data + 4} to be used in place of 537*a9fa9459Szrjinteger constants. For example, the architectural instruction 538*a9fa9459Szrj@code{lbu} allows only a signed 16-bit offset, whereas the macro 539*a9fa9459Szrj@code{lbu} allows code such as @samp{lbu $4,array+32769($5)}. 540*a9fa9459SzrjThe implementation of these symbolic offsets depends on several factors, 541*a9fa9459Szrjsuch as whether the assembler is generating SVR4-style PIC (selected by 542*a9fa9459Szrj@option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols 543*a9fa9459Szrj(@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}), 544*a9fa9459Szrjand the small data limit (@pxref{MIPS Small Data,, Controlling the use 545*a9fa9459Szrjof small data accesses}). 546*a9fa9459Szrj 547*a9fa9459Szrj@kindex @code{.set macro} 548*a9fa9459Szrj@kindex @code{.set nomacro} 549*a9fa9459SzrjSometimes it is undesirable to have one assembly instruction expand 550*a9fa9459Szrjto several machine instructions. The directive @code{.set nomacro} 551*a9fa9459Szrjtells the assembler to warn when this happens. @code{.set macro} 552*a9fa9459Szrjrestores the default behavior. 553*a9fa9459Szrj 554*a9fa9459Szrj@cindex @code{at} register, MIPS 555*a9fa9459Szrj@kindex @code{.set at=@var{reg}} 556*a9fa9459SzrjSome macro instructions need a temporary register to store intermediate 557*a9fa9459Szrjresults. This register is usually @code{$1}, also known as @code{$at}, 558*a9fa9459Szrjbut it can be changed to any core register @var{reg} using 559*a9fa9459Szrj@code{.set at=@var{reg}}. Note that @code{$at} always refers 560*a9fa9459Szrjto @code{$1} regardless of which register is being used as the 561*a9fa9459Szrjtemporary register. 562*a9fa9459Szrj 563*a9fa9459Szrj@kindex @code{.set at} 564*a9fa9459Szrj@kindex @code{.set noat} 565*a9fa9459SzrjImplicit uses of the temporary register in macros could interfere with 566*a9fa9459Szrjexplicit uses in the assembly code. The assembler therefore warns 567*a9fa9459Szrjwhenever it sees an explicit use of the temporary register. The directive 568*a9fa9459Szrj@code{.set noat} silences this warning while @code{.set at} restores 569*a9fa9459Szrjthe default behavior. It is safe to use @code{.set noat} while 570*a9fa9459Szrj@code{.set nomacro} is in effect since single-instruction macros 571*a9fa9459Szrjnever need a temporary register. 572*a9fa9459Szrj 573*a9fa9459SzrjNote that while the @sc{gnu} assembler provides these macros for compatibility, 574*a9fa9459Szrjit does not make any attempt to optimize them with the surrounding code. 575*a9fa9459Szrj 576*a9fa9459Szrj@node MIPS Symbol Sizes 577*a9fa9459Szrj@section Directives to override the size of symbols 578*a9fa9459Szrj 579*a9fa9459Szrj@kindex @code{.set sym32} 580*a9fa9459Szrj@kindex @code{.set nosym32} 581*a9fa9459SzrjThe n64 ABI allows symbols to have any 64-bit value. Although this 582*a9fa9459Szrjprovides a great deal of flexibility, it means that some macros have 583*a9fa9459Szrjmuch longer expansions than their 32-bit counterparts. For example, 584*a9fa9459Szrjthe non-PIC expansion of @samp{dla $4,sym} is usually: 585*a9fa9459Szrj 586*a9fa9459Szrj@smallexample 587*a9fa9459Szrjlui $4,%highest(sym) 588*a9fa9459Szrjlui $1,%hi(sym) 589*a9fa9459Szrjdaddiu $4,$4,%higher(sym) 590*a9fa9459Szrjdaddiu $1,$1,%lo(sym) 591*a9fa9459Szrjdsll32 $4,$4,0 592*a9fa9459Szrjdaddu $4,$4,$1 593*a9fa9459Szrj@end smallexample 594*a9fa9459Szrj 595*a9fa9459Szrjwhereas the 32-bit expansion is simply: 596*a9fa9459Szrj 597*a9fa9459Szrj@smallexample 598*a9fa9459Szrjlui $4,%hi(sym) 599*a9fa9459Szrjdaddiu $4,$4,%lo(sym) 600*a9fa9459Szrj@end smallexample 601*a9fa9459Szrj 602*a9fa9459Szrjn64 code is sometimes constructed in such a way that all symbolic 603*a9fa9459Szrjconstants are known to have 32-bit values, and in such cases, it's 604*a9fa9459Szrjpreferable to use the 32-bit expansion instead of the 64-bit 605*a9fa9459Szrjexpansion. 606*a9fa9459Szrj 607*a9fa9459SzrjYou can use the @code{.set sym32} directive to tell the assembler 608*a9fa9459Szrjthat, from this point on, all expressions of the form 609*a9fa9459Szrj@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} 610*a9fa9459Szrjhave 32-bit values. For example: 611*a9fa9459Szrj 612*a9fa9459Szrj@smallexample 613*a9fa9459Szrj.set sym32 614*a9fa9459Szrjdla $4,sym 615*a9fa9459Szrjlw $4,sym+16 616*a9fa9459Szrjsw $4,sym+0x8000($4) 617*a9fa9459Szrj@end smallexample 618*a9fa9459Szrj 619*a9fa9459Szrjwill cause the assembler to treat @samp{sym}, @code{sym+16} and 620*a9fa9459Szrj@code{sym+0x8000} as 32-bit values. The handling of non-symbolic 621*a9fa9459Szrjaddresses is not affected. 622*a9fa9459Szrj 623*a9fa9459SzrjThe directive @code{.set nosym32} ends a @code{.set sym32} block and 624*a9fa9459Szrjreverts to the normal behavior. It is also possible to change the 625*a9fa9459Szrjsymbol size using the command-line options @option{-msym32} and 626*a9fa9459Szrj@option{-mno-sym32}. 627*a9fa9459Szrj 628*a9fa9459SzrjThese options and directives are always accepted, but at present, 629*a9fa9459Szrjthey have no effect for anything other than n64. 630*a9fa9459Szrj 631*a9fa9459Szrj@node MIPS Small Data 632*a9fa9459Szrj@section Controlling the use of small data accesses 633*a9fa9459Szrj 634*a9fa9459Szrj@c This section deliberately glosses over the possibility of using -G 635*a9fa9459Szrj@c in SVR4-style PIC, as could be done on IRIX. We don't support that. 636*a9fa9459Szrj@cindex small data, MIPS 637*a9fa9459Szrj@cindex @code{gp} register, MIPS 638*a9fa9459SzrjIt often takes several instructions to load the address of a symbol. 639*a9fa9459SzrjFor example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion 640*a9fa9459Szrjof @samp{dla $4,addr} is usually: 641*a9fa9459Szrj 642*a9fa9459Szrj@smallexample 643*a9fa9459Szrjlui $4,%hi(addr) 644*a9fa9459Szrjdaddiu $4,$4,%lo(addr) 645*a9fa9459Szrj@end smallexample 646*a9fa9459Szrj 647*a9fa9459SzrjThe sequence is much longer when @samp{addr} is a 64-bit symbol. 648*a9fa9459Szrj@xref{MIPS Symbol Sizes,, Directives to override the size of symbols}. 649*a9fa9459Szrj 650*a9fa9459SzrjIn order to cut down on this overhead, most embedded MIPS systems 651*a9fa9459Szrjset aside a 64-kilobyte ``small data'' area and guarantee that all 652*a9fa9459Szrjdata of size @var{n} and smaller will be placed in that area. 653*a9fa9459SzrjThe limit @var{n} is passed to both the assembler and the linker 654*a9fa9459Szrjusing the command-line option @option{-G @var{n}}, @pxref{MIPS Options,, 655*a9fa9459SzrjAssembler options}. Note that the same value of @var{n} must be used 656*a9fa9459Szrjwhen linking and when assembling all input files to the link; any 657*a9fa9459Szrjinconsistency could cause a relocation overflow error. 658*a9fa9459Szrj 659*a9fa9459SzrjThe size of an object in the @code{.bss} section is set by the 660*a9fa9459Szrj@code{.comm} or @code{.lcomm} directive that defines it. The size of 661*a9fa9459Szrjan external object may be set with the @code{.extern} directive. For 662*a9fa9459Szrjexample, @samp{.extern sym,4} declares that the object at @code{sym} 663*a9fa9459Szrjis 4 bytes in length, while leaving @code{sym} otherwise undefined. 664*a9fa9459Szrj 665*a9fa9459SzrjWhen no @option{-G} option is given, the default limit is 8 bytes. 666*a9fa9459SzrjThe option @option{-G 0} prevents any data from being automatically 667*a9fa9459Szrjclassified as small. 668*a9fa9459Szrj 669*a9fa9459SzrjIt is also possible to mark specific objects as small by putting them 670*a9fa9459Szrjin the special sections @code{.sdata} and @code{.sbss}, which are 671*a9fa9459Szrj``small'' counterparts of @code{.data} and @code{.bss} respectively. 672*a9fa9459SzrjThe toolchain will treat such data as small regardless of the 673*a9fa9459Szrj@option{-G} setting. 674*a9fa9459Szrj 675*a9fa9459SzrjOn startup, systems that support a small data area are expected to 676*a9fa9459Szrjinitialize register @code{$28}, also known as @code{$gp}, in such a 677*a9fa9459Szrjway that small data can be accessed using a 16-bit offset from that 678*a9fa9459Szrjregister. For example, when @samp{addr} is small data, 679*a9fa9459Szrjthe @samp{dla $4,addr} instruction above is equivalent to: 680*a9fa9459Szrj 681*a9fa9459Szrj@smallexample 682*a9fa9459Szrjdaddiu $4,$28,%gp_rel(addr) 683*a9fa9459Szrj@end smallexample 684*a9fa9459Szrj 685*a9fa9459SzrjSmall data is not supported for SVR4-style PIC. 686*a9fa9459Szrj 687*a9fa9459Szrj@node MIPS ISA 688*a9fa9459Szrj@section Directives to override the ISA level 689*a9fa9459Szrj 690*a9fa9459Szrj@cindex MIPS ISA override 691*a9fa9459Szrj@kindex @code{.set mips@var{n}} 692*a9fa9459Szrj@sc{gnu} @code{@value{AS}} supports an additional directive to change 693*a9fa9459Szrjthe MIPS Instruction Set Architecture level on the fly: @code{.set 694*a9fa9459Szrjmips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3, 695*a9fa9459Szrj32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. 696*a9fa9459SzrjThe values other than 0 make the assembler accept instructions 697*a9fa9459Szrjfor the corresponding ISA level, from that point on in the 698*a9fa9459Szrjassembly. @code{.set mips@var{n}} affects not only which instructions 699*a9fa9459Szrjare permitted, but also how certain macros are expanded. @code{.set 700*a9fa9459Szrjmips0} restores the ISA level to its original level: either the 701*a9fa9459Szrjlevel you selected with command line options, or the default for your 702*a9fa9459Szrjconfiguration. You can use this feature to permit specific MIPS III 703*a9fa9459Szrjinstructions while assembling in 32 bit mode. Use this directive with 704*a9fa9459Szrjcare! 705*a9fa9459Szrj 706*a9fa9459Szrj@cindex MIPS CPU override 707*a9fa9459Szrj@kindex @code{.set arch=@var{cpu}} 708*a9fa9459SzrjThe @code{.set arch=@var{cpu}} directive provides even finer control. 709*a9fa9459SzrjIt changes the effective CPU target and allows the assembler to use 710*a9fa9459Szrjinstructions specific to a particular CPU. All CPUs supported by the 711*a9fa9459Szrj@samp{-march} command line option are also selectable by this directive. 712*a9fa9459SzrjThe original value is restored by @code{.set arch=default}. 713*a9fa9459Szrj 714*a9fa9459SzrjThe directive @code{.set mips16} puts the assembler into MIPS 16 mode, 715*a9fa9459Szrjin which it will assemble instructions for the MIPS 16 processor. Use 716*a9fa9459Szrj@code{.set nomips16} to return to normal 32 bit mode. 717*a9fa9459Szrj 718*a9fa9459SzrjTraditional MIPS assemblers do not support this directive. 719*a9fa9459Szrj 720*a9fa9459SzrjThe directive @code{.set micromips} puts the assembler into microMIPS mode, 721*a9fa9459Szrjin which it will assemble instructions for the microMIPS processor. Use 722*a9fa9459Szrj@code{.set nomicromips} to return to normal 32 bit mode. 723*a9fa9459Szrj 724*a9fa9459SzrjTraditional MIPS assemblers do not support this directive. 725*a9fa9459Szrj 726*a9fa9459Szrj@node MIPS assembly options 727*a9fa9459Szrj@section Directives to control code generation 728*a9fa9459Szrj 729*a9fa9459Szrj@cindex MIPS directives to override command line options 730*a9fa9459Szrj@kindex @code{.module} 731*a9fa9459SzrjThe @code{.module} directive allows command line options to be set directly 732*a9fa9459Szrjfrom assembly. The format of the directive matches the @code{.set} 733*a9fa9459Szrjdirective but only those options which are relevant to a whole module are 734*a9fa9459Szrjsupported. The effect of a @code{.module} directive is the same as the 735*a9fa9459Szrjcorresponding command line option. Where @code{.set} directives support 736*a9fa9459Szrjreturning to a default then the @code{.module} directives do not as they 737*a9fa9459Szrjdefine the defaults. 738*a9fa9459Szrj 739*a9fa9459SzrjThese module-level directives must appear first in assembly. 740*a9fa9459Szrj 741*a9fa9459SzrjTraditional MIPS assemblers do not support this directive. 742*a9fa9459Szrj 743*a9fa9459Szrj@cindex MIPS 32-bit microMIPS instruction generation override 744*a9fa9459Szrj@kindex @code{.set insn32} 745*a9fa9459Szrj@kindex @code{.set noinsn32} 746*a9fa9459SzrjThe directive @code{.set insn32} makes the assembler only use 32-bit 747*a9fa9459Szrjinstruction encodings when generating code for the microMIPS processor. 748*a9fa9459SzrjThis directive inhibits the use of any 16-bit instructions from that 749*a9fa9459Szrjpoint on in the assembly. The @code{.set noinsn32} directive allows 750*a9fa9459Szrj16-bit instructions to be accepted. 751*a9fa9459Szrj 752*a9fa9459SzrjTraditional MIPS assemblers do not support this directive. 753*a9fa9459Szrj 754*a9fa9459Szrj@node MIPS autoextend 755*a9fa9459Szrj@section Directives for extending MIPS 16 bit instructions 756*a9fa9459Szrj 757*a9fa9459Szrj@kindex @code{.set autoextend} 758*a9fa9459Szrj@kindex @code{.set noautoextend} 759*a9fa9459SzrjBy default, MIPS 16 instructions are automatically extended to 32 bits 760*a9fa9459Szrjwhen necessary. The directive @code{.set noautoextend} will turn this 761*a9fa9459Szrjoff. When @code{.set noautoextend} is in effect, any 32 bit instruction 762*a9fa9459Szrjmust be explicitly extended with the @code{.e} modifier (e.g., 763*a9fa9459Szrj@code{li.e $4,1000}). The directive @code{.set autoextend} may be used 764*a9fa9459Szrjto once again automatically extend instructions when necessary. 765*a9fa9459Szrj 766*a9fa9459SzrjThis directive is only meaningful when in MIPS 16 mode. Traditional 767*a9fa9459SzrjMIPS assemblers do not support this directive. 768*a9fa9459Szrj 769*a9fa9459Szrj@node MIPS insn 770*a9fa9459Szrj@section Directive to mark data as an instruction 771*a9fa9459Szrj 772*a9fa9459Szrj@kindex @code{.insn} 773*a9fa9459SzrjThe @code{.insn} directive tells @code{@value{AS}} that the following 774*a9fa9459Szrjdata is actually instructions. This makes a difference in MIPS 16 and 775*a9fa9459SzrjmicroMIPS modes: when loading the address of a label which precedes 776*a9fa9459Szrjinstructions, @code{@value{AS}} automatically adds 1 to the value, so 777*a9fa9459Szrjthat jumping to the loaded address will do the right thing. 778*a9fa9459Szrj 779*a9fa9459Szrj@kindex @code{.global} 780*a9fa9459SzrjThe @code{.global} and @code{.globl} directives supported by 781*a9fa9459Szrj@code{@value{AS}} will by default mark the symbol as pointing to a 782*a9fa9459Szrjregion of data not code. This means that, for example, any 783*a9fa9459Szrjinstructions following such a symbol will not be disassembled by 784*a9fa9459Szrj@code{objdump} as it will regard them as data. To change this 785*a9fa9459Szrjbehavior an optional section name can be placed after the symbol name 786*a9fa9459Szrjin the @code{.global} directive. If this section exists and is known 787*a9fa9459Szrjto be a code section, then the symbol will be marked as pointing at 788*a9fa9459Szrjcode not data. Ie the syntax for the directive is: 789*a9fa9459Szrj 790*a9fa9459Szrj @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...}, 791*a9fa9459Szrj 792*a9fa9459SzrjHere is a short example: 793*a9fa9459Szrj 794*a9fa9459Szrj@example 795*a9fa9459Szrj .global foo .text, bar, baz .data 796*a9fa9459Szrjfoo: 797*a9fa9459Szrj nop 798*a9fa9459Szrjbar: 799*a9fa9459Szrj .word 0x0 800*a9fa9459Szrjbaz: 801*a9fa9459Szrj .word 0x1 802*a9fa9459Szrj 803*a9fa9459Szrj@end example 804*a9fa9459Szrj 805*a9fa9459Szrj@node MIPS FP ABIs 806*a9fa9459Szrj@section Directives to control the FP ABI 807*a9fa9459Szrj@menu 808*a9fa9459Szrj* MIPS FP ABI History:: History of FP ABIs 809*a9fa9459Szrj* MIPS FP ABI Variants:: Supported FP ABIs 810*a9fa9459Szrj* MIPS FP ABI Selection:: Automatic selection of FP ABI 811*a9fa9459Szrj* MIPS FP ABI Compatibility:: Linking different FP ABI variants 812*a9fa9459Szrj@end menu 813*a9fa9459Szrj 814*a9fa9459Szrj@node MIPS FP ABI History 815*a9fa9459Szrj@subsection History of FP ABIs 816*a9fa9459Szrj@cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS 817*a9fa9459Szrj@cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS 818*a9fa9459SzrjThe MIPS ABIs support a variety of different floating-point extensions 819*a9fa9459Szrjwhere calling-convention and register sizes vary for floating-point data. 820*a9fa9459SzrjThe extensions exist to support a wide variety of optional architecture 821*a9fa9459Szrjfeatures. The resulting ABI variants are generally incompatible with each 822*a9fa9459Szrjother and must be tracked carefully. 823*a9fa9459Szrj 824*a9fa9459SzrjTraditionally the use of an explicit @code{.gnu_attribute 4, @var{n}} 825*a9fa9459Szrjdirective is used to indicate which ABI is in use by a specific module. 826*a9fa9459SzrjIt was then left to the user to ensure that command line options and the 827*a9fa9459Szrjselected ABI were compatible with some potential for inconsistencies. 828*a9fa9459Szrj 829*a9fa9459Szrj@node MIPS FP ABI Variants 830*a9fa9459Szrj@subsection Supported FP ABIs 831*a9fa9459SzrjThe supported floating-point ABI variants are: 832*a9fa9459Szrj 833*a9fa9459Szrj@table @code 834*a9fa9459Szrj@item 0 - No floating-point 835*a9fa9459SzrjThis variant is used to indicate that floating-point is not used within 836*a9fa9459Szrjthe module at all and therefore has no impact on the ABI. This is the 837*a9fa9459Szrjdefault. 838*a9fa9459Szrj 839*a9fa9459Szrj@item 1 - Double-precision 840*a9fa9459SzrjThis variant indicates that double-precision support is used. For 64-bit 841*a9fa9459SzrjABIs this means that 64-bit wide floating-point registers are required. 842*a9fa9459SzrjFor 32-bit ABIs this means that 32-bit wide floating-point registers are 843*a9fa9459Szrjrequired and double-precision operations use pairs of registers. 844*a9fa9459Szrj 845*a9fa9459Szrj@item 2 - Single-precision 846*a9fa9459SzrjThis variant indicates that single-precision support is used. Double 847*a9fa9459Szrjprecision operations will be supported via soft-float routines. 848*a9fa9459Szrj 849*a9fa9459Szrj@item 3 - Soft-float 850*a9fa9459SzrjThis variant indicates that although floating-point support is used all 851*a9fa9459Szrjoperations are emulated in software. This means the ABI is modified to 852*a9fa9459Szrjpass all floating-point data in general-purpose registers. 853*a9fa9459Szrj 854*a9fa9459Szrj@item 4 - Deprecated 855*a9fa9459SzrjThis variant existed as an initial attempt at supporting 64-bit wide 856*a9fa9459Szrjfloating-point registers for O32 ABI on a MIPS32r2 CPU. This has been 857*a9fa9459Szrjsuperseded by 5, 6 and 7. 858*a9fa9459Szrj 859*a9fa9459Szrj@item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU 860*a9fa9459SzrjThis variant is used by 32-bit ABIs to indicate that the floating-point 861*a9fa9459Szrjcode in the module has been designed to operate correctly with either 862*a9fa9459Szrj32-bit wide or 64-bit wide floating-point registers. Double-precision 863*a9fa9459Szrjsupport is used. Only O32 currently supports this variant and requires 864*a9fa9459Szrja minimum architecture of MIPS II. 865*a9fa9459Szrj 866*a9fa9459Szrj@item 6 - Double-precision 32-bit FPU, 64-bit FPU 867*a9fa9459SzrjThis variant is used by 32-bit ABIs to indicate that the floating-point 868*a9fa9459Szrjcode in the module requires 64-bit wide floating-point registers. 869*a9fa9459SzrjDouble-precision support is used. Only O32 currently supports this 870*a9fa9459Szrjvariant and requires a minimum architecture of MIPS32r2. 871*a9fa9459Szrj 872*a9fa9459Szrj@item 7 - Double-precision compat 32-bit FPU, 64-bit FPU 873*a9fa9459SzrjThis variant is used by 32-bit ABIs to indicate that the floating-point 874*a9fa9459Szrjcode in the module requires 64-bit wide floating-point registers. 875*a9fa9459SzrjDouble-precision support is used. This differs from the previous ABI 876*a9fa9459Szrjas it restricts use of odd-numbered single-precision registers. Only 877*a9fa9459SzrjO32 currently supports this variant and requires a minimum architecture 878*a9fa9459Szrjof MIPS32r2. 879*a9fa9459Szrj@end table 880*a9fa9459Szrj 881*a9fa9459Szrj@node MIPS FP ABI Selection 882*a9fa9459Szrj@subsection Automatic selection of FP ABI 883*a9fa9459Szrj@cindex @code{.module fp=@var{nn}} directive, MIPS 884*a9fa9459SzrjIn order to simplify and add safety to the process of selecting the 885*a9fa9459Szrjcorrect floating-point ABI, the assembler will automatically infer the 886*a9fa9459Szrjcorrect @code{.gnu_attribute 4, @var{n}} directive based on command line 887*a9fa9459Szrjoptions and @code{.module} overrides. Where an explicit 888*a9fa9459Szrj@code{.gnu_attribute 4, @var{n}} directive has been seen then a warning 889*a9fa9459Szrjwill be raised if it does not match an inferred setting. 890*a9fa9459Szrj 891*a9fa9459SzrjThe floating-point ABI is inferred as follows. If @samp{-msoft-float} 892*a9fa9459Szrjhas been used the module will be marked as soft-float. If 893*a9fa9459Szrj@samp{-msingle-float} has been used then the module will be marked as 894*a9fa9459Szrjsingle-precision. The remaining ABIs are then selected based 895*a9fa9459Szrjon the FP register width. Double-precision is selected if the width 896*a9fa9459Szrjof GP and FP registers match and the special double-precision variants 897*a9fa9459Szrjfor 32-bit ABIs are then selected depending on @samp{-mfpxx}, 898*a9fa9459Szrj@samp{-mfp64} and @samp{-mno-odd-spreg}. 899*a9fa9459Szrj 900*a9fa9459Szrj@node MIPS FP ABI Compatibility 901*a9fa9459Szrj@subsection Linking different FP ABI variants 902*a9fa9459SzrjModules using the default FP ABI (no floating-point) can be linked with 903*a9fa9459Szrjany other (singular) FP ABI variant. 904*a9fa9459Szrj 905*a9fa9459SzrjSpecial compatibility support exists for O32 with the four 906*a9fa9459Szrjdouble-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically 907*a9fa9459Szrjdesigned to be compatible with the standard double-precision ABI and the 908*a9fa9459Szrj@samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be 909*a9fa9459Szrjbuilt as @samp{-mfpxx} to ensure the maximum compatibility with other 910*a9fa9459Szrjmodules produced for more specific needs. The only FP ABIs which cannot 911*a9fa9459Szrjbe linked together are the standard double-precision ABI and the full 912*a9fa9459Szrj@samp{-mfp64} ABI with @samp{-modd-spreg}. 913*a9fa9459Szrj 914*a9fa9459Szrj@node MIPS NaN Encodings 915*a9fa9459Szrj@section Directives to record which NaN encoding is being used 916*a9fa9459Szrj 917*a9fa9459Szrj@cindex MIPS IEEE 754 NaN data encoding selection 918*a9fa9459Szrj@cindex @code{.nan} directive, MIPS 919*a9fa9459SzrjThe IEEE 754 floating-point standard defines two types of not-a-number 920*a9fa9459Szrj(NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version 921*a9fa9459Szrjof the standard did not specify how these two types should be 922*a9fa9459Szrjdistinguished. Most implementations followed the i387 model, in which 923*a9fa9459Szrjthe first bit of the significand is set for quiet NaNs and clear for 924*a9fa9459Szrjsignalling NaNs. However, the original MIPS implementation assigned the 925*a9fa9459Szrjopposite meaning to the bit, so that it was set for signalling NaNs and 926*a9fa9459Szrjclear for quiet NaNs. 927*a9fa9459Szrj 928*a9fa9459SzrjThe 2008 revision of the standard formally suggested the i387 choice 929*a9fa9459Szrjand as from Sep 2012 the current release of the MIPS architecture 930*a9fa9459Szrjtherefore optionally supports that form. Code that uses one NaN encoding 931*a9fa9459Szrjwould usually be incompatible with code that uses the other NaN encoding, 932*a9fa9459Szrjso MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which 933*a9fa9459Szrjencoding is being used. 934*a9fa9459Szrj 935*a9fa9459SzrjAssembly files can use the @code{.nan} directive to select between the 936*a9fa9459Szrjtwo encodings. @samp{.nan 2008} says that the assembly file uses the 937*a9fa9459SzrjIEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses 938*a9fa9459Szrjthe original MIPS encoding. If several @code{.nan} directives are given, 939*a9fa9459Szrjthe final setting is the one that is used. 940*a9fa9459Szrj 941*a9fa9459SzrjThe command-line options @option{-mnan=legacy} and @option{-mnan=2008} 942*a9fa9459Szrjcan be used instead of @samp{.nan legacy} and @samp{.nan 2008} 943*a9fa9459Szrjrespectively. However, any @code{.nan} directive overrides the 944*a9fa9459Szrjcommand-line setting. 945*a9fa9459Szrj 946*a9fa9459Szrj@samp{.nan legacy} is the default if no @code{.nan} directive or 947*a9fa9459Szrj@option{-mnan} option is given. 948*a9fa9459Szrj 949*a9fa9459SzrjNote that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and 950*a9fa9459Szrjtherefore these directives do not affect code generation. They simply 951*a9fa9459Szrjcontrol the setting of the @code{EF_MIPS_NAN2008} flag. 952*a9fa9459Szrj 953*a9fa9459SzrjTraditional MIPS assemblers do not support these directives. 954*a9fa9459Szrj 955*a9fa9459Szrj@node MIPS Option Stack 956*a9fa9459Szrj@section Directives to save and restore options 957*a9fa9459Szrj 958*a9fa9459Szrj@cindex MIPS option stack 959*a9fa9459Szrj@kindex @code{.set push} 960*a9fa9459Szrj@kindex @code{.set pop} 961*a9fa9459SzrjThe directives @code{.set push} and @code{.set pop} may be used to save 962*a9fa9459Szrjand restore the current settings for all the options which are 963*a9fa9459Szrjcontrolled by @code{.set}. The @code{.set push} directive saves the 964*a9fa9459Szrjcurrent settings on a stack. The @code{.set pop} directive pops the 965*a9fa9459Szrjstack and restores the settings. 966*a9fa9459Szrj 967*a9fa9459SzrjThese directives can be useful inside an macro which must change an 968*a9fa9459Szrjoption such as the ISA level or instruction reordering but does not want 969*a9fa9459Szrjto change the state of the code which invoked the macro. 970*a9fa9459Szrj 971*a9fa9459SzrjTraditional MIPS assemblers do not support these directives. 972*a9fa9459Szrj 973*a9fa9459Szrj@node MIPS ASE Instruction Generation Overrides 974*a9fa9459Szrj@section Directives to control generation of MIPS ASE instructions 975*a9fa9459Szrj 976*a9fa9459Szrj@cindex MIPS MIPS-3D instruction generation override 977*a9fa9459Szrj@kindex @code{.set mips3d} 978*a9fa9459Szrj@kindex @code{.set nomips3d} 979*a9fa9459SzrjThe directive @code{.set mips3d} makes the assembler accept instructions 980*a9fa9459Szrjfrom the MIPS-3D Application Specific Extension from that point on 981*a9fa9459Szrjin the assembly. The @code{.set nomips3d} directive prevents MIPS-3D 982*a9fa9459Szrjinstructions from being accepted. 983*a9fa9459Szrj 984*a9fa9459Szrj@cindex SmartMIPS instruction generation override 985*a9fa9459Szrj@kindex @code{.set smartmips} 986*a9fa9459Szrj@kindex @code{.set nosmartmips} 987*a9fa9459SzrjThe directive @code{.set smartmips} makes the assembler accept 988*a9fa9459Szrjinstructions from the SmartMIPS Application Specific Extension to the 989*a9fa9459SzrjMIPS32 ISA from that point on in the assembly. The 990*a9fa9459Szrj@code{.set nosmartmips} directive prevents SmartMIPS instructions from 991*a9fa9459Szrjbeing accepted. 992*a9fa9459Szrj 993*a9fa9459Szrj@cindex MIPS MDMX instruction generation override 994*a9fa9459Szrj@kindex @code{.set mdmx} 995*a9fa9459Szrj@kindex @code{.set nomdmx} 996*a9fa9459SzrjThe directive @code{.set mdmx} makes the assembler accept instructions 997*a9fa9459Szrjfrom the MDMX Application Specific Extension from that point on 998*a9fa9459Szrjin the assembly. The @code{.set nomdmx} directive prevents MDMX 999*a9fa9459Szrjinstructions from being accepted. 1000*a9fa9459Szrj 1001*a9fa9459Szrj@cindex MIPS DSP Release 1 instruction generation override 1002*a9fa9459Szrj@kindex @code{.set dsp} 1003*a9fa9459Szrj@kindex @code{.set nodsp} 1004*a9fa9459SzrjThe directive @code{.set dsp} makes the assembler accept instructions 1005*a9fa9459Szrjfrom the DSP Release 1 Application Specific Extension from that point 1006*a9fa9459Szrjon in the assembly. The @code{.set nodsp} directive prevents DSP 1007*a9fa9459SzrjRelease 1 instructions from being accepted. 1008*a9fa9459Szrj 1009*a9fa9459Szrj@cindex MIPS DSP Release 2 instruction generation override 1010*a9fa9459Szrj@kindex @code{.set dspr2} 1011*a9fa9459Szrj@kindex @code{.set nodspr2} 1012*a9fa9459SzrjThe directive @code{.set dspr2} makes the assembler accept instructions 1013*a9fa9459Szrjfrom the DSP Release 2 Application Specific Extension from that point 1014*a9fa9459Szrjon in the assembly. This directive implies @code{.set dsp}. The 1015*a9fa9459Szrj@code{.set nodspr2} directive prevents DSP Release 2 instructions from 1016*a9fa9459Szrjbeing accepted. 1017*a9fa9459Szrj 1018*a9fa9459Szrj@cindex MIPS DSP Release 3 instruction generation override 1019*a9fa9459Szrj@kindex @code{.set dspr3} 1020*a9fa9459Szrj@kindex @code{.set nodspr3} 1021*a9fa9459SzrjThe directive @code{.set dspr3} makes the assembler accept instructions 1022*a9fa9459Szrjfrom the DSP Release 3 Application Specific Extension from that point 1023*a9fa9459Szrjon in the assembly. This directive implies @code{.set dsp} and 1024*a9fa9459Szrj@code{.set dspr2}. The @code{.set nodspr3} directive prevents DSP 1025*a9fa9459SzrjRelease 3 instructions from being accepted. 1026*a9fa9459Szrj 1027*a9fa9459Szrj@cindex MIPS MT instruction generation override 1028*a9fa9459Szrj@kindex @code{.set mt} 1029*a9fa9459Szrj@kindex @code{.set nomt} 1030*a9fa9459SzrjThe directive @code{.set mt} makes the assembler accept instructions 1031*a9fa9459Szrjfrom the MT Application Specific Extension from that point on 1032*a9fa9459Szrjin the assembly. The @code{.set nomt} directive prevents MT 1033*a9fa9459Szrjinstructions from being accepted. 1034*a9fa9459Szrj 1035*a9fa9459Szrj@cindex MIPS MCU instruction generation override 1036*a9fa9459Szrj@kindex @code{.set mcu} 1037*a9fa9459Szrj@kindex @code{.set nomcu} 1038*a9fa9459SzrjThe directive @code{.set mcu} makes the assembler accept instructions 1039*a9fa9459Szrjfrom the MCU Application Specific Extension from that point on 1040*a9fa9459Szrjin the assembly. The @code{.set nomcu} directive prevents MCU 1041*a9fa9459Szrjinstructions from being accepted. 1042*a9fa9459Szrj 1043*a9fa9459Szrj@cindex MIPS SIMD Architecture instruction generation override 1044*a9fa9459Szrj@kindex @code{.set msa} 1045*a9fa9459Szrj@kindex @code{.set nomsa} 1046*a9fa9459SzrjThe directive @code{.set msa} makes the assembler accept instructions 1047*a9fa9459Szrjfrom the MIPS SIMD Architecture Extension from that point on 1048*a9fa9459Szrjin the assembly. The @code{.set nomsa} directive prevents MSA 1049*a9fa9459Szrjinstructions from being accepted. 1050*a9fa9459Szrj 1051*a9fa9459Szrj@cindex Virtualization instruction generation override 1052*a9fa9459Szrj@kindex @code{.set virt} 1053*a9fa9459Szrj@kindex @code{.set novirt} 1054*a9fa9459SzrjThe directive @code{.set virt} makes the assembler accept instructions 1055*a9fa9459Szrjfrom the Virtualization Application Specific Extension from that point 1056*a9fa9459Szrjon in the assembly. The @code{.set novirt} directive prevents Virtualization 1057*a9fa9459Szrjinstructions from being accepted. 1058*a9fa9459Szrj 1059*a9fa9459Szrj@cindex MIPS eXtended Physical Address (XPA) instruction generation override 1060*a9fa9459Szrj@kindex @code{.set xpa} 1061*a9fa9459Szrj@kindex @code{.set noxpa} 1062*a9fa9459SzrjThe directive @code{.set xpa} makes the assembler accept instructions 1063*a9fa9459Szrjfrom the XPA Extension from that point on in the assembly. The 1064*a9fa9459Szrj@code{.set noxpa} directive prevents XPA instructions from being accepted. 1065*a9fa9459Szrj 1066*a9fa9459SzrjTraditional MIPS assemblers do not support these directives. 1067*a9fa9459Szrj 1068*a9fa9459Szrj@node MIPS Floating-Point 1069*a9fa9459Szrj@section Directives to override floating-point options 1070*a9fa9459Szrj 1071*a9fa9459Szrj@cindex Disable floating-point instructions 1072*a9fa9459Szrj@kindex @code{.set softfloat} 1073*a9fa9459Szrj@kindex @code{.set hardfloat} 1074*a9fa9459SzrjThe directives @code{.set softfloat} and @code{.set hardfloat} provide 1075*a9fa9459Szrjfiner control of disabling and enabling float-point instructions. 1076*a9fa9459SzrjThese directives always override the default (that hard-float 1077*a9fa9459Szrjinstructions are accepted) or the command-line options 1078*a9fa9459Szrj(@samp{-msoft-float} and @samp{-mhard-float}). 1079*a9fa9459Szrj 1080*a9fa9459Szrj@cindex Disable single-precision floating-point operations 1081*a9fa9459Szrj@kindex @code{.set singlefloat} 1082*a9fa9459Szrj@kindex @code{.set doublefloat} 1083*a9fa9459SzrjThe directives @code{.set singlefloat} and @code{.set doublefloat} 1084*a9fa9459Szrjprovide finer control of disabling and enabling double-precision 1085*a9fa9459Szrjfloat-point operations. These directives always override the default 1086*a9fa9459Szrj(that double-precision operations are accepted) or the command-line 1087*a9fa9459Szrjoptions (@samp{-msingle-float} and @samp{-mdouble-float}). 1088*a9fa9459Szrj 1089*a9fa9459SzrjTraditional MIPS assemblers do not support these directives. 1090*a9fa9459Szrj 1091*a9fa9459Szrj@node MIPS Syntax 1092*a9fa9459Szrj@section Syntactical considerations for the MIPS assembler 1093*a9fa9459Szrj@menu 1094*a9fa9459Szrj* MIPS-Chars:: Special Characters 1095*a9fa9459Szrj@end menu 1096*a9fa9459Szrj 1097*a9fa9459Szrj@node MIPS-Chars 1098*a9fa9459Szrj@subsection Special Characters 1099*a9fa9459Szrj 1100*a9fa9459Szrj@cindex line comment character, MIPS 1101*a9fa9459Szrj@cindex MIPS line comment character 1102*a9fa9459SzrjThe presence of a @samp{#} on a line indicates the start of a comment 1103*a9fa9459Szrjthat extends to the end of the current line. 1104*a9fa9459Szrj 1105*a9fa9459SzrjIf a @samp{#} appears as the first character of a line, the whole line 1106*a9fa9459Szrjis treated as a comment, but in this case the line can also be a 1107*a9fa9459Szrjlogical line number directive (@pxref{Comments}) or a 1108*a9fa9459Szrjpreprocessor control command (@pxref{Preprocessing}). 1109*a9fa9459Szrj 1110*a9fa9459Szrj@cindex line separator, MIPS 1111*a9fa9459Szrj@cindex statement separator, MIPS 1112*a9fa9459Szrj@cindex MIPS line separator 1113*a9fa9459SzrjThe @samp{;} character can be used to separate statements on the same 1114*a9fa9459Szrjline. 1115