1*a9fa9459Szrj@c Copyright (C) 2009-2016 Free Software Foundation, Inc. 2*a9fa9459Szrj@c This is part of the GAS manual. 3*a9fa9459Szrj@c For copying conditions, see the file as.texinfo. 4*a9fa9459Szrj@ifset GENERIC 5*a9fa9459Szrj@page 6*a9fa9459Szrj@node S/390-Dependent 7*a9fa9459Szrj@chapter IBM S/390 Dependent Features 8*a9fa9459Szrj@end ifset 9*a9fa9459Szrj@ifclear GENERIC 10*a9fa9459Szrj@node Machine Dependencies 11*a9fa9459Szrj@chapter IBM S/390 Dependent Features 12*a9fa9459Szrj@end ifclear 13*a9fa9459Szrj 14*a9fa9459Szrj@cindex s390 support 15*a9fa9459Szrj 16*a9fa9459SzrjThe s390 version of @code{@value{AS}} supports two architectures modes 17*a9fa9459Szrjand seven chip levels. The architecture modes are the Enterprise System 18*a9fa9459SzrjArchitecture (ESA) and the newer z/Architecture mode. The chip levels 19*a9fa9459Szrjare g5, g6, z900, z990, z9-109, z9-ec, z10, z196, zEC12, and z13. 20*a9fa9459Szrj 21*a9fa9459Szrj@menu 22*a9fa9459Szrj* s390 Options:: Command-line Options. 23*a9fa9459Szrj* s390 Characters:: Special Characters. 24*a9fa9459Szrj* s390 Syntax:: Assembler Instruction syntax. 25*a9fa9459Szrj* s390 Directives:: Assembler Directives. 26*a9fa9459Szrj* s390 Floating Point:: Floating Point. 27*a9fa9459Szrj@end menu 28*a9fa9459Szrj 29*a9fa9459Szrj@node s390 Options 30*a9fa9459Szrj@section Options 31*a9fa9459Szrj@cindex options for s390 32*a9fa9459Szrj@cindex s390 options 33*a9fa9459Szrj 34*a9fa9459SzrjThe following table lists all available s390 specific options: 35*a9fa9459Szrj 36*a9fa9459Szrj@table @code 37*a9fa9459Szrj@cindex @samp{-m31} option, s390 38*a9fa9459Szrj@cindex @samp{-m64} option, s390 39*a9fa9459Szrj@item -m31 | -m64 40*a9fa9459SzrjSelect 31- or 64-bit ABI implying a word size of 32- or 64-bit. 41*a9fa9459Szrj 42*a9fa9459SzrjThese options are only available with the ELF object file format, and 43*a9fa9459Szrjrequire that the necessary BFD support has been included (on a 31-bit 44*a9fa9459Szrjplatform you must add --enable-64-bit-bfd on the call to the configure 45*a9fa9459Szrjscript to enable 64-bit usage and use s390x as target platform). 46*a9fa9459Szrj 47*a9fa9459Szrj@cindex @samp{-mesa} option, s390 48*a9fa9459Szrj@cindex @samp{-mzarch} option, s390 49*a9fa9459Szrj@item -mesa | -mzarch 50*a9fa9459SzrjSelect the architecture mode, either the Enterprise System Architecture 51*a9fa9459Szrj(esa) mode or the z/Architecture mode (zarch). 52*a9fa9459Szrj 53*a9fa9459SzrjThe 64-bit instructions are only available with the z/Architecture mode. 54*a9fa9459SzrjThe combination of @samp{-m64} and @samp{-mesa} results in a warning 55*a9fa9459Szrjmessage. 56*a9fa9459Szrj 57*a9fa9459Szrj@cindex @samp{-march=} option, s390 58*a9fa9459Szrj@item -march=@var{CPU} 59*a9fa9459SzrjThis option specifies the target processor. The following processor names 60*a9fa9459Szrjare recognized: 61*a9fa9459Szrj@code{g5}, 62*a9fa9459Szrj@code{g6}, 63*a9fa9459Szrj@code{z900}, 64*a9fa9459Szrj@code{z990}, 65*a9fa9459Szrj@code{z9-109}, 66*a9fa9459Szrj@code{z9-ec}, 67*a9fa9459Szrj@code{z10}, 68*a9fa9459Szrj@code{z196}, 69*a9fa9459Szrj@code{zEC12}, and 70*a9fa9459Szrj@code{z13}. 71*a9fa9459SzrjAssembling an instruction that is not supported on the target processor 72*a9fa9459Szrjresults in an error message. Do not specify @code{g5} or @code{g6} 73*a9fa9459Szrjwith @samp{-mzarch}. 74*a9fa9459Szrj 75*a9fa9459Szrj@cindex @samp{-mregnames} option, s390 76*a9fa9459Szrj@item -mregnames 77*a9fa9459SzrjAllow symbolic names for registers. 78*a9fa9459Szrj 79*a9fa9459Szrj@cindex @samp{-mno-regnames} option, s390 80*a9fa9459Szrj@item -mno-regnames 81*a9fa9459SzrjDo not allow symbolic names for registers. 82*a9fa9459Szrj 83*a9fa9459Szrj@cindex @samp{-mwarn-areg-zero} option, s390 84*a9fa9459Szrj@item -mwarn-areg-zero 85*a9fa9459SzrjWarn whenever the operand for a base or index register has been specified 86*a9fa9459Szrjbut evaluates to zero. This can indicate the misuse of general purpose 87*a9fa9459Szrjregister 0 as an address register. 88*a9fa9459Szrj 89*a9fa9459Szrj@end table 90*a9fa9459Szrj 91*a9fa9459Szrj@node s390 Characters 92*a9fa9459Szrj@section Special Characters 93*a9fa9459Szrj@cindex line comment character, s390 94*a9fa9459Szrj@cindex s390 line comment character 95*a9fa9459Szrj 96*a9fa9459Szrj@samp{#} is the line comment character. 97*a9fa9459Szrj 98*a9fa9459SzrjIf a @samp{#} appears as the first character of a line then the whole 99*a9fa9459Szrjline is treated as a comment, but in this case the line could also be 100*a9fa9459Szrja logical line number directive (@pxref{Comments}) or a preprocessor 101*a9fa9459Szrjcontrol command (@pxref{Preprocessing}). 102*a9fa9459Szrj 103*a9fa9459Szrj@cindex line separator, s390 104*a9fa9459Szrj@cindex statement separator, s390 105*a9fa9459Szrj@cindex s390 line separator 106*a9fa9459SzrjThe @samp{;} character can be used instead of a newline to separate 107*a9fa9459Szrjstatements. 108*a9fa9459Szrj 109*a9fa9459Szrj@node s390 Syntax 110*a9fa9459Szrj@section Instruction syntax 111*a9fa9459Szrj@cindex instruction syntax, s390 112*a9fa9459Szrj@cindex s390 instruction syntax 113*a9fa9459Szrj 114*a9fa9459SzrjThe assembler syntax closely follows the syntax outlined in 115*a9fa9459SzrjEnterprise Systems Architecture/390 Principles of Operation (SA22-7201) 116*a9fa9459Szrjand the z/Architecture Principles of Operation (SA22-7832). 117*a9fa9459Szrj 118*a9fa9459SzrjEach instruction has two major parts, the instruction mnemonic 119*a9fa9459Szrjand the instruction operands. The instruction format varies. 120*a9fa9459Szrj 121*a9fa9459Szrj@menu 122*a9fa9459Szrj* s390 Register:: Register Naming 123*a9fa9459Szrj* s390 Mnemonics:: Instruction Mnemonics 124*a9fa9459Szrj* s390 Operands:: Instruction Operands 125*a9fa9459Szrj* s390 Formats:: Instruction Formats 126*a9fa9459Szrj* s390 Aliases:: Instruction Aliases 127*a9fa9459Szrj* s390 Operand Modifier:: Instruction Operand Modifier 128*a9fa9459Szrj* s390 Instruction Marker:: Instruction Marker 129*a9fa9459Szrj* s390 Literal Pool Entries:: Literal Pool Entries 130*a9fa9459Szrj@end menu 131*a9fa9459Szrj 132*a9fa9459Szrj@node s390 Register 133*a9fa9459Szrj@subsection Register naming 134*a9fa9459Szrj@cindex register naming, s390 135*a9fa9459Szrj@cindex s390 register naming 136*a9fa9459Szrj 137*a9fa9459SzrjThe @code{@value{AS}} recognizes a number of predefined symbols for the 138*a9fa9459Szrjvarious processor registers. A register specification in one of the 139*a9fa9459Szrjinstruction formats is an unsigned integer between 0 and 15. The specific 140*a9fa9459Szrjinstruction and the position of the register in the instruction format 141*a9fa9459Szrjdenotes the type of the register. The register symbols are prefixed with 142*a9fa9459Szrj@samp{%}: 143*a9fa9459Szrj 144*a9fa9459Szrj@display 145*a9fa9459Szrj@multitable {%rN} {the 16 general purpose registers, 0 <= N <= 15} 146*a9fa9459Szrj@item %rN @tab the 16 general purpose registers, 0 <= N <= 15 147*a9fa9459Szrj@item %fN @tab the 16 floating point registers, 0 <= N <= 15 148*a9fa9459Szrj@item %aN @tab the 16 access registers, 0 <= N <= 15 149*a9fa9459Szrj@item %cN @tab the 16 control registers, 0 <= N <= 15 150*a9fa9459Szrj@item %lit @tab an alias for the general purpose register %r13 151*a9fa9459Szrj@item %sp @tab an alias for the general purpose register %r15 152*a9fa9459Szrj@end multitable 153*a9fa9459Szrj@end display 154*a9fa9459Szrj 155*a9fa9459Szrj@node s390 Mnemonics 156*a9fa9459Szrj@subsection Instruction Mnemonics 157*a9fa9459Szrj@cindex instruction mnemonics, s390 158*a9fa9459Szrj@cindex s390 instruction mnemonics 159*a9fa9459Szrj 160*a9fa9459SzrjAll instructions documented in the Principles of Operation are supported 161*a9fa9459Szrjwith the mnemonic and order of operands as described. 162*a9fa9459SzrjThe instruction mnemonic identifies the instruction format 163*a9fa9459Szrj(@ref{s390 Formats}) and the specific operation code for the instruction. 164*a9fa9459SzrjFor example, the @samp{lr} mnemonic denotes the instruction format @samp{RR} 165*a9fa9459Szrjwith the operation code @samp{0x18}. 166*a9fa9459Szrj 167*a9fa9459SzrjThe definition of the various mnemonics follows a scheme, where the first 168*a9fa9459Szrjcharacter usually hint at the type of the instruction: 169*a9fa9459Szrj 170*a9fa9459Szrj@display 171*a9fa9459Szrj@multitable {sla, sll} {if r is the last character the instruction operates on registers} 172*a9fa9459Szrj@item a @tab add instruction, for example @samp{al} for add logical 32-bit 173*a9fa9459Szrj@item b @tab branch instruction, for example @samp{bc} for branch on condition 174*a9fa9459Szrj@item c @tab compare or convert instruction, for example @samp{cr} for compare 175*a9fa9459Szrjregister 32-bit 176*a9fa9459Szrj@item d @tab divide instruction, for example @samp{dlr} devide logical register 177*a9fa9459Szrj64-bit to 32-bit 178*a9fa9459Szrj@item i @tab insert instruction, for example @samp{ic} insert character 179*a9fa9459Szrj@item l @tab load instruction, for example @samp{ltr} load and test register 180*a9fa9459Szrj@item mv @tab move instruction, for example @samp{mvc} move character 181*a9fa9459Szrj@item m @tab multiply instruction, for example @samp{mh} multiply halfword 182*a9fa9459Szrj@item n @tab and instruction, for example @samp{ni} and immediate 183*a9fa9459Szrj@item o @tab or instruction, for example @samp{oc} or character 184*a9fa9459Szrj@item sla, sll @tab shift left single instruction 185*a9fa9459Szrj@item sra, srl @tab shift right single instruction 186*a9fa9459Szrj@item st @tab store instruction, for example @samp{stm} store multiple 187*a9fa9459Szrj@item s @tab subtract instruction, for example @samp{slr} subtract 188*a9fa9459Szrjlogical 32-bit 189*a9fa9459Szrj@item t @tab test or translate instruction, of example @samp{tm} test under mask 190*a9fa9459Szrj@item x @tab exclusive or instruction, for example @samp{xc} exclusive or 191*a9fa9459Szrjcharacter 192*a9fa9459Szrj@end multitable 193*a9fa9459Szrj@end display 194*a9fa9459Szrj 195*a9fa9459SzrjCertain characters at the end of the mnemonic may describe a property 196*a9fa9459Szrjof the instruction: 197*a9fa9459Szrj 198*a9fa9459Szrj@display 199*a9fa9459Szrj@multitable {c} {if r is the last character the instruction operates on registers} 200*a9fa9459Szrj@item c @tab the instruction uses a 8-bit character operand 201*a9fa9459Szrj@item f @tab the instruction extends a 32-bit operand to 64 bit 202*a9fa9459Szrj@item g @tab the operands are treated as 64-bit values 203*a9fa9459Szrj@item h @tab the operand uses a 16-bit halfword operand 204*a9fa9459Szrj@item i @tab the instruction uses an immediate operand 205*a9fa9459Szrj@item l @tab the instruction uses unsigned, logical operands 206*a9fa9459Szrj@item m @tab the instruction uses a mask or operates on multiple values 207*a9fa9459Szrj@item r @tab if r is the last character, the instruction operates on registers 208*a9fa9459Szrj@item y @tab the instruction uses 20-bit displacements 209*a9fa9459Szrj@end multitable 210*a9fa9459Szrj@end display 211*a9fa9459Szrj 212*a9fa9459SzrjThere are many exceptions to the scheme outlined in the above lists, in 213*a9fa9459Szrjparticular for the priviledged instructions. For non-priviledged 214*a9fa9459Szrjinstruction it works quite well, for example the instruction @samp{clgfr} 215*a9fa9459Szrjc: compare instruction, l: unsigned operands, g: 64-bit operands, 216*a9fa9459Szrjf: 32- to 64-bit extension, r: register operands. The instruction compares 217*a9fa9459Szrjan 64-bit value in a register with the zero extended 32-bit value from 218*a9fa9459Szrja second register. 219*a9fa9459SzrjFor a complete list of all mnemonics see appendix B in the Principles 220*a9fa9459Szrjof Operation. 221*a9fa9459Szrj 222*a9fa9459Szrj@node s390 Operands 223*a9fa9459Szrj@subsection Instruction Operands 224*a9fa9459Szrj@cindex instruction operands, s390 225*a9fa9459Szrj@cindex s390 instruction operands 226*a9fa9459Szrj 227*a9fa9459SzrjInstruction operands can be grouped into three classes, operands located 228*a9fa9459Szrjin registers, immediate operands, and operands in storage. 229*a9fa9459Szrj 230*a9fa9459SzrjA register operand can be located in general, floating-point, access, 231*a9fa9459Szrjor control register. The register is identified by a four-bit field. 232*a9fa9459SzrjThe field containing the register operand is called the R field. 233*a9fa9459Szrj 234*a9fa9459SzrjImmediate operands are contained within the instruction and can have 235*a9fa9459Szrj8, 16 or 32 bits. The field containing the immediate operand is called 236*a9fa9459Szrjthe I field. Dependent on the instruction the I field is either signed 237*a9fa9459Szrjor unsigned. 238*a9fa9459Szrj 239*a9fa9459SzrjA storage operand consists of an address and a length. The address of a 240*a9fa9459Szrjstorage operands can be specified in any of these ways: 241*a9fa9459Szrj 242*a9fa9459Szrj@itemize 243*a9fa9459Szrj@item The content of a single general R 244*a9fa9459Szrj@item The sum of the content of a general register called the base 245*a9fa9459Szrjregister B plus the content of a displacement field D 246*a9fa9459Szrj@item The sum of the contents of two general registers called the 247*a9fa9459Szrjindex register X and the base register B plus the content of a 248*a9fa9459Szrjdisplacement field 249*a9fa9459Szrj@item The sum of the current instruction address and a 32-bit signed 250*a9fa9459Szrjimmediate field multiplied by two. 251*a9fa9459Szrj@end itemize 252*a9fa9459Szrj 253*a9fa9459SzrjThe length of a storage operand can be: 254*a9fa9459Szrj 255*a9fa9459Szrj@itemize 256*a9fa9459Szrj@item Implied by the instruction 257*a9fa9459Szrj@item Specified by a bitmask 258*a9fa9459Szrj@item Specified by a four-bit or eight-bit length field L 259*a9fa9459Szrj@item Specified by the content of a general register 260*a9fa9459Szrj@end itemize 261*a9fa9459Szrj 262*a9fa9459SzrjThe notation for storage operand addresses formed from multiple fields is 263*a9fa9459Szrjas follows: 264*a9fa9459Szrj 265*a9fa9459Szrj@table @code 266*a9fa9459Szrj@item Dn(Bn) 267*a9fa9459Szrjthe address for operand number n is formed from the content of general 268*a9fa9459Szrjregister Bn called the base register and the displacement field Dn. 269*a9fa9459Szrj@item Dn(Xn,Bn) 270*a9fa9459Szrjthe address for operand number n is formed from the content of general 271*a9fa9459Szrjregister Xn called the index register, general register Bn called the 272*a9fa9459Szrjbase register and the displacement field Dn. 273*a9fa9459Szrj@item Dn(Ln,Bn) 274*a9fa9459Szrjthe address for operand number n is formed from the content of general 275*a9fa9459Szrjregiser Bn called the base register and the displacement field Dn. 276*a9fa9459SzrjThe length of the operand n is specified by the field Ln. 277*a9fa9459Szrj@end table 278*a9fa9459Szrj 279*a9fa9459SzrjThe base registers Bn and the index registers Xn of a storage operand can 280*a9fa9459Szrjbe skipped. If Bn and Xn are skipped, a zero will be stored to the operand 281*a9fa9459Szrjfield. The notation changes as follows: 282*a9fa9459Szrj 283*a9fa9459Szrj@display 284*a9fa9459Szrj@multitable @columnfractions 0.30 0.30 285*a9fa9459Szrj@headitem full notation @tab short notation 286*a9fa9459Szrj@item Dn(0,Bn) @tab Dn(Bn) 287*a9fa9459Szrj@item Dn(0,0) @tab Dn 288*a9fa9459Szrj@item Dn(0) @tab Dn 289*a9fa9459Szrj@item Dn(Ln,0) @tab Dn(Ln) 290*a9fa9459Szrj@end multitable 291*a9fa9459Szrj@end display 292*a9fa9459Szrj 293*a9fa9459Szrj 294*a9fa9459Szrj@node s390 Formats 295*a9fa9459Szrj@subsection Instruction Formats 296*a9fa9459Szrj@cindex instruction formats, s390 297*a9fa9459Szrj@cindex s390 instruction formats 298*a9fa9459Szrj 299*a9fa9459SzrjThe Principles of Operation manuals lists 26 instruction formats where 300*a9fa9459Szrjsome of the formats have multiple variants. For the @samp{.insn} 301*a9fa9459Szrjpseudo directive the assembler recognizes some of the formats. 302*a9fa9459SzrjTypically, the most general variant of the instruction format is used 303*a9fa9459Szrjby the @samp{.insn} directive. 304*a9fa9459Szrj 305*a9fa9459SzrjThe following table lists the abbreviations used in the table of 306*a9fa9459Szrjinstruction formats: 307*a9fa9459Szrj 308*a9fa9459Szrj@display 309*a9fa9459Szrj@multitable {OpCode / OpCd} {Displacement lower 12 bits for operand x.} 310*a9fa9459Szrj@item OpCode / OpCd @tab Part of the op code. 311*a9fa9459Szrj@item Bx @tab Base register number for operand x. 312*a9fa9459Szrj@item Dx @tab Displacement for operand x. 313*a9fa9459Szrj@item DLx @tab Displacement lower 12 bits for operand x. 314*a9fa9459Szrj@item DHx @tab Displacement higher 8-bits for operand x. 315*a9fa9459Szrj@item Rx @tab Register number for operand x. 316*a9fa9459Szrj@item Xx @tab Index register number for operand x. 317*a9fa9459Szrj@item Ix @tab Signed immediate for operand x. 318*a9fa9459Szrj@item Ux @tab Unsigned immediate for operand x. 319*a9fa9459Szrj@end multitable 320*a9fa9459Szrj@end display 321*a9fa9459Szrj 322*a9fa9459SzrjAn instruction is two, four, or six bytes in length and must be aligned 323*a9fa9459Szrjon a 2 byte boundary. The first two bits of the instruction specify the 324*a9fa9459Szrjlength of the instruction, 00 indicates a two byte instruction, 01 and 10 325*a9fa9459Szrjindicates a four byte instruction, and 11 indicates a six byte instruction. 326*a9fa9459Szrj 327*a9fa9459SzrjThe following table lists the s390 instruction formats that are available 328*a9fa9459Szrjwith the @samp{.insn} pseudo directive: 329*a9fa9459Szrj 330*a9fa9459Szrj@table @code 331*a9fa9459Szrj@item E format 332*a9fa9459Szrj@verbatim 333*a9fa9459Szrj+-------------+ 334*a9fa9459Szrj| OpCode | 335*a9fa9459Szrj+-------------+ 336*a9fa9459Szrj0 15 337*a9fa9459Szrj@end verbatim 338*a9fa9459Szrj 339*a9fa9459Szrj@item RI format: <insn> R1,I2 340*a9fa9459Szrj@verbatim 341*a9fa9459Szrj+--------+----+----+------------------+ 342*a9fa9459Szrj| OpCode | R1 |OpCd| I2 | 343*a9fa9459Szrj+--------+----+----+------------------+ 344*a9fa9459Szrj0 8 12 16 31 345*a9fa9459Szrj@end verbatim 346*a9fa9459Szrj 347*a9fa9459Szrj@item RIE format: <insn> R1,R3,I2 348*a9fa9459Szrj@verbatim 349*a9fa9459Szrj+--------+----+----+------------------+--------+--------+ 350*a9fa9459Szrj| OpCode | R1 | R3 | I2 |////////| OpCode | 351*a9fa9459Szrj+--------+----+----+------------------+--------+--------+ 352*a9fa9459Szrj0 8 12 16 32 40 47 353*a9fa9459Szrj@end verbatim 354*a9fa9459Szrj 355*a9fa9459Szrj@item RIL format: <insn> R1,I2 356*a9fa9459Szrj@verbatim 357*a9fa9459Szrj+--------+----+----+------------------------------------+ 358*a9fa9459Szrj| OpCode | R1 |OpCd| I2 | 359*a9fa9459Szrj+--------+----+----+------------------------------------+ 360*a9fa9459Szrj0 8 12 16 47 361*a9fa9459Szrj@end verbatim 362*a9fa9459Szrj 363*a9fa9459Szrj@item RILU format: <insn> R1,U2 364*a9fa9459Szrj@verbatim 365*a9fa9459Szrj+--------+----+----+------------------------------------+ 366*a9fa9459Szrj| OpCode | R1 |OpCd| U2 | 367*a9fa9459Szrj+--------+----+----+------------------------------------+ 368*a9fa9459Szrj0 8 12 16 47 369*a9fa9459Szrj@end verbatim 370*a9fa9459Szrj 371*a9fa9459Szrj@item RIS format: <insn> R1,I2,M3,D4(B4) 372*a9fa9459Szrj@verbatim 373*a9fa9459Szrj+--------+----+----+----+-------------+--------+--------+ 374*a9fa9459Szrj| OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | 375*a9fa9459Szrj+--------+----+----+----+-------------+--------+--------+ 376*a9fa9459Szrj0 8 12 16 20 32 36 47 377*a9fa9459Szrj@end verbatim 378*a9fa9459Szrj 379*a9fa9459Szrj@item RR format: <insn> R1,R2 380*a9fa9459Szrj@verbatim 381*a9fa9459Szrj+--------+----+----+ 382*a9fa9459Szrj| OpCode | R1 | R2 | 383*a9fa9459Szrj+--------+----+----+ 384*a9fa9459Szrj0 8 12 15 385*a9fa9459Szrj@end verbatim 386*a9fa9459Szrj 387*a9fa9459Szrj@item RRE format: <insn> R1,R2 388*a9fa9459Szrj@verbatim 389*a9fa9459Szrj+------------------+--------+----+----+ 390*a9fa9459Szrj| OpCode |////////| R1 | R2 | 391*a9fa9459Szrj+------------------+--------+----+----+ 392*a9fa9459Szrj0 16 24 28 31 393*a9fa9459Szrj@end verbatim 394*a9fa9459Szrj 395*a9fa9459Szrj@item RRF format: <insn> R1,R2,R3,M4 396*a9fa9459Szrj@verbatim 397*a9fa9459Szrj+------------------+----+----+----+----+ 398*a9fa9459Szrj| OpCode | R3 | M4 | R1 | R2 | 399*a9fa9459Szrj+------------------+----+----+----+----+ 400*a9fa9459Szrj0 16 20 24 28 31 401*a9fa9459Szrj@end verbatim 402*a9fa9459Szrj 403*a9fa9459Szrj@item RRS format: <insn> R1,R2,M3,D4(B4) 404*a9fa9459Szrj@verbatim 405*a9fa9459Szrj+--------+----+----+----+-------------+----+----+--------+ 406*a9fa9459Szrj| OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | 407*a9fa9459Szrj+--------+----+----+----+-------------+----+----+--------+ 408*a9fa9459Szrj0 8 12 16 20 32 36 40 47 409*a9fa9459Szrj@end verbatim 410*a9fa9459Szrj 411*a9fa9459Szrj@item RS format: <insn> R1,R3,D2(B2) 412*a9fa9459Szrj@verbatim 413*a9fa9459Szrj+--------+----+----+----+-------------+ 414*a9fa9459Szrj| OpCode | R1 | R3 | B2 | D2 | 415*a9fa9459Szrj+--------+----+----+----+-------------+ 416*a9fa9459Szrj0 8 12 16 20 31 417*a9fa9459Szrj@end verbatim 418*a9fa9459Szrj 419*a9fa9459Szrj@item RSE format: <insn> R1,R3,D2(B2) 420*a9fa9459Szrj@verbatim 421*a9fa9459Szrj+--------+----+----+----+-------------+--------+--------+ 422*a9fa9459Szrj| OpCode | R1 | R3 | B2 | D2 |////////| OpCode | 423*a9fa9459Szrj+--------+----+----+----+-------------+--------+--------+ 424*a9fa9459Szrj0 8 12 16 20 32 40 47 425*a9fa9459Szrj@end verbatim 426*a9fa9459Szrj 427*a9fa9459Szrj@item RSI format: <insn> R1,R3,I2 428*a9fa9459Szrj@verbatim 429*a9fa9459Szrj+--------+----+----+------------------------------------+ 430*a9fa9459Szrj| OpCode | R1 | R3 | I2 | 431*a9fa9459Szrj+--------+----+----+------------------------------------+ 432*a9fa9459Szrj0 8 12 16 47 433*a9fa9459Szrj@end verbatim 434*a9fa9459Szrj 435*a9fa9459Szrj@item RSY format: <insn> R1,R3,D2(B2) 436*a9fa9459Szrj@verbatim 437*a9fa9459Szrj+--------+----+----+----+-------------+--------+--------+ 438*a9fa9459Szrj| OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | 439*a9fa9459Szrj+--------+----+----+----+-------------+--------+--------+ 440*a9fa9459Szrj0 8 12 16 20 32 40 47 441*a9fa9459Szrj@end verbatim 442*a9fa9459Szrj 443*a9fa9459Szrj@item RX format: <insn> R1,D2(X2,B2) 444*a9fa9459Szrj@verbatim 445*a9fa9459Szrj+--------+----+----+----+-------------+ 446*a9fa9459Szrj| OpCode | R1 | X2 | B2 | D2 | 447*a9fa9459Szrj+--------+----+----+----+-------------+ 448*a9fa9459Szrj0 8 12 16 20 31 449*a9fa9459Szrj@end verbatim 450*a9fa9459Szrj 451*a9fa9459Szrj@item RXE format: <insn> R1,D2(X2,B2) 452*a9fa9459Szrj@verbatim 453*a9fa9459Szrj+--------+----+----+----+-------------+--------+--------+ 454*a9fa9459Szrj| OpCode | R1 | X2 | B2 | D2 |////////| OpCode | 455*a9fa9459Szrj+--------+----+----+----+-------------+--------+--------+ 456*a9fa9459Szrj0 8 12 16 20 32 40 47 457*a9fa9459Szrj@end verbatim 458*a9fa9459Szrj 459*a9fa9459Szrj@item RXF format: <insn> R1,R3,D2(X2,B2) 460*a9fa9459Szrj@verbatim 461*a9fa9459Szrj+--------+----+----+----+-------------+----+---+--------+ 462*a9fa9459Szrj| OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | 463*a9fa9459Szrj+--------+----+----+----+-------------+----+---+--------+ 464*a9fa9459Szrj0 8 12 16 20 32 36 40 47 465*a9fa9459Szrj@end verbatim 466*a9fa9459Szrj 467*a9fa9459Szrj@item RXY format: <insn> R1,D2(X2,B2) 468*a9fa9459Szrj@verbatim 469*a9fa9459Szrj+--------+----+----+----+-------------+--------+--------+ 470*a9fa9459Szrj| OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | 471*a9fa9459Szrj+--------+----+----+----+-------------+--------+--------+ 472*a9fa9459Szrj0 8 12 16 20 32 36 40 47 473*a9fa9459Szrj@end verbatim 474*a9fa9459Szrj 475*a9fa9459Szrj@item S format: <insn> D2(B2) 476*a9fa9459Szrj@verbatim 477*a9fa9459Szrj+------------------+----+-------------+ 478*a9fa9459Szrj| OpCode | B2 | D2 | 479*a9fa9459Szrj+------------------+----+-------------+ 480*a9fa9459Szrj0 16 20 31 481*a9fa9459Szrj@end verbatim 482*a9fa9459Szrj 483*a9fa9459Szrj@item SI format: <insn> D1(B1),I2 484*a9fa9459Szrj@verbatim 485*a9fa9459Szrj+--------+---------+----+-------------+ 486*a9fa9459Szrj| OpCode | I2 | B1 | D1 | 487*a9fa9459Szrj+--------+---------+----+-------------+ 488*a9fa9459Szrj0 8 16 20 31 489*a9fa9459Szrj@end verbatim 490*a9fa9459Szrj 491*a9fa9459Szrj@item SIY format: <insn> D1(B1),U2 492*a9fa9459Szrj@verbatim 493*a9fa9459Szrj+--------+---------+----+-------------+--------+--------+ 494*a9fa9459Szrj| OpCode | I2 | B1 | DL1 | DH1 | OpCode | 495*a9fa9459Szrj+--------+---------+----+-------------+--------+--------+ 496*a9fa9459Szrj0 8 16 20 32 36 40 47 497*a9fa9459Szrj@end verbatim 498*a9fa9459Szrj 499*a9fa9459Szrj@item SIL format: <insn> D1(B1),I2 500*a9fa9459Szrj@verbatim 501*a9fa9459Szrj+------------------+----+-------------+-----------------+ 502*a9fa9459Szrj| OpCode | B1 | D1 | I2 | 503*a9fa9459Szrj+------------------+----+-------------+-----------------+ 504*a9fa9459Szrj0 16 20 32 47 505*a9fa9459Szrj@end verbatim 506*a9fa9459Szrj 507*a9fa9459Szrj@item SS format: <insn> D1(R1,B1),D2(B3),R3 508*a9fa9459Szrj@verbatim 509*a9fa9459Szrj+--------+----+----+----+-------------+----+------------+ 510*a9fa9459Szrj| OpCode | R1 | R3 | B1 | D1 | B2 | D2 | 511*a9fa9459Szrj+--------+----+----+----+-------------+----+------------+ 512*a9fa9459Szrj0 8 12 16 20 32 36 47 513*a9fa9459Szrj@end verbatim 514*a9fa9459Szrj 515*a9fa9459Szrj@item SSE format: <insn> D1(B1),D2(B2) 516*a9fa9459Szrj@verbatim 517*a9fa9459Szrj+------------------+----+-------------+----+------------+ 518*a9fa9459Szrj| OpCode | B1 | D1 | B2 | D2 | 519*a9fa9459Szrj+------------------+----+-------------+----+------------+ 520*a9fa9459Szrj0 8 12 16 20 32 36 47 521*a9fa9459Szrj@end verbatim 522*a9fa9459Szrj 523*a9fa9459Szrj@item SSF format: <insn> D1(B1),D2(B2),R3 524*a9fa9459Szrj@verbatim 525*a9fa9459Szrj+--------+----+----+----+-------------+----+------------+ 526*a9fa9459Szrj| OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | 527*a9fa9459Szrj+--------+----+----+----+-------------+----+------------+ 528*a9fa9459Szrj0 8 12 16 20 32 36 47 529*a9fa9459Szrj@end verbatim 530*a9fa9459Szrj 531*a9fa9459Szrj@end table 532*a9fa9459Szrj 533*a9fa9459SzrjFor the complete list of all instruction format variants see the 534*a9fa9459SzrjPrinciples of Operation manuals. 535*a9fa9459Szrj 536*a9fa9459Szrj@node s390 Aliases 537*a9fa9459Szrj@subsection Instruction Aliases 538*a9fa9459Szrj@cindex instruction aliases, s390 539*a9fa9459Szrj@cindex s390 instruction aliases 540*a9fa9459Szrj 541*a9fa9459SzrjA specific bit pattern can have multiple mnemonics, for example 542*a9fa9459Szrjthe bit pattern @samp{0xa7000000} has the mnemonics @samp{tmh} and 543*a9fa9459Szrj@samp{tmlh}. In addition, there are a number of mnemonics recognized by 544*a9fa9459Szrj@code{@value{AS}} that are not present in the Principles of Operation. 545*a9fa9459SzrjThese are the short forms of the branch instructions, where the condition 546*a9fa9459Szrjcode mask operand is encoded in the mnemonic. This is relevant for the 547*a9fa9459Szrjbranch instructions, the compare and branch instructions, and the 548*a9fa9459Szrjcompare and trap instructions. 549*a9fa9459Szrj 550*a9fa9459SzrjFor the branch instructions there are 20 condition code strings that can 551*a9fa9459Szrjbe used as part of the mnemonic in place of a mask operand in the instruction 552*a9fa9459Szrjformat: 553*a9fa9459Szrj 554*a9fa9459Szrj@display 555*a9fa9459Szrj@multitable @columnfractions .30 .30 556*a9fa9459Szrj@headitem instruction @tab short form 557*a9fa9459Szrj@item bcr M1,R2 @tab b<m>r R2 558*a9fa9459Szrj@item bc M1,D2(X2,B2) @tab b<m> D2(X2,B2) 559*a9fa9459Szrj@item brc M1,I2 @tab j<m> I2 560*a9fa9459Szrj@item brcl M1,I2 @tab jg<m> I2 561*a9fa9459Szrj@end multitable 562*a9fa9459Szrj@end display 563*a9fa9459Szrj 564*a9fa9459SzrjIn the mnemonic for a branch instruction the condition code string <m> 565*a9fa9459Szrjcan be any of the following: 566*a9fa9459Szrj 567*a9fa9459Szrj@display 568*a9fa9459Szrj@multitable {nle} {jump on not zero / if not zeros} 569*a9fa9459Szrj@item o @tab jump on overflow / if ones 570*a9fa9459Szrj@item h @tab jump on A high 571*a9fa9459Szrj@item p @tab jump on plus 572*a9fa9459Szrj@item nle @tab jump on not low or equal 573*a9fa9459Szrj@item l @tab jump on A low 574*a9fa9459Szrj@item m @tab jump on minus 575*a9fa9459Szrj@item nhe @tab jump on not high or equal 576*a9fa9459Szrj@item lh @tab jump on low or high 577*a9fa9459Szrj@item ne @tab jump on A not equal B 578*a9fa9459Szrj@item nz @tab jump on not zero / if not zeros 579*a9fa9459Szrj@item e @tab jump on A equal B 580*a9fa9459Szrj@item z @tab jump on zero / if zeroes 581*a9fa9459Szrj@item nlh @tab jump on not low or high 582*a9fa9459Szrj@item he @tab jump on high or equal 583*a9fa9459Szrj@item nl @tab jump on A not low 584*a9fa9459Szrj@item nm @tab jump on not minus / if not mixed 585*a9fa9459Szrj@item le @tab jump on low or equal 586*a9fa9459Szrj@item nh @tab jump on A not high 587*a9fa9459Szrj@item np @tab jump on not plus 588*a9fa9459Szrj@item no @tab jump on not overflow / if not ones 589*a9fa9459Szrj@end multitable 590*a9fa9459Szrj@end display 591*a9fa9459Szrj 592*a9fa9459SzrjFor the compare and branch, and compare and trap instructions there 593*a9fa9459Szrjare 12 condition code strings that can be used as part of the mnemonic in 594*a9fa9459Szrjplace of a mask operand in the instruction format: 595*a9fa9459Szrj 596*a9fa9459Szrj@display 597*a9fa9459Szrj@multitable @columnfractions .40 .40 598*a9fa9459Szrj@headitem instruction @tab short form 599*a9fa9459Szrj@item crb R1,R2,M3,D4(B4) @tab crb<m> R1,R2,D4(B4) 600*a9fa9459Szrj@item cgrb R1,R2,M3,D4(B4) @tab cgrb<m> R1,R2,D4(B4) 601*a9fa9459Szrj@item crj R1,R2,M3,I4 @tab crj<m> R1,R2,I4 602*a9fa9459Szrj@item cgrj R1,R2,M3,I4 @tab cgrj<m> R1,R2,I4 603*a9fa9459Szrj@item cib R1,I2,M3,D4(B4) @tab cib<m> R1,I2,D4(B4) 604*a9fa9459Szrj@item cgib R1,I2,M3,D4(B4) @tab cgib<m> R1,I2,D4(B4) 605*a9fa9459Szrj@item cij R1,I2,M3,I4 @tab cij<m> R1,I2,I4 606*a9fa9459Szrj@item cgij R1,I2,M3,I4 @tab cgij<m> R1,I2,I4 607*a9fa9459Szrj@item crt R1,R2,M3 @tab crt<m> R1,R2 608*a9fa9459Szrj@item cgrt R1,R2,M3 @tab cgrt<m> R1,R2 609*a9fa9459Szrj@item cit R1,I2,M3 @tab cit<m> R1,I2 610*a9fa9459Szrj@item cgit R1,I2,M3 @tab cgit<m> R1,I2 611*a9fa9459Szrj@item clrb R1,R2,M3,D4(B4) @tab clrb<m> R1,R2,D4(B4) 612*a9fa9459Szrj@item clgrb R1,R2,M3,D4(B4) @tab clgrb<m> R1,R2,D4(B4) 613*a9fa9459Szrj@item clrj R1,R2,M3,I4 @tab clrj<m> R1,R2,I4 614*a9fa9459Szrj@item clgrj R1,R2,M3,I4 @tab clgrj<m> R1,R2,I4 615*a9fa9459Szrj@item clib R1,I2,M3,D4(B4) @tab clib<m> R1,I2,D4(B4) 616*a9fa9459Szrj@item clgib R1,I2,M3,D4(B4) @tab clgib<m> R1,I2,D4(B4) 617*a9fa9459Szrj@item clij R1,I2,M3,I4 @tab clij<m> R1,I2,I4 618*a9fa9459Szrj@item clgij R1,I2,M3,I4 @tab clgij<m> R1,I2,I4 619*a9fa9459Szrj@item clrt R1,R2,M3 @tab clrt<m> R1,R2 620*a9fa9459Szrj@item clgrt R1,R2,M3 @tab clgrt<m> R1,R2 621*a9fa9459Szrj@item clfit R1,I2,M3 @tab clfit<m> R1,I2 622*a9fa9459Szrj@item clgit R1,I2,M3 @tab clgit<m> R1,I2 623*a9fa9459Szrj@end multitable 624*a9fa9459Szrj@end display 625*a9fa9459Szrj 626*a9fa9459SzrjIn the mnemonic for a compare and branch and compare and trap instruction 627*a9fa9459Szrjthe condition code string <m> can be any of the following: 628*a9fa9459Szrj 629*a9fa9459Szrj@display 630*a9fa9459Szrj@multitable {nle} {jump on not zero / if not zeros} 631*a9fa9459Szrj@item h @tab jump on A high 632*a9fa9459Szrj@item nle @tab jump on not low or equal 633*a9fa9459Szrj@item l @tab jump on A low 634*a9fa9459Szrj@item nhe @tab jump on not high or equal 635*a9fa9459Szrj@item ne @tab jump on A not equal B 636*a9fa9459Szrj@item lh @tab jump on low or high 637*a9fa9459Szrj@item e @tab jump on A equal B 638*a9fa9459Szrj@item nlh @tab jump on not low or high 639*a9fa9459Szrj@item nl @tab jump on A not low 640*a9fa9459Szrj@item he @tab jump on high or equal 641*a9fa9459Szrj@item nh @tab jump on A not high 642*a9fa9459Szrj@item le @tab jump on low or equal 643*a9fa9459Szrj@end multitable 644*a9fa9459Szrj@end display 645*a9fa9459Szrj 646*a9fa9459Szrj@node s390 Operand Modifier 647*a9fa9459Szrj@subsection Instruction Operand Modifier 648*a9fa9459Szrj@cindex instruction operand modifier, s390 649*a9fa9459Szrj@cindex s390 instruction operand modifier 650*a9fa9459Szrj 651*a9fa9459SzrjIf a symbol modifier is attached to a symbol in an expression for an 652*a9fa9459Szrjinstruction operand field, the symbol term is replaced with a reference 653*a9fa9459Szrjto an object in the global offset table (GOT) or the procedure linkage 654*a9fa9459Szrjtable (PLT). The following expressions are allowed: 655*a9fa9459Szrj@samp{symbol@@modifier + constant}, 656*a9fa9459Szrj@samp{symbol@@modifier + label + constant}, and 657*a9fa9459Szrj@samp{symbol@@modifier - label + constant}. 658*a9fa9459SzrjThe term @samp{symbol} is the symbol that will be entered into the GOT or 659*a9fa9459SzrjPLT, @samp{label} is a local label, and @samp{constant} is an arbitrary 660*a9fa9459Szrjexpression that the assembler can evaluate to a constant value. 661*a9fa9459Szrj 662*a9fa9459SzrjThe term @samp{(symbol + constant1)@@modifier +/- label + constant2} 663*a9fa9459Szrjis also accepted but a warning message is printed and the term is 664*a9fa9459Szrjconverted to @samp{symbol@@modifier +/- label + constant1 + constant2}. 665*a9fa9459Szrj 666*a9fa9459Szrj@table @code 667*a9fa9459Szrj@item @@got 668*a9fa9459Szrj@itemx @@got12 669*a9fa9459SzrjThe @@got modifier can be used for displacement fields, 16-bit immediate 670*a9fa9459Szrjfields and 32-bit pc-relative immediate fields. The @@got12 modifier is 671*a9fa9459Szrjsynonym to @@got. The symbol is added to the GOT. For displacement 672*a9fa9459Szrjfields and 16-bit immediate fields the symbol term is replaced with 673*a9fa9459Szrjthe offset from the start of the GOT to the GOT slot for the symbol. 674*a9fa9459SzrjFor a 32-bit pc-relative field the pc-relative offset to the GOT 675*a9fa9459Szrjslot from the current instruction address is used. 676*a9fa9459Szrj@item @@gotent 677*a9fa9459SzrjThe @@gotent modifier can be used for 32-bit pc-relative immediate fields. 678*a9fa9459SzrjThe symbol is added to the GOT and the symbol term is replaced with 679*a9fa9459Szrjthe pc-relative offset from the current instruction to the GOT slot for the 680*a9fa9459Szrjsymbol. 681*a9fa9459Szrj@item @@gotoff 682*a9fa9459SzrjThe @@gotoff modifier can be used for 16-bit immediate fields. The symbol 683*a9fa9459Szrjterm is replaced with the offset from the start of the GOT to the 684*a9fa9459Szrjaddress of the symbol. 685*a9fa9459Szrj@item @@gotplt 686*a9fa9459SzrjThe @@gotplt modifier can be used for displacement fields, 16-bit immediate 687*a9fa9459Szrjfields, and 32-bit pc-relative immediate fields. A procedure linkage 688*a9fa9459Szrjtable entry is generated for the symbol and a jump slot for the symbol 689*a9fa9459Szrjis added to the GOT. For displacement fields and 16-bit immediate 690*a9fa9459Szrjfields the symbol term is replaced with the offset from the start of the 691*a9fa9459SzrjGOT to the jump slot for the symbol. For a 32-bit pc-relative field 692*a9fa9459Szrjthe pc-relative offset to the jump slot from the current instruction 693*a9fa9459Szrjaddress is used. 694*a9fa9459Szrj@item @@plt 695*a9fa9459SzrjThe @@plt modifier can be used for 16-bit and 32-bit pc-relative immediate 696*a9fa9459Szrjfields. A procedure linkage table entry is generated for the symbol. 697*a9fa9459SzrjThe symbol term is replaced with the relative offset from the current 698*a9fa9459Szrjinstruction to the PLT entry for the symbol. 699*a9fa9459Szrj@item @@pltoff 700*a9fa9459SzrjThe @@pltoff modifier can be used for 16-bit immediate fields. The symbol 701*a9fa9459Szrjterm is replaced with the offset from the start of the PLT to the address 702*a9fa9459Szrjof the symbol. 703*a9fa9459Szrj@item @@gotntpoff 704*a9fa9459SzrjThe @@gotntpoff modifier can be used for displacement fields. The symbol 705*a9fa9459Szrjis added to the static TLS block and the negated offset to the symbol 706*a9fa9459Szrjin the static TLS block is added to the GOT. The symbol term is replaced 707*a9fa9459Szrjwith the offset to the GOT slot from the start of the GOT. 708*a9fa9459Szrj@item @@indntpoff 709*a9fa9459SzrjThe @@indntpoff modifier can be used for 32-bit pc-relative immediate 710*a9fa9459Szrjfields. The symbol is added to the static TLS block and the negated offset 711*a9fa9459Szrjto the symbol in the static TLS block is added to the GOT. The symbol term 712*a9fa9459Szrjis replaced with the pc-relative offset to the GOT slot from the current 713*a9fa9459Szrjinstruction address. 714*a9fa9459Szrj@end table 715*a9fa9459Szrj 716*a9fa9459SzrjFor more information about the thread local storage modifiers 717*a9fa9459Szrj@samp{gotntpoff} and @samp{indntpoff} see the ELF extension documentation 718*a9fa9459Szrj@samp{ELF Handling For Thread-Local Storage}. 719*a9fa9459Szrj 720*a9fa9459Szrj@node s390 Instruction Marker 721*a9fa9459Szrj@subsection Instruction Marker 722*a9fa9459Szrj@cindex instruction marker, s390 723*a9fa9459Szrj@cindex s390 instruction marker 724*a9fa9459Szrj 725*a9fa9459SzrjThe thread local storage instruction markers are used by the linker to 726*a9fa9459Szrjperform code optimization. 727*a9fa9459Szrj 728*a9fa9459Szrj@table @code 729*a9fa9459Szrj@item :tls_load 730*a9fa9459SzrjThe :tls_load marker is used to flag the load instruction in the initial 731*a9fa9459Szrjexec TLS model that retrieves the offset from the thread pointer to a 732*a9fa9459Szrjthread local storage variable from the GOT. 733*a9fa9459Szrj@item :tls_gdcall 734*a9fa9459SzrjThe :tls_gdcall marker is used to flag the branch-and-save instruction to 735*a9fa9459Szrjthe __tls_get_offset function in the global dynamic TLS model. 736*a9fa9459Szrj@item :tls_ldcall 737*a9fa9459SzrjThe :tls_ldcall marker is used to flag the branch-and-save instruction to 738*a9fa9459Szrjthe __tls_get_offset function in the local dynamic TLS model. 739*a9fa9459Szrj@end table 740*a9fa9459Szrj 741*a9fa9459SzrjFor more information about the thread local storage instruction marker 742*a9fa9459Szrjand the linker optimizations see the ELF extension documentation 743*a9fa9459Szrj@samp{ELF Handling For Thread-Local Storage}. 744*a9fa9459Szrj 745*a9fa9459Szrj@node s390 Literal Pool Entries 746*a9fa9459Szrj@subsection Literal Pool Entries 747*a9fa9459Szrj@cindex literal pool entries, s390 748*a9fa9459Szrj@cindex s390 literal pool entries 749*a9fa9459Szrj 750*a9fa9459SzrjA literal pool is a collection of values. To access the values a pointer 751*a9fa9459Szrjto the literal pool is loaded to a register, the literal pool register. 752*a9fa9459SzrjUsually, register %r13 is used as the literal pool register 753*a9fa9459Szrj(@ref{s390 Register}). Literal pool entries are created by adding the 754*a9fa9459Szrjsuffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an 755*a9fa9459Szrjinstruction operand. The expression is added to the literal pool and the 756*a9fa9459Szrjoperand is replaced with the offset to the literal in the literal pool. 757*a9fa9459Szrj 758*a9fa9459Szrj@table @code 759*a9fa9459Szrj@item :lit1 760*a9fa9459SzrjThe literal pool entry is created as an 8-bit value. An operand modifier 761*a9fa9459Szrjmust not be used for the original expression. 762*a9fa9459Szrj@item :lit2 763*a9fa9459SzrjThe literal pool entry is created as a 16 bit value. The operand modifier 764*a9fa9459Szrj@@got may be used in the original expression. The term @samp{x@@got:lit2} 765*a9fa9459Szrjwill put the got offset for the global symbol x to the literal pool as 766*a9fa9459Szrj16 bit value. 767*a9fa9459Szrj@item :lit4 768*a9fa9459SzrjThe literal pool entry is created as a 32-bit value. The operand modifier 769*a9fa9459Szrj@@got and @@plt may be used in the original expression. The term 770*a9fa9459Szrj@samp{x@@got:lit4} will put the got offset for the global symbol x to the 771*a9fa9459Szrjliteral pool as a 32-bit value. The term @samp{x@@plt:lit4} will put the 772*a9fa9459Szrjplt offset for the global symbol x to the literal pool as a 32-bit value. 773*a9fa9459Szrj@item :lit8 774*a9fa9459SzrjThe literal pool entry is created as a 64-bit value. The operand modifier 775*a9fa9459Szrj@@got and @@plt may be used in the original expression. The term 776*a9fa9459Szrj@samp{x@@got:lit8} will put the got offset for the global symbol x to the 777*a9fa9459Szrjliteral pool as a 64-bit value. The term @samp{x@@plt:lit8} will put the 778*a9fa9459Szrjplt offset for the global symbol x to the literal pool as a 64-bit value. 779*a9fa9459Szrj@end table 780*a9fa9459Szrj 781*a9fa9459SzrjThe assembler directive @samp{.ltorg} is used to emit all literal pool 782*a9fa9459Szrjentries to the current position. 783*a9fa9459Szrj 784*a9fa9459Szrj@node s390 Directives 785*a9fa9459Szrj@section Assembler Directives 786*a9fa9459Szrj 787*a9fa9459Szrj@code{@value{AS}} for s390 supports all of the standard ELF 788*a9fa9459Szrjassembler directives as outlined in the main part of this document. 789*a9fa9459SzrjSome directives have been extended and there are some additional 790*a9fa9459Szrjdirectives, which are only available for the s390 @code{@value{AS}}. 791*a9fa9459Szrj 792*a9fa9459Szrj@table @code 793*a9fa9459Szrj@cindex @code{.insn} directive, s390 794*a9fa9459Szrj@item .insn 795*a9fa9459SzrjThis directive permits the numeric representation of an instructions 796*a9fa9459Szrjand makes the assembler insert the operands according to one of the 797*a9fa9459Szrjinstructions formats for @samp{.insn} (@ref{s390 Formats}). 798*a9fa9459SzrjFor example, the instruction @samp{l %r1,24(%r15)} could be written as 799*a9fa9459Szrj@samp{.insn rx,0x58000000,%r1,24(%r15)}. 800*a9fa9459Szrj@cindex @code{.short} directive, s390 801*a9fa9459Szrj@cindex @code{.long} directive, s390 802*a9fa9459Szrj@cindex @code{.quad} directive, s390 803*a9fa9459Szrj@item .short 804*a9fa9459Szrj@itemx .long 805*a9fa9459Szrj@itemx .quad 806*a9fa9459SzrjThis directive places one or more 16-bit (.short), 32-bit (.long), or 807*a9fa9459Szrj64-bit (.quad) values into the current section. If an ELF or TLS modifier 808*a9fa9459Szrjis used only the following expressions are allowed: 809*a9fa9459Szrj@samp{symbol@@modifier + constant}, 810*a9fa9459Szrj@samp{symbol@@modifier + label + constant}, and 811*a9fa9459Szrj@samp{symbol@@modifier - label + constant}. 812*a9fa9459SzrjThe following modifiers are available: 813*a9fa9459Szrj@table @code 814*a9fa9459Szrj@item @@got 815*a9fa9459Szrj@itemx @@got12 816*a9fa9459SzrjThe @@got modifier can be used for .short, .long and .quad. The @@got12 817*a9fa9459Szrjmodifier is synonym to @@got. The symbol is added to the GOT. The symbol 818*a9fa9459Szrjterm is replaced with offset from the start of the GOT to the GOT slot for 819*a9fa9459Szrjthe symbol. 820*a9fa9459Szrj@item @@gotoff 821*a9fa9459SzrjThe @@gotoff modifier can be used for .short, .long and .quad. The symbol 822*a9fa9459Szrjterm is replaced with the offset from the start of the GOT to the address 823*a9fa9459Szrjof the symbol. 824*a9fa9459Szrj@item @@gotplt 825*a9fa9459SzrjThe @@gotplt modifier can be used for .long and .quad. A procedure linkage 826*a9fa9459Szrjtable entry is generated for the symbol and a jump slot for the symbol 827*a9fa9459Szrjis added to the GOT. The symbol term is replaced with the offset from the 828*a9fa9459Szrjstart of the GOT to the jump slot for the symbol. 829*a9fa9459Szrj@item @@plt 830*a9fa9459SzrjThe @@plt modifier can be used for .long and .quad. A procedure linkage 831*a9fa9459Szrjtable entry us generated for the symbol. The symbol term is replaced with 832*a9fa9459Szrjthe address of the PLT entry for the symbol. 833*a9fa9459Szrj@item @@pltoff 834*a9fa9459SzrjThe @@pltoff modifier can be used for .short, .long and .quad. The symbol 835*a9fa9459Szrjterm is replaced with the offset from the start of the PLT to the address 836*a9fa9459Szrjof the symbol. 837*a9fa9459Szrj@item @@tlsgd 838*a9fa9459Szrj@itemx @@tlsldm 839*a9fa9459SzrjThe @@tlsgd and @@tlsldm modifier can be used for .long and .quad. A 840*a9fa9459Szrjtls_index structure for the symbol is added to the GOT. The symbol term is 841*a9fa9459Szrjreplaced with the offset from the start of the GOT to the tls_index structure. 842*a9fa9459Szrj@item @@gotntpoff 843*a9fa9459Szrj@itemx @@indntpoff 844*a9fa9459SzrjThe @@gotntpoff and @@indntpoff modifier can be used for .long and .quad. 845*a9fa9459SzrjThe symbol is added to the static TLS block and the negated offset to the 846*a9fa9459Szrjsymbol in the static TLS block is added to the GOT. For @@gotntpoff the 847*a9fa9459Szrjsymbol term is replaced with the offset from the start of the GOT to the 848*a9fa9459SzrjGOT slot, for @@indntpoff the symbol term is replaced with the address 849*a9fa9459Szrjof the GOT slot. 850*a9fa9459Szrj@item @@dtpoff 851*a9fa9459SzrjThe @@dtpoff modifier can be used for .long and .quad. The symbol term 852*a9fa9459Szrjis replaced with the offset of the symbol relative to the start of the 853*a9fa9459SzrjTLS block it is contained in. 854*a9fa9459Szrj@item @@ntpoff 855*a9fa9459SzrjThe @@ntpoff modifier can be used for .long and .quad. The symbol term 856*a9fa9459Szrjis replaced with the offset of the symbol relative to the TCB pointer. 857*a9fa9459Szrj@end table 858*a9fa9459Szrj 859*a9fa9459SzrjFor more information about the thread local storage modifiers see the 860*a9fa9459SzrjELF extension documentation @samp{ELF Handling For Thread-Local Storage}. 861*a9fa9459Szrj 862*a9fa9459Szrj@cindex @code{.ltorg} directive, s390 863*a9fa9459Szrj@item .ltorg 864*a9fa9459SzrjThis directive causes the current contents of the literal pool to be 865*a9fa9459Szrjdumped to the current location (@ref{s390 Literal Pool Entries}). 866*a9fa9459Szrj 867*a9fa9459Szrj@cindex @code{.machine} directive, s390 868*a9fa9459Szrj@item .machine @var{STRING}[+@var{EXTENSION}]@dots{} 869*a9fa9459Szrj 870*a9fa9459SzrjThis directive allows changing the machine for which code is 871*a9fa9459Szrjgenerated. @code{string} may be any of the @code{-march=} 872*a9fa9459Szrjselection options, or @code{push}, or @code{pop}. @code{.machine 873*a9fa9459Szrjpush} saves the currently selected cpu, which may be restored with 874*a9fa9459Szrj@code{.machine pop}. Be aware that the cpu string has to be put 875*a9fa9459Szrjinto double quotes in case it contains characters not appropriate 876*a9fa9459Szrjfor identifiers. So you have to write @code{"z9-109"} instead of 877*a9fa9459Szrjjust @code{z9-109}. Extensions can be specified after the cpu 878*a9fa9459Szrjname, separated by plus charaters. Valid extensions are: 879*a9fa9459Szrj@code{htm}, 880*a9fa9459Szrj@code{nohtm}, 881*a9fa9459Szrj@code{vx}, 882*a9fa9459Szrj@code{novx}. 883*a9fa9459SzrjThey extend the basic instruction set with features from a higher 884*a9fa9459Szrjcpu level, or remove support for a feature from the given cpu 885*a9fa9459Szrjlevel. 886*a9fa9459Szrj 887*a9fa9459SzrjExample: @code{z13+nohtm} allows all instructions of the z13 cpu 888*a9fa9459Szrjexcept instructions from the HTM facility. 889*a9fa9459Szrj 890*a9fa9459Szrj@cindex @code{.machinemode} directive, s390 891*a9fa9459Szrj@item .machinemode string 892*a9fa9459SzrjThis directive allows to change the architecture mode for which code 893*a9fa9459Szrjis being generated. @code{string} may be @code{esa}, @code{zarch}, 894*a9fa9459Szrj@code{zarch_nohighgprs}, @code{push}, or @code{pop}. 895*a9fa9459Szrj@code{.machinemode zarch_nohighgprs} can be used to prevent the 896*a9fa9459Szrj@code{highgprs} flag from being set in the ELF header of the output 897*a9fa9459Szrjfile. This is useful in situations where the code is gated with a 898*a9fa9459Szrjruntime check which makes sure that the code is only executed on 899*a9fa9459Szrjkernels providing the @code{highgprs} feature. 900*a9fa9459Szrj@code{.machinemode push} saves the currently selected mode, which may 901*a9fa9459Szrjbe restored with @code{.machinemode pop}. 902*a9fa9459Szrj@end table 903*a9fa9459Szrj 904*a9fa9459Szrj@node s390 Floating Point 905*a9fa9459Szrj@section Floating Point 906*a9fa9459Szrj@cindex floating point, s390 907*a9fa9459Szrj@cindex s390 floating point 908*a9fa9459Szrj 909*a9fa9459SzrjThe assembler recognizes both the @sc{ieee} floating-point instruction and 910*a9fa9459Szrjthe hexadecimal floating-point instructions. The floating-point constructors 911*a9fa9459Szrj@samp{.float}, @samp{.single}, and @samp{.double} always emit the 912*a9fa9459Szrj@sc{ieee} format. To assemble hexadecimal floating-point constants the 913*a9fa9459Szrj@samp{.long} and @samp{.quad} directives must be used. 914