1*a9fa9459Szrj@c Copyright (C) 1997-2016 Free Software Foundation, Inc. 2*a9fa9459Szrj@c This is part of the GAS manual. 3*a9fa9459Szrj@c For copying conditions, see the file as.texinfo. 4*a9fa9459Szrj 5*a9fa9459Szrj@node V850-Dependent 6*a9fa9459Szrj@chapter v850 Dependent Features 7*a9fa9459Szrj 8*a9fa9459Szrj@cindex V850 support 9*a9fa9459Szrj@menu 10*a9fa9459Szrj* V850 Options:: Options 11*a9fa9459Szrj* V850 Syntax:: Syntax 12*a9fa9459Szrj* V850 Floating Point:: Floating Point 13*a9fa9459Szrj* V850 Directives:: V850 Machine Directives 14*a9fa9459Szrj* V850 Opcodes:: Opcodes 15*a9fa9459Szrj@end menu 16*a9fa9459Szrj 17*a9fa9459Szrj@node V850 Options 18*a9fa9459Szrj@section Options 19*a9fa9459Szrj@cindex V850 options (none) 20*a9fa9459Szrj@cindex options for V850 (none) 21*a9fa9459Szrj@code{@value{AS}} supports the following additional command-line options 22*a9fa9459Szrjfor the V850 processor family: 23*a9fa9459Szrj 24*a9fa9459Szrj@cindex command line options, V850 25*a9fa9459Szrj@cindex V850 command line options 26*a9fa9459Szrj@table @code 27*a9fa9459Szrj 28*a9fa9459Szrj@cindex @code{-wsigned_overflow} command line option, V850 29*a9fa9459Szrj@item -wsigned_overflow 30*a9fa9459SzrjCauses warnings to be produced when signed immediate values overflow the 31*a9fa9459Szrjspace available for then within their opcodes. By default this option 32*a9fa9459Szrjis disabled as it is possible to receive spurious warnings due to using 33*a9fa9459Szrjexact bit patterns as immediate constants. 34*a9fa9459Szrj 35*a9fa9459Szrj@cindex @code{-wunsigned_overflow} command line option, V850 36*a9fa9459Szrj@item -wunsigned_overflow 37*a9fa9459SzrjCauses warnings to be produced when unsigned immediate values overflow 38*a9fa9459Szrjthe space available for then within their opcodes. By default this 39*a9fa9459Szrjoption is disabled as it is possible to receive spurious warnings due to 40*a9fa9459Szrjusing exact bit patterns as immediate constants. 41*a9fa9459Szrj 42*a9fa9459Szrj@cindex @code{-mv850} command line option, V850 43*a9fa9459Szrj@item -mv850 44*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 45*a9fa9459Szrjthe V850 processor. This allows the linker to detect attempts to link 46*a9fa9459Szrjsuch code with code assembled for other processors. 47*a9fa9459Szrj 48*a9fa9459Szrj@cindex @code{-mv850e} command line option, V850 49*a9fa9459Szrj@item -mv850e 50*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 51*a9fa9459Szrjthe V850E processor. This allows the linker to detect attempts to link 52*a9fa9459Szrjsuch code with code assembled for other processors. 53*a9fa9459Szrj 54*a9fa9459Szrj@cindex @code{-mv850e1} command line option, V850 55*a9fa9459Szrj@item -mv850e1 56*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 57*a9fa9459Szrjthe V850E1 processor. This allows the linker to detect attempts to link 58*a9fa9459Szrjsuch code with code assembled for other processors. 59*a9fa9459Szrj 60*a9fa9459Szrj@cindex @code{-mv850any} command line option, V850 61*a9fa9459Szrj@item -mv850any 62*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 63*a9fa9459Szrjthe V850 processor but support instructions that are specific to the 64*a9fa9459Szrjextended variants of the process. This allows the production of 65*a9fa9459Szrjbinaries that contain target specific code, but which are also intended 66*a9fa9459Szrjto be used in a generic fashion. For example libgcc.a contains generic 67*a9fa9459Szrjroutines used by the code produced by GCC for all versions of the v850 68*a9fa9459Szrjarchitecture, together with support routines only used by the V850E 69*a9fa9459Szrjarchitecture. 70*a9fa9459Szrj 71*a9fa9459Szrj@cindex @code{-mv850e2} command line option, V850 72*a9fa9459Szrj@item -mv850e2 73*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 74*a9fa9459Szrjthe V850E2 processor. This allows the linker to detect attempts to link 75*a9fa9459Szrjsuch code with code assembled for other processors. 76*a9fa9459Szrj 77*a9fa9459Szrj@cindex @code{-mv850e2v3} command line option, V850 78*a9fa9459Szrj@item -mv850e2v3 79*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 80*a9fa9459Szrjthe V850E2V3 processor. This allows the linker to detect attempts to link 81*a9fa9459Szrjsuch code with code assembled for other processors. 82*a9fa9459Szrj 83*a9fa9459Szrj@cindex @code{-mv850e2v4} command line option, V850 84*a9fa9459Szrj@item -mv850e2v4 85*a9fa9459SzrjThis is an alias for @option{-mv850e3v5}. 86*a9fa9459Szrj 87*a9fa9459Szrj@cindex @code{-mv850e3v5} command line option, V850 88*a9fa9459Szrj@item -mv850e3v5 89*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 90*a9fa9459Szrjthe V850E3V5 processor. This allows the linker to detect attempts to link 91*a9fa9459Szrjsuch code with code assembled for other processors. 92*a9fa9459Szrj 93*a9fa9459Szrj@cindex @code{-mrelax} command line option, V850 94*a9fa9459Szrj@item -mrelax 95*a9fa9459SzrjEnables relaxation. This allows the .longcall and .longjump pseudo 96*a9fa9459Szrjops to be used in the assembler source code. These ops label sections 97*a9fa9459Szrjof code which are either a long function call or a long branch. The 98*a9fa9459Szrjassembler will then flag these sections of code and the linker will 99*a9fa9459Szrjattempt to relax them. 100*a9fa9459Szrj 101*a9fa9459Szrj@cindex @code{-mgcc-abi} command line option, V850 102*a9fa9459Szrj@item -mgcc-abi 103*a9fa9459SzrjMarks the generated object file as supporting the old GCC ABI. 104*a9fa9459Szrj 105*a9fa9459Szrj@cindex @code{-mrh850-abi} command line option, V850 106*a9fa9459Szrj@item -mrh850-abi 107*a9fa9459SzrjMarks the generated object file as supporting the RH850 ABI. This is 108*a9fa9459Szrjthe default. 109*a9fa9459Szrj 110*a9fa9459Szrj@cindex @code{-m8byte-align} command line option, V850 111*a9fa9459Szrj@item -m8byte-align 112*a9fa9459SzrjMarks the generated object file as supporting a maximum 64-bits of 113*a9fa9459Szrjalignment for variables defined in the source code. 114*a9fa9459Szrj 115*a9fa9459Szrj@cindex @code{-m4byte-align} command line option, V850 116*a9fa9459Szrj@item -m4byte-align 117*a9fa9459SzrjMarks the generated object file as supporting a maximum 32-bits of 118*a9fa9459Szrjalignment for variables defined in the source code. This is the 119*a9fa9459Szrjdefault. 120*a9fa9459Szrj 121*a9fa9459Szrj@cindex @code{-msoft-float} command line option, V850 122*a9fa9459Szrj@item -msoft-float 123*a9fa9459SzrjMarks the generated object file as not using any floating point 124*a9fa9459Szrjinstructions - and hence can be linked with other V850 binaries 125*a9fa9459Szrjthat do or do not use floating point. This is the default for 126*a9fa9459Szrjbinaries for architectures earlier than the @code{e2v3}. 127*a9fa9459Szrj 128*a9fa9459Szrj@cindex @code{-mhard-float} command line option, V850 129*a9fa9459Szrj@item -mhard-float 130*a9fa9459SzrjMarks the generated object file as one that uses floating point 131*a9fa9459Szrjinstructions - and hence can only be linked with other V850 binaries 132*a9fa9459Szrjthat use the same kind of floating point instructions, or with 133*a9fa9459Szrjbinaries that do not use floating point at all. This is the default 134*a9fa9459Szrjfor binaries the @code{e2v3} and later architectures. 135*a9fa9459Szrj 136*a9fa9459Szrj@end table 137*a9fa9459Szrj 138*a9fa9459Szrj@node V850 Syntax 139*a9fa9459Szrj@section Syntax 140*a9fa9459Szrj@menu 141*a9fa9459Szrj* V850-Chars:: Special Characters 142*a9fa9459Szrj* V850-Regs:: Register Names 143*a9fa9459Szrj@end menu 144*a9fa9459Szrj 145*a9fa9459Szrj@node V850-Chars 146*a9fa9459Szrj@subsection Special Characters 147*a9fa9459Szrj 148*a9fa9459Szrj@cindex line comment character, V850 149*a9fa9459Szrj@cindex V850 line comment character 150*a9fa9459Szrj@samp{#} is the line comment character. If a @samp{#} appears as the 151*a9fa9459Szrjfirst character of a line, the whole line is treated as a comment, but 152*a9fa9459Szrjin this case the line can also be a logical line number directive 153*a9fa9459Szrj(@pxref{Comments}) or a preprocessor control command 154*a9fa9459Szrj(@pxref{Preprocessing}). 155*a9fa9459Szrj 156*a9fa9459SzrjTwo dashes (@samp{--}) can also be used to start a line comment. 157*a9fa9459Szrj 158*a9fa9459Szrj@cindex line separator, V850 159*a9fa9459Szrj@cindex statement separator, V850 160*a9fa9459Szrj@cindex V850 line separator 161*a9fa9459Szrj 162*a9fa9459SzrjThe @samp{;} character can be used to separate statements on the same 163*a9fa9459Szrjline. 164*a9fa9459Szrj 165*a9fa9459Szrj@node V850-Regs 166*a9fa9459Szrj@subsection Register Names 167*a9fa9459Szrj 168*a9fa9459Szrj@cindex V850 register names 169*a9fa9459Szrj@cindex register names, V850 170*a9fa9459Szrj@code{@value{AS}} supports the following names for registers: 171*a9fa9459Szrj@table @code 172*a9fa9459Szrj@cindex @code{zero} register, V850 173*a9fa9459Szrj@item general register 0 174*a9fa9459Szrjr0, zero 175*a9fa9459Szrj@item general register 1 176*a9fa9459Szrjr1 177*a9fa9459Szrj@item general register 2 178*a9fa9459Szrjr2, hp 179*a9fa9459Szrj@cindex @code{sp} register, V850 180*a9fa9459Szrj@item general register 3 181*a9fa9459Szrjr3, sp 182*a9fa9459Szrj@cindex @code{gp} register, V850 183*a9fa9459Szrj@item general register 4 184*a9fa9459Szrjr4, gp 185*a9fa9459Szrj@cindex @code{tp} register, V850 186*a9fa9459Szrj@item general register 5 187*a9fa9459Szrjr5, tp 188*a9fa9459Szrj@item general register 6 189*a9fa9459Szrjr6 190*a9fa9459Szrj@item general register 7 191*a9fa9459Szrjr7 192*a9fa9459Szrj@item general register 8 193*a9fa9459Szrjr8 194*a9fa9459Szrj@item general register 9 195*a9fa9459Szrjr9 196*a9fa9459Szrj@item general register 10 197*a9fa9459Szrjr10 198*a9fa9459Szrj@item general register 11 199*a9fa9459Szrjr11 200*a9fa9459Szrj@item general register 12 201*a9fa9459Szrjr12 202*a9fa9459Szrj@item general register 13 203*a9fa9459Szrjr13 204*a9fa9459Szrj@item general register 14 205*a9fa9459Szrjr14 206*a9fa9459Szrj@item general register 15 207*a9fa9459Szrjr15 208*a9fa9459Szrj@item general register 16 209*a9fa9459Szrjr16 210*a9fa9459Szrj@item general register 17 211*a9fa9459Szrjr17 212*a9fa9459Szrj@item general register 18 213*a9fa9459Szrjr18 214*a9fa9459Szrj@item general register 19 215*a9fa9459Szrjr19 216*a9fa9459Szrj@item general register 20 217*a9fa9459Szrjr20 218*a9fa9459Szrj@item general register 21 219*a9fa9459Szrjr21 220*a9fa9459Szrj@item general register 22 221*a9fa9459Szrjr22 222*a9fa9459Szrj@item general register 23 223*a9fa9459Szrjr23 224*a9fa9459Szrj@item general register 24 225*a9fa9459Szrjr24 226*a9fa9459Szrj@item general register 25 227*a9fa9459Szrjr25 228*a9fa9459Szrj@item general register 26 229*a9fa9459Szrjr26 230*a9fa9459Szrj@item general register 27 231*a9fa9459Szrjr27 232*a9fa9459Szrj@item general register 28 233*a9fa9459Szrjr28 234*a9fa9459Szrj@item general register 29 235*a9fa9459Szrjr29 236*a9fa9459Szrj@cindex @code{ep} register, V850 237*a9fa9459Szrj@item general register 30 238*a9fa9459Szrjr30, ep 239*a9fa9459Szrj@cindex @code{lp} register, V850 240*a9fa9459Szrj@item general register 31 241*a9fa9459Szrjr31, lp 242*a9fa9459Szrj@cindex @code{eipc} register, V850 243*a9fa9459Szrj@item system register 0 244*a9fa9459Szrjeipc 245*a9fa9459Szrj@cindex @code{eipsw} register, V850 246*a9fa9459Szrj@item system register 1 247*a9fa9459Szrjeipsw 248*a9fa9459Szrj@cindex @code{fepc} register, V850 249*a9fa9459Szrj@item system register 2 250*a9fa9459Szrjfepc 251*a9fa9459Szrj@cindex @code{fepsw} register, V850 252*a9fa9459Szrj@item system register 3 253*a9fa9459Szrjfepsw 254*a9fa9459Szrj@cindex @code{ecr} register, V850 255*a9fa9459Szrj@item system register 4 256*a9fa9459Szrjecr 257*a9fa9459Szrj@cindex @code{psw} register, V850 258*a9fa9459Szrj@item system register 5 259*a9fa9459Szrjpsw 260*a9fa9459Szrj@cindex @code{ctpc} register, V850 261*a9fa9459Szrj@item system register 16 262*a9fa9459Szrjctpc 263*a9fa9459Szrj@cindex @code{ctpsw} register, V850 264*a9fa9459Szrj@item system register 17 265*a9fa9459Szrjctpsw 266*a9fa9459Szrj@cindex @code{dbpc} register, V850 267*a9fa9459Szrj@item system register 18 268*a9fa9459Szrjdbpc 269*a9fa9459Szrj@cindex @code{dbpsw} register, V850 270*a9fa9459Szrj@item system register 19 271*a9fa9459Szrjdbpsw 272*a9fa9459Szrj@cindex @code{ctbp} register, V850 273*a9fa9459Szrj@item system register 20 274*a9fa9459Szrjctbp 275*a9fa9459Szrj@end table 276*a9fa9459Szrj 277*a9fa9459Szrj@node V850 Floating Point 278*a9fa9459Szrj@section Floating Point 279*a9fa9459Szrj 280*a9fa9459Szrj@cindex floating point, V850 (@sc{ieee}) 281*a9fa9459Szrj@cindex V850 floating point (@sc{ieee}) 282*a9fa9459SzrjThe V850 family uses @sc{ieee} floating-point numbers. 283*a9fa9459Szrj 284*a9fa9459Szrj@node V850 Directives 285*a9fa9459Szrj@section V850 Machine Directives 286*a9fa9459Szrj 287*a9fa9459Szrj@cindex machine directives, V850 288*a9fa9459Szrj@cindex V850 machine directives 289*a9fa9459Szrj@table @code 290*a9fa9459Szrj@cindex @code{offset} directive, V850 291*a9fa9459Szrj@item .offset @var{<expression>} 292*a9fa9459SzrjMoves the offset into the current section to the specified amount. 293*a9fa9459Szrj 294*a9fa9459Szrj@cindex @code{section} directive, V850 295*a9fa9459Szrj@item .section "name", <type> 296*a9fa9459SzrjThis is an extension to the standard .section directive. It sets the 297*a9fa9459Szrjcurrent section to be <type> and creates an alias for this section 298*a9fa9459Szrjcalled "name". 299*a9fa9459Szrj 300*a9fa9459Szrj@cindex @code{.v850} directive, V850 301*a9fa9459Szrj@item .v850 302*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 303*a9fa9459Szrjthe V850 processor. This allows the linker to detect attempts to link 304*a9fa9459Szrjsuch code with code assembled for other processors. 305*a9fa9459Szrj 306*a9fa9459Szrj@cindex @code{.v850e} directive, V850 307*a9fa9459Szrj@item .v850e 308*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 309*a9fa9459Szrjthe V850E processor. This allows the linker to detect attempts to link 310*a9fa9459Szrjsuch code with code assembled for other processors. 311*a9fa9459Szrj 312*a9fa9459Szrj@cindex @code{.v850e1} directive, V850 313*a9fa9459Szrj@item .v850e1 314*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 315*a9fa9459Szrjthe V850E1 processor. This allows the linker to detect attempts to link 316*a9fa9459Szrjsuch code with code assembled for other processors. 317*a9fa9459Szrj 318*a9fa9459Szrj@cindex @code{.v850e2} directive, V850 319*a9fa9459Szrj@item .v850e2 320*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 321*a9fa9459Szrjthe V850E2 processor. This allows the linker to detect attempts to link 322*a9fa9459Szrjsuch code with code assembled for other processors. 323*a9fa9459Szrj 324*a9fa9459Szrj@cindex @code{.v850e2v3} directive, V850 325*a9fa9459Szrj@item .v850e2v3 326*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 327*a9fa9459Szrjthe V850E2V3 processor. This allows the linker to detect attempts to link 328*a9fa9459Szrjsuch code with code assembled for other processors. 329*a9fa9459Szrj 330*a9fa9459Szrj@cindex @code{.v850e2v4} directive, V850 331*a9fa9459Szrj@item .v850e2v4 332*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 333*a9fa9459Szrjthe V850E3V5 processor. This allows the linker to detect attempts to link 334*a9fa9459Szrjsuch code with code assembled for other processors. 335*a9fa9459Szrj 336*a9fa9459Szrj@cindex @code{.v850e3v5} directive, V850 337*a9fa9459Szrj@item .v850e3v5 338*a9fa9459SzrjSpecifies that the assembled code should be marked as being targeted at 339*a9fa9459Szrjthe V850E3V5 processor. This allows the linker to detect attempts to link 340*a9fa9459Szrjsuch code with code assembled for other processors. 341*a9fa9459Szrj 342*a9fa9459Szrj@end table 343*a9fa9459Szrj 344*a9fa9459Szrj@node V850 Opcodes 345*a9fa9459Szrj@section Opcodes 346*a9fa9459Szrj 347*a9fa9459Szrj@cindex V850 opcodes 348*a9fa9459Szrj@cindex opcodes for V850 349*a9fa9459Szrj@code{@value{AS}} implements all the standard V850 opcodes. 350*a9fa9459Szrj 351*a9fa9459Szrj@code{@value{AS}} also implements the following pseudo ops: 352*a9fa9459Szrj 353*a9fa9459Szrj@table @code 354*a9fa9459Szrj 355*a9fa9459Szrj@cindex @code{hi0} pseudo-op, V850 356*a9fa9459Szrj@item hi0() 357*a9fa9459SzrjComputes the higher 16 bits of the given expression and stores it into 358*a9fa9459Szrjthe immediate operand field of the given instruction. For example: 359*a9fa9459Szrj 360*a9fa9459Szrj @samp{mulhi hi0(here - there), r5, r6} 361*a9fa9459Szrj 362*a9fa9459Szrjcomputes the difference between the address of labels 'here' and 363*a9fa9459Szrj'there', takes the upper 16 bits of this difference, shifts it down 16 364*a9fa9459Szrjbits and then multiplies it by the lower 16 bits in register 5, putting 365*a9fa9459Szrjthe result into register 6. 366*a9fa9459Szrj 367*a9fa9459Szrj@cindex @code{lo} pseudo-op, V850 368*a9fa9459Szrj@item lo() 369*a9fa9459SzrjComputes the lower 16 bits of the given expression and stores it into 370*a9fa9459Szrjthe immediate operand field of the given instruction. For example: 371*a9fa9459Szrj 372*a9fa9459Szrj @samp{addi lo(here - there), r5, r6} 373*a9fa9459Szrj 374*a9fa9459Szrjcomputes the difference between the address of labels 'here' and 375*a9fa9459Szrj'there', takes the lower 16 bits of this difference and adds it to 376*a9fa9459Szrjregister 5, putting the result into register 6. 377*a9fa9459Szrj 378*a9fa9459Szrj@cindex @code{hi} pseudo-op, V850 379*a9fa9459Szrj@item hi() 380*a9fa9459SzrjComputes the higher 16 bits of the given expression and then adds the 381*a9fa9459Szrjvalue of the most significant bit of the lower 16 bits of the expression 382*a9fa9459Szrjand stores the result into the immediate operand field of the given 383*a9fa9459Szrjinstruction. For example the following code can be used to compute the 384*a9fa9459Szrjaddress of the label 'here' and store it into register 6: 385*a9fa9459Szrj 386*a9fa9459Szrj @samp{movhi hi(here), r0, r6} 387*a9fa9459Szrj @samp{movea lo(here), r6, r6} 388*a9fa9459Szrj 389*a9fa9459SzrjThe reason for this special behaviour is that movea performs a sign 390*a9fa9459Szrjextension on its immediate operand. So for example if the address of 391*a9fa9459Szrj'here' was 0xFFFFFFFF then without the special behaviour of the hi() 392*a9fa9459Szrjpseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the 393*a9fa9459Szrjmovea instruction would takes its immediate operand, 0xFFFF, sign extend 394*a9fa9459Szrjit to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF 395*a9fa9459Szrjwhich is wrong (the fifth nibble is E). With the hi() pseudo op adding 396*a9fa9459Szrjin the top bit of the lo() pseudo op, the movhi instruction actually 397*a9fa9459Szrjstores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction 398*a9fa9459Szrjstores 0xFFFFFFFF into r6 - the right value. 399*a9fa9459Szrj 400*a9fa9459Szrj@cindex @code{hilo} pseudo-op, V850 401*a9fa9459Szrj@item hilo() 402*a9fa9459SzrjComputes the 32 bit value of the given expression and stores it into 403*a9fa9459Szrjthe immediate operand field of the given instruction (which must be a 404*a9fa9459Szrjmov instruction). For example: 405*a9fa9459Szrj 406*a9fa9459Szrj @samp{mov hilo(here), r6} 407*a9fa9459Szrj 408*a9fa9459Szrjcomputes the absolute address of label 'here' and puts the result into 409*a9fa9459Szrjregister 6. 410*a9fa9459Szrj 411*a9fa9459Szrj@cindex @code{sdaoff} pseudo-op, V850 412*a9fa9459Szrj@item sdaoff() 413*a9fa9459SzrjComputes the offset of the named variable from the start of the Small 414*a9fa9459SzrjData Area (whoes address is held in register 4, the GP register) and 415*a9fa9459Szrjstores the result as a 16 bit signed value in the immediate operand 416*a9fa9459Szrjfield of the given instruction. For example: 417*a9fa9459Szrj 418*a9fa9459Szrj @samp{ld.w sdaoff(_a_variable)[gp],r6} 419*a9fa9459Szrj 420*a9fa9459Szrjloads the contents of the location pointed to by the label '_a_variable' 421*a9fa9459Szrjinto register 6, provided that the label is located somewhere within +/- 422*a9fa9459Szrj32K of the address held in the GP register. [Note the linker assumes 423*a9fa9459Szrjthat the GP register contains a fixed address set to the address of the 424*a9fa9459Szrjlabel called '__gp'. This can either be set up automatically by the 425*a9fa9459Szrjlinker, or specifically set by using the @samp{--defsym __gp=<value>} 426*a9fa9459Szrjcommand line option]. 427*a9fa9459Szrj 428*a9fa9459Szrj@cindex @code{tdaoff} pseudo-op, V850 429*a9fa9459Szrj@item tdaoff() 430*a9fa9459SzrjComputes the offset of the named variable from the start of the Tiny 431*a9fa9459SzrjData Area (whoes address is held in register 30, the EP register) and 432*a9fa9459Szrjstores the result as a 4,5, 7 or 8 bit unsigned value in the immediate 433*a9fa9459Szrjoperand field of the given instruction. For example: 434*a9fa9459Szrj 435*a9fa9459Szrj @samp{sld.w tdaoff(_a_variable)[ep],r6} 436*a9fa9459Szrj 437*a9fa9459Szrjloads the contents of the location pointed to by the label '_a_variable' 438*a9fa9459Szrjinto register 6, provided that the label is located somewhere within +256 439*a9fa9459Szrjbytes of the address held in the EP register. [Note the linker assumes 440*a9fa9459Szrjthat the EP register contains a fixed address set to the address of the 441*a9fa9459Szrjlabel called '__ep'. This can either be set up automatically by the 442*a9fa9459Szrjlinker, or specifically set by using the @samp{--defsym __ep=<value>} 443*a9fa9459Szrjcommand line option]. 444*a9fa9459Szrj 445*a9fa9459Szrj@cindex @code{zdaoff} pseudo-op, V850 446*a9fa9459Szrj@item zdaoff() 447*a9fa9459SzrjComputes the offset of the named variable from address 0 and stores the 448*a9fa9459Szrjresult as a 16 bit signed value in the immediate operand field of the 449*a9fa9459Szrjgiven instruction. For example: 450*a9fa9459Szrj 451*a9fa9459Szrj @samp{movea zdaoff(_a_variable),zero,r6} 452*a9fa9459Szrj 453*a9fa9459Szrjputs the address of the label '_a_variable' into register 6, assuming 454*a9fa9459Szrjthat the label is somewhere within the first 32K of memory. (Strictly 455*a9fa9459Szrjspeaking it also possible to access the last 32K of memory as well, as 456*a9fa9459Szrjthe offsets are signed). 457*a9fa9459Szrj 458*a9fa9459Szrj@cindex @code{ctoff} pseudo-op, V850 459*a9fa9459Szrj@item ctoff() 460*a9fa9459SzrjComputes the offset of the named variable from the start of the Call 461*a9fa9459SzrjTable Area (whoes address is helg in system register 20, the CTBP 462*a9fa9459Szrjregister) and stores the result a 6 or 16 bit unsigned value in the 463*a9fa9459Szrjimmediate field of then given instruction or piece of data. For 464*a9fa9459Szrjexample: 465*a9fa9459Szrj 466*a9fa9459Szrj @samp{callt ctoff(table_func1)} 467*a9fa9459Szrj 468*a9fa9459Szrjwill put the call the function whoes address is held in the call table 469*a9fa9459Szrjat the location labeled 'table_func1'. 470*a9fa9459Szrj 471*a9fa9459Szrj@cindex @code{longcall} pseudo-op, V850 472*a9fa9459Szrj@item .longcall @code{name} 473*a9fa9459SzrjIndicates that the following sequence of instructions is a long call 474*a9fa9459Szrjto function @code{name}. The linker will attempt to shorten this call 475*a9fa9459Szrjsequence if @code{name} is within a 22bit offset of the call. Only 476*a9fa9459Szrjvalid if the @code{-mrelax} command line switch has been enabled. 477*a9fa9459Szrj 478*a9fa9459Szrj@cindex @code{longjump} pseudo-op, V850 479*a9fa9459Szrj@item .longjump @code{name} 480*a9fa9459SzrjIndicates that the following sequence of instructions is a long jump 481*a9fa9459Szrjto label @code{name}. The linker will attempt to shorten this code 482*a9fa9459Szrjsequence if @code{name} is within a 22bit offset of the jump. Only 483*a9fa9459Szrjvalid if the @code{-mrelax} command line switch has been enabled. 484*a9fa9459Szrj 485*a9fa9459Szrj@end table 486*a9fa9459Szrj 487*a9fa9459Szrj 488*a9fa9459SzrjFor information on the V850 instruction set, see @cite{V850 489*a9fa9459SzrjFamily 32-/16-Bit single-Chip Microcontroller Architecture Manual} from NEC. 490*a9fa9459SzrjLtd. 491