1 /* Imagination Technologies Meta opcode table.
2    Copyright (C) 2013-2016 Free Software Foundation, Inc.
3    Contributed by Imagination Technologies Ltd.
4 
5    This file is part of GDB and GAS.
6 
7    GDB and GAS are free software; you can redistribute it and/or
8    modify it under the terms of the GNU General Public License as
9    published by the Free Software Foundation; either version 3, or (at
10    your option) any later version.
11 
12    GDB and GAS are distributed in the hope that it will be useful, but
13    WITHOUT ANY WARRANTY; without even the implied warranty of
14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15    General Public License for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with GDB or GAS; see the file COPYING3.  If not, write to the
19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20    MA 02110-1301, USA.  */
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 enum metag_unit
27 {
28   UNIT_CT,
29   UNIT_D0,
30   UNIT_D1,
31   UNIT_A0,
32   UNIT_A1,
33   UNIT_PC,
34   UNIT_RD,
35   UNIT_TR,
36   UNIT_TT,
37   UNIT_FX,
38   UNIT_DT,			/* DSP Template Table */
39   UNIT_ACC_D0,
40   UNIT_ACC_D1,
41   UNIT_RAM_D0,
42   UNIT_RAM_D1,
43 };
44 
45 typedef struct
46 {
47   const char *     name;
48   enum metag_unit  unit;
49   unsigned int     no;
50 } metag_reg;
51 
52 static const metag_reg metag_regtab[] =
53   {
54     { "TXENABLE",   UNIT_CT,  0 },
55     { "CT.0",       UNIT_CT,  0 },
56     { "TXMODE",     UNIT_CT,  1 },
57     { "CT.1",       UNIT_CT,  1 },
58     { "TXSTATUS",   UNIT_CT,  2 },
59     { "CT.2",       UNIT_CT,  2 },
60     { "TXRPT",      UNIT_CT,  3 },
61     { "CT.3",       UNIT_CT,  3 },
62     { "TXTIMER",    UNIT_CT,  4 },
63     { "CT.4",       UNIT_CT,  4 },
64     { "TXL1START",  UNIT_CT,  5 },
65     { "CT.5",       UNIT_CT,  5 },
66     { "TXL1END",    UNIT_CT,  6 },
67     { "CT.6",       UNIT_CT,  6 },
68     { "TXL1COUNT",  UNIT_CT,  7 },
69     { "CT.7",       UNIT_CT,  7 },
70     { "TXL2START",  UNIT_CT,  8 },
71     { "CT.8",       UNIT_CT,  8 },
72     { "TXL2END",    UNIT_CT,  9 },
73     { "CT.9",       UNIT_CT,  9 },
74     { "TXL2COUNT",  UNIT_CT, 10 },
75     { "CT.10",      UNIT_CT, 10 },
76     { "TXBPOBITS",  UNIT_CT, 11 },
77     { "CT.11",      UNIT_CT, 11 },
78     { "TXMRSIZE",   UNIT_CT, 12 },
79     { "CT.12",      UNIT_CT, 12 },
80     { "TXTIMERI",   UNIT_CT, 13 },
81     { "CT.13",      UNIT_CT, 13 },
82     { "TXDRCTRL",   UNIT_CT, 14 },
83     { "CT.14",      UNIT_CT, 14 },
84     { "TXDRSIZE",   UNIT_CT, 15 },
85     { "CT.15",      UNIT_CT, 15 },
86     { "TXCATCH0",   UNIT_CT, 16 },
87     { "CT.16",      UNIT_CT, 16 },
88     { "TXCATCH1",   UNIT_CT, 17 },
89     { "CT.17",      UNIT_CT, 17 },
90     { "TXCATCH2",   UNIT_CT, 18 },
91     { "CT.18",      UNIT_CT, 18 },
92     { "TXCATCH3",   UNIT_CT, 19 },
93     { "CT.19",      UNIT_CT, 19 },
94     { "TXDEFR",     UNIT_CT, 20 },
95     { "CT.20",      UNIT_CT, 20 },
96     { "TXCPRS",     UNIT_CT, 21 },
97     { "CT.21",      UNIT_CT, 21 },
98     { "TXCLKCTRL",  UNIT_CT, 22 },
99     { "CT.22",      UNIT_CT, 22 },
100     { "TXINTERN0",  UNIT_CT, 23 },
101     { "TXSTATE",    UNIT_CT, 23 },
102     { "CT.23",      UNIT_CT, 23 },
103     { "TXAMAREG0",  UNIT_CT, 24 },
104     { "CT.24",      UNIT_CT, 24 },
105     { "TXAMAREG1",  UNIT_CT, 25 },
106     { "CT.25",      UNIT_CT, 25 },
107     { "TXAMAREG2",  UNIT_CT, 26 },
108     { "CT.26",      UNIT_CT, 26 },
109     { "TXAMAREG3",  UNIT_CT, 27 },
110     { "CT.27",      UNIT_CT, 27 },
111     { "TXDIVTIME",  UNIT_CT, 28 },
112     { "CT.28",      UNIT_CT, 28 },
113     { "TXPRIVEXT",  UNIT_CT, 29 },
114     { "CT.29",      UNIT_CT, 29 },
115     { "TXTACTCYC",  UNIT_CT, 30 },
116     { "TXACTCYC",   UNIT_CT, 30 },
117     { "CT.30",      UNIT_CT, 30 },
118     { "TXIDLECYC",  UNIT_CT, 31 },
119     { "CT.31",      UNIT_CT, 31 },
120 
121     { "D0Re0",      UNIT_D0,  0 },
122     { "D0.0",       UNIT_D0,  0 },
123     { "D0Ar6",      UNIT_D0,  1 },
124     { "D0.1",       UNIT_D0,  1 },
125     { "D0Ar4",      UNIT_D0,  2 },
126     { "D0.2",       UNIT_D0,  2 },
127     { "D0Ar2",      UNIT_D0,  3 },
128     { "D0.3",       UNIT_D0,  3 },
129     { "D0FrT",      UNIT_D0,  4 },
130     { "D0.4",       UNIT_D0,  4 },
131     { "D0.5",       UNIT_D0,  5 },
132     { "D0.6",       UNIT_D0,  6 },
133     { "D0.7",       UNIT_D0,  7 },
134     { "D0.8",       UNIT_D0,  8 },
135     { "D0.9",       UNIT_D0,  9 },
136     { "D0.10",      UNIT_D0, 10 },
137     { "D0.11",      UNIT_D0, 11 },
138     { "D0.12",      UNIT_D0, 12 },
139     { "D0.13",      UNIT_D0, 13 },
140     { "D0.14",      UNIT_D0, 14 },
141     { "D0.15",      UNIT_D0, 15 },
142     { "D0.16",      UNIT_D0, 16 },
143     { "D0.17",      UNIT_D0, 17 },
144     { "D0.18",      UNIT_D0, 18 },
145     { "D0.19",      UNIT_D0, 19 },
146     { "D0.20",      UNIT_D0, 20 },
147     { "D0.21",      UNIT_D0, 21 },
148     { "D0.22",      UNIT_D0, 22 },
149     { "D0.23",      UNIT_D0, 23 },
150     { "D0.24",      UNIT_D0, 24 },
151     { "D0.25",      UNIT_D0, 25 },
152     { "D0.26",      UNIT_D0, 26 },
153     { "D0.27",      UNIT_D0, 27 },
154     { "D0.28",      UNIT_D0, 28 },
155     { "D0.29",      UNIT_D0, 29 },
156     { "D0.30",      UNIT_D0, 30 },
157     { "D0.31",      UNIT_D0, 31 },
158 
159     { "D1Re0",      UNIT_D1,  0 },
160     { "D1.0",       UNIT_D1,  0 },
161     { "D1Ar5",      UNIT_D1,  1 },
162     { "D1.1",       UNIT_D1,  1 },
163     { "D1Ar3",      UNIT_D1,  2 },
164     { "D1.2",       UNIT_D1,  2 },
165     { "D1Ar1",      UNIT_D1,  3 },
166     { "D1.3",       UNIT_D1,  3 },
167     { "D1RtP",      UNIT_D1,  4 },
168     { "D1.4",       UNIT_D1,  4 },
169     { "D1.5",       UNIT_D1,  5 },
170     { "D1.6",       UNIT_D1,  6 },
171     { "D1.7",       UNIT_D1,  7 },
172     { "D1.8",       UNIT_D1,  8 },
173     { "D1.9",       UNIT_D1,  9 },
174     { "D1.10",      UNIT_D1, 10 },
175     { "D1.11",      UNIT_D1, 11 },
176     { "D1.12",      UNIT_D1, 12 },
177     { "D1.13",      UNIT_D1, 13 },
178     { "D1.14",      UNIT_D1, 14 },
179     { "D1.15",      UNIT_D1, 15 },
180     { "D1.16",      UNIT_D1, 16 },
181     { "D1.17",      UNIT_D1, 17 },
182     { "D1.18",      UNIT_D1, 18 },
183     { "D1.19",      UNIT_D1, 19 },
184     { "D1.20",      UNIT_D1, 20 },
185     { "D1.21",      UNIT_D1, 21 },
186     { "D1.22",      UNIT_D1, 22 },
187     { "D1.23",      UNIT_D1, 23 },
188     { "D1.24",      UNIT_D1, 24 },
189     { "D1.25",      UNIT_D1, 25 },
190     { "D1.26",      UNIT_D1, 26 },
191     { "D1.27",      UNIT_D1, 27 },
192     { "D1.28",      UNIT_D1, 28 },
193     { "D1.29",      UNIT_D1, 29 },
194     { "D1.30",      UNIT_D1, 30 },
195     { "D1.31",      UNIT_D1, 31 },
196 
197     { "A0StP",      UNIT_A0,  0 },
198     { "A0.0",       UNIT_A0,  0 },
199     { "A0FrP",      UNIT_A0,  1 },
200     { "A0.1",       UNIT_A0,  1 },
201     { "A0.2",       UNIT_A0,  2 },
202     { "A0.3",       UNIT_A0,  3 },
203     { "A0.4",       UNIT_A0,  4 },
204     { "A0.5",       UNIT_A0,  5 },
205     { "A0.6",       UNIT_A0,  6 },
206     { "A0.7",       UNIT_A0,  7 },
207     { "A0.8",       UNIT_A0,  8 },
208     { "A0.9",       UNIT_A0,  9 },
209     { "A0.10",      UNIT_A0, 10 },
210     { "A0.11",      UNIT_A0, 11 },
211     { "A0.12",      UNIT_A0, 12 },
212     { "A0.13",      UNIT_A0, 13 },
213     { "A0.14",      UNIT_A0, 14 },
214     { "A0.15",      UNIT_A0, 15 },
215     { "CPC0",       UNIT_A0, 16 },
216 
217     { "A1GbP",      UNIT_A1,  0 },
218     { "A1.0",       UNIT_A1,  0 },
219     { "A1LbP",      UNIT_A1,  1 },
220     { "A1.1",       UNIT_A1,  1 },
221     { "A1.2",       UNIT_A1,  2 },
222     { "A1.3",       UNIT_A1,  3 },
223     { "A1.4",       UNIT_A1,  4 },
224     { "A1.5",       UNIT_A1,  5 },
225     { "A1.6",       UNIT_A1,  6 },
226     { "A1.7",       UNIT_A1,  7 },
227     { "A1.8",       UNIT_A1,  8 },
228     { "A1.9",       UNIT_A1,  9 },
229     { "A1.10",      UNIT_A1, 10 },
230     { "A1.11",      UNIT_A1, 11 },
231     { "A1.12",      UNIT_A1, 12 },
232     { "A1.13",      UNIT_A1, 13 },
233     { "A1.14",      UNIT_A1, 14 },
234     { "A1.15",      UNIT_A1, 15 },
235     { "CPC1",       UNIT_A1, 16 },
236 
237     { "PC",         UNIT_PC,  0 },
238     { "PCX",        UNIT_PC,  1 },
239 
240     { "RD",         UNIT_RD,  0 },
241     { "RA",         UNIT_RD, 16 },
242     { "RD",         UNIT_RD, 16 },
243     { "RAPF",       UNIT_RD, 17 },
244     { "RAM8X32",    UNIT_RD, 22 },
245     { "RAM8X",      UNIT_RD, 23 },
246     { "RABZ",       UNIT_RD, 24 },
247     { "RAWZ",       UNIT_RD, 25 },
248     { "RADZ",       UNIT_RD, 26 },
249     { "RABX",       UNIT_RD, 28 },
250     { "RAWX",       UNIT_RD, 29 },
251     { "RADX",       UNIT_RD, 30 },
252     { "RAMX",       UNIT_RD, 31 },
253     { "RAM16X",     UNIT_RD, 31 },
254 
255     { "TXSTAT",     UNIT_TR,  0 },
256     { "TR.0",       UNIT_TR,  0 },
257     { "TXMASK",     UNIT_TR,  1 },
258     { "TR.1",       UNIT_TR,  1 },
259     { "TXSTATI",    UNIT_TR,  2 },
260     { "TR.2",       UNIT_TR,  2 },
261     { "TXMASKI",    UNIT_TR,  3 },
262     { "TR.3",       UNIT_TR,  3 },
263     { "TXPOLL",     UNIT_TR,  4 },
264     { "TR.4",       UNIT_TR,  4 },
265     { "TXGPIOI",    UNIT_TR,  5 },
266     { "TR.5",       UNIT_TR,  5 },
267     { "TXPOLLI",    UNIT_TR,  6 },
268     { "TR.6",       UNIT_TR,  6 },
269     { "TXGPIOO",    UNIT_TR,  7 },
270     { "TR.7",       UNIT_TR,  7 },
271 
272     { "TTEXEC",     UNIT_TT,  0 },
273     { "TT.0",       UNIT_TT,  0 },
274     { "TTCTRL",     UNIT_TT,  1 },
275     { "TT.1",       UNIT_TT,  1 },
276     { "TTMARK",     UNIT_TT,  2 },
277     { "TT.2",       UNIT_TT,  2 },
278     { "TTREC",      UNIT_TT,  3 },
279     { "TT.3",       UNIT_TT,  3 },
280     { "GTEXEC",     UNIT_TT,  4 },
281     { "TT.4",       UNIT_TT,  4 },
282 
283     { "FX.0",       UNIT_FX,  0 },
284     { "FX.1",       UNIT_FX,  1 },
285     { "FX.2",       UNIT_FX,  2 },
286     { "FX.3",       UNIT_FX,  3 },
287     { "FX.4",       UNIT_FX,  4 },
288     { "FX.5",       UNIT_FX,  5 },
289     { "FX.6",       UNIT_FX,  6 },
290     { "FX.7",       UNIT_FX,  7 },
291     { "FX.8",       UNIT_FX,  8 },
292     { "FX.9",       UNIT_FX,  9 },
293     { "FX.10",      UNIT_FX, 10 },
294     { "FX.11",      UNIT_FX, 11 },
295     { "FX.12",      UNIT_FX, 12 },
296     { "FX.13",      UNIT_FX, 13 },
297     { "FX.14",      UNIT_FX, 14 },
298     { "FX.15",      UNIT_FX, 15 },
299   };
300 
301 static const metag_reg metag_dsp_regtab[] =
302   {
303     { "D0AR.0",   UNIT_RAM_D0,  0 },
304     { "D0AR.1",   UNIT_RAM_D0,  1 },
305     { "D0AW.0",   UNIT_RAM_D0,  2 },
306     { "D0AW.1",   UNIT_RAM_D0,  3 },
307     { "D0BR.0",   UNIT_RAM_D0,  4 },
308     { "D0BR.1",   UNIT_RAM_D0,  5 },
309     { "D0BW.0",   UNIT_RAM_D0,  6 },
310     { "D0BW.1",   UNIT_RAM_D0,  7 },
311     { "D0ARI.0",  UNIT_RAM_D0,  8 },
312     { "D0ARI.1",  UNIT_RAM_D0,  9 },
313     { "D0AWI.0",  UNIT_RAM_D0, 10 },
314     { "D0AWI.1",  UNIT_RAM_D0, 11 },
315     { "D0BRI.0",  UNIT_RAM_D0, 12 },
316     { "D0BRI.1",  UNIT_RAM_D0, 13 },
317     { "D0BWI.0",  UNIT_RAM_D0, 14 },
318     { "D0BWI.1",  UNIT_RAM_D0, 15 },
319 
320     { "AC0.0",    UNIT_ACC_D0, 16 },
321     { "AC0.1",    UNIT_ACC_D0, 17 },
322     { "AC0.2",    UNIT_ACC_D0, 18 },
323     { "AC0.3",    UNIT_ACC_D0, 19 },
324 
325     { "D1AR.0",   UNIT_RAM_D1,  0 },
326     { "D1AR.1",   UNIT_RAM_D1,  1 },
327     { "D1AW.0",   UNIT_RAM_D1,  2 },
328     { "D1AW.1",   UNIT_RAM_D1,  3 },
329     { "D1BR.0",   UNIT_RAM_D1,  4 },
330     { "D1BR.1",   UNIT_RAM_D1,  5 },
331     { "D1BW.0",   UNIT_RAM_D1,  6 },
332     { "D1BW.1",   UNIT_RAM_D1,  7 },
333     { "D1ARI.0",  UNIT_RAM_D1,  8 },
334     { "D1ARI.1",  UNIT_RAM_D1,  9 },
335     { "D1AWI.0",  UNIT_RAM_D1, 10 },
336     { "D1AWI.1",  UNIT_RAM_D1, 11 },
337     { "D1BRI.0",  UNIT_RAM_D1, 12 },
338     { "D1BRI.1",  UNIT_RAM_D1, 13 },
339     { "D1BWI.0",  UNIT_RAM_D1, 14 },
340     { "D1BWI.1",  UNIT_RAM_D1, 15 },
341 
342     { "AC1.0",    UNIT_ACC_D1, 16 },
343     { "AC1.1",    UNIT_ACC_D1, 17 },
344     { "AC1.2",    UNIT_ACC_D1, 18 },
345     { "AC1.3",    UNIT_ACC_D1, 19 },
346 
347     { "T0",       UNIT_DT,  0 },
348     { "T1",       UNIT_DT,  1 },
349     { "T2",       UNIT_DT,  2 },
350     { "T3",       UNIT_DT,  3 },
351     { "T4",       UNIT_DT,  4 },
352     { "T5",       UNIT_DT,  5 },
353     { "T6",       UNIT_DT,  6 },
354     { "T7",       UNIT_DT,  7 },
355     { "T8",       UNIT_DT,  8 },
356     { "T9",       UNIT_DT,  9 },
357     { "TA",       UNIT_DT, 10 },
358     { "TB",       UNIT_DT, 11 },
359     { "TC",       UNIT_DT, 12 },
360     { "TD",       UNIT_DT, 13 },
361     { "TE",       UNIT_DT, 14 },
362     { "TF",       UNIT_DT, 15 },
363   };
364 
365 /* This table differs from 'metag_dsp_regtab' in that the number
366    fields in this table are suitable for insertion into DSPRAM
367    template definition instruction encodings.
368 
369    The table is indexed by "load". The main benefit of this is that we
370    can implicitly check that the correct DSPRAM register has been used
371    when parsing, e.g. the read pointer only appears in the load table
372    and the write pointer only exists in the store table.
373 
374    The ordering of the table entries might look a bit weird but it is
375    based on matching the longest register string. */
376 static const metag_reg metag_dsp_tmpl_regtab[2][56] =
377   {
378     {
379       { "D0AW.0+D0AWI.0++", UNIT_RAM_D0, 18 },
380       { "D0AW.0+D0AWI.0",   UNIT_RAM_D0, 18 },
381       { "D0AW.0+D0AWI.1++", UNIT_RAM_D0, 19 },
382       { "D0AW.0+D0AWI.1",   UNIT_RAM_D0, 19 },
383       { "D0AW.0++",         UNIT_RAM_D0, 17 },
384       { "D0AW.0",           UNIT_RAM_D0, 16 },
385       { "D0AWI.0",          UNIT_RAM_D0, 18 },
386       { "D0AWI.1",          UNIT_RAM_D0, 19 },
387       { "D0AW.1+D0AWI.0++", UNIT_RAM_D0, 22 },
388       { "D0AW.1+D0AWI.0",   UNIT_RAM_D0, 22 },
389       { "D0AW.1+D0AWI.1++", UNIT_RAM_D0, 23 },
390       { "D0AW.1+D0AWI.1",   UNIT_RAM_D0, 23 },
391       { "D0AW.1++",         UNIT_RAM_D0, 21 },
392       { "D0AW.1",           UNIT_RAM_D0, 20 },
393       { "D0BW.0+D0BWI.0++", UNIT_RAM_D0, 26 },
394       { "D0BW.0+D0BWI.0",   UNIT_RAM_D0, 26 },
395       { "D0BW.0+D0BWI.1++", UNIT_RAM_D0, 27 },
396       { "D0BW.0+D0BWI.1",   UNIT_RAM_D0, 27 },
397       { "D0BW.0++",         UNIT_RAM_D0, 25 },
398       { "D0BW.0",           UNIT_RAM_D0, 24 },
399       { "D0BWI.0",          UNIT_RAM_D0, 18 },
400       { "D0BWI.1",          UNIT_RAM_D0, 19 },
401       { "D0BW.1+D0BWI.0++", UNIT_RAM_D0, 30 },
402       { "D0BW.1+D0BWI.0",   UNIT_RAM_D0, 30 },
403       { "D0BW.1+D0BWI.1++", UNIT_RAM_D0, 31 },
404       { "D0BW.1+D0BWI.1",   UNIT_RAM_D0, 31 },
405       { "D0BW.1++",         UNIT_RAM_D0, 29 },
406       { "D0BW.1",           UNIT_RAM_D0, 28 },
407 
408       { "D1AW.0+D1AWI.0++", UNIT_RAM_D1, 18 },
409       { "D1AW.0+D1AWI.0",   UNIT_RAM_D1, 18 },
410       { "D1AW.0+D1AWI.1++", UNIT_RAM_D1, 19 },
411       { "D1AW.0+D1AWI.1",   UNIT_RAM_D1, 19 },
412       { "D1AW.0++",         UNIT_RAM_D1, 17 },
413       { "D1AW.0",           UNIT_RAM_D1, 16 },
414       { "D1AWI.0",          UNIT_RAM_D1, 18 },
415       { "D1AWI.1",          UNIT_RAM_D1, 19 },
416       { "D1AW.1+D1AWI.0++", UNIT_RAM_D1, 22 },
417       { "D1AW.1+D1AWI.0",   UNIT_RAM_D1, 22 },
418       { "D1AW.1+D1AWI.1++", UNIT_RAM_D1, 23 },
419       { "D1AW.1+D1AWI.1",   UNIT_RAM_D1, 23 },
420       { "D1AW.1++",         UNIT_RAM_D1, 21 },
421       { "D1AW.1",           UNIT_RAM_D1, 20 },
422       { "D1BW.0+D1BWI.0++", UNIT_RAM_D1, 26 },
423       { "D1BW.0+D1BWI.0",   UNIT_RAM_D1, 26 },
424       { "D1BW.0+D1BWI.1++", UNIT_RAM_D1, 27 },
425       { "D1BW.0+D1BWI.1",   UNIT_RAM_D1, 27 },
426       { "D1BW.0++",         UNIT_RAM_D1, 25 },
427       { "D1BW.0",           UNIT_RAM_D1, 24 },
428       { "D1BWI.0",          UNIT_RAM_D1, 18 },
429       { "D1BWI.1",          UNIT_RAM_D1, 19 },
430       { "D1BW.1+D1BWI.0++", UNIT_RAM_D1, 30 },
431       { "D1BW.1+D1BWI.0",   UNIT_RAM_D1, 30 },
432       { "D1BW.1+D1BWI.1++", UNIT_RAM_D1, 31 },
433       { "D1BW.1+D1BWI.1",   UNIT_RAM_D1, 31 },
434       { "D1BW.1++",         UNIT_RAM_D1, 29 },
435       { "D1BW.1",           UNIT_RAM_D1, 28 },
436     },
437 
438     {
439       { "D0AR.0+D0ARI.0++", UNIT_RAM_D0, 18 },
440       { "D0AR.0+D0ARI.0",   UNIT_RAM_D0, 18 },
441       { "D0AR.0+D0ARI.1++", UNIT_RAM_D0, 19 },
442       { "D0AR.0+D0ARI.1",   UNIT_RAM_D0, 19 },
443       { "D0AR.0++",         UNIT_RAM_D0, 17 },
444       { "D0AR.0",           UNIT_RAM_D0, 16 },
445       { "D0ARI.0",          UNIT_RAM_D0, 18 },
446       { "D0ARI.1",          UNIT_RAM_D0, 19 },
447       { "D0AR.1+D0ARI.0++", UNIT_RAM_D0, 22 },
448       { "D0AR.1+D0ARI.0",   UNIT_RAM_D0, 22 },
449       { "D0AR.1+D0ARI.1++", UNIT_RAM_D0, 23 },
450       { "D0AR.1+D0ARI.1",   UNIT_RAM_D0, 23 },
451       { "D0AR.1++",         UNIT_RAM_D0, 21 },
452       { "D0AR.1",           UNIT_RAM_D0, 20 },
453       { "D0BR.0+D0BRI.0++", UNIT_RAM_D0, 26 },
454       { "D0BR.0+D0BRI.0",   UNIT_RAM_D0, 26 },
455       { "D0BR.0+D0BRI.1++", UNIT_RAM_D0, 27 },
456       { "D0BR.0+D0BRI.1",   UNIT_RAM_D0, 27 },
457       { "D0BR.0++",         UNIT_RAM_D0, 25 },
458       { "D0BR.0",           UNIT_RAM_D0, 24 },
459       { "D0BRI.0",          UNIT_RAM_D0, 18 },
460       { "D0BRI.1",          UNIT_RAM_D0, 19 },
461       { "D0BR.1+D0BRI.0++", UNIT_RAM_D0, 30 },
462       { "D0BR.1+D0BRI.0",   UNIT_RAM_D0, 30 },
463       { "D0BR.1+D0BRI.1++", UNIT_RAM_D0, 31 },
464       { "D0BR.1+D0BRI.1",   UNIT_RAM_D0, 31 },
465       { "D0BR.1++",         UNIT_RAM_D0, 29 },
466       { "D0BR.1",           UNIT_RAM_D0, 28 },
467 
468       { "D1AR.0+D1ARI.0++", UNIT_RAM_D1, 18 },
469       { "D1AR.0+D1ARI.0",   UNIT_RAM_D1, 18 },
470       { "D1AR.0+D1ARI.1++", UNIT_RAM_D1, 19 },
471       { "D1AR.0+D1ARI.1",   UNIT_RAM_D1, 19 },
472       { "D1AR.0++",         UNIT_RAM_D1, 17 },
473       { "D1AR.0",           UNIT_RAM_D1, 16 },
474       { "D1ARI.0",          UNIT_RAM_D1, 18 },
475       { "D1ARI.1",          UNIT_RAM_D1, 19 },
476       { "D1AR.1+D1ARI.0++", UNIT_RAM_D1, 22 },
477       { "D1AR.1+D1ARI.0",   UNIT_RAM_D1, 22 },
478       { "D1AR.1+D1ARI.1++", UNIT_RAM_D1, 23 },
479       { "D1AR.1+D1ARI.1",   UNIT_RAM_D1, 23 },
480       { "D1AR.1++",         UNIT_RAM_D1, 21 },
481       { "D1AR.1",           UNIT_RAM_D1, 20 },
482       { "D1BR.0+D1BRI.0++", UNIT_RAM_D1, 26 },
483       { "D1BR.0+D1BRI.0",   UNIT_RAM_D1, 26 },
484       { "D1BR.0+D1BRI.1++", UNIT_RAM_D1, 27 },
485       { "D1BR.0+D1BRI.1",   UNIT_RAM_D1, 27 },
486       { "D1BR.0++",         UNIT_RAM_D1, 25 },
487       { "D1BR.0",           UNIT_RAM_D1, 24 },
488       { "D1BR.1+D1BRI.0++", UNIT_RAM_D1, 30 },
489       { "D1BR.1+D1BRI.0",   UNIT_RAM_D1, 30 },
490       { "D1BR.1+D1BRI.1++", UNIT_RAM_D1, 31 },
491       { "D1BR.1+D1BRI.1",   UNIT_RAM_D1, 31 },
492       { "D1BR.1++",         UNIT_RAM_D1, 29 },
493       { "D1BR.1",           UNIT_RAM_D1, 28 },
494       { "D1BRI.0",          UNIT_RAM_D1, 18 },
495       { "D1BRI.1",          UNIT_RAM_D1, 19 },
496     },
497   };
498 
499 typedef struct
500 {
501   const char *  name;
502   unsigned int  part;
503 } metag_acf;
504 
505 static const metag_acf metag_acftab[] =
506   {
507     { "ACF.0", 0},
508     { "ACF.1", 1},
509     { "ACF.2", 2},
510     { "ACF.3", 3},
511   };
512 
513 enum insn_encoding
514 {
515   ENC_NONE,
516   ENC_MOV_U2U,
517   ENC_MOV_PORT,
518   ENC_MMOV,
519   ENC_MDRD,
520   ENC_MOVL_TTREC,
521   ENC_GET_SET,
522   ENC_GET_SET_EXT,
523   ENC_MGET_MSET,
524   ENC_COND_SET,
525   ENC_XFR,
526   ENC_MOV_CT,
527   ENC_SWAP,
528   ENC_JUMP,
529   ENC_CALLR,
530   ENC_ALU,
531   ENC_SHIFT,
532   ENC_MIN_MAX,
533   ENC_BITOP,
534   ENC_CMP,
535   ENC_BRANCH,
536   ENC_KICK,
537   ENC_SWITCH,
538   ENC_CACHER,
539   ENC_CACHEW,
540   ENC_ICACHE,
541   ENC_LNKGET,
542   ENC_FMOV,
543   ENC_FMMOV,
544   ENC_FMOV_DATA,
545   ENC_FMOV_I,
546   ENC_FPACK,
547   ENC_FSWAP,
548   ENC_FCMP,
549   ENC_FMINMAX,
550   ENC_FCONV,
551   ENC_FCONVX,
552   ENC_FBARITH,
553   ENC_FEARITH,
554   ENC_FREC,
555   ENC_FSIMD,
556   ENC_FGET_SET_ACF,
557   ENC_DGET_SET,
558   ENC_DTEMPLATE,
559   ENC_DALU,
560   ENC_MAX,
561 };
562 
563 enum insn_type
564 {
565   INSN_GP,
566   INSN_FPU,
567   INSN_DSP,
568   INSN_DSP_FPU,
569 };
570 
571 typedef struct
572 {
573   const char *name;
574 
575   unsigned int core_flags;
576 #define CoreMeta11             0x1 /* The earliest Meta core we support */
577 #define CoreMeta12             0x2
578 #define CoreMeta21             0x4
579 
580 #define FpuMeta21             0x21
581 
582 #define DspMeta21             0x100
583 
584   unsigned int meta_opcode;
585   unsigned int meta_mask;
586 
587   enum insn_type insn_type;
588 
589   enum insn_encoding encoding;
590 
591 #define DSP_ARGS_1    0x0000001 /* De.r,Dx.r,De.r (3 register operands) */
592 #define DSP_ARGS_ACC2 0x0000002 /* Accumulator source operand 2 */
593 #define DSP_ARGS_QR   0x0000004 /* QUICKRoT */
594 #define DSP_ARGS_XACC 0x0000008 /* Cross-unit accumulator op */
595 #define DSP_ARGS_DACC 0x0000010 /* Target accumulator as destination */
596 #define DSP_ARGS_SRD  0x0000020 /* Source the RD port */
597 #define DSP_ARGS_2    0x0000040 /* De.r,Dx.r (2 register operands) */
598 #define DSP_ARGS_DSP_SRC1   0x0000080 /* Source a DSP register */
599 #define DSP_ARGS_DSP_SRC2   0x0000100 /* Source a DSP register */
600 #define DSP_ARGS_IMM 0x0000200 /* Immediate value for src 2 */
601 #define DSP_ARGS_SPLIT8  0x0000400 /* Data unit split 8 operations */
602 #define DSP_ARGS_12  0x0000800 /* De.r,Dx.r */
603 #define DSP_ARGS_13  0x0001000 /* Dx.r,Rx.r */
604 #define DSP_ARGS_14  0x0002000 /* DSPe.r,Dx.r */
605 #define DSP_ARGS_15  0x0004000 /* DSPx.r,#I16 */
606 #define DSP_ARGS_16  0x0008000 /* De.r,DSPx.r */
607 #define DSP_ARGS_17  0x0010000 /* De.r|ACe.r,Dx.r,Rx.r|RD */
608 #define DSP_ARGS_18  0x0020000 /* De.r,Dx.r|ACx.r */
609 #define DSP_ARGS_20  0x0080000 /* De.r,Dx.r|ACx.r,De.r */
610 #define DSP_ARGS_21  0x0100000 /* De.r,Dx.r|ACx.r,#I5 */
611 #define DSP_ARGS_22  0x0200000 /* De.r,Dx.r|ACx.r,De.r|#I5 */
612 #define DSP_ARGS_23  0x0400000 /* Ux.r,Dx.r|ACx.r,De.r|#I5 */
613 #define GP_ARGS_QR   0x0000001 /* QUICKRoT */
614   unsigned int arg_type;
615 } insn_template;
616 
617 enum major_opcode
618 {
619   OPC_ADD,
620   OPC_SUB,
621   OPC_AND,
622   OPC_OR,
623   OPC_XOR,
624   OPC_SHIFT,
625   OPC_MUL,
626   OPC_CMP,
627   OPC_ADDR,
628   OPC_9,
629   OPC_MISC,
630   OPC_SET,
631   OPC_GET,
632   OPC_XFR,
633   OPC_CPR,
634   OPC_FPU,
635 };
636 
637 #define GET_EXT_MINOR        0x7
638 #define MOV_EXT_MINOR        0x6
639 #define MOVL_MINOR           0x2
640 
641 #define MAJOR_OPCODE(opcode) (((opcode) >> 28) & 0xf)
642 #define MINOR_OPCODE(opcode) (((opcode) >> 24) & 0xf)
643 
644 enum cond_code
645 {
646   COND_A,
647   COND_EQ,
648   COND_NE,
649   COND_CS,
650   COND_CC,
651   COND_MI,
652   COND_PL,
653   COND_VS,
654   COND_VC,
655   COND_HI,
656   COND_LS,
657   COND_GE,
658   COND_LT,
659   COND_GT,
660   COND_LE,
661   COND_NV,
662 };
663 
664 enum scond_code
665 {
666   SCOND_A,
667   SCOND_LEQ,
668   SCOND_LNE,
669   SCOND_LLO,
670   SCOND_LHS,
671   SCOND_HEQ,
672   SCOND_HNE,
673   SCOND_HLO,
674   SCOND_HHS,
675   SCOND_LGR,
676   SCOND_LLE,
677   SCOND_HGR,
678   SCOND_HLE,
679   SCOND_EEQ,
680   SCOND_ELO,
681   SCOND_NV,
682 };
683 
684 typedef struct
685 {
686   const char *name;
687   enum scond_code code;
688 } split_condition;
689 
690 static const split_condition metag_scondtab[] ATTRIBUTE_UNUSED =
691   {
692     { "LEQ",   SCOND_LEQ },
693     { "LEZ",   SCOND_LEQ },
694     { "LNE",   SCOND_LNE },
695     { "LNZ",   SCOND_LNE },
696     { "LLO",   SCOND_LLO },
697     { "LCS",   SCOND_LLO },
698     { "LHS",   SCOND_LHS },
699     { "LCC",   SCOND_LHS },
700     { "HEQ",   SCOND_HEQ },
701     { "HEZ",   SCOND_HEQ },
702     { "HNE",   SCOND_HNE },
703     { "HNZ",   SCOND_HNE },
704     { "HLO",   SCOND_HLO },
705     { "HCS",   SCOND_HLO },
706     { "HHS",   SCOND_HHS },
707     { "HCC",   SCOND_HHS },
708     { "LGR",   SCOND_LGR },
709     { "LHI",   SCOND_LGR },
710     { "LLE",   SCOND_LLE },
711     { "LLS",   SCOND_LLE },
712     { "HGR",   SCOND_HGR },
713     { "HHI",   SCOND_HGR },
714     { "HLE",   SCOND_HLE },
715     { "HLS",   SCOND_HLE },
716     { "EEQ",   SCOND_EEQ },
717     { "EEZ",   SCOND_EEQ },
718     { "ELO",   SCOND_ELO },
719     { "ECS",   SCOND_ELO },
720   };
721 
722 static const split_condition metag_dsp_scondtab[] =
723   {
724     { "LEQ",   SCOND_LEQ },
725     { "LEZ",   SCOND_LEQ },
726     { "LNE",   SCOND_LNE },
727     { "LNZ",   SCOND_LNE },
728     { "LCS",   SCOND_LLO },
729     { "LLO",   SCOND_LLO },
730     { "LCC",   SCOND_LHS },
731     { "LHS",   SCOND_LHS },
732     { "HEQ",   SCOND_HEQ },
733     { "HEZ",   SCOND_HEQ },
734     { "HNE",   SCOND_HNE },
735     { "HNZ",   SCOND_HNE },
736     { "HCS",   SCOND_HLO },
737     { "HLO",   SCOND_HLO },
738     { "HCC",   SCOND_HHS },
739     { "HHS",   SCOND_HHS },
740     { "LHI",   SCOND_LGR },
741     { "LGR",   SCOND_LGR },
742     { "LLS",   SCOND_LLE },
743     { "LLE",   SCOND_LLE },
744     { "HHI",   SCOND_HGR },
745     { "HGR",   SCOND_HGR },
746     { "HLS",   SCOND_HLE },
747     { "HLE",   SCOND_HLE },
748     { "EEQ",   SCOND_EEQ },
749     { "EEZ",   SCOND_EEQ },
750     { "ECS",   SCOND_ELO },
751     { "ELO",   SCOND_ELO },
752   };
753 
754 static const split_condition metag_fpu_scondtab[] =
755   {
756     { "LEQ",   SCOND_LEQ },
757     { "LEZ",   SCOND_LEQ },
758     { "LNE",   SCOND_LNE },
759     { "LNZ",   SCOND_LNE },
760     { "LLO",   SCOND_LLO },
761     { "LCS",   SCOND_LLO },
762     { "LHS",   SCOND_LHS },
763     { "LCC",   SCOND_LHS },
764     { "HEQ",   SCOND_HEQ },
765     { "HEZ",   SCOND_HEQ },
766     { "HNE",   SCOND_HNE },
767     { "HNZ",   SCOND_HNE },
768     { "HLO",   SCOND_HLO },
769     { "HCS",   SCOND_HLO },
770     { "HHS",   SCOND_HHS },
771     { "HCC",   SCOND_HHS },
772     { "LGR",   SCOND_LGR },
773     { "LHI",   SCOND_LGR },
774     { "LLE",   SCOND_LLE },
775     { "LLS",   SCOND_LLE },
776     { "HGR",   SCOND_HGR },
777     { "HHI",   SCOND_HGR },
778     { "HLE",   SCOND_HLE },
779     { "HLS",   SCOND_HLE },
780     { "EEQ",   SCOND_EEQ },
781     { "EEZ",   SCOND_EEQ },
782     { "ELO",   SCOND_ELO },
783     { "ECS",   SCOND_ELO },
784   };
785 
786 enum fcond_code
787 {
788   FCOND_A,
789   FCOND_FEQ,
790   FCOND_UNE,
791   FCOND_FLT,
792   FCOND_UGE,
793 
794   FCOND_UVS = 7,
795   FCOND_FVC,
796   FCOND_UGT,
797   FCOND_FLE,
798   FCOND_FGE,
799   FCOND_ULT,
800   FCOND_FGT,
801   FCOND_ULE,
802   FCOND_NV,
803 };
804 
805 #define COND_INSN(mnemonic, suffix, field_shift, flags, meta_opcode,	\
806 		  meta_mask, insn_type,	encoding, args)			\
807   { mnemonic suffix, flags, meta_opcode, meta_mask,			\
808       insn_type, encoding, args },					\
809   { mnemonic "A" suffix, flags, meta_opcode, meta_mask,			\
810       insn_type, encoding, args },					\
811   { mnemonic "EQ" suffix, flags, meta_opcode | (COND_EQ << field_shift), \
812       meta_mask, insn_type, encoding, args },				\
813   { mnemonic "Z" suffix, flags, meta_opcode | (COND_EQ << field_shift),	\
814       meta_mask, insn_type, encoding, args },				\
815   { mnemonic "NE" suffix, flags, meta_opcode | (COND_NE << field_shift), \
816       meta_mask, insn_type, encoding, args },				\
817   { mnemonic "NZ" suffix, flags, meta_opcode | (COND_NE << field_shift), \
818       meta_mask, insn_type, encoding, args },				\
819   { mnemonic "CS" suffix, flags, meta_opcode | (COND_CS << field_shift), \
820       meta_mask, insn_type, encoding, args },				\
821   { mnemonic "LO" suffix, flags, meta_opcode | (COND_CS << field_shift), \
822       meta_mask, insn_type, encoding, args },				\
823   { mnemonic "CC" suffix, flags, meta_opcode | (COND_CC << field_shift), \
824       meta_mask, insn_type, encoding, args },				\
825   { mnemonic "HS" suffix, flags, meta_opcode | (COND_CC << field_shift), \
826       meta_mask, insn_type, encoding, args },				\
827   { mnemonic "MI" suffix, flags, meta_opcode | (COND_MI << field_shift), \
828       meta_mask, insn_type, encoding, args },				\
829   { mnemonic "N" suffix, flags, meta_opcode | (COND_MI << field_shift),	\
830       meta_mask, insn_type, encoding, args },				\
831   { mnemonic "PL" suffix, flags, meta_opcode | (COND_PL << field_shift), \
832       meta_mask, insn_type, encoding, args },				\
833   { mnemonic "NC" suffix, flags, meta_opcode | (COND_PL << field_shift), \
834       meta_mask, insn_type, encoding, args },				\
835   { mnemonic "VS" suffix, flags, meta_opcode | (COND_VS << field_shift), \
836       meta_mask, insn_type, encoding, args },				\
837   { mnemonic "VC" suffix, flags, meta_opcode | (COND_VC << field_shift), \
838       meta_mask, insn_type, encoding, args },				\
839   { mnemonic "HI" suffix, flags, meta_opcode | (COND_HI << field_shift), \
840       meta_mask, insn_type, encoding, args },				\
841   { mnemonic "LS" suffix, flags, meta_opcode | (COND_LS << field_shift), \
842       meta_mask, insn_type, encoding, args },				\
843   { mnemonic "GE" suffix, flags, meta_opcode | (COND_GE << field_shift), \
844       meta_mask, insn_type, encoding, args },				\
845   { mnemonic "LT" suffix, flags, meta_opcode | (COND_LT << field_shift), \
846       meta_mask, insn_type, encoding, args },				\
847   { mnemonic "GT" suffix, flags, meta_opcode | (COND_GT << field_shift), \
848       meta_mask, insn_type, encoding, args },				\
849   { mnemonic "LE" suffix, flags, meta_opcode | (COND_LE << field_shift), \
850       meta_mask, insn_type, encoding, args },				\
851   { mnemonic "NV" suffix, flags, meta_opcode | (COND_NV << field_shift), \
852       meta_mask, insn_type, encoding, args },				\
853   { mnemonic "FEQ" suffix, flags, meta_opcode |				\
854       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
855   { mnemonic "FZ" suffix, flags, meta_opcode |				\
856       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
857   { mnemonic "UNE" suffix, flags, meta_opcode |				\
858       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
859   { mnemonic "UNZ" suffix, flags, meta_opcode |				\
860       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
861   { mnemonic "FLT" suffix, flags, meta_opcode |				\
862       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
863   { mnemonic "FLO" suffix, flags, meta_opcode |				\
864       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
865   { mnemonic "UGE" suffix, flags, meta_opcode |				\
866       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
867   { mnemonic "UHS" suffix, flags, meta_opcode |				\
868       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
869   { mnemonic "UVS" suffix, flags, meta_opcode |				\
870       (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \
871   { mnemonic "FVC" suffix, flags, meta_opcode |				\
872       (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \
873   { mnemonic "UGT" suffix, flags, meta_opcode |				\
874       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
875   { mnemonic "UHI" suffix, flags, meta_opcode |				\
876       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
877   { mnemonic "FLE" suffix, flags, meta_opcode |				\
878       (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
879   { mnemonic "FGE" suffix, flags, meta_opcode |				\
880       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
881   { mnemonic "FHS" suffix, flags, meta_opcode |				\
882       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
883   { mnemonic "ULT" suffix, flags, meta_opcode |				\
884       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
885   { mnemonic "ULO" suffix, flags, meta_opcode |				\
886       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
887   { mnemonic "FGT" suffix, flags, meta_opcode |				\
888       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
889   { mnemonic "FHI" suffix, flags, meta_opcode |				\
890       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
891   { mnemonic "ULE" suffix, flags, meta_opcode |				\
892       (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
893   { mnemonic "NV" suffix, flags, meta_opcode |				\
894       (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args }
895 
896 #define FCOND_INSN(mnemonic, suffix, field_shift, flags, meta_opcode,	\
897 		  meta_mask, insn_type,	encoding, args)			\
898   { mnemonic suffix, flags, meta_opcode, meta_mask,			\
899       insn_type, encoding, args },					\
900   { mnemonic "A" suffix, flags, meta_opcode, meta_mask,			\
901       insn_type, encoding, args },					\
902   { mnemonic "FEQ" suffix, flags, meta_opcode |				\
903       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
904   { mnemonic "FZ" suffix, flags, meta_opcode |				\
905       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
906   { mnemonic "UNE" suffix, flags, meta_opcode |				\
907       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
908   { mnemonic "UNZ" suffix, flags, meta_opcode |				\
909       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
910   { mnemonic "FLO" suffix, flags, meta_opcode |				\
911       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
912   { mnemonic "FLT" suffix, flags, meta_opcode |				\
913       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
914   { mnemonic "UHS" suffix, flags, meta_opcode |				\
915       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
916   { mnemonic "UGE" suffix, flags, meta_opcode |				\
917       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
918   { mnemonic "UVS" suffix, flags, meta_opcode |				\
919       (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \
920   { mnemonic "FVC" suffix, flags, meta_opcode |				\
921       (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \
922   { mnemonic "UHI" suffix, flags, meta_opcode |				\
923       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
924   { mnemonic "UGT" suffix, flags, meta_opcode |				\
925       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
926   { mnemonic "FLE" suffix, flags, meta_opcode |				\
927       (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
928   { mnemonic "FGE" suffix, flags, meta_opcode |				\
929       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
930   { mnemonic "FHS" suffix, flags, meta_opcode |				\
931       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
932   { mnemonic "ULT" suffix, flags, meta_opcode |				\
933       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
934   { mnemonic "ULO" suffix, flags, meta_opcode |				\
935       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
936   { mnemonic "FGT" suffix, flags, meta_opcode |				\
937       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
938   { mnemonic "FHI" suffix, flags, meta_opcode |				\
939       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
940   { mnemonic "ULE" suffix, flags, meta_opcode |				\
941       (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
942   { mnemonic "NV" suffix, flags, meta_opcode |				\
943       (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args },	\
944   { mnemonic "EQ" suffix, flags, meta_opcode | (COND_EQ << field_shift), \
945       meta_mask, insn_type, encoding, args },				\
946   { mnemonic "Z" suffix, flags, meta_opcode | (COND_EQ << field_shift),	\
947       meta_mask, insn_type, encoding, args },				\
948   { mnemonic "NE" suffix, flags, meta_opcode | (COND_NE << field_shift), \
949       meta_mask, insn_type, encoding, args },				\
950   { mnemonic "NZ" suffix, flags, meta_opcode | (COND_NE << field_shift), \
951       meta_mask, insn_type, encoding, args },				\
952   { mnemonic "CS" suffix, flags, meta_opcode | (COND_CS << field_shift), \
953       meta_mask, insn_type, encoding, args },				\
954   { mnemonic "LO" suffix, flags, meta_opcode | (COND_CS << field_shift), \
955       meta_mask, insn_type, encoding, args },				\
956   { mnemonic "CC" suffix, flags, meta_opcode | (COND_CC << field_shift), \
957       meta_mask, insn_type, encoding, args },				\
958   { mnemonic "HS" suffix, flags, meta_opcode | (COND_CC << field_shift), \
959       meta_mask, insn_type, encoding, args },				\
960   { mnemonic "MI" suffix, flags, meta_opcode | (COND_MI << field_shift), \
961       meta_mask, insn_type, encoding, args },				\
962   { mnemonic "N" suffix, flags, meta_opcode | (COND_MI << field_shift),	\
963       meta_mask, insn_type, encoding, args },				\
964   { mnemonic "PL" suffix, flags, meta_opcode | (COND_PL << field_shift), \
965       meta_mask, insn_type, encoding, args },				\
966   { mnemonic "NC" suffix, flags, meta_opcode | (COND_PL << field_shift), \
967       meta_mask, insn_type, encoding, args },				\
968   { mnemonic "VS" suffix, flags, meta_opcode | (COND_VS << field_shift), \
969       meta_mask, insn_type, encoding, args },				\
970   { mnemonic "VC" suffix, flags, meta_opcode | (COND_VC << field_shift), \
971       meta_mask, insn_type, encoding, args },				\
972   { mnemonic "HI" suffix, flags, meta_opcode | (COND_HI << field_shift), \
973       meta_mask, insn_type, encoding, args },				\
974   { mnemonic "LS" suffix, flags, meta_opcode | (COND_LS << field_shift), \
975       meta_mask, insn_type, encoding, args },				\
976   { mnemonic "GE" suffix, flags, meta_opcode | (COND_GE << field_shift), \
977       meta_mask, insn_type, encoding, args },				\
978   { mnemonic "LT" suffix, flags, meta_opcode | (COND_LT << field_shift), \
979       meta_mask, insn_type, encoding, args },				\
980   { mnemonic "GT" suffix, flags, meta_opcode | (COND_GT << field_shift), \
981       meta_mask, insn_type, encoding, args },				\
982   { mnemonic "LE" suffix, flags, meta_opcode | (COND_LE << field_shift), \
983       meta_mask, insn_type, encoding, args },				\
984   { mnemonic "NV" suffix, flags, meta_opcode | (COND_NV << field_shift), \
985       meta_mask, insn_type, encoding, args }
986 
987 #define TEMPLATE_INSN(flags, meta_opcode, meta_mask, insn_type)		\
988   { "T0", flags, meta_opcode | 0x0, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
989   { "T1", flags, meta_opcode | 0x1, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
990   { "T2", flags, meta_opcode | 0x2, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
991   { "T3", flags, meta_opcode | 0x3, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
992   { "T4", flags, meta_opcode | 0x4, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
993   { "T5", flags, meta_opcode | 0x5, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
994   { "T6", flags, meta_opcode | 0x6, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
995   { "T7", flags, meta_opcode | 0x7, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
996   { "T8", flags, meta_opcode | 0x8, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
997   { "T9", flags, meta_opcode | 0x9, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
998   { "TA", flags, meta_opcode | 0xa, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
999   { "TB", flags, meta_opcode | 0xb, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
1000   { "TC", flags, meta_opcode | 0xc, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
1001   { "TD", flags, meta_opcode | 0xd, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
1002   { "TE", flags, meta_opcode | 0xe, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
1003   { "TF", flags, meta_opcode | 0xf, meta_mask, insn_type, ENC_DTEMPLATE, 0 }
1004 
1005 
1006 /* Unimplemented GP instructions:
1007      CPR - coprocessor read
1008      CPW - coprocessor write
1009      MORT - morton order operation
1010      VPACK, VADD, VSUB - vector instructions
1011 
1012    The order of the entries in this table is extremely important. DO
1013    NOT modify it unless you know what you're doing. If you do modify
1014    it, be sure to run the entire testsuite to make sure you haven't
1015    caused a regression.  */
1016 
1017 static const insn_template metag_optab[] =
1018   {
1019     /* Port-to-unit MOV */
1020     COND_INSN ("MOVB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1021 	       0xa1800000, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
1022     COND_INSN ("MOVW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1023 	       0xa1800001, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
1024     COND_INSN ("MOVD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1025 	       0xa1800200, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
1026     COND_INSN ("MOVL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1027 	       0xa2800000, 0xfff8019f, INSN_GP, ENC_MOV_PORT, 0),
1028 
1029     /* Read pipeline prime/drain */
1030     { "MMOVD", CoreMeta11|CoreMeta12|CoreMeta21,
1031       0xca000000, 0xff00001f, INSN_GP, ENC_MMOV, 0 },
1032     { "MMOVL", CoreMeta11|CoreMeta12|CoreMeta21,
1033       0xcb000000, 0xff00001f, INSN_GP, ENC_MMOV, 0 },
1034     { "MMOVD", CoreMeta11|CoreMeta12|CoreMeta21,
1035       0xcc000000, 0xff07c067, INSN_GP, ENC_MMOV, 0 },
1036     { "MMOVL", CoreMeta11|CoreMeta12|CoreMeta21,
1037       0xcd000000, 0xff07c067, INSN_GP, ENC_MMOV, 0 },
1038 
1039     /* Read pipeline flush */
1040     { "MDRD", CoreMeta11|CoreMeta12|CoreMeta21,
1041       0xcc000002, 0xffffc07f, INSN_GP, ENC_MDRD, 0 },
1042 
1043     /* Unit-to-TTREC MOVL */
1044     COND_INSN ("MOVL", "", 1, CoreMeta12|CoreMeta21,
1045 	       0xa2002001, 0xff003e7f, INSN_GP, ENC_MOVL_TTREC, 0),
1046 
1047     /* MOV to RA (extended) */
1048     { "MOVB", CoreMeta11|CoreMeta12|CoreMeta21,
1049       0xa6000000, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
1050     { "MOVW", CoreMeta11|CoreMeta12|CoreMeta21,
1051       0xa6000002, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
1052     { "MOVD", CoreMeta11|CoreMeta12|CoreMeta21,
1053       0xa6000004, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
1054     { "MOVL", CoreMeta11|CoreMeta12|CoreMeta21,
1055       0xa6000006, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
1056 
1057     /* Extended GET */
1058     { "GETB", CoreMeta11|CoreMeta12|CoreMeta21,
1059       0xa7000000, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
1060     { "GETW", CoreMeta11|CoreMeta12|CoreMeta21,
1061       0xa7000002, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
1062     { "GETD", CoreMeta11|CoreMeta12|CoreMeta21,
1063       0xa7000004, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
1064     { "GETL", CoreMeta11|CoreMeta12|CoreMeta21,
1065       0xa7000006, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
1066 
1067     /* Extended SET */
1068     { "SETB", CoreMeta11|CoreMeta12|CoreMeta21,
1069       0xa5000000, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
1070     { "SETW", CoreMeta11|CoreMeta12|CoreMeta21,
1071       0xa5000002, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
1072     { "SETD", CoreMeta11|CoreMeta12|CoreMeta21,
1073       0xa5000004, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
1074     { "SETL", CoreMeta11|CoreMeta12|CoreMeta21,
1075       0xa5000006, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
1076 
1077     /* MOV to RA */
1078     { "MOVB", CoreMeta11|CoreMeta12|CoreMeta21,
1079       0xc000000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
1080     { "MOVW", CoreMeta11|CoreMeta12|CoreMeta21,
1081       0xc100000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
1082     { "MOVD", CoreMeta11|CoreMeta12|CoreMeta21,
1083       0xc400000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
1084     { "MOVL", CoreMeta11|CoreMeta12|CoreMeta21,
1085       0xc500000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
1086 
1087     /* Standard GET */
1088     { "GETB", CoreMeta11|CoreMeta12|CoreMeta21,
1089       0xc0000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
1090     { "GETW", CoreMeta11|CoreMeta12|CoreMeta21,
1091       0xc1000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
1092     { "GETD", CoreMeta11|CoreMeta12|CoreMeta21,
1093       0xc4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
1094     /* GET is a synonym for GETD. */
1095     { "GET", CoreMeta11|CoreMeta12|CoreMeta21,
1096       0xc4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
1097     { "GETL", CoreMeta11|CoreMeta12|CoreMeta21,
1098       0xc5000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
1099 
1100     /* Standard SET */
1101     { "SETB", CoreMeta11|CoreMeta12|CoreMeta21,
1102       0xb0000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
1103     { "SETW", CoreMeta11|CoreMeta12|CoreMeta21,
1104       0xb1000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
1105     { "SETD", CoreMeta11|CoreMeta12|CoreMeta21,
1106       0xb4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
1107     /* SET is a synonym for SETD. */
1108     { "SET", CoreMeta11|CoreMeta12|CoreMeta21,
1109       0xb4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
1110     { "SETL", CoreMeta11|CoreMeta12|CoreMeta21,
1111       0xb5000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
1112 
1113     /* Multiple GET */
1114     { "MGETD", CoreMeta11|CoreMeta12|CoreMeta21,
1115       0xc8000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
1116     { "MGETL", CoreMeta11|CoreMeta12|CoreMeta21,
1117       0xc9000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
1118 
1119     /* Multiple SET */
1120     { "MSETD", CoreMeta11|CoreMeta12|CoreMeta21,
1121       0xb8000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
1122     { "MSETL", CoreMeta11|CoreMeta12|CoreMeta21,
1123       0xb9000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
1124 
1125     /* Conditional SET */
1126     COND_INSN ("SETB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1127 	       0xa4000000, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
1128     COND_INSN ("SETW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1129 	       0xa4000001, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
1130     COND_INSN ("SETD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1131 	       0xa4000200, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
1132     COND_INSN ("SETL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1133 	       0xa4000201, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
1134     { "XFRD", CoreMeta11|CoreMeta12|CoreMeta21,
1135       0xd0000000, 0xf2000000, INSN_GP, ENC_XFR, 0 },
1136     { "XFRL", CoreMeta11|CoreMeta12|CoreMeta21,
1137       0xd2000000, 0xf2000000, INSN_GP, ENC_XFR, 0 },
1138 
1139     /* Fast control register setup */
1140     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
1141       0xa9000000, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
1142     { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
1143       0xa9000001, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
1144     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
1145       0xa9000004, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
1146     { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
1147       0xa9000005, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
1148 
1149     /* Internal transfer operations */
1150     { "JUMP", CoreMeta11|CoreMeta12|CoreMeta21,
1151       0xac000000, 0xff000004, INSN_GP, ENC_JUMP, 0 },
1152     { "CALL", CoreMeta11|CoreMeta12|CoreMeta21,
1153       0xac000004, 0xff000004, INSN_GP, ENC_JUMP, 0 },
1154     { "CALLR", CoreMeta11|CoreMeta12|CoreMeta21,
1155       0xab000000, 0xff000000, INSN_GP, ENC_CALLR, 0 },
1156 
1157     /* Address unit ALU operations */
1158     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
1159       0x80000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1160     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
1161       0x82000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1162     { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
1163       0x82000005, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1164     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
1165       0x80000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1166     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
1167       0x82000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1168     { "ADDT", CoreMeta11|CoreMeta12|CoreMeta21,
1169       0x82000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1170     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
1171       0x86000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1172     COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1173 	       0x84000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1174     COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1175 	       0x86000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1176     { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
1177       0x88000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1178     { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
1179       0x8a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1180     { "NEGT", CoreMeta11|CoreMeta12|CoreMeta21,
1181       0x8a000005, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1182     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
1183       0x88000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1184     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
1185       0x8a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1186     { "SUBT", CoreMeta11|CoreMeta12|CoreMeta21,
1187       0x8a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1188     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
1189       0x8e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1190     COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1191 	       0x8c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1192     COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1193 	       0x8e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1194 
1195     /* Data unit ALU operations */
1196     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
1197       0x00000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1198     { "MOVS", CoreMeta11|CoreMeta12|CoreMeta21,
1199       0x08000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1200     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
1201       0x02000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1202     { "MOVS", CoreMeta11|CoreMeta12|CoreMeta21,
1203       0x0a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1204     { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
1205       0x02000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1206     { "MOVST", CoreMeta11|CoreMeta12|CoreMeta21,
1207       0x0a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1208     { "ADD", DspMeta21,
1209       0x00000100, 0xfe000104, INSN_DSP, ENC_DALU,
1210       DSP_ARGS_1|DSP_ARGS_ACC2|DSP_ARGS_XACC|DSP_ARGS_IMM },
1211     { "ADD", DspMeta21,
1212       0x02000003, 0xfe000003, INSN_DSP, ENC_DALU,
1213       DSP_ARGS_1|DSP_ARGS_IMM },
1214     COND_INSN ("ADD", "", 1, DspMeta21,
1215 	       0x040001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
1216     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
1217       0x00000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1218     { "ADDS", DspMeta21,
1219       0x08000100, 0xfe000104, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_ACC2 },
1220     { "ADDS", DspMeta21,
1221       0x0a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
1222     { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
1223       0x08000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1224     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
1225       0x02000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1226     { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
1227       0x0a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1228     { "ADDT", CoreMeta11|CoreMeta12|CoreMeta21,
1229       0x02000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1230     { "ADDST", CoreMeta11|CoreMeta12|CoreMeta21,
1231       0x0a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1232     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
1233       0x06000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1234     COND_INSN ("ADDS", "", 1, DspMeta21,
1235 	       0x0c0001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
1236     { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
1237       0x0e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1238     COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1239 	       0x04000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1240     COND_INSN ("ADDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1241 	       0x0c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1242     COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1243 	       0x06000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1244     COND_INSN ("ADDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1245 	       0x0e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1246     { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
1247       0x10000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1248     { "NEGS", CoreMeta11|CoreMeta12|CoreMeta21,
1249       0x18000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1250     { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
1251       0x12000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1252     { "NEGS", CoreMeta11|CoreMeta12|CoreMeta21,
1253       0x1a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1254     { "NEGT", CoreMeta11|CoreMeta12|CoreMeta21,
1255       0x12000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1256     { "NEGST", CoreMeta11|CoreMeta12|CoreMeta21,
1257       0x1a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1258     { "SUB", DspMeta21,
1259       0x10000100, 0xfe000104, INSN_DSP, ENC_DALU,
1260       DSP_ARGS_1|DSP_ARGS_ACC2|DSP_ARGS_XACC },
1261     { "SUB", DspMeta21,
1262       0x12000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
1263     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
1264       0x10000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1265     { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
1266       0x18000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
1267     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
1268       0x12000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1269     { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
1270       0x1a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1271     { "SUBT", CoreMeta11|CoreMeta12|CoreMeta21,
1272       0x12000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1273     { "SUBS", DspMeta21,
1274       0x18000100, 0xfe000104, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_ACC2 },
1275     { "SUBS", DspMeta21,
1276       0x1a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
1277     { "SUBST", CoreMeta11|CoreMeta12|CoreMeta21,
1278       0x1a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1279     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
1280       0x16000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1281     { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
1282       0x1e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1283     COND_INSN ("SUBS", "", 1, DspMeta21,
1284 	       0x1c0001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
1285     COND_INSN ("SUB", "", 1, DspMeta21,
1286 	       0x140001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
1287     COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1288 	       0x14000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1289     COND_INSN ("SUBS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1290 	       0x1c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1291     COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1292 	       0x16000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1293     COND_INSN ("SUBS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1294 	       0x1e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1295     { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
1296       0x20000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
1297     { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
1298       0x28000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
1299     { "ANDQ", CoreMeta11|CoreMeta12|CoreMeta21,
1300       0x20000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
1301     { "ANDSQ", CoreMeta11|CoreMeta12|CoreMeta21,
1302       0x28000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
1303     { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
1304       0x22000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1305     { "ANDMB", CoreMeta11|CoreMeta12|CoreMeta21,
1306       0x22000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1307     { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
1308       0x2a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1309     { "ANDSMB", CoreMeta11|CoreMeta12|CoreMeta21,
1310       0x2a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1311     { "ANDT", CoreMeta11|CoreMeta12|CoreMeta21,
1312       0x22000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1313     { "ANDMT", CoreMeta11|CoreMeta12|CoreMeta21,
1314       0x22000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1315     { "ANDST", CoreMeta11|CoreMeta12|CoreMeta21,
1316       0x2a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1317     { "ANDSMT", CoreMeta11|CoreMeta12|CoreMeta21,
1318       0x2a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1319     { "AND", DspMeta21,
1320       0x20000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
1321     { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
1322       0x26000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1323     { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
1324       0x2e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1325     { "ANDQ", CoreMeta11|CoreMeta12|CoreMeta21,
1326       0x26000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
1327     { "ANDSQ", CoreMeta11|CoreMeta12|CoreMeta21,
1328       0x2e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
1329     { "ANDQ", DspMeta21,
1330       0x20000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
1331     COND_INSN ("ANDQ", "", 1, DspMeta21,
1332 	       0x240001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
1333 	       DSP_ARGS_1|DSP_ARGS_QR),
1334     COND_INSN ("AND", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1335 	       0x24000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1336     { "ANDSQ", DspMeta21,
1337       0x28000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
1338     COND_INSN ("ANDSQ", "", 1, DspMeta21,
1339 	       0x2c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
1340 	       DSP_ARGS_1|DSP_ARGS_QR),
1341     COND_INSN ("ANDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1342 	       0x2c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1343     COND_INSN ("AND", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1344 	       0x26000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1345     COND_INSN ("ANDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1346 	       0x2e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1347     COND_INSN ("ANDQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1348 	       0x26000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
1349     COND_INSN ("ANDSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1350 	       0x2e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
1351     { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
1352       0x30000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
1353     { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
1354       0x38000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
1355     { "ORQ", CoreMeta11|CoreMeta12|CoreMeta21,
1356       0x30000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
1357     { "ORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
1358       0x38000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
1359     { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
1360       0x32000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1361     { "ORMB", CoreMeta11|CoreMeta12|CoreMeta21,
1362       0x32000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1363     { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
1364       0x3a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1365     { "ORSMB", CoreMeta11|CoreMeta12|CoreMeta21,
1366       0x3a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1367     { "ORT", CoreMeta11|CoreMeta12|CoreMeta21,
1368       0x32000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1369     { "ORMT", CoreMeta11|CoreMeta12|CoreMeta21,
1370       0x32000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1371     { "ORST", CoreMeta11|CoreMeta12|CoreMeta21,
1372       0x3a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1373     { "ORSMT", CoreMeta11|CoreMeta12|CoreMeta21,
1374       0x3a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1375     { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
1376       0x36000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1377     { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
1378       0x3e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1379     { "ORQ", CoreMeta11|CoreMeta12|CoreMeta21,
1380       0x36000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
1381     { "ORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
1382       0x3e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
1383     { "ORQ", DspMeta21,
1384       0x30000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
1385     COND_INSN ("ORQ", "", 1, DspMeta21,
1386 	       0x340001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
1387 	       DSP_ARGS_1|DSP_ARGS_QR),
1388     COND_INSN ("OR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1389 	       0x34000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1390     { "ORSQ", DspMeta21,
1391       0x38000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
1392     COND_INSN ("ORSQ", "", 1, DspMeta21,
1393 	       0x3c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
1394 	       DSP_ARGS_1|DSP_ARGS_QR),
1395     COND_INSN ("ORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1396 	       0x3c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1397     COND_INSN ("OR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1398 	       0x36000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1399     COND_INSN ("ORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1400 	       0x3e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1401     COND_INSN ("ORQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1402 	       0x36000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
1403     COND_INSN ("ORSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1404 	       0x3e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
1405     { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
1406       0x40000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
1407     { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
1408       0x48000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
1409     { "XORQ", CoreMeta11|CoreMeta12|CoreMeta21,
1410       0x40000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
1411     { "XORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
1412       0x48000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
1413     { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
1414       0x42000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1415     { "XORMB", CoreMeta11|CoreMeta12|CoreMeta21,
1416       0x42000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1417     { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
1418       0x4a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1419     { "XORSMB", CoreMeta11|CoreMeta12|CoreMeta21,
1420       0x4a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1421     { "XORT", CoreMeta11|CoreMeta12|CoreMeta21,
1422       0x42000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1423     { "XORMT", CoreMeta11|CoreMeta12|CoreMeta21,
1424       0x42000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1425     { "XORST", CoreMeta11|CoreMeta12|CoreMeta21,
1426       0x4a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1427     { "XORSMT", CoreMeta11|CoreMeta12|CoreMeta21,
1428       0x4a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1429     { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
1430       0x46000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1431     { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
1432       0x4e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1433     { "XORQ", CoreMeta11|CoreMeta12|CoreMeta21,
1434       0x46000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
1435     { "XORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
1436       0x4e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
1437     { "XORQ", DspMeta21,
1438       0x40000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
1439     COND_INSN ("XORQ", "", 1, DspMeta21,
1440 	       0x440001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
1441 	       DSP_ARGS_1|DSP_ARGS_QR),
1442     COND_INSN ("XOR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1443 	       0x44000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1444     { "XORSQ", DspMeta21,
1445       0x48000140, 0xfe000140, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
1446     COND_INSN ("XORSQ", "", 1, DspMeta21,
1447 	       0x4c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
1448 	       DSP_ARGS_1|DSP_ARGS_QR),
1449     COND_INSN ("XORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1450 	       0x4c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
1451     COND_INSN ("XOR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1452 	       0x46000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1453     COND_INSN ("XORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1454 	       0x4e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1455     COND_INSN ("XORQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1456 	       0x46000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
1457     COND_INSN ("XORSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1458 	       0x4e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
1459     { "LSL", CoreMeta11|CoreMeta12|CoreMeta21,
1460       0x50000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
1461     { "LSL", CoreMeta11|CoreMeta12|CoreMeta21,
1462       0x54000020, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
1463     COND_INSN ("LSL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1464 	       0x54000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
1465     { "LSLS", CoreMeta11|CoreMeta12|CoreMeta21,
1466       0x58000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
1467     { "LSLS", CoreMeta11|CoreMeta12|CoreMeta21,
1468       0x5c000020, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
1469     COND_INSN ("LSLS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1470 	       0x5c000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
1471     { "LSR", CoreMeta11|CoreMeta12|CoreMeta21,
1472       0x50000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
1473     { "LSR", CoreMeta11|CoreMeta12|CoreMeta21,
1474       0x54000060, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
1475     COND_INSN ("LSR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1476 	       0x54000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
1477     { "LSRS", CoreMeta11|CoreMeta12|CoreMeta21,
1478       0x58000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
1479     { "LSRS", CoreMeta11|CoreMeta12|CoreMeta21,
1480       0x5c000060, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
1481     COND_INSN ("LSRS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1482 	       0x5c000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
1483     { "ASL", CoreMeta11|CoreMeta12|CoreMeta21,
1484       0x50000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
1485     { "ASL", CoreMeta11|CoreMeta12|CoreMeta21,
1486       0x540000a0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
1487     COND_INSN ("ASL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1488 	       0x54000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
1489     { "ASLS", CoreMeta11|CoreMeta12|CoreMeta21,
1490       0x58000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
1491     { "ASLS", CoreMeta11|CoreMeta12|CoreMeta21,
1492       0x5c0000a0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
1493     COND_INSN ("ASLS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1494 	       0x5c000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
1495     { "ASR", CoreMeta11|CoreMeta12|CoreMeta21,
1496       0x500000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
1497     { "ASR", CoreMeta11|CoreMeta12|CoreMeta21,
1498       0x540000e0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
1499     COND_INSN ("ASR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1500 	       0x540000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
1501     { "ASRS", CoreMeta11|CoreMeta12|CoreMeta21,
1502       0x580000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
1503     { "ASRS", CoreMeta11|CoreMeta12|CoreMeta21,
1504       0x5c0000e0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
1505     COND_INSN ("ASRS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1506 	       0x5c0000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
1507     { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
1508       0x60000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
1509     { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
1510       0x60000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
1511     /* MUL is a synonym from MULD. */
1512     { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
1513       0x60000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
1514     { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
1515       0x62000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1516     { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
1517       0x62000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1518     { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
1519       0x62000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
1520     { "MULWT", CoreMeta11|CoreMeta12|CoreMeta21,
1521       0x62000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1522     { "MULDT", CoreMeta11|CoreMeta12|CoreMeta21,
1523       0x62000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1524     { "MULT", CoreMeta11|CoreMeta12|CoreMeta21,
1525       0x62000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
1526     { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
1527       0x64000020, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
1528     { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
1529       0x64000060, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
1530     { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
1531       0x64000060, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
1532     { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
1533       0x66000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1534     { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
1535       0x66000021, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1536     { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
1537       0x66000021, 0xfe000021, INSN_GP, ENC_ALU, 0 },
1538     COND_INSN ("MULW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1539 	       0x64000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
1540     COND_INSN ("MULD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1541 	       0x64000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
1542     COND_INSN ("MUL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1543 	       0x64000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
1544     COND_INSN ("MULW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1545 	       0x66000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1546     COND_INSN ("MULD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1547 	       0x66000001, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1548     COND_INSN ("MUL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1549 	       0x66000001, 0xfe00003f, INSN_GP, ENC_ALU, 0),
1550     { "MIN", CoreMeta11|CoreMeta12|CoreMeta21,
1551       0x70000020, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
1552     { "MAX", CoreMeta11|CoreMeta12|CoreMeta21,
1553       0x70000024, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
1554     { "FFB", CoreMeta11|CoreMeta12|CoreMeta21,
1555       0x70000004, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
1556     { "NORM", CoreMeta11|CoreMeta12|CoreMeta21,
1557       0x70000008, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
1558     { "ABS", CoreMeta11|CoreMeta12|CoreMeta21,
1559       0x70000028, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
1560     { "XSDB", CoreMeta11|CoreMeta12|CoreMeta21,
1561       0xaa000000, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
1562     { "XSDSB", CoreMeta11|CoreMeta12|CoreMeta21,
1563       0xaa000008, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
1564     { "XSDW", CoreMeta11|CoreMeta12|CoreMeta21,
1565       0xaa000002, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
1566     { "XSDSW", CoreMeta11|CoreMeta12|CoreMeta21,
1567       0xaa00000a, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
1568     { "RTDW", CoreMeta11|CoreMeta12|CoreMeta21,
1569       0xaa000006, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
1570     { "RTDSW", CoreMeta11|CoreMeta12|CoreMeta21,
1571       0xaa00000e, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
1572     { "NMIN", CoreMeta11|CoreMeta12|CoreMeta21,
1573       0x7000002c, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
1574 
1575     /* Condition setting operations */
1576     { "CMP", CoreMeta11|CoreMeta12|CoreMeta21,
1577       0x70000000, 0xfef801fe, INSN_GP, ENC_CMP, 0 },
1578     { "TST", CoreMeta11|CoreMeta12|CoreMeta21,
1579       0x78000000, 0xfef801fe, INSN_GP, ENC_CMP, 0 },
1580     { "CMP", CoreMeta11|CoreMeta12|CoreMeta21,
1581       0x72000000, 0xfe000005, INSN_GP, ENC_CMP, 0 },
1582     { "CMPMB", CoreMeta11|CoreMeta12|CoreMeta21,
1583       0x72000004, 0xfe000005, INSN_GP, ENC_CMP, 0 },
1584     { "TST", CoreMeta11|CoreMeta12|CoreMeta21,
1585       0x7a000000, 0xfe000005, INSN_GP, ENC_CMP, 0 },
1586     { "TSTMB", CoreMeta11|CoreMeta12|CoreMeta21,
1587       0x7a000004, 0xfe000005, INSN_GP, ENC_CMP, 0 },
1588     { "CMPT", CoreMeta11|CoreMeta12|CoreMeta21,
1589       0x72000001, 0xfe000007, INSN_GP, ENC_CMP, 0 },
1590     { "CMPMT", CoreMeta11|CoreMeta12|CoreMeta21,
1591       0x72000005, 0xfe000007, INSN_GP, ENC_CMP, 0 },
1592     { "TSTT", CoreMeta11|CoreMeta12|CoreMeta21,
1593       0x7a000001, 0xfe000007, INSN_GP, ENC_CMP, 0 },
1594     { "TSTMT", CoreMeta11|CoreMeta12|CoreMeta21,
1595       0x7a000005, 0xfe000007, INSN_GP, ENC_CMP, 0 },
1596     COND_INSN ("CMP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1597 	       0x74000000, 0xfef801fe, INSN_GP, ENC_CMP, 0),
1598     COND_INSN ("TST", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1599 	       0x7c000000, 0xfef801fe, INSN_GP, ENC_CMP, 0),
1600     COND_INSN ("CMP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1601 	       0x76000000, 0xfef8003e, INSN_GP, ENC_CMP, 0),
1602     COND_INSN ("TST", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1603 	       0x7e000000, 0xfef8003e, INSN_GP, ENC_CMP, 0),
1604 
1605     /* No-op (BNV) */
1606     { "NOP", CoreMeta11|CoreMeta12|CoreMeta21,
1607       0xa0fffffe, 0xffffffff, INSN_GP, ENC_NONE, 0 },
1608 
1609     /* Branch */
1610     COND_INSN ("B", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1611 	       0xa0000000, 0xff00001f, INSN_GP, ENC_BRANCH, 0),
1612     COND_INSN ("B", "R", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1613 	       0xa0000001, 0xff00001f, INSN_GP, ENC_BRANCH, 0),
1614 
1615     /* System operations */
1616     { "LOCK0", CoreMeta11|CoreMeta12|CoreMeta21,
1617       0xa8000000, 0xffffffff, INSN_GP, ENC_NONE, 0 },
1618     { "LOCK1", CoreMeta11|CoreMeta12|CoreMeta21,
1619       0xa8000001, 0xffffffff, INSN_GP, ENC_NONE, 0 },
1620     { "LOCK2", CoreMeta11|CoreMeta12|CoreMeta21,
1621       0xa8000003, 0xffffffff, INSN_GP, ENC_NONE, 0 },
1622     { "RTI", CoreMeta11|CoreMeta12|CoreMeta21,
1623       0xa3ffffff, 0xffffffff, INSN_GP, ENC_NONE, 0 },
1624     { "RTH", CoreMeta11|CoreMeta12|CoreMeta21,
1625       0xa37fffff, 0xffffffff, INSN_GP, ENC_NONE, 0 },
1626     COND_INSN ("KICK", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1627 	       0xa3000001, 0xff003e1f, INSN_GP, ENC_KICK, 0),
1628     { "SWITCH", CoreMeta11|CoreMeta12|CoreMeta21,
1629       0xaf000000, 0xff000000, INSN_GP, ENC_SWITCH, 0 },
1630     { "DCACHE", CoreMeta11|CoreMeta12|CoreMeta21,
1631       0xad000000, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
1632     { "ICACHEEXIT", CoreMeta12|CoreMeta21,
1633       0xae000000, 0xffffffff, INSN_GP, ENC_NONE, 0 },
1634     { "ICACHEEXITR", CoreMeta12|CoreMeta21,
1635       0xae000001, 0xffffffff, INSN_GP, ENC_NONE, 0 },
1636     { "ICACHE", CoreMeta12|CoreMeta21,
1637       0xae000000, 0xff0001e1, INSN_GP, ENC_ICACHE, 0 },
1638     { "ICACHER", CoreMeta12|CoreMeta21,
1639       0xae000001, 0xff0001e1, INSN_GP, ENC_ICACHE, 0 },
1640 
1641     /* Meta 2 instructions */
1642     { "CACHERD", CoreMeta21,
1643       0xad000081, 0xff000087, INSN_GP, ENC_CACHER, 0 },
1644     { "CACHERL", CoreMeta21,
1645       0xad000083, 0xff000087, INSN_GP, ENC_CACHER, 0 },
1646     { "CACHEWD", CoreMeta21,
1647       0xad000001, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
1648     { "CACHEWL", CoreMeta21,
1649       0xad000003, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
1650     COND_INSN ("DEFR", "", 1, CoreMeta21,
1651 	       0xa3002001, 0xff003e1f, INSN_GP, ENC_KICK, 0),
1652     { "BEXD", CoreMeta21,
1653       0xaa000004, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
1654     { "BEXSD", CoreMeta21,
1655       0xaa00000c, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
1656     { "BEXL", CoreMeta21,
1657       0xaa000014, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
1658     { "BEXSL", CoreMeta21,
1659       0xaa00001c, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
1660     { "LNKGETB", CoreMeta21,
1661       0xad000080, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
1662     { "LNKGETW", CoreMeta21,
1663       0xad000082, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
1664     { "LNKGETD", CoreMeta21,
1665       0xad000084, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
1666     { "LNKGETL", CoreMeta21,
1667       0xad000086, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
1668     COND_INSN ("LNKSETB", "", 1, CoreMeta21,
1669 	       0xa4000080, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
1670     COND_INSN ("LNKSETW", "", 1, CoreMeta21,
1671 	       0xa4000081, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
1672     COND_INSN ("LNKSETD", "", 1, CoreMeta21,
1673 	       0xa4000280, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
1674     COND_INSN ("LNKSETL", "", 1, CoreMeta21,
1675 	       0xa4000281, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
1676 
1677     /* Meta 2 FPU instructions */
1678 
1679     /* Port-to-unit MOV */
1680     COND_INSN ("MOVL", "", 1, FpuMeta21,
1681 	       0xa1800201, 0xfff83e1f, INSN_FPU, ENC_MOV_PORT, 0),
1682 
1683     /* Read pipeline drain */
1684     { "MMOVD", FpuMeta21,
1685       0xce000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 },
1686     { "MMOVL", FpuMeta21,
1687       0xcf000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 },
1688 
1689     /* FP data movement instructions */
1690     FCOND_INSN ("ABS", "", 1, FpuMeta21,
1691 		0xf0000080, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
1692     { "MMOVD", FpuMeta21,
1693       0xbe000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
1694     { "MMOVL", FpuMeta21,
1695       0xbf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
1696     { "MMOVD", FpuMeta21,
1697       0xce000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
1698     { "MMOVL", FpuMeta21,
1699       0xcf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
1700     { "MOVD", FpuMeta21,
1701       0x08000144, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
1702     { "MOVD", FpuMeta21,
1703       0x080001c4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
1704     { "MOVL", FpuMeta21,
1705       0x08000154, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
1706     { "MOVL", FpuMeta21,
1707       0x080001d4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
1708     FCOND_INSN ("MOV", "", 1, FpuMeta21,
1709 		0xf0000000, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
1710     { "MOV", FpuMeta21,
1711       0xf0000001, 0xff800001, INSN_FPU, ENC_FMOV_I, 0 },
1712     FCOND_INSN ("NEG", "", 1, FpuMeta21,
1713 		0xf0000100, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
1714     { "PACK", FpuMeta21,
1715       0xf0000180, 0xff8c21ff, INSN_FPU, ENC_FPACK, 0 },
1716     { "SWAP", FpuMeta21,
1717       0xf00001c0, 0xff8c7fff, INSN_FPU, ENC_FSWAP, 0 },
1718 
1719     /* FP comparison instructions */
1720     FCOND_INSN ("CMP", "", 1, FpuMeta21,
1721 		0xf3000000, 0xfff4201f, INSN_FPU, ENC_FCMP, 0),
1722     FCOND_INSN ("MAX", "", 1, FpuMeta21,
1723 		0xf3000081, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0),
1724     FCOND_INSN ("MIN", "", 1, FpuMeta21,
1725 		0xf3000001, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0),
1726 
1727     /* FP data conversion instructions */
1728     FCOND_INSN ("DTOF", "", 1, FpuMeta21,
1729 		0xf2000121, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
1730     FCOND_INSN ("FTOD", "", 1, FpuMeta21,
1731 		0xf2000101, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
1732     FCOND_INSN ("DTOH", "", 1, FpuMeta21,
1733 		0xf2000320, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
1734     FCOND_INSN ("FTOH", "", 1, FpuMeta21,
1735 		0xf2000300, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
1736     FCOND_INSN ("DTOI", "", 1, FpuMeta21,
1737 		0xf2002120, 0xff842fff, INSN_FPU, ENC_FCONV, 0),
1738     FCOND_INSN ("FTOI", "", 1, FpuMeta21,
1739 		0xf2002100, 0xff842fbf, INSN_FPU, ENC_FCONV, 0),
1740     FCOND_INSN ("DTOL", "", 1, FpuMeta21,
1741 		0xf2002320, 0xff8c6fff, INSN_FPU, ENC_FCONV, 0),
1742 
1743     FCOND_INSN ("DTOX", "", 1, FpuMeta21,
1744 		0xf2000020, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
1745     FCOND_INSN ("FTOX", "", 1, FpuMeta21,
1746 		0xf2000000, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
1747     FCOND_INSN ("DTOXL", "", 1, FpuMeta21,
1748 		0xf20000a0, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0),
1749 
1750     FCOND_INSN ("HTOD", "", 1, FpuMeta21,
1751 		0xf2000321, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
1752     FCOND_INSN ("HTOF", "", 1, FpuMeta21,
1753 		0xf2000301, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
1754     FCOND_INSN ("ITOD", "", 1, FpuMeta21,
1755 		0xf2002121, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
1756     FCOND_INSN ("ITOF", "", 1, FpuMeta21,
1757 		0xf2002101, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
1758     FCOND_INSN ("LTOD", "", 1, FpuMeta21,
1759 		0xf2002321, 0xff8c7fff, INSN_FPU, ENC_FCONV, 0),
1760 
1761     FCOND_INSN ("XTOD", "", 1, FpuMeta21,
1762 		0xf2000021, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
1763     FCOND_INSN ("XTOF", "", 1, FpuMeta21,
1764 		0xf2000001, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
1765     FCOND_INSN ("XLTOD", "", 1, FpuMeta21,
1766 		0xf20000a1, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0),
1767 
1768     /* FP basic arithmetic instructions */
1769     FCOND_INSN ("ADD", "", 1, FpuMeta21,
1770 		0xf1000001, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
1771     FCOND_INSN ("MUL", "", 1, FpuMeta21,
1772 		0xf1000100, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
1773     FCOND_INSN ("SUB", "", 1, FpuMeta21,
1774 		0xf1000101, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
1775 
1776     /* FP extended arithmetic instructions */
1777     { "MAC", FpuMeta21,
1778       0xf6000000, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 },
1779     { "MACS", FpuMeta21,
1780       0xf6000100, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 },
1781 
1782     { "MAR", FpuMeta21,
1783       0xf6000004, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 },
1784     { "MARS", FpuMeta21,
1785       0xf6000104, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 },
1786 
1787     { "MAW", FpuMeta21,
1788       0xf6000008, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
1789     { "MAWS", FpuMeta21,
1790       0xf6000108, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
1791     { "MAW1", FpuMeta21,
1792       0xf6000009, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
1793     { "MAWS1", FpuMeta21,
1794       0xf6000109, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
1795 
1796     FCOND_INSN ("MXA", "", 1, FpuMeta21,
1797 		0xf5000000, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
1798     FCOND_INSN ("MXAS", "", 1, FpuMeta21,
1799 		0xf5000100, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
1800     FCOND_INSN ("MXA1", "", 1, FpuMeta21,
1801 		0xf5000001, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
1802     FCOND_INSN ("MXAS1", "", 1, FpuMeta21,
1803 		0xf5000101, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
1804 
1805     { "MUZ", FpuMeta21,
1806       0xf6000010, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
1807     { "MUZS", FpuMeta21,
1808       0xf6000110, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
1809     { "MUZ1", FpuMeta21,
1810       0xf6000011, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
1811     { "MUZS1", FpuMeta21,
1812       0xf6000111, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
1813 
1814     { "RCP", FpuMeta21,
1815       0xf7000000, 0xff84391f, INSN_FPU, ENC_FREC, 0 },
1816     { "RSQ", FpuMeta21,
1817       0xf7000100, 0xff84391f, INSN_FPU, ENC_FREC, 0 },
1818 
1819     /* FP SIMD arithmetic instructions */
1820     { "ADDRE", FpuMeta21,
1821       0xf4000000, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
1822     { "MULRE", FpuMeta21,
1823       0xf4000001, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
1824     { "SUBRE", FpuMeta21,
1825       0xf4000100, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
1826 
1827     /* FP memory instructions */
1828     { "MGETD", FpuMeta21,
1829       0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1830     { "MGET", FpuMeta21,
1831       0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1832     { "MGETL", FpuMeta21,
1833       0xcf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1834 
1835     { "MSETD", FpuMeta21,
1836       0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1837     { "MSET", FpuMeta21,
1838       0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1839     { "MSETL", FpuMeta21,
1840       0xbf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
1841 
1842     /* FP accumulator memory instructions */
1843     { "GETL", FpuMeta21,
1844       0xcf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 },
1845     { "SETL", FpuMeta21,
1846       0xbf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 },
1847 
1848     /* DSP FPU data movement */
1849     { "MOV", DspMeta21|FpuMeta21,
1850       0x08000146, 0xfe0001ee, INSN_DSP_FPU, ENC_DALU,
1851       DSP_ARGS_2|DSP_ARGS_DSP_SRC1 },
1852     { "MOV", DspMeta21|FpuMeta21,
1853       0x080001c6, 0xfe0001ee, INSN_DSP_FPU, ENC_DALU,
1854       DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
1855 
1856     /* Unit-to-unit MOV */
1857     COND_INSN ("MOV", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1858 	       0xa3000000, 0xff00021f, INSN_GP, ENC_MOV_U2U, 0),
1859     COND_INSN ("TTMOV", "", 1, CoreMeta12|CoreMeta21,
1860 	       0xa3000201, 0xff00021f, INSN_GP, ENC_MOV_U2U, 0),
1861     COND_INSN ("SWAP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
1862 	       0xa3000200, 0xff00021f, INSN_GP, ENC_SWAP, 0),
1863 
1864     /* DSP memory instructions */
1865     { "GETD", DspMeta21,
1866       0x94000100, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
1867     { "SETD", DspMeta21,
1868       0x94000000, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
1869     { "GETL", DspMeta21,
1870       0x94000104, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
1871     { "SETL", DspMeta21,
1872       0x94000004, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
1873 
1874     /* DSP read pipeline prime/drain */
1875     { "MMOVD", DspMeta21,
1876       0xca000001, 0xff00001f, INSN_DSP, ENC_MMOV, 0 },
1877     { "MMOVL", DspMeta21,
1878       0xcb000001, 0xff00001f, INSN_DSP, ENC_MMOV, 0 },
1879     { "MMOVD", DspMeta21,
1880       0xcc000001, 0xff07c067, INSN_DSP, ENC_MMOV, 0 },
1881     { "MMOVL", DspMeta21,
1882       0xcd000001, 0xff07c067, INSN_DSP, ENC_MMOV, 0 },
1883 
1884     /* DSP Template instantiation */
1885     TEMPLATE_INSN (DspMeta21, 0x90000000, 0xff00000f, INSN_DSP),
1886     TEMPLATE_INSN (DspMeta21, 0x93000000, 0xff0001ff, INSN_DSP),
1887     TEMPLATE_INSN (DspMeta21, 0x95000000, 0xff00000f, INSN_DSP),
1888 
1889     { "AND", DspMeta21,
1890       0x22000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
1891     { "ANDS", DspMeta21,
1892       0x28000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
1893     { "ANDS", DspMeta21,
1894       0x2a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
1895     { "MAX", DspMeta21,
1896       0x70000124, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
1897     { "MIN", DspMeta21,
1898       0x70000120, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
1899     { "NMIN", DspMeta21,
1900       0x7000012c, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
1901     { "OR", DspMeta21,
1902       0x30000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
1903     { "OR", DspMeta21,
1904       0x32000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
1905     { "ORS", DspMeta21,
1906       0x38000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
1907     { "ORS", DspMeta21,
1908       0x3a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
1909     { "XOR", DspMeta21,
1910       0x40000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
1911     { "XOR", DspMeta21,
1912       0x42000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
1913     { "XORS", DspMeta21,
1914       0x48000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
1915     { "XORS", DspMeta21,
1916       0x4a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
1917     { "ADDB8", DspMeta21,
1918       0x20000108, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1919     { "ADDT8", DspMeta21,
1920       0x2000010c, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1921     { "ADDSB8", DspMeta21,
1922       0x28000108, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1923     { "ADDST8", DspMeta21,
1924       0x2800010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1925     { "MULB8", DspMeta21,
1926       0x40000108, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1927     { "MULT8", DspMeta21,
1928       0x4000010c, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1929     { "MULSB8", DspMeta21,
1930       0x48000108, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1931     { "MULST8", DspMeta21,
1932       0x4800010c, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1933     { "SUBB8", DspMeta21,
1934       0x30000108, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1935     { "SUBT8", DspMeta21,
1936       0x3000010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1937     { "SUBSB8", DspMeta21,
1938       0x38000108, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1939     { "SUBST8", DspMeta21,
1940       0x3800010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
1941     { "MUL", DspMeta21,
1942       0x60000100, 0xfe000100, INSN_DSP, ENC_DALU,
1943       DSP_ARGS_1|DSP_ARGS_DACC },
1944     { "MUL", DspMeta21,
1945       0x62000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
1946     { "ABS", DspMeta21,
1947       0x70000128, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
1948     { "FFB", DspMeta21,
1949       0x70000104, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
1950     { "NORM", DspMeta21,
1951       0x70000108, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
1952     { "CMP", DspMeta21,
1953       0x70000000, 0xfe0000ec, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
1954     { "CMP", DspMeta21,
1955       0x72000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
1956     { "TST", DspMeta21,
1957       0x78000100, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
1958     { "TST", DspMeta21,
1959       0x7a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
1960     { "MOV", DspMeta21,
1961       0x00000104, 0xfe078146, INSN_DSP, ENC_DALU,
1962       DSP_ARGS_2|DSP_ARGS_DSP_SRC1|DSP_ARGS_DSP_SRC2|DSP_ARGS_IMM },
1963     { "MOVS", DspMeta21,
1964       0x08000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
1965     { "MOV", DspMeta21,
1966       0x91000000, 0xff000000, INSN_DSP, ENC_DALU,
1967       DSP_ARGS_2|DSP_ARGS_DSP_SRC1|DSP_ARGS_IMM },
1968     { "MOV", DspMeta21,
1969       0x92000000, 0xff000000, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
1970     { "NEG", DspMeta21,
1971       0x10000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
1972     { "NEGS", DspMeta21,
1973       0x18000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
1974     { "XSDB", DspMeta21,
1975       0xaa000100, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
1976     { "XSD", DspMeta21,
1977       0xaa000100, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
1978     { "XSDW", DspMeta21,
1979       0xaa000102, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
1980     { "XSDSB", DspMeta21,
1981       0xaa000108, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
1982     { "XSDS", DspMeta21,
1983       0xaa000108, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
1984     { "XSDSW", DspMeta21,
1985       0xaa00010a, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
1986     { "LSL", DspMeta21,
1987       0x50000100, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
1988     { "LSR", DspMeta21,
1989       0x50000140, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
1990     { "ASL", DspMeta21,
1991       0x50000180, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
1992     { "ASR", DspMeta21,
1993       0x500001c0, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
1994     { "LSL", DspMeta21,
1995       0x54000120, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
1996     { "LSR", DspMeta21,
1997       0x54000160, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
1998     { "ASL", DspMeta21,
1999       0x540001a0, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
2000     { "ASR", DspMeta21,
2001       0x540001e0, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
2002     COND_INSN ("LSL", "", 1, DspMeta21,
2003 	       0x54000100, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
2004     COND_INSN ("LSR", "", 1, DspMeta21,
2005 	       0x54000140, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
2006     COND_INSN ("ASL", "", 1, DspMeta21,
2007 	       0x54000180, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
2008     COND_INSN ("ASR", "", 1, DspMeta21,
2009 	       0x540001c0, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
2010     { "LSLS", DspMeta21,
2011       0x58000100, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
2012     { "LSRS", DspMeta21,
2013       0x58000140, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
2014     { "ASLS", DspMeta21,
2015       0x58000180, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
2016     { "ASRS", DspMeta21,
2017       0x580001c0, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
2018     COND_INSN ("LSLS", "", 1, DspMeta21,
2019 	       0x5c000100, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
2020     COND_INSN ("LSRS", "", 1, DspMeta21,
2021 	       0x5c000140, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
2022     COND_INSN ("ASLS", "", 1, DspMeta21,
2023 	       0x5c000180, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
2024     COND_INSN ("ASRS", "", 1, DspMeta21,
2025 	       0x5c0001c0, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
2026     { "LSLS", DspMeta21,
2027       0x5c000120, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
2028     { "LSRS", DspMeta21,
2029       0x5c000160, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
2030     { "ASLS", DspMeta21,
2031       0x5c0001a0, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
2032     { "ASRS", DspMeta21,
2033       0x5c0001e0, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
2034     { "RTDW", DspMeta21,
2035       0xaa000106, 0xff00010e, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
2036     { "RTDSW", DspMeta21,
2037       0xaa00010e, 0xff00010e, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
2038   };
2039 
2040 #define UNIT_MASK                  0xf
2041 #define SHORT_UNIT_MASK            0x3
2042 #define EXT_BASE_REG_MASK          0x1
2043 #define REG_MASK                  0x1f
2044 #define CC_MASK                    0xf
2045 #define RMASK_MASK                0x7f
2046 #define GET_SET_IMM_MASK          0x3f
2047 #define GET_SET_IMM_BITS             6
2048 #define GET_SET_EXT_IMM_MASK     0xfff
2049 #define GET_SET_EXT_IMM_BITS        12
2050 #define DGET_SET_IMM_MASK          0x3
2051 #define DGET_SET_IMM_BITS            2
2052 #define MGET_MSET_MAX_REGS           8
2053 #define MMOV_MAX_REGS                8
2054 #define IMM16_MASK              0xffff
2055 #define IMM16_BITS                  16
2056 #define IMM19_MASK             0x7ffff
2057 #define IMM19_BITS                  19
2058 #define IMM8_MASK                 0xff
2059 #define IMM8_BITS                    8
2060 #define IMM24_MASK            0xffffff
2061 #define IMM24_BITS                  24
2062 #define IMM5_MASK                 0x1f
2063 #define IMM5_BITS                    5
2064 #define IMM6_MASK                 0x3f
2065 #define IMM6_BITS                    6
2066 #define IMM15_MASK              0x7fff
2067 #define IMM15_BITS                  15
2068 #define IMM4_MASK                 0x1f
2069 #define IMM4_BITS                    4
2070 #define CALLR_REG_MASK             0x7
2071 #define CPC_REG_MASK               0xf
2072 #define O2R_REG_MASK               0x7
2073 #define ACF_PART_MASK              0x3
2074 #define DSP_REG_MASK               0xf
2075 #define DSP_PART_MASK             0x17
2076 #define TEMPLATE_NUM_REGS            4
2077 #define TEMPLATE_REGS_MASK         0xf
2078 
2079 #define IS_TEMPLATE_DEF(insn) (insn->dsp_daoppame_flags & DSP_DAOPPAME_TEMP)
2080 
2081 unsigned int metag_get_set_size_bytes (unsigned int opcode);
2082 unsigned int metag_get_set_ext_size_bytes (unsigned int opcode);
2083 unsigned int metag_cond_set_size_bytes (unsigned int opcode);
2084 
2085 #ifdef __cplusplus
2086 }
2087 #endif
2088