1*a9fa9459Szrj /* Nios II opcode list for GAS, the GNU assembler. 2*a9fa9459Szrj Copyright (C) 2012-2016 Free Software Foundation, Inc. 3*a9fa9459Szrj Contributed by Nigel Gray (ngray@altera.com). 4*a9fa9459Szrj Contributed by Mentor Graphics, Inc. 5*a9fa9459Szrj 6*a9fa9459Szrj This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. 7*a9fa9459Szrj 8*a9fa9459Szrj GAS/GDB is free software; you can redistribute it and/or modify 9*a9fa9459Szrj it under the terms of the GNU General Public License as published by 10*a9fa9459Szrj the Free Software Foundation; either version 3, or (at your option) 11*a9fa9459Szrj any later version. 12*a9fa9459Szrj 13*a9fa9459Szrj GAS/GDB is distributed in the hope that it will be useful, 14*a9fa9459Szrj but WITHOUT ANY WARRANTY; without even the implied warranty of 15*a9fa9459Szrj MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*a9fa9459Szrj GNU General Public License for more details. 17*a9fa9459Szrj 18*a9fa9459Szrj You should have received a copy of the GNU General Public License 19*a9fa9459Szrj along with GAS or GDB; see the file COPYING3. If not, write to 20*a9fa9459Szrj the Free Software Foundation, 51 Franklin Street - Fifth Floor, 21*a9fa9459Szrj Boston, MA 02110-1301, USA. */ 22*a9fa9459Szrj 23*a9fa9459Szrj #ifndef _NIOS2_H_ 24*a9fa9459Szrj #define _NIOS2_H_ 25*a9fa9459Szrj 26*a9fa9459Szrj #include "bfd.h" 27*a9fa9459Szrj 28*a9fa9459Szrj #ifdef __cplusplus 29*a9fa9459Szrj extern "C" { 30*a9fa9459Szrj #endif 31*a9fa9459Szrj 32*a9fa9459Szrj /**************************************************************************** 33*a9fa9459Szrj * This file contains structures, bit masks and shift counts used 34*a9fa9459Szrj * by the GNU toolchain to define the Nios II instruction set and 35*a9fa9459Szrj * access various opcode fields. 36*a9fa9459Szrj ****************************************************************************/ 37*a9fa9459Szrj 38*a9fa9459Szrj /* Instruction encoding formats. */ 39*a9fa9459Szrj enum iw_format_type { 40*a9fa9459Szrj /* R1 formats. */ 41*a9fa9459Szrj iw_i_type, 42*a9fa9459Szrj iw_r_type, 43*a9fa9459Szrj iw_j_type, 44*a9fa9459Szrj iw_custom_type, 45*a9fa9459Szrj 46*a9fa9459Szrj /* 32-bit R2 formats. */ 47*a9fa9459Szrj iw_L26_type, 48*a9fa9459Szrj iw_F2I16_type, 49*a9fa9459Szrj iw_F2X4I12_type, 50*a9fa9459Szrj iw_F1X4I12_type, 51*a9fa9459Szrj iw_F1X4L17_type, 52*a9fa9459Szrj iw_F3X6L5_type, 53*a9fa9459Szrj iw_F2X6L10_type, 54*a9fa9459Szrj iw_F3X6_type, 55*a9fa9459Szrj iw_F3X8_type, 56*a9fa9459Szrj 57*a9fa9459Szrj /* 16-bit R2 formats. */ 58*a9fa9459Szrj iw_I10_type, 59*a9fa9459Szrj iw_T1I7_type, 60*a9fa9459Szrj iw_T2I4_type, 61*a9fa9459Szrj iw_T1X1I6_type, 62*a9fa9459Szrj iw_X1I7_type, 63*a9fa9459Szrj iw_L5I4X1_type, 64*a9fa9459Szrj iw_T2X1L3_type, 65*a9fa9459Szrj iw_T2X1I3_type, 66*a9fa9459Szrj iw_T3X1_type, 67*a9fa9459Szrj iw_T2X3_type, 68*a9fa9459Szrj iw_F1X1_type, 69*a9fa9459Szrj iw_X2L5_type, 70*a9fa9459Szrj iw_F1I5_type, 71*a9fa9459Szrj iw_F2_type 72*a9fa9459Szrj }; 73*a9fa9459Szrj 74*a9fa9459Szrj /* Identify different overflow situations for error messages. */ 75*a9fa9459Szrj enum overflow_type 76*a9fa9459Szrj { 77*a9fa9459Szrj call_target_overflow = 0, 78*a9fa9459Szrj branch_target_overflow, 79*a9fa9459Szrj address_offset_overflow, 80*a9fa9459Szrj signed_immed16_overflow, 81*a9fa9459Szrj unsigned_immed16_overflow, 82*a9fa9459Szrj unsigned_immed5_overflow, 83*a9fa9459Szrj signed_immed12_overflow, 84*a9fa9459Szrj custom_opcode_overflow, 85*a9fa9459Szrj enumeration_overflow, 86*a9fa9459Szrj no_overflow 87*a9fa9459Szrj }; 88*a9fa9459Szrj 89*a9fa9459Szrj /* This structure holds information for a particular instruction. 90*a9fa9459Szrj 91*a9fa9459Szrj The args field is a string describing the operands. The following 92*a9fa9459Szrj letters can appear in the args: 93*a9fa9459Szrj c - a 5-bit control register index 94*a9fa9459Szrj d - a 5-bit destination register index 95*a9fa9459Szrj s - a 5-bit left source register index 96*a9fa9459Szrj t - a 5-bit right source register index 97*a9fa9459Szrj D - a 3-bit encoded destination register 98*a9fa9459Szrj S - a 3-bit encoded left source register 99*a9fa9459Szrj T - a 3-bit encoded right source register 100*a9fa9459Szrj i - a 16-bit signed immediate 101*a9fa9459Szrj j - a 5-bit unsigned immediate 102*a9fa9459Szrj k - a (second) 5-bit unsigned immediate 103*a9fa9459Szrj l - a 8-bit custom instruction constant 104*a9fa9459Szrj m - a 26-bit unsigned immediate 105*a9fa9459Szrj o - a 16-bit signed pc-relative offset 106*a9fa9459Szrj u - a 16-bit unsigned immediate 107*a9fa9459Szrj I - a 12-bit signed immediate 108*a9fa9459Szrj M - a 6-bit unsigned immediate 109*a9fa9459Szrj N - a 6-bit unsigned immediate with 2-bit shift 110*a9fa9459Szrj O - a 10-bit signed pc-relative offset with 1-bit shift 111*a9fa9459Szrj P - a 7-bit signed pc-relative offset with 1-bit shift 112*a9fa9459Szrj U - a 7-bit unsigned immediate with 2-bit shift 113*a9fa9459Szrj V - a 5-bit unsigned immediate with 2-bit shift 114*a9fa9459Szrj W - a 4-bit unsigned immediate with 2-bit shift 115*a9fa9459Szrj X - a 4-bit unsigned immediate with 1-bit shift 116*a9fa9459Szrj Y - a 4-bit unsigned immediate 117*a9fa9459Szrj e - an immediate coded as an enumeration for addi.n/subi.n 118*a9fa9459Szrj f - an immediate coded as an enumeration for slli.n/srli.n 119*a9fa9459Szrj g - an immediate coded as an enumeration for andi.n 120*a9fa9459Szrj h - an immediate coded as an enumeration for movi.n 121*a9fa9459Szrj R - a reglist for ldwm/stwm or push.n/pop.n 122*a9fa9459Szrj B - a base register specifier and option list for ldwm/stwm 123*a9fa9459Szrj Literal ',', '(', and ')' characters may also appear in the args as 124*a9fa9459Szrj delimiters. 125*a9fa9459Szrj 126*a9fa9459Szrj Note that the args describe the semantics and assembly-language syntax 127*a9fa9459Szrj of the operands, not their encoding into the instruction word. 128*a9fa9459Szrj 129*a9fa9459Szrj The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection 130*a9fa9459Szrj of bits describing the instruction, notably any relevant hazard 131*a9fa9459Szrj information. 132*a9fa9459Szrj 133*a9fa9459Szrj When assembling, the match field contains the opcode template, which 134*a9fa9459Szrj is modified by the arguments to produce the actual opcode 135*a9fa9459Szrj that is emitted. If pinfo is INSN_MACRO, then this is 0. 136*a9fa9459Szrj 137*a9fa9459Szrj If pinfo is INSN_MACRO, the mask field stores the macro identifier. 138*a9fa9459Szrj Otherwise this is a bit mask for the relevant portions of the opcode 139*a9fa9459Szrj when disassembling. If the actual opcode anded with the match field 140*a9fa9459Szrj equals the opcode field, then we have found the correct instruction. */ 141*a9fa9459Szrj 142*a9fa9459Szrj struct nios2_opcode 143*a9fa9459Szrj { 144*a9fa9459Szrj const char *name; /* The name of the instruction. */ 145*a9fa9459Szrj const char *args; /* A string describing the arguments for this 146*a9fa9459Szrj instruction. */ 147*a9fa9459Szrj const char *args_test; /* Like args, but with an extra argument for 148*a9fa9459Szrj the expected opcode. */ 149*a9fa9459Szrj unsigned long num_args; /* The number of arguments the instruction 150*a9fa9459Szrj takes. */ 151*a9fa9459Szrj unsigned size; /* Size in bytes of the instruction. */ 152*a9fa9459Szrj enum iw_format_type format; /* Instruction format. */ 153*a9fa9459Szrj unsigned long match; /* The basic opcode for the instruction. */ 154*a9fa9459Szrj unsigned long mask; /* Mask for the opcode field of the 155*a9fa9459Szrj instruction. */ 156*a9fa9459Szrj unsigned long pinfo; /* Is this a real instruction or instruction 157*a9fa9459Szrj macro? */ 158*a9fa9459Szrj enum overflow_type overflow_msg; /* Used to generate informative 159*a9fa9459Szrj message when fixup overflows. */ 160*a9fa9459Szrj }; 161*a9fa9459Szrj 162*a9fa9459Szrj /* This value is used in the nios2_opcode.pinfo field to indicate that the 163*a9fa9459Szrj instruction is a macro or pseudo-op. This requires special treatment by 164*a9fa9459Szrj the assembler, and is used by the disassembler to determine whether to 165*a9fa9459Szrj check for a nop. */ 166*a9fa9459Szrj #define NIOS2_INSN_MACRO 0x80000000 167*a9fa9459Szrj #define NIOS2_INSN_MACRO_MOV 0x80000001 168*a9fa9459Szrj #define NIOS2_INSN_MACRO_MOVI 0x80000002 169*a9fa9459Szrj #define NIOS2_INSN_MACRO_MOVIA 0x80000004 170*a9fa9459Szrj 171*a9fa9459Szrj #define NIOS2_INSN_RELAXABLE 0x40000000 172*a9fa9459Szrj #define NIOS2_INSN_UBRANCH 0x00000010 173*a9fa9459Szrj #define NIOS2_INSN_CBRANCH 0x00000020 174*a9fa9459Szrj #define NIOS2_INSN_CALL 0x00000040 175*a9fa9459Szrj 176*a9fa9459Szrj #define NIOS2_INSN_OPTARG 0x00000080 177*a9fa9459Szrj 178*a9fa9459Szrj /* Register attributes. */ 179*a9fa9459Szrj #define REG_NORMAL (1<<0) /* Normal registers. */ 180*a9fa9459Szrj #define REG_CONTROL (1<<1) /* Control registers. */ 181*a9fa9459Szrj #define REG_COPROCESSOR (1<<2) /* For custom instructions. */ 182*a9fa9459Szrj #define REG_3BIT (1<<3) /* For R2 CDX instructions. */ 183*a9fa9459Szrj #define REG_LDWM (1<<4) /* For R2 ldwm/stwm. */ 184*a9fa9459Szrj #define REG_POP (1<<5) /* For R2 pop.n/push.n. */ 185*a9fa9459Szrj 186*a9fa9459Szrj struct nios2_reg 187*a9fa9459Szrj { 188*a9fa9459Szrj const char *name; 189*a9fa9459Szrj const int index; 190*a9fa9459Szrj unsigned long regtype; 191*a9fa9459Szrj }; 192*a9fa9459Szrj 193*a9fa9459Szrj /* Pull in the instruction field accessors, opcodes, and masks. */ 194*a9fa9459Szrj #include "nios2r1.h" 195*a9fa9459Szrj #include "nios2r2.h" 196*a9fa9459Szrj 197*a9fa9459Szrj /* These are the data structures used to hold the instruction information. */ 198*a9fa9459Szrj extern const struct nios2_opcode nios2_r1_opcodes[]; 199*a9fa9459Szrj extern const int nios2_num_r1_opcodes; 200*a9fa9459Szrj extern const struct nios2_opcode nios2_r2_opcodes[]; 201*a9fa9459Szrj extern const int nios2_num_r2_opcodes; 202*a9fa9459Szrj extern struct nios2_opcode *nios2_opcodes; 203*a9fa9459Szrj extern int nios2_num_opcodes; 204*a9fa9459Szrj 205*a9fa9459Szrj /* These are the data structures used to hold the register information. */ 206*a9fa9459Szrj extern const struct nios2_reg nios2_builtin_regs[]; 207*a9fa9459Szrj extern struct nios2_reg *nios2_regs; 208*a9fa9459Szrj extern const int nios2_num_builtin_regs; 209*a9fa9459Szrj extern int nios2_num_regs; 210*a9fa9459Szrj 211*a9fa9459Szrj /* Return the opcode descriptor for a single instruction. */ 212*a9fa9459Szrj extern const struct nios2_opcode * 213*a9fa9459Szrj nios2_find_opcode_hash (unsigned long, unsigned long); 214*a9fa9459Szrj 215*a9fa9459Szrj /* Lookup tables for R2 immediate decodings. */ 216*a9fa9459Szrj extern unsigned int nios2_r2_asi_n_mappings[]; 217*a9fa9459Szrj extern const int nios2_num_r2_asi_n_mappings; 218*a9fa9459Szrj extern unsigned int nios2_r2_shi_n_mappings[]; 219*a9fa9459Szrj extern const int nios2_num_r2_shi_n_mappings; 220*a9fa9459Szrj extern unsigned int nios2_r2_andi_n_mappings[]; 221*a9fa9459Szrj extern const int nios2_num_r2_andi_n_mappings; 222*a9fa9459Szrj 223*a9fa9459Szrj /* Lookup table for 3-bit register decodings. */ 224*a9fa9459Szrj extern int nios2_r2_reg3_mappings[]; 225*a9fa9459Szrj extern const int nios2_num_r2_reg3_mappings; 226*a9fa9459Szrj 227*a9fa9459Szrj /* Lookup table for REG_RANGE value list decodings. */ 228*a9fa9459Szrj extern unsigned long nios2_r2_reg_range_mappings[]; 229*a9fa9459Szrj extern const int nios2_num_r2_reg_range_mappings; 230*a9fa9459Szrj 231*a9fa9459Szrj #ifdef __cplusplus 232*a9fa9459Szrj } 233*a9fa9459Szrj #endif 234*a9fa9459Szrj 235*a9fa9459Szrj #endif /* _NIOS2_H */ 236