1 /* Nios II opcode list for GAS, the GNU assembler.
2    Copyright (C) 2012-2016 Free Software Foundation, Inc.
3    Contributed by Nigel Gray (ngray@altera.com).
4    Contributed by Mentor Graphics, Inc.
5 
6    This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
7 
8    GAS/GDB is free software; you can redistribute it and/or modify
9    it under the terms of the GNU General Public License as published by
10    the Free Software Foundation; either version 3, or (at your option)
11    any later version.
12 
13    GAS/GDB is distributed in the hope that it will be useful,
14    but WITHOUT ANY WARRANTY; without even the implied warranty of
15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16    GNU General Public License for more details.
17 
18    You should have received a copy of the GNU General Public License
19    along with GAS or GDB; see the file COPYING3.  If not, write to
20    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21    Boston, MA 02110-1301, USA.  */
22 
23 #ifndef _NIOS2_H_
24 #define _NIOS2_H_
25 
26 #include "bfd.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 /****************************************************************************
33  * This file contains structures, bit masks and shift counts used
34  * by the GNU toolchain to define the Nios II instruction set and
35  * access various opcode fields.
36  ****************************************************************************/
37 
38 /* Instruction encoding formats.  */
39 enum iw_format_type {
40   /* R1 formats.  */
41   iw_i_type,
42   iw_r_type,
43   iw_j_type,
44   iw_custom_type,
45 
46   /* 32-bit R2 formats.  */
47   iw_L26_type,
48   iw_F2I16_type,
49   iw_F2X4I12_type,
50   iw_F1X4I12_type,
51   iw_F1X4L17_type,
52   iw_F3X6L5_type,
53   iw_F2X6L10_type,
54   iw_F3X6_type,
55   iw_F3X8_type,
56 
57   /* 16-bit R2 formats.  */
58   iw_I10_type,
59   iw_T1I7_type,
60   iw_T2I4_type,
61   iw_T1X1I6_type,
62   iw_X1I7_type,
63   iw_L5I4X1_type,
64   iw_T2X1L3_type,
65   iw_T2X1I3_type,
66   iw_T3X1_type,
67   iw_T2X3_type,
68   iw_F1X1_type,
69   iw_X2L5_type,
70   iw_F1I5_type,
71   iw_F2_type
72 };
73 
74 /* Identify different overflow situations for error messages.  */
75 enum overflow_type
76 {
77   call_target_overflow = 0,
78   branch_target_overflow,
79   address_offset_overflow,
80   signed_immed16_overflow,
81   unsigned_immed16_overflow,
82   unsigned_immed5_overflow,
83   signed_immed12_overflow,
84   custom_opcode_overflow,
85   enumeration_overflow,
86   no_overflow
87 };
88 
89 /* This structure holds information for a particular instruction.
90 
91    The args field is a string describing the operands.  The following
92    letters can appear in the args:
93      c - a 5-bit control register index
94      d - a 5-bit destination register index
95      s - a 5-bit left source register index
96      t - a 5-bit right source register index
97      D - a 3-bit encoded destination register
98      S - a 3-bit encoded left source register
99      T - a 3-bit encoded right source register
100      i - a 16-bit signed immediate
101      j - a 5-bit unsigned immediate
102      k - a (second) 5-bit unsigned immediate
103      l - a 8-bit custom instruction constant
104      m - a 26-bit unsigned immediate
105      o - a 16-bit signed pc-relative offset
106      u - a 16-bit unsigned immediate
107      I - a 12-bit signed immediate
108      M - a 6-bit unsigned immediate
109      N - a 6-bit unsigned immediate with 2-bit shift
110      O - a 10-bit signed pc-relative offset with 1-bit shift
111      P - a 7-bit signed pc-relative offset with 1-bit shift
112      U - a 7-bit unsigned immediate with 2-bit shift
113      V - a 5-bit unsigned immediate with 2-bit shift
114      W - a 4-bit unsigned immediate with 2-bit shift
115      X - a 4-bit unsigned immediate with 1-bit shift
116      Y - a 4-bit unsigned immediate
117      e - an immediate coded as an enumeration for addi.n/subi.n
118      f - an immediate coded as an enumeration for slli.n/srli.n
119      g - an immediate coded as an enumeration for andi.n
120      h - an immediate coded as an enumeration for movi.n
121      R - a reglist for ldwm/stwm or push.n/pop.n
122      B - a base register specifier and option list for ldwm/stwm
123    Literal ',', '(', and ')' characters may also appear in the args as
124    delimiters.
125 
126    Note that the args describe the semantics and assembly-language syntax
127    of the operands, not their encoding into the instruction word.
128 
129    The pinfo field is INSN_MACRO for a macro.  Otherwise, it is a collection
130    of bits describing the instruction, notably any relevant hazard
131    information.
132 
133    When assembling, the match field contains the opcode template, which
134    is modified by the arguments to produce the actual opcode
135    that is emitted.  If pinfo is INSN_MACRO, then this is 0.
136 
137    If pinfo is INSN_MACRO, the mask field stores the macro identifier.
138    Otherwise this is a bit mask for the relevant portions of the opcode
139    when disassembling.  If the actual opcode anded with the match field
140    equals the opcode field, then we have found the correct instruction.  */
141 
142 struct nios2_opcode
143 {
144   const char *name;		/* The name of the instruction.  */
145   const char *args;		/* A string describing the arguments for this
146 				   instruction.  */
147   const char *args_test;	/* Like args, but with an extra argument for
148 				   the expected opcode.  */
149   unsigned long num_args;	/* The number of arguments the instruction
150 				   takes.  */
151   unsigned size;		/* Size in bytes of the instruction.  */
152   enum iw_format_type format;	/* Instruction format.  */
153   unsigned long match;		/* The basic opcode for the instruction.  */
154   unsigned long mask;		/* Mask for the opcode field of the
155 				   instruction.  */
156   unsigned long pinfo;		/* Is this a real instruction or instruction
157 				   macro?  */
158   enum overflow_type overflow_msg;  /* Used to generate informative
159 				       message when fixup overflows.  */
160 };
161 
162 /* This value is used in the nios2_opcode.pinfo field to indicate that the
163    instruction is a macro or pseudo-op.  This requires special treatment by
164    the assembler, and is used by the disassembler to determine whether to
165    check for a nop.  */
166 #define NIOS2_INSN_MACRO	0x80000000
167 #define NIOS2_INSN_MACRO_MOV	0x80000001
168 #define NIOS2_INSN_MACRO_MOVI	0x80000002
169 #define NIOS2_INSN_MACRO_MOVIA	0x80000004
170 
171 #define NIOS2_INSN_RELAXABLE	0x40000000
172 #define NIOS2_INSN_UBRANCH	0x00000010
173 #define NIOS2_INSN_CBRANCH	0x00000020
174 #define NIOS2_INSN_CALL		0x00000040
175 
176 #define NIOS2_INSN_OPTARG	0x00000080
177 
178 /* Register attributes.  */
179 #define REG_NORMAL	(1<<0)	/* Normal registers.  */
180 #define REG_CONTROL	(1<<1)  /* Control registers.  */
181 #define REG_COPROCESSOR	(1<<2)  /* For custom instructions.  */
182 #define REG_3BIT	(1<<3)  /* For R2 CDX instructions.  */
183 #define REG_LDWM	(1<<4)  /* For R2 ldwm/stwm.  */
184 #define REG_POP		(1<<5)  /* For R2 pop.n/push.n.  */
185 
186 struct nios2_reg
187 {
188   const char *name;
189   const int index;
190   unsigned long regtype;
191 };
192 
193 /* Pull in the instruction field accessors, opcodes, and masks.  */
194 #include "nios2r1.h"
195 #include "nios2r2.h"
196 
197 /* These are the data structures used to hold the instruction information.  */
198 extern const struct nios2_opcode nios2_r1_opcodes[];
199 extern const int nios2_num_r1_opcodes;
200 extern const struct nios2_opcode nios2_r2_opcodes[];
201 extern const int nios2_num_r2_opcodes;
202 extern struct nios2_opcode *nios2_opcodes;
203 extern int nios2_num_opcodes;
204 
205 /* These are the data structures used to hold the register information.  */
206 extern const struct nios2_reg nios2_builtin_regs[];
207 extern struct nios2_reg *nios2_regs;
208 extern const int nios2_num_builtin_regs;
209 extern int nios2_num_regs;
210 
211 /* Return the opcode descriptor for a single instruction.  */
212 extern const struct nios2_opcode *
213 nios2_find_opcode_hash (unsigned long, unsigned long);
214 
215 /* Lookup tables for R2 immediate decodings.  */
216 extern unsigned int nios2_r2_asi_n_mappings[];
217 extern const int nios2_num_r2_asi_n_mappings;
218 extern unsigned int nios2_r2_shi_n_mappings[];
219 extern const int nios2_num_r2_shi_n_mappings;
220 extern unsigned int nios2_r2_andi_n_mappings[];
221 extern const int nios2_num_r2_andi_n_mappings;
222 
223 /* Lookup table for 3-bit register decodings.  */
224 extern int nios2_r2_reg3_mappings[];
225 extern const int nios2_num_r2_reg3_mappings;
226 
227 /* Lookup table for REG_RANGE value list decodings.  */
228 extern unsigned long nios2_r2_reg_range_mappings[];
229 extern const int nios2_num_r2_reg_range_mappings;
230 
231 #ifdef __cplusplus
232 }
233 #endif
234 
235 #endif /* _NIOS2_H */
236