1*a9fa9459Szrj /* Declarations for Intel 80386 opcode table 2*a9fa9459Szrj Copyright (C) 2007-2016 Free Software Foundation, Inc. 3*a9fa9459Szrj 4*a9fa9459Szrj This file is part of the GNU opcodes library. 5*a9fa9459Szrj 6*a9fa9459Szrj This library is free software; you can redistribute it and/or modify 7*a9fa9459Szrj it under the terms of the GNU General Public License as published by 8*a9fa9459Szrj the Free Software Foundation; either version 3, or (at your option) 9*a9fa9459Szrj any later version. 10*a9fa9459Szrj 11*a9fa9459Szrj It is distributed in the hope that it will be useful, but WITHOUT 12*a9fa9459Szrj ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13*a9fa9459Szrj or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14*a9fa9459Szrj License for more details. 15*a9fa9459Szrj 16*a9fa9459Szrj You should have received a copy of the GNU General Public License 17*a9fa9459Szrj along with GAS; see the file COPYING. If not, write to the Free 18*a9fa9459Szrj Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19*a9fa9459Szrj 02110-1301, USA. */ 20*a9fa9459Szrj 21*a9fa9459Szrj #include "opcode/i386.h" 22*a9fa9459Szrj #ifdef HAVE_LIMITS_H 23*a9fa9459Szrj #include <limits.h> 24*a9fa9459Szrj #endif 25*a9fa9459Szrj 26*a9fa9459Szrj #ifndef CHAR_BIT 27*a9fa9459Szrj #define CHAR_BIT 8 28*a9fa9459Szrj #endif 29*a9fa9459Szrj 30*a9fa9459Szrj /* Position of cpu flags bitfiled. */ 31*a9fa9459Szrj 32*a9fa9459Szrj enum 33*a9fa9459Szrj { 34*a9fa9459Szrj /* i186 or better required */ 35*a9fa9459Szrj Cpu186 = 0, 36*a9fa9459Szrj /* i286 or better required */ 37*a9fa9459Szrj Cpu286, 38*a9fa9459Szrj /* i386 or better required */ 39*a9fa9459Szrj Cpu386, 40*a9fa9459Szrj /* i486 or better required */ 41*a9fa9459Szrj Cpu486, 42*a9fa9459Szrj /* i585 or better required */ 43*a9fa9459Szrj Cpu586, 44*a9fa9459Szrj /* i686 or better required */ 45*a9fa9459Szrj Cpu686, 46*a9fa9459Szrj /* CLFLUSH Instruction support required */ 47*a9fa9459Szrj CpuClflush, 48*a9fa9459Szrj /* NOP Instruction support required */ 49*a9fa9459Szrj CpuNop, 50*a9fa9459Szrj /* SYSCALL Instructions support required */ 51*a9fa9459Szrj CpuSYSCALL, 52*a9fa9459Szrj /* Floating point support required */ 53*a9fa9459Szrj Cpu8087, 54*a9fa9459Szrj /* i287 support required */ 55*a9fa9459Szrj Cpu287, 56*a9fa9459Szrj /* i387 support required */ 57*a9fa9459Szrj Cpu387, 58*a9fa9459Szrj /* i686 and floating point support required */ 59*a9fa9459Szrj Cpu687, 60*a9fa9459Szrj /* SSE3 and floating point support required */ 61*a9fa9459Szrj CpuFISTTP, 62*a9fa9459Szrj /* MMX support required */ 63*a9fa9459Szrj CpuMMX, 64*a9fa9459Szrj /* SSE support required */ 65*a9fa9459Szrj CpuSSE, 66*a9fa9459Szrj /* SSE2 support required */ 67*a9fa9459Szrj CpuSSE2, 68*a9fa9459Szrj /* 3dnow! support required */ 69*a9fa9459Szrj Cpu3dnow, 70*a9fa9459Szrj /* 3dnow! Extensions support required */ 71*a9fa9459Szrj Cpu3dnowA, 72*a9fa9459Szrj /* SSE3 support required */ 73*a9fa9459Szrj CpuSSE3, 74*a9fa9459Szrj /* VIA PadLock required */ 75*a9fa9459Szrj CpuPadLock, 76*a9fa9459Szrj /* AMD Secure Virtual Machine Ext-s required */ 77*a9fa9459Szrj CpuSVME, 78*a9fa9459Szrj /* VMX Instructions required */ 79*a9fa9459Szrj CpuVMX, 80*a9fa9459Szrj /* SMX Instructions required */ 81*a9fa9459Szrj CpuSMX, 82*a9fa9459Szrj /* SSSE3 support required */ 83*a9fa9459Szrj CpuSSSE3, 84*a9fa9459Szrj /* SSE4a support required */ 85*a9fa9459Szrj CpuSSE4a, 86*a9fa9459Szrj /* ABM New Instructions required */ 87*a9fa9459Szrj CpuABM, 88*a9fa9459Szrj /* SSE4.1 support required */ 89*a9fa9459Szrj CpuSSE4_1, 90*a9fa9459Szrj /* SSE4.2 support required */ 91*a9fa9459Szrj CpuSSE4_2, 92*a9fa9459Szrj /* AVX support required */ 93*a9fa9459Szrj CpuAVX, 94*a9fa9459Szrj /* AVX2 support required */ 95*a9fa9459Szrj CpuAVX2, 96*a9fa9459Szrj /* Intel AVX-512 Foundation Instructions support required */ 97*a9fa9459Szrj CpuAVX512F, 98*a9fa9459Szrj /* Intel AVX-512 Conflict Detection Instructions support required */ 99*a9fa9459Szrj CpuAVX512CD, 100*a9fa9459Szrj /* Intel AVX-512 Exponential and Reciprocal Instructions support 101*a9fa9459Szrj required */ 102*a9fa9459Szrj CpuAVX512ER, 103*a9fa9459Szrj /* Intel AVX-512 Prefetch Instructions support required */ 104*a9fa9459Szrj CpuAVX512PF, 105*a9fa9459Szrj /* Intel AVX-512 VL Instructions support required. */ 106*a9fa9459Szrj CpuAVX512VL, 107*a9fa9459Szrj /* Intel AVX-512 DQ Instructions support required. */ 108*a9fa9459Szrj CpuAVX512DQ, 109*a9fa9459Szrj /* Intel AVX-512 BW Instructions support required. */ 110*a9fa9459Szrj CpuAVX512BW, 111*a9fa9459Szrj /* Intel L1OM support required */ 112*a9fa9459Szrj CpuL1OM, 113*a9fa9459Szrj /* Intel K1OM support required */ 114*a9fa9459Szrj CpuK1OM, 115*a9fa9459Szrj /* Intel IAMCU support required */ 116*a9fa9459Szrj CpuIAMCU, 117*a9fa9459Szrj /* Xsave/xrstor New Instructions support required */ 118*a9fa9459Szrj CpuXsave, 119*a9fa9459Szrj /* Xsaveopt New Instructions support required */ 120*a9fa9459Szrj CpuXsaveopt, 121*a9fa9459Szrj /* AES support required */ 122*a9fa9459Szrj CpuAES, 123*a9fa9459Szrj /* PCLMUL support required */ 124*a9fa9459Szrj CpuPCLMUL, 125*a9fa9459Szrj /* FMA support required */ 126*a9fa9459Szrj CpuFMA, 127*a9fa9459Szrj /* FMA4 support required */ 128*a9fa9459Szrj CpuFMA4, 129*a9fa9459Szrj /* XOP support required */ 130*a9fa9459Szrj CpuXOP, 131*a9fa9459Szrj /* LWP support required */ 132*a9fa9459Szrj CpuLWP, 133*a9fa9459Szrj /* BMI support required */ 134*a9fa9459Szrj CpuBMI, 135*a9fa9459Szrj /* TBM support required */ 136*a9fa9459Szrj CpuTBM, 137*a9fa9459Szrj /* MOVBE Instruction support required */ 138*a9fa9459Szrj CpuMovbe, 139*a9fa9459Szrj /* CMPXCHG16B instruction support required. */ 140*a9fa9459Szrj CpuCX16, 141*a9fa9459Szrj /* EPT Instructions required */ 142*a9fa9459Szrj CpuEPT, 143*a9fa9459Szrj /* RDTSCP Instruction support required */ 144*a9fa9459Szrj CpuRdtscp, 145*a9fa9459Szrj /* FSGSBASE Instructions required */ 146*a9fa9459Szrj CpuFSGSBase, 147*a9fa9459Szrj /* RDRND Instructions required */ 148*a9fa9459Szrj CpuRdRnd, 149*a9fa9459Szrj /* F16C Instructions required */ 150*a9fa9459Szrj CpuF16C, 151*a9fa9459Szrj /* Intel BMI2 support required */ 152*a9fa9459Szrj CpuBMI2, 153*a9fa9459Szrj /* LZCNT support required */ 154*a9fa9459Szrj CpuLZCNT, 155*a9fa9459Szrj /* HLE support required */ 156*a9fa9459Szrj CpuHLE, 157*a9fa9459Szrj /* RTM support required */ 158*a9fa9459Szrj CpuRTM, 159*a9fa9459Szrj /* INVPCID Instructions required */ 160*a9fa9459Szrj CpuINVPCID, 161*a9fa9459Szrj /* VMFUNC Instruction required */ 162*a9fa9459Szrj CpuVMFUNC, 163*a9fa9459Szrj /* Intel MPX Instructions required */ 164*a9fa9459Szrj CpuMPX, 165*a9fa9459Szrj /* 64bit support available, used by -march= in assembler. */ 166*a9fa9459Szrj CpuLM, 167*a9fa9459Szrj /* RDRSEED instruction required. */ 168*a9fa9459Szrj CpuRDSEED, 169*a9fa9459Szrj /* Multi-presisionn add-carry instructions are required. */ 170*a9fa9459Szrj CpuADX, 171*a9fa9459Szrj /* Supports prefetchw and prefetch instructions. */ 172*a9fa9459Szrj CpuPRFCHW, 173*a9fa9459Szrj /* SMAP instructions required. */ 174*a9fa9459Szrj CpuSMAP, 175*a9fa9459Szrj /* SHA instructions required. */ 176*a9fa9459Szrj CpuSHA, 177*a9fa9459Szrj /* VREX support required */ 178*a9fa9459Szrj CpuVREX, 179*a9fa9459Szrj /* CLFLUSHOPT instruction required */ 180*a9fa9459Szrj CpuClflushOpt, 181*a9fa9459Szrj /* XSAVES/XRSTORS instruction required */ 182*a9fa9459Szrj CpuXSAVES, 183*a9fa9459Szrj /* XSAVEC instruction required */ 184*a9fa9459Szrj CpuXSAVEC, 185*a9fa9459Szrj /* PREFETCHWT1 instruction required */ 186*a9fa9459Szrj CpuPREFETCHWT1, 187*a9fa9459Szrj /* SE1 instruction required */ 188*a9fa9459Szrj CpuSE1, 189*a9fa9459Szrj /* CLWB instruction required */ 190*a9fa9459Szrj CpuCLWB, 191*a9fa9459Szrj /* PCOMMIT instruction required */ 192*a9fa9459Szrj CpuPCOMMIT, 193*a9fa9459Szrj /* Intel AVX-512 IFMA Instructions support required. */ 194*a9fa9459Szrj CpuAVX512IFMA, 195*a9fa9459Szrj /* Intel AVX-512 VBMI Instructions support required. */ 196*a9fa9459Szrj CpuAVX512VBMI, 197*a9fa9459Szrj /* mwaitx instruction required */ 198*a9fa9459Szrj CpuMWAITX, 199*a9fa9459Szrj /* Clzero instruction required */ 200*a9fa9459Szrj CpuCLZERO, 201*a9fa9459Szrj /* OSPKE instruction required */ 202*a9fa9459Szrj CpuOSPKE, 203*a9fa9459Szrj /* RDPID instruction required */ 204*a9fa9459Szrj CpuRDPID, 205*a9fa9459Szrj /* MMX register support required */ 206*a9fa9459Szrj CpuRegMMX, 207*a9fa9459Szrj /* XMM register support required */ 208*a9fa9459Szrj CpuRegXMM, 209*a9fa9459Szrj /* YMM register support required */ 210*a9fa9459Szrj CpuRegYMM, 211*a9fa9459Szrj /* ZMM register support required */ 212*a9fa9459Szrj CpuRegZMM, 213*a9fa9459Szrj /* Mask register support required */ 214*a9fa9459Szrj CpuRegMask, 215*a9fa9459Szrj /* 64bit support required */ 216*a9fa9459Szrj Cpu64, 217*a9fa9459Szrj /* Not supported in the 64bit mode */ 218*a9fa9459Szrj CpuNo64, 219*a9fa9459Szrj /* The last bitfield in i386_cpu_flags. */ 220*a9fa9459Szrj CpuMax = CpuNo64 221*a9fa9459Szrj }; 222*a9fa9459Szrj 223*a9fa9459Szrj #define CpuNumOfUints \ 224*a9fa9459Szrj (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) 225*a9fa9459Szrj #define CpuNumOfBits \ 226*a9fa9459Szrj (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) 227*a9fa9459Szrj 228*a9fa9459Szrj /* If you get a compiler error for zero width of the unused field, 229*a9fa9459Szrj comment it out. */ 230*a9fa9459Szrj #define CpuUnused (CpuMax + 1) 231*a9fa9459Szrj 232*a9fa9459Szrj /* We can check if an instruction is available with array instead 233*a9fa9459Szrj of bitfield. */ 234*a9fa9459Szrj typedef union i386_cpu_flags 235*a9fa9459Szrj { 236*a9fa9459Szrj struct 237*a9fa9459Szrj { 238*a9fa9459Szrj unsigned int cpui186:1; 239*a9fa9459Szrj unsigned int cpui286:1; 240*a9fa9459Szrj unsigned int cpui386:1; 241*a9fa9459Szrj unsigned int cpui486:1; 242*a9fa9459Szrj unsigned int cpui586:1; 243*a9fa9459Szrj unsigned int cpui686:1; 244*a9fa9459Szrj unsigned int cpuclflush:1; 245*a9fa9459Szrj unsigned int cpunop:1; 246*a9fa9459Szrj unsigned int cpusyscall:1; 247*a9fa9459Szrj unsigned int cpu8087:1; 248*a9fa9459Szrj unsigned int cpu287:1; 249*a9fa9459Szrj unsigned int cpu387:1; 250*a9fa9459Szrj unsigned int cpu687:1; 251*a9fa9459Szrj unsigned int cpufisttp:1; 252*a9fa9459Szrj unsigned int cpummx:1; 253*a9fa9459Szrj unsigned int cpusse:1; 254*a9fa9459Szrj unsigned int cpusse2:1; 255*a9fa9459Szrj unsigned int cpua3dnow:1; 256*a9fa9459Szrj unsigned int cpua3dnowa:1; 257*a9fa9459Szrj unsigned int cpusse3:1; 258*a9fa9459Szrj unsigned int cpupadlock:1; 259*a9fa9459Szrj unsigned int cpusvme:1; 260*a9fa9459Szrj unsigned int cpuvmx:1; 261*a9fa9459Szrj unsigned int cpusmx:1; 262*a9fa9459Szrj unsigned int cpussse3:1; 263*a9fa9459Szrj unsigned int cpusse4a:1; 264*a9fa9459Szrj unsigned int cpuabm:1; 265*a9fa9459Szrj unsigned int cpusse4_1:1; 266*a9fa9459Szrj unsigned int cpusse4_2:1; 267*a9fa9459Szrj unsigned int cpuavx:1; 268*a9fa9459Szrj unsigned int cpuavx2:1; 269*a9fa9459Szrj unsigned int cpuavx512f:1; 270*a9fa9459Szrj unsigned int cpuavx512cd:1; 271*a9fa9459Szrj unsigned int cpuavx512er:1; 272*a9fa9459Szrj unsigned int cpuavx512pf:1; 273*a9fa9459Szrj unsigned int cpuavx512vl:1; 274*a9fa9459Szrj unsigned int cpuavx512dq:1; 275*a9fa9459Szrj unsigned int cpuavx512bw:1; 276*a9fa9459Szrj unsigned int cpul1om:1; 277*a9fa9459Szrj unsigned int cpuk1om:1; 278*a9fa9459Szrj unsigned int cpuiamcu:1; 279*a9fa9459Szrj unsigned int cpuxsave:1; 280*a9fa9459Szrj unsigned int cpuxsaveopt:1; 281*a9fa9459Szrj unsigned int cpuaes:1; 282*a9fa9459Szrj unsigned int cpupclmul:1; 283*a9fa9459Szrj unsigned int cpufma:1; 284*a9fa9459Szrj unsigned int cpufma4:1; 285*a9fa9459Szrj unsigned int cpuxop:1; 286*a9fa9459Szrj unsigned int cpulwp:1; 287*a9fa9459Szrj unsigned int cpubmi:1; 288*a9fa9459Szrj unsigned int cputbm:1; 289*a9fa9459Szrj unsigned int cpumovbe:1; 290*a9fa9459Szrj unsigned int cpucx16:1; 291*a9fa9459Szrj unsigned int cpuept:1; 292*a9fa9459Szrj unsigned int cpurdtscp:1; 293*a9fa9459Szrj unsigned int cpufsgsbase:1; 294*a9fa9459Szrj unsigned int cpurdrnd:1; 295*a9fa9459Szrj unsigned int cpuf16c:1; 296*a9fa9459Szrj unsigned int cpubmi2:1; 297*a9fa9459Szrj unsigned int cpulzcnt:1; 298*a9fa9459Szrj unsigned int cpuhle:1; 299*a9fa9459Szrj unsigned int cpurtm:1; 300*a9fa9459Szrj unsigned int cpuinvpcid:1; 301*a9fa9459Szrj unsigned int cpuvmfunc:1; 302*a9fa9459Szrj unsigned int cpumpx:1; 303*a9fa9459Szrj unsigned int cpulm:1; 304*a9fa9459Szrj unsigned int cpurdseed:1; 305*a9fa9459Szrj unsigned int cpuadx:1; 306*a9fa9459Szrj unsigned int cpuprfchw:1; 307*a9fa9459Szrj unsigned int cpusmap:1; 308*a9fa9459Szrj unsigned int cpusha:1; 309*a9fa9459Szrj unsigned int cpuvrex:1; 310*a9fa9459Szrj unsigned int cpuclflushopt:1; 311*a9fa9459Szrj unsigned int cpuxsaves:1; 312*a9fa9459Szrj unsigned int cpuxsavec:1; 313*a9fa9459Szrj unsigned int cpuprefetchwt1:1; 314*a9fa9459Szrj unsigned int cpuse1:1; 315*a9fa9459Szrj unsigned int cpuclwb:1; 316*a9fa9459Szrj unsigned int cpupcommit:1; 317*a9fa9459Szrj unsigned int cpuavx512ifma:1; 318*a9fa9459Szrj unsigned int cpuavx512vbmi:1; 319*a9fa9459Szrj unsigned int cpumwaitx:1; 320*a9fa9459Szrj unsigned int cpuclzero:1; 321*a9fa9459Szrj unsigned int cpuospke:1; 322*a9fa9459Szrj unsigned int cpurdpid:1; 323*a9fa9459Szrj unsigned int cpuregmmx:1; 324*a9fa9459Szrj unsigned int cpuregxmm:1; 325*a9fa9459Szrj unsigned int cpuregymm:1; 326*a9fa9459Szrj unsigned int cpuregzmm:1; 327*a9fa9459Szrj unsigned int cpuregmask:1; 328*a9fa9459Szrj unsigned int cpu64:1; 329*a9fa9459Szrj unsigned int cpuno64:1; 330*a9fa9459Szrj #ifdef CpuUnused 331*a9fa9459Szrj unsigned int unused:(CpuNumOfBits - CpuUnused); 332*a9fa9459Szrj #endif 333*a9fa9459Szrj } bitfield; 334*a9fa9459Szrj unsigned int array[CpuNumOfUints]; 335*a9fa9459Szrj } i386_cpu_flags; 336*a9fa9459Szrj 337*a9fa9459Szrj /* Position of opcode_modifier bits. */ 338*a9fa9459Szrj 339*a9fa9459Szrj enum 340*a9fa9459Szrj { 341*a9fa9459Szrj /* has direction bit. */ 342*a9fa9459Szrj D = 0, 343*a9fa9459Szrj /* set if operands can be words or dwords encoded the canonical way */ 344*a9fa9459Szrj W, 345*a9fa9459Szrj /* Skip the current insn and use the next insn in i386-opc.tbl to swap 346*a9fa9459Szrj operand in encoding. */ 347*a9fa9459Szrj S, 348*a9fa9459Szrj /* insn has a modrm byte. */ 349*a9fa9459Szrj Modrm, 350*a9fa9459Szrj /* register is in low 3 bits of opcode */ 351*a9fa9459Szrj ShortForm, 352*a9fa9459Szrj /* special case for jump insns. */ 353*a9fa9459Szrj Jump, 354*a9fa9459Szrj /* call and jump */ 355*a9fa9459Szrj JumpDword, 356*a9fa9459Szrj /* loop and jecxz */ 357*a9fa9459Szrj JumpByte, 358*a9fa9459Szrj /* special case for intersegment leaps/calls */ 359*a9fa9459Szrj JumpInterSegment, 360*a9fa9459Szrj /* FP insn memory format bit, sized by 0x4 */ 361*a9fa9459Szrj FloatMF, 362*a9fa9459Szrj /* src/dest swap for floats. */ 363*a9fa9459Szrj FloatR, 364*a9fa9459Szrj /* has float insn direction bit. */ 365*a9fa9459Szrj FloatD, 366*a9fa9459Szrj /* needs size prefix if in 32-bit mode */ 367*a9fa9459Szrj Size16, 368*a9fa9459Szrj /* needs size prefix if in 16-bit mode */ 369*a9fa9459Szrj Size32, 370*a9fa9459Szrj /* needs size prefix if in 64-bit mode */ 371*a9fa9459Szrj Size64, 372*a9fa9459Szrj /* check register size. */ 373*a9fa9459Szrj CheckRegSize, 374*a9fa9459Szrj /* instruction ignores operand size prefix and in Intel mode ignores 375*a9fa9459Szrj mnemonic size suffix check. */ 376*a9fa9459Szrj IgnoreSize, 377*a9fa9459Szrj /* default insn size depends on mode */ 378*a9fa9459Szrj DefaultSize, 379*a9fa9459Szrj /* b suffix on instruction illegal */ 380*a9fa9459Szrj No_bSuf, 381*a9fa9459Szrj /* w suffix on instruction illegal */ 382*a9fa9459Szrj No_wSuf, 383*a9fa9459Szrj /* l suffix on instruction illegal */ 384*a9fa9459Szrj No_lSuf, 385*a9fa9459Szrj /* s suffix on instruction illegal */ 386*a9fa9459Szrj No_sSuf, 387*a9fa9459Szrj /* q suffix on instruction illegal */ 388*a9fa9459Szrj No_qSuf, 389*a9fa9459Szrj /* long double suffix on instruction illegal */ 390*a9fa9459Szrj No_ldSuf, 391*a9fa9459Szrj /* instruction needs FWAIT */ 392*a9fa9459Szrj FWait, 393*a9fa9459Szrj /* quick test for string instructions */ 394*a9fa9459Szrj IsString, 395*a9fa9459Szrj /* quick test if branch instruction is MPX supported */ 396*a9fa9459Szrj BNDPrefixOk, 397*a9fa9459Szrj /* quick test for lockable instructions */ 398*a9fa9459Szrj IsLockable, 399*a9fa9459Szrj /* fake an extra reg operand for clr, imul and special register 400*a9fa9459Szrj processing for some instructions. */ 401*a9fa9459Szrj RegKludge, 402*a9fa9459Szrj /* The first operand must be xmm0 */ 403*a9fa9459Szrj FirstXmm0, 404*a9fa9459Szrj /* An implicit xmm0 as the first operand */ 405*a9fa9459Szrj Implicit1stXmm0, 406*a9fa9459Szrj /* The HLE prefix is OK: 407*a9fa9459Szrj 1. With a LOCK prefix. 408*a9fa9459Szrj 2. With or without a LOCK prefix. 409*a9fa9459Szrj 3. With a RELEASE (0xf3) prefix. 410*a9fa9459Szrj */ 411*a9fa9459Szrj #define HLEPrefixNone 0 412*a9fa9459Szrj #define HLEPrefixLock 1 413*a9fa9459Szrj #define HLEPrefixAny 2 414*a9fa9459Szrj #define HLEPrefixRelease 3 415*a9fa9459Szrj HLEPrefixOk, 416*a9fa9459Szrj /* An instruction on which a "rep" prefix is acceptable. */ 417*a9fa9459Szrj RepPrefixOk, 418*a9fa9459Szrj /* Convert to DWORD */ 419*a9fa9459Szrj ToDword, 420*a9fa9459Szrj /* Convert to QWORD */ 421*a9fa9459Szrj ToQword, 422*a9fa9459Szrj /* Address prefix changes operand 0 */ 423*a9fa9459Szrj AddrPrefixOp0, 424*a9fa9459Szrj /* opcode is a prefix */ 425*a9fa9459Szrj IsPrefix, 426*a9fa9459Szrj /* instruction has extension in 8 bit imm */ 427*a9fa9459Szrj ImmExt, 428*a9fa9459Szrj /* instruction don't need Rex64 prefix. */ 429*a9fa9459Szrj NoRex64, 430*a9fa9459Szrj /* instruction require Rex64 prefix. */ 431*a9fa9459Szrj Rex64, 432*a9fa9459Szrj /* deprecated fp insn, gets a warning */ 433*a9fa9459Szrj Ugh, 434*a9fa9459Szrj /* insn has VEX prefix: 435*a9fa9459Szrj 1: 128bit VEX prefix. 436*a9fa9459Szrj 2: 256bit VEX prefix. 437*a9fa9459Szrj 3: Scalar VEX prefix. 438*a9fa9459Szrj */ 439*a9fa9459Szrj #define VEX128 1 440*a9fa9459Szrj #define VEX256 2 441*a9fa9459Szrj #define VEXScalar 3 442*a9fa9459Szrj Vex, 443*a9fa9459Szrj /* How to encode VEX.vvvv: 444*a9fa9459Szrj 0: VEX.vvvv must be 1111b. 445*a9fa9459Szrj 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where 446*a9fa9459Szrj the content of source registers will be preserved. 447*a9fa9459Szrj VEX.DDS. The second register operand is encoded in VEX.vvvv 448*a9fa9459Szrj where the content of first source register will be overwritten 449*a9fa9459Szrj by the result. 450*a9fa9459Szrj VEX.NDD2. The second destination register operand is encoded in 451*a9fa9459Szrj VEX.vvvv for instructions with 2 destination register operands. 452*a9fa9459Szrj For assembler, there are no difference between VEX.NDS, VEX.DDS 453*a9fa9459Szrj and VEX.NDD2. 454*a9fa9459Szrj 2. VEX.NDD. Register destination is encoded in VEX.vvvv for 455*a9fa9459Szrj instructions with 1 destination register operand. 456*a9fa9459Szrj 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one 457*a9fa9459Szrj of the operands can access a memory location. 458*a9fa9459Szrj */ 459*a9fa9459Szrj #define VEXXDS 1 460*a9fa9459Szrj #define VEXNDD 2 461*a9fa9459Szrj #define VEXLWP 3 462*a9fa9459Szrj VexVVVV, 463*a9fa9459Szrj /* How the VEX.W bit is used: 464*a9fa9459Szrj 0: Set by the REX.W bit. 465*a9fa9459Szrj 1: VEX.W0. Should always be 0. 466*a9fa9459Szrj 2: VEX.W1. Should always be 1. 467*a9fa9459Szrj */ 468*a9fa9459Szrj #define VEXW0 1 469*a9fa9459Szrj #define VEXW1 2 470*a9fa9459Szrj VexW, 471*a9fa9459Szrj /* VEX opcode prefix: 472*a9fa9459Szrj 0: VEX 0x0F opcode prefix. 473*a9fa9459Szrj 1: VEX 0x0F38 opcode prefix. 474*a9fa9459Szrj 2: VEX 0x0F3A opcode prefix 475*a9fa9459Szrj 3: XOP 0x08 opcode prefix. 476*a9fa9459Szrj 4: XOP 0x09 opcode prefix 477*a9fa9459Szrj 5: XOP 0x0A opcode prefix. 478*a9fa9459Szrj */ 479*a9fa9459Szrj #define VEX0F 0 480*a9fa9459Szrj #define VEX0F38 1 481*a9fa9459Szrj #define VEX0F3A 2 482*a9fa9459Szrj #define XOP08 3 483*a9fa9459Szrj #define XOP09 4 484*a9fa9459Szrj #define XOP0A 5 485*a9fa9459Szrj VexOpcode, 486*a9fa9459Szrj /* number of VEX source operands: 487*a9fa9459Szrj 0: <= 2 source operands. 488*a9fa9459Szrj 1: 2 XOP source operands. 489*a9fa9459Szrj 2: 3 source operands. 490*a9fa9459Szrj */ 491*a9fa9459Szrj #define XOP2SOURCES 1 492*a9fa9459Szrj #define VEX3SOURCES 2 493*a9fa9459Szrj VexSources, 494*a9fa9459Szrj /* instruction has VEX 8 bit imm */ 495*a9fa9459Szrj VexImmExt, 496*a9fa9459Szrj /* Instruction with vector SIB byte: 497*a9fa9459Szrj 1: 128bit vector register. 498*a9fa9459Szrj 2: 256bit vector register. 499*a9fa9459Szrj 3: 512bit vector register. 500*a9fa9459Szrj */ 501*a9fa9459Szrj #define VecSIB128 1 502*a9fa9459Szrj #define VecSIB256 2 503*a9fa9459Szrj #define VecSIB512 3 504*a9fa9459Szrj VecSIB, 505*a9fa9459Szrj /* SSE to AVX support required */ 506*a9fa9459Szrj SSE2AVX, 507*a9fa9459Szrj /* No AVX equivalent */ 508*a9fa9459Szrj NoAVX, 509*a9fa9459Szrj 510*a9fa9459Szrj /* insn has EVEX prefix: 511*a9fa9459Szrj 1: 512bit EVEX prefix. 512*a9fa9459Szrj 2: 128bit EVEX prefix. 513*a9fa9459Szrj 3: 256bit EVEX prefix. 514*a9fa9459Szrj 4: Length-ignored (LIG) EVEX prefix. 515*a9fa9459Szrj */ 516*a9fa9459Szrj #define EVEX512 1 517*a9fa9459Szrj #define EVEX128 2 518*a9fa9459Szrj #define EVEX256 3 519*a9fa9459Szrj #define EVEXLIG 4 520*a9fa9459Szrj EVex, 521*a9fa9459Szrj 522*a9fa9459Szrj /* AVX512 masking support: 523*a9fa9459Szrj 1: Zeroing-masking. 524*a9fa9459Szrj 2: Merging-masking. 525*a9fa9459Szrj 3: Both zeroing and merging masking. 526*a9fa9459Szrj */ 527*a9fa9459Szrj #define ZEROING_MASKING 1 528*a9fa9459Szrj #define MERGING_MASKING 2 529*a9fa9459Szrj #define BOTH_MASKING 3 530*a9fa9459Szrj Masking, 531*a9fa9459Szrj 532*a9fa9459Szrj /* Input element size of vector insn: 533*a9fa9459Szrj 0: 32bit. 534*a9fa9459Szrj 1: 64bit. 535*a9fa9459Szrj */ 536*a9fa9459Szrj VecESize, 537*a9fa9459Szrj 538*a9fa9459Szrj /* Broadcast factor. 539*a9fa9459Szrj 0: No broadcast. 540*a9fa9459Szrj 1: 1to16 broadcast. 541*a9fa9459Szrj 2: 1to8 broadcast. 542*a9fa9459Szrj */ 543*a9fa9459Szrj #define NO_BROADCAST 0 544*a9fa9459Szrj #define BROADCAST_1TO16 1 545*a9fa9459Szrj #define BROADCAST_1TO8 2 546*a9fa9459Szrj #define BROADCAST_1TO4 3 547*a9fa9459Szrj #define BROADCAST_1TO2 4 548*a9fa9459Szrj Broadcast, 549*a9fa9459Szrj 550*a9fa9459Szrj /* Static rounding control is supported. */ 551*a9fa9459Szrj StaticRounding, 552*a9fa9459Szrj 553*a9fa9459Szrj /* Supress All Exceptions is supported. */ 554*a9fa9459Szrj SAE, 555*a9fa9459Szrj 556*a9fa9459Szrj /* Copressed Disp8*N attribute. */ 557*a9fa9459Szrj Disp8MemShift, 558*a9fa9459Szrj 559*a9fa9459Szrj /* Default mask isn't allowed. */ 560*a9fa9459Szrj NoDefMask, 561*a9fa9459Szrj 562*a9fa9459Szrj /* Compatible with old (<= 2.8.1) versions of gcc */ 563*a9fa9459Szrj OldGcc, 564*a9fa9459Szrj /* AT&T mnemonic. */ 565*a9fa9459Szrj ATTMnemonic, 566*a9fa9459Szrj /* AT&T syntax. */ 567*a9fa9459Szrj ATTSyntax, 568*a9fa9459Szrj /* Intel syntax. */ 569*a9fa9459Szrj IntelSyntax, 570*a9fa9459Szrj /* AMD64. */ 571*a9fa9459Szrj AMD64, 572*a9fa9459Szrj /* Intel64. */ 573*a9fa9459Szrj Intel64, 574*a9fa9459Szrj /* The last bitfield in i386_opcode_modifier. */ 575*a9fa9459Szrj Opcode_Modifier_Max 576*a9fa9459Szrj }; 577*a9fa9459Szrj 578*a9fa9459Szrj typedef struct i386_opcode_modifier 579*a9fa9459Szrj { 580*a9fa9459Szrj unsigned int d:1; 581*a9fa9459Szrj unsigned int w:1; 582*a9fa9459Szrj unsigned int s:1; 583*a9fa9459Szrj unsigned int modrm:1; 584*a9fa9459Szrj unsigned int shortform:1; 585*a9fa9459Szrj unsigned int jump:1; 586*a9fa9459Szrj unsigned int jumpdword:1; 587*a9fa9459Szrj unsigned int jumpbyte:1; 588*a9fa9459Szrj unsigned int jumpintersegment:1; 589*a9fa9459Szrj unsigned int floatmf:1; 590*a9fa9459Szrj unsigned int floatr:1; 591*a9fa9459Szrj unsigned int floatd:1; 592*a9fa9459Szrj unsigned int size16:1; 593*a9fa9459Szrj unsigned int size32:1; 594*a9fa9459Szrj unsigned int size64:1; 595*a9fa9459Szrj unsigned int checkregsize:1; 596*a9fa9459Szrj unsigned int ignoresize:1; 597*a9fa9459Szrj unsigned int defaultsize:1; 598*a9fa9459Szrj unsigned int no_bsuf:1; 599*a9fa9459Szrj unsigned int no_wsuf:1; 600*a9fa9459Szrj unsigned int no_lsuf:1; 601*a9fa9459Szrj unsigned int no_ssuf:1; 602*a9fa9459Szrj unsigned int no_qsuf:1; 603*a9fa9459Szrj unsigned int no_ldsuf:1; 604*a9fa9459Szrj unsigned int fwait:1; 605*a9fa9459Szrj unsigned int isstring:1; 606*a9fa9459Szrj unsigned int bndprefixok:1; 607*a9fa9459Szrj unsigned int islockable:1; 608*a9fa9459Szrj unsigned int regkludge:1; 609*a9fa9459Szrj unsigned int firstxmm0:1; 610*a9fa9459Szrj unsigned int implicit1stxmm0:1; 611*a9fa9459Szrj unsigned int hleprefixok:2; 612*a9fa9459Szrj unsigned int repprefixok:1; 613*a9fa9459Szrj unsigned int todword:1; 614*a9fa9459Szrj unsigned int toqword:1; 615*a9fa9459Szrj unsigned int addrprefixop0:1; 616*a9fa9459Szrj unsigned int isprefix:1; 617*a9fa9459Szrj unsigned int immext:1; 618*a9fa9459Szrj unsigned int norex64:1; 619*a9fa9459Szrj unsigned int rex64:1; 620*a9fa9459Szrj unsigned int ugh:1; 621*a9fa9459Szrj unsigned int vex:2; 622*a9fa9459Szrj unsigned int vexvvvv:2; 623*a9fa9459Szrj unsigned int vexw:2; 624*a9fa9459Szrj unsigned int vexopcode:3; 625*a9fa9459Szrj unsigned int vexsources:2; 626*a9fa9459Szrj unsigned int veximmext:1; 627*a9fa9459Szrj unsigned int vecsib:2; 628*a9fa9459Szrj unsigned int sse2avx:1; 629*a9fa9459Szrj unsigned int noavx:1; 630*a9fa9459Szrj unsigned int evex:3; 631*a9fa9459Szrj unsigned int masking:2; 632*a9fa9459Szrj unsigned int vecesize:1; 633*a9fa9459Szrj unsigned int broadcast:3; 634*a9fa9459Szrj unsigned int staticrounding:1; 635*a9fa9459Szrj unsigned int sae:1; 636*a9fa9459Szrj unsigned int disp8memshift:3; 637*a9fa9459Szrj unsigned int nodefmask:1; 638*a9fa9459Szrj unsigned int oldgcc:1; 639*a9fa9459Szrj unsigned int attmnemonic:1; 640*a9fa9459Szrj unsigned int attsyntax:1; 641*a9fa9459Szrj unsigned int intelsyntax:1; 642*a9fa9459Szrj unsigned int amd64:1; 643*a9fa9459Szrj unsigned int intel64:1; 644*a9fa9459Szrj } i386_opcode_modifier; 645*a9fa9459Szrj 646*a9fa9459Szrj /* Position of operand_type bits. */ 647*a9fa9459Szrj 648*a9fa9459Szrj enum 649*a9fa9459Szrj { 650*a9fa9459Szrj /* 8bit register */ 651*a9fa9459Szrj Reg8 = 0, 652*a9fa9459Szrj /* 16bit register */ 653*a9fa9459Szrj Reg16, 654*a9fa9459Szrj /* 32bit register */ 655*a9fa9459Szrj Reg32, 656*a9fa9459Szrj /* 64bit register */ 657*a9fa9459Szrj Reg64, 658*a9fa9459Szrj /* Floating pointer stack register */ 659*a9fa9459Szrj FloatReg, 660*a9fa9459Szrj /* MMX register */ 661*a9fa9459Szrj RegMMX, 662*a9fa9459Szrj /* SSE register */ 663*a9fa9459Szrj RegXMM, 664*a9fa9459Szrj /* AVX registers */ 665*a9fa9459Szrj RegYMM, 666*a9fa9459Szrj /* AVX512 registers */ 667*a9fa9459Szrj RegZMM, 668*a9fa9459Szrj /* Vector Mask registers */ 669*a9fa9459Szrj RegMask, 670*a9fa9459Szrj /* Control register */ 671*a9fa9459Szrj Control, 672*a9fa9459Szrj /* Debug register */ 673*a9fa9459Szrj Debug, 674*a9fa9459Szrj /* Test register */ 675*a9fa9459Szrj Test, 676*a9fa9459Szrj /* 2 bit segment register */ 677*a9fa9459Szrj SReg2, 678*a9fa9459Szrj /* 3 bit segment register */ 679*a9fa9459Szrj SReg3, 680*a9fa9459Szrj /* 1 bit immediate */ 681*a9fa9459Szrj Imm1, 682*a9fa9459Szrj /* 8 bit immediate */ 683*a9fa9459Szrj Imm8, 684*a9fa9459Szrj /* 8 bit immediate sign extended */ 685*a9fa9459Szrj Imm8S, 686*a9fa9459Szrj /* 16 bit immediate */ 687*a9fa9459Szrj Imm16, 688*a9fa9459Szrj /* 32 bit immediate */ 689*a9fa9459Szrj Imm32, 690*a9fa9459Szrj /* 32 bit immediate sign extended */ 691*a9fa9459Szrj Imm32S, 692*a9fa9459Szrj /* 64 bit immediate */ 693*a9fa9459Szrj Imm64, 694*a9fa9459Szrj /* 8bit/16bit/32bit displacements are used in different ways, 695*a9fa9459Szrj depending on the instruction. For jumps, they specify the 696*a9fa9459Szrj size of the PC relative displacement, for instructions with 697*a9fa9459Szrj memory operand, they specify the size of the offset relative 698*a9fa9459Szrj to the base register, and for instructions with memory offset 699*a9fa9459Szrj such as `mov 1234,%al' they specify the size of the offset 700*a9fa9459Szrj relative to the segment base. */ 701*a9fa9459Szrj /* 8 bit displacement */ 702*a9fa9459Szrj Disp8, 703*a9fa9459Szrj /* 16 bit displacement */ 704*a9fa9459Szrj Disp16, 705*a9fa9459Szrj /* 32 bit displacement */ 706*a9fa9459Szrj Disp32, 707*a9fa9459Szrj /* 32 bit signed displacement */ 708*a9fa9459Szrj Disp32S, 709*a9fa9459Szrj /* 64 bit displacement */ 710*a9fa9459Szrj Disp64, 711*a9fa9459Szrj /* Accumulator %al/%ax/%eax/%rax */ 712*a9fa9459Szrj Acc, 713*a9fa9459Szrj /* Floating pointer top stack register %st(0) */ 714*a9fa9459Szrj FloatAcc, 715*a9fa9459Szrj /* Register which can be used for base or index in memory operand. */ 716*a9fa9459Szrj BaseIndex, 717*a9fa9459Szrj /* Register to hold in/out port addr = dx */ 718*a9fa9459Szrj InOutPortReg, 719*a9fa9459Szrj /* Register to hold shift count = cl */ 720*a9fa9459Szrj ShiftCount, 721*a9fa9459Szrj /* Absolute address for jump. */ 722*a9fa9459Szrj JumpAbsolute, 723*a9fa9459Szrj /* String insn operand with fixed es segment */ 724*a9fa9459Szrj EsSeg, 725*a9fa9459Szrj /* RegMem is for instructions with a modrm byte where the register 726*a9fa9459Szrj destination operand should be encoded in the mod and regmem fields. 727*a9fa9459Szrj Normally, it will be encoded in the reg field. We add a RegMem 728*a9fa9459Szrj flag to the destination register operand to indicate that it should 729*a9fa9459Szrj be encoded in the regmem field. */ 730*a9fa9459Szrj RegMem, 731*a9fa9459Szrj /* Memory. */ 732*a9fa9459Szrj Mem, 733*a9fa9459Szrj /* BYTE memory. */ 734*a9fa9459Szrj Byte, 735*a9fa9459Szrj /* WORD memory. 2 byte */ 736*a9fa9459Szrj Word, 737*a9fa9459Szrj /* DWORD memory. 4 byte */ 738*a9fa9459Szrj Dword, 739*a9fa9459Szrj /* FWORD memory. 6 byte */ 740*a9fa9459Szrj Fword, 741*a9fa9459Szrj /* QWORD memory. 8 byte */ 742*a9fa9459Szrj Qword, 743*a9fa9459Szrj /* TBYTE memory. 10 byte */ 744*a9fa9459Szrj Tbyte, 745*a9fa9459Szrj /* XMMWORD memory. */ 746*a9fa9459Szrj Xmmword, 747*a9fa9459Szrj /* YMMWORD memory. */ 748*a9fa9459Szrj Ymmword, 749*a9fa9459Szrj /* ZMMWORD memory. */ 750*a9fa9459Szrj Zmmword, 751*a9fa9459Szrj /* Unspecified memory size. */ 752*a9fa9459Szrj Unspecified, 753*a9fa9459Szrj /* Any memory size. */ 754*a9fa9459Szrj Anysize, 755*a9fa9459Szrj 756*a9fa9459Szrj /* Vector 4 bit immediate. */ 757*a9fa9459Szrj Vec_Imm4, 758*a9fa9459Szrj 759*a9fa9459Szrj /* Bound register. */ 760*a9fa9459Szrj RegBND, 761*a9fa9459Szrj 762*a9fa9459Szrj /* Vector 8bit displacement */ 763*a9fa9459Szrj Vec_Disp8, 764*a9fa9459Szrj 765*a9fa9459Szrj /* The last bitfield in i386_operand_type. */ 766*a9fa9459Szrj OTMax 767*a9fa9459Szrj }; 768*a9fa9459Szrj 769*a9fa9459Szrj #define OTNumOfUints \ 770*a9fa9459Szrj (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) 771*a9fa9459Szrj #define OTNumOfBits \ 772*a9fa9459Szrj (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) 773*a9fa9459Szrj 774*a9fa9459Szrj /* If you get a compiler error for zero width of the unused field, 775*a9fa9459Szrj comment it out. */ 776*a9fa9459Szrj #define OTUnused (OTMax + 1) 777*a9fa9459Szrj 778*a9fa9459Szrj typedef union i386_operand_type 779*a9fa9459Szrj { 780*a9fa9459Szrj struct 781*a9fa9459Szrj { 782*a9fa9459Szrj unsigned int reg8:1; 783*a9fa9459Szrj unsigned int reg16:1; 784*a9fa9459Szrj unsigned int reg32:1; 785*a9fa9459Szrj unsigned int reg64:1; 786*a9fa9459Szrj unsigned int floatreg:1; 787*a9fa9459Szrj unsigned int regmmx:1; 788*a9fa9459Szrj unsigned int regxmm:1; 789*a9fa9459Szrj unsigned int regymm:1; 790*a9fa9459Szrj unsigned int regzmm:1; 791*a9fa9459Szrj unsigned int regmask:1; 792*a9fa9459Szrj unsigned int control:1; 793*a9fa9459Szrj unsigned int debug:1; 794*a9fa9459Szrj unsigned int test:1; 795*a9fa9459Szrj unsigned int sreg2:1; 796*a9fa9459Szrj unsigned int sreg3:1; 797*a9fa9459Szrj unsigned int imm1:1; 798*a9fa9459Szrj unsigned int imm8:1; 799*a9fa9459Szrj unsigned int imm8s:1; 800*a9fa9459Szrj unsigned int imm16:1; 801*a9fa9459Szrj unsigned int imm32:1; 802*a9fa9459Szrj unsigned int imm32s:1; 803*a9fa9459Szrj unsigned int imm64:1; 804*a9fa9459Szrj unsigned int disp8:1; 805*a9fa9459Szrj unsigned int disp16:1; 806*a9fa9459Szrj unsigned int disp32:1; 807*a9fa9459Szrj unsigned int disp32s:1; 808*a9fa9459Szrj unsigned int disp64:1; 809*a9fa9459Szrj unsigned int acc:1; 810*a9fa9459Szrj unsigned int floatacc:1; 811*a9fa9459Szrj unsigned int baseindex:1; 812*a9fa9459Szrj unsigned int inoutportreg:1; 813*a9fa9459Szrj unsigned int shiftcount:1; 814*a9fa9459Szrj unsigned int jumpabsolute:1; 815*a9fa9459Szrj unsigned int esseg:1; 816*a9fa9459Szrj unsigned int regmem:1; 817*a9fa9459Szrj unsigned int mem:1; 818*a9fa9459Szrj unsigned int byte:1; 819*a9fa9459Szrj unsigned int word:1; 820*a9fa9459Szrj unsigned int dword:1; 821*a9fa9459Szrj unsigned int fword:1; 822*a9fa9459Szrj unsigned int qword:1; 823*a9fa9459Szrj unsigned int tbyte:1; 824*a9fa9459Szrj unsigned int xmmword:1; 825*a9fa9459Szrj unsigned int ymmword:1; 826*a9fa9459Szrj unsigned int zmmword:1; 827*a9fa9459Szrj unsigned int unspecified:1; 828*a9fa9459Szrj unsigned int anysize:1; 829*a9fa9459Szrj unsigned int vec_imm4:1; 830*a9fa9459Szrj unsigned int regbnd:1; 831*a9fa9459Szrj unsigned int vec_disp8:1; 832*a9fa9459Szrj #ifdef OTUnused 833*a9fa9459Szrj unsigned int unused:(OTNumOfBits - OTUnused); 834*a9fa9459Szrj #endif 835*a9fa9459Szrj } bitfield; 836*a9fa9459Szrj unsigned int array[OTNumOfUints]; 837*a9fa9459Szrj } i386_operand_type; 838*a9fa9459Szrj 839*a9fa9459Szrj typedef struct insn_template 840*a9fa9459Szrj { 841*a9fa9459Szrj /* instruction name sans width suffix ("mov" for movl insns) */ 842*a9fa9459Szrj char *name; 843*a9fa9459Szrj 844*a9fa9459Szrj /* how many operands */ 845*a9fa9459Szrj unsigned int operands; 846*a9fa9459Szrj 847*a9fa9459Szrj /* base_opcode is the fundamental opcode byte without optional 848*a9fa9459Szrj prefix(es). */ 849*a9fa9459Szrj unsigned int base_opcode; 850*a9fa9459Szrj #define Opcode_D 0x2 /* Direction bit: 851*a9fa9459Szrj set if Reg --> Regmem; 852*a9fa9459Szrj unset if Regmem --> Reg. */ 853*a9fa9459Szrj #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ 854*a9fa9459Szrj #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ 855*a9fa9459Szrj 856*a9fa9459Szrj /* extension_opcode is the 3 bit extension for group <n> insns. 857*a9fa9459Szrj This field is also used to store the 8-bit opcode suffix for the 858*a9fa9459Szrj AMD 3DNow! instructions. 859*a9fa9459Szrj If this template has no extension opcode (the usual case) use None 860*a9fa9459Szrj Instructions */ 861*a9fa9459Szrj unsigned int extension_opcode; 862*a9fa9459Szrj #define None 0xffff /* If no extension_opcode is possible. */ 863*a9fa9459Szrj 864*a9fa9459Szrj /* Opcode length. */ 865*a9fa9459Szrj unsigned char opcode_length; 866*a9fa9459Szrj 867*a9fa9459Szrj /* cpu feature flags */ 868*a9fa9459Szrj i386_cpu_flags cpu_flags; 869*a9fa9459Szrj 870*a9fa9459Szrj /* the bits in opcode_modifier are used to generate the final opcode from 871*a9fa9459Szrj the base_opcode. These bits also are used to detect alternate forms of 872*a9fa9459Szrj the same instruction */ 873*a9fa9459Szrj i386_opcode_modifier opcode_modifier; 874*a9fa9459Szrj 875*a9fa9459Szrj /* operand_types[i] describes the type of operand i. This is made 876*a9fa9459Szrj by OR'ing together all of the possible type masks. (e.g. 877*a9fa9459Szrj 'operand_types[i] = Reg|Imm' specifies that operand i can be 878*a9fa9459Szrj either a register or an immediate operand. */ 879*a9fa9459Szrj i386_operand_type operand_types[MAX_OPERANDS]; 880*a9fa9459Szrj } 881*a9fa9459Szrj insn_template; 882*a9fa9459Szrj 883*a9fa9459Szrj extern const insn_template i386_optab[]; 884*a9fa9459Szrj 885*a9fa9459Szrj /* these are for register name --> number & type hash lookup */ 886*a9fa9459Szrj typedef struct 887*a9fa9459Szrj { 888*a9fa9459Szrj char *reg_name; 889*a9fa9459Szrj i386_operand_type reg_type; 890*a9fa9459Szrj unsigned char reg_flags; 891*a9fa9459Szrj #define RegRex 0x1 /* Extended register. */ 892*a9fa9459Szrj #define RegRex64 0x2 /* Extended 8 bit register. */ 893*a9fa9459Szrj #define RegVRex 0x4 /* Extended vector register. */ 894*a9fa9459Szrj unsigned char reg_num; 895*a9fa9459Szrj #define RegRip ((unsigned char ) ~0) 896*a9fa9459Szrj #define RegEip (RegRip - 1) 897*a9fa9459Szrj /* EIZ and RIZ are fake index registers. */ 898*a9fa9459Szrj #define RegEiz (RegEip - 1) 899*a9fa9459Szrj #define RegRiz (RegEiz - 1) 900*a9fa9459Szrj /* FLAT is a fake segment register (Intel mode). */ 901*a9fa9459Szrj #define RegFlat ((unsigned char) ~0) 902*a9fa9459Szrj signed char dw2_regnum[2]; 903*a9fa9459Szrj #define Dw2Inval (-1) 904*a9fa9459Szrj } 905*a9fa9459Szrj reg_entry; 906*a9fa9459Szrj 907*a9fa9459Szrj /* Entries in i386_regtab. */ 908*a9fa9459Szrj #define REGNAM_AL 1 909*a9fa9459Szrj #define REGNAM_AX 25 910*a9fa9459Szrj #define REGNAM_EAX 41 911*a9fa9459Szrj 912*a9fa9459Szrj extern const reg_entry i386_regtab[]; 913*a9fa9459Szrj extern const unsigned int i386_regtab_size; 914*a9fa9459Szrj 915*a9fa9459Szrj typedef struct 916*a9fa9459Szrj { 917*a9fa9459Szrj char *seg_name; 918*a9fa9459Szrj unsigned int seg_prefix; 919*a9fa9459Szrj } 920*a9fa9459Szrj seg_entry; 921*a9fa9459Szrj 922*a9fa9459Szrj extern const seg_entry cs; 923*a9fa9459Szrj extern const seg_entry ds; 924*a9fa9459Szrj extern const seg_entry ss; 925*a9fa9459Szrj extern const seg_entry es; 926*a9fa9459Szrj extern const seg_entry fs; 927*a9fa9459Szrj extern const seg_entry gs; 928