1*fae548d3Szrj /* Declarations for Intel 80386 opcode table 2*fae548d3Szrj Copyright (C) 2007-2020 Free Software Foundation, Inc. 3*fae548d3Szrj 4*fae548d3Szrj This file is part of the GNU opcodes library. 5*fae548d3Szrj 6*fae548d3Szrj This library is free software; you can redistribute it and/or modify 7*fae548d3Szrj it under the terms of the GNU General Public License as published by 8*fae548d3Szrj the Free Software Foundation; either version 3, or (at your option) 9*fae548d3Szrj any later version. 10*fae548d3Szrj 11*fae548d3Szrj It is distributed in the hope that it will be useful, but WITHOUT 12*fae548d3Szrj ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13*fae548d3Szrj or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14*fae548d3Szrj License for more details. 15*fae548d3Szrj 16*fae548d3Szrj You should have received a copy of the GNU General Public License 17*fae548d3Szrj along with GAS; see the file COPYING. If not, write to the Free 18*fae548d3Szrj Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19*fae548d3Szrj 02110-1301, USA. */ 20*fae548d3Szrj 21*fae548d3Szrj #include "opcode/i386.h" 22*fae548d3Szrj #ifdef HAVE_LIMITS_H 23*fae548d3Szrj #include <limits.h> 24*fae548d3Szrj #endif 25*fae548d3Szrj 26*fae548d3Szrj #ifndef CHAR_BIT 27*fae548d3Szrj #define CHAR_BIT 8 28*fae548d3Szrj #endif 29*fae548d3Szrj 30*fae548d3Szrj /* Position of cpu flags bitfiled. */ 31*fae548d3Szrj 32*fae548d3Szrj enum 33*fae548d3Szrj { 34*fae548d3Szrj /* i186 or better required */ 35*fae548d3Szrj Cpu186 = 0, 36*fae548d3Szrj /* i286 or better required */ 37*fae548d3Szrj Cpu286, 38*fae548d3Szrj /* i386 or better required */ 39*fae548d3Szrj Cpu386, 40*fae548d3Szrj /* i486 or better required */ 41*fae548d3Szrj Cpu486, 42*fae548d3Szrj /* i585 or better required */ 43*fae548d3Szrj Cpu586, 44*fae548d3Szrj /* i686 or better required */ 45*fae548d3Szrj Cpu686, 46*fae548d3Szrj /* CMOV Instruction support required */ 47*fae548d3Szrj CpuCMOV, 48*fae548d3Szrj /* FXSR Instruction support required */ 49*fae548d3Szrj CpuFXSR, 50*fae548d3Szrj /* CLFLUSH Instruction support required */ 51*fae548d3Szrj CpuClflush, 52*fae548d3Szrj /* NOP Instruction support required */ 53*fae548d3Szrj CpuNop, 54*fae548d3Szrj /* SYSCALL Instructions support required */ 55*fae548d3Szrj CpuSYSCALL, 56*fae548d3Szrj /* Floating point support required */ 57*fae548d3Szrj Cpu8087, 58*fae548d3Szrj /* i287 support required */ 59*fae548d3Szrj Cpu287, 60*fae548d3Szrj /* i387 support required */ 61*fae548d3Szrj Cpu387, 62*fae548d3Szrj /* i686 and floating point support required */ 63*fae548d3Szrj Cpu687, 64*fae548d3Szrj /* SSE3 and floating point support required */ 65*fae548d3Szrj CpuFISTTP, 66*fae548d3Szrj /* MMX support required */ 67*fae548d3Szrj CpuMMX, 68*fae548d3Szrj /* SSE support required */ 69*fae548d3Szrj CpuSSE, 70*fae548d3Szrj /* SSE2 support required */ 71*fae548d3Szrj CpuSSE2, 72*fae548d3Szrj /* 3dnow! support required */ 73*fae548d3Szrj Cpu3dnow, 74*fae548d3Szrj /* 3dnow! Extensions support required */ 75*fae548d3Szrj Cpu3dnowA, 76*fae548d3Szrj /* SSE3 support required */ 77*fae548d3Szrj CpuSSE3, 78*fae548d3Szrj /* VIA PadLock required */ 79*fae548d3Szrj CpuPadLock, 80*fae548d3Szrj /* AMD Secure Virtual Machine Ext-s required */ 81*fae548d3Szrj CpuSVME, 82*fae548d3Szrj /* VMX Instructions required */ 83*fae548d3Szrj CpuVMX, 84*fae548d3Szrj /* SMX Instructions required */ 85*fae548d3Szrj CpuSMX, 86*fae548d3Szrj /* SSSE3 support required */ 87*fae548d3Szrj CpuSSSE3, 88*fae548d3Szrj /* SSE4a support required */ 89*fae548d3Szrj CpuSSE4a, 90*fae548d3Szrj /* ABM New Instructions required */ 91*fae548d3Szrj CpuABM, 92*fae548d3Szrj /* SSE4.1 support required */ 93*fae548d3Szrj CpuSSE4_1, 94*fae548d3Szrj /* SSE4.2 support required */ 95*fae548d3Szrj CpuSSE4_2, 96*fae548d3Szrj /* AVX support required */ 97*fae548d3Szrj CpuAVX, 98*fae548d3Szrj /* AVX2 support required */ 99*fae548d3Szrj CpuAVX2, 100*fae548d3Szrj /* Intel AVX-512 Foundation Instructions support required */ 101*fae548d3Szrj CpuAVX512F, 102*fae548d3Szrj /* Intel AVX-512 Conflict Detection Instructions support required */ 103*fae548d3Szrj CpuAVX512CD, 104*fae548d3Szrj /* Intel AVX-512 Exponential and Reciprocal Instructions support 105*fae548d3Szrj required */ 106*fae548d3Szrj CpuAVX512ER, 107*fae548d3Szrj /* Intel AVX-512 Prefetch Instructions support required */ 108*fae548d3Szrj CpuAVX512PF, 109*fae548d3Szrj /* Intel AVX-512 VL Instructions support required. */ 110*fae548d3Szrj CpuAVX512VL, 111*fae548d3Szrj /* Intel AVX-512 DQ Instructions support required. */ 112*fae548d3Szrj CpuAVX512DQ, 113*fae548d3Szrj /* Intel AVX-512 BW Instructions support required. */ 114*fae548d3Szrj CpuAVX512BW, 115*fae548d3Szrj /* Intel L1OM support required */ 116*fae548d3Szrj CpuL1OM, 117*fae548d3Szrj /* Intel K1OM support required */ 118*fae548d3Szrj CpuK1OM, 119*fae548d3Szrj /* Intel IAMCU support required */ 120*fae548d3Szrj CpuIAMCU, 121*fae548d3Szrj /* Xsave/xrstor New Instructions support required */ 122*fae548d3Szrj CpuXsave, 123*fae548d3Szrj /* Xsaveopt New Instructions support required */ 124*fae548d3Szrj CpuXsaveopt, 125*fae548d3Szrj /* AES support required */ 126*fae548d3Szrj CpuAES, 127*fae548d3Szrj /* PCLMUL support required */ 128*fae548d3Szrj CpuPCLMUL, 129*fae548d3Szrj /* FMA support required */ 130*fae548d3Szrj CpuFMA, 131*fae548d3Szrj /* FMA4 support required */ 132*fae548d3Szrj CpuFMA4, 133*fae548d3Szrj /* XOP support required */ 134*fae548d3Szrj CpuXOP, 135*fae548d3Szrj /* LWP support required */ 136*fae548d3Szrj CpuLWP, 137*fae548d3Szrj /* BMI support required */ 138*fae548d3Szrj CpuBMI, 139*fae548d3Szrj /* TBM support required */ 140*fae548d3Szrj CpuTBM, 141*fae548d3Szrj /* MOVBE Instruction support required */ 142*fae548d3Szrj CpuMovbe, 143*fae548d3Szrj /* CMPXCHG16B instruction support required. */ 144*fae548d3Szrj CpuCX16, 145*fae548d3Szrj /* EPT Instructions required */ 146*fae548d3Szrj CpuEPT, 147*fae548d3Szrj /* RDTSCP Instruction support required */ 148*fae548d3Szrj CpuRdtscp, 149*fae548d3Szrj /* FSGSBASE Instructions required */ 150*fae548d3Szrj CpuFSGSBase, 151*fae548d3Szrj /* RDRND Instructions required */ 152*fae548d3Szrj CpuRdRnd, 153*fae548d3Szrj /* F16C Instructions required */ 154*fae548d3Szrj CpuF16C, 155*fae548d3Szrj /* Intel BMI2 support required */ 156*fae548d3Szrj CpuBMI2, 157*fae548d3Szrj /* LZCNT support required */ 158*fae548d3Szrj CpuLZCNT, 159*fae548d3Szrj /* HLE support required */ 160*fae548d3Szrj CpuHLE, 161*fae548d3Szrj /* RTM support required */ 162*fae548d3Szrj CpuRTM, 163*fae548d3Szrj /* INVPCID Instructions required */ 164*fae548d3Szrj CpuINVPCID, 165*fae548d3Szrj /* VMFUNC Instruction required */ 166*fae548d3Szrj CpuVMFUNC, 167*fae548d3Szrj /* Intel MPX Instructions required */ 168*fae548d3Szrj CpuMPX, 169*fae548d3Szrj /* 64bit support available, used by -march= in assembler. */ 170*fae548d3Szrj CpuLM, 171*fae548d3Szrj /* RDRSEED instruction required. */ 172*fae548d3Szrj CpuRDSEED, 173*fae548d3Szrj /* Multi-presisionn add-carry instructions are required. */ 174*fae548d3Szrj CpuADX, 175*fae548d3Szrj /* Supports prefetchw and prefetch instructions. */ 176*fae548d3Szrj CpuPRFCHW, 177*fae548d3Szrj /* SMAP instructions required. */ 178*fae548d3Szrj CpuSMAP, 179*fae548d3Szrj /* SHA instructions required. */ 180*fae548d3Szrj CpuSHA, 181*fae548d3Szrj /* CLFLUSHOPT instruction required */ 182*fae548d3Szrj CpuClflushOpt, 183*fae548d3Szrj /* XSAVES/XRSTORS instruction required */ 184*fae548d3Szrj CpuXSAVES, 185*fae548d3Szrj /* XSAVEC instruction required */ 186*fae548d3Szrj CpuXSAVEC, 187*fae548d3Szrj /* PREFETCHWT1 instruction required */ 188*fae548d3Szrj CpuPREFETCHWT1, 189*fae548d3Szrj /* SE1 instruction required */ 190*fae548d3Szrj CpuSE1, 191*fae548d3Szrj /* CLWB instruction required */ 192*fae548d3Szrj CpuCLWB, 193*fae548d3Szrj /* Intel AVX-512 IFMA Instructions support required. */ 194*fae548d3Szrj CpuAVX512IFMA, 195*fae548d3Szrj /* Intel AVX-512 VBMI Instructions support required. */ 196*fae548d3Szrj CpuAVX512VBMI, 197*fae548d3Szrj /* Intel AVX-512 4FMAPS Instructions support required. */ 198*fae548d3Szrj CpuAVX512_4FMAPS, 199*fae548d3Szrj /* Intel AVX-512 4VNNIW Instructions support required. */ 200*fae548d3Szrj CpuAVX512_4VNNIW, 201*fae548d3Szrj /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ 202*fae548d3Szrj CpuAVX512_VPOPCNTDQ, 203*fae548d3Szrj /* Intel AVX-512 VBMI2 Instructions support required. */ 204*fae548d3Szrj CpuAVX512_VBMI2, 205*fae548d3Szrj /* Intel AVX-512 VNNI Instructions support required. */ 206*fae548d3Szrj CpuAVX512_VNNI, 207*fae548d3Szrj /* Intel AVX-512 BITALG Instructions support required. */ 208*fae548d3Szrj CpuAVX512_BITALG, 209*fae548d3Szrj /* Intel AVX-512 BF16 Instructions support required. */ 210*fae548d3Szrj CpuAVX512_BF16, 211*fae548d3Szrj /* Intel AVX-512 VP2INTERSECT Instructions support required. */ 212*fae548d3Szrj CpuAVX512_VP2INTERSECT, 213*fae548d3Szrj /* mwaitx instruction required */ 214*fae548d3Szrj CpuMWAITX, 215*fae548d3Szrj /* Clzero instruction required */ 216*fae548d3Szrj CpuCLZERO, 217*fae548d3Szrj /* OSPKE instruction required */ 218*fae548d3Szrj CpuOSPKE, 219*fae548d3Szrj /* RDPID instruction required */ 220*fae548d3Szrj CpuRDPID, 221*fae548d3Szrj /* PTWRITE instruction required */ 222*fae548d3Szrj CpuPTWRITE, 223*fae548d3Szrj /* CET instructions support required */ 224*fae548d3Szrj CpuIBT, 225*fae548d3Szrj CpuSHSTK, 226*fae548d3Szrj /* GFNI instructions required */ 227*fae548d3Szrj CpuGFNI, 228*fae548d3Szrj /* VAES instructions required */ 229*fae548d3Szrj CpuVAES, 230*fae548d3Szrj /* VPCLMULQDQ instructions required */ 231*fae548d3Szrj CpuVPCLMULQDQ, 232*fae548d3Szrj /* WBNOINVD instructions required */ 233*fae548d3Szrj CpuWBNOINVD, 234*fae548d3Szrj /* PCONFIG instructions required */ 235*fae548d3Szrj CpuPCONFIG, 236*fae548d3Szrj /* WAITPKG instructions required */ 237*fae548d3Szrj CpuWAITPKG, 238*fae548d3Szrj /* CLDEMOTE instruction required */ 239*fae548d3Szrj CpuCLDEMOTE, 240*fae548d3Szrj /* MOVDIRI instruction support required */ 241*fae548d3Szrj CpuMOVDIRI, 242*fae548d3Szrj /* MOVDIRR64B instruction required */ 243*fae548d3Szrj CpuMOVDIR64B, 244*fae548d3Szrj /* ENQCMD instruction required */ 245*fae548d3Szrj CpuENQCMD, 246*fae548d3Szrj /* RDPRU instruction required */ 247*fae548d3Szrj CpuRDPRU, 248*fae548d3Szrj /* MCOMMIT instruction required */ 249*fae548d3Szrj CpuMCOMMIT, 250*fae548d3Szrj /* 64bit support required */ 251*fae548d3Szrj Cpu64, 252*fae548d3Szrj /* Not supported in the 64bit mode */ 253*fae548d3Szrj CpuNo64, 254*fae548d3Szrj /* The last bitfield in i386_cpu_flags. */ 255*fae548d3Szrj CpuMax = CpuNo64 256*fae548d3Szrj }; 257*fae548d3Szrj 258*fae548d3Szrj #define CpuNumOfUints \ 259*fae548d3Szrj (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) 260*fae548d3Szrj #define CpuNumOfBits \ 261*fae548d3Szrj (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) 262*fae548d3Szrj 263*fae548d3Szrj /* If you get a compiler error for zero width of the unused field, 264*fae548d3Szrj comment it out. */ 265*fae548d3Szrj #define CpuUnused (CpuMax + 1) 266*fae548d3Szrj 267*fae548d3Szrj /* We can check if an instruction is available with array instead 268*fae548d3Szrj of bitfield. */ 269*fae548d3Szrj typedef union i386_cpu_flags 270*fae548d3Szrj { 271*fae548d3Szrj struct 272*fae548d3Szrj { 273*fae548d3Szrj unsigned int cpui186:1; 274*fae548d3Szrj unsigned int cpui286:1; 275*fae548d3Szrj unsigned int cpui386:1; 276*fae548d3Szrj unsigned int cpui486:1; 277*fae548d3Szrj unsigned int cpui586:1; 278*fae548d3Szrj unsigned int cpui686:1; 279*fae548d3Szrj unsigned int cpucmov:1; 280*fae548d3Szrj unsigned int cpufxsr:1; 281*fae548d3Szrj unsigned int cpuclflush:1; 282*fae548d3Szrj unsigned int cpunop:1; 283*fae548d3Szrj unsigned int cpusyscall:1; 284*fae548d3Szrj unsigned int cpu8087:1; 285*fae548d3Szrj unsigned int cpu287:1; 286*fae548d3Szrj unsigned int cpu387:1; 287*fae548d3Szrj unsigned int cpu687:1; 288*fae548d3Szrj unsigned int cpufisttp:1; 289*fae548d3Szrj unsigned int cpummx:1; 290*fae548d3Szrj unsigned int cpusse:1; 291*fae548d3Szrj unsigned int cpusse2:1; 292*fae548d3Szrj unsigned int cpua3dnow:1; 293*fae548d3Szrj unsigned int cpua3dnowa:1; 294*fae548d3Szrj unsigned int cpusse3:1; 295*fae548d3Szrj unsigned int cpupadlock:1; 296*fae548d3Szrj unsigned int cpusvme:1; 297*fae548d3Szrj unsigned int cpuvmx:1; 298*fae548d3Szrj unsigned int cpusmx:1; 299*fae548d3Szrj unsigned int cpussse3:1; 300*fae548d3Szrj unsigned int cpusse4a:1; 301*fae548d3Szrj unsigned int cpuabm:1; 302*fae548d3Szrj unsigned int cpusse4_1:1; 303*fae548d3Szrj unsigned int cpusse4_2:1; 304*fae548d3Szrj unsigned int cpuavx:1; 305*fae548d3Szrj unsigned int cpuavx2:1; 306*fae548d3Szrj unsigned int cpuavx512f:1; 307*fae548d3Szrj unsigned int cpuavx512cd:1; 308*fae548d3Szrj unsigned int cpuavx512er:1; 309*fae548d3Szrj unsigned int cpuavx512pf:1; 310*fae548d3Szrj unsigned int cpuavx512vl:1; 311*fae548d3Szrj unsigned int cpuavx512dq:1; 312*fae548d3Szrj unsigned int cpuavx512bw:1; 313*fae548d3Szrj unsigned int cpul1om:1; 314*fae548d3Szrj unsigned int cpuk1om:1; 315*fae548d3Szrj unsigned int cpuiamcu:1; 316*fae548d3Szrj unsigned int cpuxsave:1; 317*fae548d3Szrj unsigned int cpuxsaveopt:1; 318*fae548d3Szrj unsigned int cpuaes:1; 319*fae548d3Szrj unsigned int cpupclmul:1; 320*fae548d3Szrj unsigned int cpufma:1; 321*fae548d3Szrj unsigned int cpufma4:1; 322*fae548d3Szrj unsigned int cpuxop:1; 323*fae548d3Szrj unsigned int cpulwp:1; 324*fae548d3Szrj unsigned int cpubmi:1; 325*fae548d3Szrj unsigned int cputbm:1; 326*fae548d3Szrj unsigned int cpumovbe:1; 327*fae548d3Szrj unsigned int cpucx16:1; 328*fae548d3Szrj unsigned int cpuept:1; 329*fae548d3Szrj unsigned int cpurdtscp:1; 330*fae548d3Szrj unsigned int cpufsgsbase:1; 331*fae548d3Szrj unsigned int cpurdrnd:1; 332*fae548d3Szrj unsigned int cpuf16c:1; 333*fae548d3Szrj unsigned int cpubmi2:1; 334*fae548d3Szrj unsigned int cpulzcnt:1; 335*fae548d3Szrj unsigned int cpuhle:1; 336*fae548d3Szrj unsigned int cpurtm:1; 337*fae548d3Szrj unsigned int cpuinvpcid:1; 338*fae548d3Szrj unsigned int cpuvmfunc:1; 339*fae548d3Szrj unsigned int cpumpx:1; 340*fae548d3Szrj unsigned int cpulm:1; 341*fae548d3Szrj unsigned int cpurdseed:1; 342*fae548d3Szrj unsigned int cpuadx:1; 343*fae548d3Szrj unsigned int cpuprfchw:1; 344*fae548d3Szrj unsigned int cpusmap:1; 345*fae548d3Szrj unsigned int cpusha:1; 346*fae548d3Szrj unsigned int cpuclflushopt:1; 347*fae548d3Szrj unsigned int cpuxsaves:1; 348*fae548d3Szrj unsigned int cpuxsavec:1; 349*fae548d3Szrj unsigned int cpuprefetchwt1:1; 350*fae548d3Szrj unsigned int cpuse1:1; 351*fae548d3Szrj unsigned int cpuclwb:1; 352*fae548d3Szrj unsigned int cpuavx512ifma:1; 353*fae548d3Szrj unsigned int cpuavx512vbmi:1; 354*fae548d3Szrj unsigned int cpuavx512_4fmaps:1; 355*fae548d3Szrj unsigned int cpuavx512_4vnniw:1; 356*fae548d3Szrj unsigned int cpuavx512_vpopcntdq:1; 357*fae548d3Szrj unsigned int cpuavx512_vbmi2:1; 358*fae548d3Szrj unsigned int cpuavx512_vnni:1; 359*fae548d3Szrj unsigned int cpuavx512_bitalg:1; 360*fae548d3Szrj unsigned int cpuavx512_bf16:1; 361*fae548d3Szrj unsigned int cpuavx512_vp2intersect:1; 362*fae548d3Szrj unsigned int cpumwaitx:1; 363*fae548d3Szrj unsigned int cpuclzero:1; 364*fae548d3Szrj unsigned int cpuospke:1; 365*fae548d3Szrj unsigned int cpurdpid:1; 366*fae548d3Szrj unsigned int cpuptwrite:1; 367*fae548d3Szrj unsigned int cpuibt:1; 368*fae548d3Szrj unsigned int cpushstk:1; 369*fae548d3Szrj unsigned int cpugfni:1; 370*fae548d3Szrj unsigned int cpuvaes:1; 371*fae548d3Szrj unsigned int cpuvpclmulqdq:1; 372*fae548d3Szrj unsigned int cpuwbnoinvd:1; 373*fae548d3Szrj unsigned int cpupconfig:1; 374*fae548d3Szrj unsigned int cpuwaitpkg:1; 375*fae548d3Szrj unsigned int cpucldemote:1; 376*fae548d3Szrj unsigned int cpumovdiri:1; 377*fae548d3Szrj unsigned int cpumovdir64b:1; 378*fae548d3Szrj unsigned int cpuenqcmd:1; 379*fae548d3Szrj unsigned int cpurdpru:1; 380*fae548d3Szrj unsigned int cpumcommit:1; 381*fae548d3Szrj unsigned int cpu64:1; 382*fae548d3Szrj unsigned int cpuno64:1; 383*fae548d3Szrj #ifdef CpuUnused 384*fae548d3Szrj unsigned int unused:(CpuNumOfBits - CpuUnused); 385*fae548d3Szrj #endif 386*fae548d3Szrj } bitfield; 387*fae548d3Szrj unsigned int array[CpuNumOfUints]; 388*fae548d3Szrj } i386_cpu_flags; 389*fae548d3Szrj 390*fae548d3Szrj /* Position of opcode_modifier bits. */ 391*fae548d3Szrj 392*fae548d3Szrj enum 393*fae548d3Szrj { 394*fae548d3Szrj /* has direction bit. */ 395*fae548d3Szrj D = 0, 396*fae548d3Szrj /* set if operands can be both bytes and words/dwords/qwords, encoded the 397*fae548d3Szrj canonical way; the base_opcode field should hold the encoding for byte 398*fae548d3Szrj operands */ 399*fae548d3Szrj W, 400*fae548d3Szrj /* load form instruction. Must be placed before store form. */ 401*fae548d3Szrj Load, 402*fae548d3Szrj /* insn has a modrm byte. */ 403*fae548d3Szrj Modrm, 404*fae548d3Szrj /* register is in low 3 bits of opcode */ 405*fae548d3Szrj ShortForm, 406*fae548d3Szrj /* special case for jump insns; value has to be 1 */ 407*fae548d3Szrj #define JUMP 1 408*fae548d3Szrj /* call and jump */ 409*fae548d3Szrj #define JUMP_DWORD 2 410*fae548d3Szrj /* loop and jecxz */ 411*fae548d3Szrj #define JUMP_BYTE 3 412*fae548d3Szrj /* special case for intersegment leaps/calls */ 413*fae548d3Szrj #define JUMP_INTERSEGMENT 4 414*fae548d3Szrj /* absolute address for jump */ 415*fae548d3Szrj #define JUMP_ABSOLUTE 5 416*fae548d3Szrj Jump, 417*fae548d3Szrj /* FP insn memory format bit, sized by 0x4 */ 418*fae548d3Szrj FloatMF, 419*fae548d3Szrj /* src/dest swap for floats. */ 420*fae548d3Szrj FloatR, 421*fae548d3Szrj /* needs size prefix if in 32-bit mode */ 422*fae548d3Szrj #define SIZE16 1 423*fae548d3Szrj /* needs size prefix if in 16-bit mode */ 424*fae548d3Szrj #define SIZE32 2 425*fae548d3Szrj /* needs size prefix if in 64-bit mode */ 426*fae548d3Szrj #define SIZE64 3 427*fae548d3Szrj Size, 428*fae548d3Szrj /* check register size. */ 429*fae548d3Szrj CheckRegSize, 430*fae548d3Szrj /* instruction ignores operand size prefix and in Intel mode ignores 431*fae548d3Szrj mnemonic size suffix check. */ 432*fae548d3Szrj IgnoreSize, 433*fae548d3Szrj /* default insn size depends on mode */ 434*fae548d3Szrj DefaultSize, 435*fae548d3Szrj /* any memory size */ 436*fae548d3Szrj Anysize, 437*fae548d3Szrj /* b suffix on instruction illegal */ 438*fae548d3Szrj No_bSuf, 439*fae548d3Szrj /* w suffix on instruction illegal */ 440*fae548d3Szrj No_wSuf, 441*fae548d3Szrj /* l suffix on instruction illegal */ 442*fae548d3Szrj No_lSuf, 443*fae548d3Szrj /* s suffix on instruction illegal */ 444*fae548d3Szrj No_sSuf, 445*fae548d3Szrj /* q suffix on instruction illegal */ 446*fae548d3Szrj No_qSuf, 447*fae548d3Szrj /* long double suffix on instruction illegal */ 448*fae548d3Szrj No_ldSuf, 449*fae548d3Szrj /* instruction needs FWAIT */ 450*fae548d3Szrj FWait, 451*fae548d3Szrj /* IsString provides for a quick test for string instructions, and 452*fae548d3Szrj its actual value also indicates which of the operands (if any) 453*fae548d3Szrj requires use of the %es segment. */ 454*fae548d3Szrj #define IS_STRING_ES_OP0 2 455*fae548d3Szrj #define IS_STRING_ES_OP1 3 456*fae548d3Szrj IsString, 457*fae548d3Szrj /* RegMem is for instructions with a modrm byte where the register 458*fae548d3Szrj destination operand should be encoded in the mod and regmem fields. 459*fae548d3Szrj Normally, it will be encoded in the reg field. We add a RegMem 460*fae548d3Szrj flag to indicate that it should be encoded in the regmem field. */ 461*fae548d3Szrj RegMem, 462*fae548d3Szrj /* quick test if branch instruction is MPX supported */ 463*fae548d3Szrj BNDPrefixOk, 464*fae548d3Szrj /* quick test if NOTRACK prefix is supported */ 465*fae548d3Szrj NoTrackPrefixOk, 466*fae548d3Szrj /* quick test for lockable instructions */ 467*fae548d3Szrj IsLockable, 468*fae548d3Szrj /* fake an extra reg operand for clr, imul and special register 469*fae548d3Szrj processing for some instructions. */ 470*fae548d3Szrj RegKludge, 471*fae548d3Szrj /* An implicit xmm0 as the first operand */ 472*fae548d3Szrj Implicit1stXmm0, 473*fae548d3Szrj /* The HLE prefix is OK: 474*fae548d3Szrj 1. With a LOCK prefix. 475*fae548d3Szrj 2. With or without a LOCK prefix. 476*fae548d3Szrj 3. With a RELEASE (0xf3) prefix. 477*fae548d3Szrj */ 478*fae548d3Szrj #define HLEPrefixNone 0 479*fae548d3Szrj #define HLEPrefixLock 1 480*fae548d3Szrj #define HLEPrefixAny 2 481*fae548d3Szrj #define HLEPrefixRelease 3 482*fae548d3Szrj HLEPrefixOk, 483*fae548d3Szrj /* An instruction on which a "rep" prefix is acceptable. */ 484*fae548d3Szrj RepPrefixOk, 485*fae548d3Szrj /* Convert to DWORD */ 486*fae548d3Szrj ToDword, 487*fae548d3Szrj /* Convert to QWORD */ 488*fae548d3Szrj ToQword, 489*fae548d3Szrj /* Address prefix changes register operand */ 490*fae548d3Szrj AddrPrefixOpReg, 491*fae548d3Szrj /* opcode is a prefix */ 492*fae548d3Szrj IsPrefix, 493*fae548d3Szrj /* instruction has extension in 8 bit imm */ 494*fae548d3Szrj ImmExt, 495*fae548d3Szrj /* instruction don't need Rex64 prefix. */ 496*fae548d3Szrj NoRex64, 497*fae548d3Szrj /* instruction require Rex64 prefix. */ 498*fae548d3Szrj Rex64, 499*fae548d3Szrj /* deprecated fp insn, gets a warning */ 500*fae548d3Szrj Ugh, 501*fae548d3Szrj /* insn has VEX prefix: 502*fae548d3Szrj 1: 128bit VEX prefix (or operand dependent). 503*fae548d3Szrj 2: 256bit VEX prefix. 504*fae548d3Szrj 3: Scalar VEX prefix. 505*fae548d3Szrj */ 506*fae548d3Szrj #define VEX128 1 507*fae548d3Szrj #define VEX256 2 508*fae548d3Szrj #define VEXScalar 3 509*fae548d3Szrj Vex, 510*fae548d3Szrj /* How to encode VEX.vvvv: 511*fae548d3Szrj 0: VEX.vvvv must be 1111b. 512*fae548d3Szrj 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where 513*fae548d3Szrj the content of source registers will be preserved. 514*fae548d3Szrj VEX.DDS. The second register operand is encoded in VEX.vvvv 515*fae548d3Szrj where the content of first source register will be overwritten 516*fae548d3Szrj by the result. 517*fae548d3Szrj VEX.NDD2. The second destination register operand is encoded in 518*fae548d3Szrj VEX.vvvv for instructions with 2 destination register operands. 519*fae548d3Szrj For assembler, there are no difference between VEX.NDS, VEX.DDS 520*fae548d3Szrj and VEX.NDD2. 521*fae548d3Szrj 2. VEX.NDD. Register destination is encoded in VEX.vvvv for 522*fae548d3Szrj instructions with 1 destination register operand. 523*fae548d3Szrj 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one 524*fae548d3Szrj of the operands can access a memory location. 525*fae548d3Szrj */ 526*fae548d3Szrj #define VEXXDS 1 527*fae548d3Szrj #define VEXNDD 2 528*fae548d3Szrj #define VEXLWP 3 529*fae548d3Szrj VexVVVV, 530*fae548d3Szrj /* How the VEX.W bit is used: 531*fae548d3Szrj 0: Set by the REX.W bit. 532*fae548d3Szrj 1: VEX.W0. Should always be 0. 533*fae548d3Szrj 2: VEX.W1. Should always be 1. 534*fae548d3Szrj 3: VEX.WIG. The VEX.W bit is ignored. 535*fae548d3Szrj */ 536*fae548d3Szrj #define VEXW0 1 537*fae548d3Szrj #define VEXW1 2 538*fae548d3Szrj #define VEXWIG 3 539*fae548d3Szrj VexW, 540*fae548d3Szrj /* VEX opcode prefix: 541*fae548d3Szrj 0: VEX 0x0F opcode prefix. 542*fae548d3Szrj 1: VEX 0x0F38 opcode prefix. 543*fae548d3Szrj 2: VEX 0x0F3A opcode prefix 544*fae548d3Szrj 3: XOP 0x08 opcode prefix. 545*fae548d3Szrj 4: XOP 0x09 opcode prefix 546*fae548d3Szrj 5: XOP 0x0A opcode prefix. 547*fae548d3Szrj */ 548*fae548d3Szrj #define VEX0F 0 549*fae548d3Szrj #define VEX0F38 1 550*fae548d3Szrj #define VEX0F3A 2 551*fae548d3Szrj #define XOP08 3 552*fae548d3Szrj #define XOP09 4 553*fae548d3Szrj #define XOP0A 5 554*fae548d3Szrj VexOpcode, 555*fae548d3Szrj /* number of VEX source operands: 556*fae548d3Szrj 0: <= 2 source operands. 557*fae548d3Szrj 1: 2 XOP source operands. 558*fae548d3Szrj 2: 3 source operands. 559*fae548d3Szrj */ 560*fae548d3Szrj #define XOP2SOURCES 1 561*fae548d3Szrj #define VEX3SOURCES 2 562*fae548d3Szrj VexSources, 563*fae548d3Szrj /* Instruction with vector SIB byte: 564*fae548d3Szrj 1: 128bit vector register. 565*fae548d3Szrj 2: 256bit vector register. 566*fae548d3Szrj 3: 512bit vector register. 567*fae548d3Szrj */ 568*fae548d3Szrj #define VecSIB128 1 569*fae548d3Szrj #define VecSIB256 2 570*fae548d3Szrj #define VecSIB512 3 571*fae548d3Szrj VecSIB, 572*fae548d3Szrj /* SSE to AVX support required */ 573*fae548d3Szrj SSE2AVX, 574*fae548d3Szrj /* No AVX equivalent */ 575*fae548d3Szrj NoAVX, 576*fae548d3Szrj 577*fae548d3Szrj /* insn has EVEX prefix: 578*fae548d3Szrj 1: 512bit EVEX prefix. 579*fae548d3Szrj 2: 128bit EVEX prefix. 580*fae548d3Szrj 3: 256bit EVEX prefix. 581*fae548d3Szrj 4: Length-ignored (LIG) EVEX prefix. 582*fae548d3Szrj 5: Length determined from actual operands. 583*fae548d3Szrj */ 584*fae548d3Szrj #define EVEX512 1 585*fae548d3Szrj #define EVEX128 2 586*fae548d3Szrj #define EVEX256 3 587*fae548d3Szrj #define EVEXLIG 4 588*fae548d3Szrj #define EVEXDYN 5 589*fae548d3Szrj EVex, 590*fae548d3Szrj 591*fae548d3Szrj /* AVX512 masking support: 592*fae548d3Szrj 1: Zeroing or merging masking depending on operands. 593*fae548d3Szrj 2: Merging-masking. 594*fae548d3Szrj 3: Both zeroing and merging masking. 595*fae548d3Szrj */ 596*fae548d3Szrj #define DYNAMIC_MASKING 1 597*fae548d3Szrj #define MERGING_MASKING 2 598*fae548d3Szrj #define BOTH_MASKING 3 599*fae548d3Szrj Masking, 600*fae548d3Szrj 601*fae548d3Szrj /* AVX512 broadcast support. The number of bytes to broadcast is 602*fae548d3Szrj 1 << (Broadcast - 1): 603*fae548d3Szrj 1: Byte broadcast. 604*fae548d3Szrj 2: Word broadcast. 605*fae548d3Szrj 3: Dword broadcast. 606*fae548d3Szrj 4: Qword broadcast. 607*fae548d3Szrj */ 608*fae548d3Szrj #define BYTE_BROADCAST 1 609*fae548d3Szrj #define WORD_BROADCAST 2 610*fae548d3Szrj #define DWORD_BROADCAST 3 611*fae548d3Szrj #define QWORD_BROADCAST 4 612*fae548d3Szrj Broadcast, 613*fae548d3Szrj 614*fae548d3Szrj /* Static rounding control is supported. */ 615*fae548d3Szrj StaticRounding, 616*fae548d3Szrj 617*fae548d3Szrj /* Supress All Exceptions is supported. */ 618*fae548d3Szrj SAE, 619*fae548d3Szrj 620*fae548d3Szrj /* Compressed Disp8*N attribute. */ 621*fae548d3Szrj #define DISP8_SHIFT_VL 7 622*fae548d3Szrj Disp8MemShift, 623*fae548d3Szrj 624*fae548d3Szrj /* Default mask isn't allowed. */ 625*fae548d3Szrj NoDefMask, 626*fae548d3Szrj 627*fae548d3Szrj /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. 628*fae548d3Szrj It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). 629*fae548d3Szrj */ 630*fae548d3Szrj ImplicitQuadGroup, 631*fae548d3Szrj 632*fae548d3Szrj /* Support encoding optimization. */ 633*fae548d3Szrj Optimize, 634*fae548d3Szrj 635*fae548d3Szrj /* AT&T mnemonic. */ 636*fae548d3Szrj ATTMnemonic, 637*fae548d3Szrj /* AT&T syntax. */ 638*fae548d3Szrj ATTSyntax, 639*fae548d3Szrj /* Intel syntax. */ 640*fae548d3Szrj IntelSyntax, 641*fae548d3Szrj /* AMD64. */ 642*fae548d3Szrj AMD64, 643*fae548d3Szrj /* Intel64. */ 644*fae548d3Szrj Intel64, 645*fae548d3Szrj /* The last bitfield in i386_opcode_modifier. */ 646*fae548d3Szrj Opcode_Modifier_Num 647*fae548d3Szrj }; 648*fae548d3Szrj 649*fae548d3Szrj typedef struct i386_opcode_modifier 650*fae548d3Szrj { 651*fae548d3Szrj unsigned int d:1; 652*fae548d3Szrj unsigned int w:1; 653*fae548d3Szrj unsigned int load:1; 654*fae548d3Szrj unsigned int modrm:1; 655*fae548d3Szrj unsigned int shortform:1; 656*fae548d3Szrj unsigned int jump:3; 657*fae548d3Szrj unsigned int floatmf:1; 658*fae548d3Szrj unsigned int floatr:1; 659*fae548d3Szrj unsigned int size:2; 660*fae548d3Szrj unsigned int checkregsize:1; 661*fae548d3Szrj unsigned int ignoresize:1; 662*fae548d3Szrj unsigned int defaultsize:1; 663*fae548d3Szrj unsigned int anysize:1; 664*fae548d3Szrj unsigned int no_bsuf:1; 665*fae548d3Szrj unsigned int no_wsuf:1; 666*fae548d3Szrj unsigned int no_lsuf:1; 667*fae548d3Szrj unsigned int no_ssuf:1; 668*fae548d3Szrj unsigned int no_qsuf:1; 669*fae548d3Szrj unsigned int no_ldsuf:1; 670*fae548d3Szrj unsigned int fwait:1; 671*fae548d3Szrj unsigned int isstring:2; 672*fae548d3Szrj unsigned int regmem:1; 673*fae548d3Szrj unsigned int bndprefixok:1; 674*fae548d3Szrj unsigned int notrackprefixok:1; 675*fae548d3Szrj unsigned int islockable:1; 676*fae548d3Szrj unsigned int regkludge:1; 677*fae548d3Szrj unsigned int implicit1stxmm0:1; 678*fae548d3Szrj unsigned int hleprefixok:2; 679*fae548d3Szrj unsigned int repprefixok:1; 680*fae548d3Szrj unsigned int todword:1; 681*fae548d3Szrj unsigned int toqword:1; 682*fae548d3Szrj unsigned int addrprefixopreg:1; 683*fae548d3Szrj unsigned int isprefix:1; 684*fae548d3Szrj unsigned int immext:1; 685*fae548d3Szrj unsigned int norex64:1; 686*fae548d3Szrj unsigned int rex64:1; 687*fae548d3Szrj unsigned int ugh:1; 688*fae548d3Szrj unsigned int vex:2; 689*fae548d3Szrj unsigned int vexvvvv:2; 690*fae548d3Szrj unsigned int vexw:2; 691*fae548d3Szrj unsigned int vexopcode:3; 692*fae548d3Szrj unsigned int vexsources:2; 693*fae548d3Szrj unsigned int vecsib:2; 694*fae548d3Szrj unsigned int sse2avx:1; 695*fae548d3Szrj unsigned int noavx:1; 696*fae548d3Szrj unsigned int evex:3; 697*fae548d3Szrj unsigned int masking:2; 698*fae548d3Szrj unsigned int broadcast:3; 699*fae548d3Szrj unsigned int staticrounding:1; 700*fae548d3Szrj unsigned int sae:1; 701*fae548d3Szrj unsigned int disp8memshift:3; 702*fae548d3Szrj unsigned int nodefmask:1; 703*fae548d3Szrj unsigned int implicitquadgroup:1; 704*fae548d3Szrj unsigned int optimize:1; 705*fae548d3Szrj unsigned int attmnemonic:1; 706*fae548d3Szrj unsigned int attsyntax:1; 707*fae548d3Szrj unsigned int intelsyntax:1; 708*fae548d3Szrj unsigned int amd64:1; 709*fae548d3Szrj unsigned int intel64:1; 710*fae548d3Szrj } i386_opcode_modifier; 711*fae548d3Szrj 712*fae548d3Szrj /* Operand classes. */ 713*fae548d3Szrj 714*fae548d3Szrj #define CLASS_WIDTH 4 715*fae548d3Szrj enum operand_class 716*fae548d3Szrj { 717*fae548d3Szrj ClassNone, 718*fae548d3Szrj Reg, /* GPRs and FP regs, distinguished by operand size */ 719*fae548d3Szrj SReg, /* Segment register */ 720*fae548d3Szrj RegCR, /* Control register */ 721*fae548d3Szrj RegDR, /* Debug register */ 722*fae548d3Szrj RegTR, /* Test register */ 723*fae548d3Szrj RegMMX, /* MMX register */ 724*fae548d3Szrj RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */ 725*fae548d3Szrj RegMask, /* Vector Mask register */ 726*fae548d3Szrj RegBND, /* Bound register */ 727*fae548d3Szrj }; 728*fae548d3Szrj 729*fae548d3Szrj /* Special operand instances. */ 730*fae548d3Szrj 731*fae548d3Szrj #define INSTANCE_WIDTH 3 732*fae548d3Szrj enum operand_instance 733*fae548d3Szrj { 734*fae548d3Szrj InstanceNone, 735*fae548d3Szrj Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */ 736*fae548d3Szrj RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */ 737*fae548d3Szrj RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */ 738*fae548d3Szrj RegB, /* %bl / %bx / %ebx / %rbx */ 739*fae548d3Szrj }; 740*fae548d3Szrj 741*fae548d3Szrj /* Position of operand_type bits. */ 742*fae548d3Szrj 743*fae548d3Szrj enum 744*fae548d3Szrj { 745*fae548d3Szrj /* Class and Instance */ 746*fae548d3Szrj ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1, 747*fae548d3Szrj /* 1 bit immediate */ 748*fae548d3Szrj Imm1, 749*fae548d3Szrj /* 8 bit immediate */ 750*fae548d3Szrj Imm8, 751*fae548d3Szrj /* 8 bit immediate sign extended */ 752*fae548d3Szrj Imm8S, 753*fae548d3Szrj /* 16 bit immediate */ 754*fae548d3Szrj Imm16, 755*fae548d3Szrj /* 32 bit immediate */ 756*fae548d3Szrj Imm32, 757*fae548d3Szrj /* 32 bit immediate sign extended */ 758*fae548d3Szrj Imm32S, 759*fae548d3Szrj /* 64 bit immediate */ 760*fae548d3Szrj Imm64, 761*fae548d3Szrj /* 8bit/16bit/32bit displacements are used in different ways, 762*fae548d3Szrj depending on the instruction. For jumps, they specify the 763*fae548d3Szrj size of the PC relative displacement, for instructions with 764*fae548d3Szrj memory operand, they specify the size of the offset relative 765*fae548d3Szrj to the base register, and for instructions with memory offset 766*fae548d3Szrj such as `mov 1234,%al' they specify the size of the offset 767*fae548d3Szrj relative to the segment base. */ 768*fae548d3Szrj /* 8 bit displacement */ 769*fae548d3Szrj Disp8, 770*fae548d3Szrj /* 16 bit displacement */ 771*fae548d3Szrj Disp16, 772*fae548d3Szrj /* 32 bit displacement */ 773*fae548d3Szrj Disp32, 774*fae548d3Szrj /* 32 bit signed displacement */ 775*fae548d3Szrj Disp32S, 776*fae548d3Szrj /* 64 bit displacement */ 777*fae548d3Szrj Disp64, 778*fae548d3Szrj /* Register which can be used for base or index in memory operand. */ 779*fae548d3Szrj BaseIndex, 780*fae548d3Szrj /* BYTE size. */ 781*fae548d3Szrj Byte, 782*fae548d3Szrj /* WORD size. 2 byte */ 783*fae548d3Szrj Word, 784*fae548d3Szrj /* DWORD size. 4 byte */ 785*fae548d3Szrj Dword, 786*fae548d3Szrj /* FWORD size. 6 byte */ 787*fae548d3Szrj Fword, 788*fae548d3Szrj /* QWORD size. 8 byte */ 789*fae548d3Szrj Qword, 790*fae548d3Szrj /* TBYTE size. 10 byte */ 791*fae548d3Szrj Tbyte, 792*fae548d3Szrj /* XMMWORD size. */ 793*fae548d3Szrj Xmmword, 794*fae548d3Szrj /* YMMWORD size. */ 795*fae548d3Szrj Ymmword, 796*fae548d3Szrj /* ZMMWORD size. */ 797*fae548d3Szrj Zmmword, 798*fae548d3Szrj /* Unspecified memory size. */ 799*fae548d3Szrj Unspecified, 800*fae548d3Szrj 801*fae548d3Szrj /* The number of bits in i386_operand_type. */ 802*fae548d3Szrj OTNum 803*fae548d3Szrj }; 804*fae548d3Szrj 805*fae548d3Szrj #define OTNumOfUints \ 806*fae548d3Szrj ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1) 807*fae548d3Szrj #define OTNumOfBits \ 808*fae548d3Szrj (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) 809*fae548d3Szrj 810*fae548d3Szrj /* If you get a compiler error for zero width of the unused field, 811*fae548d3Szrj comment it out. */ 812*fae548d3Szrj #define OTUnused OTNum 813*fae548d3Szrj 814*fae548d3Szrj typedef union i386_operand_type 815*fae548d3Szrj { 816*fae548d3Szrj struct 817*fae548d3Szrj { 818*fae548d3Szrj unsigned int class:CLASS_WIDTH; 819*fae548d3Szrj unsigned int instance:INSTANCE_WIDTH; 820*fae548d3Szrj unsigned int imm1:1; 821*fae548d3Szrj unsigned int imm8:1; 822*fae548d3Szrj unsigned int imm8s:1; 823*fae548d3Szrj unsigned int imm16:1; 824*fae548d3Szrj unsigned int imm32:1; 825*fae548d3Szrj unsigned int imm32s:1; 826*fae548d3Szrj unsigned int imm64:1; 827*fae548d3Szrj unsigned int disp8:1; 828*fae548d3Szrj unsigned int disp16:1; 829*fae548d3Szrj unsigned int disp32:1; 830*fae548d3Szrj unsigned int disp32s:1; 831*fae548d3Szrj unsigned int disp64:1; 832*fae548d3Szrj unsigned int baseindex:1; 833*fae548d3Szrj unsigned int byte:1; 834*fae548d3Szrj unsigned int word:1; 835*fae548d3Szrj unsigned int dword:1; 836*fae548d3Szrj unsigned int fword:1; 837*fae548d3Szrj unsigned int qword:1; 838*fae548d3Szrj unsigned int tbyte:1; 839*fae548d3Szrj unsigned int xmmword:1; 840*fae548d3Szrj unsigned int ymmword:1; 841*fae548d3Szrj unsigned int zmmword:1; 842*fae548d3Szrj unsigned int unspecified:1; 843*fae548d3Szrj #ifdef OTUnused 844*fae548d3Szrj unsigned int unused:(OTNumOfBits - OTUnused); 845*fae548d3Szrj #endif 846*fae548d3Szrj } bitfield; 847*fae548d3Szrj unsigned int array[OTNumOfUints]; 848*fae548d3Szrj } i386_operand_type; 849*fae548d3Szrj 850*fae548d3Szrj typedef struct insn_template 851*fae548d3Szrj { 852*fae548d3Szrj /* instruction name sans width suffix ("mov" for movl insns) */ 853*fae548d3Szrj char *name; 854*fae548d3Szrj 855*fae548d3Szrj /* base_opcode is the fundamental opcode byte without optional 856*fae548d3Szrj prefix(es). */ 857*fae548d3Szrj unsigned int base_opcode; 858*fae548d3Szrj #define Opcode_D 0x2 /* Direction bit: 859*fae548d3Szrj set if Reg --> Regmem; 860*fae548d3Szrj unset if Regmem --> Reg. */ 861*fae548d3Szrj #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ 862*fae548d3Szrj #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ 863*fae548d3Szrj #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */ 864*fae548d3Szrj #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ 865*fae548d3Szrj 866*fae548d3Szrj /* extension_opcode is the 3 bit extension for group <n> insns. 867*fae548d3Szrj This field is also used to store the 8-bit opcode suffix for the 868*fae548d3Szrj AMD 3DNow! instructions. 869*fae548d3Szrj If this template has no extension opcode (the usual case) use None 870*fae548d3Szrj Instructions */ 871*fae548d3Szrj unsigned short extension_opcode; 872*fae548d3Szrj #define None 0xffff /* If no extension_opcode is possible. */ 873*fae548d3Szrj 874*fae548d3Szrj /* Opcode length. */ 875*fae548d3Szrj unsigned char opcode_length; 876*fae548d3Szrj 877*fae548d3Szrj /* how many operands */ 878*fae548d3Szrj unsigned char operands; 879*fae548d3Szrj 880*fae548d3Szrj /* cpu feature flags */ 881*fae548d3Szrj i386_cpu_flags cpu_flags; 882*fae548d3Szrj 883*fae548d3Szrj /* the bits in opcode_modifier are used to generate the final opcode from 884*fae548d3Szrj the base_opcode. These bits also are used to detect alternate forms of 885*fae548d3Szrj the same instruction */ 886*fae548d3Szrj i386_opcode_modifier opcode_modifier; 887*fae548d3Szrj 888*fae548d3Szrj /* operand_types[i] describes the type of operand i. This is made 889*fae548d3Szrj by OR'ing together all of the possible type masks. (e.g. 890*fae548d3Szrj 'operand_types[i] = Reg|Imm' specifies that operand i can be 891*fae548d3Szrj either a register or an immediate operand. */ 892*fae548d3Szrj i386_operand_type operand_types[MAX_OPERANDS]; 893*fae548d3Szrj } 894*fae548d3Szrj insn_template; 895*fae548d3Szrj 896*fae548d3Szrj extern const insn_template i386_optab[]; 897*fae548d3Szrj 898*fae548d3Szrj /* these are for register name --> number & type hash lookup */ 899*fae548d3Szrj typedef struct 900*fae548d3Szrj { 901*fae548d3Szrj char *reg_name; 902*fae548d3Szrj i386_operand_type reg_type; 903*fae548d3Szrj unsigned char reg_flags; 904*fae548d3Szrj #define RegRex 0x1 /* Extended register. */ 905*fae548d3Szrj #define RegRex64 0x2 /* Extended 8 bit register. */ 906*fae548d3Szrj #define RegVRex 0x4 /* Extended vector register. */ 907*fae548d3Szrj unsigned char reg_num; 908*fae548d3Szrj #define RegIP ((unsigned char ) ~0) 909*fae548d3Szrj /* EIZ and RIZ are fake index registers. */ 910*fae548d3Szrj #define RegIZ (RegIP - 1) 911*fae548d3Szrj /* FLAT is a fake segment register (Intel mode). */ 912*fae548d3Szrj #define RegFlat ((unsigned char) ~0) 913*fae548d3Szrj signed char dw2_regnum[2]; 914*fae548d3Szrj #define Dw2Inval (-1) 915*fae548d3Szrj } 916*fae548d3Szrj reg_entry; 917*fae548d3Szrj 918*fae548d3Szrj /* Entries in i386_regtab. */ 919*fae548d3Szrj #define REGNAM_AL 1 920*fae548d3Szrj #define REGNAM_AX 25 921*fae548d3Szrj #define REGNAM_EAX 41 922*fae548d3Szrj 923*fae548d3Szrj extern const reg_entry i386_regtab[]; 924*fae548d3Szrj extern const unsigned int i386_regtab_size; 925*fae548d3Szrj 926*fae548d3Szrj typedef struct 927*fae548d3Szrj { 928*fae548d3Szrj char *seg_name; 929*fae548d3Szrj unsigned int seg_prefix; 930*fae548d3Szrj } 931*fae548d3Szrj seg_entry; 932*fae548d3Szrj 933*fae548d3Szrj extern const seg_entry cs; 934*fae548d3Szrj extern const seg_entry ds; 935*fae548d3Szrj extern const seg_entry ss; 936*fae548d3Szrj extern const seg_entry es; 937*fae548d3Szrj extern const seg_entry fs; 938*fae548d3Szrj extern const seg_entry gs; 939