1; Options for the IA-32 and AMD64 ports of the compiler.
2
3; Copyright (C) 2005, 2006, 2007, 2008, 2009,
4; 2010, 2011 Free Software Foundation, Inc.
5;
6; This file is part of GCC.
7;
8; GCC is free software; you can redistribute it and/or modify it under
9; the terms of the GNU General Public License as published by the Free
10; Software Foundation; either version 3, or (at your option) any later
11; version.
12;
13; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14; WARRANTY; without even the implied warranty of MERCHANTABILITY or
15; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16; for more details.
17;
18; You should have received a copy of the GNU General Public License
19; along with GCC; see the file COPYING3.  If not see
20; <http://www.gnu.org/licenses/>.
21
22HeaderInclude
23config/i386/i386-opts.h
24
25; Bit flags that specify the ISA we are compiling for.
26Variable
27HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
28
29; A mask of ix86_isa_flags that includes bit X if X was set or cleared
30; on the command line.
31Variable
32HOST_WIDE_INT ix86_isa_flags_explicit
33
34TargetVariable
35int recip_mask = RECIP_MASK_DEFAULT
36
37Variable
38int recip_mask_explicit
39
40TargetSave
41int x_recip_mask_explicit
42
43;; Definitions to add to the cl_target_option structure
44;; -march= processor
45TargetSave
46unsigned char arch
47
48;; -mtune= processor
49TargetSave
50unsigned char tune
51
52;; CPU schedule model
53TargetSave
54unsigned char schedule
55
56;; branch cost
57TargetSave
58unsigned char branch_cost
59
60;; which flags were passed by the user
61TargetSave
62HOST_WIDE_INT x_ix86_isa_flags_explicit
63
64;; which flags were passed by the user
65TargetSave
66int ix86_target_flags_explicit
67
68;; whether -mtune was not specified
69TargetSave
70unsigned char tune_defaulted
71
72;; whether -march was specified
73TargetSave
74unsigned char arch_specified
75
76;; x86 options
77m128bit-long-double
78Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
79sizeof(long double) is 16
80
81m80387
82Target Report Mask(80387) Save
83Use hardware fp
84
85m96bit-long-double
86Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
87sizeof(long double) is 12
88
89maccumulate-outgoing-args
90Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
91Reserve space for outgoing arguments in the function prologue
92
93malign-double
94Target Report Mask(ALIGN_DOUBLE) Save
95Align some doubles on dword boundary
96
97malign-functions=
98Target RejectNegative Joined UInteger
99Function starts are aligned to this power of 2
100
101malign-jumps=
102Target RejectNegative Joined UInteger
103Jump targets are aligned to this power of 2
104
105malign-loops=
106Target RejectNegative Joined UInteger
107Loop code aligned to this power of 2
108
109malign-stringops
110Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
111Align destination of the string operations
112
113march=
114Target RejectNegative Joined Var(ix86_arch_string)
115Generate code for given CPU
116
117masm=
118Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
119Use given assembler dialect
120
121Enum
122Name(asm_dialect) Type(enum asm_dialect)
123Known assembler dialects (for use with the -masm-dialect= option):
124
125EnumValue
126Enum(asm_dialect) String(intel) Value(ASM_INTEL)
127
128EnumValue
129Enum(asm_dialect) String(att) Value(ASM_ATT)
130
131mbranch-cost=
132Target RejectNegative Joined UInteger Var(ix86_branch_cost)
133Branches are this expensive (1-5, arbitrary units)
134
135mlarge-data-threshold=
136Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(65536)
137Data greater than given threshold will go into .ldata section in x86-64 medium model
138
139mcmodel=
140Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
141Use given x86-64 code model
142
143Enum
144Name(cmodel) Type(enum cmodel)
145Known code models (for use with the -mcmodel= option):
146
147EnumValue
148Enum(cmodel) String(small) Value(CM_SMALL)
149
150EnumValue
151Enum(cmodel) String(medium) Value(CM_MEDIUM)
152
153EnumValue
154Enum(cmodel) String(large) Value(CM_LARGE)
155
156EnumValue
157Enum(cmodel) String(32) Value(CM_32)
158
159EnumValue
160Enum(cmodel) String(kernel) Value(CM_KERNEL)
161
162mcpu=
163Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
164
165mfancy-math-387
166Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
167Generate sin, cos, sqrt for FPU
168
169mforce-drap
170Target Report Var(ix86_force_drap)
171Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
172
173mfp-ret-in-387
174Target Report Mask(FLOAT_RETURNS) Save
175Return values of functions in FPU registers
176
177mfpmath=
178Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
179Generate floating point mathematics using given instruction set
180
181Enum
182Name(fpmath_unit) Type(enum fpmath_unit)
183Valid arguments to -mfpmath=:
184
185EnumValue
186Enum(fpmath_unit) String(387) Value(FPMATH_387)
187
188EnumValue
189Enum(fpmath_unit) String(sse) Value(FPMATH_SSE)
190
191EnumValue
192Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
193
194EnumValue
195Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
196
197EnumValue
198Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
199
200EnumValue
201Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
202
203EnumValue
204Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
205
206mhard-float
207Target RejectNegative Mask(80387) MaskExists Save
208Use hardware fp
209
210mieee-fp
211Target Report Mask(IEEE_FP) Save
212Use IEEE math for fp comparisons
213
214minline-all-stringops
215Target Report Mask(INLINE_ALL_STRINGOPS) Save
216Inline all known string operations
217
218minline-stringops-dynamically
219Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
220Inline memset/memcpy string operations, but perform inline version only for small blocks
221
222mintel-syntax
223Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
224;; Deprecated
225
226mms-bitfields
227Target Report Mask(MS_BITFIELD_LAYOUT) Save
228Use native (MS) bitfield layout
229
230mno-align-stringops
231Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
232
233mno-fancy-math-387
234Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
235
236mno-push-args
237Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
238
239mno-red-zone
240Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
241
242momit-leaf-frame-pointer
243Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
244Omit the frame pointer in leaf functions
245
246mpc32
247Target RejectNegative Report
248Set 80387 floating-point precision to 32-bit
249
250mpc64
251Target RejectNegative Report
252Set 80387 floating-point precision to 64-bit
253
254mpc80
255Target RejectNegative Report
256Set 80387 floating-point precision to 80-bit
257
258mpreferred-stack-boundary=
259Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
260Attempt to keep stack aligned to this power of 2
261
262mincoming-stack-boundary=
263Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
264Assume incoming stack aligned to this power of 2
265
266mpush-args
267Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
268Use push instructions to save outgoing arguments
269
270mred-zone
271Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
272Use red-zone in the x86-64 code
273
274mregparm=
275Target RejectNegative Joined UInteger Var(ix86_regparm)
276Number of registers used to pass integer arguments
277
278mrtd
279Target Report Mask(RTD) Save
280Alternate calling convention
281
282msoft-float
283Target InverseMask(80387) Save
284Do not use hardware fp
285
286msseregparm
287Target RejectNegative Mask(SSEREGPARM) Save
288Use SSE register passing conventions for SF and DF mode
289
290mstackrealign
291Target Report Var(ix86_force_align_arg_pointer) Init(-1)
292Realign stack in prologue
293
294mstack-arg-probe
295Target Report Mask(STACK_PROBE) Save
296Enable stack probing
297
298mstringop-strategy=
299Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
300Chose strategy to generate stringop using
301
302Enum
303Name(stringop_alg) Type(enum stringop_alg)
304Valid arguments to -mstringop-strategy=:
305
306EnumValue
307Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
308
309EnumValue
310Enum(stringop_alg) String(libcall) Value(libcall)
311
312EnumValue
313Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte)
314
315EnumValue
316Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte)
317
318EnumValue
319Enum(stringop_alg) String(byte_loop) Value(loop_1_byte)
320
321EnumValue
322Enum(stringop_alg) String(loop) Value(loop)
323
324EnumValue
325Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop)
326
327mtls-dialect=
328Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
329Use given thread-local storage dialect
330
331Enum
332Name(tls_dialect) Type(enum tls_dialect)
333Known TLS dialects (for use with the -mtls-dialect= option):
334
335EnumValue
336Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU)
337
338EnumValue
339Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
340
341mtls-direct-seg-refs
342Target Report Mask(TLS_DIRECT_SEG_REFS)
343Use direct references against %gs when accessing tls data
344
345mtune=
346Target RejectNegative Joined Var(ix86_tune_string)
347Schedule code for given CPU
348
349mabi=
350Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
351Generate code that conforms to the given ABI
352
353Enum
354Name(calling_abi) Type(enum calling_abi)
355Known ABIs (for use with the -mabi= option):
356
357EnumValue
358Enum(calling_abi) String(sysv) Value(SYSV_ABI)
359
360EnumValue
361Enum(calling_abi) String(ms) Value(MS_ABI)
362
363mveclibabi=
364Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
365Vector library ABI to use
366
367Enum
368Name(ix86_veclibabi) Type(enum ix86_veclibabi)
369Known vectorization library ABIs (for use with the -mveclibabi= option):
370
371EnumValue
372Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml)
373
374EnumValue
375Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
376
377mvect8-ret-in-mem
378Target Report Mask(VECT8_RETURNS) Save
379Return 8-byte vectors in memory
380
381mrecip
382Target Report Mask(RECIP) Save
383Generate reciprocals instead of divss and sqrtss.
384
385mrecip=
386Target Report RejectNegative Joined Var(ix86_recip_name)
387Control generation of reciprocal estimates.
388
389mcld
390Target Report Mask(CLD) Save
391Generate cld instruction in the function prologue.
392
393mvzeroupper
394Target Report Mask(VZEROUPPER) Save
395Generate vzeroupper instruction before a transfer of control flow out of
396the function.
397
398mdispatch-scheduler
399Target RejectNegative Var(flag_dispatch_scheduler)
400Do dispatch scheduling if processor is bdver1 or bdver2 and Haifa scheduling
401is selected.
402
403mprefer-avx128
404Target Report Mask(PREFER_AVX128) SAVE
405Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
406
407;; ISA support
408
409m32
410Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
411Generate 32bit i386 code
412
413m64
414Target RejectNegative Negative(mx32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) Save
415Generate 64bit x86-64 code
416
417mx32
418Target RejectNegative Negative(m32) Report Mask(ISA_X32) Var(ix86_isa_flags) Save
419Generate 32bit x86-64 code
420
421mmmx
422Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
423Support MMX built-in functions
424
425m3dnow
426Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
427Support 3DNow! built-in functions
428
429m3dnowa
430Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
431Support Athlon 3Dnow! built-in functions
432
433msse
434Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
435Support MMX and SSE built-in functions and code generation
436
437msse2
438Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
439Support MMX, SSE and SSE2 built-in functions and code generation
440
441msse3
442Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
443Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
444
445mssse3
446Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
447Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
448
449msse4.1
450Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
451Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
452
453msse4.2
454Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
455Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
456
457msse4
458Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) Save
459Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
460
461mno-sse4
462Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) Save
463Do not support SSE4.1 and SSE4.2 built-in functions and code generation
464
465msse5
466Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
467;; Deprecated
468
469mavx
470Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
471Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
472
473mavx2
474Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
475Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation
476
477mfma
478Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
479Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
480
481msse4a
482Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
483Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
484
485mfma4
486Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
487Support FMA4 built-in functions and code generation
488
489mxop
490Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
491Support XOP built-in functions and code generation
492
493mlwp
494Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
495Support LWP built-in functions and code generation
496
497mabm
498Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
499Support code generation of Advanced Bit Manipulation (ABM) instructions.
500
501mpopcnt
502Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
503Support code generation of popcnt instruction.
504
505mbmi
506Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
507Support BMI built-in functions and code generation
508
509mbmi2
510Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
511Support BMI2 built-in functions and code generation
512
513mlzcnt
514Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
515Support LZCNT built-in function and code generation
516
517mtbm
518Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
519Support TBM built-in functions and code generation
520
521mcx16
522Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save
523Support code generation of cmpxchg16b instruction.
524
525msahf
526Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
527Support code generation of sahf instruction in 64bit x86-64 code.
528
529mmovbe
530Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save
531Support code generation of movbe instruction.
532
533mcrc32
534Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
535Support code generation of crc32 instruction.
536
537maes
538Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
539Support AES built-in functions and code generation
540
541mpclmul
542Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
543Support PCLMUL built-in functions and code generation
544
545msse2avx
546Target Report Var(ix86_sse2avx)
547Encode SSE instructions with VEX prefix
548
549mfsgsbase
550Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
551Support FSGSBASE built-in functions and code generation
552
553mrdrnd
554Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
555Support RDRND built-in functions and code generation
556
557mf16c
558Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
559Support F16C built-in functions and code generation
560
561mfentry
562Target Report Var(flag_fentry) Init(-1)
563Emit profiling counter call at function entry before prologue.
564
565m8bit-idiv
566Target Report Mask(USE_8BIT_IDIV) Save
567Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check
568
569mavx256-split-unaligned-load
570Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
571Split 32-byte AVX unaligned load
572
573mavx256-split-unaligned-store
574Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
575Split 32-byte AVX unaligned store
576