1*e4b17023SJohn Marino;; AMD K6/K6-2 Scheduling 2*e4b17023SJohn Marino;; Copyright (C) 2002, 2004, 2007 3*e4b17023SJohn Marino;; Free Software Foundation, Inc. 4*e4b17023SJohn Marino;; 5*e4b17023SJohn Marino;; This file is part of GCC. 6*e4b17023SJohn Marino;; 7*e4b17023SJohn Marino;; GCC is free software; you can redistribute it and/or modify 8*e4b17023SJohn Marino;; it under the terms of the GNU General Public License as published by 9*e4b17023SJohn Marino;; the Free Software Foundation; either version 3, or (at your option) 10*e4b17023SJohn Marino;; any later version. 11*e4b17023SJohn Marino;; 12*e4b17023SJohn Marino;; GCC is distributed in the hope that it will be useful, 13*e4b17023SJohn Marino;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14*e4b17023SJohn Marino;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*e4b17023SJohn Marino;; GNU General Public License for more details. 16*e4b17023SJohn Marino;; 17*e4b17023SJohn Marino;; You should have received a copy of the GNU General Public License 18*e4b17023SJohn Marino;; along with GCC; see the file COPYING3. If not see 19*e4b17023SJohn Marino;; <http://www.gnu.org/licenses/>. 20*e4b17023SJohn Marino;; 21*e4b17023SJohn Marino;; The K6 architecture is quite similar to PPro. Important difference is 22*e4b17023SJohn Marino;; that there are only two decoders and they seems to be much slower than 23*e4b17023SJohn Marino;; any of the execution units. So we have to pay much more attention to 24*e4b17023SJohn Marino;; proper scheduling for the decoders. 25*e4b17023SJohn Marino;; FIXME: We don't do that right now. A good start would be to sort the 26*e4b17023SJohn Marino;; instructions based on length. 27*e4b17023SJohn Marino;; 28*e4b17023SJohn Marino;; This description is based on data from the following documents: 29*e4b17023SJohn Marino;; 30*e4b17023SJohn Marino;; "AMD-K6 Processor Data Sheet (Preliminary information)" 31*e4b17023SJohn Marino;; Advanced Micro Devices, Inc., 1998. 32*e4b17023SJohn Marino;; 33*e4b17023SJohn Marino;; "AMD-K6 Processor Code Optimization Application Note" 34*e4b17023SJohn Marino;; Advanced Micro Devices, Inc., 2000. 35*e4b17023SJohn Marino;; 36*e4b17023SJohn Marino;; CPU execution units of the K6: 37*e4b17023SJohn Marino;; 38*e4b17023SJohn Marino;; store describes the Store unit. This unit is not modelled 39*e4b17023SJohn Marino;; completely and it is only used to model lea operation. 40*e4b17023SJohn Marino;; Otherwise it lies outside of any critical path. 41*e4b17023SJohn Marino;; load describes the Load unit 42*e4b17023SJohn Marino;; alux describes the Integer X unit 43*e4b17023SJohn Marino;; mm describes the Multimedia unit, which shares a pipe 44*e4b17023SJohn Marino;; with the Integer X unit. This unit is used for MMX, 45*e4b17023SJohn Marino;; which is not implemented for K6. 46*e4b17023SJohn Marino;; aluy describes the Integer Y unit 47*e4b17023SJohn Marino;; fpu describes the FPU unit 48*e4b17023SJohn Marino;; branch describes the Branch unit 49*e4b17023SJohn Marino;; 50*e4b17023SJohn Marino;; The fp unit is not pipelined, and it can only do one operation per two 51*e4b17023SJohn Marino;; cycles, including fxcg. 52*e4b17023SJohn Marino;; 53*e4b17023SJohn Marino;; Generally this is a very poor description, but at least no worse than 54*e4b17023SJohn Marino;; the old description, and a lot easier to extend to something more 55*e4b17023SJohn Marino;; reasonable if anyone still cares enough about this architecture in 2004. 56*e4b17023SJohn Marino;; 57*e4b17023SJohn Marino;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real. 58*e4b17023SJohn Marino 59*e4b17023SJohn Marino(define_automaton "k6_decoder,k6_load_unit,k6_store_unit,k6_integer_units,k6_fpu_unit,k6_branch_unit") 60*e4b17023SJohn Marino 61*e4b17023SJohn Marino;; The K6 instruction decoding begins before the on-chip instruction cache is 62*e4b17023SJohn Marino;; filled. Depending on the length of the instruction, two simple instructions 63*e4b17023SJohn Marino;; can be decoded in two parallel short decoders, or one complex instruction can 64*e4b17023SJohn Marino;; be decoded in either the long or the vector decoder. For all practical 65*e4b17023SJohn Marino;; purposes, the long and vector decoder can be modelled as one decoder. 66*e4b17023SJohn Marino(define_cpu_unit "k6_decode_short0" "k6_decoder") 67*e4b17023SJohn Marino(define_cpu_unit "k6_decode_short1" "k6_decoder") 68*e4b17023SJohn Marino(define_cpu_unit "k6_decode_long" "k6_decoder") 69*e4b17023SJohn Marino(exclusion_set "k6_decode_long" "k6_decode_short0,k6_decode_short1") 70*e4b17023SJohn Marino(define_reservation "k6_decode_short" "k6_decode_short0|k6_decode_short1") 71*e4b17023SJohn Marino(define_reservation "k6_decode_vector" "k6_decode_long") 72*e4b17023SJohn Marino 73*e4b17023SJohn Marino(define_cpu_unit "k6_store" "k6_store_unit") 74*e4b17023SJohn Marino(define_cpu_unit "k6_load" "k6_load_unit") 75*e4b17023SJohn Marino(define_cpu_unit "k6_alux,k6_aluy" "k6_integer_units") 76*e4b17023SJohn Marino(define_cpu_unit "k6_fpu" "k6_fpu_unit") 77*e4b17023SJohn Marino(define_cpu_unit "k6_branch" "k6_branch_unit") 78*e4b17023SJohn Marino 79*e4b17023SJohn Marino;; Shift instructions and certain arithmetic are issued only on Integer X. 80*e4b17023SJohn Marino(define_insn_reservation "k6_alux_only" 1 81*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 82*e4b17023SJohn Marino (and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot") 83*e4b17023SJohn Marino (eq_attr "memory" "none"))) 84*e4b17023SJohn Marino "k6_decode_short,k6_alux") 85*e4b17023SJohn Marino 86*e4b17023SJohn Marino(define_insn_reservation "k6_alux_only_load" 3 87*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 88*e4b17023SJohn Marino (and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot") 89*e4b17023SJohn Marino (eq_attr "memory" "load"))) 90*e4b17023SJohn Marino "k6_decode_short,k6_load,k6_alux") 91*e4b17023SJohn Marino 92*e4b17023SJohn Marino(define_insn_reservation "k6_alux_only_store" 3 93*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 94*e4b17023SJohn Marino (and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot") 95*e4b17023SJohn Marino (eq_attr "memory" "store,both,unknown"))) 96*e4b17023SJohn Marino "k6_decode_long,k6_load,k6_alux,k6_store") 97*e4b17023SJohn Marino 98*e4b17023SJohn Marino;; Integer divide and multiply can only be issued on Integer X, too. 99*e4b17023SJohn Marino(define_insn_reservation "k6_alu_imul" 2 100*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 101*e4b17023SJohn Marino (eq_attr "type" "imul")) 102*e4b17023SJohn Marino "k6_decode_vector,k6_alux*3") 103*e4b17023SJohn Marino 104*e4b17023SJohn Marino(define_insn_reservation "k6_alu_imul_load" 4 105*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 106*e4b17023SJohn Marino (and (eq_attr "type" "imul") 107*e4b17023SJohn Marino (eq_attr "memory" "load"))) 108*e4b17023SJohn Marino "k6_decode_vector,k6_load,k6_alux*3") 109*e4b17023SJohn Marino 110*e4b17023SJohn Marino(define_insn_reservation "k6_alu_imul_store" 4 111*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 112*e4b17023SJohn Marino (and (eq_attr "type" "imul") 113*e4b17023SJohn Marino (eq_attr "memory" "store,both,unknown"))) 114*e4b17023SJohn Marino "k6_decode_vector,k6_load,k6_alux*3,k6_store") 115*e4b17023SJohn Marino 116*e4b17023SJohn Marino;; ??? Guessed latencies based on the old pipeline description. 117*e4b17023SJohn Marino(define_insn_reservation "k6_alu_idiv" 17 118*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 119*e4b17023SJohn Marino (and (eq_attr "type" "idiv") 120*e4b17023SJohn Marino (eq_attr "memory" "none"))) 121*e4b17023SJohn Marino "k6_decode_vector,k6_alux*17") 122*e4b17023SJohn Marino 123*e4b17023SJohn Marino(define_insn_reservation "k6_alu_idiv_mem" 19 124*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 125*e4b17023SJohn Marino (and (eq_attr "type" "idiv") 126*e4b17023SJohn Marino (eq_attr "memory" "!none"))) 127*e4b17023SJohn Marino "k6_decode_vector,k6_load,k6_alux*17") 128*e4b17023SJohn Marino 129*e4b17023SJohn Marino;; Basic word and doubleword ALU ops can be issued on both Integer units. 130*e4b17023SJohn Marino(define_insn_reservation "k6_alu" 1 131*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 132*e4b17023SJohn Marino (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc") 133*e4b17023SJohn Marino (eq_attr "memory" "none"))) 134*e4b17023SJohn Marino "k6_decode_short,k6_alux|k6_aluy") 135*e4b17023SJohn Marino 136*e4b17023SJohn Marino(define_insn_reservation "k6_alu_load" 3 137*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 138*e4b17023SJohn Marino (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc") 139*e4b17023SJohn Marino (eq_attr "memory" "load"))) 140*e4b17023SJohn Marino "k6_decode_short,k6_load,k6_alux|k6_aluy") 141*e4b17023SJohn Marino 142*e4b17023SJohn Marino(define_insn_reservation "k6_alu_store" 3 143*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 144*e4b17023SJohn Marino (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc") 145*e4b17023SJohn Marino (eq_attr "memory" "store,both,unknown"))) 146*e4b17023SJohn Marino "k6_decode_long,k6_load,k6_alux|k6_aluy,k6_store") 147*e4b17023SJohn Marino 148*e4b17023SJohn Marino;; A "load immediate" operation does not require execution at all, 149*e4b17023SJohn Marino;; it is available immediately after decoding. Special-case this. 150*e4b17023SJohn Marino(define_insn_reservation "k6_alu_imov" 1 151*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 152*e4b17023SJohn Marino (and (eq_attr "type" "imov") 153*e4b17023SJohn Marino (and (eq_attr "memory" "none") 154*e4b17023SJohn Marino (match_operand 1 "nonimmediate_operand")))) 155*e4b17023SJohn Marino "k6_decode_short,k6_alux|k6_aluy") 156*e4b17023SJohn Marino 157*e4b17023SJohn Marino(define_insn_reservation "k6_alu_imov_imm" 0 158*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 159*e4b17023SJohn Marino (and (eq_attr "type" "imov") 160*e4b17023SJohn Marino (and (eq_attr "memory" "none") 161*e4b17023SJohn Marino (match_operand 1 "immediate_operand")))) 162*e4b17023SJohn Marino "k6_decode_short") 163*e4b17023SJohn Marino 164*e4b17023SJohn Marino(define_insn_reservation "k6_alu_imov_load" 2 165*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 166*e4b17023SJohn Marino (and (eq_attr "type" "imov") 167*e4b17023SJohn Marino (eq_attr "memory" "load"))) 168*e4b17023SJohn Marino "k6_decode_short,k6_load") 169*e4b17023SJohn Marino 170*e4b17023SJohn Marino(define_insn_reservation "k6_alu_imov_store" 1 171*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 172*e4b17023SJohn Marino (and (eq_attr "type" "imov") 173*e4b17023SJohn Marino (eq_attr "memory" "store"))) 174*e4b17023SJohn Marino "k6_decode_short,k6_store") 175*e4b17023SJohn Marino 176*e4b17023SJohn Marino(define_insn_reservation "k6_alu_imov_both" 2 177*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 178*e4b17023SJohn Marino (and (eq_attr "type" "imov") 179*e4b17023SJohn Marino (eq_attr "memory" "both,unknown"))) 180*e4b17023SJohn Marino "k6_decode_long,k6_load,k6_alux|k6_aluy") 181*e4b17023SJohn Marino 182*e4b17023SJohn Marino;; The branch unit. 183*e4b17023SJohn Marino(define_insn_reservation "k6_branch_call" 1 184*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 185*e4b17023SJohn Marino (eq_attr "type" "call,callv")) 186*e4b17023SJohn Marino "k6_decode_vector,k6_branch") 187*e4b17023SJohn Marino 188*e4b17023SJohn Marino(define_insn_reservation "k6_branch_branch" 1 189*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 190*e4b17023SJohn Marino (eq_attr "type" "ibr")) 191*e4b17023SJohn Marino "k6_decode_short,k6_branch") 192*e4b17023SJohn Marino 193*e4b17023SJohn Marino;; The load and units have two pipeline stages. The load latency is 194*e4b17023SJohn Marino;; two cycles. 195*e4b17023SJohn Marino(define_insn_reservation "k6_load_pop" 3 196*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 197*e4b17023SJohn Marino (ior (eq_attr "type" "pop") 198*e4b17023SJohn Marino (eq_attr "memory" "load,both"))) 199*e4b17023SJohn Marino "k6_decode_short,k6_load") 200*e4b17023SJohn Marino 201*e4b17023SJohn Marino(define_insn_reservation "k6_load_leave" 5 202*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 203*e4b17023SJohn Marino (eq_attr "type" "leave")) 204*e4b17023SJohn Marino "k6_decode_long,k6_load,(k6_alux|k6_aluy)*2") 205*e4b17023SJohn Marino 206*e4b17023SJohn Marino;; ??? From the old pipeline description. Egad! 207*e4b17023SJohn Marino;; ??? Apparently we take care of this reservation in adjust_cost. 208*e4b17023SJohn Marino(define_insn_reservation "k6_load_str" 10 209*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 210*e4b17023SJohn Marino (and (eq_attr "type" "str") 211*e4b17023SJohn Marino (eq_attr "memory" "load,both"))) 212*e4b17023SJohn Marino "k6_decode_vector,k6_load*10") 213*e4b17023SJohn Marino 214*e4b17023SJohn Marino;; The store unit handles lea and push. It is otherwise unmodelled. 215*e4b17023SJohn Marino(define_insn_reservation "k6_store_lea" 2 216*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 217*e4b17023SJohn Marino (eq_attr "type" "lea")) 218*e4b17023SJohn Marino "k6_decode_short,k6_store,k6_alux|k6_aluy") 219*e4b17023SJohn Marino 220*e4b17023SJohn Marino(define_insn_reservation "k6_store_push" 2 221*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 222*e4b17023SJohn Marino (ior (eq_attr "type" "push") 223*e4b17023SJohn Marino (eq_attr "memory" "store,both"))) 224*e4b17023SJohn Marino "k6_decode_short,k6_store") 225*e4b17023SJohn Marino 226*e4b17023SJohn Marino(define_insn_reservation "k6_store_str" 10 227*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 228*e4b17023SJohn Marino (eq_attr "type" "str")) 229*e4b17023SJohn Marino "k6_store*10") 230*e4b17023SJohn Marino 231*e4b17023SJohn Marino;; Most FPU instructions have latency 2 and throughput 2. 232*e4b17023SJohn Marino(define_insn_reservation "k6_fpu" 2 233*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 234*e4b17023SJohn Marino (and (eq_attr "type" "fop,fmov,fcmp,fistp") 235*e4b17023SJohn Marino (eq_attr "memory" "none"))) 236*e4b17023SJohn Marino "k6_decode_vector,k6_fpu*2") 237*e4b17023SJohn Marino 238*e4b17023SJohn Marino(define_insn_reservation "k6_fpu_load" 6 239*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 240*e4b17023SJohn Marino (and (eq_attr "type" "fop,fmov,fcmp,fistp") 241*e4b17023SJohn Marino (eq_attr "memory" "load,both"))) 242*e4b17023SJohn Marino "k6_decode_short,k6_load,k6_fpu*2") 243*e4b17023SJohn Marino 244*e4b17023SJohn Marino(define_insn_reservation "k6_fpu_store" 6 245*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 246*e4b17023SJohn Marino (and (eq_attr "type" "fop,fmov,fcmp,fistp") 247*e4b17023SJohn Marino (eq_attr "memory" "store"))) 248*e4b17023SJohn Marino "k6_decode_short,k6_store,k6_fpu*2") 249*e4b17023SJohn Marino 250*e4b17023SJohn Marino(define_insn_reservation "k6_fpu_fmul" 2 251*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 252*e4b17023SJohn Marino (and (eq_attr "type" "fmul") 253*e4b17023SJohn Marino (eq_attr "memory" "none"))) 254*e4b17023SJohn Marino "k6_decode_short,k6_fpu*2") 255*e4b17023SJohn Marino 256*e4b17023SJohn Marino(define_insn_reservation "k6_fpu_fmul_load" 2 257*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 258*e4b17023SJohn Marino (and (eq_attr "type" "fmul") 259*e4b17023SJohn Marino (eq_attr "memory" "load,both"))) 260*e4b17023SJohn Marino "k6_decode_short,k6_load,k6_fpu*2") 261*e4b17023SJohn Marino 262*e4b17023SJohn Marino;; ??? Guessed latencies from the old pipeline description. 263*e4b17023SJohn Marino(define_insn_reservation "k6_fpu_expensive" 56 264*e4b17023SJohn Marino (and (eq_attr "cpu" "k6") 265*e4b17023SJohn Marino (eq_attr "type" "fdiv,fpspc")) 266*e4b17023SJohn Marino "k6_decode_short,k6_fpu*56") 267*e4b17023SJohn Marino 268