1;; GCC machine description for i386 synchronization instructions. 2;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011 3;; Free Software Foundation, Inc. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_c_enum "unspec" [ 22 UNSPEC_LFENCE 23 UNSPEC_SFENCE 24 UNSPEC_MFENCE 25 UNSPEC_MOVA ; For __atomic support 26 UNSPEC_LDA 27 UNSPEC_STA 28]) 29 30(define_c_enum "unspecv" [ 31 UNSPECV_CMPXCHG 32 UNSPECV_XCHG 33 UNSPECV_LOCK 34]) 35 36(define_expand "sse2_lfence" 37 [(set (match_dup 0) 38 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))] 39 "TARGET_SSE2" 40{ 41 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 42 MEM_VOLATILE_P (operands[0]) = 1; 43}) 44 45(define_insn "*sse2_lfence" 46 [(set (match_operand:BLK 0 "" "") 47 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))] 48 "TARGET_SSE2" 49 "lfence" 50 [(set_attr "type" "sse") 51 (set_attr "length_address" "0") 52 (set_attr "atom_sse_attr" "lfence") 53 (set_attr "memory" "unknown")]) 54 55(define_expand "sse_sfence" 56 [(set (match_dup 0) 57 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))] 58 "TARGET_SSE || TARGET_3DNOW_A" 59{ 60 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 61 MEM_VOLATILE_P (operands[0]) = 1; 62}) 63 64(define_insn "*sse_sfence" 65 [(set (match_operand:BLK 0 "" "") 66 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))] 67 "TARGET_SSE || TARGET_3DNOW_A" 68 "sfence" 69 [(set_attr "type" "sse") 70 (set_attr "length_address" "0") 71 (set_attr "atom_sse_attr" "fence") 72 (set_attr "memory" "unknown")]) 73 74(define_expand "sse2_mfence" 75 [(set (match_dup 0) 76 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] 77 "TARGET_SSE2" 78{ 79 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 80 MEM_VOLATILE_P (operands[0]) = 1; 81}) 82 83(define_insn "mfence_sse2" 84 [(set (match_operand:BLK 0 "" "") 85 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] 86 "TARGET_64BIT || TARGET_SSE2" 87 "mfence" 88 [(set_attr "type" "sse") 89 (set_attr "length_address" "0") 90 (set_attr "atom_sse_attr" "fence") 91 (set_attr "memory" "unknown")]) 92 93(define_insn "mfence_nosse" 94 [(set (match_operand:BLK 0 "" "") 95 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE)) 96 (clobber (reg:CC FLAGS_REG))] 97 "!(TARGET_64BIT || TARGET_SSE2)" 98 "lock{%;} or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}" 99 [(set_attr "memory" "unknown")]) 100 101(define_expand "mem_thread_fence" 102 [(match_operand:SI 0 "const_int_operand" "")] ;; model 103 "" 104{ 105 /* Unless this is a SEQ_CST fence, the i386 memory model is strong 106 enough not to require barriers of any kind. */ 107 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST) 108 { 109 rtx (*mfence_insn)(rtx); 110 rtx mem; 111 112 if (TARGET_64BIT || TARGET_SSE2) 113 mfence_insn = gen_mfence_sse2; 114 else 115 mfence_insn = gen_mfence_nosse; 116 117 mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 118 MEM_VOLATILE_P (mem) = 1; 119 120 emit_insn (mfence_insn (mem)); 121 } 122 DONE; 123}) 124 125;; ??? From volume 3 section 8.1.1 Guaranteed Atomic Operations, 126;; Only beginning at Pentium family processors do we get any guarantee of 127;; atomicity in aligned 64-bit quantities. Beginning at P6, we get a 128;; guarantee for 64-bit accesses that do not cross a cacheline boundary. 129;; 130;; Note that the TARGET_CMPXCHG8B test below is a stand-in for "Pentium". 131;; 132;; Importantly, *no* processor makes atomicity guarantees for larger 133;; accesses. In particular, there's no way to perform an atomic TImode 134;; move, despite the apparent applicability of MOVDQA et al. 135 136(define_mode_iterator ATOMIC 137 [QI HI SI 138 (DI "TARGET_64BIT || (TARGET_CMPXCHG8B && (TARGET_80387 || TARGET_SSE))") 139 ]) 140 141(define_expand "atomic_load<mode>" 142 [(set (match_operand:ATOMIC 0 "register_operand" "") 143 (unspec:ATOMIC [(match_operand:ATOMIC 1 "memory_operand" "") 144 (match_operand:SI 2 "const_int_operand" "")] 145 UNSPEC_MOVA))] 146 "" 147{ 148 /* For DImode on 32-bit, we can use the FPU to perform the load. */ 149 if (<MODE>mode == DImode && !TARGET_64BIT) 150 emit_insn (gen_atomic_loaddi_fpu 151 (operands[0], operands[1], 152 assign_386_stack_local (DImode, 153 (virtuals_instantiated 154 ? SLOT_TEMP : SLOT_VIRTUAL)))); 155 else 156 emit_move_insn (operands[0], operands[1]); 157 DONE; 158}) 159 160(define_insn_and_split "atomic_loaddi_fpu" 161 [(set (match_operand:DI 0 "nonimmediate_operand" "=x,m,?r") 162 (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m,m")] 163 UNSPEC_MOVA)) 164 (clobber (match_operand:DI 2 "memory_operand" "=X,X,m")) 165 (clobber (match_scratch:DF 3 "=X,xf,xf"))] 166 "!TARGET_64BIT && (TARGET_80387 || TARGET_SSE)" 167 "#" 168 "&& reload_completed" 169 [(const_int 0)] 170{ 171 rtx dst = operands[0], src = operands[1]; 172 rtx mem = operands[2], tmp = operands[3]; 173 174 if (SSE_REG_P (dst)) 175 emit_move_insn (dst, src); 176 else 177 { 178 if (MEM_P (dst)) 179 mem = dst; 180 181 if (FP_REG_P (tmp)) 182 { 183 emit_insn (gen_loaddi_via_fpu (tmp, src)); 184 emit_insn (gen_storedi_via_fpu (mem, tmp)); 185 } 186 else 187 { 188 adjust_reg_mode (tmp, DImode); 189 emit_move_insn (tmp, src); 190 emit_move_insn (mem, tmp); 191 } 192 193 if (mem != dst) 194 emit_move_insn (dst, mem); 195 } 196 DONE; 197}) 198 199(define_expand "atomic_store<mode>" 200 [(set (match_operand:ATOMIC 0 "memory_operand" "") 201 (unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand" "") 202 (match_operand:SI 2 "const_int_operand" "")] 203 UNSPEC_MOVA))] 204 "" 205{ 206 enum memmodel model = (enum memmodel) INTVAL (operands[2]); 207 208 if (<MODE>mode == DImode && !TARGET_64BIT) 209 { 210 /* For DImode on 32-bit, we can use the FPU to perform the store. */ 211 /* Note that while we could perform a cmpxchg8b loop, that turns 212 out to be significantly larger than this plus a barrier. */ 213 emit_insn (gen_atomic_storedi_fpu 214 (operands[0], operands[1], 215 assign_386_stack_local (DImode, 216 (virtuals_instantiated 217 ? SLOT_TEMP : SLOT_VIRTUAL)))); 218 } 219 else 220 { 221 /* For seq-cst stores, when we lack MFENCE, use XCHG. */ 222 if (model == MEMMODEL_SEQ_CST && !(TARGET_64BIT || TARGET_SSE2)) 223 { 224 emit_insn (gen_atomic_exchange<mode> (gen_reg_rtx (<MODE>mode), 225 operands[0], operands[1], 226 operands[2])); 227 DONE; 228 } 229 230 /* Otherwise use a normal store. */ 231 emit_move_insn (operands[0], operands[1]); 232 } 233 /* ... followed by an MFENCE, if required. */ 234 if (model == MEMMODEL_SEQ_CST) 235 emit_insn (gen_mem_thread_fence (operands[2])); 236 DONE; 237}) 238 239(define_insn_and_split "atomic_storedi_fpu" 240 [(set (match_operand:DI 0 "memory_operand" "=m,m,m") 241 (unspec:DI [(match_operand:DI 1 "register_operand" "x,m,?r")] 242 UNSPEC_MOVA)) 243 (clobber (match_operand:DI 2 "memory_operand" "=X,X,m")) 244 (clobber (match_scratch:DF 3 "=X,xf,xf"))] 245 "!TARGET_64BIT && (TARGET_80387 || TARGET_SSE)" 246 "#" 247 "&& reload_completed" 248 [(const_int 0)] 249{ 250 rtx dst = operands[0], src = operands[1]; 251 rtx mem = operands[2], tmp = operands[3]; 252 253 if (!SSE_REG_P (src)) 254 { 255 if (REG_P (src)) 256 { 257 emit_move_insn (mem, src); 258 src = mem; 259 } 260 261 if (FP_REG_P (tmp)) 262 { 263 emit_insn (gen_loaddi_via_fpu (tmp, src)); 264 emit_insn (gen_storedi_via_fpu (dst, tmp)); 265 DONE; 266 } 267 else 268 { 269 adjust_reg_mode (tmp, DImode); 270 emit_move_insn (tmp, mem); 271 src = tmp; 272 } 273 } 274 emit_move_insn (dst, src); 275 DONE; 276}) 277 278;; ??? You'd think that we'd be able to perform this via FLOAT + FIX_TRUNC 279;; operations. But the fix_trunc patterns want way more setup than we want 280;; to provide. Note that the scratch is DFmode instead of XFmode in order 281;; to make it easy to allocate a scratch in either SSE or FP_REGs above. 282 283(define_insn "loaddi_via_fpu" 284 [(set (match_operand:DF 0 "register_operand" "=f") 285 (unspec:DF [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_LDA))] 286 "TARGET_80387" 287 "fild%Z1\t%1" 288 [(set_attr "type" "fmov") 289 (set_attr "mode" "DF") 290 (set_attr "fp_int_src" "true")]) 291 292(define_insn "storedi_via_fpu" 293 [(set (match_operand:DI 0 "memory_operand" "=m") 294 (unspec:DI [(match_operand:DF 1 "register_operand" "f")] UNSPEC_STA))] 295 "TARGET_80387" 296{ 297 gcc_assert (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != NULL_RTX); 298 299 return "fistp%Z0\t%0"; 300} 301 [(set_attr "type" "fmov") 302 (set_attr "mode" "DI")]) 303 304(define_expand "atomic_compare_and_swap<mode>" 305 [(match_operand:QI 0 "register_operand" "") ;; bool success output 306 (match_operand:SWI124 1 "register_operand" "") ;; oldval output 307 (match_operand:SWI124 2 "memory_operand" "") ;; memory 308 (match_operand:SWI124 3 "register_operand" "") ;; expected input 309 (match_operand:SWI124 4 "register_operand" "") ;; newval input 310 (match_operand:SI 5 "const_int_operand" "") ;; is_weak 311 (match_operand:SI 6 "const_int_operand" "") ;; success model 312 (match_operand:SI 7 "const_int_operand" "")] ;; failure model 313 "TARGET_CMPXCHG" 314{ 315 emit_insn 316 (gen_atomic_compare_and_swap<mode>_1 317 (operands[1], operands[2], operands[3], operands[4])); 318 ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG), 319 const0_rtx); 320 DONE; 321}) 322 323(define_mode_iterator CASMODE 324 [(DI "TARGET_64BIT || TARGET_CMPXCHG8B") 325 (TI "TARGET_64BIT && TARGET_CMPXCHG16B")]) 326(define_mode_attr CASHMODE [(DI "SI") (TI "DI")]) 327 328(define_expand "atomic_compare_and_swap<mode>" 329 [(match_operand:QI 0 "register_operand" "") ;; bool success output 330 (match_operand:CASMODE 1 "register_operand" "") ;; oldval output 331 (match_operand:CASMODE 2 "memory_operand" "") ;; memory 332 (match_operand:CASMODE 3 "register_operand" "") ;; expected input 333 (match_operand:CASMODE 4 "register_operand" "") ;; newval input 334 (match_operand:SI 5 "const_int_operand" "") ;; is_weak 335 (match_operand:SI 6 "const_int_operand" "") ;; success model 336 (match_operand:SI 7 "const_int_operand" "")] ;; failure model 337 "TARGET_CMPXCHG" 338{ 339 if (<MODE>mode == DImode && TARGET_64BIT) 340 { 341 emit_insn 342 (gen_atomic_compare_and_swapdi_1 343 (operands[1], operands[2], operands[3], operands[4])); 344 } 345 else 346 { 347 enum machine_mode hmode = <CASHMODE>mode; 348 rtx lo_o, lo_e, lo_n, hi_o, hi_e, hi_n, mem; 349 350 lo_o = operands[1]; 351 mem = operands[2]; 352 lo_e = operands[3]; 353 lo_n = operands[4]; 354 hi_o = gen_highpart (hmode, lo_o); 355 hi_e = gen_highpart (hmode, lo_e); 356 hi_n = gen_highpart (hmode, lo_n); 357 lo_o = gen_lowpart (hmode, lo_o); 358 lo_e = gen_lowpart (hmode, lo_e); 359 lo_n = gen_lowpart (hmode, lo_n); 360 361 if (!cmpxchg8b_pic_memory_operand (mem, <MODE>mode)) 362 mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0))); 363 364 emit_insn 365 (gen_atomic_compare_and_swap<mode>_doubleword 366 (lo_o, hi_o, mem, lo_e, hi_e, lo_n, hi_n)); 367 } 368 369 ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG), 370 const0_rtx); 371 DONE; 372}) 373 374(define_insn "atomic_compare_and_swap<mode>_1" 375 [(set (match_operand:SWI 0 "register_operand" "=a") 376 (unspec_volatile:SWI 377 [(match_operand:SWI 1 "memory_operand" "+m") 378 (match_operand:SWI 2 "register_operand" "0") 379 (match_operand:SWI 3 "register_operand" "<r>")] 380 UNSPECV_CMPXCHG)) 381 (set (match_dup 1) 382 (unspec_volatile:SWI [(const_int 0)] UNSPECV_CMPXCHG)) 383 (set (reg:CCZ FLAGS_REG) 384 (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG))] 385 "TARGET_CMPXCHG" 386 "lock{%;} cmpxchg{<imodesuffix>}\t{%3, %1|%1, %3}") 387 388;; For double-word compare and swap, we are obliged to play tricks with 389;; the input newval (op5:op6) because the Intel register numbering does 390;; not match the gcc register numbering, so the pair must be CX:BX. 391;; That said, in order to take advantage of possible lower-subreg opts, 392;; treat all of the integral operands in the same way. 393 394;; Operands 5 and 6 really need to be different registers, which in 395;; this case means op5 must not be ecx. If op5 and op6 are the same 396;; (like when the input is -1LL) GCC might chose to allocate op5 to ecx, 397;; like op6. This breaks, as the xchg will move the PIC register 398;; contents to %ecx then --> boom. 399 400(define_mode_attr doublemodesuffix [(SI "8") (DI "16")]) 401(define_mode_attr regprefix [(SI "e") (DI "r")]) 402 403(define_insn "atomic_compare_and_swap<dwi>_doubleword" 404 [(set (match_operand:DWIH 0 "register_operand" "=a,a") 405 (unspec_volatile:DWIH 406 [(match_operand:<DWI> 2 "cmpxchg8b_pic_memory_operand" "+m,m") 407 (match_operand:DWIH 3 "register_operand" "0,0") 408 (match_operand:DWIH 4 "register_operand" "1,1") 409 (match_operand:DWIH 5 "register_operand" "b,!*r") 410 (match_operand:DWIH 6 "register_operand" "c,c")] 411 UNSPECV_CMPXCHG)) 412 (set (match_operand:DWIH 1 "register_operand" "=d,d") 413 (unspec_volatile:DWIH [(const_int 0)] UNSPECV_CMPXCHG)) 414 (set (match_dup 2) 415 (unspec_volatile:<DWI> [(const_int 0)] UNSPECV_CMPXCHG)) 416 (set (reg:CCZ FLAGS_REG) 417 (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG)) 418 (clobber (match_scratch:DWIH 7 "=X,&5"))] 419 "TARGET_CMPXCHG<doublemodesuffix>B" 420{ 421 bool swap = REGNO (operands[5]) != BX_REG; 422 423 if (swap) 424 output_asm_insn ("xchg{<imodesuffix>}\t%%<regprefix>bx, %5", operands); 425 426 output_asm_insn ("lock{%;} cmpxchg<doublemodesuffix>b\t%2", operands); 427 428 if (swap) 429 output_asm_insn ("xchg{<imodesuffix>}\t%%<regprefix>bx, %5", operands); 430 431 return ""; 432}) 433 434;; For operand 2 nonmemory_operand predicate is used instead of 435;; register_operand to allow combiner to better optimize atomic 436;; additions of constants. 437(define_insn "atomic_fetch_add<mode>" 438 [(set (match_operand:SWI 0 "register_operand" "=<r>") 439 (unspec_volatile:SWI 440 [(match_operand:SWI 1 "memory_operand" "+m") 441 (match_operand:SI 3 "const_int_operand" "")] ;; model 442 UNSPECV_XCHG)) 443 (set (match_dup 1) 444 (plus:SWI (match_dup 1) 445 (match_operand:SWI 2 "nonmemory_operand" "0"))) 446 (clobber (reg:CC FLAGS_REG))] 447 "TARGET_XADD" 448 "lock{%;} xadd{<imodesuffix>}\t{%0, %1|%1, %0}") 449 450;; This peephole2 and following insn optimize 451;; __sync_fetch_and_add (x, -N) == N into just lock {add,sub,inc,dec} 452;; followed by testing of flags instead of lock xadd and comparisons. 453(define_peephole2 454 [(set (match_operand:SWI 0 "register_operand" "") 455 (match_operand:SWI 2 "const_int_operand" "")) 456 (parallel [(set (match_dup 0) 457 (unspec_volatile:SWI 458 [(match_operand:SWI 1 "memory_operand" "") 459 (match_operand:SI 4 "const_int_operand" "")] 460 UNSPECV_XCHG)) 461 (set (match_dup 1) 462 (plus:SWI (match_dup 1) 463 (match_dup 0))) 464 (clobber (reg:CC FLAGS_REG))]) 465 (set (reg:CCZ FLAGS_REG) 466 (compare:CCZ (match_dup 0) 467 (match_operand:SWI 3 "const_int_operand" "")))] 468 "peep2_reg_dead_p (3, operands[0]) 469 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) 470 == -(unsigned HOST_WIDE_INT) INTVAL (operands[3]) 471 && !reg_overlap_mentioned_p (operands[0], operands[1])" 472 [(parallel [(set (reg:CCZ FLAGS_REG) 473 (compare:CCZ 474 (unspec_volatile:SWI [(match_dup 1) (match_dup 4)] 475 UNSPECV_XCHG) 476 (match_dup 3))) 477 (set (match_dup 1) 478 (plus:SWI (match_dup 1) 479 (match_dup 2)))])]) 480 481(define_insn "*atomic_fetch_add_cmp<mode>" 482 [(set (reg:CCZ FLAGS_REG) 483 (compare:CCZ (unspec_volatile:SWI 484 [(match_operand:SWI 0 "memory_operand" "+m") 485 (match_operand:SI 3 "const_int_operand" "")] 486 UNSPECV_XCHG) 487 (match_operand:SWI 2 "const_int_operand" "i"))) 488 (set (match_dup 0) 489 (plus:SWI (match_dup 0) 490 (match_operand:SWI 1 "const_int_operand" "i")))] 491 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) 492 == -(unsigned HOST_WIDE_INT) INTVAL (operands[2])" 493{ 494 if (TARGET_USE_INCDEC) 495 { 496 if (operands[1] == const1_rtx) 497 return "lock{%;} inc{<imodesuffix>}\t%0"; 498 if (operands[1] == constm1_rtx) 499 return "lock{%;} dec{<imodesuffix>}\t%0"; 500 } 501 502 if (x86_maybe_negate_const_int (&operands[1], <MODE>mode)) 503 return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}"; 504 505 return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}"; 506}) 507 508;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space. 509;; In addition, it is always a full barrier, so we can ignore the memory model. 510(define_insn "atomic_exchange<mode>" 511 [(set (match_operand:SWI 0 "register_operand" "=<r>") ;; output 512 (unspec_volatile:SWI 513 [(match_operand:SWI 1 "memory_operand" "+m") ;; memory 514 (match_operand:SI 3 "const_int_operand" "")] ;; model 515 UNSPECV_XCHG)) 516 (set (match_dup 1) 517 (match_operand:SWI 2 "register_operand" "0"))] ;; input 518 "" 519 "xchg{<imodesuffix>}\t{%1, %0|%0, %1}") 520 521(define_insn "atomic_add<mode>" 522 [(set (match_operand:SWI 0 "memory_operand" "+m") 523 (unspec_volatile:SWI 524 [(plus:SWI (match_dup 0) 525 (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) 526 (match_operand:SI 2 "const_int_operand" "")] ;; model 527 UNSPECV_LOCK)) 528 (clobber (reg:CC FLAGS_REG))] 529 "" 530{ 531 if (TARGET_USE_INCDEC) 532 { 533 if (operands[1] == const1_rtx) 534 return "lock{%;} inc{<imodesuffix>}\t%0"; 535 if (operands[1] == constm1_rtx) 536 return "lock{%;} dec{<imodesuffix>}\t%0"; 537 } 538 539 if (x86_maybe_negate_const_int (&operands[1], <MODE>mode)) 540 return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}"; 541 542 return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}"; 543}) 544 545(define_insn "atomic_sub<mode>" 546 [(set (match_operand:SWI 0 "memory_operand" "+m") 547 (unspec_volatile:SWI 548 [(minus:SWI (match_dup 0) 549 (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) 550 (match_operand:SI 2 "const_int_operand" "")] ;; model 551 UNSPECV_LOCK)) 552 (clobber (reg:CC FLAGS_REG))] 553 "" 554{ 555 if (TARGET_USE_INCDEC) 556 { 557 if (operands[1] == const1_rtx) 558 return "lock{%;} dec{<imodesuffix>}\t%0"; 559 if (operands[1] == constm1_rtx) 560 return "lock{%;} inc{<imodesuffix>}\t%0"; 561 } 562 563 if (x86_maybe_negate_const_int (&operands[1], <MODE>mode)) 564 return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}"; 565 566 return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}"; 567}) 568 569(define_insn "atomic_<logic><mode>" 570 [(set (match_operand:SWI 0 "memory_operand" "+m") 571 (unspec_volatile:SWI 572 [(any_logic:SWI (match_dup 0) 573 (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) 574 (match_operand:SI 2 "const_int_operand" "")] ;; model 575 UNSPECV_LOCK)) 576 (clobber (reg:CC FLAGS_REG))] 577 "" 578 "lock{%;} <logic>{<imodesuffix>}\t{%1, %0|%0, %1}") 579