1;; GCC machine description for i386 synchronization instructions. 2;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011 3;; Free Software Foundation, Inc. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_c_enum "unspec" [ 22 UNSPEC_LFENCE 23 UNSPEC_SFENCE 24 UNSPEC_MFENCE 25 UNSPEC_MOVA ; For __atomic support 26 UNSPEC_LDA 27 UNSPEC_STA 28]) 29 30(define_c_enum "unspecv" [ 31 UNSPECV_CMPXCHG 32 UNSPECV_XCHG 33 UNSPECV_LOCK 34]) 35 36(define_expand "sse2_lfence" 37 [(set (match_dup 0) 38 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))] 39 "TARGET_SSE2" 40{ 41 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 42 MEM_VOLATILE_P (operands[0]) = 1; 43}) 44 45(define_insn "*sse2_lfence" 46 [(set (match_operand:BLK 0 "" "") 47 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))] 48 "TARGET_SSE2" 49 "lfence" 50 [(set_attr "type" "sse") 51 (set_attr "length_address" "0") 52 (set_attr "atom_sse_attr" "lfence") 53 (set_attr "memory" "unknown")]) 54 55(define_expand "sse_sfence" 56 [(set (match_dup 0) 57 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))] 58 "TARGET_SSE || TARGET_3DNOW_A" 59{ 60 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 61 MEM_VOLATILE_P (operands[0]) = 1; 62}) 63 64(define_insn "*sse_sfence" 65 [(set (match_operand:BLK 0 "" "") 66 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))] 67 "TARGET_SSE || TARGET_3DNOW_A" 68 "sfence" 69 [(set_attr "type" "sse") 70 (set_attr "length_address" "0") 71 (set_attr "atom_sse_attr" "fence") 72 (set_attr "memory" "unknown")]) 73 74(define_expand "sse2_mfence" 75 [(set (match_dup 0) 76 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] 77 "TARGET_SSE2" 78{ 79 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 80 MEM_VOLATILE_P (operands[0]) = 1; 81}) 82 83(define_insn "mfence_sse2" 84 [(set (match_operand:BLK 0 "" "") 85 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] 86 "TARGET_64BIT || TARGET_SSE2" 87 "mfence" 88 [(set_attr "type" "sse") 89 (set_attr "length_address" "0") 90 (set_attr "atom_sse_attr" "fence") 91 (set_attr "memory" "unknown")]) 92 93(define_insn "mfence_nosse" 94 [(set (match_operand:BLK 0 "" "") 95 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE)) 96 (clobber (reg:CC FLAGS_REG))] 97 "!(TARGET_64BIT || TARGET_SSE2)" 98 "lock{%;} or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}" 99 [(set_attr "memory" "unknown")]) 100 101(define_expand "mem_thread_fence" 102 [(match_operand:SI 0 "const_int_operand" "")] ;; model 103 "" 104{ 105 /* Unless this is a SEQ_CST fence, the i386 memory model is strong 106 enough not to require barriers of any kind. */ 107 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST) 108 { 109 rtx (*mfence_insn)(rtx); 110 rtx mem; 111 112 if (TARGET_64BIT || TARGET_SSE2) 113 mfence_insn = gen_mfence_sse2; 114 else 115 mfence_insn = gen_mfence_nosse; 116 117 mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 118 MEM_VOLATILE_P (mem) = 1; 119 120 emit_insn (mfence_insn (mem)); 121 } 122 DONE; 123}) 124 125;; ??? From volume 3 section 8.1.1 Guaranteed Atomic Operations, 126;; Only beginning at Pentium family processors do we get any guarantee of 127;; atomicity in aligned 64-bit quantities. Beginning at P6, we get a 128;; guarantee for 64-bit accesses that do not cross a cacheline boundary. 129;; 130;; Note that the TARGET_CMPXCHG8B test below is a stand-in for "Pentium". 131;; 132;; Importantly, *no* processor makes atomicity guarantees for larger 133;; accesses. In particular, there's no way to perform an atomic TImode 134;; move, despite the apparent applicability of MOVDQA et al. 135 136(define_mode_iterator ATOMIC 137 [QI HI SI 138 (DI "TARGET_64BIT || (TARGET_CMPXCHG8B && (TARGET_80387 || TARGET_SSE))") 139 ]) 140 141(define_expand "atomic_load<mode>" 142 [(set (match_operand:ATOMIC 0 "register_operand" "") 143 (unspec:ATOMIC [(match_operand:ATOMIC 1 "memory_operand" "") 144 (match_operand:SI 2 "const_int_operand" "")] 145 UNSPEC_MOVA))] 146 "" 147{ 148 /* For DImode on 32-bit, we can use the FPU to perform the load. */ 149 if (<MODE>mode == DImode && !TARGET_64BIT) 150 emit_insn (gen_atomic_loaddi_fpu 151 (operands[0], operands[1], 152 assign_386_stack_local (DImode, SLOT_TEMP))); 153 else 154 emit_move_insn (operands[0], operands[1]); 155 DONE; 156}) 157 158(define_insn_and_split "atomic_loaddi_fpu" 159 [(set (match_operand:DI 0 "nonimmediate_operand" "=x,m,?r") 160 (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m,m")] 161 UNSPEC_MOVA)) 162 (clobber (match_operand:DI 2 "memory_operand" "=X,X,m")) 163 (clobber (match_scratch:DF 3 "=X,xf,xf"))] 164 "!TARGET_64BIT && (TARGET_80387 || TARGET_SSE)" 165 "#" 166 "&& reload_completed" 167 [(const_int 0)] 168{ 169 rtx dst = operands[0], src = operands[1]; 170 rtx mem = operands[2], tmp = operands[3]; 171 172 if (SSE_REG_P (dst)) 173 emit_move_insn (dst, src); 174 else 175 { 176 if (MEM_P (dst)) 177 mem = dst; 178 179 if (FP_REG_P (tmp)) 180 { 181 emit_insn (gen_loaddi_via_fpu (tmp, src)); 182 emit_insn (gen_storedi_via_fpu (mem, tmp)); 183 } 184 else 185 { 186 adjust_reg_mode (tmp, DImode); 187 emit_move_insn (tmp, src); 188 emit_move_insn (mem, tmp); 189 } 190 191 if (mem != dst) 192 emit_move_insn (dst, mem); 193 } 194 DONE; 195}) 196 197(define_expand "atomic_store<mode>" 198 [(set (match_operand:ATOMIC 0 "memory_operand" "") 199 (unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand" "") 200 (match_operand:SI 2 "const_int_operand" "")] 201 UNSPEC_MOVA))] 202 "" 203{ 204 enum memmodel model = (enum memmodel) INTVAL (operands[2]); 205 206 if (<MODE>mode == DImode && !TARGET_64BIT) 207 { 208 /* For DImode on 32-bit, we can use the FPU to perform the store. */ 209 /* Note that while we could perform a cmpxchg8b loop, that turns 210 out to be significantly larger than this plus a barrier. */ 211 emit_insn (gen_atomic_storedi_fpu 212 (operands[0], operands[1], 213 assign_386_stack_local (DImode, SLOT_TEMP))); 214 } 215 else 216 { 217 /* For seq-cst stores, when we lack MFENCE, use XCHG. */ 218 if (model == MEMMODEL_SEQ_CST && !(TARGET_64BIT || TARGET_SSE2)) 219 { 220 emit_insn (gen_atomic_exchange<mode> (gen_reg_rtx (<MODE>mode), 221 operands[0], operands[1], 222 operands[2])); 223 DONE; 224 } 225 226 /* Otherwise use a store. */ 227 emit_insn (gen_atomic_store<mode>_1 (operands[0], operands[1], 228 operands[2])); 229 } 230 /* ... followed by an MFENCE, if required. */ 231 if (model == MEMMODEL_SEQ_CST) 232 emit_insn (gen_mem_thread_fence (operands[2])); 233 DONE; 234}) 235 236(define_insn "atomic_store<mode>_1" 237 [(set (match_operand:SWI 0 "memory_operand" "=m") 238 (unspec:SWI [(match_operand:SWI 1 "<nonmemory_operand>" "<r><i>") 239 (match_operand:SI 2 "const_int_operand")] 240 UNSPEC_MOVA))] 241 "" 242 "mov{<imodesuffix>}\t{%1, %0|%0, %1}") 243 244(define_insn_and_split "atomic_storedi_fpu" 245 [(set (match_operand:DI 0 "memory_operand" "=m,m,m") 246 (unspec:DI [(match_operand:DI 1 "register_operand" "x,m,?r")] 247 UNSPEC_MOVA)) 248 (clobber (match_operand:DI 2 "memory_operand" "=X,X,m")) 249 (clobber (match_scratch:DF 3 "=X,xf,xf"))] 250 "!TARGET_64BIT && (TARGET_80387 || TARGET_SSE)" 251 "#" 252 "&& reload_completed" 253 [(const_int 0)] 254{ 255 rtx dst = operands[0], src = operands[1]; 256 rtx mem = operands[2], tmp = operands[3]; 257 258 if (!SSE_REG_P (src)) 259 { 260 if (REG_P (src)) 261 { 262 emit_move_insn (mem, src); 263 src = mem; 264 } 265 266 if (FP_REG_P (tmp)) 267 { 268 emit_insn (gen_loaddi_via_fpu (tmp, src)); 269 emit_insn (gen_storedi_via_fpu (dst, tmp)); 270 DONE; 271 } 272 else 273 { 274 adjust_reg_mode (tmp, DImode); 275 emit_move_insn (tmp, mem); 276 src = tmp; 277 } 278 } 279 emit_move_insn (dst, src); 280 DONE; 281}) 282 283;; ??? You'd think that we'd be able to perform this via FLOAT + FIX_TRUNC 284;; operations. But the fix_trunc patterns want way more setup than we want 285;; to provide. Note that the scratch is DFmode instead of XFmode in order 286;; to make it easy to allocate a scratch in either SSE or FP_REGs above. 287 288(define_insn "loaddi_via_fpu" 289 [(set (match_operand:DF 0 "register_operand" "=f") 290 (unspec:DF [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_LDA))] 291 "TARGET_80387" 292 "fild%Z1\t%1" 293 [(set_attr "type" "fmov") 294 (set_attr "mode" "DF") 295 (set_attr "fp_int_src" "true")]) 296 297(define_insn "storedi_via_fpu" 298 [(set (match_operand:DI 0 "memory_operand" "=m") 299 (unspec:DI [(match_operand:DF 1 "register_operand" "f")] UNSPEC_STA))] 300 "TARGET_80387" 301{ 302 gcc_assert (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != NULL_RTX); 303 304 return "fistp%Z0\t%0"; 305} 306 [(set_attr "type" "fmov") 307 (set_attr "mode" "DI")]) 308 309(define_expand "atomic_compare_and_swap<mode>" 310 [(match_operand:QI 0 "register_operand" "") ;; bool success output 311 (match_operand:SWI124 1 "register_operand" "") ;; oldval output 312 (match_operand:SWI124 2 "memory_operand" "") ;; memory 313 (match_operand:SWI124 3 "register_operand" "") ;; expected input 314 (match_operand:SWI124 4 "register_operand" "") ;; newval input 315 (match_operand:SI 5 "const_int_operand" "") ;; is_weak 316 (match_operand:SI 6 "const_int_operand" "") ;; success model 317 (match_operand:SI 7 "const_int_operand" "")] ;; failure model 318 "TARGET_CMPXCHG" 319{ 320 emit_insn 321 (gen_atomic_compare_and_swap<mode>_1 322 (operands[1], operands[2], operands[3], operands[4])); 323 ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG), 324 const0_rtx); 325 DONE; 326}) 327 328(define_mode_iterator CASMODE 329 [(DI "TARGET_64BIT || TARGET_CMPXCHG8B") 330 (TI "TARGET_64BIT && TARGET_CMPXCHG16B")]) 331(define_mode_attr CASHMODE [(DI "SI") (TI "DI")]) 332 333(define_expand "atomic_compare_and_swap<mode>" 334 [(match_operand:QI 0 "register_operand" "") ;; bool success output 335 (match_operand:CASMODE 1 "register_operand" "") ;; oldval output 336 (match_operand:CASMODE 2 "memory_operand" "") ;; memory 337 (match_operand:CASMODE 3 "register_operand" "") ;; expected input 338 (match_operand:CASMODE 4 "register_operand" "") ;; newval input 339 (match_operand:SI 5 "const_int_operand" "") ;; is_weak 340 (match_operand:SI 6 "const_int_operand" "") ;; success model 341 (match_operand:SI 7 "const_int_operand" "")] ;; failure model 342 "TARGET_CMPXCHG" 343{ 344 if (<MODE>mode == DImode && TARGET_64BIT) 345 { 346 emit_insn 347 (gen_atomic_compare_and_swapdi_1 348 (operands[1], operands[2], operands[3], operands[4])); 349 } 350 else 351 { 352 enum machine_mode hmode = <CASHMODE>mode; 353 rtx lo_o, lo_e, lo_n, hi_o, hi_e, hi_n, mem; 354 355 lo_o = operands[1]; 356 mem = operands[2]; 357 lo_e = operands[3]; 358 lo_n = operands[4]; 359 hi_o = gen_highpart (hmode, lo_o); 360 hi_e = gen_highpart (hmode, lo_e); 361 hi_n = gen_highpart (hmode, lo_n); 362 lo_o = gen_lowpart (hmode, lo_o); 363 lo_e = gen_lowpart (hmode, lo_e); 364 lo_n = gen_lowpart (hmode, lo_n); 365 366 if (!cmpxchg8b_pic_memory_operand (mem, <MODE>mode)) 367 mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0))); 368 369 emit_insn 370 (gen_atomic_compare_and_swap<mode>_doubleword 371 (lo_o, hi_o, mem, lo_e, hi_e, lo_n, hi_n)); 372 } 373 374 ix86_expand_setcc (operands[0], EQ, gen_rtx_REG (CCZmode, FLAGS_REG), 375 const0_rtx); 376 DONE; 377}) 378 379(define_insn "atomic_compare_and_swap<mode>_1" 380 [(set (match_operand:SWI 0 "register_operand" "=a") 381 (unspec_volatile:SWI 382 [(match_operand:SWI 1 "memory_operand" "+m") 383 (match_operand:SWI 2 "register_operand" "0") 384 (match_operand:SWI 3 "register_operand" "<r>")] 385 UNSPECV_CMPXCHG)) 386 (set (match_dup 1) 387 (unspec_volatile:SWI [(const_int 0)] UNSPECV_CMPXCHG)) 388 (set (reg:CCZ FLAGS_REG) 389 (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG))] 390 "TARGET_CMPXCHG" 391 "lock{%;} cmpxchg{<imodesuffix>}\t{%3, %1|%1, %3}") 392 393;; For double-word compare and swap, we are obliged to play tricks with 394;; the input newval (op5:op6) because the Intel register numbering does 395;; not match the gcc register numbering, so the pair must be CX:BX. 396;; That said, in order to take advantage of possible lower-subreg opts, 397;; treat all of the integral operands in the same way. 398 399;; Operands 5 and 6 really need to be different registers, which in 400;; this case means op5 must not be ecx. If op5 and op6 are the same 401;; (like when the input is -1LL) GCC might chose to allocate op5 to ecx, 402;; like op6. This breaks, as the xchg will move the PIC register 403;; contents to %ecx then --> boom. 404 405(define_mode_attr doublemodesuffix [(SI "8") (DI "16")]) 406(define_mode_attr regprefix [(SI "e") (DI "r")]) 407 408(define_insn "atomic_compare_and_swap<dwi>_doubleword" 409 [(set (match_operand:DWIH 0 "register_operand" "=a,a") 410 (unspec_volatile:DWIH 411 [(match_operand:<DWI> 2 "cmpxchg8b_pic_memory_operand" "+m,m") 412 (match_operand:DWIH 3 "register_operand" "0,0") 413 (match_operand:DWIH 4 "register_operand" "1,1") 414 (match_operand:DWIH 5 "register_operand" "b,!*r") 415 (match_operand:DWIH 6 "register_operand" "c,c")] 416 UNSPECV_CMPXCHG)) 417 (set (match_operand:DWIH 1 "register_operand" "=d,d") 418 (unspec_volatile:DWIH [(const_int 0)] UNSPECV_CMPXCHG)) 419 (set (match_dup 2) 420 (unspec_volatile:<DWI> [(const_int 0)] UNSPECV_CMPXCHG)) 421 (set (reg:CCZ FLAGS_REG) 422 (unspec_volatile:CCZ [(const_int 0)] UNSPECV_CMPXCHG)) 423 (clobber (match_scratch:DWIH 7 "=X,&5"))] 424 "TARGET_CMPXCHG<doublemodesuffix>B" 425{ 426 bool swap = REGNO (operands[5]) != BX_REG; 427 428 if (swap) 429 output_asm_insn ("xchg{<imodesuffix>}\t%%<regprefix>bx, %5", operands); 430 431 output_asm_insn ("lock{%;} cmpxchg<doublemodesuffix>b\t%2", operands); 432 433 if (swap) 434 output_asm_insn ("xchg{<imodesuffix>}\t%%<regprefix>bx, %5", operands); 435 436 return ""; 437}) 438 439;; For operand 2 nonmemory_operand predicate is used instead of 440;; register_operand to allow combiner to better optimize atomic 441;; additions of constants. 442(define_insn "atomic_fetch_add<mode>" 443 [(set (match_operand:SWI 0 "register_operand" "=<r>") 444 (unspec_volatile:SWI 445 [(match_operand:SWI 1 "memory_operand" "+m") 446 (match_operand:SI 3 "const_int_operand" "")] ;; model 447 UNSPECV_XCHG)) 448 (set (match_dup 1) 449 (plus:SWI (match_dup 1) 450 (match_operand:SWI 2 "nonmemory_operand" "0"))) 451 (clobber (reg:CC FLAGS_REG))] 452 "TARGET_XADD" 453 "lock{%;} xadd{<imodesuffix>}\t{%0, %1|%1, %0}") 454 455;; This peephole2 and following insn optimize 456;; __sync_fetch_and_add (x, -N) == N into just lock {add,sub,inc,dec} 457;; followed by testing of flags instead of lock xadd and comparisons. 458(define_peephole2 459 [(set (match_operand:SWI 0 "register_operand" "") 460 (match_operand:SWI 2 "const_int_operand" "")) 461 (parallel [(set (match_dup 0) 462 (unspec_volatile:SWI 463 [(match_operand:SWI 1 "memory_operand" "") 464 (match_operand:SI 4 "const_int_operand" "")] 465 UNSPECV_XCHG)) 466 (set (match_dup 1) 467 (plus:SWI (match_dup 1) 468 (match_dup 0))) 469 (clobber (reg:CC FLAGS_REG))]) 470 (set (reg:CCZ FLAGS_REG) 471 (compare:CCZ (match_dup 0) 472 (match_operand:SWI 3 "const_int_operand" "")))] 473 "peep2_reg_dead_p (3, operands[0]) 474 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) 475 == -(unsigned HOST_WIDE_INT) INTVAL (operands[3]) 476 && !reg_overlap_mentioned_p (operands[0], operands[1])" 477 [(parallel [(set (reg:CCZ FLAGS_REG) 478 (compare:CCZ 479 (unspec_volatile:SWI [(match_dup 1) (match_dup 4)] 480 UNSPECV_XCHG) 481 (match_dup 3))) 482 (set (match_dup 1) 483 (plus:SWI (match_dup 1) 484 (match_dup 2)))])]) 485 486(define_insn "*atomic_fetch_add_cmp<mode>" 487 [(set (reg:CCZ FLAGS_REG) 488 (compare:CCZ (unspec_volatile:SWI 489 [(match_operand:SWI 0 "memory_operand" "+m") 490 (match_operand:SI 3 "const_int_operand" "")] 491 UNSPECV_XCHG) 492 (match_operand:SWI 2 "const_int_operand" "i"))) 493 (set (match_dup 0) 494 (plus:SWI (match_dup 0) 495 (match_operand:SWI 1 "const_int_operand" "i")))] 496 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) 497 == -(unsigned HOST_WIDE_INT) INTVAL (operands[2])" 498{ 499 if (TARGET_USE_INCDEC) 500 { 501 if (operands[1] == const1_rtx) 502 return "lock{%;} inc{<imodesuffix>}\t%0"; 503 if (operands[1] == constm1_rtx) 504 return "lock{%;} dec{<imodesuffix>}\t%0"; 505 } 506 507 if (x86_maybe_negate_const_int (&operands[1], <MODE>mode)) 508 return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}"; 509 510 return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}"; 511}) 512 513;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space. 514;; In addition, it is always a full barrier, so we can ignore the memory model. 515(define_insn "atomic_exchange<mode>" 516 [(set (match_operand:SWI 0 "register_operand" "=<r>") ;; output 517 (unspec_volatile:SWI 518 [(match_operand:SWI 1 "memory_operand" "+m") ;; memory 519 (match_operand:SI 3 "const_int_operand" "")] ;; model 520 UNSPECV_XCHG)) 521 (set (match_dup 1) 522 (match_operand:SWI 2 "register_operand" "0"))] ;; input 523 "" 524 "xchg{<imodesuffix>}\t{%1, %0|%0, %1}") 525 526(define_insn "atomic_add<mode>" 527 [(set (match_operand:SWI 0 "memory_operand" "+m") 528 (unspec_volatile:SWI 529 [(plus:SWI (match_dup 0) 530 (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) 531 (match_operand:SI 2 "const_int_operand" "")] ;; model 532 UNSPECV_LOCK)) 533 (clobber (reg:CC FLAGS_REG))] 534 "" 535{ 536 if (TARGET_USE_INCDEC) 537 { 538 if (operands[1] == const1_rtx) 539 return "lock{%;} inc{<imodesuffix>}\t%0"; 540 if (operands[1] == constm1_rtx) 541 return "lock{%;} dec{<imodesuffix>}\t%0"; 542 } 543 544 if (x86_maybe_negate_const_int (&operands[1], <MODE>mode)) 545 return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}"; 546 547 return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}"; 548}) 549 550(define_insn "atomic_sub<mode>" 551 [(set (match_operand:SWI 0 "memory_operand" "+m") 552 (unspec_volatile:SWI 553 [(minus:SWI (match_dup 0) 554 (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) 555 (match_operand:SI 2 "const_int_operand" "")] ;; model 556 UNSPECV_LOCK)) 557 (clobber (reg:CC FLAGS_REG))] 558 "" 559{ 560 if (TARGET_USE_INCDEC) 561 { 562 if (operands[1] == const1_rtx) 563 return "lock{%;} dec{<imodesuffix>}\t%0"; 564 if (operands[1] == constm1_rtx) 565 return "lock{%;} inc{<imodesuffix>}\t%0"; 566 } 567 568 if (x86_maybe_negate_const_int (&operands[1], <MODE>mode)) 569 return "lock{%;} add{<imodesuffix>}\t{%1, %0|%0, %1}"; 570 571 return "lock{%;} sub{<imodesuffix>}\t{%1, %0|%0, %1}"; 572}) 573 574(define_insn "atomic_<logic><mode>" 575 [(set (match_operand:SWI 0 "memory_operand" "+m") 576 (unspec_volatile:SWI 577 [(any_logic:SWI (match_dup 0) 578 (match_operand:SWI 1 "nonmemory_operand" "<r><i>")) 579 (match_operand:SI 2 "const_int_operand" "")] ;; model 580 UNSPECV_LOCK)) 581 (clobber (reg:CC FLAGS_REG))] 582 "" 583 "lock{%;} <logic>{<imodesuffix>}\t{%1, %0|%0, %1}") 584