1@c Copyright (C) 2006 Free Software Foundation, Inc.
2@c This is part of the GCC manual.
3@c For copying conditions, see the file gcc.texi.
4
5@c This file is generated automatically using gcc/config/arm/neon-docgen.ml
6@c Please do not edit manually.
7@subsubsection Addition
8
9@itemize @bullet
10@item uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t)
11@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
12@end itemize
13
14
15@itemize @bullet
16@item uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t)
17@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
18@end itemize
19
20
21@itemize @bullet
22@item uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t)
23@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
24@end itemize
25
26
27@itemize @bullet
28@item int32x2_t vadd_s32 (int32x2_t, int32x2_t)
29@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
30@end itemize
31
32
33@itemize @bullet
34@item int16x4_t vadd_s16 (int16x4_t, int16x4_t)
35@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
36@end itemize
37
38
39@itemize @bullet
40@item int8x8_t vadd_s8 (int8x8_t, int8x8_t)
41@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
42@end itemize
43
44
45@itemize @bullet
46@item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
47@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
48@end itemize
49
50
51@itemize @bullet
52@item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
53@end itemize
54
55
56@itemize @bullet
57@item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
58@end itemize
59
60
61@itemize @bullet
62@item uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t)
63@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
64@end itemize
65
66
67@itemize @bullet
68@item uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t)
69@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
70@end itemize
71
72
73@itemize @bullet
74@item uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t)
75@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
76@end itemize
77
78
79@itemize @bullet
80@item int32x4_t vaddq_s32 (int32x4_t, int32x4_t)
81@*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
82@end itemize
83
84
85@itemize @bullet
86@item int16x8_t vaddq_s16 (int16x8_t, int16x8_t)
87@*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
88@end itemize
89
90
91@itemize @bullet
92@item int8x16_t vaddq_s8 (int8x16_t, int8x16_t)
93@*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
94@end itemize
95
96
97@itemize @bullet
98@item uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t)
99@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
100@end itemize
101
102
103@itemize @bullet
104@item int64x2_t vaddq_s64 (int64x2_t, int64x2_t)
105@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
106@end itemize
107
108
109@itemize @bullet
110@item float32x4_t vaddq_f32 (float32x4_t, float32x4_t)
111@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{q0}, @var{q0}, @var{q0}}
112@end itemize
113
114
115@itemize @bullet
116@item uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t)
117@*@emph{Form of expected instruction(s):} @code{vaddl.u32 @var{q0}, @var{d0}, @var{d0}}
118@end itemize
119
120
121@itemize @bullet
122@item uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t)
123@*@emph{Form of expected instruction(s):} @code{vaddl.u16 @var{q0}, @var{d0}, @var{d0}}
124@end itemize
125
126
127@itemize @bullet
128@item uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t)
129@*@emph{Form of expected instruction(s):} @code{vaddl.u8 @var{q0}, @var{d0}, @var{d0}}
130@end itemize
131
132
133@itemize @bullet
134@item int64x2_t vaddl_s32 (int32x2_t, int32x2_t)
135@*@emph{Form of expected instruction(s):} @code{vaddl.s32 @var{q0}, @var{d0}, @var{d0}}
136@end itemize
137
138
139@itemize @bullet
140@item int32x4_t vaddl_s16 (int16x4_t, int16x4_t)
141@*@emph{Form of expected instruction(s):} @code{vaddl.s16 @var{q0}, @var{d0}, @var{d0}}
142@end itemize
143
144
145@itemize @bullet
146@item int16x8_t vaddl_s8 (int8x8_t, int8x8_t)
147@*@emph{Form of expected instruction(s):} @code{vaddl.s8 @var{q0}, @var{d0}, @var{d0}}
148@end itemize
149
150
151@itemize @bullet
152@item uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t)
153@*@emph{Form of expected instruction(s):} @code{vaddw.u32 @var{q0}, @var{q0}, @var{d0}}
154@end itemize
155
156
157@itemize @bullet
158@item uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t)
159@*@emph{Form of expected instruction(s):} @code{vaddw.u16 @var{q0}, @var{q0}, @var{d0}}
160@end itemize
161
162
163@itemize @bullet
164@item uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t)
165@*@emph{Form of expected instruction(s):} @code{vaddw.u8 @var{q0}, @var{q0}, @var{d0}}
166@end itemize
167
168
169@itemize @bullet
170@item int64x2_t vaddw_s32 (int64x2_t, int32x2_t)
171@*@emph{Form of expected instruction(s):} @code{vaddw.s32 @var{q0}, @var{q0}, @var{d0}}
172@end itemize
173
174
175@itemize @bullet
176@item int32x4_t vaddw_s16 (int32x4_t, int16x4_t)
177@*@emph{Form of expected instruction(s):} @code{vaddw.s16 @var{q0}, @var{q0}, @var{d0}}
178@end itemize
179
180
181@itemize @bullet
182@item int16x8_t vaddw_s8 (int16x8_t, int8x8_t)
183@*@emph{Form of expected instruction(s):} @code{vaddw.s8 @var{q0}, @var{q0}, @var{d0}}
184@end itemize
185
186
187@itemize @bullet
188@item uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t)
189@*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{d0}, @var{d0}, @var{d0}}
190@end itemize
191
192
193@itemize @bullet
194@item uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t)
195@*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{d0}, @var{d0}, @var{d0}}
196@end itemize
197
198
199@itemize @bullet
200@item uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t)
201@*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{d0}, @var{d0}, @var{d0}}
202@end itemize
203
204
205@itemize @bullet
206@item int32x2_t vhadd_s32 (int32x2_t, int32x2_t)
207@*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{d0}, @var{d0}, @var{d0}}
208@end itemize
209
210
211@itemize @bullet
212@item int16x4_t vhadd_s16 (int16x4_t, int16x4_t)
213@*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{d0}, @var{d0}, @var{d0}}
214@end itemize
215
216
217@itemize @bullet
218@item int8x8_t vhadd_s8 (int8x8_t, int8x8_t)
219@*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{d0}, @var{d0}, @var{d0}}
220@end itemize
221
222
223@itemize @bullet
224@item uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t)
225@*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{q0}, @var{q0}, @var{q0}}
226@end itemize
227
228
229@itemize @bullet
230@item uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t)
231@*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{q0}, @var{q0}, @var{q0}}
232@end itemize
233
234
235@itemize @bullet
236@item uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t)
237@*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{q0}, @var{q0}, @var{q0}}
238@end itemize
239
240
241@itemize @bullet
242@item int32x4_t vhaddq_s32 (int32x4_t, int32x4_t)
243@*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{q0}, @var{q0}, @var{q0}}
244@end itemize
245
246
247@itemize @bullet
248@item int16x8_t vhaddq_s16 (int16x8_t, int16x8_t)
249@*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{q0}, @var{q0}, @var{q0}}
250@end itemize
251
252
253@itemize @bullet
254@item int8x16_t vhaddq_s8 (int8x16_t, int8x16_t)
255@*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{q0}, @var{q0}, @var{q0}}
256@end itemize
257
258
259@itemize @bullet
260@item uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t)
261@*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{d0}, @var{d0}, @var{d0}}
262@end itemize
263
264
265@itemize @bullet
266@item uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t)
267@*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{d0}, @var{d0}, @var{d0}}
268@end itemize
269
270
271@itemize @bullet
272@item uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t)
273@*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{d0}, @var{d0}, @var{d0}}
274@end itemize
275
276
277@itemize @bullet
278@item int32x2_t vrhadd_s32 (int32x2_t, int32x2_t)
279@*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{d0}, @var{d0}, @var{d0}}
280@end itemize
281
282
283@itemize @bullet
284@item int16x4_t vrhadd_s16 (int16x4_t, int16x4_t)
285@*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{d0}, @var{d0}, @var{d0}}
286@end itemize
287
288
289@itemize @bullet
290@item int8x8_t vrhadd_s8 (int8x8_t, int8x8_t)
291@*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{d0}, @var{d0}, @var{d0}}
292@end itemize
293
294
295@itemize @bullet
296@item uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t)
297@*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{q0}, @var{q0}, @var{q0}}
298@end itemize
299
300
301@itemize @bullet
302@item uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t)
303@*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{q0}, @var{q0}, @var{q0}}
304@end itemize
305
306
307@itemize @bullet
308@item uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t)
309@*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{q0}, @var{q0}, @var{q0}}
310@end itemize
311
312
313@itemize @bullet
314@item int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t)
315@*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{q0}, @var{q0}, @var{q0}}
316@end itemize
317
318
319@itemize @bullet
320@item int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t)
321@*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{q0}, @var{q0}, @var{q0}}
322@end itemize
323
324
325@itemize @bullet
326@item int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t)
327@*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{q0}, @var{q0}, @var{q0}}
328@end itemize
329
330
331@itemize @bullet
332@item uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t)
333@*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{d0}, @var{d0}, @var{d0}}
334@end itemize
335
336
337@itemize @bullet
338@item uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t)
339@*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{d0}, @var{d0}, @var{d0}}
340@end itemize
341
342
343@itemize @bullet
344@item uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t)
345@*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{d0}, @var{d0}, @var{d0}}
346@end itemize
347
348
349@itemize @bullet
350@item int32x2_t vqadd_s32 (int32x2_t, int32x2_t)
351@*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{d0}, @var{d0}, @var{d0}}
352@end itemize
353
354
355@itemize @bullet
356@item int16x4_t vqadd_s16 (int16x4_t, int16x4_t)
357@*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{d0}, @var{d0}, @var{d0}}
358@end itemize
359
360
361@itemize @bullet
362@item int8x8_t vqadd_s8 (int8x8_t, int8x8_t)
363@*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{d0}, @var{d0}, @var{d0}}
364@end itemize
365
366
367@itemize @bullet
368@item uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t)
369@*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{d0}, @var{d0}, @var{d0}}
370@end itemize
371
372
373@itemize @bullet
374@item int64x1_t vqadd_s64 (int64x1_t, int64x1_t)
375@*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{d0}, @var{d0}, @var{d0}}
376@end itemize
377
378
379@itemize @bullet
380@item uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t)
381@*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{q0}, @var{q0}, @var{q0}}
382@end itemize
383
384
385@itemize @bullet
386@item uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t)
387@*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{q0}, @var{q0}, @var{q0}}
388@end itemize
389
390
391@itemize @bullet
392@item uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t)
393@*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{q0}, @var{q0}, @var{q0}}
394@end itemize
395
396
397@itemize @bullet
398@item int32x4_t vqaddq_s32 (int32x4_t, int32x4_t)
399@*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{q0}, @var{q0}, @var{q0}}
400@end itemize
401
402
403@itemize @bullet
404@item int16x8_t vqaddq_s16 (int16x8_t, int16x8_t)
405@*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{q0}, @var{q0}, @var{q0}}
406@end itemize
407
408
409@itemize @bullet
410@item int8x16_t vqaddq_s8 (int8x16_t, int8x16_t)
411@*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{q0}, @var{q0}, @var{q0}}
412@end itemize
413
414
415@itemize @bullet
416@item uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t)
417@*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{q0}, @var{q0}, @var{q0}}
418@end itemize
419
420
421@itemize @bullet
422@item int64x2_t vqaddq_s64 (int64x2_t, int64x2_t)
423@*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{q0}, @var{q0}, @var{q0}}
424@end itemize
425
426
427@itemize @bullet
428@item uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t)
429@*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
430@end itemize
431
432
433@itemize @bullet
434@item uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t)
435@*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
436@end itemize
437
438
439@itemize @bullet
440@item uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t)
441@*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
442@end itemize
443
444
445@itemize @bullet
446@item int32x2_t vaddhn_s64 (int64x2_t, int64x2_t)
447@*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
448@end itemize
449
450
451@itemize @bullet
452@item int16x4_t vaddhn_s32 (int32x4_t, int32x4_t)
453@*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
454@end itemize
455
456
457@itemize @bullet
458@item int8x8_t vaddhn_s16 (int16x8_t, int16x8_t)
459@*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
460@end itemize
461
462
463@itemize @bullet
464@item uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t)
465@*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
466@end itemize
467
468
469@itemize @bullet
470@item uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t)
471@*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
472@end itemize
473
474
475@itemize @bullet
476@item uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t)
477@*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
478@end itemize
479
480
481@itemize @bullet
482@item int32x2_t vraddhn_s64 (int64x2_t, int64x2_t)
483@*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
484@end itemize
485
486
487@itemize @bullet
488@item int16x4_t vraddhn_s32 (int32x4_t, int32x4_t)
489@*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
490@end itemize
491
492
493@itemize @bullet
494@item int8x8_t vraddhn_s16 (int16x8_t, int16x8_t)
495@*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
496@end itemize
497
498
499
500
501@subsubsection Multiplication
502
503@itemize @bullet
504@item uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t)
505@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
506@end itemize
507
508
509@itemize @bullet
510@item uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t)
511@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
512@end itemize
513
514
515@itemize @bullet
516@item uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t)
517@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
518@end itemize
519
520
521@itemize @bullet
522@item int32x2_t vmul_s32 (int32x2_t, int32x2_t)
523@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
524@end itemize
525
526
527@itemize @bullet
528@item int16x4_t vmul_s16 (int16x4_t, int16x4_t)
529@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
530@end itemize
531
532
533@itemize @bullet
534@item int8x8_t vmul_s8 (int8x8_t, int8x8_t)
535@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
536@end itemize
537
538
539@itemize @bullet
540@item float32x2_t vmul_f32 (float32x2_t, float32x2_t)
541@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}}
542@end itemize
543
544
545@itemize @bullet
546@item poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t)
547@*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{d0}, @var{d0}, @var{d0}}
548@end itemize
549
550
551@itemize @bullet
552@item uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t)
553@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
554@end itemize
555
556
557@itemize @bullet
558@item uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t)
559@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
560@end itemize
561
562
563@itemize @bullet
564@item uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t)
565@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
566@end itemize
567
568
569@itemize @bullet
570@item int32x4_t vmulq_s32 (int32x4_t, int32x4_t)
571@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
572@end itemize
573
574
575@itemize @bullet
576@item int16x8_t vmulq_s16 (int16x8_t, int16x8_t)
577@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
578@end itemize
579
580
581@itemize @bullet
582@item int8x16_t vmulq_s8 (int8x16_t, int8x16_t)
583@*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
584@end itemize
585
586
587@itemize @bullet
588@item float32x4_t vmulq_f32 (float32x4_t, float32x4_t)
589@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{q0}}
590@end itemize
591
592
593@itemize @bullet
594@item poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t)
595@*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{q0}, @var{q0}, @var{q0}}
596@end itemize
597
598
599@itemize @bullet
600@item int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t)
601@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
602@end itemize
603
604
605@itemize @bullet
606@item int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t)
607@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
608@end itemize
609
610
611@itemize @bullet
612@item int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t)
613@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
614@end itemize
615
616
617@itemize @bullet
618@item int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t)
619@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
620@end itemize
621
622
623@itemize @bullet
624@item int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t)
625@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
626@end itemize
627
628
629@itemize @bullet
630@item int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t)
631@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
632@end itemize
633
634
635@itemize @bullet
636@item int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t)
637@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
638@end itemize
639
640
641@itemize @bullet
642@item int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t)
643@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
644@end itemize
645
646
647@itemize @bullet
648@item uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t)
649@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}}
650@end itemize
651
652
653@itemize @bullet
654@item uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t)
655@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}}
656@end itemize
657
658
659@itemize @bullet
660@item uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t)
661@*@emph{Form of expected instruction(s):} @code{vmull.u8 @var{q0}, @var{d0}, @var{d0}}
662@end itemize
663
664
665@itemize @bullet
666@item int64x2_t vmull_s32 (int32x2_t, int32x2_t)
667@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}}
668@end itemize
669
670
671@itemize @bullet
672@item int32x4_t vmull_s16 (int16x4_t, int16x4_t)
673@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}}
674@end itemize
675
676
677@itemize @bullet
678@item int16x8_t vmull_s8 (int8x8_t, int8x8_t)
679@*@emph{Form of expected instruction(s):} @code{vmull.s8 @var{q0}, @var{d0}, @var{d0}}
680@end itemize
681
682
683@itemize @bullet
684@item poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t)
685@*@emph{Form of expected instruction(s):} @code{vmull.p8 @var{q0}, @var{d0}, @var{d0}}
686@end itemize
687
688
689@itemize @bullet
690@item int64x2_t vqdmull_s32 (int32x2_t, int32x2_t)
691@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}}
692@end itemize
693
694
695@itemize @bullet
696@item int32x4_t vqdmull_s16 (int16x4_t, int16x4_t)
697@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}}
698@end itemize
699
700
701
702
703@subsubsection Multiply-accumulate
704
705@itemize @bullet
706@item uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
707@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
708@end itemize
709
710
711@itemize @bullet
712@item uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
713@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
714@end itemize
715
716
717@itemize @bullet
718@item uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
719@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
720@end itemize
721
722
723@itemize @bullet
724@item int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t)
725@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
726@end itemize
727
728
729@itemize @bullet
730@item int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t)
731@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
732@end itemize
733
734
735@itemize @bullet
736@item int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t)
737@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
738@end itemize
739
740
741@itemize @bullet
742@item float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t)
743@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}}
744@end itemize
745
746
747@itemize @bullet
748@item uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
749@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
750@end itemize
751
752
753@itemize @bullet
754@item uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
755@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
756@end itemize
757
758
759@itemize @bullet
760@item uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
761@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
762@end itemize
763
764
765@itemize @bullet
766@item int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t)
767@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
768@end itemize
769
770
771@itemize @bullet
772@item int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t)
773@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
774@end itemize
775
776
777@itemize @bullet
778@item int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t)
779@*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
780@end itemize
781
782
783@itemize @bullet
784@item float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t)
785@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{q0}}
786@end itemize
787
788
789@itemize @bullet
790@item uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
791@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}}
792@end itemize
793
794
795@itemize @bullet
796@item uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
797@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}}
798@end itemize
799
800
801@itemize @bullet
802@item uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
803@*@emph{Form of expected instruction(s):} @code{vmlal.u8 @var{q0}, @var{d0}, @var{d0}}
804@end itemize
805
806
807@itemize @bullet
808@item int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
809@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}}
810@end itemize
811
812
813@itemize @bullet
814@item int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
815@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}}
816@end itemize
817
818
819@itemize @bullet
820@item int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t)
821@*@emph{Form of expected instruction(s):} @code{vmlal.s8 @var{q0}, @var{d0}, @var{d0}}
822@end itemize
823
824
825@itemize @bullet
826@item int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
827@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}}
828@end itemize
829
830
831@itemize @bullet
832@item int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
833@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}}
834@end itemize
835
836
837
838
839@subsubsection Multiply-subtract
840
841@itemize @bullet
842@item uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
843@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
844@end itemize
845
846
847@itemize @bullet
848@item uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
849@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
850@end itemize
851
852
853@itemize @bullet
854@item uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
855@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
856@end itemize
857
858
859@itemize @bullet
860@item int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t)
861@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
862@end itemize
863
864
865@itemize @bullet
866@item int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t)
867@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
868@end itemize
869
870
871@itemize @bullet
872@item int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t)
873@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
874@end itemize
875
876
877@itemize @bullet
878@item float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t)
879@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}}
880@end itemize
881
882
883@itemize @bullet
884@item uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
885@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
886@end itemize
887
888
889@itemize @bullet
890@item uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
891@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
892@end itemize
893
894
895@itemize @bullet
896@item uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
897@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
898@end itemize
899
900
901@itemize @bullet
902@item int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t)
903@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
904@end itemize
905
906
907@itemize @bullet
908@item int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t)
909@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
910@end itemize
911
912
913@itemize @bullet
914@item int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t)
915@*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
916@end itemize
917
918
919@itemize @bullet
920@item float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t)
921@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{q0}}
922@end itemize
923
924
925@itemize @bullet
926@item uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
927@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}}
928@end itemize
929
930
931@itemize @bullet
932@item uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
933@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}}
934@end itemize
935
936
937@itemize @bullet
938@item uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
939@*@emph{Form of expected instruction(s):} @code{vmlsl.u8 @var{q0}, @var{d0}, @var{d0}}
940@end itemize
941
942
943@itemize @bullet
944@item int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
945@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
946@end itemize
947
948
949@itemize @bullet
950@item int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
951@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
952@end itemize
953
954
955@itemize @bullet
956@item int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t)
957@*@emph{Form of expected instruction(s):} @code{vmlsl.s8 @var{q0}, @var{d0}, @var{d0}}
958@end itemize
959
960
961@itemize @bullet
962@item int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
963@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
964@end itemize
965
966
967@itemize @bullet
968@item int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
969@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
970@end itemize
971
972
973
974
975@subsubsection Subtraction
976
977@itemize @bullet
978@item uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t)
979@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
980@end itemize
981
982
983@itemize @bullet
984@item uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t)
985@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
986@end itemize
987
988
989@itemize @bullet
990@item uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t)
991@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
992@end itemize
993
994
995@itemize @bullet
996@item int32x2_t vsub_s32 (int32x2_t, int32x2_t)
997@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
998@end itemize
999
1000
1001@itemize @bullet
1002@item int16x4_t vsub_s16 (int16x4_t, int16x4_t)
1003@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
1004@end itemize
1005
1006
1007@itemize @bullet
1008@item int8x8_t vsub_s8 (int8x8_t, int8x8_t)
1009@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
1010@end itemize
1011
1012
1013@itemize @bullet
1014@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
1015@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
1016@end itemize
1017
1018
1019@itemize @bullet
1020@item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
1021@end itemize
1022
1023
1024@itemize @bullet
1025@item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
1026@end itemize
1027
1028
1029@itemize @bullet
1030@item uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t)
1031@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1032@end itemize
1033
1034
1035@itemize @bullet
1036@item uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t)
1037@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1038@end itemize
1039
1040
1041@itemize @bullet
1042@item uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t)
1043@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1044@end itemize
1045
1046
1047@itemize @bullet
1048@item int32x4_t vsubq_s32 (int32x4_t, int32x4_t)
1049@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1050@end itemize
1051
1052
1053@itemize @bullet
1054@item int16x8_t vsubq_s16 (int16x8_t, int16x8_t)
1055@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1056@end itemize
1057
1058
1059@itemize @bullet
1060@item int8x16_t vsubq_s8 (int8x16_t, int8x16_t)
1061@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1062@end itemize
1063
1064
1065@itemize @bullet
1066@item uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t)
1067@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1068@end itemize
1069
1070
1071@itemize @bullet
1072@item int64x2_t vsubq_s64 (int64x2_t, int64x2_t)
1073@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1074@end itemize
1075
1076
1077@itemize @bullet
1078@item float32x4_t vsubq_f32 (float32x4_t, float32x4_t)
1079@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{q0}, @var{q0}, @var{q0}}
1080@end itemize
1081
1082
1083@itemize @bullet
1084@item uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t)
1085@*@emph{Form of expected instruction(s):} @code{vsubl.u32 @var{q0}, @var{d0}, @var{d0}}
1086@end itemize
1087
1088
1089@itemize @bullet
1090@item uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t)
1091@*@emph{Form of expected instruction(s):} @code{vsubl.u16 @var{q0}, @var{d0}, @var{d0}}
1092@end itemize
1093
1094
1095@itemize @bullet
1096@item uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t)
1097@*@emph{Form of expected instruction(s):} @code{vsubl.u8 @var{q0}, @var{d0}, @var{d0}}
1098@end itemize
1099
1100
1101@itemize @bullet
1102@item int64x2_t vsubl_s32 (int32x2_t, int32x2_t)
1103@*@emph{Form of expected instruction(s):} @code{vsubl.s32 @var{q0}, @var{d0}, @var{d0}}
1104@end itemize
1105
1106
1107@itemize @bullet
1108@item int32x4_t vsubl_s16 (int16x4_t, int16x4_t)
1109@*@emph{Form of expected instruction(s):} @code{vsubl.s16 @var{q0}, @var{d0}, @var{d0}}
1110@end itemize
1111
1112
1113@itemize @bullet
1114@item int16x8_t vsubl_s8 (int8x8_t, int8x8_t)
1115@*@emph{Form of expected instruction(s):} @code{vsubl.s8 @var{q0}, @var{d0}, @var{d0}}
1116@end itemize
1117
1118
1119@itemize @bullet
1120@item uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t)
1121@*@emph{Form of expected instruction(s):} @code{vsubw.u32 @var{q0}, @var{q0}, @var{d0}}
1122@end itemize
1123
1124
1125@itemize @bullet
1126@item uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t)
1127@*@emph{Form of expected instruction(s):} @code{vsubw.u16 @var{q0}, @var{q0}, @var{d0}}
1128@end itemize
1129
1130
1131@itemize @bullet
1132@item uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t)
1133@*@emph{Form of expected instruction(s):} @code{vsubw.u8 @var{q0}, @var{q0}, @var{d0}}
1134@end itemize
1135
1136
1137@itemize @bullet
1138@item int64x2_t vsubw_s32 (int64x2_t, int32x2_t)
1139@*@emph{Form of expected instruction(s):} @code{vsubw.s32 @var{q0}, @var{q0}, @var{d0}}
1140@end itemize
1141
1142
1143@itemize @bullet
1144@item int32x4_t vsubw_s16 (int32x4_t, int16x4_t)
1145@*@emph{Form of expected instruction(s):} @code{vsubw.s16 @var{q0}, @var{q0}, @var{d0}}
1146@end itemize
1147
1148
1149@itemize @bullet
1150@item int16x8_t vsubw_s8 (int16x8_t, int8x8_t)
1151@*@emph{Form of expected instruction(s):} @code{vsubw.s8 @var{q0}, @var{q0}, @var{d0}}
1152@end itemize
1153
1154
1155@itemize @bullet
1156@item uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t)
1157@*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{d0}, @var{d0}, @var{d0}}
1158@end itemize
1159
1160
1161@itemize @bullet
1162@item uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t)
1163@*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{d0}, @var{d0}, @var{d0}}
1164@end itemize
1165
1166
1167@itemize @bullet
1168@item uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t)
1169@*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{d0}, @var{d0}, @var{d0}}
1170@end itemize
1171
1172
1173@itemize @bullet
1174@item int32x2_t vhsub_s32 (int32x2_t, int32x2_t)
1175@*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{d0}, @var{d0}, @var{d0}}
1176@end itemize
1177
1178
1179@itemize @bullet
1180@item int16x4_t vhsub_s16 (int16x4_t, int16x4_t)
1181@*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{d0}, @var{d0}, @var{d0}}
1182@end itemize
1183
1184
1185@itemize @bullet
1186@item int8x8_t vhsub_s8 (int8x8_t, int8x8_t)
1187@*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{d0}, @var{d0}, @var{d0}}
1188@end itemize
1189
1190
1191@itemize @bullet
1192@item uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t)
1193@*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{q0}, @var{q0}, @var{q0}}
1194@end itemize
1195
1196
1197@itemize @bullet
1198@item uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t)
1199@*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{q0}, @var{q0}, @var{q0}}
1200@end itemize
1201
1202
1203@itemize @bullet
1204@item uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t)
1205@*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{q0}, @var{q0}, @var{q0}}
1206@end itemize
1207
1208
1209@itemize @bullet
1210@item int32x4_t vhsubq_s32 (int32x4_t, int32x4_t)
1211@*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{q0}, @var{q0}, @var{q0}}
1212@end itemize
1213
1214
1215@itemize @bullet
1216@item int16x8_t vhsubq_s16 (int16x8_t, int16x8_t)
1217@*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{q0}, @var{q0}, @var{q0}}
1218@end itemize
1219
1220
1221@itemize @bullet
1222@item int8x16_t vhsubq_s8 (int8x16_t, int8x16_t)
1223@*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{q0}, @var{q0}, @var{q0}}
1224@end itemize
1225
1226
1227@itemize @bullet
1228@item uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t)
1229@*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{d0}, @var{d0}, @var{d0}}
1230@end itemize
1231
1232
1233@itemize @bullet
1234@item uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t)
1235@*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{d0}, @var{d0}, @var{d0}}
1236@end itemize
1237
1238
1239@itemize @bullet
1240@item uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t)
1241@*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{d0}, @var{d0}, @var{d0}}
1242@end itemize
1243
1244
1245@itemize @bullet
1246@item int32x2_t vqsub_s32 (int32x2_t, int32x2_t)
1247@*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{d0}, @var{d0}, @var{d0}}
1248@end itemize
1249
1250
1251@itemize @bullet
1252@item int16x4_t vqsub_s16 (int16x4_t, int16x4_t)
1253@*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{d0}, @var{d0}, @var{d0}}
1254@end itemize
1255
1256
1257@itemize @bullet
1258@item int8x8_t vqsub_s8 (int8x8_t, int8x8_t)
1259@*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{d0}, @var{d0}, @var{d0}}
1260@end itemize
1261
1262
1263@itemize @bullet
1264@item uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t)
1265@*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{d0}, @var{d0}, @var{d0}}
1266@end itemize
1267
1268
1269@itemize @bullet
1270@item int64x1_t vqsub_s64 (int64x1_t, int64x1_t)
1271@*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{d0}, @var{d0}, @var{d0}}
1272@end itemize
1273
1274
1275@itemize @bullet
1276@item uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t)
1277@*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{q0}, @var{q0}, @var{q0}}
1278@end itemize
1279
1280
1281@itemize @bullet
1282@item uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t)
1283@*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{q0}, @var{q0}, @var{q0}}
1284@end itemize
1285
1286
1287@itemize @bullet
1288@item uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t)
1289@*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{q0}, @var{q0}, @var{q0}}
1290@end itemize
1291
1292
1293@itemize @bullet
1294@item int32x4_t vqsubq_s32 (int32x4_t, int32x4_t)
1295@*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{q0}, @var{q0}, @var{q0}}
1296@end itemize
1297
1298
1299@itemize @bullet
1300@item int16x8_t vqsubq_s16 (int16x8_t, int16x8_t)
1301@*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{q0}, @var{q0}, @var{q0}}
1302@end itemize
1303
1304
1305@itemize @bullet
1306@item int8x16_t vqsubq_s8 (int8x16_t, int8x16_t)
1307@*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{q0}, @var{q0}, @var{q0}}
1308@end itemize
1309
1310
1311@itemize @bullet
1312@item uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t)
1313@*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{q0}, @var{q0}, @var{q0}}
1314@end itemize
1315
1316
1317@itemize @bullet
1318@item int64x2_t vqsubq_s64 (int64x2_t, int64x2_t)
1319@*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{q0}, @var{q0}, @var{q0}}
1320@end itemize
1321
1322
1323@itemize @bullet
1324@item uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t)
1325@*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1326@end itemize
1327
1328
1329@itemize @bullet
1330@item uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t)
1331@*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1332@end itemize
1333
1334
1335@itemize @bullet
1336@item uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t)
1337@*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1338@end itemize
1339
1340
1341@itemize @bullet
1342@item int32x2_t vsubhn_s64 (int64x2_t, int64x2_t)
1343@*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1344@end itemize
1345
1346
1347@itemize @bullet
1348@item int16x4_t vsubhn_s32 (int32x4_t, int32x4_t)
1349@*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1350@end itemize
1351
1352
1353@itemize @bullet
1354@item int8x8_t vsubhn_s16 (int16x8_t, int16x8_t)
1355@*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1356@end itemize
1357
1358
1359@itemize @bullet
1360@item uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t)
1361@*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1362@end itemize
1363
1364
1365@itemize @bullet
1366@item uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t)
1367@*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1368@end itemize
1369
1370
1371@itemize @bullet
1372@item uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t)
1373@*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1374@end itemize
1375
1376
1377@itemize @bullet
1378@item int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t)
1379@*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1380@end itemize
1381
1382
1383@itemize @bullet
1384@item int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t)
1385@*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1386@end itemize
1387
1388
1389@itemize @bullet
1390@item int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t)
1391@*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1392@end itemize
1393
1394
1395
1396
1397@subsubsection Comparison (equal-to)
1398
1399@itemize @bullet
1400@item uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t)
1401@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1402@end itemize
1403
1404
1405@itemize @bullet
1406@item uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t)
1407@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1408@end itemize
1409
1410
1411@itemize @bullet
1412@item uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t)
1413@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1414@end itemize
1415
1416
1417@itemize @bullet
1418@item uint32x2_t vceq_s32 (int32x2_t, int32x2_t)
1419@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1420@end itemize
1421
1422
1423@itemize @bullet
1424@item uint16x4_t vceq_s16 (int16x4_t, int16x4_t)
1425@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1426@end itemize
1427
1428
1429@itemize @bullet
1430@item uint8x8_t vceq_s8 (int8x8_t, int8x8_t)
1431@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1432@end itemize
1433
1434
1435@itemize @bullet
1436@item uint32x2_t vceq_f32 (float32x2_t, float32x2_t)
1437@*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{d0}, @var{d0}, @var{d0}}
1438@end itemize
1439
1440
1441@itemize @bullet
1442@item uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t)
1443@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1444@end itemize
1445
1446
1447@itemize @bullet
1448@item uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t)
1449@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1450@end itemize
1451
1452
1453@itemize @bullet
1454@item uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t)
1455@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1456@end itemize
1457
1458
1459@itemize @bullet
1460@item uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t)
1461@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1462@end itemize
1463
1464
1465@itemize @bullet
1466@item uint32x4_t vceqq_s32 (int32x4_t, int32x4_t)
1467@*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1468@end itemize
1469
1470
1471@itemize @bullet
1472@item uint16x8_t vceqq_s16 (int16x8_t, int16x8_t)
1473@*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1474@end itemize
1475
1476
1477@itemize @bullet
1478@item uint8x16_t vceqq_s8 (int8x16_t, int8x16_t)
1479@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1480@end itemize
1481
1482
1483@itemize @bullet
1484@item uint32x4_t vceqq_f32 (float32x4_t, float32x4_t)
1485@*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{q0}, @var{q0}, @var{q0}}
1486@end itemize
1487
1488
1489@itemize @bullet
1490@item uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t)
1491@*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1492@end itemize
1493
1494
1495
1496
1497@subsubsection Comparison (greater-than-or-equal-to)
1498
1499@itemize @bullet
1500@item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
1501@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1502@end itemize
1503
1504
1505@itemize @bullet
1506@item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
1507@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1508@end itemize
1509
1510
1511@itemize @bullet
1512@item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
1513@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1514@end itemize
1515
1516
1517@itemize @bullet
1518@item uint32x2_t vcge_s32 (int32x2_t, int32x2_t)
1519@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1520@end itemize
1521
1522
1523@itemize @bullet
1524@item uint16x4_t vcge_s16 (int16x4_t, int16x4_t)
1525@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1526@end itemize
1527
1528
1529@itemize @bullet
1530@item uint8x8_t vcge_s8 (int8x8_t, int8x8_t)
1531@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1532@end itemize
1533
1534
1535@itemize @bullet
1536@item uint32x2_t vcge_f32 (float32x2_t, float32x2_t)
1537@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1538@end itemize
1539
1540
1541@itemize @bullet
1542@item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
1543@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1544@end itemize
1545
1546
1547@itemize @bullet
1548@item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
1549@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1550@end itemize
1551
1552
1553@itemize @bullet
1554@item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
1555@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1556@end itemize
1557
1558
1559@itemize @bullet
1560@item uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t)
1561@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1562@end itemize
1563
1564
1565@itemize @bullet
1566@item uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t)
1567@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1568@end itemize
1569
1570
1571@itemize @bullet
1572@item uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t)
1573@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1574@end itemize
1575
1576
1577@itemize @bullet
1578@item uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t)
1579@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1580@end itemize
1581
1582
1583
1584
1585@subsubsection Comparison (less-than-or-equal-to)
1586
1587@itemize @bullet
1588@item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
1589@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1590@end itemize
1591
1592
1593@itemize @bullet
1594@item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
1595@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1596@end itemize
1597
1598
1599@itemize @bullet
1600@item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
1601@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1602@end itemize
1603
1604
1605@itemize @bullet
1606@item uint32x2_t vcle_s32 (int32x2_t, int32x2_t)
1607@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1608@end itemize
1609
1610
1611@itemize @bullet
1612@item uint16x4_t vcle_s16 (int16x4_t, int16x4_t)
1613@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1614@end itemize
1615
1616
1617@itemize @bullet
1618@item uint8x8_t vcle_s8 (int8x8_t, int8x8_t)
1619@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1620@end itemize
1621
1622
1623@itemize @bullet
1624@item uint32x2_t vcle_f32 (float32x2_t, float32x2_t)
1625@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1626@end itemize
1627
1628
1629@itemize @bullet
1630@item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
1631@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1632@end itemize
1633
1634
1635@itemize @bullet
1636@item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
1637@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1638@end itemize
1639
1640
1641@itemize @bullet
1642@item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
1643@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1644@end itemize
1645
1646
1647@itemize @bullet
1648@item uint32x4_t vcleq_s32 (int32x4_t, int32x4_t)
1649@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1650@end itemize
1651
1652
1653@itemize @bullet
1654@item uint16x8_t vcleq_s16 (int16x8_t, int16x8_t)
1655@*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1656@end itemize
1657
1658
1659@itemize @bullet
1660@item uint8x16_t vcleq_s8 (int8x16_t, int8x16_t)
1661@*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1662@end itemize
1663
1664
1665@itemize @bullet
1666@item uint32x4_t vcleq_f32 (float32x4_t, float32x4_t)
1667@*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1668@end itemize
1669
1670
1671
1672
1673@subsubsection Comparison (greater-than)
1674
1675@itemize @bullet
1676@item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
1677@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1678@end itemize
1679
1680
1681@itemize @bullet
1682@item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
1683@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1684@end itemize
1685
1686
1687@itemize @bullet
1688@item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
1689@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1690@end itemize
1691
1692
1693@itemize @bullet
1694@item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t)
1695@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1696@end itemize
1697
1698
1699@itemize @bullet
1700@item uint16x4_t vcgt_s16 (int16x4_t, int16x4_t)
1701@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1702@end itemize
1703
1704
1705@itemize @bullet
1706@item uint8x8_t vcgt_s8 (int8x8_t, int8x8_t)
1707@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1708@end itemize
1709
1710
1711@itemize @bullet
1712@item uint32x2_t vcgt_f32 (float32x2_t, float32x2_t)
1713@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1714@end itemize
1715
1716
1717@itemize @bullet
1718@item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
1719@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1720@end itemize
1721
1722
1723@itemize @bullet
1724@item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
1725@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1726@end itemize
1727
1728
1729@itemize @bullet
1730@item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
1731@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1732@end itemize
1733
1734
1735@itemize @bullet
1736@item uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t)
1737@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1738@end itemize
1739
1740
1741@itemize @bullet
1742@item uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t)
1743@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1744@end itemize
1745
1746
1747@itemize @bullet
1748@item uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t)
1749@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1750@end itemize
1751
1752
1753@itemize @bullet
1754@item uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t)
1755@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1756@end itemize
1757
1758
1759
1760
1761@subsubsection Comparison (less-than)
1762
1763@itemize @bullet
1764@item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
1765@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1766@end itemize
1767
1768
1769@itemize @bullet
1770@item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
1771@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1772@end itemize
1773
1774
1775@itemize @bullet
1776@item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
1777@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1778@end itemize
1779
1780
1781@itemize @bullet
1782@item uint32x2_t vclt_s32 (int32x2_t, int32x2_t)
1783@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1784@end itemize
1785
1786
1787@itemize @bullet
1788@item uint16x4_t vclt_s16 (int16x4_t, int16x4_t)
1789@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1790@end itemize
1791
1792
1793@itemize @bullet
1794@item uint8x8_t vclt_s8 (int8x8_t, int8x8_t)
1795@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1796@end itemize
1797
1798
1799@itemize @bullet
1800@item uint32x2_t vclt_f32 (float32x2_t, float32x2_t)
1801@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1802@end itemize
1803
1804
1805@itemize @bullet
1806@item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
1807@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1808@end itemize
1809
1810
1811@itemize @bullet
1812@item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
1813@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1814@end itemize
1815
1816
1817@itemize @bullet
1818@item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
1819@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1820@end itemize
1821
1822
1823@itemize @bullet
1824@item uint32x4_t vcltq_s32 (int32x4_t, int32x4_t)
1825@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1826@end itemize
1827
1828
1829@itemize @bullet
1830@item uint16x8_t vcltq_s16 (int16x8_t, int16x8_t)
1831@*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1832@end itemize
1833
1834
1835@itemize @bullet
1836@item uint8x16_t vcltq_s8 (int8x16_t, int8x16_t)
1837@*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1838@end itemize
1839
1840
1841@itemize @bullet
1842@item uint32x4_t vcltq_f32 (float32x4_t, float32x4_t)
1843@*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1844@end itemize
1845
1846
1847
1848
1849@subsubsection Comparison (absolute greater-than-or-equal-to)
1850
1851@itemize @bullet
1852@item uint32x2_t vcage_f32 (float32x2_t, float32x2_t)
1853@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1854@end itemize
1855
1856
1857@itemize @bullet
1858@item uint32x4_t vcageq_f32 (float32x4_t, float32x4_t)
1859@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1860@end itemize
1861
1862
1863
1864
1865@subsubsection Comparison (absolute less-than-or-equal-to)
1866
1867@itemize @bullet
1868@item uint32x2_t vcale_f32 (float32x2_t, float32x2_t)
1869@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1870@end itemize
1871
1872
1873@itemize @bullet
1874@item uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t)
1875@*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1876@end itemize
1877
1878
1879
1880
1881@subsubsection Comparison (absolute greater-than)
1882
1883@itemize @bullet
1884@item uint32x2_t vcagt_f32 (float32x2_t, float32x2_t)
1885@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1886@end itemize
1887
1888
1889@itemize @bullet
1890@item uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t)
1891@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
1892@end itemize
1893
1894
1895
1896
1897@subsubsection Comparison (absolute less-than)
1898
1899@itemize @bullet
1900@item uint32x2_t vcalt_f32 (float32x2_t, float32x2_t)
1901@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1902@end itemize
1903
1904
1905@itemize @bullet
1906@item uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t)
1907@*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
1908@end itemize
1909
1910
1911
1912
1913@subsubsection Test bits
1914
1915@itemize @bullet
1916@item uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t)
1917@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
1918@end itemize
1919
1920
1921@itemize @bullet
1922@item uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t)
1923@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
1924@end itemize
1925
1926
1927@itemize @bullet
1928@item uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t)
1929@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1930@end itemize
1931
1932
1933@itemize @bullet
1934@item uint32x2_t vtst_s32 (int32x2_t, int32x2_t)
1935@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
1936@end itemize
1937
1938
1939@itemize @bullet
1940@item uint16x4_t vtst_s16 (int16x4_t, int16x4_t)
1941@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
1942@end itemize
1943
1944
1945@itemize @bullet
1946@item uint8x8_t vtst_s8 (int8x8_t, int8x8_t)
1947@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1948@end itemize
1949
1950
1951@itemize @bullet
1952@item uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t)
1953@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1954@end itemize
1955
1956
1957@itemize @bullet
1958@item uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t)
1959@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
1960@end itemize
1961
1962
1963@itemize @bullet
1964@item uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t)
1965@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
1966@end itemize
1967
1968
1969@itemize @bullet
1970@item uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t)
1971@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
1972@end itemize
1973
1974
1975@itemize @bullet
1976@item uint32x4_t vtstq_s32 (int32x4_t, int32x4_t)
1977@*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
1978@end itemize
1979
1980
1981@itemize @bullet
1982@item uint16x8_t vtstq_s16 (int16x8_t, int16x8_t)
1983@*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
1984@end itemize
1985
1986
1987@itemize @bullet
1988@item uint8x16_t vtstq_s8 (int8x16_t, int8x16_t)
1989@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
1990@end itemize
1991
1992
1993@itemize @bullet
1994@item uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t)
1995@*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
1996@end itemize
1997
1998
1999
2000
2001@subsubsection Absolute difference
2002
2003@itemize @bullet
2004@item uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t)
2005@*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{d0}, @var{d0}, @var{d0}}
2006@end itemize
2007
2008
2009@itemize @bullet
2010@item uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t)
2011@*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{d0}, @var{d0}, @var{d0}}
2012@end itemize
2013
2014
2015@itemize @bullet
2016@item uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t)
2017@*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{d0}, @var{d0}, @var{d0}}
2018@end itemize
2019
2020
2021@itemize @bullet
2022@item int32x2_t vabd_s32 (int32x2_t, int32x2_t)
2023@*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{d0}, @var{d0}, @var{d0}}
2024@end itemize
2025
2026
2027@itemize @bullet
2028@item int16x4_t vabd_s16 (int16x4_t, int16x4_t)
2029@*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{d0}, @var{d0}, @var{d0}}
2030@end itemize
2031
2032
2033@itemize @bullet
2034@item int8x8_t vabd_s8 (int8x8_t, int8x8_t)
2035@*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{d0}, @var{d0}, @var{d0}}
2036@end itemize
2037
2038
2039@itemize @bullet
2040@item float32x2_t vabd_f32 (float32x2_t, float32x2_t)
2041@*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{d0}, @var{d0}, @var{d0}}
2042@end itemize
2043
2044
2045@itemize @bullet
2046@item uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t)
2047@*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{q0}, @var{q0}, @var{q0}}
2048@end itemize
2049
2050
2051@itemize @bullet
2052@item uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t)
2053@*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{q0}, @var{q0}, @var{q0}}
2054@end itemize
2055
2056
2057@itemize @bullet
2058@item uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t)
2059@*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{q0}, @var{q0}, @var{q0}}
2060@end itemize
2061
2062
2063@itemize @bullet
2064@item int32x4_t vabdq_s32 (int32x4_t, int32x4_t)
2065@*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{q0}, @var{q0}, @var{q0}}
2066@end itemize
2067
2068
2069@itemize @bullet
2070@item int16x8_t vabdq_s16 (int16x8_t, int16x8_t)
2071@*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{q0}, @var{q0}, @var{q0}}
2072@end itemize
2073
2074
2075@itemize @bullet
2076@item int8x16_t vabdq_s8 (int8x16_t, int8x16_t)
2077@*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{q0}, @var{q0}, @var{q0}}
2078@end itemize
2079
2080
2081@itemize @bullet
2082@item float32x4_t vabdq_f32 (float32x4_t, float32x4_t)
2083@*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{q0}, @var{q0}, @var{q0}}
2084@end itemize
2085
2086
2087@itemize @bullet
2088@item uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t)
2089@*@emph{Form of expected instruction(s):} @code{vabdl.u32 @var{q0}, @var{d0}, @var{d0}}
2090@end itemize
2091
2092
2093@itemize @bullet
2094@item uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t)
2095@*@emph{Form of expected instruction(s):} @code{vabdl.u16 @var{q0}, @var{d0}, @var{d0}}
2096@end itemize
2097
2098
2099@itemize @bullet
2100@item uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t)
2101@*@emph{Form of expected instruction(s):} @code{vabdl.u8 @var{q0}, @var{d0}, @var{d0}}
2102@end itemize
2103
2104
2105@itemize @bullet
2106@item int64x2_t vabdl_s32 (int32x2_t, int32x2_t)
2107@*@emph{Form of expected instruction(s):} @code{vabdl.s32 @var{q0}, @var{d0}, @var{d0}}
2108@end itemize
2109
2110
2111@itemize @bullet
2112@item int32x4_t vabdl_s16 (int16x4_t, int16x4_t)
2113@*@emph{Form of expected instruction(s):} @code{vabdl.s16 @var{q0}, @var{d0}, @var{d0}}
2114@end itemize
2115
2116
2117@itemize @bullet
2118@item int16x8_t vabdl_s8 (int8x8_t, int8x8_t)
2119@*@emph{Form of expected instruction(s):} @code{vabdl.s8 @var{q0}, @var{d0}, @var{d0}}
2120@end itemize
2121
2122
2123
2124
2125@subsubsection Absolute difference and accumulate
2126
2127@itemize @bullet
2128@item uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
2129@*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{d0}, @var{d0}, @var{d0}}
2130@end itemize
2131
2132
2133@itemize @bullet
2134@item uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
2135@*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{d0}, @var{d0}, @var{d0}}
2136@end itemize
2137
2138
2139@itemize @bullet
2140@item uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
2141@*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{d0}, @var{d0}, @var{d0}}
2142@end itemize
2143
2144
2145@itemize @bullet
2146@item int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t)
2147@*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{d0}, @var{d0}, @var{d0}}
2148@end itemize
2149
2150
2151@itemize @bullet
2152@item int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t)
2153@*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{d0}, @var{d0}, @var{d0}}
2154@end itemize
2155
2156
2157@itemize @bullet
2158@item int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t)
2159@*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{d0}, @var{d0}, @var{d0}}
2160@end itemize
2161
2162
2163@itemize @bullet
2164@item uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2165@*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{q0}, @var{q0}, @var{q0}}
2166@end itemize
2167
2168
2169@itemize @bullet
2170@item uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
2171@*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{q0}, @var{q0}, @var{q0}}
2172@end itemize
2173
2174
2175@itemize @bullet
2176@item uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
2177@*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{q0}, @var{q0}, @var{q0}}
2178@end itemize
2179
2180
2181@itemize @bullet
2182@item int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t)
2183@*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{q0}, @var{q0}, @var{q0}}
2184@end itemize
2185
2186
2187@itemize @bullet
2188@item int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t)
2189@*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{q0}, @var{q0}, @var{q0}}
2190@end itemize
2191
2192
2193@itemize @bullet
2194@item int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t)
2195@*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{q0}, @var{q0}, @var{q0}}
2196@end itemize
2197
2198
2199@itemize @bullet
2200@item uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
2201@*@emph{Form of expected instruction(s):} @code{vabal.u32 @var{q0}, @var{d0}, @var{d0}}
2202@end itemize
2203
2204
2205@itemize @bullet
2206@item uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
2207@*@emph{Form of expected instruction(s):} @code{vabal.u16 @var{q0}, @var{d0}, @var{d0}}
2208@end itemize
2209
2210
2211@itemize @bullet
2212@item uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
2213@*@emph{Form of expected instruction(s):} @code{vabal.u8 @var{q0}, @var{d0}, @var{d0}}
2214@end itemize
2215
2216
2217@itemize @bullet
2218@item int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t)
2219@*@emph{Form of expected instruction(s):} @code{vabal.s32 @var{q0}, @var{d0}, @var{d0}}
2220@end itemize
2221
2222
2223@itemize @bullet
2224@item int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t)
2225@*@emph{Form of expected instruction(s):} @code{vabal.s16 @var{q0}, @var{d0}, @var{d0}}
2226@end itemize
2227
2228
2229@itemize @bullet
2230@item int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t)
2231@*@emph{Form of expected instruction(s):} @code{vabal.s8 @var{q0}, @var{d0}, @var{d0}}
2232@end itemize
2233
2234
2235
2236
2237@subsubsection Maximum
2238
2239@itemize @bullet
2240@item uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t)
2241@*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{d0}, @var{d0}, @var{d0}}
2242@end itemize
2243
2244
2245@itemize @bullet
2246@item uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t)
2247@*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{d0}, @var{d0}, @var{d0}}
2248@end itemize
2249
2250
2251@itemize @bullet
2252@item uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t)
2253@*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{d0}, @var{d0}, @var{d0}}
2254@end itemize
2255
2256
2257@itemize @bullet
2258@item int32x2_t vmax_s32 (int32x2_t, int32x2_t)
2259@*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{d0}, @var{d0}, @var{d0}}
2260@end itemize
2261
2262
2263@itemize @bullet
2264@item int16x4_t vmax_s16 (int16x4_t, int16x4_t)
2265@*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{d0}, @var{d0}, @var{d0}}
2266@end itemize
2267
2268
2269@itemize @bullet
2270@item int8x8_t vmax_s8 (int8x8_t, int8x8_t)
2271@*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{d0}, @var{d0}, @var{d0}}
2272@end itemize
2273
2274
2275@itemize @bullet
2276@item float32x2_t vmax_f32 (float32x2_t, float32x2_t)
2277@*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{d0}, @var{d0}, @var{d0}}
2278@end itemize
2279
2280
2281@itemize @bullet
2282@item uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t)
2283@*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{q0}, @var{q0}, @var{q0}}
2284@end itemize
2285
2286
2287@itemize @bullet
2288@item uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t)
2289@*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{q0}, @var{q0}, @var{q0}}
2290@end itemize
2291
2292
2293@itemize @bullet
2294@item uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t)
2295@*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{q0}, @var{q0}, @var{q0}}
2296@end itemize
2297
2298
2299@itemize @bullet
2300@item int32x4_t vmaxq_s32 (int32x4_t, int32x4_t)
2301@*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{q0}, @var{q0}, @var{q0}}
2302@end itemize
2303
2304
2305@itemize @bullet
2306@item int16x8_t vmaxq_s16 (int16x8_t, int16x8_t)
2307@*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{q0}, @var{q0}, @var{q0}}
2308@end itemize
2309
2310
2311@itemize @bullet
2312@item int8x16_t vmaxq_s8 (int8x16_t, int8x16_t)
2313@*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{q0}, @var{q0}, @var{q0}}
2314@end itemize
2315
2316
2317@itemize @bullet
2318@item float32x4_t vmaxq_f32 (float32x4_t, float32x4_t)
2319@*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{q0}, @var{q0}, @var{q0}}
2320@end itemize
2321
2322
2323
2324
2325@subsubsection Minimum
2326
2327@itemize @bullet
2328@item uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t)
2329@*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{d0}, @var{d0}, @var{d0}}
2330@end itemize
2331
2332
2333@itemize @bullet
2334@item uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t)
2335@*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{d0}, @var{d0}, @var{d0}}
2336@end itemize
2337
2338
2339@itemize @bullet
2340@item uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t)
2341@*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{d0}, @var{d0}, @var{d0}}
2342@end itemize
2343
2344
2345@itemize @bullet
2346@item int32x2_t vmin_s32 (int32x2_t, int32x2_t)
2347@*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{d0}, @var{d0}, @var{d0}}
2348@end itemize
2349
2350
2351@itemize @bullet
2352@item int16x4_t vmin_s16 (int16x4_t, int16x4_t)
2353@*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{d0}, @var{d0}, @var{d0}}
2354@end itemize
2355
2356
2357@itemize @bullet
2358@item int8x8_t vmin_s8 (int8x8_t, int8x8_t)
2359@*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{d0}, @var{d0}, @var{d0}}
2360@end itemize
2361
2362
2363@itemize @bullet
2364@item float32x2_t vmin_f32 (float32x2_t, float32x2_t)
2365@*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{d0}, @var{d0}, @var{d0}}
2366@end itemize
2367
2368
2369@itemize @bullet
2370@item uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t)
2371@*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{q0}, @var{q0}, @var{q0}}
2372@end itemize
2373
2374
2375@itemize @bullet
2376@item uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t)
2377@*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{q0}, @var{q0}, @var{q0}}
2378@end itemize
2379
2380
2381@itemize @bullet
2382@item uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t)
2383@*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{q0}, @var{q0}, @var{q0}}
2384@end itemize
2385
2386
2387@itemize @bullet
2388@item int32x4_t vminq_s32 (int32x4_t, int32x4_t)
2389@*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{q0}, @var{q0}, @var{q0}}
2390@end itemize
2391
2392
2393@itemize @bullet
2394@item int16x8_t vminq_s16 (int16x8_t, int16x8_t)
2395@*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{q0}, @var{q0}, @var{q0}}
2396@end itemize
2397
2398
2399@itemize @bullet
2400@item int8x16_t vminq_s8 (int8x16_t, int8x16_t)
2401@*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{q0}, @var{q0}, @var{q0}}
2402@end itemize
2403
2404
2405@itemize @bullet
2406@item float32x4_t vminq_f32 (float32x4_t, float32x4_t)
2407@*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{q0}, @var{q0}, @var{q0}}
2408@end itemize
2409
2410
2411
2412
2413@subsubsection Pairwise add
2414
2415@itemize @bullet
2416@item uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t)
2417@*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2418@end itemize
2419
2420
2421@itemize @bullet
2422@item uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t)
2423@*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2424@end itemize
2425
2426
2427@itemize @bullet
2428@item uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t)
2429@*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2430@end itemize
2431
2432
2433@itemize @bullet
2434@item int32x2_t vpadd_s32 (int32x2_t, int32x2_t)
2435@*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2436@end itemize
2437
2438
2439@itemize @bullet
2440@item int16x4_t vpadd_s16 (int16x4_t, int16x4_t)
2441@*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2442@end itemize
2443
2444
2445@itemize @bullet
2446@item int8x8_t vpadd_s8 (int8x8_t, int8x8_t)
2447@*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2448@end itemize
2449
2450
2451@itemize @bullet
2452@item float32x2_t vpadd_f32 (float32x2_t, float32x2_t)
2453@*@emph{Form of expected instruction(s):} @code{vpadd.f32 @var{d0}, @var{d0}, @var{d0}}
2454@end itemize
2455
2456
2457@itemize @bullet
2458@item uint64x1_t vpaddl_u32 (uint32x2_t)
2459@*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{d0}, @var{d0}}
2460@end itemize
2461
2462
2463@itemize @bullet
2464@item uint32x2_t vpaddl_u16 (uint16x4_t)
2465@*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{d0}, @var{d0}}
2466@end itemize
2467
2468
2469@itemize @bullet
2470@item uint16x4_t vpaddl_u8 (uint8x8_t)
2471@*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{d0}, @var{d0}}
2472@end itemize
2473
2474
2475@itemize @bullet
2476@item int64x1_t vpaddl_s32 (int32x2_t)
2477@*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{d0}, @var{d0}}
2478@end itemize
2479
2480
2481@itemize @bullet
2482@item int32x2_t vpaddl_s16 (int16x4_t)
2483@*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{d0}, @var{d0}}
2484@end itemize
2485
2486
2487@itemize @bullet
2488@item int16x4_t vpaddl_s8 (int8x8_t)
2489@*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{d0}, @var{d0}}
2490@end itemize
2491
2492
2493@itemize @bullet
2494@item uint64x2_t vpaddlq_u32 (uint32x4_t)
2495@*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{q0}, @var{q0}}
2496@end itemize
2497
2498
2499@itemize @bullet
2500@item uint32x4_t vpaddlq_u16 (uint16x8_t)
2501@*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{q0}, @var{q0}}
2502@end itemize
2503
2504
2505@itemize @bullet
2506@item uint16x8_t vpaddlq_u8 (uint8x16_t)
2507@*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{q0}, @var{q0}}
2508@end itemize
2509
2510
2511@itemize @bullet
2512@item int64x2_t vpaddlq_s32 (int32x4_t)
2513@*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{q0}, @var{q0}}
2514@end itemize
2515
2516
2517@itemize @bullet
2518@item int32x4_t vpaddlq_s16 (int16x8_t)
2519@*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{q0}, @var{q0}}
2520@end itemize
2521
2522
2523@itemize @bullet
2524@item int16x8_t vpaddlq_s8 (int8x16_t)
2525@*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{q0}, @var{q0}}
2526@end itemize
2527
2528
2529
2530
2531@subsubsection Pairwise add, single_opcode widen and accumulate
2532
2533@itemize @bullet
2534@item uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t)
2535@*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{d0}, @var{d0}}
2536@end itemize
2537
2538
2539@itemize @bullet
2540@item uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t)
2541@*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{d0}, @var{d0}}
2542@end itemize
2543
2544
2545@itemize @bullet
2546@item uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t)
2547@*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{d0}, @var{d0}}
2548@end itemize
2549
2550
2551@itemize @bullet
2552@item int64x1_t vpadal_s32 (int64x1_t, int32x2_t)
2553@*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{d0}, @var{d0}}
2554@end itemize
2555
2556
2557@itemize @bullet
2558@item int32x2_t vpadal_s16 (int32x2_t, int16x4_t)
2559@*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{d0}, @var{d0}}
2560@end itemize
2561
2562
2563@itemize @bullet
2564@item int16x4_t vpadal_s8 (int16x4_t, int8x8_t)
2565@*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{d0}, @var{d0}}
2566@end itemize
2567
2568
2569@itemize @bullet
2570@item uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t)
2571@*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{q0}, @var{q0}}
2572@end itemize
2573
2574
2575@itemize @bullet
2576@item uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t)
2577@*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{q0}, @var{q0}}
2578@end itemize
2579
2580
2581@itemize @bullet
2582@item uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t)
2583@*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{q0}, @var{q0}}
2584@end itemize
2585
2586
2587@itemize @bullet
2588@item int64x2_t vpadalq_s32 (int64x2_t, int32x4_t)
2589@*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{q0}, @var{q0}}
2590@end itemize
2591
2592
2593@itemize @bullet
2594@item int32x4_t vpadalq_s16 (int32x4_t, int16x8_t)
2595@*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{q0}, @var{q0}}
2596@end itemize
2597
2598
2599@itemize @bullet
2600@item int16x8_t vpadalq_s8 (int16x8_t, int8x16_t)
2601@*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{q0}, @var{q0}}
2602@end itemize
2603
2604
2605
2606
2607@subsubsection Folding maximum
2608
2609@itemize @bullet
2610@item uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t)
2611@*@emph{Form of expected instruction(s):} @code{vpmax.u32 @var{d0}, @var{d0}, @var{d0}}
2612@end itemize
2613
2614
2615@itemize @bullet
2616@item uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t)
2617@*@emph{Form of expected instruction(s):} @code{vpmax.u16 @var{d0}, @var{d0}, @var{d0}}
2618@end itemize
2619
2620
2621@itemize @bullet
2622@item uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t)
2623@*@emph{Form of expected instruction(s):} @code{vpmax.u8 @var{d0}, @var{d0}, @var{d0}}
2624@end itemize
2625
2626
2627@itemize @bullet
2628@item int32x2_t vpmax_s32 (int32x2_t, int32x2_t)
2629@*@emph{Form of expected instruction(s):} @code{vpmax.s32 @var{d0}, @var{d0}, @var{d0}}
2630@end itemize
2631
2632
2633@itemize @bullet
2634@item int16x4_t vpmax_s16 (int16x4_t, int16x4_t)
2635@*@emph{Form of expected instruction(s):} @code{vpmax.s16 @var{d0}, @var{d0}, @var{d0}}
2636@end itemize
2637
2638
2639@itemize @bullet
2640@item int8x8_t vpmax_s8 (int8x8_t, int8x8_t)
2641@*@emph{Form of expected instruction(s):} @code{vpmax.s8 @var{d0}, @var{d0}, @var{d0}}
2642@end itemize
2643
2644
2645@itemize @bullet
2646@item float32x2_t vpmax_f32 (float32x2_t, float32x2_t)
2647@*@emph{Form of expected instruction(s):} @code{vpmax.f32 @var{d0}, @var{d0}, @var{d0}}
2648@end itemize
2649
2650
2651
2652
2653@subsubsection Folding minimum
2654
2655@itemize @bullet
2656@item uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t)
2657@*@emph{Form of expected instruction(s):} @code{vpmin.u32 @var{d0}, @var{d0}, @var{d0}}
2658@end itemize
2659
2660
2661@itemize @bullet
2662@item uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t)
2663@*@emph{Form of expected instruction(s):} @code{vpmin.u16 @var{d0}, @var{d0}, @var{d0}}
2664@end itemize
2665
2666
2667@itemize @bullet
2668@item uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t)
2669@*@emph{Form of expected instruction(s):} @code{vpmin.u8 @var{d0}, @var{d0}, @var{d0}}
2670@end itemize
2671
2672
2673@itemize @bullet
2674@item int32x2_t vpmin_s32 (int32x2_t, int32x2_t)
2675@*@emph{Form of expected instruction(s):} @code{vpmin.s32 @var{d0}, @var{d0}, @var{d0}}
2676@end itemize
2677
2678
2679@itemize @bullet
2680@item int16x4_t vpmin_s16 (int16x4_t, int16x4_t)
2681@*@emph{Form of expected instruction(s):} @code{vpmin.s16 @var{d0}, @var{d0}, @var{d0}}
2682@end itemize
2683
2684
2685@itemize @bullet
2686@item int8x8_t vpmin_s8 (int8x8_t, int8x8_t)
2687@*@emph{Form of expected instruction(s):} @code{vpmin.s8 @var{d0}, @var{d0}, @var{d0}}
2688@end itemize
2689
2690
2691@itemize @bullet
2692@item float32x2_t vpmin_f32 (float32x2_t, float32x2_t)
2693@*@emph{Form of expected instruction(s):} @code{vpmin.f32 @var{d0}, @var{d0}, @var{d0}}
2694@end itemize
2695
2696
2697
2698
2699@subsubsection Reciprocal step
2700
2701@itemize @bullet
2702@item float32x2_t vrecps_f32 (float32x2_t, float32x2_t)
2703@*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{d0}, @var{d0}, @var{d0}}
2704@end itemize
2705
2706
2707@itemize @bullet
2708@item float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t)
2709@*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{q0}, @var{q0}, @var{q0}}
2710@end itemize
2711
2712
2713@itemize @bullet
2714@item float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t)
2715@*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{d0}, @var{d0}, @var{d0}}
2716@end itemize
2717
2718
2719@itemize @bullet
2720@item float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t)
2721@*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{q0}, @var{q0}, @var{q0}}
2722@end itemize
2723
2724
2725
2726
2727@subsubsection Vector shift left
2728
2729@itemize @bullet
2730@item uint32x2_t vshl_u32 (uint32x2_t, int32x2_t)
2731@*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{d0}, @var{d0}, @var{d0}}
2732@end itemize
2733
2734
2735@itemize @bullet
2736@item uint16x4_t vshl_u16 (uint16x4_t, int16x4_t)
2737@*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{d0}, @var{d0}, @var{d0}}
2738@end itemize
2739
2740
2741@itemize @bullet
2742@item uint8x8_t vshl_u8 (uint8x8_t, int8x8_t)
2743@*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{d0}, @var{d0}, @var{d0}}
2744@end itemize
2745
2746
2747@itemize @bullet
2748@item int32x2_t vshl_s32 (int32x2_t, int32x2_t)
2749@*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{d0}, @var{d0}, @var{d0}}
2750@end itemize
2751
2752
2753@itemize @bullet
2754@item int16x4_t vshl_s16 (int16x4_t, int16x4_t)
2755@*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{d0}, @var{d0}, @var{d0}}
2756@end itemize
2757
2758
2759@itemize @bullet
2760@item int8x8_t vshl_s8 (int8x8_t, int8x8_t)
2761@*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{d0}, @var{d0}, @var{d0}}
2762@end itemize
2763
2764
2765@itemize @bullet
2766@item uint64x1_t vshl_u64 (uint64x1_t, int64x1_t)
2767@*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{d0}, @var{d0}, @var{d0}}
2768@end itemize
2769
2770
2771@itemize @bullet
2772@item int64x1_t vshl_s64 (int64x1_t, int64x1_t)
2773@*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{d0}, @var{d0}, @var{d0}}
2774@end itemize
2775
2776
2777@itemize @bullet
2778@item uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t)
2779@*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{q0}, @var{q0}, @var{q0}}
2780@end itemize
2781
2782
2783@itemize @bullet
2784@item uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t)
2785@*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{q0}, @var{q0}, @var{q0}}
2786@end itemize
2787
2788
2789@itemize @bullet
2790@item uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t)
2791@*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{q0}, @var{q0}, @var{q0}}
2792@end itemize
2793
2794
2795@itemize @bullet
2796@item int32x4_t vshlq_s32 (int32x4_t, int32x4_t)
2797@*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{q0}, @var{q0}, @var{q0}}
2798@end itemize
2799
2800
2801@itemize @bullet
2802@item int16x8_t vshlq_s16 (int16x8_t, int16x8_t)
2803@*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{q0}, @var{q0}, @var{q0}}
2804@end itemize
2805
2806
2807@itemize @bullet
2808@item int8x16_t vshlq_s8 (int8x16_t, int8x16_t)
2809@*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{q0}, @var{q0}, @var{q0}}
2810@end itemize
2811
2812
2813@itemize @bullet
2814@item uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t)
2815@*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{q0}, @var{q0}, @var{q0}}
2816@end itemize
2817
2818
2819@itemize @bullet
2820@item int64x2_t vshlq_s64 (int64x2_t, int64x2_t)
2821@*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{q0}, @var{q0}, @var{q0}}
2822@end itemize
2823
2824
2825@itemize @bullet
2826@item uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t)
2827@*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{d0}, @var{d0}, @var{d0}}
2828@end itemize
2829
2830
2831@itemize @bullet
2832@item uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t)
2833@*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{d0}, @var{d0}, @var{d0}}
2834@end itemize
2835
2836
2837@itemize @bullet
2838@item uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t)
2839@*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{d0}, @var{d0}, @var{d0}}
2840@end itemize
2841
2842
2843@itemize @bullet
2844@item int32x2_t vrshl_s32 (int32x2_t, int32x2_t)
2845@*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{d0}, @var{d0}, @var{d0}}
2846@end itemize
2847
2848
2849@itemize @bullet
2850@item int16x4_t vrshl_s16 (int16x4_t, int16x4_t)
2851@*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{d0}, @var{d0}, @var{d0}}
2852@end itemize
2853
2854
2855@itemize @bullet
2856@item int8x8_t vrshl_s8 (int8x8_t, int8x8_t)
2857@*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{d0}, @var{d0}, @var{d0}}
2858@end itemize
2859
2860
2861@itemize @bullet
2862@item uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t)
2863@*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{d0}, @var{d0}, @var{d0}}
2864@end itemize
2865
2866
2867@itemize @bullet
2868@item int64x1_t vrshl_s64 (int64x1_t, int64x1_t)
2869@*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{d0}, @var{d0}, @var{d0}}
2870@end itemize
2871
2872
2873@itemize @bullet
2874@item uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t)
2875@*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{q0}, @var{q0}, @var{q0}}
2876@end itemize
2877
2878
2879@itemize @bullet
2880@item uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t)
2881@*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{q0}, @var{q0}, @var{q0}}
2882@end itemize
2883
2884
2885@itemize @bullet
2886@item uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t)
2887@*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{q0}, @var{q0}, @var{q0}}
2888@end itemize
2889
2890
2891@itemize @bullet
2892@item int32x4_t vrshlq_s32 (int32x4_t, int32x4_t)
2893@*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{q0}, @var{q0}, @var{q0}}
2894@end itemize
2895
2896
2897@itemize @bullet
2898@item int16x8_t vrshlq_s16 (int16x8_t, int16x8_t)
2899@*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{q0}, @var{q0}, @var{q0}}
2900@end itemize
2901
2902
2903@itemize @bullet
2904@item int8x16_t vrshlq_s8 (int8x16_t, int8x16_t)
2905@*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{q0}, @var{q0}, @var{q0}}
2906@end itemize
2907
2908
2909@itemize @bullet
2910@item uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t)
2911@*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{q0}, @var{q0}, @var{q0}}
2912@end itemize
2913
2914
2915@itemize @bullet
2916@item int64x2_t vrshlq_s64 (int64x2_t, int64x2_t)
2917@*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{q0}, @var{q0}, @var{q0}}
2918@end itemize
2919
2920
2921@itemize @bullet
2922@item uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t)
2923@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, @var{d0}}
2924@end itemize
2925
2926
2927@itemize @bullet
2928@item uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t)
2929@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, @var{d0}}
2930@end itemize
2931
2932
2933@itemize @bullet
2934@item uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t)
2935@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, @var{d0}}
2936@end itemize
2937
2938
2939@itemize @bullet
2940@item int32x2_t vqshl_s32 (int32x2_t, int32x2_t)
2941@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, @var{d0}}
2942@end itemize
2943
2944
2945@itemize @bullet
2946@item int16x4_t vqshl_s16 (int16x4_t, int16x4_t)
2947@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, @var{d0}}
2948@end itemize
2949
2950
2951@itemize @bullet
2952@item int8x8_t vqshl_s8 (int8x8_t, int8x8_t)
2953@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, @var{d0}}
2954@end itemize
2955
2956
2957@itemize @bullet
2958@item uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t)
2959@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, @var{d0}}
2960@end itemize
2961
2962
2963@itemize @bullet
2964@item int64x1_t vqshl_s64 (int64x1_t, int64x1_t)
2965@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, @var{d0}}
2966@end itemize
2967
2968
2969@itemize @bullet
2970@item uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t)
2971@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, @var{q0}}
2972@end itemize
2973
2974
2975@itemize @bullet
2976@item uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t)
2977@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, @var{q0}}
2978@end itemize
2979
2980
2981@itemize @bullet
2982@item uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t)
2983@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, @var{q0}}
2984@end itemize
2985
2986
2987@itemize @bullet
2988@item int32x4_t vqshlq_s32 (int32x4_t, int32x4_t)
2989@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, @var{q0}}
2990@end itemize
2991
2992
2993@itemize @bullet
2994@item int16x8_t vqshlq_s16 (int16x8_t, int16x8_t)
2995@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, @var{q0}}
2996@end itemize
2997
2998
2999@itemize @bullet
3000@item int8x16_t vqshlq_s8 (int8x16_t, int8x16_t)
3001@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, @var{q0}}
3002@end itemize
3003
3004
3005@itemize @bullet
3006@item uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t)
3007@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, @var{q0}}
3008@end itemize
3009
3010
3011@itemize @bullet
3012@item int64x2_t vqshlq_s64 (int64x2_t, int64x2_t)
3013@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, @var{q0}}
3014@end itemize
3015
3016
3017@itemize @bullet
3018@item uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t)
3019@*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{d0}, @var{d0}, @var{d0}}
3020@end itemize
3021
3022
3023@itemize @bullet
3024@item uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t)
3025@*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{d0}, @var{d0}, @var{d0}}
3026@end itemize
3027
3028
3029@itemize @bullet
3030@item uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t)
3031@*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{d0}, @var{d0}, @var{d0}}
3032@end itemize
3033
3034
3035@itemize @bullet
3036@item int32x2_t vqrshl_s32 (int32x2_t, int32x2_t)
3037@*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{d0}, @var{d0}, @var{d0}}
3038@end itemize
3039
3040
3041@itemize @bullet
3042@item int16x4_t vqrshl_s16 (int16x4_t, int16x4_t)
3043@*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{d0}, @var{d0}, @var{d0}}
3044@end itemize
3045
3046
3047@itemize @bullet
3048@item int8x8_t vqrshl_s8 (int8x8_t, int8x8_t)
3049@*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{d0}, @var{d0}, @var{d0}}
3050@end itemize
3051
3052
3053@itemize @bullet
3054@item uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t)
3055@*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{d0}, @var{d0}, @var{d0}}
3056@end itemize
3057
3058
3059@itemize @bullet
3060@item int64x1_t vqrshl_s64 (int64x1_t, int64x1_t)
3061@*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{d0}, @var{d0}, @var{d0}}
3062@end itemize
3063
3064
3065@itemize @bullet
3066@item uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t)
3067@*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{q0}, @var{q0}, @var{q0}}
3068@end itemize
3069
3070
3071@itemize @bullet
3072@item uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t)
3073@*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{q0}, @var{q0}, @var{q0}}
3074@end itemize
3075
3076
3077@itemize @bullet
3078@item uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t)
3079@*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{q0}, @var{q0}, @var{q0}}
3080@end itemize
3081
3082
3083@itemize @bullet
3084@item int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t)
3085@*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{q0}, @var{q0}, @var{q0}}
3086@end itemize
3087
3088
3089@itemize @bullet
3090@item int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t)
3091@*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{q0}, @var{q0}, @var{q0}}
3092@end itemize
3093
3094
3095@itemize @bullet
3096@item int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t)
3097@*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{q0}, @var{q0}, @var{q0}}
3098@end itemize
3099
3100
3101@itemize @bullet
3102@item uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t)
3103@*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{q0}, @var{q0}, @var{q0}}
3104@end itemize
3105
3106
3107@itemize @bullet
3108@item int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t)
3109@*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{q0}, @var{q0}, @var{q0}}
3110@end itemize
3111
3112
3113
3114
3115@subsubsection Vector shift left by constant
3116
3117@itemize @bullet
3118@item uint32x2_t vshl_n_u32 (uint32x2_t, const int)
3119@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3120@end itemize
3121
3122
3123@itemize @bullet
3124@item uint16x4_t vshl_n_u16 (uint16x4_t, const int)
3125@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3126@end itemize
3127
3128
3129@itemize @bullet
3130@item uint8x8_t vshl_n_u8 (uint8x8_t, const int)
3131@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3132@end itemize
3133
3134
3135@itemize @bullet
3136@item int32x2_t vshl_n_s32 (int32x2_t, const int)
3137@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3138@end itemize
3139
3140
3141@itemize @bullet
3142@item int16x4_t vshl_n_s16 (int16x4_t, const int)
3143@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3144@end itemize
3145
3146
3147@itemize @bullet
3148@item int8x8_t vshl_n_s8 (int8x8_t, const int)
3149@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3150@end itemize
3151
3152
3153@itemize @bullet
3154@item uint64x1_t vshl_n_u64 (uint64x1_t, const int)
3155@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3156@end itemize
3157
3158
3159@itemize @bullet
3160@item int64x1_t vshl_n_s64 (int64x1_t, const int)
3161@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3162@end itemize
3163
3164
3165@itemize @bullet
3166@item uint32x4_t vshlq_n_u32 (uint32x4_t, const int)
3167@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3168@end itemize
3169
3170
3171@itemize @bullet
3172@item uint16x8_t vshlq_n_u16 (uint16x8_t, const int)
3173@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3174@end itemize
3175
3176
3177@itemize @bullet
3178@item uint8x16_t vshlq_n_u8 (uint8x16_t, const int)
3179@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3180@end itemize
3181
3182
3183@itemize @bullet
3184@item int32x4_t vshlq_n_s32 (int32x4_t, const int)
3185@*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3186@end itemize
3187
3188
3189@itemize @bullet
3190@item int16x8_t vshlq_n_s16 (int16x8_t, const int)
3191@*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3192@end itemize
3193
3194
3195@itemize @bullet
3196@item int8x16_t vshlq_n_s8 (int8x16_t, const int)
3197@*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3198@end itemize
3199
3200
3201@itemize @bullet
3202@item uint64x2_t vshlq_n_u64 (uint64x2_t, const int)
3203@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3204@end itemize
3205
3206
3207@itemize @bullet
3208@item int64x2_t vshlq_n_s64 (int64x2_t, const int)
3209@*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3210@end itemize
3211
3212
3213@itemize @bullet
3214@item uint32x2_t vqshl_n_u32 (uint32x2_t, const int)
3215@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, #@var{0}}
3216@end itemize
3217
3218
3219@itemize @bullet
3220@item uint16x4_t vqshl_n_u16 (uint16x4_t, const int)
3221@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, #@var{0}}
3222@end itemize
3223
3224
3225@itemize @bullet
3226@item uint8x8_t vqshl_n_u8 (uint8x8_t, const int)
3227@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, #@var{0}}
3228@end itemize
3229
3230
3231@itemize @bullet
3232@item int32x2_t vqshl_n_s32 (int32x2_t, const int)
3233@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, #@var{0}}
3234@end itemize
3235
3236
3237@itemize @bullet
3238@item int16x4_t vqshl_n_s16 (int16x4_t, const int)
3239@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, #@var{0}}
3240@end itemize
3241
3242
3243@itemize @bullet
3244@item int8x8_t vqshl_n_s8 (int8x8_t, const int)
3245@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, #@var{0}}
3246@end itemize
3247
3248
3249@itemize @bullet
3250@item uint64x1_t vqshl_n_u64 (uint64x1_t, const int)
3251@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, #@var{0}}
3252@end itemize
3253
3254
3255@itemize @bullet
3256@item int64x1_t vqshl_n_s64 (int64x1_t, const int)
3257@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, #@var{0}}
3258@end itemize
3259
3260
3261@itemize @bullet
3262@item uint32x4_t vqshlq_n_u32 (uint32x4_t, const int)
3263@*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, #@var{0}}
3264@end itemize
3265
3266
3267@itemize @bullet
3268@item uint16x8_t vqshlq_n_u16 (uint16x8_t, const int)
3269@*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, #@var{0}}
3270@end itemize
3271
3272
3273@itemize @bullet
3274@item uint8x16_t vqshlq_n_u8 (uint8x16_t, const int)
3275@*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, #@var{0}}
3276@end itemize
3277
3278
3279@itemize @bullet
3280@item int32x4_t vqshlq_n_s32 (int32x4_t, const int)
3281@*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, #@var{0}}
3282@end itemize
3283
3284
3285@itemize @bullet
3286@item int16x8_t vqshlq_n_s16 (int16x8_t, const int)
3287@*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, #@var{0}}
3288@end itemize
3289
3290
3291@itemize @bullet
3292@item int8x16_t vqshlq_n_s8 (int8x16_t, const int)
3293@*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, #@var{0}}
3294@end itemize
3295
3296
3297@itemize @bullet
3298@item uint64x2_t vqshlq_n_u64 (uint64x2_t, const int)
3299@*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, #@var{0}}
3300@end itemize
3301
3302
3303@itemize @bullet
3304@item int64x2_t vqshlq_n_s64 (int64x2_t, const int)
3305@*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, #@var{0}}
3306@end itemize
3307
3308
3309@itemize @bullet
3310@item uint64x1_t vqshlu_n_s64 (int64x1_t, const int)
3311@*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{d0}, @var{d0}, #@var{0}}
3312@end itemize
3313
3314
3315@itemize @bullet
3316@item uint32x2_t vqshlu_n_s32 (int32x2_t, const int)
3317@*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{d0}, @var{d0}, #@var{0}}
3318@end itemize
3319
3320
3321@itemize @bullet
3322@item uint16x4_t vqshlu_n_s16 (int16x4_t, const int)
3323@*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{d0}, @var{d0}, #@var{0}}
3324@end itemize
3325
3326
3327@itemize @bullet
3328@item uint8x8_t vqshlu_n_s8 (int8x8_t, const int)
3329@*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{d0}, @var{d0}, #@var{0}}
3330@end itemize
3331
3332
3333@itemize @bullet
3334@item uint64x2_t vqshluq_n_s64 (int64x2_t, const int)
3335@*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{q0}, @var{q0}, #@var{0}}
3336@end itemize
3337
3338
3339@itemize @bullet
3340@item uint32x4_t vqshluq_n_s32 (int32x4_t, const int)
3341@*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{q0}, @var{q0}, #@var{0}}
3342@end itemize
3343
3344
3345@itemize @bullet
3346@item uint16x8_t vqshluq_n_s16 (int16x8_t, const int)
3347@*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{q0}, @var{q0}, #@var{0}}
3348@end itemize
3349
3350
3351@itemize @bullet
3352@item uint8x16_t vqshluq_n_s8 (int8x16_t, const int)
3353@*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{q0}, @var{q0}, #@var{0}}
3354@end itemize
3355
3356
3357@itemize @bullet
3358@item uint64x2_t vshll_n_u32 (uint32x2_t, const int)
3359@*@emph{Form of expected instruction(s):} @code{vshll.u32 @var{q0}, @var{d0}, #@var{0}}
3360@end itemize
3361
3362
3363@itemize @bullet
3364@item uint32x4_t vshll_n_u16 (uint16x4_t, const int)
3365@*@emph{Form of expected instruction(s):} @code{vshll.u16 @var{q0}, @var{d0}, #@var{0}}
3366@end itemize
3367
3368
3369@itemize @bullet
3370@item uint16x8_t vshll_n_u8 (uint8x8_t, const int)
3371@*@emph{Form of expected instruction(s):} @code{vshll.u8 @var{q0}, @var{d0}, #@var{0}}
3372@end itemize
3373
3374
3375@itemize @bullet
3376@item int64x2_t vshll_n_s32 (int32x2_t, const int)
3377@*@emph{Form of expected instruction(s):} @code{vshll.s32 @var{q0}, @var{d0}, #@var{0}}
3378@end itemize
3379
3380
3381@itemize @bullet
3382@item int32x4_t vshll_n_s16 (int16x4_t, const int)
3383@*@emph{Form of expected instruction(s):} @code{vshll.s16 @var{q0}, @var{d0}, #@var{0}}
3384@end itemize
3385
3386
3387@itemize @bullet
3388@item int16x8_t vshll_n_s8 (int8x8_t, const int)
3389@*@emph{Form of expected instruction(s):} @code{vshll.s8 @var{q0}, @var{d0}, #@var{0}}
3390@end itemize
3391
3392
3393
3394
3395@subsubsection Vector shift right by constant
3396
3397@itemize @bullet
3398@item uint32x2_t vshr_n_u32 (uint32x2_t, const int)
3399@*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{d0}, @var{d0}, #@var{0}}
3400@end itemize
3401
3402
3403@itemize @bullet
3404@item uint16x4_t vshr_n_u16 (uint16x4_t, const int)
3405@*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{d0}, @var{d0}, #@var{0}}
3406@end itemize
3407
3408
3409@itemize @bullet
3410@item uint8x8_t vshr_n_u8 (uint8x8_t, const int)
3411@*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{d0}, @var{d0}, #@var{0}}
3412@end itemize
3413
3414
3415@itemize @bullet
3416@item int32x2_t vshr_n_s32 (int32x2_t, const int)
3417@*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{d0}, @var{d0}, #@var{0}}
3418@end itemize
3419
3420
3421@itemize @bullet
3422@item int16x4_t vshr_n_s16 (int16x4_t, const int)
3423@*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{d0}, @var{d0}, #@var{0}}
3424@end itemize
3425
3426
3427@itemize @bullet
3428@item int8x8_t vshr_n_s8 (int8x8_t, const int)
3429@*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{d0}, @var{d0}, #@var{0}}
3430@end itemize
3431
3432
3433@itemize @bullet
3434@item uint64x1_t vshr_n_u64 (uint64x1_t, const int)
3435@*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{d0}, @var{d0}, #@var{0}}
3436@end itemize
3437
3438
3439@itemize @bullet
3440@item int64x1_t vshr_n_s64 (int64x1_t, const int)
3441@*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{d0}, @var{d0}, #@var{0}}
3442@end itemize
3443
3444
3445@itemize @bullet
3446@item uint32x4_t vshrq_n_u32 (uint32x4_t, const int)
3447@*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{q0}, @var{q0}, #@var{0}}
3448@end itemize
3449
3450
3451@itemize @bullet
3452@item uint16x8_t vshrq_n_u16 (uint16x8_t, const int)
3453@*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{q0}, @var{q0}, #@var{0}}
3454@end itemize
3455
3456
3457@itemize @bullet
3458@item uint8x16_t vshrq_n_u8 (uint8x16_t, const int)
3459@*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{q0}, @var{q0}, #@var{0}}
3460@end itemize
3461
3462
3463@itemize @bullet
3464@item int32x4_t vshrq_n_s32 (int32x4_t, const int)
3465@*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{q0}, @var{q0}, #@var{0}}
3466@end itemize
3467
3468
3469@itemize @bullet
3470@item int16x8_t vshrq_n_s16 (int16x8_t, const int)
3471@*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{q0}, @var{q0}, #@var{0}}
3472@end itemize
3473
3474
3475@itemize @bullet
3476@item int8x16_t vshrq_n_s8 (int8x16_t, const int)
3477@*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{q0}, @var{q0}, #@var{0}}
3478@end itemize
3479
3480
3481@itemize @bullet
3482@item uint64x2_t vshrq_n_u64 (uint64x2_t, const int)
3483@*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{q0}, @var{q0}, #@var{0}}
3484@end itemize
3485
3486
3487@itemize @bullet
3488@item int64x2_t vshrq_n_s64 (int64x2_t, const int)
3489@*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{q0}, @var{q0}, #@var{0}}
3490@end itemize
3491
3492
3493@itemize @bullet
3494@item uint32x2_t vrshr_n_u32 (uint32x2_t, const int)
3495@*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{d0}, @var{d0}, #@var{0}}
3496@end itemize
3497
3498
3499@itemize @bullet
3500@item uint16x4_t vrshr_n_u16 (uint16x4_t, const int)
3501@*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{d0}, @var{d0}, #@var{0}}
3502@end itemize
3503
3504
3505@itemize @bullet
3506@item uint8x8_t vrshr_n_u8 (uint8x8_t, const int)
3507@*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{d0}, @var{d0}, #@var{0}}
3508@end itemize
3509
3510
3511@itemize @bullet
3512@item int32x2_t vrshr_n_s32 (int32x2_t, const int)
3513@*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{d0}, @var{d0}, #@var{0}}
3514@end itemize
3515
3516
3517@itemize @bullet
3518@item int16x4_t vrshr_n_s16 (int16x4_t, const int)
3519@*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{d0}, @var{d0}, #@var{0}}
3520@end itemize
3521
3522
3523@itemize @bullet
3524@item int8x8_t vrshr_n_s8 (int8x8_t, const int)
3525@*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{d0}, @var{d0}, #@var{0}}
3526@end itemize
3527
3528
3529@itemize @bullet
3530@item uint64x1_t vrshr_n_u64 (uint64x1_t, const int)
3531@*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{d0}, @var{d0}, #@var{0}}
3532@end itemize
3533
3534
3535@itemize @bullet
3536@item int64x1_t vrshr_n_s64 (int64x1_t, const int)
3537@*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{d0}, @var{d0}, #@var{0}}
3538@end itemize
3539
3540
3541@itemize @bullet
3542@item uint32x4_t vrshrq_n_u32 (uint32x4_t, const int)
3543@*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{q0}, @var{q0}, #@var{0}}
3544@end itemize
3545
3546
3547@itemize @bullet
3548@item uint16x8_t vrshrq_n_u16 (uint16x8_t, const int)
3549@*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{q0}, @var{q0}, #@var{0}}
3550@end itemize
3551
3552
3553@itemize @bullet
3554@item uint8x16_t vrshrq_n_u8 (uint8x16_t, const int)
3555@*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{q0}, @var{q0}, #@var{0}}
3556@end itemize
3557
3558
3559@itemize @bullet
3560@item int32x4_t vrshrq_n_s32 (int32x4_t, const int)
3561@*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{q0}, @var{q0}, #@var{0}}
3562@end itemize
3563
3564
3565@itemize @bullet
3566@item int16x8_t vrshrq_n_s16 (int16x8_t, const int)
3567@*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{q0}, @var{q0}, #@var{0}}
3568@end itemize
3569
3570
3571@itemize @bullet
3572@item int8x16_t vrshrq_n_s8 (int8x16_t, const int)
3573@*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{q0}, @var{q0}, #@var{0}}
3574@end itemize
3575
3576
3577@itemize @bullet
3578@item uint64x2_t vrshrq_n_u64 (uint64x2_t, const int)
3579@*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{q0}, @var{q0}, #@var{0}}
3580@end itemize
3581
3582
3583@itemize @bullet
3584@item int64x2_t vrshrq_n_s64 (int64x2_t, const int)
3585@*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{q0}, @var{q0}, #@var{0}}
3586@end itemize
3587
3588
3589@itemize @bullet
3590@item uint32x2_t vshrn_n_u64 (uint64x2_t, const int)
3591@*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3592@end itemize
3593
3594
3595@itemize @bullet
3596@item uint16x4_t vshrn_n_u32 (uint32x4_t, const int)
3597@*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3598@end itemize
3599
3600
3601@itemize @bullet
3602@item uint8x8_t vshrn_n_u16 (uint16x8_t, const int)
3603@*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3604@end itemize
3605
3606
3607@itemize @bullet
3608@item int32x2_t vshrn_n_s64 (int64x2_t, const int)
3609@*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3610@end itemize
3611
3612
3613@itemize @bullet
3614@item int16x4_t vshrn_n_s32 (int32x4_t, const int)
3615@*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3616@end itemize
3617
3618
3619@itemize @bullet
3620@item int8x8_t vshrn_n_s16 (int16x8_t, const int)
3621@*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3622@end itemize
3623
3624
3625@itemize @bullet
3626@item uint32x2_t vrshrn_n_u64 (uint64x2_t, const int)
3627@*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3628@end itemize
3629
3630
3631@itemize @bullet
3632@item uint16x4_t vrshrn_n_u32 (uint32x4_t, const int)
3633@*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3634@end itemize
3635
3636
3637@itemize @bullet
3638@item uint8x8_t vrshrn_n_u16 (uint16x8_t, const int)
3639@*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3640@end itemize
3641
3642
3643@itemize @bullet
3644@item int32x2_t vrshrn_n_s64 (int64x2_t, const int)
3645@*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3646@end itemize
3647
3648
3649@itemize @bullet
3650@item int16x4_t vrshrn_n_s32 (int32x4_t, const int)
3651@*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3652@end itemize
3653
3654
3655@itemize @bullet
3656@item int8x8_t vrshrn_n_s16 (int16x8_t, const int)
3657@*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3658@end itemize
3659
3660
3661@itemize @bullet
3662@item uint32x2_t vqshrn_n_u64 (uint64x2_t, const int)
3663@*@emph{Form of expected instruction(s):} @code{vqshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3664@end itemize
3665
3666
3667@itemize @bullet
3668@item uint16x4_t vqshrn_n_u32 (uint32x4_t, const int)
3669@*@emph{Form of expected instruction(s):} @code{vqshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3670@end itemize
3671
3672
3673@itemize @bullet
3674@item uint8x8_t vqshrn_n_u16 (uint16x8_t, const int)
3675@*@emph{Form of expected instruction(s):} @code{vqshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3676@end itemize
3677
3678
3679@itemize @bullet
3680@item int32x2_t vqshrn_n_s64 (int64x2_t, const int)
3681@*@emph{Form of expected instruction(s):} @code{vqshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3682@end itemize
3683
3684
3685@itemize @bullet
3686@item int16x4_t vqshrn_n_s32 (int32x4_t, const int)
3687@*@emph{Form of expected instruction(s):} @code{vqshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3688@end itemize
3689
3690
3691@itemize @bullet
3692@item int8x8_t vqshrn_n_s16 (int16x8_t, const int)
3693@*@emph{Form of expected instruction(s):} @code{vqshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3694@end itemize
3695
3696
3697@itemize @bullet
3698@item uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int)
3699@*@emph{Form of expected instruction(s):} @code{vqrshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3700@end itemize
3701
3702
3703@itemize @bullet
3704@item uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int)
3705@*@emph{Form of expected instruction(s):} @code{vqrshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3706@end itemize
3707
3708
3709@itemize @bullet
3710@item uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int)
3711@*@emph{Form of expected instruction(s):} @code{vqrshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3712@end itemize
3713
3714
3715@itemize @bullet
3716@item int32x2_t vqrshrn_n_s64 (int64x2_t, const int)
3717@*@emph{Form of expected instruction(s):} @code{vqrshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3718@end itemize
3719
3720
3721@itemize @bullet
3722@item int16x4_t vqrshrn_n_s32 (int32x4_t, const int)
3723@*@emph{Form of expected instruction(s):} @code{vqrshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3724@end itemize
3725
3726
3727@itemize @bullet
3728@item int8x8_t vqrshrn_n_s16 (int16x8_t, const int)
3729@*@emph{Form of expected instruction(s):} @code{vqrshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3730@end itemize
3731
3732
3733@itemize @bullet
3734@item uint32x2_t vqshrun_n_s64 (int64x2_t, const int)
3735@*@emph{Form of expected instruction(s):} @code{vqshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3736@end itemize
3737
3738
3739@itemize @bullet
3740@item uint16x4_t vqshrun_n_s32 (int32x4_t, const int)
3741@*@emph{Form of expected instruction(s):} @code{vqshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3742@end itemize
3743
3744
3745@itemize @bullet
3746@item uint8x8_t vqshrun_n_s16 (int16x8_t, const int)
3747@*@emph{Form of expected instruction(s):} @code{vqshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3748@end itemize
3749
3750
3751@itemize @bullet
3752@item uint32x2_t vqrshrun_n_s64 (int64x2_t, const int)
3753@*@emph{Form of expected instruction(s):} @code{vqrshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3754@end itemize
3755
3756
3757@itemize @bullet
3758@item uint16x4_t vqrshrun_n_s32 (int32x4_t, const int)
3759@*@emph{Form of expected instruction(s):} @code{vqrshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3760@end itemize
3761
3762
3763@itemize @bullet
3764@item uint8x8_t vqrshrun_n_s16 (int16x8_t, const int)
3765@*@emph{Form of expected instruction(s):} @code{vqrshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3766@end itemize
3767
3768
3769
3770
3771@subsubsection Vector shift right by constant and accumulate
3772
3773@itemize @bullet
3774@item uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3775@*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{d0}, @var{d0}, #@var{0}}
3776@end itemize
3777
3778
3779@itemize @bullet
3780@item uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3781@*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{d0}, @var{d0}, #@var{0}}
3782@end itemize
3783
3784
3785@itemize @bullet
3786@item uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3787@*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{d0}, @var{d0}, #@var{0}}
3788@end itemize
3789
3790
3791@itemize @bullet
3792@item int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int)
3793@*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{d0}, @var{d0}, #@var{0}}
3794@end itemize
3795
3796
3797@itemize @bullet
3798@item int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int)
3799@*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{d0}, @var{d0}, #@var{0}}
3800@end itemize
3801
3802
3803@itemize @bullet
3804@item int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int)
3805@*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{d0}, @var{d0}, #@var{0}}
3806@end itemize
3807
3808
3809@itemize @bullet
3810@item uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3811@*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{d0}, @var{d0}, #@var{0}}
3812@end itemize
3813
3814
3815@itemize @bullet
3816@item int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int)
3817@*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{d0}, @var{d0}, #@var{0}}
3818@end itemize
3819
3820
3821@itemize @bullet
3822@item uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3823@*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{q0}, @var{q0}, #@var{0}}
3824@end itemize
3825
3826
3827@itemize @bullet
3828@item uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3829@*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{q0}, @var{q0}, #@var{0}}
3830@end itemize
3831
3832
3833@itemize @bullet
3834@item uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3835@*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{q0}, @var{q0}, #@var{0}}
3836@end itemize
3837
3838
3839@itemize @bullet
3840@item int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int)
3841@*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{q0}, @var{q0}, #@var{0}}
3842@end itemize
3843
3844
3845@itemize @bullet
3846@item int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int)
3847@*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{q0}, @var{q0}, #@var{0}}
3848@end itemize
3849
3850
3851@itemize @bullet
3852@item int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int)
3853@*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{q0}, @var{q0}, #@var{0}}
3854@end itemize
3855
3856
3857@itemize @bullet
3858@item uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3859@*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{q0}, @var{q0}, #@var{0}}
3860@end itemize
3861
3862
3863@itemize @bullet
3864@item int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int)
3865@*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{q0}, @var{q0}, #@var{0}}
3866@end itemize
3867
3868
3869@itemize @bullet
3870@item uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3871@*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{d0}, @var{d0}, #@var{0}}
3872@end itemize
3873
3874
3875@itemize @bullet
3876@item uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3877@*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{d0}, @var{d0}, #@var{0}}
3878@end itemize
3879
3880
3881@itemize @bullet
3882@item uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3883@*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{d0}, @var{d0}, #@var{0}}
3884@end itemize
3885
3886
3887@itemize @bullet
3888@item int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int)
3889@*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{d0}, @var{d0}, #@var{0}}
3890@end itemize
3891
3892
3893@itemize @bullet
3894@item int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int)
3895@*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{d0}, @var{d0}, #@var{0}}
3896@end itemize
3897
3898
3899@itemize @bullet
3900@item int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int)
3901@*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{d0}, @var{d0}, #@var{0}}
3902@end itemize
3903
3904
3905@itemize @bullet
3906@item uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3907@*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{d0}, @var{d0}, #@var{0}}
3908@end itemize
3909
3910
3911@itemize @bullet
3912@item int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int)
3913@*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{d0}, @var{d0}, #@var{0}}
3914@end itemize
3915
3916
3917@itemize @bullet
3918@item uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3919@*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{q0}, @var{q0}, #@var{0}}
3920@end itemize
3921
3922
3923@itemize @bullet
3924@item uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3925@*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{q0}, @var{q0}, #@var{0}}
3926@end itemize
3927
3928
3929@itemize @bullet
3930@item uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3931@*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{q0}, @var{q0}, #@var{0}}
3932@end itemize
3933
3934
3935@itemize @bullet
3936@item int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int)
3937@*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{q0}, @var{q0}, #@var{0}}
3938@end itemize
3939
3940
3941@itemize @bullet
3942@item int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int)
3943@*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{q0}, @var{q0}, #@var{0}}
3944@end itemize
3945
3946
3947@itemize @bullet
3948@item int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int)
3949@*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{q0}, @var{q0}, #@var{0}}
3950@end itemize
3951
3952
3953@itemize @bullet
3954@item uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3955@*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{q0}, @var{q0}, #@var{0}}
3956@end itemize
3957
3958
3959@itemize @bullet
3960@item int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int)
3961@*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{q0}, @var{q0}, #@var{0}}
3962@end itemize
3963
3964
3965
3966
3967@subsubsection Vector shift right and insert
3968
3969@itemize @bullet
3970@item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int)
3971@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
3972@end itemize
3973
3974
3975@itemize @bullet
3976@item uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int)
3977@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
3978@end itemize
3979
3980
3981@itemize @bullet
3982@item uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int)
3983@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
3984@end itemize
3985
3986
3987@itemize @bullet
3988@item int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int)
3989@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
3990@end itemize
3991
3992
3993@itemize @bullet
3994@item int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int)
3995@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
3996@end itemize
3997
3998
3999@itemize @bullet
4000@item int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int)
4001@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4002@end itemize
4003
4004
4005@itemize @bullet
4006@item uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int)
4007@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4008@end itemize
4009
4010
4011@itemize @bullet
4012@item int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int)
4013@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4014@end itemize
4015
4016
4017@itemize @bullet
4018@item poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int)
4019@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4020@end itemize
4021
4022
4023@itemize @bullet
4024@item poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int)
4025@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4026@end itemize
4027
4028
4029@itemize @bullet
4030@item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int)
4031@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4032@end itemize
4033
4034
4035@itemize @bullet
4036@item uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int)
4037@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4038@end itemize
4039
4040
4041@itemize @bullet
4042@item uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int)
4043@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4044@end itemize
4045
4046
4047@itemize @bullet
4048@item int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int)
4049@*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4050@end itemize
4051
4052
4053@itemize @bullet
4054@item int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int)
4055@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4056@end itemize
4057
4058
4059@itemize @bullet
4060@item int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int)
4061@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4062@end itemize
4063
4064
4065@itemize @bullet
4066@item uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int)
4067@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4068@end itemize
4069
4070
4071@itemize @bullet
4072@item int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int)
4073@*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4074@end itemize
4075
4076
4077@itemize @bullet
4078@item poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int)
4079@*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4080@end itemize
4081
4082
4083@itemize @bullet
4084@item poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int)
4085@*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4086@end itemize
4087
4088
4089
4090
4091@subsubsection Vector shift left and insert
4092
4093@itemize @bullet
4094@item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int)
4095@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4096@end itemize
4097
4098
4099@itemize @bullet
4100@item uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int)
4101@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4102@end itemize
4103
4104
4105@itemize @bullet
4106@item uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int)
4107@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4108@end itemize
4109
4110
4111@itemize @bullet
4112@item int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int)
4113@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4114@end itemize
4115
4116
4117@itemize @bullet
4118@item int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int)
4119@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4120@end itemize
4121
4122
4123@itemize @bullet
4124@item int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int)
4125@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4126@end itemize
4127
4128
4129@itemize @bullet
4130@item uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int)
4131@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4132@end itemize
4133
4134
4135@itemize @bullet
4136@item int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int)
4137@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4138@end itemize
4139
4140
4141@itemize @bullet
4142@item poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int)
4143@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4144@end itemize
4145
4146
4147@itemize @bullet
4148@item poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int)
4149@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4150@end itemize
4151
4152
4153@itemize @bullet
4154@item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int)
4155@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4156@end itemize
4157
4158
4159@itemize @bullet
4160@item uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int)
4161@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4162@end itemize
4163
4164
4165@itemize @bullet
4166@item uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int)
4167@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4168@end itemize
4169
4170
4171@itemize @bullet
4172@item int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int)
4173@*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4174@end itemize
4175
4176
4177@itemize @bullet
4178@item int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int)
4179@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4180@end itemize
4181
4182
4183@itemize @bullet
4184@item int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int)
4185@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4186@end itemize
4187
4188
4189@itemize @bullet
4190@item uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int)
4191@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4192@end itemize
4193
4194
4195@itemize @bullet
4196@item int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int)
4197@*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4198@end itemize
4199
4200
4201@itemize @bullet
4202@item poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int)
4203@*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4204@end itemize
4205
4206
4207@itemize @bullet
4208@item poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int)
4209@*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4210@end itemize
4211
4212
4213
4214
4215@subsubsection Absolute value
4216
4217@itemize @bullet
4218@item float32x2_t vabs_f32 (float32x2_t)
4219@*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{d0}, @var{d0}}
4220@end itemize
4221
4222
4223@itemize @bullet
4224@item int32x2_t vabs_s32 (int32x2_t)
4225@*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{d0}, @var{d0}}
4226@end itemize
4227
4228
4229@itemize @bullet
4230@item int16x4_t vabs_s16 (int16x4_t)
4231@*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{d0}, @var{d0}}
4232@end itemize
4233
4234
4235@itemize @bullet
4236@item int8x8_t vabs_s8 (int8x8_t)
4237@*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{d0}, @var{d0}}
4238@end itemize
4239
4240
4241@itemize @bullet
4242@item float32x4_t vabsq_f32 (float32x4_t)
4243@*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{q0}, @var{q0}}
4244@end itemize
4245
4246
4247@itemize @bullet
4248@item int32x4_t vabsq_s32 (int32x4_t)
4249@*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{q0}, @var{q0}}
4250@end itemize
4251
4252
4253@itemize @bullet
4254@item int16x8_t vabsq_s16 (int16x8_t)
4255@*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{q0}, @var{q0}}
4256@end itemize
4257
4258
4259@itemize @bullet
4260@item int8x16_t vabsq_s8 (int8x16_t)
4261@*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{q0}, @var{q0}}
4262@end itemize
4263
4264
4265@itemize @bullet
4266@item int32x2_t vqabs_s32 (int32x2_t)
4267@*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{d0}, @var{d0}}
4268@end itemize
4269
4270
4271@itemize @bullet
4272@item int16x4_t vqabs_s16 (int16x4_t)
4273@*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{d0}, @var{d0}}
4274@end itemize
4275
4276
4277@itemize @bullet
4278@item int8x8_t vqabs_s8 (int8x8_t)
4279@*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{d0}, @var{d0}}
4280@end itemize
4281
4282
4283@itemize @bullet
4284@item int32x4_t vqabsq_s32 (int32x4_t)
4285@*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{q0}, @var{q0}}
4286@end itemize
4287
4288
4289@itemize @bullet
4290@item int16x8_t vqabsq_s16 (int16x8_t)
4291@*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{q0}, @var{q0}}
4292@end itemize
4293
4294
4295@itemize @bullet
4296@item int8x16_t vqabsq_s8 (int8x16_t)
4297@*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{q0}, @var{q0}}
4298@end itemize
4299
4300
4301
4302
4303@subsubsection Negation
4304
4305@itemize @bullet
4306@item float32x2_t vneg_f32 (float32x2_t)
4307@*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{d0}, @var{d0}}
4308@end itemize
4309
4310
4311@itemize @bullet
4312@item int32x2_t vneg_s32 (int32x2_t)
4313@*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{d0}, @var{d0}}
4314@end itemize
4315
4316
4317@itemize @bullet
4318@item int16x4_t vneg_s16 (int16x4_t)
4319@*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{d0}, @var{d0}}
4320@end itemize
4321
4322
4323@itemize @bullet
4324@item int8x8_t vneg_s8 (int8x8_t)
4325@*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{d0}, @var{d0}}
4326@end itemize
4327
4328
4329@itemize @bullet
4330@item float32x4_t vnegq_f32 (float32x4_t)
4331@*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{q0}, @var{q0}}
4332@end itemize
4333
4334
4335@itemize @bullet
4336@item int32x4_t vnegq_s32 (int32x4_t)
4337@*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{q0}, @var{q0}}
4338@end itemize
4339
4340
4341@itemize @bullet
4342@item int16x8_t vnegq_s16 (int16x8_t)
4343@*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{q0}, @var{q0}}
4344@end itemize
4345
4346
4347@itemize @bullet
4348@item int8x16_t vnegq_s8 (int8x16_t)
4349@*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{q0}, @var{q0}}
4350@end itemize
4351
4352
4353@itemize @bullet
4354@item int32x2_t vqneg_s32 (int32x2_t)
4355@*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{d0}, @var{d0}}
4356@end itemize
4357
4358
4359@itemize @bullet
4360@item int16x4_t vqneg_s16 (int16x4_t)
4361@*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{d0}, @var{d0}}
4362@end itemize
4363
4364
4365@itemize @bullet
4366@item int8x8_t vqneg_s8 (int8x8_t)
4367@*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{d0}, @var{d0}}
4368@end itemize
4369
4370
4371@itemize @bullet
4372@item int32x4_t vqnegq_s32 (int32x4_t)
4373@*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{q0}, @var{q0}}
4374@end itemize
4375
4376
4377@itemize @bullet
4378@item int16x8_t vqnegq_s16 (int16x8_t)
4379@*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{q0}, @var{q0}}
4380@end itemize
4381
4382
4383@itemize @bullet
4384@item int8x16_t vqnegq_s8 (int8x16_t)
4385@*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{q0}, @var{q0}}
4386@end itemize
4387
4388
4389
4390
4391@subsubsection Bitwise not
4392
4393@itemize @bullet
4394@item uint32x2_t vmvn_u32 (uint32x2_t)
4395@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4396@end itemize
4397
4398
4399@itemize @bullet
4400@item uint16x4_t vmvn_u16 (uint16x4_t)
4401@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4402@end itemize
4403
4404
4405@itemize @bullet
4406@item uint8x8_t vmvn_u8 (uint8x8_t)
4407@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4408@end itemize
4409
4410
4411@itemize @bullet
4412@item int32x2_t vmvn_s32 (int32x2_t)
4413@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4414@end itemize
4415
4416
4417@itemize @bullet
4418@item int16x4_t vmvn_s16 (int16x4_t)
4419@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4420@end itemize
4421
4422
4423@itemize @bullet
4424@item int8x8_t vmvn_s8 (int8x8_t)
4425@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4426@end itemize
4427
4428
4429@itemize @bullet
4430@item poly8x8_t vmvn_p8 (poly8x8_t)
4431@*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4432@end itemize
4433
4434
4435@itemize @bullet
4436@item uint32x4_t vmvnq_u32 (uint32x4_t)
4437@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4438@end itemize
4439
4440
4441@itemize @bullet
4442@item uint16x8_t vmvnq_u16 (uint16x8_t)
4443@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4444@end itemize
4445
4446
4447@itemize @bullet
4448@item uint8x16_t vmvnq_u8 (uint8x16_t)
4449@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4450@end itemize
4451
4452
4453@itemize @bullet
4454@item int32x4_t vmvnq_s32 (int32x4_t)
4455@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4456@end itemize
4457
4458
4459@itemize @bullet
4460@item int16x8_t vmvnq_s16 (int16x8_t)
4461@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4462@end itemize
4463
4464
4465@itemize @bullet
4466@item int8x16_t vmvnq_s8 (int8x16_t)
4467@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4468@end itemize
4469
4470
4471@itemize @bullet
4472@item poly8x16_t vmvnq_p8 (poly8x16_t)
4473@*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4474@end itemize
4475
4476
4477
4478
4479@subsubsection Count leading sign bits
4480
4481@itemize @bullet
4482@item int32x2_t vcls_s32 (int32x2_t)
4483@*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{d0}, @var{d0}}
4484@end itemize
4485
4486
4487@itemize @bullet
4488@item int16x4_t vcls_s16 (int16x4_t)
4489@*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{d0}, @var{d0}}
4490@end itemize
4491
4492
4493@itemize @bullet
4494@item int8x8_t vcls_s8 (int8x8_t)
4495@*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{d0}, @var{d0}}
4496@end itemize
4497
4498
4499@itemize @bullet
4500@item int32x4_t vclsq_s32 (int32x4_t)
4501@*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{q0}, @var{q0}}
4502@end itemize
4503
4504
4505@itemize @bullet
4506@item int16x8_t vclsq_s16 (int16x8_t)
4507@*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{q0}, @var{q0}}
4508@end itemize
4509
4510
4511@itemize @bullet
4512@item int8x16_t vclsq_s8 (int8x16_t)
4513@*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{q0}, @var{q0}}
4514@end itemize
4515
4516
4517
4518
4519@subsubsection Count leading zeros
4520
4521@itemize @bullet
4522@item uint32x2_t vclz_u32 (uint32x2_t)
4523@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4524@end itemize
4525
4526
4527@itemize @bullet
4528@item uint16x4_t vclz_u16 (uint16x4_t)
4529@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4530@end itemize
4531
4532
4533@itemize @bullet
4534@item uint8x8_t vclz_u8 (uint8x8_t)
4535@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4536@end itemize
4537
4538
4539@itemize @bullet
4540@item int32x2_t vclz_s32 (int32x2_t)
4541@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4542@end itemize
4543
4544
4545@itemize @bullet
4546@item int16x4_t vclz_s16 (int16x4_t)
4547@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4548@end itemize
4549
4550
4551@itemize @bullet
4552@item int8x8_t vclz_s8 (int8x8_t)
4553@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4554@end itemize
4555
4556
4557@itemize @bullet
4558@item uint32x4_t vclzq_u32 (uint32x4_t)
4559@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4560@end itemize
4561
4562
4563@itemize @bullet
4564@item uint16x8_t vclzq_u16 (uint16x8_t)
4565@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4566@end itemize
4567
4568
4569@itemize @bullet
4570@item uint8x16_t vclzq_u8 (uint8x16_t)
4571@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4572@end itemize
4573
4574
4575@itemize @bullet
4576@item int32x4_t vclzq_s32 (int32x4_t)
4577@*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4578@end itemize
4579
4580
4581@itemize @bullet
4582@item int16x8_t vclzq_s16 (int16x8_t)
4583@*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4584@end itemize
4585
4586
4587@itemize @bullet
4588@item int8x16_t vclzq_s8 (int8x16_t)
4589@*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4590@end itemize
4591
4592
4593
4594
4595@subsubsection Count number of set bits
4596
4597@itemize @bullet
4598@item uint8x8_t vcnt_u8 (uint8x8_t)
4599@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4600@end itemize
4601
4602
4603@itemize @bullet
4604@item int8x8_t vcnt_s8 (int8x8_t)
4605@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4606@end itemize
4607
4608
4609@itemize @bullet
4610@item poly8x8_t vcnt_p8 (poly8x8_t)
4611@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4612@end itemize
4613
4614
4615@itemize @bullet
4616@item uint8x16_t vcntq_u8 (uint8x16_t)
4617@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4618@end itemize
4619
4620
4621@itemize @bullet
4622@item int8x16_t vcntq_s8 (int8x16_t)
4623@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4624@end itemize
4625
4626
4627@itemize @bullet
4628@item poly8x16_t vcntq_p8 (poly8x16_t)
4629@*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4630@end itemize
4631
4632
4633
4634
4635@subsubsection Reciprocal estimate
4636
4637@itemize @bullet
4638@item float32x2_t vrecpe_f32 (float32x2_t)
4639@*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{d0}, @var{d0}}
4640@end itemize
4641
4642
4643@itemize @bullet
4644@item uint32x2_t vrecpe_u32 (uint32x2_t)
4645@*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{d0}, @var{d0}}
4646@end itemize
4647
4648
4649@itemize @bullet
4650@item float32x4_t vrecpeq_f32 (float32x4_t)
4651@*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{q0}, @var{q0}}
4652@end itemize
4653
4654
4655@itemize @bullet
4656@item uint32x4_t vrecpeq_u32 (uint32x4_t)
4657@*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{q0}, @var{q0}}
4658@end itemize
4659
4660
4661
4662
4663@subsubsection Reciprocal square-root estimate
4664
4665@itemize @bullet
4666@item float32x2_t vrsqrte_f32 (float32x2_t)
4667@*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{d0}, @var{d0}}
4668@end itemize
4669
4670
4671@itemize @bullet
4672@item uint32x2_t vrsqrte_u32 (uint32x2_t)
4673@*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{d0}, @var{d0}}
4674@end itemize
4675
4676
4677@itemize @bullet
4678@item float32x4_t vrsqrteq_f32 (float32x4_t)
4679@*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{q0}, @var{q0}}
4680@end itemize
4681
4682
4683@itemize @bullet
4684@item uint32x4_t vrsqrteq_u32 (uint32x4_t)
4685@*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{q0}, @var{q0}}
4686@end itemize
4687
4688
4689
4690
4691@subsubsection Get lanes from a vector
4692
4693@itemize @bullet
4694@item uint32_t vget_lane_u32 (uint32x2_t, const int)
4695@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4696@end itemize
4697
4698
4699@itemize @bullet
4700@item uint16_t vget_lane_u16 (uint16x4_t, const int)
4701@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4702@end itemize
4703
4704
4705@itemize @bullet
4706@item uint8_t vget_lane_u8 (uint8x8_t, const int)
4707@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4708@end itemize
4709
4710
4711@itemize @bullet
4712@item int32_t vget_lane_s32 (int32x2_t, const int)
4713@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4714@end itemize
4715
4716
4717@itemize @bullet
4718@item int16_t vget_lane_s16 (int16x4_t, const int)
4719@*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4720@end itemize
4721
4722
4723@itemize @bullet
4724@item int8_t vget_lane_s8 (int8x8_t, const int)
4725@*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4726@end itemize
4727
4728
4729@itemize @bullet
4730@item float32_t vget_lane_f32 (float32x2_t, const int)
4731@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4732@end itemize
4733
4734
4735@itemize @bullet
4736@item poly16_t vget_lane_p16 (poly16x4_t, const int)
4737@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4738@end itemize
4739
4740
4741@itemize @bullet
4742@item poly8_t vget_lane_p8 (poly8x8_t, const int)
4743@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4744@end itemize
4745
4746
4747@itemize @bullet
4748@item uint64_t vget_lane_u64 (uint64x1_t, const int)
4749@end itemize
4750
4751
4752@itemize @bullet
4753@item int64_t vget_lane_s64 (int64x1_t, const int)
4754@end itemize
4755
4756
4757@itemize @bullet
4758@item uint32_t vgetq_lane_u32 (uint32x4_t, const int)
4759@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4760@end itemize
4761
4762
4763@itemize @bullet
4764@item uint16_t vgetq_lane_u16 (uint16x8_t, const int)
4765@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4766@end itemize
4767
4768
4769@itemize @bullet
4770@item uint8_t vgetq_lane_u8 (uint8x16_t, const int)
4771@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4772@end itemize
4773
4774
4775@itemize @bullet
4776@item int32_t vgetq_lane_s32 (int32x4_t, const int)
4777@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4778@end itemize
4779
4780
4781@itemize @bullet
4782@item int16_t vgetq_lane_s16 (int16x8_t, const int)
4783@*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4784@end itemize
4785
4786
4787@itemize @bullet
4788@item int8_t vgetq_lane_s8 (int8x16_t, const int)
4789@*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4790@end itemize
4791
4792
4793@itemize @bullet
4794@item float32_t vgetq_lane_f32 (float32x4_t, const int)
4795@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4796@end itemize
4797
4798
4799@itemize @bullet
4800@item poly16_t vgetq_lane_p16 (poly16x8_t, const int)
4801@*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4802@end itemize
4803
4804
4805@itemize @bullet
4806@item poly8_t vgetq_lane_p8 (poly8x16_t, const int)
4807@*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4808@end itemize
4809
4810
4811@itemize @bullet
4812@item uint64_t vgetq_lane_u64 (uint64x2_t, const int)
4813@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4814@end itemize
4815
4816
4817@itemize @bullet
4818@item int64_t vgetq_lane_s64 (int64x2_t, const int)
4819@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4820@end itemize
4821
4822
4823
4824
4825@subsubsection Set lanes in a vector
4826
4827@itemize @bullet
4828@item uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int)
4829@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4830@end itemize
4831
4832
4833@itemize @bullet
4834@item uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int)
4835@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4836@end itemize
4837
4838
4839@itemize @bullet
4840@item uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int)
4841@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4842@end itemize
4843
4844
4845@itemize @bullet
4846@item int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int)
4847@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4848@end itemize
4849
4850
4851@itemize @bullet
4852@item int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int)
4853@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4854@end itemize
4855
4856
4857@itemize @bullet
4858@item int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int)
4859@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4860@end itemize
4861
4862
4863@itemize @bullet
4864@item float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int)
4865@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4866@end itemize
4867
4868
4869@itemize @bullet
4870@item poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int)
4871@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4872@end itemize
4873
4874
4875@itemize @bullet
4876@item poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int)
4877@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4878@end itemize
4879
4880
4881@itemize @bullet
4882@item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
4883@end itemize
4884
4885
4886@itemize @bullet
4887@item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
4888@end itemize
4889
4890
4891@itemize @bullet
4892@item uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int)
4893@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4894@end itemize
4895
4896
4897@itemize @bullet
4898@item uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int)
4899@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4900@end itemize
4901
4902
4903@itemize @bullet
4904@item uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int)
4905@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4906@end itemize
4907
4908
4909@itemize @bullet
4910@item int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int)
4911@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4912@end itemize
4913
4914
4915@itemize @bullet
4916@item int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int)
4917@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4918@end itemize
4919
4920
4921@itemize @bullet
4922@item int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int)
4923@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4924@end itemize
4925
4926
4927@itemize @bullet
4928@item float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int)
4929@*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4930@end itemize
4931
4932
4933@itemize @bullet
4934@item poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int)
4935@*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4936@end itemize
4937
4938
4939@itemize @bullet
4940@item poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int)
4941@*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4942@end itemize
4943
4944
4945@itemize @bullet
4946@item uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int)
4947@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4948@end itemize
4949
4950
4951@itemize @bullet
4952@item int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int)
4953@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4954@end itemize
4955
4956
4957
4958
4959@subsubsection Create vector from literal bit pattern
4960
4961@itemize @bullet
4962@item uint32x2_t vcreate_u32 (uint64_t)
4963@end itemize
4964
4965
4966@itemize @bullet
4967@item uint16x4_t vcreate_u16 (uint64_t)
4968@end itemize
4969
4970
4971@itemize @bullet
4972@item uint8x8_t vcreate_u8 (uint64_t)
4973@end itemize
4974
4975
4976@itemize @bullet
4977@item int32x2_t vcreate_s32 (uint64_t)
4978@end itemize
4979
4980
4981@itemize @bullet
4982@item int16x4_t vcreate_s16 (uint64_t)
4983@end itemize
4984
4985
4986@itemize @bullet
4987@item int8x8_t vcreate_s8 (uint64_t)
4988@end itemize
4989
4990
4991@itemize @bullet
4992@item uint64x1_t vcreate_u64 (uint64_t)
4993@end itemize
4994
4995
4996@itemize @bullet
4997@item int64x1_t vcreate_s64 (uint64_t)
4998@end itemize
4999
5000
5001@itemize @bullet
5002@item float32x2_t vcreate_f32 (uint64_t)
5003@end itemize
5004
5005
5006@itemize @bullet
5007@item poly16x4_t vcreate_p16 (uint64_t)
5008@end itemize
5009
5010
5011@itemize @bullet
5012@item poly8x8_t vcreate_p8 (uint64_t)
5013@end itemize
5014
5015
5016
5017
5018@subsubsection Set all lanes to the same value
5019
5020@itemize @bullet
5021@item uint32x2_t vdup_n_u32 (uint32_t)
5022@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5023@end itemize
5024
5025
5026@itemize @bullet
5027@item uint16x4_t vdup_n_u16 (uint16_t)
5028@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5029@end itemize
5030
5031
5032@itemize @bullet
5033@item uint8x8_t vdup_n_u8 (uint8_t)
5034@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5035@end itemize
5036
5037
5038@itemize @bullet
5039@item int32x2_t vdup_n_s32 (int32_t)
5040@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5041@end itemize
5042
5043
5044@itemize @bullet
5045@item int16x4_t vdup_n_s16 (int16_t)
5046@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5047@end itemize
5048
5049
5050@itemize @bullet
5051@item int8x8_t vdup_n_s8 (int8_t)
5052@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5053@end itemize
5054
5055
5056@itemize @bullet
5057@item float32x2_t vdup_n_f32 (float32_t)
5058@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5059@end itemize
5060
5061
5062@itemize @bullet
5063@item poly16x4_t vdup_n_p16 (poly16_t)
5064@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5065@end itemize
5066
5067
5068@itemize @bullet
5069@item poly8x8_t vdup_n_p8 (poly8_t)
5070@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5071@end itemize
5072
5073
5074@itemize @bullet
5075@item uint64x1_t vdup_n_u64 (uint64_t)
5076@end itemize
5077
5078
5079@itemize @bullet
5080@item int64x1_t vdup_n_s64 (int64_t)
5081@end itemize
5082
5083
5084@itemize @bullet
5085@item uint32x4_t vdupq_n_u32 (uint32_t)
5086@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5087@end itemize
5088
5089
5090@itemize @bullet
5091@item uint16x8_t vdupq_n_u16 (uint16_t)
5092@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5093@end itemize
5094
5095
5096@itemize @bullet
5097@item uint8x16_t vdupq_n_u8 (uint8_t)
5098@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5099@end itemize
5100
5101
5102@itemize @bullet
5103@item int32x4_t vdupq_n_s32 (int32_t)
5104@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5105@end itemize
5106
5107
5108@itemize @bullet
5109@item int16x8_t vdupq_n_s16 (int16_t)
5110@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5111@end itemize
5112
5113
5114@itemize @bullet
5115@item int8x16_t vdupq_n_s8 (int8_t)
5116@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5117@end itemize
5118
5119
5120@itemize @bullet
5121@item float32x4_t vdupq_n_f32 (float32_t)
5122@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5123@end itemize
5124
5125
5126@itemize @bullet
5127@item poly16x8_t vdupq_n_p16 (poly16_t)
5128@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5129@end itemize
5130
5131
5132@itemize @bullet
5133@item poly8x16_t vdupq_n_p8 (poly8_t)
5134@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5135@end itemize
5136
5137
5138@itemize @bullet
5139@item uint64x2_t vdupq_n_u64 (uint64_t)
5140@end itemize
5141
5142
5143@itemize @bullet
5144@item int64x2_t vdupq_n_s64 (int64_t)
5145@end itemize
5146
5147
5148@itemize @bullet
5149@item uint32x2_t vmov_n_u32 (uint32_t)
5150@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5151@end itemize
5152
5153
5154@itemize @bullet
5155@item uint16x4_t vmov_n_u16 (uint16_t)
5156@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5157@end itemize
5158
5159
5160@itemize @bullet
5161@item uint8x8_t vmov_n_u8 (uint8_t)
5162@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5163@end itemize
5164
5165
5166@itemize @bullet
5167@item int32x2_t vmov_n_s32 (int32_t)
5168@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5169@end itemize
5170
5171
5172@itemize @bullet
5173@item int16x4_t vmov_n_s16 (int16_t)
5174@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5175@end itemize
5176
5177
5178@itemize @bullet
5179@item int8x8_t vmov_n_s8 (int8_t)
5180@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5181@end itemize
5182
5183
5184@itemize @bullet
5185@item float32x2_t vmov_n_f32 (float32_t)
5186@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5187@end itemize
5188
5189
5190@itemize @bullet
5191@item poly16x4_t vmov_n_p16 (poly16_t)
5192@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5193@end itemize
5194
5195
5196@itemize @bullet
5197@item poly8x8_t vmov_n_p8 (poly8_t)
5198@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5199@end itemize
5200
5201
5202@itemize @bullet
5203@item uint64x1_t vmov_n_u64 (uint64_t)
5204@end itemize
5205
5206
5207@itemize @bullet
5208@item int64x1_t vmov_n_s64 (int64_t)
5209@end itemize
5210
5211
5212@itemize @bullet
5213@item uint32x4_t vmovq_n_u32 (uint32_t)
5214@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5215@end itemize
5216
5217
5218@itemize @bullet
5219@item uint16x8_t vmovq_n_u16 (uint16_t)
5220@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5221@end itemize
5222
5223
5224@itemize @bullet
5225@item uint8x16_t vmovq_n_u8 (uint8_t)
5226@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5227@end itemize
5228
5229
5230@itemize @bullet
5231@item int32x4_t vmovq_n_s32 (int32_t)
5232@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5233@end itemize
5234
5235
5236@itemize @bullet
5237@item int16x8_t vmovq_n_s16 (int16_t)
5238@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5239@end itemize
5240
5241
5242@itemize @bullet
5243@item int8x16_t vmovq_n_s8 (int8_t)
5244@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5245@end itemize
5246
5247
5248@itemize @bullet
5249@item float32x4_t vmovq_n_f32 (float32_t)
5250@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5251@end itemize
5252
5253
5254@itemize @bullet
5255@item poly16x8_t vmovq_n_p16 (poly16_t)
5256@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5257@end itemize
5258
5259
5260@itemize @bullet
5261@item poly8x16_t vmovq_n_p8 (poly8_t)
5262@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5263@end itemize
5264
5265
5266@itemize @bullet
5267@item uint64x2_t vmovq_n_u64 (uint64_t)
5268@end itemize
5269
5270
5271@itemize @bullet
5272@item int64x2_t vmovq_n_s64 (int64_t)
5273@end itemize
5274
5275
5276@itemize @bullet
5277@item uint32x2_t vdup_lane_u32 (uint32x2_t, const int)
5278@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5279@end itemize
5280
5281
5282@itemize @bullet
5283@item uint16x4_t vdup_lane_u16 (uint16x4_t, const int)
5284@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5285@end itemize
5286
5287
5288@itemize @bullet
5289@item uint8x8_t vdup_lane_u8 (uint8x8_t, const int)
5290@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5291@end itemize
5292
5293
5294@itemize @bullet
5295@item int32x2_t vdup_lane_s32 (int32x2_t, const int)
5296@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5297@end itemize
5298
5299
5300@itemize @bullet
5301@item int16x4_t vdup_lane_s16 (int16x4_t, const int)
5302@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5303@end itemize
5304
5305
5306@itemize @bullet
5307@item int8x8_t vdup_lane_s8 (int8x8_t, const int)
5308@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5309@end itemize
5310
5311
5312@itemize @bullet
5313@item float32x2_t vdup_lane_f32 (float32x2_t, const int)
5314@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5315@end itemize
5316
5317
5318@itemize @bullet
5319@item poly16x4_t vdup_lane_p16 (poly16x4_t, const int)
5320@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5321@end itemize
5322
5323
5324@itemize @bullet
5325@item poly8x8_t vdup_lane_p8 (poly8x8_t, const int)
5326@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5327@end itemize
5328
5329
5330@itemize @bullet
5331@item uint64x1_t vdup_lane_u64 (uint64x1_t, const int)
5332@end itemize
5333
5334
5335@itemize @bullet
5336@item int64x1_t vdup_lane_s64 (int64x1_t, const int)
5337@end itemize
5338
5339
5340@itemize @bullet
5341@item uint32x4_t vdupq_lane_u32 (uint32x2_t, const int)
5342@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5343@end itemize
5344
5345
5346@itemize @bullet
5347@item uint16x8_t vdupq_lane_u16 (uint16x4_t, const int)
5348@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5349@end itemize
5350
5351
5352@itemize @bullet
5353@item uint8x16_t vdupq_lane_u8 (uint8x8_t, const int)
5354@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5355@end itemize
5356
5357
5358@itemize @bullet
5359@item int32x4_t vdupq_lane_s32 (int32x2_t, const int)
5360@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5361@end itemize
5362
5363
5364@itemize @bullet
5365@item int16x8_t vdupq_lane_s16 (int16x4_t, const int)
5366@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5367@end itemize
5368
5369
5370@itemize @bullet
5371@item int8x16_t vdupq_lane_s8 (int8x8_t, const int)
5372@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5373@end itemize
5374
5375
5376@itemize @bullet
5377@item float32x4_t vdupq_lane_f32 (float32x2_t, const int)
5378@*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5379@end itemize
5380
5381
5382@itemize @bullet
5383@item poly16x8_t vdupq_lane_p16 (poly16x4_t, const int)
5384@*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5385@end itemize
5386
5387
5388@itemize @bullet
5389@item poly8x16_t vdupq_lane_p8 (poly8x8_t, const int)
5390@*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5391@end itemize
5392
5393
5394@itemize @bullet
5395@item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int)
5396@end itemize
5397
5398
5399@itemize @bullet
5400@item int64x2_t vdupq_lane_s64 (int64x1_t, const int)
5401@end itemize
5402
5403
5404
5405
5406@subsubsection Combining vectors
5407
5408@itemize @bullet
5409@item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t)
5410@end itemize
5411
5412
5413@itemize @bullet
5414@item uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t)
5415@end itemize
5416
5417
5418@itemize @bullet
5419@item uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t)
5420@end itemize
5421
5422
5423@itemize @bullet
5424@item int32x4_t vcombine_s32 (int32x2_t, int32x2_t)
5425@end itemize
5426
5427
5428@itemize @bullet
5429@item int16x8_t vcombine_s16 (int16x4_t, int16x4_t)
5430@end itemize
5431
5432
5433@itemize @bullet
5434@item int8x16_t vcombine_s8 (int8x8_t, int8x8_t)
5435@end itemize
5436
5437
5438@itemize @bullet
5439@item uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t)
5440@end itemize
5441
5442
5443@itemize @bullet
5444@item int64x2_t vcombine_s64 (int64x1_t, int64x1_t)
5445@end itemize
5446
5447
5448@itemize @bullet
5449@item float32x4_t vcombine_f32 (float32x2_t, float32x2_t)
5450@end itemize
5451
5452
5453@itemize @bullet
5454@item poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t)
5455@end itemize
5456
5457
5458@itemize @bullet
5459@item poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t)
5460@end itemize
5461
5462
5463
5464
5465@subsubsection Splitting vectors
5466
5467@itemize @bullet
5468@item uint32x2_t vget_high_u32 (uint32x4_t)
5469@end itemize
5470
5471
5472@itemize @bullet
5473@item uint16x4_t vget_high_u16 (uint16x8_t)
5474@end itemize
5475
5476
5477@itemize @bullet
5478@item uint8x8_t vget_high_u8 (uint8x16_t)
5479@end itemize
5480
5481
5482@itemize @bullet
5483@item int32x2_t vget_high_s32 (int32x4_t)
5484@end itemize
5485
5486
5487@itemize @bullet
5488@item int16x4_t vget_high_s16 (int16x8_t)
5489@end itemize
5490
5491
5492@itemize @bullet
5493@item int8x8_t vget_high_s8 (int8x16_t)
5494@end itemize
5495
5496
5497@itemize @bullet
5498@item uint64x1_t vget_high_u64 (uint64x2_t)
5499@end itemize
5500
5501
5502@itemize @bullet
5503@item int64x1_t vget_high_s64 (int64x2_t)
5504@end itemize
5505
5506
5507@itemize @bullet
5508@item float32x2_t vget_high_f32 (float32x4_t)
5509@end itemize
5510
5511
5512@itemize @bullet
5513@item poly16x4_t vget_high_p16 (poly16x8_t)
5514@end itemize
5515
5516
5517@itemize @bullet
5518@item poly8x8_t vget_high_p8 (poly8x16_t)
5519@end itemize
5520
5521
5522@itemize @bullet
5523@item uint32x2_t vget_low_u32 (uint32x4_t)
5524@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5525@end itemize
5526
5527
5528@itemize @bullet
5529@item uint16x4_t vget_low_u16 (uint16x8_t)
5530@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5531@end itemize
5532
5533
5534@itemize @bullet
5535@item uint8x8_t vget_low_u8 (uint8x16_t)
5536@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5537@end itemize
5538
5539
5540@itemize @bullet
5541@item int32x2_t vget_low_s32 (int32x4_t)
5542@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5543@end itemize
5544
5545
5546@itemize @bullet
5547@item int16x4_t vget_low_s16 (int16x8_t)
5548@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5549@end itemize
5550
5551
5552@itemize @bullet
5553@item int8x8_t vget_low_s8 (int8x16_t)
5554@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5555@end itemize
5556
5557
5558@itemize @bullet
5559@item float32x2_t vget_low_f32 (float32x4_t)
5560@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5561@end itemize
5562
5563
5564@itemize @bullet
5565@item poly16x4_t vget_low_p16 (poly16x8_t)
5566@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5567@end itemize
5568
5569
5570@itemize @bullet
5571@item poly8x8_t vget_low_p8 (poly8x16_t)
5572@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5573@end itemize
5574
5575
5576@itemize @bullet
5577@item uint64x1_t vget_low_u64 (uint64x2_t)
5578@end itemize
5579
5580
5581@itemize @bullet
5582@item int64x1_t vget_low_s64 (int64x2_t)
5583@end itemize
5584
5585
5586
5587
5588@subsubsection Conversions
5589
5590@itemize @bullet
5591@item float32x2_t vcvt_f32_u32 (uint32x2_t)
5592@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}}
5593@end itemize
5594
5595
5596@itemize @bullet
5597@item float32x2_t vcvt_f32_s32 (int32x2_t)
5598@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}}
5599@end itemize
5600
5601
5602@itemize @bullet
5603@item uint32x2_t vcvt_u32_f32 (float32x2_t)
5604@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}}
5605@end itemize
5606
5607
5608@itemize @bullet
5609@item int32x2_t vcvt_s32_f32 (float32x2_t)
5610@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}}
5611@end itemize
5612
5613
5614@itemize @bullet
5615@item float32x4_t vcvtq_f32_u32 (uint32x4_t)
5616@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}}
5617@end itemize
5618
5619
5620@itemize @bullet
5621@item float32x4_t vcvtq_f32_s32 (int32x4_t)
5622@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}}
5623@end itemize
5624
5625
5626@itemize @bullet
5627@item uint32x4_t vcvtq_u32_f32 (float32x4_t)
5628@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}}
5629@end itemize
5630
5631
5632@itemize @bullet
5633@item int32x4_t vcvtq_s32_f32 (float32x4_t)
5634@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}}
5635@end itemize
5636
5637
5638@itemize @bullet
5639@item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
5640@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}}
5641@end itemize
5642
5643
5644@itemize @bullet
5645@item float32x2_t vcvt_n_f32_s32 (int32x2_t, const int)
5646@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}, #@var{0}}
5647@end itemize
5648
5649
5650@itemize @bullet
5651@item uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int)
5652@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}, #@var{0}}
5653@end itemize
5654
5655
5656@itemize @bullet
5657@item int32x2_t vcvt_n_s32_f32 (float32x2_t, const int)
5658@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}, #@var{0}}
5659@end itemize
5660
5661
5662@itemize @bullet
5663@item float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int)
5664@*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}, #@var{0}}
5665@end itemize
5666
5667
5668@itemize @bullet
5669@item float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int)
5670@*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}, #@var{0}}
5671@end itemize
5672
5673
5674@itemize @bullet
5675@item uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int)
5676@*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}, #@var{0}}
5677@end itemize
5678
5679
5680@itemize @bullet
5681@item int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int)
5682@*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}, #@var{0}}
5683@end itemize
5684
5685
5686
5687
5688@subsubsection Move, single_opcode narrowing
5689
5690@itemize @bullet
5691@item uint32x2_t vmovn_u64 (uint64x2_t)
5692@*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5693@end itemize
5694
5695
5696@itemize @bullet
5697@item uint16x4_t vmovn_u32 (uint32x4_t)
5698@*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5699@end itemize
5700
5701
5702@itemize @bullet
5703@item uint8x8_t vmovn_u16 (uint16x8_t)
5704@*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5705@end itemize
5706
5707
5708@itemize @bullet
5709@item int32x2_t vmovn_s64 (int64x2_t)
5710@*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5711@end itemize
5712
5713
5714@itemize @bullet
5715@item int16x4_t vmovn_s32 (int32x4_t)
5716@*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5717@end itemize
5718
5719
5720@itemize @bullet
5721@item int8x8_t vmovn_s16 (int16x8_t)
5722@*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5723@end itemize
5724
5725
5726@itemize @bullet
5727@item uint32x2_t vqmovn_u64 (uint64x2_t)
5728@*@emph{Form of expected instruction(s):} @code{vqmovn.u64 @var{d0}, @var{q0}}
5729@end itemize
5730
5731
5732@itemize @bullet
5733@item uint16x4_t vqmovn_u32 (uint32x4_t)
5734@*@emph{Form of expected instruction(s):} @code{vqmovn.u32 @var{d0}, @var{q0}}
5735@end itemize
5736
5737
5738@itemize @bullet
5739@item uint8x8_t vqmovn_u16 (uint16x8_t)
5740@*@emph{Form of expected instruction(s):} @code{vqmovn.u16 @var{d0}, @var{q0}}
5741@end itemize
5742
5743
5744@itemize @bullet
5745@item int32x2_t vqmovn_s64 (int64x2_t)
5746@*@emph{Form of expected instruction(s):} @code{vqmovn.s64 @var{d0}, @var{q0}}
5747@end itemize
5748
5749
5750@itemize @bullet
5751@item int16x4_t vqmovn_s32 (int32x4_t)
5752@*@emph{Form of expected instruction(s):} @code{vqmovn.s32 @var{d0}, @var{q0}}
5753@end itemize
5754
5755
5756@itemize @bullet
5757@item int8x8_t vqmovn_s16 (int16x8_t)
5758@*@emph{Form of expected instruction(s):} @code{vqmovn.s16 @var{d0}, @var{q0}}
5759@end itemize
5760
5761
5762@itemize @bullet
5763@item uint32x2_t vqmovun_s64 (int64x2_t)
5764@*@emph{Form of expected instruction(s):} @code{vqmovun.s64 @var{d0}, @var{q0}}
5765@end itemize
5766
5767
5768@itemize @bullet
5769@item uint16x4_t vqmovun_s32 (int32x4_t)
5770@*@emph{Form of expected instruction(s):} @code{vqmovun.s32 @var{d0}, @var{q0}}
5771@end itemize
5772
5773
5774@itemize @bullet
5775@item uint8x8_t vqmovun_s16 (int16x8_t)
5776@*@emph{Form of expected instruction(s):} @code{vqmovun.s16 @var{d0}, @var{q0}}
5777@end itemize
5778
5779
5780
5781
5782@subsubsection Move, single_opcode long
5783
5784@itemize @bullet
5785@item uint64x2_t vmovl_u32 (uint32x2_t)
5786@*@emph{Form of expected instruction(s):} @code{vmovl.u32 @var{q0}, @var{d0}}
5787@end itemize
5788
5789
5790@itemize @bullet
5791@item uint32x4_t vmovl_u16 (uint16x4_t)
5792@*@emph{Form of expected instruction(s):} @code{vmovl.u16 @var{q0}, @var{d0}}
5793@end itemize
5794
5795
5796@itemize @bullet
5797@item uint16x8_t vmovl_u8 (uint8x8_t)
5798@*@emph{Form of expected instruction(s):} @code{vmovl.u8 @var{q0}, @var{d0}}
5799@end itemize
5800
5801
5802@itemize @bullet
5803@item int64x2_t vmovl_s32 (int32x2_t)
5804@*@emph{Form of expected instruction(s):} @code{vmovl.s32 @var{q0}, @var{d0}}
5805@end itemize
5806
5807
5808@itemize @bullet
5809@item int32x4_t vmovl_s16 (int16x4_t)
5810@*@emph{Form of expected instruction(s):} @code{vmovl.s16 @var{q0}, @var{d0}}
5811@end itemize
5812
5813
5814@itemize @bullet
5815@item int16x8_t vmovl_s8 (int8x8_t)
5816@*@emph{Form of expected instruction(s):} @code{vmovl.s8 @var{q0}, @var{d0}}
5817@end itemize
5818
5819
5820
5821
5822@subsubsection Table lookup
5823
5824@itemize @bullet
5825@item poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t)
5826@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5827@end itemize
5828
5829
5830@itemize @bullet
5831@item int8x8_t vtbl1_s8 (int8x8_t, int8x8_t)
5832@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5833@end itemize
5834
5835
5836@itemize @bullet
5837@item uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t)
5838@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5839@end itemize
5840
5841
5842@itemize @bullet
5843@item poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t)
5844@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5845@end itemize
5846
5847
5848@itemize @bullet
5849@item int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t)
5850@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5851@end itemize
5852
5853
5854@itemize @bullet
5855@item uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t)
5856@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5857@end itemize
5858
5859
5860@itemize @bullet
5861@item poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t)
5862@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5863@end itemize
5864
5865
5866@itemize @bullet
5867@item int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t)
5868@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5869@end itemize
5870
5871
5872@itemize @bullet
5873@item uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t)
5874@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5875@end itemize
5876
5877
5878@itemize @bullet
5879@item poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t)
5880@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5881@end itemize
5882
5883
5884@itemize @bullet
5885@item int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t)
5886@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5887@end itemize
5888
5889
5890@itemize @bullet
5891@item uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t)
5892@*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5893@end itemize
5894
5895
5896
5897
5898@subsubsection Extended table lookup
5899
5900@itemize @bullet
5901@item poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t)
5902@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5903@end itemize
5904
5905
5906@itemize @bullet
5907@item int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t)
5908@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5909@end itemize
5910
5911
5912@itemize @bullet
5913@item uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
5914@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5915@end itemize
5916
5917
5918@itemize @bullet
5919@item poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t)
5920@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5921@end itemize
5922
5923
5924@itemize @bullet
5925@item int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t)
5926@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5927@end itemize
5928
5929
5930@itemize @bullet
5931@item uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t)
5932@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5933@end itemize
5934
5935
5936@itemize @bullet
5937@item poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t)
5938@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5939@end itemize
5940
5941
5942@itemize @bullet
5943@item int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t)
5944@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5945@end itemize
5946
5947
5948@itemize @bullet
5949@item uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t)
5950@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5951@end itemize
5952
5953
5954@itemize @bullet
5955@item poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t)
5956@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5957@end itemize
5958
5959
5960@itemize @bullet
5961@item int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t)
5962@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5963@end itemize
5964
5965
5966@itemize @bullet
5967@item uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t)
5968@*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5969@end itemize
5970
5971
5972
5973
5974@subsubsection Multiply, lane
5975
5976@itemize @bullet
5977@item float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int)
5978@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
5979@end itemize
5980
5981
5982@itemize @bullet
5983@item uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int)
5984@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
5985@end itemize
5986
5987
5988@itemize @bullet
5989@item uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int)
5990@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
5991@end itemize
5992
5993
5994@itemize @bullet
5995@item int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int)
5996@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
5997@end itemize
5998
5999
6000@itemize @bullet
6001@item int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int)
6002@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6003@end itemize
6004
6005
6006@itemize @bullet
6007@item float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int)
6008@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6009@end itemize
6010
6011
6012@itemize @bullet
6013@item uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int)
6014@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6015@end itemize
6016
6017
6018@itemize @bullet
6019@item uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int)
6020@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6021@end itemize
6022
6023
6024@itemize @bullet
6025@item int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int)
6026@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6027@end itemize
6028
6029
6030@itemize @bullet
6031@item int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int)
6032@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6033@end itemize
6034
6035
6036
6037
6038@subsubsection Long multiply, lane
6039
6040@itemize @bullet
6041@item uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int)
6042@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6043@end itemize
6044
6045
6046@itemize @bullet
6047@item uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int)
6048@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6049@end itemize
6050
6051
6052@itemize @bullet
6053@item int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int)
6054@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6055@end itemize
6056
6057
6058@itemize @bullet
6059@item int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int)
6060@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6061@end itemize
6062
6063
6064
6065
6066@subsubsection Saturating doubling long multiply, lane
6067
6068@itemize @bullet
6069@item int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int)
6070@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6071@end itemize
6072
6073
6074@itemize @bullet
6075@item int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int)
6076@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6077@end itemize
6078
6079
6080
6081
6082@subsubsection Saturating doubling multiply high, lane
6083
6084@itemize @bullet
6085@item int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6086@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6087@end itemize
6088
6089
6090@itemize @bullet
6091@item int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6092@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6093@end itemize
6094
6095
6096@itemize @bullet
6097@item int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6098@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6099@end itemize
6100
6101
6102@itemize @bullet
6103@item int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6104@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6105@end itemize
6106
6107
6108@itemize @bullet
6109@item int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6110@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6111@end itemize
6112
6113
6114@itemize @bullet
6115@item int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6116@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6117@end itemize
6118
6119
6120@itemize @bullet
6121@item int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6122@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6123@end itemize
6124
6125
6126@itemize @bullet
6127@item int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6128@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6129@end itemize
6130
6131
6132
6133
6134@subsubsection Multiply-accumulate, lane
6135
6136@itemize @bullet
6137@item float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6138@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6139@end itemize
6140
6141
6142@itemize @bullet
6143@item uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6144@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6145@end itemize
6146
6147
6148@itemize @bullet
6149@item uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6150@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6151@end itemize
6152
6153
6154@itemize @bullet
6155@item int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6156@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6157@end itemize
6158
6159
6160@itemize @bullet
6161@item int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6162@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6163@end itemize
6164
6165
6166@itemize @bullet
6167@item float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6168@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6169@end itemize
6170
6171
6172@itemize @bullet
6173@item uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6174@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6175@end itemize
6176
6177
6178@itemize @bullet
6179@item uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6180@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6181@end itemize
6182
6183
6184@itemize @bullet
6185@item int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6186@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6187@end itemize
6188
6189
6190@itemize @bullet
6191@item int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6192@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6193@end itemize
6194
6195
6196@itemize @bullet
6197@item uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6198@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6199@end itemize
6200
6201
6202@itemize @bullet
6203@item uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6204@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6205@end itemize
6206
6207
6208@itemize @bullet
6209@item int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6210@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6211@end itemize
6212
6213
6214@itemize @bullet
6215@item int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6216@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6217@end itemize
6218
6219
6220@itemize @bullet
6221@item int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6222@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6223@end itemize
6224
6225
6226@itemize @bullet
6227@item int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6228@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6229@end itemize
6230
6231
6232
6233
6234@subsubsection Multiply-subtract, lane
6235
6236@itemize @bullet
6237@item float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6238@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6239@end itemize
6240
6241
6242@itemize @bullet
6243@item uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6244@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6245@end itemize
6246
6247
6248@itemize @bullet
6249@item uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6250@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6251@end itemize
6252
6253
6254@itemize @bullet
6255@item int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6256@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6257@end itemize
6258
6259
6260@itemize @bullet
6261@item int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6262@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6263@end itemize
6264
6265
6266@itemize @bullet
6267@item float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6268@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6269@end itemize
6270
6271
6272@itemize @bullet
6273@item uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6274@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6275@end itemize
6276
6277
6278@itemize @bullet
6279@item uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6280@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6281@end itemize
6282
6283
6284@itemize @bullet
6285@item int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6286@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6287@end itemize
6288
6289
6290@itemize @bullet
6291@item int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6292@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6293@end itemize
6294
6295
6296@itemize @bullet
6297@item uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6298@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6299@end itemize
6300
6301
6302@itemize @bullet
6303@item uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6304@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6305@end itemize
6306
6307
6308@itemize @bullet
6309@item int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6310@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6311@end itemize
6312
6313
6314@itemize @bullet
6315@item int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6316@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6317@end itemize
6318
6319
6320@itemize @bullet
6321@item int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6322@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6323@end itemize
6324
6325
6326@itemize @bullet
6327@item int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6328@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6329@end itemize
6330
6331
6332
6333
6334@subsubsection Vector multiply by scalar
6335
6336@itemize @bullet
6337@item float32x2_t vmul_n_f32 (float32x2_t, float32_t)
6338@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6339@end itemize
6340
6341
6342@itemize @bullet
6343@item uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t)
6344@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6345@end itemize
6346
6347
6348@itemize @bullet
6349@item uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t)
6350@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6351@end itemize
6352
6353
6354@itemize @bullet
6355@item int32x2_t vmul_n_s32 (int32x2_t, int32_t)
6356@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6357@end itemize
6358
6359
6360@itemize @bullet
6361@item int16x4_t vmul_n_s16 (int16x4_t, int16_t)
6362@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6363@end itemize
6364
6365
6366@itemize @bullet
6367@item float32x4_t vmulq_n_f32 (float32x4_t, float32_t)
6368@*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6369@end itemize
6370
6371
6372@itemize @bullet
6373@item uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t)
6374@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6375@end itemize
6376
6377
6378@itemize @bullet
6379@item uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t)
6380@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6381@end itemize
6382
6383
6384@itemize @bullet
6385@item int32x4_t vmulq_n_s32 (int32x4_t, int32_t)
6386@*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6387@end itemize
6388
6389
6390@itemize @bullet
6391@item int16x8_t vmulq_n_s16 (int16x8_t, int16_t)
6392@*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6393@end itemize
6394
6395
6396
6397
6398@subsubsection Vector long multiply by scalar
6399
6400@itemize @bullet
6401@item uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t)
6402@*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6403@end itemize
6404
6405
6406@itemize @bullet
6407@item uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t)
6408@*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6409@end itemize
6410
6411
6412@itemize @bullet
6413@item int64x2_t vmull_n_s32 (int32x2_t, int32_t)
6414@*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6415@end itemize
6416
6417
6418@itemize @bullet
6419@item int32x4_t vmull_n_s16 (int16x4_t, int16_t)
6420@*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6421@end itemize
6422
6423
6424
6425
6426@subsubsection Vector saturating doubling long multiply by scalar
6427
6428@itemize @bullet
6429@item int64x2_t vqdmull_n_s32 (int32x2_t, int32_t)
6430@*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6431@end itemize
6432
6433
6434@itemize @bullet
6435@item int32x4_t vqdmull_n_s16 (int16x4_t, int16_t)
6436@*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6437@end itemize
6438
6439
6440
6441
6442@subsubsection Vector saturating doubling multiply high by scalar
6443
6444@itemize @bullet
6445@item int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t)
6446@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6447@end itemize
6448
6449
6450@itemize @bullet
6451@item int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t)
6452@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6453@end itemize
6454
6455
6456@itemize @bullet
6457@item int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t)
6458@*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6459@end itemize
6460
6461
6462@itemize @bullet
6463@item int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t)
6464@*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6465@end itemize
6466
6467
6468@itemize @bullet
6469@item int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t)
6470@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6471@end itemize
6472
6473
6474@itemize @bullet
6475@item int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t)
6476@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6477@end itemize
6478
6479
6480@itemize @bullet
6481@item int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t)
6482@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6483@end itemize
6484
6485
6486@itemize @bullet
6487@item int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t)
6488@*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6489@end itemize
6490
6491
6492
6493
6494@subsubsection Vector multiply-accumulate by scalar
6495
6496@itemize @bullet
6497@item float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t)
6498@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6499@end itemize
6500
6501
6502@itemize @bullet
6503@item uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6504@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6505@end itemize
6506
6507
6508@itemize @bullet
6509@item uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6510@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6511@end itemize
6512
6513
6514@itemize @bullet
6515@item int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t)
6516@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6517@end itemize
6518
6519
6520@itemize @bullet
6521@item int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t)
6522@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6523@end itemize
6524
6525
6526@itemize @bullet
6527@item float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t)
6528@*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6529@end itemize
6530
6531
6532@itemize @bullet
6533@item uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6534@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6535@end itemize
6536
6537
6538@itemize @bullet
6539@item uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6540@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6541@end itemize
6542
6543
6544@itemize @bullet
6545@item int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t)
6546@*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6547@end itemize
6548
6549
6550@itemize @bullet
6551@item int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t)
6552@*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6553@end itemize
6554
6555
6556@itemize @bullet
6557@item uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6558@*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6559@end itemize
6560
6561
6562@itemize @bullet
6563@item uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6564@*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6565@end itemize
6566
6567
6568@itemize @bullet
6569@item int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6570@*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6571@end itemize
6572
6573
6574@itemize @bullet
6575@item int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6576@*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6577@end itemize
6578
6579
6580@itemize @bullet
6581@item int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6582@*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6583@end itemize
6584
6585
6586@itemize @bullet
6587@item int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6588@*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6589@end itemize
6590
6591
6592
6593
6594@subsubsection Vector multiply-subtract by scalar
6595
6596@itemize @bullet
6597@item float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t)
6598@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6599@end itemize
6600
6601
6602@itemize @bullet
6603@item uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6604@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6605@end itemize
6606
6607
6608@itemize @bullet
6609@item uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6610@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6611@end itemize
6612
6613
6614@itemize @bullet
6615@item int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t)
6616@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6617@end itemize
6618
6619
6620@itemize @bullet
6621@item int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t)
6622@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6623@end itemize
6624
6625
6626@itemize @bullet
6627@item float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t)
6628@*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6629@end itemize
6630
6631
6632@itemize @bullet
6633@item uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6634@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6635@end itemize
6636
6637
6638@itemize @bullet
6639@item uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6640@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6641@end itemize
6642
6643
6644@itemize @bullet
6645@item int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t)
6646@*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6647@end itemize
6648
6649
6650@itemize @bullet
6651@item int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t)
6652@*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6653@end itemize
6654
6655
6656@itemize @bullet
6657@item uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6658@*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6659@end itemize
6660
6661
6662@itemize @bullet
6663@item uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6664@*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6665@end itemize
6666
6667
6668@itemize @bullet
6669@item int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6670@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6671@end itemize
6672
6673
6674@itemize @bullet
6675@item int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6676@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6677@end itemize
6678
6679
6680@itemize @bullet
6681@item int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6682@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6683@end itemize
6684
6685
6686@itemize @bullet
6687@item int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6688@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6689@end itemize
6690
6691
6692
6693
6694@subsubsection Vector extract
6695
6696@itemize @bullet
6697@item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int)
6698@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6699@end itemize
6700
6701
6702@itemize @bullet
6703@item uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int)
6704@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6705@end itemize
6706
6707
6708@itemize @bullet
6709@item uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int)
6710@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6711@end itemize
6712
6713
6714@itemize @bullet
6715@item int32x2_t vext_s32 (int32x2_t, int32x2_t, const int)
6716@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6717@end itemize
6718
6719
6720@itemize @bullet
6721@item int16x4_t vext_s16 (int16x4_t, int16x4_t, const int)
6722@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6723@end itemize
6724
6725
6726@itemize @bullet
6727@item int8x8_t vext_s8 (int8x8_t, int8x8_t, const int)
6728@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6729@end itemize
6730
6731
6732@itemize @bullet
6733@item uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int)
6734@*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6735@end itemize
6736
6737
6738@itemize @bullet
6739@item int64x1_t vext_s64 (int64x1_t, int64x1_t, const int)
6740@*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6741@end itemize
6742
6743
6744@itemize @bullet
6745@item float32x2_t vext_f32 (float32x2_t, float32x2_t, const int)
6746@*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6747@end itemize
6748
6749
6750@itemize @bullet
6751@item poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int)
6752@*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6753@end itemize
6754
6755
6756@itemize @bullet
6757@item poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int)
6758@*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6759@end itemize
6760
6761
6762@itemize @bullet
6763@item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int)
6764@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6765@end itemize
6766
6767
6768@itemize @bullet
6769@item uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int)
6770@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6771@end itemize
6772
6773
6774@itemize @bullet
6775@item uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int)
6776@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6777@end itemize
6778
6779
6780@itemize @bullet
6781@item int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int)
6782@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6783@end itemize
6784
6785
6786@itemize @bullet
6787@item int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int)
6788@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6789@end itemize
6790
6791
6792@itemize @bullet
6793@item int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int)
6794@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6795@end itemize
6796
6797
6798@itemize @bullet
6799@item uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int)
6800@*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6801@end itemize
6802
6803
6804@itemize @bullet
6805@item int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int)
6806@*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6807@end itemize
6808
6809
6810@itemize @bullet
6811@item float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int)
6812@*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6813@end itemize
6814
6815
6816@itemize @bullet
6817@item poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int)
6818@*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6819@end itemize
6820
6821
6822@itemize @bullet
6823@item poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int)
6824@*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6825@end itemize
6826
6827
6828
6829
6830@subsubsection Reverse elements
6831
6832@itemize @bullet
6833@item uint32x2_t vrev64_u32 (uint32x2_t)
6834@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6835@end itemize
6836
6837
6838@itemize @bullet
6839@item uint16x4_t vrev64_u16 (uint16x4_t)
6840@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6841@end itemize
6842
6843
6844@itemize @bullet
6845@item uint8x8_t vrev64_u8 (uint8x8_t)
6846@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6847@end itemize
6848
6849
6850@itemize @bullet
6851@item int32x2_t vrev64_s32 (int32x2_t)
6852@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6853@end itemize
6854
6855
6856@itemize @bullet
6857@item int16x4_t vrev64_s16 (int16x4_t)
6858@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6859@end itemize
6860
6861
6862@itemize @bullet
6863@item int8x8_t vrev64_s8 (int8x8_t)
6864@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6865@end itemize
6866
6867
6868@itemize @bullet
6869@item float32x2_t vrev64_f32 (float32x2_t)
6870@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6871@end itemize
6872
6873
6874@itemize @bullet
6875@item poly16x4_t vrev64_p16 (poly16x4_t)
6876@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6877@end itemize
6878
6879
6880@itemize @bullet
6881@item poly8x8_t vrev64_p8 (poly8x8_t)
6882@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6883@end itemize
6884
6885
6886@itemize @bullet
6887@item uint32x4_t vrev64q_u32 (uint32x4_t)
6888@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6889@end itemize
6890
6891
6892@itemize @bullet
6893@item uint16x8_t vrev64q_u16 (uint16x8_t)
6894@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6895@end itemize
6896
6897
6898@itemize @bullet
6899@item uint8x16_t vrev64q_u8 (uint8x16_t)
6900@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6901@end itemize
6902
6903
6904@itemize @bullet
6905@item int32x4_t vrev64q_s32 (int32x4_t)
6906@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6907@end itemize
6908
6909
6910@itemize @bullet
6911@item int16x8_t vrev64q_s16 (int16x8_t)
6912@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6913@end itemize
6914
6915
6916@itemize @bullet
6917@item int8x16_t vrev64q_s8 (int8x16_t)
6918@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6919@end itemize
6920
6921
6922@itemize @bullet
6923@item float32x4_t vrev64q_f32 (float32x4_t)
6924@*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6925@end itemize
6926
6927
6928@itemize @bullet
6929@item poly16x8_t vrev64q_p16 (poly16x8_t)
6930@*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6931@end itemize
6932
6933
6934@itemize @bullet
6935@item poly8x16_t vrev64q_p8 (poly8x16_t)
6936@*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6937@end itemize
6938
6939
6940@itemize @bullet
6941@item uint16x4_t vrev32_u16 (uint16x4_t)
6942@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6943@end itemize
6944
6945
6946@itemize @bullet
6947@item int16x4_t vrev32_s16 (int16x4_t)
6948@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6949@end itemize
6950
6951
6952@itemize @bullet
6953@item uint8x8_t vrev32_u8 (uint8x8_t)
6954@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6955@end itemize
6956
6957
6958@itemize @bullet
6959@item int8x8_t vrev32_s8 (int8x8_t)
6960@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6961@end itemize
6962
6963
6964@itemize @bullet
6965@item poly16x4_t vrev32_p16 (poly16x4_t)
6966@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6967@end itemize
6968
6969
6970@itemize @bullet
6971@item poly8x8_t vrev32_p8 (poly8x8_t)
6972@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6973@end itemize
6974
6975
6976@itemize @bullet
6977@item uint16x8_t vrev32q_u16 (uint16x8_t)
6978@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
6979@end itemize
6980
6981
6982@itemize @bullet
6983@item int16x8_t vrev32q_s16 (int16x8_t)
6984@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
6985@end itemize
6986
6987
6988@itemize @bullet
6989@item uint8x16_t vrev32q_u8 (uint8x16_t)
6990@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
6991@end itemize
6992
6993
6994@itemize @bullet
6995@item int8x16_t vrev32q_s8 (int8x16_t)
6996@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
6997@end itemize
6998
6999
7000@itemize @bullet
7001@item poly16x8_t vrev32q_p16 (poly16x8_t)
7002@*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7003@end itemize
7004
7005
7006@itemize @bullet
7007@item poly8x16_t vrev32q_p8 (poly8x16_t)
7008@*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7009@end itemize
7010
7011
7012@itemize @bullet
7013@item uint8x8_t vrev16_u8 (uint8x8_t)
7014@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7015@end itemize
7016
7017
7018@itemize @bullet
7019@item int8x8_t vrev16_s8 (int8x8_t)
7020@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7021@end itemize
7022
7023
7024@itemize @bullet
7025@item poly8x8_t vrev16_p8 (poly8x8_t)
7026@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7027@end itemize
7028
7029
7030@itemize @bullet
7031@item uint8x16_t vrev16q_u8 (uint8x16_t)
7032@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7033@end itemize
7034
7035
7036@itemize @bullet
7037@item int8x16_t vrev16q_s8 (int8x16_t)
7038@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7039@end itemize
7040
7041
7042@itemize @bullet
7043@item poly8x16_t vrev16q_p8 (poly8x16_t)
7044@*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7045@end itemize
7046
7047
7048
7049
7050@subsubsection Bit selection
7051
7052@itemize @bullet
7053@item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
7054@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7055@end itemize
7056
7057
7058@itemize @bullet
7059@item uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
7060@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7061@end itemize
7062
7063
7064@itemize @bullet
7065@item uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
7066@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7067@end itemize
7068
7069
7070@itemize @bullet
7071@item int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t)
7072@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7073@end itemize
7074
7075
7076@itemize @bullet
7077@item int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t)
7078@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7079@end itemize
7080
7081
7082@itemize @bullet
7083@item int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t)
7084@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7085@end itemize
7086
7087
7088@itemize @bullet
7089@item uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t)
7090@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7091@end itemize
7092
7093
7094@itemize @bullet
7095@item int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t)
7096@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7097@end itemize
7098
7099
7100@itemize @bullet
7101@item float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t)
7102@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7103@end itemize
7104
7105
7106@itemize @bullet
7107@item poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t)
7108@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7109@end itemize
7110
7111
7112@itemize @bullet
7113@item poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t)
7114@*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7115@end itemize
7116
7117
7118@itemize @bullet
7119@item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
7120@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7121@end itemize
7122
7123
7124@itemize @bullet
7125@item uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
7126@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7127@end itemize
7128
7129
7130@itemize @bullet
7131@item uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
7132@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7133@end itemize
7134
7135
7136@itemize @bullet
7137@item int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t)
7138@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7139@end itemize
7140
7141
7142@itemize @bullet
7143@item int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t)
7144@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7145@end itemize
7146
7147
7148@itemize @bullet
7149@item int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t)
7150@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7151@end itemize
7152
7153
7154@itemize @bullet
7155@item uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t)
7156@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7157@end itemize
7158
7159
7160@itemize @bullet
7161@item int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t)
7162@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7163@end itemize
7164
7165
7166@itemize @bullet
7167@item float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t)
7168@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7169@end itemize
7170
7171
7172@itemize @bullet
7173@item poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t)
7174@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7175@end itemize
7176
7177
7178@itemize @bullet
7179@item poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t)
7180@*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7181@end itemize
7182
7183
7184
7185
7186@subsubsection Transpose elements
7187
7188@itemize @bullet
7189@item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
7190@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7191@end itemize
7192
7193
7194@itemize @bullet
7195@item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
7196@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7197@end itemize
7198
7199
7200@itemize @bullet
7201@item uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t)
7202@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7203@end itemize
7204
7205
7206@itemize @bullet
7207@item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
7208@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7209@end itemize
7210
7211
7212@itemize @bullet
7213@item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
7214@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7215@end itemize
7216
7217
7218@itemize @bullet
7219@item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
7220@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7221@end itemize
7222
7223
7224@itemize @bullet
7225@item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
7226@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7227@end itemize
7228
7229
7230@itemize @bullet
7231@item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
7232@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7233@end itemize
7234
7235
7236@itemize @bullet
7237@item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
7238@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7239@end itemize
7240
7241
7242@itemize @bullet
7243@item uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t)
7244@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7245@end itemize
7246
7247
7248@itemize @bullet
7249@item uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t)
7250@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7251@end itemize
7252
7253
7254@itemize @bullet
7255@item uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t)
7256@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7257@end itemize
7258
7259
7260@itemize @bullet
7261@item int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t)
7262@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7263@end itemize
7264
7265
7266@itemize @bullet
7267@item int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t)
7268@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7269@end itemize
7270
7271
7272@itemize @bullet
7273@item int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t)
7274@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7275@end itemize
7276
7277
7278@itemize @bullet
7279@item float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t)
7280@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7281@end itemize
7282
7283
7284@itemize @bullet
7285@item poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t)
7286@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7287@end itemize
7288
7289
7290@itemize @bullet
7291@item poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t)
7292@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7293@end itemize
7294
7295
7296
7297
7298@subsubsection Zip elements
7299
7300@itemize @bullet
7301@item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
7302@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7303@end itemize
7304
7305
7306@itemize @bullet
7307@item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
7308@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7309@end itemize
7310
7311
7312@itemize @bullet
7313@item uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t)
7314@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7315@end itemize
7316
7317
7318@itemize @bullet
7319@item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
7320@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7321@end itemize
7322
7323
7324@itemize @bullet
7325@item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
7326@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7327@end itemize
7328
7329
7330@itemize @bullet
7331@item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
7332@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7333@end itemize
7334
7335
7336@itemize @bullet
7337@item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
7338@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7339@end itemize
7340
7341
7342@itemize @bullet
7343@item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
7344@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7345@end itemize
7346
7347
7348@itemize @bullet
7349@item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
7350@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7351@end itemize
7352
7353
7354@itemize @bullet
7355@item uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t)
7356@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7357@end itemize
7358
7359
7360@itemize @bullet
7361@item uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t)
7362@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7363@end itemize
7364
7365
7366@itemize @bullet
7367@item uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t)
7368@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7369@end itemize
7370
7371
7372@itemize @bullet
7373@item int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t)
7374@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7375@end itemize
7376
7377
7378@itemize @bullet
7379@item int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t)
7380@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7381@end itemize
7382
7383
7384@itemize @bullet
7385@item int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t)
7386@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7387@end itemize
7388
7389
7390@itemize @bullet
7391@item float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t)
7392@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7393@end itemize
7394
7395
7396@itemize @bullet
7397@item poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t)
7398@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7399@end itemize
7400
7401
7402@itemize @bullet
7403@item poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t)
7404@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7405@end itemize
7406
7407
7408
7409
7410@subsubsection Unzip elements
7411
7412@itemize @bullet
7413@item uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t)
7414@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7415@end itemize
7416
7417
7418@itemize @bullet
7419@item uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t)
7420@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7421@end itemize
7422
7423
7424@itemize @bullet
7425@item uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t)
7426@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7427@end itemize
7428
7429
7430@itemize @bullet
7431@item int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t)
7432@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7433@end itemize
7434
7435
7436@itemize @bullet
7437@item int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t)
7438@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7439@end itemize
7440
7441
7442@itemize @bullet
7443@item int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t)
7444@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7445@end itemize
7446
7447
7448@itemize @bullet
7449@item float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t)
7450@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7451@end itemize
7452
7453
7454@itemize @bullet
7455@item poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t)
7456@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7457@end itemize
7458
7459
7460@itemize @bullet
7461@item poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t)
7462@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7463@end itemize
7464
7465
7466@itemize @bullet
7467@item uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t)
7468@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7469@end itemize
7470
7471
7472@itemize @bullet
7473@item uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t)
7474@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7475@end itemize
7476
7477
7478@itemize @bullet
7479@item uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t)
7480@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7481@end itemize
7482
7483
7484@itemize @bullet
7485@item int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t)
7486@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7487@end itemize
7488
7489
7490@itemize @bullet
7491@item int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t)
7492@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7493@end itemize
7494
7495
7496@itemize @bullet
7497@item int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t)
7498@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7499@end itemize
7500
7501
7502@itemize @bullet
7503@item float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t)
7504@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7505@end itemize
7506
7507
7508@itemize @bullet
7509@item poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t)
7510@*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7511@end itemize
7512
7513
7514@itemize @bullet
7515@item poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t)
7516@*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7517@end itemize
7518
7519
7520
7521
7522@subsubsection Element/structure loads, VLD1 variants
7523
7524@itemize @bullet
7525@item uint32x2_t vld1_u32 (const uint32_t *)
7526@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7527@end itemize
7528
7529
7530@itemize @bullet
7531@item uint16x4_t vld1_u16 (const uint16_t *)
7532@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7533@end itemize
7534
7535
7536@itemize @bullet
7537@item uint8x8_t vld1_u8 (const uint8_t *)
7538@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7539@end itemize
7540
7541
7542@itemize @bullet
7543@item int32x2_t vld1_s32 (const int32_t *)
7544@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7545@end itemize
7546
7547
7548@itemize @bullet
7549@item int16x4_t vld1_s16 (const int16_t *)
7550@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7551@end itemize
7552
7553
7554@itemize @bullet
7555@item int8x8_t vld1_s8 (const int8_t *)
7556@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7557@end itemize
7558
7559
7560@itemize @bullet
7561@item uint64x1_t vld1_u64 (const uint64_t *)
7562@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7563@end itemize
7564
7565
7566@itemize @bullet
7567@item int64x1_t vld1_s64 (const int64_t *)
7568@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7569@end itemize
7570
7571
7572@itemize @bullet
7573@item float32x2_t vld1_f32 (const float32_t *)
7574@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7575@end itemize
7576
7577
7578@itemize @bullet
7579@item poly16x4_t vld1_p16 (const poly16_t *)
7580@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7581@end itemize
7582
7583
7584@itemize @bullet
7585@item poly8x8_t vld1_p8 (const poly8_t *)
7586@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7587@end itemize
7588
7589
7590@itemize @bullet
7591@item uint32x4_t vld1q_u32 (const uint32_t *)
7592@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7593@end itemize
7594
7595
7596@itemize @bullet
7597@item uint16x8_t vld1q_u16 (const uint16_t *)
7598@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7599@end itemize
7600
7601
7602@itemize @bullet
7603@item uint8x16_t vld1q_u8 (const uint8_t *)
7604@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7605@end itemize
7606
7607
7608@itemize @bullet
7609@item int32x4_t vld1q_s32 (const int32_t *)
7610@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7611@end itemize
7612
7613
7614@itemize @bullet
7615@item int16x8_t vld1q_s16 (const int16_t *)
7616@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7617@end itemize
7618
7619
7620@itemize @bullet
7621@item int8x16_t vld1q_s8 (const int8_t *)
7622@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7623@end itemize
7624
7625
7626@itemize @bullet
7627@item uint64x2_t vld1q_u64 (const uint64_t *)
7628@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7629@end itemize
7630
7631
7632@itemize @bullet
7633@item int64x2_t vld1q_s64 (const int64_t *)
7634@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7635@end itemize
7636
7637
7638@itemize @bullet
7639@item float32x4_t vld1q_f32 (const float32_t *)
7640@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7641@end itemize
7642
7643
7644@itemize @bullet
7645@item poly16x8_t vld1q_p16 (const poly16_t *)
7646@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7647@end itemize
7648
7649
7650@itemize @bullet
7651@item poly8x16_t vld1q_p8 (const poly8_t *)
7652@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7653@end itemize
7654
7655
7656@itemize @bullet
7657@item uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int)
7658@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7659@end itemize
7660
7661
7662@itemize @bullet
7663@item uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int)
7664@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7665@end itemize
7666
7667
7668@itemize @bullet
7669@item uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int)
7670@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7671@end itemize
7672
7673
7674@itemize @bullet
7675@item int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int)
7676@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7677@end itemize
7678
7679
7680@itemize @bullet
7681@item int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int)
7682@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7683@end itemize
7684
7685
7686@itemize @bullet
7687@item int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int)
7688@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7689@end itemize
7690
7691
7692@itemize @bullet
7693@item float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int)
7694@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7695@end itemize
7696
7697
7698@itemize @bullet
7699@item poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int)
7700@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7701@end itemize
7702
7703
7704@itemize @bullet
7705@item poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int)
7706@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7707@end itemize
7708
7709
7710@itemize @bullet
7711@item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int)
7712@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7713@end itemize
7714
7715
7716@itemize @bullet
7717@item int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int)
7718@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7719@end itemize
7720
7721
7722@itemize @bullet
7723@item uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int)
7724@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7725@end itemize
7726
7727
7728@itemize @bullet
7729@item uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int)
7730@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7731@end itemize
7732
7733
7734@itemize @bullet
7735@item uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int)
7736@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7737@end itemize
7738
7739
7740@itemize @bullet
7741@item int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int)
7742@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7743@end itemize
7744
7745
7746@itemize @bullet
7747@item int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int)
7748@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7749@end itemize
7750
7751
7752@itemize @bullet
7753@item int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int)
7754@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7755@end itemize
7756
7757
7758@itemize @bullet
7759@item float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int)
7760@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7761@end itemize
7762
7763
7764@itemize @bullet
7765@item poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int)
7766@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7767@end itemize
7768
7769
7770@itemize @bullet
7771@item poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int)
7772@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7773@end itemize
7774
7775
7776@itemize @bullet
7777@item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int)
7778@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7779@end itemize
7780
7781
7782@itemize @bullet
7783@item int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int)
7784@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7785@end itemize
7786
7787
7788@itemize @bullet
7789@item uint32x2_t vld1_dup_u32 (const uint32_t *)
7790@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7791@end itemize
7792
7793
7794@itemize @bullet
7795@item uint16x4_t vld1_dup_u16 (const uint16_t *)
7796@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7797@end itemize
7798
7799
7800@itemize @bullet
7801@item uint8x8_t vld1_dup_u8 (const uint8_t *)
7802@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7803@end itemize
7804
7805
7806@itemize @bullet
7807@item int32x2_t vld1_dup_s32 (const int32_t *)
7808@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7809@end itemize
7810
7811
7812@itemize @bullet
7813@item int16x4_t vld1_dup_s16 (const int16_t *)
7814@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7815@end itemize
7816
7817
7818@itemize @bullet
7819@item int8x8_t vld1_dup_s8 (const int8_t *)
7820@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7821@end itemize
7822
7823
7824@itemize @bullet
7825@item float32x2_t vld1_dup_f32 (const float32_t *)
7826@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7827@end itemize
7828
7829
7830@itemize @bullet
7831@item poly16x4_t vld1_dup_p16 (const poly16_t *)
7832@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7833@end itemize
7834
7835
7836@itemize @bullet
7837@item poly8x8_t vld1_dup_p8 (const poly8_t *)
7838@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7839@end itemize
7840
7841
7842@itemize @bullet
7843@item uint64x1_t vld1_dup_u64 (const uint64_t *)
7844@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7845@end itemize
7846
7847
7848@itemize @bullet
7849@item int64x1_t vld1_dup_s64 (const int64_t *)
7850@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7851@end itemize
7852
7853
7854@itemize @bullet
7855@item uint32x4_t vld1q_dup_u32 (const uint32_t *)
7856@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7857@end itemize
7858
7859
7860@itemize @bullet
7861@item uint16x8_t vld1q_dup_u16 (const uint16_t *)
7862@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7863@end itemize
7864
7865
7866@itemize @bullet
7867@item uint8x16_t vld1q_dup_u8 (const uint8_t *)
7868@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7869@end itemize
7870
7871
7872@itemize @bullet
7873@item int32x4_t vld1q_dup_s32 (const int32_t *)
7874@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7875@end itemize
7876
7877
7878@itemize @bullet
7879@item int16x8_t vld1q_dup_s16 (const int16_t *)
7880@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7881@end itemize
7882
7883
7884@itemize @bullet
7885@item int8x16_t vld1q_dup_s8 (const int8_t *)
7886@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7887@end itemize
7888
7889
7890@itemize @bullet
7891@item float32x4_t vld1q_dup_f32 (const float32_t *)
7892@*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7893@end itemize
7894
7895
7896@itemize @bullet
7897@item poly16x8_t vld1q_dup_p16 (const poly16_t *)
7898@*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7899@end itemize
7900
7901
7902@itemize @bullet
7903@item poly8x16_t vld1q_dup_p8 (const poly8_t *)
7904@*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7905@end itemize
7906
7907
7908@itemize @bullet
7909@item uint64x2_t vld1q_dup_u64 (const uint64_t *)
7910@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7911@end itemize
7912
7913
7914@itemize @bullet
7915@item int64x2_t vld1q_dup_s64 (const int64_t *)
7916@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7917@end itemize
7918
7919
7920
7921
7922@subsubsection Element/structure stores, VST1 variants
7923
7924@itemize @bullet
7925@item void vst1_u32 (uint32_t *, uint32x2_t)
7926@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7927@end itemize
7928
7929
7930@itemize @bullet
7931@item void vst1_u16 (uint16_t *, uint16x4_t)
7932@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7933@end itemize
7934
7935
7936@itemize @bullet
7937@item void vst1_u8 (uint8_t *, uint8x8_t)
7938@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
7939@end itemize
7940
7941
7942@itemize @bullet
7943@item void vst1_s32 (int32_t *, int32x2_t)
7944@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7945@end itemize
7946
7947
7948@itemize @bullet
7949@item void vst1_s16 (int16_t *, int16x4_t)
7950@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7951@end itemize
7952
7953
7954@itemize @bullet
7955@item void vst1_s8 (int8_t *, int8x8_t)
7956@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
7957@end itemize
7958
7959
7960@itemize @bullet
7961@item void vst1_u64 (uint64_t *, uint64x1_t)
7962@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
7963@end itemize
7964
7965
7966@itemize @bullet
7967@item void vst1_s64 (int64_t *, int64x1_t)
7968@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
7969@end itemize
7970
7971
7972@itemize @bullet
7973@item void vst1_f32 (float32_t *, float32x2_t)
7974@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7975@end itemize
7976
7977
7978@itemize @bullet
7979@item void vst1_p16 (poly16_t *, poly16x4_t)
7980@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7981@end itemize
7982
7983
7984@itemize @bullet
7985@item void vst1_p8 (poly8_t *, poly8x8_t)
7986@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
7987@end itemize
7988
7989
7990@itemize @bullet
7991@item void vst1q_u32 (uint32_t *, uint32x4_t)
7992@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7993@end itemize
7994
7995
7996@itemize @bullet
7997@item void vst1q_u16 (uint16_t *, uint16x8_t)
7998@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7999@end itemize
8000
8001
8002@itemize @bullet
8003@item void vst1q_u8 (uint8_t *, uint8x16_t)
8004@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8005@end itemize
8006
8007
8008@itemize @bullet
8009@item void vst1q_s32 (int32_t *, int32x4_t)
8010@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8011@end itemize
8012
8013
8014@itemize @bullet
8015@item void vst1q_s16 (int16_t *, int16x8_t)
8016@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8017@end itemize
8018
8019
8020@itemize @bullet
8021@item void vst1q_s8 (int8_t *, int8x16_t)
8022@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8023@end itemize
8024
8025
8026@itemize @bullet
8027@item void vst1q_u64 (uint64_t *, uint64x2_t)
8028@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8029@end itemize
8030
8031
8032@itemize @bullet
8033@item void vst1q_s64 (int64_t *, int64x2_t)
8034@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8035@end itemize
8036
8037
8038@itemize @bullet
8039@item void vst1q_f32 (float32_t *, float32x4_t)
8040@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8041@end itemize
8042
8043
8044@itemize @bullet
8045@item void vst1q_p16 (poly16_t *, poly16x8_t)
8046@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8047@end itemize
8048
8049
8050@itemize @bullet
8051@item void vst1q_p8 (poly8_t *, poly8x16_t)
8052@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8053@end itemize
8054
8055
8056@itemize @bullet
8057@item void vst1_lane_u32 (uint32_t *, uint32x2_t, const int)
8058@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8059@end itemize
8060
8061
8062@itemize @bullet
8063@item void vst1_lane_u16 (uint16_t *, uint16x4_t, const int)
8064@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8065@end itemize
8066
8067
8068@itemize @bullet
8069@item void vst1_lane_u8 (uint8_t *, uint8x8_t, const int)
8070@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8071@end itemize
8072
8073
8074@itemize @bullet
8075@item void vst1_lane_s32 (int32_t *, int32x2_t, const int)
8076@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8077@end itemize
8078
8079
8080@itemize @bullet
8081@item void vst1_lane_s16 (int16_t *, int16x4_t, const int)
8082@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8083@end itemize
8084
8085
8086@itemize @bullet
8087@item void vst1_lane_s8 (int8_t *, int8x8_t, const int)
8088@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8089@end itemize
8090
8091
8092@itemize @bullet
8093@item void vst1_lane_f32 (float32_t *, float32x2_t, const int)
8094@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8095@end itemize
8096
8097
8098@itemize @bullet
8099@item void vst1_lane_p16 (poly16_t *, poly16x4_t, const int)
8100@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8101@end itemize
8102
8103
8104@itemize @bullet
8105@item void vst1_lane_p8 (poly8_t *, poly8x8_t, const int)
8106@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8107@end itemize
8108
8109
8110@itemize @bullet
8111@item void vst1_lane_s64 (int64_t *, int64x1_t, const int)
8112@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8113@end itemize
8114
8115
8116@itemize @bullet
8117@item void vst1_lane_u64 (uint64_t *, uint64x1_t, const int)
8118@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8119@end itemize
8120
8121
8122@itemize @bullet
8123@item void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int)
8124@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8125@end itemize
8126
8127
8128@itemize @bullet
8129@item void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int)
8130@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8131@end itemize
8132
8133
8134@itemize @bullet
8135@item void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int)
8136@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8137@end itemize
8138
8139
8140@itemize @bullet
8141@item void vst1q_lane_s32 (int32_t *, int32x4_t, const int)
8142@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8143@end itemize
8144
8145
8146@itemize @bullet
8147@item void vst1q_lane_s16 (int16_t *, int16x8_t, const int)
8148@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8149@end itemize
8150
8151
8152@itemize @bullet
8153@item void vst1q_lane_s8 (int8_t *, int8x16_t, const int)
8154@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8155@end itemize
8156
8157
8158@itemize @bullet
8159@item void vst1q_lane_f32 (float32_t *, float32x4_t, const int)
8160@*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8161@end itemize
8162
8163
8164@itemize @bullet
8165@item void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int)
8166@*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8167@end itemize
8168
8169
8170@itemize @bullet
8171@item void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int)
8172@*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8173@end itemize
8174
8175
8176@itemize @bullet
8177@item void vst1q_lane_s64 (int64_t *, int64x2_t, const int)
8178@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8179@end itemize
8180
8181
8182@itemize @bullet
8183@item void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int)
8184@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8185@end itemize
8186
8187
8188
8189
8190@subsubsection Element/structure loads, VLD2 variants
8191
8192@itemize @bullet
8193@item uint32x2x2_t vld2_u32 (const uint32_t *)
8194@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8195@end itemize
8196
8197
8198@itemize @bullet
8199@item uint16x4x2_t vld2_u16 (const uint16_t *)
8200@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8201@end itemize
8202
8203
8204@itemize @bullet
8205@item uint8x8x2_t vld2_u8 (const uint8_t *)
8206@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8207@end itemize
8208
8209
8210@itemize @bullet
8211@item int32x2x2_t vld2_s32 (const int32_t *)
8212@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8213@end itemize
8214
8215
8216@itemize @bullet
8217@item int16x4x2_t vld2_s16 (const int16_t *)
8218@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8219@end itemize
8220
8221
8222@itemize @bullet
8223@item int8x8x2_t vld2_s8 (const int8_t *)
8224@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8225@end itemize
8226
8227
8228@itemize @bullet
8229@item float32x2x2_t vld2_f32 (const float32_t *)
8230@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8231@end itemize
8232
8233
8234@itemize @bullet
8235@item poly16x4x2_t vld2_p16 (const poly16_t *)
8236@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8237@end itemize
8238
8239
8240@itemize @bullet
8241@item poly8x8x2_t vld2_p8 (const poly8_t *)
8242@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8243@end itemize
8244
8245
8246@itemize @bullet
8247@item uint64x1x2_t vld2_u64 (const uint64_t *)
8248@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8249@end itemize
8250
8251
8252@itemize @bullet
8253@item int64x1x2_t vld2_s64 (const int64_t *)
8254@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8255@end itemize
8256
8257
8258@itemize @bullet
8259@item uint32x4x2_t vld2q_u32 (const uint32_t *)
8260@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8261@end itemize
8262
8263
8264@itemize @bullet
8265@item uint16x8x2_t vld2q_u16 (const uint16_t *)
8266@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8267@end itemize
8268
8269
8270@itemize @bullet
8271@item uint8x16x2_t vld2q_u8 (const uint8_t *)
8272@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8273@end itemize
8274
8275
8276@itemize @bullet
8277@item int32x4x2_t vld2q_s32 (const int32_t *)
8278@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8279@end itemize
8280
8281
8282@itemize @bullet
8283@item int16x8x2_t vld2q_s16 (const int16_t *)
8284@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8285@end itemize
8286
8287
8288@itemize @bullet
8289@item int8x16x2_t vld2q_s8 (const int8_t *)
8290@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8291@end itemize
8292
8293
8294@itemize @bullet
8295@item float32x4x2_t vld2q_f32 (const float32_t *)
8296@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8297@end itemize
8298
8299
8300@itemize @bullet
8301@item poly16x8x2_t vld2q_p16 (const poly16_t *)
8302@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8303@end itemize
8304
8305
8306@itemize @bullet
8307@item poly8x16x2_t vld2q_p8 (const poly8_t *)
8308@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8309@end itemize
8310
8311
8312@itemize @bullet
8313@item uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int)
8314@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8315@end itemize
8316
8317
8318@itemize @bullet
8319@item uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int)
8320@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8321@end itemize
8322
8323
8324@itemize @bullet
8325@item uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int)
8326@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8327@end itemize
8328
8329
8330@itemize @bullet
8331@item int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int)
8332@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8333@end itemize
8334
8335
8336@itemize @bullet
8337@item int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int)
8338@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8339@end itemize
8340
8341
8342@itemize @bullet
8343@item int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int)
8344@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8345@end itemize
8346
8347
8348@itemize @bullet
8349@item float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int)
8350@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8351@end itemize
8352
8353
8354@itemize @bullet
8355@item poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int)
8356@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8357@end itemize
8358
8359
8360@itemize @bullet
8361@item poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int)
8362@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8363@end itemize
8364
8365
8366@itemize @bullet
8367@item int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int)
8368@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8369@end itemize
8370
8371
8372@itemize @bullet
8373@item int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int)
8374@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8375@end itemize
8376
8377
8378@itemize @bullet
8379@item uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int)
8380@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8381@end itemize
8382
8383
8384@itemize @bullet
8385@item uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int)
8386@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8387@end itemize
8388
8389
8390@itemize @bullet
8391@item float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int)
8392@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8393@end itemize
8394
8395
8396@itemize @bullet
8397@item poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int)
8398@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8399@end itemize
8400
8401
8402@itemize @bullet
8403@item uint32x2x2_t vld2_dup_u32 (const uint32_t *)
8404@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8405@end itemize
8406
8407
8408@itemize @bullet
8409@item uint16x4x2_t vld2_dup_u16 (const uint16_t *)
8410@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8411@end itemize
8412
8413
8414@itemize @bullet
8415@item uint8x8x2_t vld2_dup_u8 (const uint8_t *)
8416@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8417@end itemize
8418
8419
8420@itemize @bullet
8421@item int32x2x2_t vld2_dup_s32 (const int32_t *)
8422@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8423@end itemize
8424
8425
8426@itemize @bullet
8427@item int16x4x2_t vld2_dup_s16 (const int16_t *)
8428@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8429@end itemize
8430
8431
8432@itemize @bullet
8433@item int8x8x2_t vld2_dup_s8 (const int8_t *)
8434@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8435@end itemize
8436
8437
8438@itemize @bullet
8439@item float32x2x2_t vld2_dup_f32 (const float32_t *)
8440@*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8441@end itemize
8442
8443
8444@itemize @bullet
8445@item poly16x4x2_t vld2_dup_p16 (const poly16_t *)
8446@*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8447@end itemize
8448
8449
8450@itemize @bullet
8451@item poly8x8x2_t vld2_dup_p8 (const poly8_t *)
8452@*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8453@end itemize
8454
8455
8456@itemize @bullet
8457@item uint64x1x2_t vld2_dup_u64 (const uint64_t *)
8458@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8459@end itemize
8460
8461
8462@itemize @bullet
8463@item int64x1x2_t vld2_dup_s64 (const int64_t *)
8464@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8465@end itemize
8466
8467
8468
8469
8470@subsubsection Element/structure stores, VST2 variants
8471
8472@itemize @bullet
8473@item void vst2_u32 (uint32_t *, uint32x2x2_t)
8474@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8475@end itemize
8476
8477
8478@itemize @bullet
8479@item void vst2_u16 (uint16_t *, uint16x4x2_t)
8480@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8481@end itemize
8482
8483
8484@itemize @bullet
8485@item void vst2_u8 (uint8_t *, uint8x8x2_t)
8486@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8487@end itemize
8488
8489
8490@itemize @bullet
8491@item void vst2_s32 (int32_t *, int32x2x2_t)
8492@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8493@end itemize
8494
8495
8496@itemize @bullet
8497@item void vst2_s16 (int16_t *, int16x4x2_t)
8498@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8499@end itemize
8500
8501
8502@itemize @bullet
8503@item void vst2_s8 (int8_t *, int8x8x2_t)
8504@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8505@end itemize
8506
8507
8508@itemize @bullet
8509@item void vst2_f32 (float32_t *, float32x2x2_t)
8510@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8511@end itemize
8512
8513
8514@itemize @bullet
8515@item void vst2_p16 (poly16_t *, poly16x4x2_t)
8516@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8517@end itemize
8518
8519
8520@itemize @bullet
8521@item void vst2_p8 (poly8_t *, poly8x8x2_t)
8522@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8523@end itemize
8524
8525
8526@itemize @bullet
8527@item void vst2_u64 (uint64_t *, uint64x1x2_t)
8528@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8529@end itemize
8530
8531
8532@itemize @bullet
8533@item void vst2_s64 (int64_t *, int64x1x2_t)
8534@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8535@end itemize
8536
8537
8538@itemize @bullet
8539@item void vst2q_u32 (uint32_t *, uint32x4x2_t)
8540@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8541@end itemize
8542
8543
8544@itemize @bullet
8545@item void vst2q_u16 (uint16_t *, uint16x8x2_t)
8546@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8547@end itemize
8548
8549
8550@itemize @bullet
8551@item void vst2q_u8 (uint8_t *, uint8x16x2_t)
8552@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8553@end itemize
8554
8555
8556@itemize @bullet
8557@item void vst2q_s32 (int32_t *, int32x4x2_t)
8558@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8559@end itemize
8560
8561
8562@itemize @bullet
8563@item void vst2q_s16 (int16_t *, int16x8x2_t)
8564@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8565@end itemize
8566
8567
8568@itemize @bullet
8569@item void vst2q_s8 (int8_t *, int8x16x2_t)
8570@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8571@end itemize
8572
8573
8574@itemize @bullet
8575@item void vst2q_f32 (float32_t *, float32x4x2_t)
8576@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8577@end itemize
8578
8579
8580@itemize @bullet
8581@item void vst2q_p16 (poly16_t *, poly16x8x2_t)
8582@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8583@end itemize
8584
8585
8586@itemize @bullet
8587@item void vst2q_p8 (poly8_t *, poly8x16x2_t)
8588@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8589@end itemize
8590
8591
8592@itemize @bullet
8593@item void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int)
8594@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8595@end itemize
8596
8597
8598@itemize @bullet
8599@item void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int)
8600@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8601@end itemize
8602
8603
8604@itemize @bullet
8605@item void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int)
8606@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8607@end itemize
8608
8609
8610@itemize @bullet
8611@item void vst2_lane_s32 (int32_t *, int32x2x2_t, const int)
8612@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8613@end itemize
8614
8615
8616@itemize @bullet
8617@item void vst2_lane_s16 (int16_t *, int16x4x2_t, const int)
8618@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8619@end itemize
8620
8621
8622@itemize @bullet
8623@item void vst2_lane_s8 (int8_t *, int8x8x2_t, const int)
8624@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8625@end itemize
8626
8627
8628@itemize @bullet
8629@item void vst2_lane_f32 (float32_t *, float32x2x2_t, const int)
8630@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8631@end itemize
8632
8633
8634@itemize @bullet
8635@item void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int)
8636@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8637@end itemize
8638
8639
8640@itemize @bullet
8641@item void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int)
8642@*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8643@end itemize
8644
8645
8646@itemize @bullet
8647@item void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int)
8648@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8649@end itemize
8650
8651
8652@itemize @bullet
8653@item void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int)
8654@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8655@end itemize
8656
8657
8658@itemize @bullet
8659@item void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int)
8660@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8661@end itemize
8662
8663
8664@itemize @bullet
8665@item void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int)
8666@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8667@end itemize
8668
8669
8670@itemize @bullet
8671@item void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int)
8672@*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8673@end itemize
8674
8675
8676@itemize @bullet
8677@item void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int)
8678@*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8679@end itemize
8680
8681
8682
8683
8684@subsubsection Element/structure loads, VLD3 variants
8685
8686@itemize @bullet
8687@item uint32x2x3_t vld3_u32 (const uint32_t *)
8688@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8689@end itemize
8690
8691
8692@itemize @bullet
8693@item uint16x4x3_t vld3_u16 (const uint16_t *)
8694@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8695@end itemize
8696
8697
8698@itemize @bullet
8699@item uint8x8x3_t vld3_u8 (const uint8_t *)
8700@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8701@end itemize
8702
8703
8704@itemize @bullet
8705@item int32x2x3_t vld3_s32 (const int32_t *)
8706@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8707@end itemize
8708
8709
8710@itemize @bullet
8711@item int16x4x3_t vld3_s16 (const int16_t *)
8712@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8713@end itemize
8714
8715
8716@itemize @bullet
8717@item int8x8x3_t vld3_s8 (const int8_t *)
8718@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8719@end itemize
8720
8721
8722@itemize @bullet
8723@item float32x2x3_t vld3_f32 (const float32_t *)
8724@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8725@end itemize
8726
8727
8728@itemize @bullet
8729@item poly16x4x3_t vld3_p16 (const poly16_t *)
8730@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8731@end itemize
8732
8733
8734@itemize @bullet
8735@item poly8x8x3_t vld3_p8 (const poly8_t *)
8736@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8737@end itemize
8738
8739
8740@itemize @bullet
8741@item uint64x1x3_t vld3_u64 (const uint64_t *)
8742@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8743@end itemize
8744
8745
8746@itemize @bullet
8747@item int64x1x3_t vld3_s64 (const int64_t *)
8748@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8749@end itemize
8750
8751
8752@itemize @bullet
8753@item uint32x4x3_t vld3q_u32 (const uint32_t *)
8754@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8755@end itemize
8756
8757
8758@itemize @bullet
8759@item uint16x8x3_t vld3q_u16 (const uint16_t *)
8760@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8761@end itemize
8762
8763
8764@itemize @bullet
8765@item uint8x16x3_t vld3q_u8 (const uint8_t *)
8766@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8767@end itemize
8768
8769
8770@itemize @bullet
8771@item int32x4x3_t vld3q_s32 (const int32_t *)
8772@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8773@end itemize
8774
8775
8776@itemize @bullet
8777@item int16x8x3_t vld3q_s16 (const int16_t *)
8778@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8779@end itemize
8780
8781
8782@itemize @bullet
8783@item int8x16x3_t vld3q_s8 (const int8_t *)
8784@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8785@end itemize
8786
8787
8788@itemize @bullet
8789@item float32x4x3_t vld3q_f32 (const float32_t *)
8790@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8791@end itemize
8792
8793
8794@itemize @bullet
8795@item poly16x8x3_t vld3q_p16 (const poly16_t *)
8796@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8797@end itemize
8798
8799
8800@itemize @bullet
8801@item poly8x16x3_t vld3q_p8 (const poly8_t *)
8802@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8803@end itemize
8804
8805
8806@itemize @bullet
8807@item uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int)
8808@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8809@end itemize
8810
8811
8812@itemize @bullet
8813@item uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int)
8814@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8815@end itemize
8816
8817
8818@itemize @bullet
8819@item uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int)
8820@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8821@end itemize
8822
8823
8824@itemize @bullet
8825@item int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int)
8826@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8827@end itemize
8828
8829
8830@itemize @bullet
8831@item int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int)
8832@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8833@end itemize
8834
8835
8836@itemize @bullet
8837@item int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int)
8838@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8839@end itemize
8840
8841
8842@itemize @bullet
8843@item float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int)
8844@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8845@end itemize
8846
8847
8848@itemize @bullet
8849@item poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int)
8850@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8851@end itemize
8852
8853
8854@itemize @bullet
8855@item poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int)
8856@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8857@end itemize
8858
8859
8860@itemize @bullet
8861@item int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int)
8862@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8863@end itemize
8864
8865
8866@itemize @bullet
8867@item int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int)
8868@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8869@end itemize
8870
8871
8872@itemize @bullet
8873@item uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int)
8874@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8875@end itemize
8876
8877
8878@itemize @bullet
8879@item uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int)
8880@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8881@end itemize
8882
8883
8884@itemize @bullet
8885@item float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int)
8886@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8887@end itemize
8888
8889
8890@itemize @bullet
8891@item poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int)
8892@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8893@end itemize
8894
8895
8896@itemize @bullet
8897@item uint32x2x3_t vld3_dup_u32 (const uint32_t *)
8898@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8899@end itemize
8900
8901
8902@itemize @bullet
8903@item uint16x4x3_t vld3_dup_u16 (const uint16_t *)
8904@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8905@end itemize
8906
8907
8908@itemize @bullet
8909@item uint8x8x3_t vld3_dup_u8 (const uint8_t *)
8910@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8911@end itemize
8912
8913
8914@itemize @bullet
8915@item int32x2x3_t vld3_dup_s32 (const int32_t *)
8916@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8917@end itemize
8918
8919
8920@itemize @bullet
8921@item int16x4x3_t vld3_dup_s16 (const int16_t *)
8922@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8923@end itemize
8924
8925
8926@itemize @bullet
8927@item int8x8x3_t vld3_dup_s8 (const int8_t *)
8928@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8929@end itemize
8930
8931
8932@itemize @bullet
8933@item float32x2x3_t vld3_dup_f32 (const float32_t *)
8934@*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8935@end itemize
8936
8937
8938@itemize @bullet
8939@item poly16x4x3_t vld3_dup_p16 (const poly16_t *)
8940@*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8941@end itemize
8942
8943
8944@itemize @bullet
8945@item poly8x8x3_t vld3_dup_p8 (const poly8_t *)
8946@*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8947@end itemize
8948
8949
8950@itemize @bullet
8951@item uint64x1x3_t vld3_dup_u64 (const uint64_t *)
8952@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8953@end itemize
8954
8955
8956@itemize @bullet
8957@item int64x1x3_t vld3_dup_s64 (const int64_t *)
8958@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8959@end itemize
8960
8961
8962
8963
8964@subsubsection Element/structure stores, VST3 variants
8965
8966@itemize @bullet
8967@item void vst3_u32 (uint32_t *, uint32x2x3_t)
8968@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8969@end itemize
8970
8971
8972@itemize @bullet
8973@item void vst3_u16 (uint16_t *, uint16x4x3_t)
8974@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8975@end itemize
8976
8977
8978@itemize @bullet
8979@item void vst3_u8 (uint8_t *, uint8x8x3_t)
8980@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8981@end itemize
8982
8983
8984@itemize @bullet
8985@item void vst3_s32 (int32_t *, int32x2x3_t)
8986@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8987@end itemize
8988
8989
8990@itemize @bullet
8991@item void vst3_s16 (int16_t *, int16x4x3_t)
8992@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8993@end itemize
8994
8995
8996@itemize @bullet
8997@item void vst3_s8 (int8_t *, int8x8x3_t)
8998@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8999@end itemize
9000
9001
9002@itemize @bullet
9003@item void vst3_f32 (float32_t *, float32x2x3_t)
9004@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9005@end itemize
9006
9007
9008@itemize @bullet
9009@item void vst3_p16 (poly16_t *, poly16x4x3_t)
9010@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9011@end itemize
9012
9013
9014@itemize @bullet
9015@item void vst3_p8 (poly8_t *, poly8x8x3_t)
9016@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9017@end itemize
9018
9019
9020@itemize @bullet
9021@item void vst3_u64 (uint64_t *, uint64x1x3_t)
9022@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9023@end itemize
9024
9025
9026@itemize @bullet
9027@item void vst3_s64 (int64_t *, int64x1x3_t)
9028@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9029@end itemize
9030
9031
9032@itemize @bullet
9033@item void vst3q_u32 (uint32_t *, uint32x4x3_t)
9034@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9035@end itemize
9036
9037
9038@itemize @bullet
9039@item void vst3q_u16 (uint16_t *, uint16x8x3_t)
9040@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9041@end itemize
9042
9043
9044@itemize @bullet
9045@item void vst3q_u8 (uint8_t *, uint8x16x3_t)
9046@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9047@end itemize
9048
9049
9050@itemize @bullet
9051@item void vst3q_s32 (int32_t *, int32x4x3_t)
9052@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9053@end itemize
9054
9055
9056@itemize @bullet
9057@item void vst3q_s16 (int16_t *, int16x8x3_t)
9058@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9059@end itemize
9060
9061
9062@itemize @bullet
9063@item void vst3q_s8 (int8_t *, int8x16x3_t)
9064@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9065@end itemize
9066
9067
9068@itemize @bullet
9069@item void vst3q_f32 (float32_t *, float32x4x3_t)
9070@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9071@end itemize
9072
9073
9074@itemize @bullet
9075@item void vst3q_p16 (poly16_t *, poly16x8x3_t)
9076@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9077@end itemize
9078
9079
9080@itemize @bullet
9081@item void vst3q_p8 (poly8_t *, poly8x16x3_t)
9082@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9083@end itemize
9084
9085
9086@itemize @bullet
9087@item void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int)
9088@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9089@end itemize
9090
9091
9092@itemize @bullet
9093@item void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int)
9094@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9095@end itemize
9096
9097
9098@itemize @bullet
9099@item void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int)
9100@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9101@end itemize
9102
9103
9104@itemize @bullet
9105@item void vst3_lane_s32 (int32_t *, int32x2x3_t, const int)
9106@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9107@end itemize
9108
9109
9110@itemize @bullet
9111@item void vst3_lane_s16 (int16_t *, int16x4x3_t, const int)
9112@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9113@end itemize
9114
9115
9116@itemize @bullet
9117@item void vst3_lane_s8 (int8_t *, int8x8x3_t, const int)
9118@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9119@end itemize
9120
9121
9122@itemize @bullet
9123@item void vst3_lane_f32 (float32_t *, float32x2x3_t, const int)
9124@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9125@end itemize
9126
9127
9128@itemize @bullet
9129@item void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int)
9130@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9131@end itemize
9132
9133
9134@itemize @bullet
9135@item void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int)
9136@*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9137@end itemize
9138
9139
9140@itemize @bullet
9141@item void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int)
9142@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9143@end itemize
9144
9145
9146@itemize @bullet
9147@item void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int)
9148@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9149@end itemize
9150
9151
9152@itemize @bullet
9153@item void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int)
9154@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9155@end itemize
9156
9157
9158@itemize @bullet
9159@item void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int)
9160@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9161@end itemize
9162
9163
9164@itemize @bullet
9165@item void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int)
9166@*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9167@end itemize
9168
9169
9170@itemize @bullet
9171@item void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int)
9172@*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9173@end itemize
9174
9175
9176
9177
9178@subsubsection Element/structure loads, VLD4 variants
9179
9180@itemize @bullet
9181@item uint32x2x4_t vld4_u32 (const uint32_t *)
9182@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9183@end itemize
9184
9185
9186@itemize @bullet
9187@item uint16x4x4_t vld4_u16 (const uint16_t *)
9188@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9189@end itemize
9190
9191
9192@itemize @bullet
9193@item uint8x8x4_t vld4_u8 (const uint8_t *)
9194@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9195@end itemize
9196
9197
9198@itemize @bullet
9199@item int32x2x4_t vld4_s32 (const int32_t *)
9200@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9201@end itemize
9202
9203
9204@itemize @bullet
9205@item int16x4x4_t vld4_s16 (const int16_t *)
9206@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9207@end itemize
9208
9209
9210@itemize @bullet
9211@item int8x8x4_t vld4_s8 (const int8_t *)
9212@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9213@end itemize
9214
9215
9216@itemize @bullet
9217@item float32x2x4_t vld4_f32 (const float32_t *)
9218@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9219@end itemize
9220
9221
9222@itemize @bullet
9223@item poly16x4x4_t vld4_p16 (const poly16_t *)
9224@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9225@end itemize
9226
9227
9228@itemize @bullet
9229@item poly8x8x4_t vld4_p8 (const poly8_t *)
9230@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9231@end itemize
9232
9233
9234@itemize @bullet
9235@item uint64x1x4_t vld4_u64 (const uint64_t *)
9236@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9237@end itemize
9238
9239
9240@itemize @bullet
9241@item int64x1x4_t vld4_s64 (const int64_t *)
9242@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9243@end itemize
9244
9245
9246@itemize @bullet
9247@item uint32x4x4_t vld4q_u32 (const uint32_t *)
9248@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9249@end itemize
9250
9251
9252@itemize @bullet
9253@item uint16x8x4_t vld4q_u16 (const uint16_t *)
9254@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9255@end itemize
9256
9257
9258@itemize @bullet
9259@item uint8x16x4_t vld4q_u8 (const uint8_t *)
9260@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9261@end itemize
9262
9263
9264@itemize @bullet
9265@item int32x4x4_t vld4q_s32 (const int32_t *)
9266@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9267@end itemize
9268
9269
9270@itemize @bullet
9271@item int16x8x4_t vld4q_s16 (const int16_t *)
9272@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9273@end itemize
9274
9275
9276@itemize @bullet
9277@item int8x16x4_t vld4q_s8 (const int8_t *)
9278@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9279@end itemize
9280
9281
9282@itemize @bullet
9283@item float32x4x4_t vld4q_f32 (const float32_t *)
9284@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9285@end itemize
9286
9287
9288@itemize @bullet
9289@item poly16x8x4_t vld4q_p16 (const poly16_t *)
9290@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9291@end itemize
9292
9293
9294@itemize @bullet
9295@item poly8x16x4_t vld4q_p8 (const poly8_t *)
9296@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9297@end itemize
9298
9299
9300@itemize @bullet
9301@item uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int)
9302@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9303@end itemize
9304
9305
9306@itemize @bullet
9307@item uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int)
9308@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9309@end itemize
9310
9311
9312@itemize @bullet
9313@item uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int)
9314@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9315@end itemize
9316
9317
9318@itemize @bullet
9319@item int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int)
9320@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9321@end itemize
9322
9323
9324@itemize @bullet
9325@item int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int)
9326@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9327@end itemize
9328
9329
9330@itemize @bullet
9331@item int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int)
9332@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9333@end itemize
9334
9335
9336@itemize @bullet
9337@item float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int)
9338@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9339@end itemize
9340
9341
9342@itemize @bullet
9343@item poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int)
9344@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9345@end itemize
9346
9347
9348@itemize @bullet
9349@item poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int)
9350@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9351@end itemize
9352
9353
9354@itemize @bullet
9355@item int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int)
9356@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9357@end itemize
9358
9359
9360@itemize @bullet
9361@item int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int)
9362@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9363@end itemize
9364
9365
9366@itemize @bullet
9367@item uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int)
9368@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9369@end itemize
9370
9371
9372@itemize @bullet
9373@item uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int)
9374@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9375@end itemize
9376
9377
9378@itemize @bullet
9379@item float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int)
9380@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9381@end itemize
9382
9383
9384@itemize @bullet
9385@item poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int)
9386@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9387@end itemize
9388
9389
9390@itemize @bullet
9391@item uint32x2x4_t vld4_dup_u32 (const uint32_t *)
9392@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9393@end itemize
9394
9395
9396@itemize @bullet
9397@item uint16x4x4_t vld4_dup_u16 (const uint16_t *)
9398@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9399@end itemize
9400
9401
9402@itemize @bullet
9403@item uint8x8x4_t vld4_dup_u8 (const uint8_t *)
9404@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9405@end itemize
9406
9407
9408@itemize @bullet
9409@item int32x2x4_t vld4_dup_s32 (const int32_t *)
9410@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9411@end itemize
9412
9413
9414@itemize @bullet
9415@item int16x4x4_t vld4_dup_s16 (const int16_t *)
9416@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9417@end itemize
9418
9419
9420@itemize @bullet
9421@item int8x8x4_t vld4_dup_s8 (const int8_t *)
9422@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9423@end itemize
9424
9425
9426@itemize @bullet
9427@item float32x2x4_t vld4_dup_f32 (const float32_t *)
9428@*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9429@end itemize
9430
9431
9432@itemize @bullet
9433@item poly16x4x4_t vld4_dup_p16 (const poly16_t *)
9434@*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9435@end itemize
9436
9437
9438@itemize @bullet
9439@item poly8x8x4_t vld4_dup_p8 (const poly8_t *)
9440@*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9441@end itemize
9442
9443
9444@itemize @bullet
9445@item uint64x1x4_t vld4_dup_u64 (const uint64_t *)
9446@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9447@end itemize
9448
9449
9450@itemize @bullet
9451@item int64x1x4_t vld4_dup_s64 (const int64_t *)
9452@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9453@end itemize
9454
9455
9456
9457
9458@subsubsection Element/structure stores, VST4 variants
9459
9460@itemize @bullet
9461@item void vst4_u32 (uint32_t *, uint32x2x4_t)
9462@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9463@end itemize
9464
9465
9466@itemize @bullet
9467@item void vst4_u16 (uint16_t *, uint16x4x4_t)
9468@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9469@end itemize
9470
9471
9472@itemize @bullet
9473@item void vst4_u8 (uint8_t *, uint8x8x4_t)
9474@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9475@end itemize
9476
9477
9478@itemize @bullet
9479@item void vst4_s32 (int32_t *, int32x2x4_t)
9480@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9481@end itemize
9482
9483
9484@itemize @bullet
9485@item void vst4_s16 (int16_t *, int16x4x4_t)
9486@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9487@end itemize
9488
9489
9490@itemize @bullet
9491@item void vst4_s8 (int8_t *, int8x8x4_t)
9492@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9493@end itemize
9494
9495
9496@itemize @bullet
9497@item void vst4_f32 (float32_t *, float32x2x4_t)
9498@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9499@end itemize
9500
9501
9502@itemize @bullet
9503@item void vst4_p16 (poly16_t *, poly16x4x4_t)
9504@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9505@end itemize
9506
9507
9508@itemize @bullet
9509@item void vst4_p8 (poly8_t *, poly8x8x4_t)
9510@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9511@end itemize
9512
9513
9514@itemize @bullet
9515@item void vst4_u64 (uint64_t *, uint64x1x4_t)
9516@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9517@end itemize
9518
9519
9520@itemize @bullet
9521@item void vst4_s64 (int64_t *, int64x1x4_t)
9522@*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9523@end itemize
9524
9525
9526@itemize @bullet
9527@item void vst4q_u32 (uint32_t *, uint32x4x4_t)
9528@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9529@end itemize
9530
9531
9532@itemize @bullet
9533@item void vst4q_u16 (uint16_t *, uint16x8x4_t)
9534@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9535@end itemize
9536
9537
9538@itemize @bullet
9539@item void vst4q_u8 (uint8_t *, uint8x16x4_t)
9540@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9541@end itemize
9542
9543
9544@itemize @bullet
9545@item void vst4q_s32 (int32_t *, int32x4x4_t)
9546@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9547@end itemize
9548
9549
9550@itemize @bullet
9551@item void vst4q_s16 (int16_t *, int16x8x4_t)
9552@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9553@end itemize
9554
9555
9556@itemize @bullet
9557@item void vst4q_s8 (int8_t *, int8x16x4_t)
9558@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9559@end itemize
9560
9561
9562@itemize @bullet
9563@item void vst4q_f32 (float32_t *, float32x4x4_t)
9564@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9565@end itemize
9566
9567
9568@itemize @bullet
9569@item void vst4q_p16 (poly16_t *, poly16x8x4_t)
9570@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9571@end itemize
9572
9573
9574@itemize @bullet
9575@item void vst4q_p8 (poly8_t *, poly8x16x4_t)
9576@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9577@end itemize
9578
9579
9580@itemize @bullet
9581@item void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int)
9582@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9583@end itemize
9584
9585
9586@itemize @bullet
9587@item void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int)
9588@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9589@end itemize
9590
9591
9592@itemize @bullet
9593@item void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int)
9594@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9595@end itemize
9596
9597
9598@itemize @bullet
9599@item void vst4_lane_s32 (int32_t *, int32x2x4_t, const int)
9600@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9601@end itemize
9602
9603
9604@itemize @bullet
9605@item void vst4_lane_s16 (int16_t *, int16x4x4_t, const int)
9606@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9607@end itemize
9608
9609
9610@itemize @bullet
9611@item void vst4_lane_s8 (int8_t *, int8x8x4_t, const int)
9612@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9613@end itemize
9614
9615
9616@itemize @bullet
9617@item void vst4_lane_f32 (float32_t *, float32x2x4_t, const int)
9618@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9619@end itemize
9620
9621
9622@itemize @bullet
9623@item void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int)
9624@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9625@end itemize
9626
9627
9628@itemize @bullet
9629@item void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int)
9630@*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9631@end itemize
9632
9633
9634@itemize @bullet
9635@item void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int)
9636@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9637@end itemize
9638
9639
9640@itemize @bullet
9641@item void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int)
9642@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9643@end itemize
9644
9645
9646@itemize @bullet
9647@item void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int)
9648@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9649@end itemize
9650
9651
9652@itemize @bullet
9653@item void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int)
9654@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9655@end itemize
9656
9657
9658@itemize @bullet
9659@item void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int)
9660@*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9661@end itemize
9662
9663
9664@itemize @bullet
9665@item void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int)
9666@*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9667@end itemize
9668
9669
9670
9671
9672@subsubsection Logical operations (AND)
9673
9674@itemize @bullet
9675@item uint32x2_t vand_u32 (uint32x2_t, uint32x2_t)
9676@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9677@end itemize
9678
9679
9680@itemize @bullet
9681@item uint16x4_t vand_u16 (uint16x4_t, uint16x4_t)
9682@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9683@end itemize
9684
9685
9686@itemize @bullet
9687@item uint8x8_t vand_u8 (uint8x8_t, uint8x8_t)
9688@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9689@end itemize
9690
9691
9692@itemize @bullet
9693@item int32x2_t vand_s32 (int32x2_t, int32x2_t)
9694@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9695@end itemize
9696
9697
9698@itemize @bullet
9699@item int16x4_t vand_s16 (int16x4_t, int16x4_t)
9700@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9701@end itemize
9702
9703
9704@itemize @bullet
9705@item int8x8_t vand_s8 (int8x8_t, int8x8_t)
9706@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9707@end itemize
9708
9709
9710@itemize @bullet
9711@item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
9712@end itemize
9713
9714
9715@itemize @bullet
9716@item int64x1_t vand_s64 (int64x1_t, int64x1_t)
9717@end itemize
9718
9719
9720@itemize @bullet
9721@item uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t)
9722@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9723@end itemize
9724
9725
9726@itemize @bullet
9727@item uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t)
9728@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9729@end itemize
9730
9731
9732@itemize @bullet
9733@item uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t)
9734@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9735@end itemize
9736
9737
9738@itemize @bullet
9739@item int32x4_t vandq_s32 (int32x4_t, int32x4_t)
9740@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9741@end itemize
9742
9743
9744@itemize @bullet
9745@item int16x8_t vandq_s16 (int16x8_t, int16x8_t)
9746@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9747@end itemize
9748
9749
9750@itemize @bullet
9751@item int8x16_t vandq_s8 (int8x16_t, int8x16_t)
9752@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9753@end itemize
9754
9755
9756@itemize @bullet
9757@item uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t)
9758@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9759@end itemize
9760
9761
9762@itemize @bullet
9763@item int64x2_t vandq_s64 (int64x2_t, int64x2_t)
9764@*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9765@end itemize
9766
9767
9768
9769
9770@subsubsection Logical operations (OR)
9771
9772@itemize @bullet
9773@item uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t)
9774@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9775@end itemize
9776
9777
9778@itemize @bullet
9779@item uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t)
9780@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9781@end itemize
9782
9783
9784@itemize @bullet
9785@item uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t)
9786@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9787@end itemize
9788
9789
9790@itemize @bullet
9791@item int32x2_t vorr_s32 (int32x2_t, int32x2_t)
9792@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9793@end itemize
9794
9795
9796@itemize @bullet
9797@item int16x4_t vorr_s16 (int16x4_t, int16x4_t)
9798@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9799@end itemize
9800
9801
9802@itemize @bullet
9803@item int8x8_t vorr_s8 (int8x8_t, int8x8_t)
9804@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9805@end itemize
9806
9807
9808@itemize @bullet
9809@item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
9810@end itemize
9811
9812
9813@itemize @bullet
9814@item int64x1_t vorr_s64 (int64x1_t, int64x1_t)
9815@end itemize
9816
9817
9818@itemize @bullet
9819@item uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t)
9820@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9821@end itemize
9822
9823
9824@itemize @bullet
9825@item uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t)
9826@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9827@end itemize
9828
9829
9830@itemize @bullet
9831@item uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t)
9832@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9833@end itemize
9834
9835
9836@itemize @bullet
9837@item int32x4_t vorrq_s32 (int32x4_t, int32x4_t)
9838@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9839@end itemize
9840
9841
9842@itemize @bullet
9843@item int16x8_t vorrq_s16 (int16x8_t, int16x8_t)
9844@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9845@end itemize
9846
9847
9848@itemize @bullet
9849@item int8x16_t vorrq_s8 (int8x16_t, int8x16_t)
9850@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9851@end itemize
9852
9853
9854@itemize @bullet
9855@item uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t)
9856@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9857@end itemize
9858
9859
9860@itemize @bullet
9861@item int64x2_t vorrq_s64 (int64x2_t, int64x2_t)
9862@*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9863@end itemize
9864
9865
9866
9867
9868@subsubsection Logical operations (exclusive OR)
9869
9870@itemize @bullet
9871@item uint32x2_t veor_u32 (uint32x2_t, uint32x2_t)
9872@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9873@end itemize
9874
9875
9876@itemize @bullet
9877@item uint16x4_t veor_u16 (uint16x4_t, uint16x4_t)
9878@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9879@end itemize
9880
9881
9882@itemize @bullet
9883@item uint8x8_t veor_u8 (uint8x8_t, uint8x8_t)
9884@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9885@end itemize
9886
9887
9888@itemize @bullet
9889@item int32x2_t veor_s32 (int32x2_t, int32x2_t)
9890@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9891@end itemize
9892
9893
9894@itemize @bullet
9895@item int16x4_t veor_s16 (int16x4_t, int16x4_t)
9896@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9897@end itemize
9898
9899
9900@itemize @bullet
9901@item int8x8_t veor_s8 (int8x8_t, int8x8_t)
9902@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9903@end itemize
9904
9905
9906@itemize @bullet
9907@item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
9908@end itemize
9909
9910
9911@itemize @bullet
9912@item int64x1_t veor_s64 (int64x1_t, int64x1_t)
9913@end itemize
9914
9915
9916@itemize @bullet
9917@item uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t)
9918@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9919@end itemize
9920
9921
9922@itemize @bullet
9923@item uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t)
9924@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9925@end itemize
9926
9927
9928@itemize @bullet
9929@item uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t)
9930@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9931@end itemize
9932
9933
9934@itemize @bullet
9935@item int32x4_t veorq_s32 (int32x4_t, int32x4_t)
9936@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9937@end itemize
9938
9939
9940@itemize @bullet
9941@item int16x8_t veorq_s16 (int16x8_t, int16x8_t)
9942@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9943@end itemize
9944
9945
9946@itemize @bullet
9947@item int8x16_t veorq_s8 (int8x16_t, int8x16_t)
9948@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9949@end itemize
9950
9951
9952@itemize @bullet
9953@item uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t)
9954@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9955@end itemize
9956
9957
9958@itemize @bullet
9959@item int64x2_t veorq_s64 (int64x2_t, int64x2_t)
9960@*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9961@end itemize
9962
9963
9964
9965
9966@subsubsection Logical operations (AND-NOT)
9967
9968@itemize @bullet
9969@item uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t)
9970@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9971@end itemize
9972
9973
9974@itemize @bullet
9975@item uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t)
9976@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9977@end itemize
9978
9979
9980@itemize @bullet
9981@item uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t)
9982@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9983@end itemize
9984
9985
9986@itemize @bullet
9987@item int32x2_t vbic_s32 (int32x2_t, int32x2_t)
9988@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9989@end itemize
9990
9991
9992@itemize @bullet
9993@item int16x4_t vbic_s16 (int16x4_t, int16x4_t)
9994@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9995@end itemize
9996
9997
9998@itemize @bullet
9999@item int8x8_t vbic_s8 (int8x8_t, int8x8_t)
10000@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10001@end itemize
10002
10003
10004@itemize @bullet
10005@item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
10006@end itemize
10007
10008
10009@itemize @bullet
10010@item int64x1_t vbic_s64 (int64x1_t, int64x1_t)
10011@end itemize
10012
10013
10014@itemize @bullet
10015@item uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t)
10016@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10017@end itemize
10018
10019
10020@itemize @bullet
10021@item uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t)
10022@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10023@end itemize
10024
10025
10026@itemize @bullet
10027@item uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t)
10028@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10029@end itemize
10030
10031
10032@itemize @bullet
10033@item int32x4_t vbicq_s32 (int32x4_t, int32x4_t)
10034@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10035@end itemize
10036
10037
10038@itemize @bullet
10039@item int16x8_t vbicq_s16 (int16x8_t, int16x8_t)
10040@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10041@end itemize
10042
10043
10044@itemize @bullet
10045@item int8x16_t vbicq_s8 (int8x16_t, int8x16_t)
10046@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10047@end itemize
10048
10049
10050@itemize @bullet
10051@item uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t)
10052@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10053@end itemize
10054
10055
10056@itemize @bullet
10057@item int64x2_t vbicq_s64 (int64x2_t, int64x2_t)
10058@*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10059@end itemize
10060
10061
10062
10063
10064@subsubsection Logical operations (OR-NOT)
10065
10066@itemize @bullet
10067@item uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t)
10068@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10069@end itemize
10070
10071
10072@itemize @bullet
10073@item uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t)
10074@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10075@end itemize
10076
10077
10078@itemize @bullet
10079@item uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t)
10080@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10081@end itemize
10082
10083
10084@itemize @bullet
10085@item int32x2_t vorn_s32 (int32x2_t, int32x2_t)
10086@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10087@end itemize
10088
10089
10090@itemize @bullet
10091@item int16x4_t vorn_s16 (int16x4_t, int16x4_t)
10092@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10093@end itemize
10094
10095
10096@itemize @bullet
10097@item int8x8_t vorn_s8 (int8x8_t, int8x8_t)
10098@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10099@end itemize
10100
10101
10102@itemize @bullet
10103@item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
10104@end itemize
10105
10106
10107@itemize @bullet
10108@item int64x1_t vorn_s64 (int64x1_t, int64x1_t)
10109@end itemize
10110
10111
10112@itemize @bullet
10113@item uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t)
10114@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10115@end itemize
10116
10117
10118@itemize @bullet
10119@item uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t)
10120@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10121@end itemize
10122
10123
10124@itemize @bullet
10125@item uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t)
10126@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10127@end itemize
10128
10129
10130@itemize @bullet
10131@item int32x4_t vornq_s32 (int32x4_t, int32x4_t)
10132@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10133@end itemize
10134
10135
10136@itemize @bullet
10137@item int16x8_t vornq_s16 (int16x8_t, int16x8_t)
10138@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10139@end itemize
10140
10141
10142@itemize @bullet
10143@item int8x16_t vornq_s8 (int8x16_t, int8x16_t)
10144@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10145@end itemize
10146
10147
10148@itemize @bullet
10149@item uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t)
10150@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10151@end itemize
10152
10153
10154@itemize @bullet
10155@item int64x2_t vornq_s64 (int64x2_t, int64x2_t)
10156@*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10157@end itemize
10158
10159
10160
10161
10162@subsubsection Reinterpret casts
10163
10164@itemize @bullet
10165@item poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
10166@end itemize
10167
10168
10169@itemize @bullet
10170@item poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
10171@end itemize
10172
10173
10174@itemize @bullet
10175@item poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
10176@end itemize
10177
10178
10179@itemize @bullet
10180@item poly8x8_t vreinterpret_p8_s32 (int32x2_t)
10181@end itemize
10182
10183
10184@itemize @bullet
10185@item poly8x8_t vreinterpret_p8_s16 (int16x4_t)
10186@end itemize
10187
10188
10189@itemize @bullet
10190@item poly8x8_t vreinterpret_p8_s8 (int8x8_t)
10191@end itemize
10192
10193
10194@itemize @bullet
10195@item poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
10196@end itemize
10197
10198
10199@itemize @bullet
10200@item poly8x8_t vreinterpret_p8_s64 (int64x1_t)
10201@end itemize
10202
10203
10204@itemize @bullet
10205@item poly8x8_t vreinterpret_p8_f32 (float32x2_t)
10206@end itemize
10207
10208
10209@itemize @bullet
10210@item poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
10211@end itemize
10212
10213
10214@itemize @bullet
10215@item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
10216@end itemize
10217
10218
10219@itemize @bullet
10220@item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
10221@end itemize
10222
10223
10224@itemize @bullet
10225@item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
10226@end itemize
10227
10228
10229@itemize @bullet
10230@item poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
10231@end itemize
10232
10233
10234@itemize @bullet
10235@item poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
10236@end itemize
10237
10238
10239@itemize @bullet
10240@item poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
10241@end itemize
10242
10243
10244@itemize @bullet
10245@item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
10246@end itemize
10247
10248
10249@itemize @bullet
10250@item poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
10251@end itemize
10252
10253
10254@itemize @bullet
10255@item poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
10256@end itemize
10257
10258
10259@itemize @bullet
10260@item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
10261@end itemize
10262
10263
10264@itemize @bullet
10265@item poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
10266@end itemize
10267
10268
10269@itemize @bullet
10270@item poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
10271@end itemize
10272
10273
10274@itemize @bullet
10275@item poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
10276@end itemize
10277
10278
10279@itemize @bullet
10280@item poly16x4_t vreinterpret_p16_s32 (int32x2_t)
10281@end itemize
10282
10283
10284@itemize @bullet
10285@item poly16x4_t vreinterpret_p16_s16 (int16x4_t)
10286@end itemize
10287
10288
10289@itemize @bullet
10290@item poly16x4_t vreinterpret_p16_s8 (int8x8_t)
10291@end itemize
10292
10293
10294@itemize @bullet
10295@item poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
10296@end itemize
10297
10298
10299@itemize @bullet
10300@item poly16x4_t vreinterpret_p16_s64 (int64x1_t)
10301@end itemize
10302
10303
10304@itemize @bullet
10305@item poly16x4_t vreinterpret_p16_f32 (float32x2_t)
10306@end itemize
10307
10308
10309@itemize @bullet
10310@item poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
10311@end itemize
10312
10313
10314@itemize @bullet
10315@item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
10316@end itemize
10317
10318
10319@itemize @bullet
10320@item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
10321@end itemize
10322
10323
10324@itemize @bullet
10325@item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
10326@end itemize
10327
10328
10329@itemize @bullet
10330@item poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
10331@end itemize
10332
10333
10334@itemize @bullet
10335@item poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
10336@end itemize
10337
10338
10339@itemize @bullet
10340@item poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
10341@end itemize
10342
10343
10344@itemize @bullet
10345@item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
10346@end itemize
10347
10348
10349@itemize @bullet
10350@item poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
10351@end itemize
10352
10353
10354@itemize @bullet
10355@item poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
10356@end itemize
10357
10358
10359@itemize @bullet
10360@item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
10361@end itemize
10362
10363
10364@itemize @bullet
10365@item float32x2_t vreinterpret_f32_u32 (uint32x2_t)
10366@end itemize
10367
10368
10369@itemize @bullet
10370@item float32x2_t vreinterpret_f32_u16 (uint16x4_t)
10371@end itemize
10372
10373
10374@itemize @bullet
10375@item float32x2_t vreinterpret_f32_u8 (uint8x8_t)
10376@end itemize
10377
10378
10379@itemize @bullet
10380@item float32x2_t vreinterpret_f32_s32 (int32x2_t)
10381@end itemize
10382
10383
10384@itemize @bullet
10385@item float32x2_t vreinterpret_f32_s16 (int16x4_t)
10386@end itemize
10387
10388
10389@itemize @bullet
10390@item float32x2_t vreinterpret_f32_s8 (int8x8_t)
10391@end itemize
10392
10393
10394@itemize @bullet
10395@item float32x2_t vreinterpret_f32_u64 (uint64x1_t)
10396@end itemize
10397
10398
10399@itemize @bullet
10400@item float32x2_t vreinterpret_f32_s64 (int64x1_t)
10401@end itemize
10402
10403
10404@itemize @bullet
10405@item float32x2_t vreinterpret_f32_p16 (poly16x4_t)
10406@end itemize
10407
10408
10409@itemize @bullet
10410@item float32x2_t vreinterpret_f32_p8 (poly8x8_t)
10411@end itemize
10412
10413
10414@itemize @bullet
10415@item float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
10416@end itemize
10417
10418
10419@itemize @bullet
10420@item float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
10421@end itemize
10422
10423
10424@itemize @bullet
10425@item float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
10426@end itemize
10427
10428
10429@itemize @bullet
10430@item float32x4_t vreinterpretq_f32_s32 (int32x4_t)
10431@end itemize
10432
10433
10434@itemize @bullet
10435@item float32x4_t vreinterpretq_f32_s16 (int16x8_t)
10436@end itemize
10437
10438
10439@itemize @bullet
10440@item float32x4_t vreinterpretq_f32_s8 (int8x16_t)
10441@end itemize
10442
10443
10444@itemize @bullet
10445@item float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
10446@end itemize
10447
10448
10449@itemize @bullet
10450@item float32x4_t vreinterpretq_f32_s64 (int64x2_t)
10451@end itemize
10452
10453
10454@itemize @bullet
10455@item float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
10456@end itemize
10457
10458
10459@itemize @bullet
10460@item float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
10461@end itemize
10462
10463
10464@itemize @bullet
10465@item int64x1_t vreinterpret_s64_u32 (uint32x2_t)
10466@end itemize
10467
10468
10469@itemize @bullet
10470@item int64x1_t vreinterpret_s64_u16 (uint16x4_t)
10471@end itemize
10472
10473
10474@itemize @bullet
10475@item int64x1_t vreinterpret_s64_u8 (uint8x8_t)
10476@end itemize
10477
10478
10479@itemize @bullet
10480@item int64x1_t vreinterpret_s64_s32 (int32x2_t)
10481@end itemize
10482
10483
10484@itemize @bullet
10485@item int64x1_t vreinterpret_s64_s16 (int16x4_t)
10486@end itemize
10487
10488
10489@itemize @bullet
10490@item int64x1_t vreinterpret_s64_s8 (int8x8_t)
10491@end itemize
10492
10493
10494@itemize @bullet
10495@item int64x1_t vreinterpret_s64_u64 (uint64x1_t)
10496@end itemize
10497
10498
10499@itemize @bullet
10500@item int64x1_t vreinterpret_s64_f32 (float32x2_t)
10501@end itemize
10502
10503
10504@itemize @bullet
10505@item int64x1_t vreinterpret_s64_p16 (poly16x4_t)
10506@end itemize
10507
10508
10509@itemize @bullet
10510@item int64x1_t vreinterpret_s64_p8 (poly8x8_t)
10511@end itemize
10512
10513
10514@itemize @bullet
10515@item int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
10516@end itemize
10517
10518
10519@itemize @bullet
10520@item int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
10521@end itemize
10522
10523
10524@itemize @bullet
10525@item int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
10526@end itemize
10527
10528
10529@itemize @bullet
10530@item int64x2_t vreinterpretq_s64_s32 (int32x4_t)
10531@end itemize
10532
10533
10534@itemize @bullet
10535@item int64x2_t vreinterpretq_s64_s16 (int16x8_t)
10536@end itemize
10537
10538
10539@itemize @bullet
10540@item int64x2_t vreinterpretq_s64_s8 (int8x16_t)
10541@end itemize
10542
10543
10544@itemize @bullet
10545@item int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
10546@end itemize
10547
10548
10549@itemize @bullet
10550@item int64x2_t vreinterpretq_s64_f32 (float32x4_t)
10551@end itemize
10552
10553
10554@itemize @bullet
10555@item int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
10556@end itemize
10557
10558
10559@itemize @bullet
10560@item int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
10561@end itemize
10562
10563
10564@itemize @bullet
10565@item uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
10566@end itemize
10567
10568
10569@itemize @bullet
10570@item uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
10571@end itemize
10572
10573
10574@itemize @bullet
10575@item uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
10576@end itemize
10577
10578
10579@itemize @bullet
10580@item uint64x1_t vreinterpret_u64_s32 (int32x2_t)
10581@end itemize
10582
10583
10584@itemize @bullet
10585@item uint64x1_t vreinterpret_u64_s16 (int16x4_t)
10586@end itemize
10587
10588
10589@itemize @bullet
10590@item uint64x1_t vreinterpret_u64_s8 (int8x8_t)
10591@end itemize
10592
10593
10594@itemize @bullet
10595@item uint64x1_t vreinterpret_u64_s64 (int64x1_t)
10596@end itemize
10597
10598
10599@itemize @bullet
10600@item uint64x1_t vreinterpret_u64_f32 (float32x2_t)
10601@end itemize
10602
10603
10604@itemize @bullet
10605@item uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
10606@end itemize
10607
10608
10609@itemize @bullet
10610@item uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
10611@end itemize
10612
10613
10614@itemize @bullet
10615@item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
10616@end itemize
10617
10618
10619@itemize @bullet
10620@item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
10621@end itemize
10622
10623
10624@itemize @bullet
10625@item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
10626@end itemize
10627
10628
10629@itemize @bullet
10630@item uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
10631@end itemize
10632
10633
10634@itemize @bullet
10635@item uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
10636@end itemize
10637
10638
10639@itemize @bullet
10640@item uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
10641@end itemize
10642
10643
10644@itemize @bullet
10645@item uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
10646@end itemize
10647
10648
10649@itemize @bullet
10650@item uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
10651@end itemize
10652
10653
10654@itemize @bullet
10655@item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
10656@end itemize
10657
10658
10659@itemize @bullet
10660@item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
10661@end itemize
10662
10663
10664@itemize @bullet
10665@item int8x8_t vreinterpret_s8_u32 (uint32x2_t)
10666@end itemize
10667
10668
10669@itemize @bullet
10670@item int8x8_t vreinterpret_s8_u16 (uint16x4_t)
10671@end itemize
10672
10673
10674@itemize @bullet
10675@item int8x8_t vreinterpret_s8_u8 (uint8x8_t)
10676@end itemize
10677
10678
10679@itemize @bullet
10680@item int8x8_t vreinterpret_s8_s32 (int32x2_t)
10681@end itemize
10682
10683
10684@itemize @bullet
10685@item int8x8_t vreinterpret_s8_s16 (int16x4_t)
10686@end itemize
10687
10688
10689@itemize @bullet
10690@item int8x8_t vreinterpret_s8_u64 (uint64x1_t)
10691@end itemize
10692
10693
10694@itemize @bullet
10695@item int8x8_t vreinterpret_s8_s64 (int64x1_t)
10696@end itemize
10697
10698
10699@itemize @bullet
10700@item int8x8_t vreinterpret_s8_f32 (float32x2_t)
10701@end itemize
10702
10703
10704@itemize @bullet
10705@item int8x8_t vreinterpret_s8_p16 (poly16x4_t)
10706@end itemize
10707
10708
10709@itemize @bullet
10710@item int8x8_t vreinterpret_s8_p8 (poly8x8_t)
10711@end itemize
10712
10713
10714@itemize @bullet
10715@item int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
10716@end itemize
10717
10718
10719@itemize @bullet
10720@item int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
10721@end itemize
10722
10723
10724@itemize @bullet
10725@item int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
10726@end itemize
10727
10728
10729@itemize @bullet
10730@item int8x16_t vreinterpretq_s8_s32 (int32x4_t)
10731@end itemize
10732
10733
10734@itemize @bullet
10735@item int8x16_t vreinterpretq_s8_s16 (int16x8_t)
10736@end itemize
10737
10738
10739@itemize @bullet
10740@item int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
10741@end itemize
10742
10743
10744@itemize @bullet
10745@item int8x16_t vreinterpretq_s8_s64 (int64x2_t)
10746@end itemize
10747
10748
10749@itemize @bullet
10750@item int8x16_t vreinterpretq_s8_f32 (float32x4_t)
10751@end itemize
10752
10753
10754@itemize @bullet
10755@item int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
10756@end itemize
10757
10758
10759@itemize @bullet
10760@item int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
10761@end itemize
10762
10763
10764@itemize @bullet
10765@item int16x4_t vreinterpret_s16_u32 (uint32x2_t)
10766@end itemize
10767
10768
10769@itemize @bullet
10770@item int16x4_t vreinterpret_s16_u16 (uint16x4_t)
10771@end itemize
10772
10773
10774@itemize @bullet
10775@item int16x4_t vreinterpret_s16_u8 (uint8x8_t)
10776@end itemize
10777
10778
10779@itemize @bullet
10780@item int16x4_t vreinterpret_s16_s32 (int32x2_t)
10781@end itemize
10782
10783
10784@itemize @bullet
10785@item int16x4_t vreinterpret_s16_s8 (int8x8_t)
10786@end itemize
10787
10788
10789@itemize @bullet
10790@item int16x4_t vreinterpret_s16_u64 (uint64x1_t)
10791@end itemize
10792
10793
10794@itemize @bullet
10795@item int16x4_t vreinterpret_s16_s64 (int64x1_t)
10796@end itemize
10797
10798
10799@itemize @bullet
10800@item int16x4_t vreinterpret_s16_f32 (float32x2_t)
10801@end itemize
10802
10803
10804@itemize @bullet
10805@item int16x4_t vreinterpret_s16_p16 (poly16x4_t)
10806@end itemize
10807
10808
10809@itemize @bullet
10810@item int16x4_t vreinterpret_s16_p8 (poly8x8_t)
10811@end itemize
10812
10813
10814@itemize @bullet
10815@item int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
10816@end itemize
10817
10818
10819@itemize @bullet
10820@item int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
10821@end itemize
10822
10823
10824@itemize @bullet
10825@item int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
10826@end itemize
10827
10828
10829@itemize @bullet
10830@item int16x8_t vreinterpretq_s16_s32 (int32x4_t)
10831@end itemize
10832
10833
10834@itemize @bullet
10835@item int16x8_t vreinterpretq_s16_s8 (int8x16_t)
10836@end itemize
10837
10838
10839@itemize @bullet
10840@item int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
10841@end itemize
10842
10843
10844@itemize @bullet
10845@item int16x8_t vreinterpretq_s16_s64 (int64x2_t)
10846@end itemize
10847
10848
10849@itemize @bullet
10850@item int16x8_t vreinterpretq_s16_f32 (float32x4_t)
10851@end itemize
10852
10853
10854@itemize @bullet
10855@item int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
10856@end itemize
10857
10858
10859@itemize @bullet
10860@item int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
10861@end itemize
10862
10863
10864@itemize @bullet
10865@item int32x2_t vreinterpret_s32_u32 (uint32x2_t)
10866@end itemize
10867
10868
10869@itemize @bullet
10870@item int32x2_t vreinterpret_s32_u16 (uint16x4_t)
10871@end itemize
10872
10873
10874@itemize @bullet
10875@item int32x2_t vreinterpret_s32_u8 (uint8x8_t)
10876@end itemize
10877
10878
10879@itemize @bullet
10880@item int32x2_t vreinterpret_s32_s16 (int16x4_t)
10881@end itemize
10882
10883
10884@itemize @bullet
10885@item int32x2_t vreinterpret_s32_s8 (int8x8_t)
10886@end itemize
10887
10888
10889@itemize @bullet
10890@item int32x2_t vreinterpret_s32_u64 (uint64x1_t)
10891@end itemize
10892
10893
10894@itemize @bullet
10895@item int32x2_t vreinterpret_s32_s64 (int64x1_t)
10896@end itemize
10897
10898
10899@itemize @bullet
10900@item int32x2_t vreinterpret_s32_f32 (float32x2_t)
10901@end itemize
10902
10903
10904@itemize @bullet
10905@item int32x2_t vreinterpret_s32_p16 (poly16x4_t)
10906@end itemize
10907
10908
10909@itemize @bullet
10910@item int32x2_t vreinterpret_s32_p8 (poly8x8_t)
10911@end itemize
10912
10913
10914@itemize @bullet
10915@item int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
10916@end itemize
10917
10918
10919@itemize @bullet
10920@item int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
10921@end itemize
10922
10923
10924@itemize @bullet
10925@item int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
10926@end itemize
10927
10928
10929@itemize @bullet
10930@item int32x4_t vreinterpretq_s32_s16 (int16x8_t)
10931@end itemize
10932
10933
10934@itemize @bullet
10935@item int32x4_t vreinterpretq_s32_s8 (int8x16_t)
10936@end itemize
10937
10938
10939@itemize @bullet
10940@item int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
10941@end itemize
10942
10943
10944@itemize @bullet
10945@item int32x4_t vreinterpretq_s32_s64 (int64x2_t)
10946@end itemize
10947
10948
10949@itemize @bullet
10950@item int32x4_t vreinterpretq_s32_f32 (float32x4_t)
10951@end itemize
10952
10953
10954@itemize @bullet
10955@item int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
10956@end itemize
10957
10958
10959@itemize @bullet
10960@item int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
10961@end itemize
10962
10963
10964@itemize @bullet
10965@item uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
10966@end itemize
10967
10968
10969@itemize @bullet
10970@item uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
10971@end itemize
10972
10973
10974@itemize @bullet
10975@item uint8x8_t vreinterpret_u8_s32 (int32x2_t)
10976@end itemize
10977
10978
10979@itemize @bullet
10980@item uint8x8_t vreinterpret_u8_s16 (int16x4_t)
10981@end itemize
10982
10983
10984@itemize @bullet
10985@item uint8x8_t vreinterpret_u8_s8 (int8x8_t)
10986@end itemize
10987
10988
10989@itemize @bullet
10990@item uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
10991@end itemize
10992
10993
10994@itemize @bullet
10995@item uint8x8_t vreinterpret_u8_s64 (int64x1_t)
10996@end itemize
10997
10998
10999@itemize @bullet
11000@item uint8x8_t vreinterpret_u8_f32 (float32x2_t)
11001@end itemize
11002
11003
11004@itemize @bullet
11005@item uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
11006@end itemize
11007
11008
11009@itemize @bullet
11010@item uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
11011@end itemize
11012
11013
11014@itemize @bullet
11015@item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
11016@end itemize
11017
11018
11019@itemize @bullet
11020@item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
11021@end itemize
11022
11023
11024@itemize @bullet
11025@item uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
11026@end itemize
11027
11028
11029@itemize @bullet
11030@item uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
11031@end itemize
11032
11033
11034@itemize @bullet
11035@item uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
11036@end itemize
11037
11038
11039@itemize @bullet
11040@item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
11041@end itemize
11042
11043
11044@itemize @bullet
11045@item uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
11046@end itemize
11047
11048
11049@itemize @bullet
11050@item uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
11051@end itemize
11052
11053
11054@itemize @bullet
11055@item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
11056@end itemize
11057
11058
11059@itemize @bullet
11060@item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
11061@end itemize
11062
11063
11064@itemize @bullet
11065@item uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
11066@end itemize
11067
11068
11069@itemize @bullet
11070@item uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
11071@end itemize
11072
11073
11074@itemize @bullet
11075@item uint16x4_t vreinterpret_u16_s32 (int32x2_t)
11076@end itemize
11077
11078
11079@itemize @bullet
11080@item uint16x4_t vreinterpret_u16_s16 (int16x4_t)
11081@end itemize
11082
11083
11084@itemize @bullet
11085@item uint16x4_t vreinterpret_u16_s8 (int8x8_t)
11086@end itemize
11087
11088
11089@itemize @bullet
11090@item uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
11091@end itemize
11092
11093
11094@itemize @bullet
11095@item uint16x4_t vreinterpret_u16_s64 (int64x1_t)
11096@end itemize
11097
11098
11099@itemize @bullet
11100@item uint16x4_t vreinterpret_u16_f32 (float32x2_t)
11101@end itemize
11102
11103
11104@itemize @bullet
11105@item uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
11106@end itemize
11107
11108
11109@itemize @bullet
11110@item uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
11111@end itemize
11112
11113
11114@itemize @bullet
11115@item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
11116@end itemize
11117
11118
11119@itemize @bullet
11120@item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
11121@end itemize
11122
11123
11124@itemize @bullet
11125@item uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
11126@end itemize
11127
11128
11129@itemize @bullet
11130@item uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
11131@end itemize
11132
11133
11134@itemize @bullet
11135@item uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
11136@end itemize
11137
11138
11139@itemize @bullet
11140@item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
11141@end itemize
11142
11143
11144@itemize @bullet
11145@item uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
11146@end itemize
11147
11148
11149@itemize @bullet
11150@item uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
11151@end itemize
11152
11153
11154@itemize @bullet
11155@item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
11156@end itemize
11157
11158
11159@itemize @bullet
11160@item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t)
11161@end itemize
11162
11163
11164@itemize @bullet
11165@item uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
11166@end itemize
11167
11168
11169@itemize @bullet
11170@item uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
11171@end itemize
11172
11173
11174@itemize @bullet
11175@item uint32x2_t vreinterpret_u32_s32 (int32x2_t)
11176@end itemize
11177
11178
11179@itemize @bullet
11180@item uint32x2_t vreinterpret_u32_s16 (int16x4_t)
11181@end itemize
11182
11183
11184@itemize @bullet
11185@item uint32x2_t vreinterpret_u32_s8 (int8x8_t)
11186@end itemize
11187
11188
11189@itemize @bullet
11190@item uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
11191@end itemize
11192
11193
11194@itemize @bullet
11195@item uint32x2_t vreinterpret_u32_s64 (int64x1_t)
11196@end itemize
11197
11198
11199@itemize @bullet
11200@item uint32x2_t vreinterpret_u32_f32 (float32x2_t)
11201@end itemize
11202
11203
11204@itemize @bullet
11205@item uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
11206@end itemize
11207
11208
11209@itemize @bullet
11210@item uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
11211@end itemize
11212
11213
11214@itemize @bullet
11215@item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
11216@end itemize
11217
11218
11219@itemize @bullet
11220@item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
11221@end itemize
11222
11223
11224@itemize @bullet
11225@item uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
11226@end itemize
11227
11228
11229@itemize @bullet
11230@item uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
11231@end itemize
11232
11233
11234@itemize @bullet
11235@item uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
11236@end itemize
11237
11238
11239@itemize @bullet
11240@item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
11241@end itemize
11242
11243
11244@itemize @bullet
11245@item uint32x4_t vreinterpretq_u32_s64 (int64x2_t)
11246@end itemize
11247
11248
11249@itemize @bullet
11250@item uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
11251@end itemize
11252
11253
11254@itemize @bullet
11255@item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
11256@end itemize
11257
11258
11259@itemize @bullet
11260@item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)
11261@end itemize
11262
11263
11264
11265
11266