1*e4b17023SJohn Marino@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001, 2*e4b17023SJohn Marino@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 3*e4b17023SJohn Marino@c Free Software Foundation, Inc. 4*e4b17023SJohn Marino@c This is part of the GCC manual. 5*e4b17023SJohn Marino@c For copying conditions, see the file gcc.texi. 6*e4b17023SJohn Marino 7*e4b17023SJohn Marino@ifset INTERNALS 8*e4b17023SJohn Marino@node Machine Desc 9*e4b17023SJohn Marino@chapter Machine Descriptions 10*e4b17023SJohn Marino@cindex machine descriptions 11*e4b17023SJohn Marino 12*e4b17023SJohn MarinoA machine description has two parts: a file of instruction patterns 13*e4b17023SJohn Marino(@file{.md} file) and a C header file of macro definitions. 14*e4b17023SJohn Marino 15*e4b17023SJohn MarinoThe @file{.md} file for a target machine contains a pattern for each 16*e4b17023SJohn Marinoinstruction that the target machine supports (or at least each instruction 17*e4b17023SJohn Marinothat is worth telling the compiler about). It may also contain comments. 18*e4b17023SJohn MarinoA semicolon causes the rest of the line to be a comment, unless the semicolon 19*e4b17023SJohn Marinois inside a quoted string. 20*e4b17023SJohn Marino 21*e4b17023SJohn MarinoSee the next chapter for information on the C header file. 22*e4b17023SJohn Marino 23*e4b17023SJohn Marino@menu 24*e4b17023SJohn Marino* Overview:: How the machine description is used. 25*e4b17023SJohn Marino* Patterns:: How to write instruction patterns. 26*e4b17023SJohn Marino* Example:: An explained example of a @code{define_insn} pattern. 27*e4b17023SJohn Marino* RTL Template:: The RTL template defines what insns match a pattern. 28*e4b17023SJohn Marino* Output Template:: The output template says how to make assembler code 29*e4b17023SJohn Marino from such an insn. 30*e4b17023SJohn Marino* Output Statement:: For more generality, write C code to output 31*e4b17023SJohn Marino the assembler code. 32*e4b17023SJohn Marino* Predicates:: Controlling what kinds of operands can be used 33*e4b17023SJohn Marino for an insn. 34*e4b17023SJohn Marino* Constraints:: Fine-tuning operand selection. 35*e4b17023SJohn Marino* Standard Names:: Names mark patterns to use for code generation. 36*e4b17023SJohn Marino* Pattern Ordering:: When the order of patterns makes a difference. 37*e4b17023SJohn Marino* Dependent Patterns:: Having one pattern may make you need another. 38*e4b17023SJohn Marino* Jump Patterns:: Special considerations for patterns for jump insns. 39*e4b17023SJohn Marino* Looping Patterns:: How to define patterns for special looping insns. 40*e4b17023SJohn Marino* Insn Canonicalizations::Canonicalization of Instructions 41*e4b17023SJohn Marino* Expander Definitions::Generating a sequence of several RTL insns 42*e4b17023SJohn Marino for a standard operation. 43*e4b17023SJohn Marino* Insn Splitting:: Splitting Instructions into Multiple Instructions. 44*e4b17023SJohn Marino* Including Patterns:: Including Patterns in Machine Descriptions. 45*e4b17023SJohn Marino* Peephole Definitions::Defining machine-specific peephole optimizations. 46*e4b17023SJohn Marino* Insn Attributes:: Specifying the value of attributes for generated insns. 47*e4b17023SJohn Marino* Conditional Execution::Generating @code{define_insn} patterns for 48*e4b17023SJohn Marino predication. 49*e4b17023SJohn Marino* Constant Definitions::Defining symbolic constants that can be used in the 50*e4b17023SJohn Marino md file. 51*e4b17023SJohn Marino* Iterators:: Using iterators to generate patterns from a template. 52*e4b17023SJohn Marino@end menu 53*e4b17023SJohn Marino 54*e4b17023SJohn Marino@node Overview 55*e4b17023SJohn Marino@section Overview of How the Machine Description is Used 56*e4b17023SJohn Marino 57*e4b17023SJohn MarinoThere are three main conversions that happen in the compiler: 58*e4b17023SJohn Marino 59*e4b17023SJohn Marino@enumerate 60*e4b17023SJohn Marino 61*e4b17023SJohn Marino@item 62*e4b17023SJohn MarinoThe front end reads the source code and builds a parse tree. 63*e4b17023SJohn Marino 64*e4b17023SJohn Marino@item 65*e4b17023SJohn MarinoThe parse tree is used to generate an RTL insn list based on named 66*e4b17023SJohn Marinoinstruction patterns. 67*e4b17023SJohn Marino 68*e4b17023SJohn Marino@item 69*e4b17023SJohn MarinoThe insn list is matched against the RTL templates to produce assembler 70*e4b17023SJohn Marinocode. 71*e4b17023SJohn Marino 72*e4b17023SJohn Marino@end enumerate 73*e4b17023SJohn Marino 74*e4b17023SJohn MarinoFor the generate pass, only the names of the insns matter, from either a 75*e4b17023SJohn Marinonamed @code{define_insn} or a @code{define_expand}. The compiler will 76*e4b17023SJohn Marinochoose the pattern with the right name and apply the operands according 77*e4b17023SJohn Marinoto the documentation later in this chapter, without regard for the RTL 78*e4b17023SJohn Marinotemplate or operand constraints. Note that the names the compiler looks 79*e4b17023SJohn Marinofor are hard-coded in the compiler---it will ignore unnamed patterns and 80*e4b17023SJohn Marinopatterns with names it doesn't know about, but if you don't provide a 81*e4b17023SJohn Marinonamed pattern it needs, it will abort. 82*e4b17023SJohn Marino 83*e4b17023SJohn MarinoIf a @code{define_insn} is used, the template given is inserted into the 84*e4b17023SJohn Marinoinsn list. If a @code{define_expand} is used, one of three things 85*e4b17023SJohn Marinohappens, based on the condition logic. The condition logic may manually 86*e4b17023SJohn Marinocreate new insns for the insn list, say via @code{emit_insn()}, and 87*e4b17023SJohn Marinoinvoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the 88*e4b17023SJohn Marinocompiler to use an alternate way of performing that task. If it invokes 89*e4b17023SJohn Marinoneither @code{DONE} nor @code{FAIL}, the template given in the pattern 90*e4b17023SJohn Marinois inserted, as if the @code{define_expand} were a @code{define_insn}. 91*e4b17023SJohn Marino 92*e4b17023SJohn MarinoOnce the insn list is generated, various optimization passes convert, 93*e4b17023SJohn Marinoreplace, and rearrange the insns in the insn list. This is where the 94*e4b17023SJohn Marino@code{define_split} and @code{define_peephole} patterns get used, for 95*e4b17023SJohn Marinoexample. 96*e4b17023SJohn Marino 97*e4b17023SJohn MarinoFinally, the insn list's RTL is matched up with the RTL templates in the 98*e4b17023SJohn Marino@code{define_insn} patterns, and those patterns are used to emit the 99*e4b17023SJohn Marinofinal assembly code. For this purpose, each named @code{define_insn} 100*e4b17023SJohn Marinoacts like it's unnamed, since the names are ignored. 101*e4b17023SJohn Marino 102*e4b17023SJohn Marino@node Patterns 103*e4b17023SJohn Marino@section Everything about Instruction Patterns 104*e4b17023SJohn Marino@cindex patterns 105*e4b17023SJohn Marino@cindex instruction patterns 106*e4b17023SJohn Marino 107*e4b17023SJohn Marino@findex define_insn 108*e4b17023SJohn MarinoEach instruction pattern contains an incomplete RTL expression, with pieces 109*e4b17023SJohn Marinoto be filled in later, operand constraints that restrict how the pieces can 110*e4b17023SJohn Marinobe filled in, and an output pattern or C code to generate the assembler 111*e4b17023SJohn Marinooutput, all wrapped up in a @code{define_insn} expression. 112*e4b17023SJohn Marino 113*e4b17023SJohn MarinoA @code{define_insn} is an RTL expression containing four or five operands: 114*e4b17023SJohn Marino 115*e4b17023SJohn Marino@enumerate 116*e4b17023SJohn Marino@item 117*e4b17023SJohn MarinoAn optional name. The presence of a name indicate that this instruction 118*e4b17023SJohn Marinopattern can perform a certain standard job for the RTL-generation 119*e4b17023SJohn Marinopass of the compiler. This pass knows certain names and will use 120*e4b17023SJohn Marinothe instruction patterns with those names, if the names are defined 121*e4b17023SJohn Marinoin the machine description. 122*e4b17023SJohn Marino 123*e4b17023SJohn MarinoThe absence of a name is indicated by writing an empty string 124*e4b17023SJohn Marinowhere the name should go. Nameless instruction patterns are never 125*e4b17023SJohn Marinoused for generating RTL code, but they may permit several simpler insns 126*e4b17023SJohn Marinoto be combined later on. 127*e4b17023SJohn Marino 128*e4b17023SJohn MarinoNames that are not thus known and used in RTL-generation have no 129*e4b17023SJohn Marinoeffect; they are equivalent to no name at all. 130*e4b17023SJohn Marino 131*e4b17023SJohn MarinoFor the purpose of debugging the compiler, you may also specify a 132*e4b17023SJohn Marinoname beginning with the @samp{*} character. Such a name is used only 133*e4b17023SJohn Marinofor identifying the instruction in RTL dumps; it is entirely equivalent 134*e4b17023SJohn Marinoto having a nameless pattern for all other purposes. 135*e4b17023SJohn Marino 136*e4b17023SJohn Marino@item 137*e4b17023SJohn MarinoThe @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete 138*e4b17023SJohn MarinoRTL expressions which show what the instruction should look like. It is 139*e4b17023SJohn Marinoincomplete because it may contain @code{match_operand}, 140*e4b17023SJohn Marino@code{match_operator}, and @code{match_dup} expressions that stand for 141*e4b17023SJohn Marinooperands of the instruction. 142*e4b17023SJohn Marino 143*e4b17023SJohn MarinoIf the vector has only one element, that element is the template for the 144*e4b17023SJohn Marinoinstruction pattern. If the vector has multiple elements, then the 145*e4b17023SJohn Marinoinstruction pattern is a @code{parallel} expression containing the 146*e4b17023SJohn Marinoelements described. 147*e4b17023SJohn Marino 148*e4b17023SJohn Marino@item 149*e4b17023SJohn Marino@cindex pattern conditions 150*e4b17023SJohn Marino@cindex conditions, in patterns 151*e4b17023SJohn MarinoA condition. This is a string which contains a C expression that is 152*e4b17023SJohn Marinothe final test to decide whether an insn body matches this pattern. 153*e4b17023SJohn Marino 154*e4b17023SJohn Marino@cindex named patterns and conditions 155*e4b17023SJohn MarinoFor a named pattern, the condition (if present) may not depend on 156*e4b17023SJohn Marinothe data in the insn being matched, but only the target-machine-type 157*e4b17023SJohn Marinoflags. The compiler needs to test these conditions during 158*e4b17023SJohn Marinoinitialization in order to learn exactly which named instructions are 159*e4b17023SJohn Marinoavailable in a particular run. 160*e4b17023SJohn Marino 161*e4b17023SJohn Marino@findex operands 162*e4b17023SJohn MarinoFor nameless patterns, the condition is applied only when matching an 163*e4b17023SJohn Marinoindividual insn, and only after the insn has matched the pattern's 164*e4b17023SJohn Marinorecognition template. The insn's operands may be found in the vector 165*e4b17023SJohn Marino@code{operands}. For an insn where the condition has once matched, it 166*e4b17023SJohn Marinocan't be used to control register allocation, for example by excluding 167*e4b17023SJohn Marinocertain hard registers or hard register combinations. 168*e4b17023SJohn Marino 169*e4b17023SJohn Marino@item 170*e4b17023SJohn MarinoThe @dfn{output template}: a string that says how to output matching 171*e4b17023SJohn Marinoinsns as assembler code. @samp{%} in this string specifies where 172*e4b17023SJohn Marinoto substitute the value of an operand. @xref{Output Template}. 173*e4b17023SJohn Marino 174*e4b17023SJohn MarinoWhen simple substitution isn't general enough, you can specify a piece 175*e4b17023SJohn Marinoof C code to compute the output. @xref{Output Statement}. 176*e4b17023SJohn Marino 177*e4b17023SJohn Marino@item 178*e4b17023SJohn MarinoOptionally, a vector containing the values of attributes for insns matching 179*e4b17023SJohn Marinothis pattern. @xref{Insn Attributes}. 180*e4b17023SJohn Marino@end enumerate 181*e4b17023SJohn Marino 182*e4b17023SJohn Marino@node Example 183*e4b17023SJohn Marino@section Example of @code{define_insn} 184*e4b17023SJohn Marino@cindex @code{define_insn} example 185*e4b17023SJohn Marino 186*e4b17023SJohn MarinoHere is an actual example of an instruction pattern, for the 68000/68020. 187*e4b17023SJohn Marino 188*e4b17023SJohn Marino@smallexample 189*e4b17023SJohn Marino(define_insn "tstsi" 190*e4b17023SJohn Marino [(set (cc0) 191*e4b17023SJohn Marino (match_operand:SI 0 "general_operand" "rm"))] 192*e4b17023SJohn Marino "" 193*e4b17023SJohn Marino "* 194*e4b17023SJohn Marino@{ 195*e4b17023SJohn Marino if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) 196*e4b17023SJohn Marino return \"tstl %0\"; 197*e4b17023SJohn Marino return \"cmpl #0,%0\"; 198*e4b17023SJohn Marino@}") 199*e4b17023SJohn Marino@end smallexample 200*e4b17023SJohn Marino 201*e4b17023SJohn Marino@noindent 202*e4b17023SJohn MarinoThis can also be written using braced strings: 203*e4b17023SJohn Marino 204*e4b17023SJohn Marino@smallexample 205*e4b17023SJohn Marino(define_insn "tstsi" 206*e4b17023SJohn Marino [(set (cc0) 207*e4b17023SJohn Marino (match_operand:SI 0 "general_operand" "rm"))] 208*e4b17023SJohn Marino "" 209*e4b17023SJohn Marino@{ 210*e4b17023SJohn Marino if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) 211*e4b17023SJohn Marino return "tstl %0"; 212*e4b17023SJohn Marino return "cmpl #0,%0"; 213*e4b17023SJohn Marino@}) 214*e4b17023SJohn Marino@end smallexample 215*e4b17023SJohn Marino 216*e4b17023SJohn MarinoThis is an instruction that sets the condition codes based on the value of 217*e4b17023SJohn Marinoa general operand. It has no condition, so any insn whose RTL description 218*e4b17023SJohn Marinohas the form shown may be handled according to this pattern. The name 219*e4b17023SJohn Marino@samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation 220*e4b17023SJohn Marinopass that, when it is necessary to test such a value, an insn to do so 221*e4b17023SJohn Marinocan be constructed using this pattern. 222*e4b17023SJohn Marino 223*e4b17023SJohn MarinoThe output control string is a piece of C code which chooses which 224*e4b17023SJohn Marinooutput template to return based on the kind of operand and the specific 225*e4b17023SJohn Marinotype of CPU for which code is being generated. 226*e4b17023SJohn Marino 227*e4b17023SJohn Marino@samp{"rm"} is an operand constraint. Its meaning is explained below. 228*e4b17023SJohn Marino 229*e4b17023SJohn Marino@node RTL Template 230*e4b17023SJohn Marino@section RTL Template 231*e4b17023SJohn Marino@cindex RTL insn template 232*e4b17023SJohn Marino@cindex generating insns 233*e4b17023SJohn Marino@cindex insns, generating 234*e4b17023SJohn Marino@cindex recognizing insns 235*e4b17023SJohn Marino@cindex insns, recognizing 236*e4b17023SJohn Marino 237*e4b17023SJohn MarinoThe RTL template is used to define which insns match the particular pattern 238*e4b17023SJohn Marinoand how to find their operands. For named patterns, the RTL template also 239*e4b17023SJohn Marinosays how to construct an insn from specified operands. 240*e4b17023SJohn Marino 241*e4b17023SJohn MarinoConstruction involves substituting specified operands into a copy of the 242*e4b17023SJohn Marinotemplate. Matching involves determining the values that serve as the 243*e4b17023SJohn Marinooperands in the insn being matched. Both of these activities are 244*e4b17023SJohn Marinocontrolled by special expression types that direct matching and 245*e4b17023SJohn Marinosubstitution of the operands. 246*e4b17023SJohn Marino 247*e4b17023SJohn Marino@table @code 248*e4b17023SJohn Marino@findex match_operand 249*e4b17023SJohn Marino@item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint}) 250*e4b17023SJohn MarinoThis expression is a placeholder for operand number @var{n} of 251*e4b17023SJohn Marinothe insn. When constructing an insn, operand number @var{n} 252*e4b17023SJohn Marinowill be substituted at this point. When matching an insn, whatever 253*e4b17023SJohn Marinoappears at this position in the insn will be taken as operand 254*e4b17023SJohn Marinonumber @var{n}; but it must satisfy @var{predicate} or this instruction 255*e4b17023SJohn Marinopattern will not match at all. 256*e4b17023SJohn Marino 257*e4b17023SJohn MarinoOperand numbers must be chosen consecutively counting from zero in 258*e4b17023SJohn Marinoeach instruction pattern. There may be only one @code{match_operand} 259*e4b17023SJohn Marinoexpression in the pattern for each operand number. Usually operands 260*e4b17023SJohn Marinoare numbered in the order of appearance in @code{match_operand} 261*e4b17023SJohn Marinoexpressions. In the case of a @code{define_expand}, any operand numbers 262*e4b17023SJohn Marinoused only in @code{match_dup} expressions have higher values than all 263*e4b17023SJohn Marinoother operand numbers. 264*e4b17023SJohn Marino 265*e4b17023SJohn Marino@var{predicate} is a string that is the name of a function that 266*e4b17023SJohn Marinoaccepts two arguments, an expression and a machine mode. 267*e4b17023SJohn Marino@xref{Predicates}. During matching, the function will be called with 268*e4b17023SJohn Marinothe putative operand as the expression and @var{m} as the mode 269*e4b17023SJohn Marinoargument (if @var{m} is not specified, @code{VOIDmode} will be used, 270*e4b17023SJohn Marinowhich normally causes @var{predicate} to accept any mode). If it 271*e4b17023SJohn Marinoreturns zero, this instruction pattern fails to match. 272*e4b17023SJohn Marino@var{predicate} may be an empty string; then it means no test is to be 273*e4b17023SJohn Marinodone on the operand, so anything which occurs in this position is 274*e4b17023SJohn Marinovalid. 275*e4b17023SJohn Marino 276*e4b17023SJohn MarinoMost of the time, @var{predicate} will reject modes other than @var{m}---but 277*e4b17023SJohn Marinonot always. For example, the predicate @code{address_operand} uses 278*e4b17023SJohn Marino@var{m} as the mode of memory ref that the address should be valid for. 279*e4b17023SJohn MarinoMany predicates accept @code{const_int} nodes even though their mode is 280*e4b17023SJohn Marino@code{VOIDmode}. 281*e4b17023SJohn Marino 282*e4b17023SJohn Marino@var{constraint} controls reloading and the choice of the best register 283*e4b17023SJohn Marinoclass to use for a value, as explained later (@pxref{Constraints}). 284*e4b17023SJohn MarinoIf the constraint would be an empty string, it can be omitted. 285*e4b17023SJohn Marino 286*e4b17023SJohn MarinoPeople are often unclear on the difference between the constraint and the 287*e4b17023SJohn Marinopredicate. The predicate helps decide whether a given insn matches the 288*e4b17023SJohn Marinopattern. The constraint plays no role in this decision; instead, it 289*e4b17023SJohn Marinocontrols various decisions in the case of an insn which does match. 290*e4b17023SJohn Marino 291*e4b17023SJohn Marino@findex match_scratch 292*e4b17023SJohn Marino@item (match_scratch:@var{m} @var{n} @var{constraint}) 293*e4b17023SJohn MarinoThis expression is also a placeholder for operand number @var{n} 294*e4b17023SJohn Marinoand indicates that operand must be a @code{scratch} or @code{reg} 295*e4b17023SJohn Marinoexpression. 296*e4b17023SJohn Marino 297*e4b17023SJohn MarinoWhen matching patterns, this is equivalent to 298*e4b17023SJohn Marino 299*e4b17023SJohn Marino@smallexample 300*e4b17023SJohn Marino(match_operand:@var{m} @var{n} "scratch_operand" @var{pred}) 301*e4b17023SJohn Marino@end smallexample 302*e4b17023SJohn Marino 303*e4b17023SJohn Marinobut, when generating RTL, it produces a (@code{scratch}:@var{m}) 304*e4b17023SJohn Marinoexpression. 305*e4b17023SJohn Marino 306*e4b17023SJohn MarinoIf the last few expressions in a @code{parallel} are @code{clobber} 307*e4b17023SJohn Marinoexpressions whose operands are either a hard register or 308*e4b17023SJohn Marino@code{match_scratch}, the combiner can add or delete them when 309*e4b17023SJohn Marinonecessary. @xref{Side Effects}. 310*e4b17023SJohn Marino 311*e4b17023SJohn Marino@findex match_dup 312*e4b17023SJohn Marino@item (match_dup @var{n}) 313*e4b17023SJohn MarinoThis expression is also a placeholder for operand number @var{n}. 314*e4b17023SJohn MarinoIt is used when the operand needs to appear more than once in the 315*e4b17023SJohn Marinoinsn. 316*e4b17023SJohn Marino 317*e4b17023SJohn MarinoIn construction, @code{match_dup} acts just like @code{match_operand}: 318*e4b17023SJohn Marinothe operand is substituted into the insn being constructed. But in 319*e4b17023SJohn Marinomatching, @code{match_dup} behaves differently. It assumes that operand 320*e4b17023SJohn Marinonumber @var{n} has already been determined by a @code{match_operand} 321*e4b17023SJohn Marinoappearing earlier in the recognition template, and it matches only an 322*e4b17023SJohn Marinoidentical-looking expression. 323*e4b17023SJohn Marino 324*e4b17023SJohn MarinoNote that @code{match_dup} should not be used to tell the compiler that 325*e4b17023SJohn Marinoa particular register is being used for two operands (example: 326*e4b17023SJohn Marino@code{add} that adds one register to another; the second register is 327*e4b17023SJohn Marinoboth an input operand and the output operand). Use a matching 328*e4b17023SJohn Marinoconstraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one 329*e4b17023SJohn Marinooperand is used in two places in the template, such as an instruction 330*e4b17023SJohn Marinothat computes both a quotient and a remainder, where the opcode takes 331*e4b17023SJohn Marinotwo input operands but the RTL template has to refer to each of those 332*e4b17023SJohn Marinotwice; once for the quotient pattern and once for the remainder pattern. 333*e4b17023SJohn Marino 334*e4b17023SJohn Marino@findex match_operator 335*e4b17023SJohn Marino@item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}]) 336*e4b17023SJohn MarinoThis pattern is a kind of placeholder for a variable RTL expression 337*e4b17023SJohn Marinocode. 338*e4b17023SJohn Marino 339*e4b17023SJohn MarinoWhen constructing an insn, it stands for an RTL expression whose 340*e4b17023SJohn Marinoexpression code is taken from that of operand @var{n}, and whose 341*e4b17023SJohn Marinooperands are constructed from the patterns @var{operands}. 342*e4b17023SJohn Marino 343*e4b17023SJohn MarinoWhen matching an expression, it matches an expression if the function 344*e4b17023SJohn Marino@var{predicate} returns nonzero on that expression @emph{and} the 345*e4b17023SJohn Marinopatterns @var{operands} match the operands of the expression. 346*e4b17023SJohn Marino 347*e4b17023SJohn MarinoSuppose that the function @code{commutative_operator} is defined as 348*e4b17023SJohn Marinofollows, to match any expression whose operator is one of the 349*e4b17023SJohn Marinocommutative arithmetic operators of RTL and whose mode is @var{mode}: 350*e4b17023SJohn Marino 351*e4b17023SJohn Marino@smallexample 352*e4b17023SJohn Marinoint 353*e4b17023SJohn Marinocommutative_integer_operator (x, mode) 354*e4b17023SJohn Marino rtx x; 355*e4b17023SJohn Marino enum machine_mode mode; 356*e4b17023SJohn Marino@{ 357*e4b17023SJohn Marino enum rtx_code code = GET_CODE (x); 358*e4b17023SJohn Marino if (GET_MODE (x) != mode) 359*e4b17023SJohn Marino return 0; 360*e4b17023SJohn Marino return (GET_RTX_CLASS (code) == RTX_COMM_ARITH 361*e4b17023SJohn Marino || code == EQ || code == NE); 362*e4b17023SJohn Marino@} 363*e4b17023SJohn Marino@end smallexample 364*e4b17023SJohn Marino 365*e4b17023SJohn MarinoThen the following pattern will match any RTL expression consisting 366*e4b17023SJohn Marinoof a commutative operator applied to two general operands: 367*e4b17023SJohn Marino 368*e4b17023SJohn Marino@smallexample 369*e4b17023SJohn Marino(match_operator:SI 3 "commutative_operator" 370*e4b17023SJohn Marino [(match_operand:SI 1 "general_operand" "g") 371*e4b17023SJohn Marino (match_operand:SI 2 "general_operand" "g")]) 372*e4b17023SJohn Marino@end smallexample 373*e4b17023SJohn Marino 374*e4b17023SJohn MarinoHere the vector @code{[@var{operands}@dots{}]} contains two patterns 375*e4b17023SJohn Marinobecause the expressions to be matched all contain two operands. 376*e4b17023SJohn Marino 377*e4b17023SJohn MarinoWhen this pattern does match, the two operands of the commutative 378*e4b17023SJohn Marinooperator are recorded as operands 1 and 2 of the insn. (This is done 379*e4b17023SJohn Marinoby the two instances of @code{match_operand}.) Operand 3 of the insn 380*e4b17023SJohn Marinowill be the entire commutative expression: use @code{GET_CODE 381*e4b17023SJohn Marino(operands[3])} to see which commutative operator was used. 382*e4b17023SJohn Marino 383*e4b17023SJohn MarinoThe machine mode @var{m} of @code{match_operator} works like that of 384*e4b17023SJohn Marino@code{match_operand}: it is passed as the second argument to the 385*e4b17023SJohn Marinopredicate function, and that function is solely responsible for 386*e4b17023SJohn Marinodeciding whether the expression to be matched ``has'' that mode. 387*e4b17023SJohn Marino 388*e4b17023SJohn MarinoWhen constructing an insn, argument 3 of the gen-function will specify 389*e4b17023SJohn Marinothe operation (i.e.@: the expression code) for the expression to be 390*e4b17023SJohn Marinomade. It should be an RTL expression, whose expression code is copied 391*e4b17023SJohn Marinointo a new expression whose operands are arguments 1 and 2 of the 392*e4b17023SJohn Marinogen-function. The subexpressions of argument 3 are not used; 393*e4b17023SJohn Marinoonly its expression code matters. 394*e4b17023SJohn Marino 395*e4b17023SJohn MarinoWhen @code{match_operator} is used in a pattern for matching an insn, 396*e4b17023SJohn Marinoit usually best if the operand number of the @code{match_operator} 397*e4b17023SJohn Marinois higher than that of the actual operands of the insn. This improves 398*e4b17023SJohn Marinoregister allocation because the register allocator often looks at 399*e4b17023SJohn Marinooperands 1 and 2 of insns to see if it can do register tying. 400*e4b17023SJohn Marino 401*e4b17023SJohn MarinoThere is no way to specify constraints in @code{match_operator}. The 402*e4b17023SJohn Marinooperand of the insn which corresponds to the @code{match_operator} 403*e4b17023SJohn Marinonever has any constraints because it is never reloaded as a whole. 404*e4b17023SJohn MarinoHowever, if parts of its @var{operands} are matched by 405*e4b17023SJohn Marino@code{match_operand} patterns, those parts may have constraints of 406*e4b17023SJohn Marinotheir own. 407*e4b17023SJohn Marino 408*e4b17023SJohn Marino@findex match_op_dup 409*e4b17023SJohn Marino@item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}]) 410*e4b17023SJohn MarinoLike @code{match_dup}, except that it applies to operators instead of 411*e4b17023SJohn Marinooperands. When constructing an insn, operand number @var{n} will be 412*e4b17023SJohn Marinosubstituted at this point. But in matching, @code{match_op_dup} behaves 413*e4b17023SJohn Marinodifferently. It assumes that operand number @var{n} has already been 414*e4b17023SJohn Marinodetermined by a @code{match_operator} appearing earlier in the 415*e4b17023SJohn Marinorecognition template, and it matches only an identical-looking 416*e4b17023SJohn Marinoexpression. 417*e4b17023SJohn Marino 418*e4b17023SJohn Marino@findex match_parallel 419*e4b17023SJohn Marino@item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}]) 420*e4b17023SJohn MarinoThis pattern is a placeholder for an insn that consists of a 421*e4b17023SJohn Marino@code{parallel} expression with a variable number of elements. This 422*e4b17023SJohn Marinoexpression should only appear at the top level of an insn pattern. 423*e4b17023SJohn Marino 424*e4b17023SJohn MarinoWhen constructing an insn, operand number @var{n} will be substituted at 425*e4b17023SJohn Marinothis point. When matching an insn, it matches if the body of the insn 426*e4b17023SJohn Marinois a @code{parallel} expression with at least as many elements as the 427*e4b17023SJohn Marinovector of @var{subpat} expressions in the @code{match_parallel}, if each 428*e4b17023SJohn Marino@var{subpat} matches the corresponding element of the @code{parallel}, 429*e4b17023SJohn Marino@emph{and} the function @var{predicate} returns nonzero on the 430*e4b17023SJohn Marino@code{parallel} that is the body of the insn. It is the responsibility 431*e4b17023SJohn Marinoof the predicate to validate elements of the @code{parallel} beyond 432*e4b17023SJohn Marinothose listed in the @code{match_parallel}. 433*e4b17023SJohn Marino 434*e4b17023SJohn MarinoA typical use of @code{match_parallel} is to match load and store 435*e4b17023SJohn Marinomultiple expressions, which can contain a variable number of elements 436*e4b17023SJohn Marinoin a @code{parallel}. For example, 437*e4b17023SJohn Marino 438*e4b17023SJohn Marino@smallexample 439*e4b17023SJohn Marino(define_insn "" 440*e4b17023SJohn Marino [(match_parallel 0 "load_multiple_operation" 441*e4b17023SJohn Marino [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 442*e4b17023SJohn Marino (match_operand:SI 2 "memory_operand" "m")) 443*e4b17023SJohn Marino (use (reg:SI 179)) 444*e4b17023SJohn Marino (clobber (reg:SI 179))])] 445*e4b17023SJohn Marino "" 446*e4b17023SJohn Marino "loadm 0,0,%1,%2") 447*e4b17023SJohn Marino@end smallexample 448*e4b17023SJohn Marino 449*e4b17023SJohn MarinoThis example comes from @file{a29k.md}. The function 450*e4b17023SJohn Marino@code{load_multiple_operation} is defined in @file{a29k.c} and checks 451*e4b17023SJohn Marinothat subsequent elements in the @code{parallel} are the same as the 452*e4b17023SJohn Marino@code{set} in the pattern, except that they are referencing subsequent 453*e4b17023SJohn Marinoregisters and memory locations. 454*e4b17023SJohn Marino 455*e4b17023SJohn MarinoAn insn that matches this pattern might look like: 456*e4b17023SJohn Marino 457*e4b17023SJohn Marino@smallexample 458*e4b17023SJohn Marino(parallel 459*e4b17023SJohn Marino [(set (reg:SI 20) (mem:SI (reg:SI 100))) 460*e4b17023SJohn Marino (use (reg:SI 179)) 461*e4b17023SJohn Marino (clobber (reg:SI 179)) 462*e4b17023SJohn Marino (set (reg:SI 21) 463*e4b17023SJohn Marino (mem:SI (plus:SI (reg:SI 100) 464*e4b17023SJohn Marino (const_int 4)))) 465*e4b17023SJohn Marino (set (reg:SI 22) 466*e4b17023SJohn Marino (mem:SI (plus:SI (reg:SI 100) 467*e4b17023SJohn Marino (const_int 8))))]) 468*e4b17023SJohn Marino@end smallexample 469*e4b17023SJohn Marino 470*e4b17023SJohn Marino@findex match_par_dup 471*e4b17023SJohn Marino@item (match_par_dup @var{n} [@var{subpat}@dots{}]) 472*e4b17023SJohn MarinoLike @code{match_op_dup}, but for @code{match_parallel} instead of 473*e4b17023SJohn Marino@code{match_operator}. 474*e4b17023SJohn Marino 475*e4b17023SJohn Marino@end table 476*e4b17023SJohn Marino 477*e4b17023SJohn Marino@node Output Template 478*e4b17023SJohn Marino@section Output Templates and Operand Substitution 479*e4b17023SJohn Marino@cindex output templates 480*e4b17023SJohn Marino@cindex operand substitution 481*e4b17023SJohn Marino 482*e4b17023SJohn Marino@cindex @samp{%} in template 483*e4b17023SJohn Marino@cindex percent sign 484*e4b17023SJohn MarinoThe @dfn{output template} is a string which specifies how to output the 485*e4b17023SJohn Marinoassembler code for an instruction pattern. Most of the template is a 486*e4b17023SJohn Marinofixed string which is output literally. The character @samp{%} is used 487*e4b17023SJohn Marinoto specify where to substitute an operand; it can also be used to 488*e4b17023SJohn Marinoidentify places where different variants of the assembler require 489*e4b17023SJohn Marinodifferent syntax. 490*e4b17023SJohn Marino 491*e4b17023SJohn MarinoIn the simplest case, a @samp{%} followed by a digit @var{n} says to output 492*e4b17023SJohn Marinooperand @var{n} at that point in the string. 493*e4b17023SJohn Marino 494*e4b17023SJohn Marino@samp{%} followed by a letter and a digit says to output an operand in an 495*e4b17023SJohn Marinoalternate fashion. Four letters have standard, built-in meanings described 496*e4b17023SJohn Marinobelow. The machine description macro @code{PRINT_OPERAND} can define 497*e4b17023SJohn Marinoadditional letters with nonstandard meanings. 498*e4b17023SJohn Marino 499*e4b17023SJohn Marino@samp{%c@var{digit}} can be used to substitute an operand that is a 500*e4b17023SJohn Marinoconstant value without the syntax that normally indicates an immediate 501*e4b17023SJohn Marinooperand. 502*e4b17023SJohn Marino 503*e4b17023SJohn Marino@samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of 504*e4b17023SJohn Marinothe constant is negated before printing. 505*e4b17023SJohn Marino 506*e4b17023SJohn Marino@samp{%a@var{digit}} can be used to substitute an operand as if it were a 507*e4b17023SJohn Marinomemory reference, with the actual operand treated as the address. This may 508*e4b17023SJohn Marinobe useful when outputting a ``load address'' instruction, because often the 509*e4b17023SJohn Marinoassembler syntax for such an instruction requires you to write the operand 510*e4b17023SJohn Marinoas if it were a memory reference. 511*e4b17023SJohn Marino 512*e4b17023SJohn Marino@samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump 513*e4b17023SJohn Marinoinstruction. 514*e4b17023SJohn Marino 515*e4b17023SJohn Marino@samp{%=} outputs a number which is unique to each instruction in the 516*e4b17023SJohn Marinoentire compilation. This is useful for making local labels to be 517*e4b17023SJohn Marinoreferred to more than once in a single template that generates multiple 518*e4b17023SJohn Marinoassembler instructions. 519*e4b17023SJohn Marino 520*e4b17023SJohn Marino@samp{%} followed by a punctuation character specifies a substitution that 521*e4b17023SJohn Marinodoes not use an operand. Only one case is standard: @samp{%%} outputs a 522*e4b17023SJohn Marino@samp{%} into the assembler code. Other nonstandard cases can be 523*e4b17023SJohn Marinodefined in the @code{PRINT_OPERAND} macro. You must also define 524*e4b17023SJohn Marinowhich punctuation characters are valid with the 525*e4b17023SJohn Marino@code{PRINT_OPERAND_PUNCT_VALID_P} macro. 526*e4b17023SJohn Marino 527*e4b17023SJohn Marino@cindex \ 528*e4b17023SJohn Marino@cindex backslash 529*e4b17023SJohn MarinoThe template may generate multiple assembler instructions. Write the text 530*e4b17023SJohn Marinofor the instructions, with @samp{\;} between them. 531*e4b17023SJohn Marino 532*e4b17023SJohn Marino@cindex matching operands 533*e4b17023SJohn MarinoWhen the RTL contains two operands which are required by constraint to match 534*e4b17023SJohn Marinoeach other, the output template must refer only to the lower-numbered operand. 535*e4b17023SJohn MarinoMatching operands are not always identical, and the rest of the compiler 536*e4b17023SJohn Marinoarranges to put the proper RTL expression for printing into the lower-numbered 537*e4b17023SJohn Marinooperand. 538*e4b17023SJohn Marino 539*e4b17023SJohn MarinoOne use of nonstandard letters or punctuation following @samp{%} is to 540*e4b17023SJohn Marinodistinguish between different assembler languages for the same machine; for 541*e4b17023SJohn Marinoexample, Motorola syntax versus MIT syntax for the 68000. Motorola syntax 542*e4b17023SJohn Marinorequires periods in most opcode names, while MIT syntax does not. For 543*e4b17023SJohn Marinoexample, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola 544*e4b17023SJohn Marinosyntax. The same file of patterns is used for both kinds of output syntax, 545*e4b17023SJohn Marinobut the character sequence @samp{%.} is used in each place where Motorola 546*e4b17023SJohn Marinosyntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax 547*e4b17023SJohn Marinodefines the sequence to output a period; the macro for MIT syntax defines 548*e4b17023SJohn Marinoit to do nothing. 549*e4b17023SJohn Marino 550*e4b17023SJohn Marino@cindex @code{#} in template 551*e4b17023SJohn MarinoAs a special case, a template consisting of the single character @code{#} 552*e4b17023SJohn Marinoinstructs the compiler to first split the insn, and then output the 553*e4b17023SJohn Marinoresulting instructions separately. This helps eliminate redundancy in the 554*e4b17023SJohn Marinooutput templates. If you have a @code{define_insn} that needs to emit 555*e4b17023SJohn Marinomultiple assembler instructions, and there is a matching @code{define_split} 556*e4b17023SJohn Marinoalready defined, then you can simply use @code{#} as the output template 557*e4b17023SJohn Marinoinstead of writing an output template that emits the multiple assembler 558*e4b17023SJohn Marinoinstructions. 559*e4b17023SJohn Marino 560*e4b17023SJohn MarinoIf the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct 561*e4b17023SJohn Marinoof the form @samp{@{option0|option1|option2@}} in the templates. These 562*e4b17023SJohn Marinodescribe multiple variants of assembler language syntax. 563*e4b17023SJohn Marino@xref{Instruction Output}. 564*e4b17023SJohn Marino 565*e4b17023SJohn Marino@node Output Statement 566*e4b17023SJohn Marino@section C Statements for Assembler Output 567*e4b17023SJohn Marino@cindex output statements 568*e4b17023SJohn Marino@cindex C statements for assembler output 569*e4b17023SJohn Marino@cindex generating assembler output 570*e4b17023SJohn Marino 571*e4b17023SJohn MarinoOften a single fixed template string cannot produce correct and efficient 572*e4b17023SJohn Marinoassembler code for all the cases that are recognized by a single 573*e4b17023SJohn Marinoinstruction pattern. For example, the opcodes may depend on the kinds of 574*e4b17023SJohn Marinooperands; or some unfortunate combinations of operands may require extra 575*e4b17023SJohn Marinomachine instructions. 576*e4b17023SJohn Marino 577*e4b17023SJohn MarinoIf the output control string starts with a @samp{@@}, then it is actually 578*e4b17023SJohn Marinoa series of templates, each on a separate line. (Blank lines and 579*e4b17023SJohn Marinoleading spaces and tabs are ignored.) The templates correspond to the 580*e4b17023SJohn Marinopattern's constraint alternatives (@pxref{Multi-Alternative}). For example, 581*e4b17023SJohn Marinoif a target machine has a two-address add instruction @samp{addr} to add 582*e4b17023SJohn Marinointo a register and another @samp{addm} to add a register to memory, you 583*e4b17023SJohn Marinomight write this pattern: 584*e4b17023SJohn Marino 585*e4b17023SJohn Marino@smallexample 586*e4b17023SJohn Marino(define_insn "addsi3" 587*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "=r,m") 588*e4b17023SJohn Marino (plus:SI (match_operand:SI 1 "general_operand" "0,0") 589*e4b17023SJohn Marino (match_operand:SI 2 "general_operand" "g,r")))] 590*e4b17023SJohn Marino "" 591*e4b17023SJohn Marino "@@ 592*e4b17023SJohn Marino addr %2,%0 593*e4b17023SJohn Marino addm %2,%0") 594*e4b17023SJohn Marino@end smallexample 595*e4b17023SJohn Marino 596*e4b17023SJohn Marino@cindex @code{*} in template 597*e4b17023SJohn Marino@cindex asterisk in template 598*e4b17023SJohn MarinoIf the output control string starts with a @samp{*}, then it is not an 599*e4b17023SJohn Marinooutput template but rather a piece of C program that should compute a 600*e4b17023SJohn Marinotemplate. It should execute a @code{return} statement to return the 601*e4b17023SJohn Marinotemplate-string you want. Most such templates use C string literals, which 602*e4b17023SJohn Marinorequire doublequote characters to delimit them. To include these 603*e4b17023SJohn Marinodoublequote characters in the string, prefix each one with @samp{\}. 604*e4b17023SJohn Marino 605*e4b17023SJohn MarinoIf the output control string is written as a brace block instead of a 606*e4b17023SJohn Marinodouble-quoted string, it is automatically assumed to be C code. In that 607*e4b17023SJohn Marinocase, it is not necessary to put in a leading asterisk, or to escape the 608*e4b17023SJohn Marinodoublequotes surrounding C string literals. 609*e4b17023SJohn Marino 610*e4b17023SJohn MarinoThe operands may be found in the array @code{operands}, whose C data type 611*e4b17023SJohn Marinois @code{rtx []}. 612*e4b17023SJohn Marino 613*e4b17023SJohn MarinoIt is very common to select different ways of generating assembler code 614*e4b17023SJohn Marinobased on whether an immediate operand is within a certain range. Be 615*e4b17023SJohn Marinocareful when doing this, because the result of @code{INTVAL} is an 616*e4b17023SJohn Marinointeger on the host machine. If the host machine has more bits in an 617*e4b17023SJohn Marino@code{int} than the target machine has in the mode in which the constant 618*e4b17023SJohn Marinowill be used, then some of the bits you get from @code{INTVAL} will be 619*e4b17023SJohn Marinosuperfluous. For proper results, you must carefully disregard the 620*e4b17023SJohn Marinovalues of those bits. 621*e4b17023SJohn Marino 622*e4b17023SJohn Marino@findex output_asm_insn 623*e4b17023SJohn MarinoIt is possible to output an assembler instruction and then go on to output 624*e4b17023SJohn Marinoor compute more of them, using the subroutine @code{output_asm_insn}. This 625*e4b17023SJohn Marinoreceives two arguments: a template-string and a vector of operands. The 626*e4b17023SJohn Marinovector may be @code{operands}, or it may be another array of @code{rtx} 627*e4b17023SJohn Marinothat you declare locally and initialize yourself. 628*e4b17023SJohn Marino 629*e4b17023SJohn Marino@findex which_alternative 630*e4b17023SJohn MarinoWhen an insn pattern has multiple alternatives in its constraints, often 631*e4b17023SJohn Marinothe appearance of the assembler code is determined mostly by which alternative 632*e4b17023SJohn Marinowas matched. When this is so, the C code can test the variable 633*e4b17023SJohn Marino@code{which_alternative}, which is the ordinal number of the alternative 634*e4b17023SJohn Marinothat was actually satisfied (0 for the first, 1 for the second alternative, 635*e4b17023SJohn Marinoetc.). 636*e4b17023SJohn Marino 637*e4b17023SJohn MarinoFor example, suppose there are two opcodes for storing zero, @samp{clrreg} 638*e4b17023SJohn Marinofor registers and @samp{clrmem} for memory locations. Here is how 639*e4b17023SJohn Marinoa pattern could use @code{which_alternative} to choose between them: 640*e4b17023SJohn Marino 641*e4b17023SJohn Marino@smallexample 642*e4b17023SJohn Marino(define_insn "" 643*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "=r,m") 644*e4b17023SJohn Marino (const_int 0))] 645*e4b17023SJohn Marino "" 646*e4b17023SJohn Marino @{ 647*e4b17023SJohn Marino return (which_alternative == 0 648*e4b17023SJohn Marino ? "clrreg %0" : "clrmem %0"); 649*e4b17023SJohn Marino @}) 650*e4b17023SJohn Marino@end smallexample 651*e4b17023SJohn Marino 652*e4b17023SJohn MarinoThe example above, where the assembler code to generate was 653*e4b17023SJohn Marino@emph{solely} determined by the alternative, could also have been specified 654*e4b17023SJohn Marinoas follows, having the output control string start with a @samp{@@}: 655*e4b17023SJohn Marino 656*e4b17023SJohn Marino@smallexample 657*e4b17023SJohn Marino@group 658*e4b17023SJohn Marino(define_insn "" 659*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "=r,m") 660*e4b17023SJohn Marino (const_int 0))] 661*e4b17023SJohn Marino "" 662*e4b17023SJohn Marino "@@ 663*e4b17023SJohn Marino clrreg %0 664*e4b17023SJohn Marino clrmem %0") 665*e4b17023SJohn Marino@end group 666*e4b17023SJohn Marino@end smallexample 667*e4b17023SJohn Marino 668*e4b17023SJohn Marino@node Predicates 669*e4b17023SJohn Marino@section Predicates 670*e4b17023SJohn Marino@cindex predicates 671*e4b17023SJohn Marino@cindex operand predicates 672*e4b17023SJohn Marino@cindex operator predicates 673*e4b17023SJohn Marino 674*e4b17023SJohn MarinoA predicate determines whether a @code{match_operand} or 675*e4b17023SJohn Marino@code{match_operator} expression matches, and therefore whether the 676*e4b17023SJohn Marinosurrounding instruction pattern will be used for that combination of 677*e4b17023SJohn Marinooperands. GCC has a number of machine-independent predicates, and you 678*e4b17023SJohn Marinocan define machine-specific predicates as needed. By convention, 679*e4b17023SJohn Marinopredicates used with @code{match_operand} have names that end in 680*e4b17023SJohn Marino@samp{_operand}, and those used with @code{match_operator} have names 681*e4b17023SJohn Marinothat end in @samp{_operator}. 682*e4b17023SJohn Marino 683*e4b17023SJohn MarinoAll predicates are Boolean functions (in the mathematical sense) of 684*e4b17023SJohn Marinotwo arguments: the RTL expression that is being considered at that 685*e4b17023SJohn Marinoposition in the instruction pattern, and the machine mode that the 686*e4b17023SJohn Marino@code{match_operand} or @code{match_operator} specifies. In this 687*e4b17023SJohn Marinosection, the first argument is called @var{op} and the second argument 688*e4b17023SJohn Marino@var{mode}. Predicates can be called from C as ordinary two-argument 689*e4b17023SJohn Marinofunctions; this can be useful in output templates or other 690*e4b17023SJohn Marinomachine-specific code. 691*e4b17023SJohn Marino 692*e4b17023SJohn MarinoOperand predicates can allow operands that are not actually acceptable 693*e4b17023SJohn Marinoto the hardware, as long as the constraints give reload the ability to 694*e4b17023SJohn Marinofix them up (@pxref{Constraints}). However, GCC will usually generate 695*e4b17023SJohn Marinobetter code if the predicates specify the requirements of the machine 696*e4b17023SJohn Marinoinstructions as closely as possible. Reload cannot fix up operands 697*e4b17023SJohn Marinothat must be constants (``immediate operands''); you must use a 698*e4b17023SJohn Marinopredicate that allows only constants, or else enforce the requirement 699*e4b17023SJohn Marinoin the extra condition. 700*e4b17023SJohn Marino 701*e4b17023SJohn Marino@cindex predicates and machine modes 702*e4b17023SJohn Marino@cindex normal predicates 703*e4b17023SJohn Marino@cindex special predicates 704*e4b17023SJohn MarinoMost predicates handle their @var{mode} argument in a uniform manner. 705*e4b17023SJohn MarinoIf @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have 706*e4b17023SJohn Marinoany mode. If @var{mode} is anything else, then @var{op} must have the 707*e4b17023SJohn Marinosame mode, unless @var{op} is a @code{CONST_INT} or integer 708*e4b17023SJohn Marino@code{CONST_DOUBLE}. These RTL expressions always have 709*e4b17023SJohn Marino@code{VOIDmode}, so it would be counterproductive to check that their 710*e4b17023SJohn Marinomode matches. Instead, predicates that accept @code{CONST_INT} and/or 711*e4b17023SJohn Marinointeger @code{CONST_DOUBLE} check that the value stored in the 712*e4b17023SJohn Marinoconstant will fit in the requested mode. 713*e4b17023SJohn Marino 714*e4b17023SJohn MarinoPredicates with this behavior are called @dfn{normal}. 715*e4b17023SJohn Marino@command{genrecog} can optimize the instruction recognizer based on 716*e4b17023SJohn Marinoknowledge of how normal predicates treat modes. It can also diagnose 717*e4b17023SJohn Marinocertain kinds of common errors in the use of normal predicates; for 718*e4b17023SJohn Marinoinstance, it is almost always an error to use a normal predicate 719*e4b17023SJohn Marinowithout specifying a mode. 720*e4b17023SJohn Marino 721*e4b17023SJohn MarinoPredicates that do something different with their @var{mode} argument 722*e4b17023SJohn Marinoare called @dfn{special}. The generic predicates 723*e4b17023SJohn Marino@code{address_operand} and @code{pmode_register_operand} are special 724*e4b17023SJohn Marinopredicates. @command{genrecog} does not do any optimizations or 725*e4b17023SJohn Marinodiagnosis when special predicates are used. 726*e4b17023SJohn Marino 727*e4b17023SJohn Marino@menu 728*e4b17023SJohn Marino* Machine-Independent Predicates:: Predicates available to all back ends. 729*e4b17023SJohn Marino* Defining Predicates:: How to write machine-specific predicate 730*e4b17023SJohn Marino functions. 731*e4b17023SJohn Marino@end menu 732*e4b17023SJohn Marino 733*e4b17023SJohn Marino@node Machine-Independent Predicates 734*e4b17023SJohn Marino@subsection Machine-Independent Predicates 735*e4b17023SJohn Marino@cindex machine-independent predicates 736*e4b17023SJohn Marino@cindex generic predicates 737*e4b17023SJohn Marino 738*e4b17023SJohn MarinoThese are the generic predicates available to all back ends. They are 739*e4b17023SJohn Marinodefined in @file{recog.c}. The first category of predicates allow 740*e4b17023SJohn Marinoonly constant, or @dfn{immediate}, operands. 741*e4b17023SJohn Marino 742*e4b17023SJohn Marino@defun immediate_operand 743*e4b17023SJohn MarinoThis predicate allows any sort of constant that fits in @var{mode}. 744*e4b17023SJohn MarinoIt is an appropriate choice for instructions that take operands that 745*e4b17023SJohn Marinomust be constant. 746*e4b17023SJohn Marino@end defun 747*e4b17023SJohn Marino 748*e4b17023SJohn Marino@defun const_int_operand 749*e4b17023SJohn MarinoThis predicate allows any @code{CONST_INT} expression that fits in 750*e4b17023SJohn Marino@var{mode}. It is an appropriate choice for an immediate operand that 751*e4b17023SJohn Marinodoes not allow a symbol or label. 752*e4b17023SJohn Marino@end defun 753*e4b17023SJohn Marino 754*e4b17023SJohn Marino@defun const_double_operand 755*e4b17023SJohn MarinoThis predicate accepts any @code{CONST_DOUBLE} expression that has 756*e4b17023SJohn Marinoexactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also 757*e4b17023SJohn Marinoaccept @code{CONST_INT}. It is intended for immediate floating point 758*e4b17023SJohn Marinoconstants. 759*e4b17023SJohn Marino@end defun 760*e4b17023SJohn Marino 761*e4b17023SJohn Marino@noindent 762*e4b17023SJohn MarinoThe second category of predicates allow only some kind of machine 763*e4b17023SJohn Marinoregister. 764*e4b17023SJohn Marino 765*e4b17023SJohn Marino@defun register_operand 766*e4b17023SJohn MarinoThis predicate allows any @code{REG} or @code{SUBREG} expression that 767*e4b17023SJohn Marinois valid for @var{mode}. It is often suitable for arithmetic 768*e4b17023SJohn Marinoinstruction operands on a RISC machine. 769*e4b17023SJohn Marino@end defun 770*e4b17023SJohn Marino 771*e4b17023SJohn Marino@defun pmode_register_operand 772*e4b17023SJohn MarinoThis is a slight variant on @code{register_operand} which works around 773*e4b17023SJohn Marinoa limitation in the machine-description reader. 774*e4b17023SJohn Marino 775*e4b17023SJohn Marino@smallexample 776*e4b17023SJohn Marino(match_operand @var{n} "pmode_register_operand" @var{constraint}) 777*e4b17023SJohn Marino@end smallexample 778*e4b17023SJohn Marino 779*e4b17023SJohn Marino@noindent 780*e4b17023SJohn Marinomeans exactly what 781*e4b17023SJohn Marino 782*e4b17023SJohn Marino@smallexample 783*e4b17023SJohn Marino(match_operand:P @var{n} "register_operand" @var{constraint}) 784*e4b17023SJohn Marino@end smallexample 785*e4b17023SJohn Marino 786*e4b17023SJohn Marino@noindent 787*e4b17023SJohn Marinowould mean, if the machine-description reader accepted @samp{:P} 788*e4b17023SJohn Marinomode suffixes. Unfortunately, it cannot, because @code{Pmode} is an 789*e4b17023SJohn Marinoalias for some other mode, and might vary with machine-specific 790*e4b17023SJohn Marinooptions. @xref{Misc}. 791*e4b17023SJohn Marino@end defun 792*e4b17023SJohn Marino 793*e4b17023SJohn Marino@defun scratch_operand 794*e4b17023SJohn MarinoThis predicate allows hard registers and @code{SCRATCH} expressions, 795*e4b17023SJohn Marinobut not pseudo-registers. It is used internally by @code{match_scratch}; 796*e4b17023SJohn Marinoit should not be used directly. 797*e4b17023SJohn Marino@end defun 798*e4b17023SJohn Marino 799*e4b17023SJohn Marino@noindent 800*e4b17023SJohn MarinoThe third category of predicates allow only some kind of memory reference. 801*e4b17023SJohn Marino 802*e4b17023SJohn Marino@defun memory_operand 803*e4b17023SJohn MarinoThis predicate allows any valid reference to a quantity of mode 804*e4b17023SJohn Marino@var{mode} in memory, as determined by the weak form of 805*e4b17023SJohn Marino@code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}). 806*e4b17023SJohn Marino@end defun 807*e4b17023SJohn Marino 808*e4b17023SJohn Marino@defun address_operand 809*e4b17023SJohn MarinoThis predicate is a little unusual; it allows any operand that is a 810*e4b17023SJohn Marinovalid expression for the @emph{address} of a quantity of mode 811*e4b17023SJohn Marino@var{mode}, again determined by the weak form of 812*e4b17023SJohn Marino@code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if 813*e4b17023SJohn Marino@samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to 814*e4b17023SJohn Marino@code{memory_operand}, then @var{exp} is acceptable to 815*e4b17023SJohn Marino@code{address_operand}. Note that @var{exp} does not necessarily have 816*e4b17023SJohn Marinothe mode @var{mode}. 817*e4b17023SJohn Marino@end defun 818*e4b17023SJohn Marino 819*e4b17023SJohn Marino@defun indirect_operand 820*e4b17023SJohn MarinoThis is a stricter form of @code{memory_operand} which allows only 821*e4b17023SJohn Marinomemory references with a @code{general_operand} as the address 822*e4b17023SJohn Marinoexpression. New uses of this predicate are discouraged, because 823*e4b17023SJohn Marino@code{general_operand} is very permissive, so it's hard to tell what 824*e4b17023SJohn Marinoan @code{indirect_operand} does or does not allow. If a target has 825*e4b17023SJohn Marinodifferent requirements for memory operands for different instructions, 826*e4b17023SJohn Marinoit is better to define target-specific predicates which enforce the 827*e4b17023SJohn Marinohardware's requirements explicitly. 828*e4b17023SJohn Marino@end defun 829*e4b17023SJohn Marino 830*e4b17023SJohn Marino@defun push_operand 831*e4b17023SJohn MarinoThis predicate allows a memory reference suitable for pushing a value 832*e4b17023SJohn Marinoonto the stack. This will be a @code{MEM} which refers to 833*e4b17023SJohn Marino@code{stack_pointer_rtx}, with a side-effect in its address expression 834*e4b17023SJohn Marino(@pxref{Incdec}); which one is determined by the 835*e4b17023SJohn Marino@code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}). 836*e4b17023SJohn Marino@end defun 837*e4b17023SJohn Marino 838*e4b17023SJohn Marino@defun pop_operand 839*e4b17023SJohn MarinoThis predicate allows a memory reference suitable for popping a value 840*e4b17023SJohn Marinooff the stack. Again, this will be a @code{MEM} referring to 841*e4b17023SJohn Marino@code{stack_pointer_rtx}, with a side-effect in its address 842*e4b17023SJohn Marinoexpression. However, this time @code{STACK_POP_CODE} is expected. 843*e4b17023SJohn Marino@end defun 844*e4b17023SJohn Marino 845*e4b17023SJohn Marino@noindent 846*e4b17023SJohn MarinoThe fourth category of predicates allow some combination of the above 847*e4b17023SJohn Marinooperands. 848*e4b17023SJohn Marino 849*e4b17023SJohn Marino@defun nonmemory_operand 850*e4b17023SJohn MarinoThis predicate allows any immediate or register operand valid for @var{mode}. 851*e4b17023SJohn Marino@end defun 852*e4b17023SJohn Marino 853*e4b17023SJohn Marino@defun nonimmediate_operand 854*e4b17023SJohn MarinoThis predicate allows any register or memory operand valid for @var{mode}. 855*e4b17023SJohn Marino@end defun 856*e4b17023SJohn Marino 857*e4b17023SJohn Marino@defun general_operand 858*e4b17023SJohn MarinoThis predicate allows any immediate, register, or memory operand 859*e4b17023SJohn Marinovalid for @var{mode}. 860*e4b17023SJohn Marino@end defun 861*e4b17023SJohn Marino 862*e4b17023SJohn Marino@noindent 863*e4b17023SJohn MarinoFinally, there are two generic operator predicates. 864*e4b17023SJohn Marino 865*e4b17023SJohn Marino@defun comparison_operator 866*e4b17023SJohn MarinoThis predicate matches any expression which performs an arithmetic 867*e4b17023SJohn Marinocomparison in @var{mode}; that is, @code{COMPARISON_P} is true for the 868*e4b17023SJohn Marinoexpression code. 869*e4b17023SJohn Marino@end defun 870*e4b17023SJohn Marino 871*e4b17023SJohn Marino@defun ordered_comparison_operator 872*e4b17023SJohn MarinoThis predicate matches any expression which performs an arithmetic 873*e4b17023SJohn Marinocomparison in @var{mode} and whose expression code is valid for integer 874*e4b17023SJohn Marinomodes; that is, the expression code will be one of @code{eq}, @code{ne}, 875*e4b17023SJohn Marino@code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu}, 876*e4b17023SJohn Marino@code{ge}, @code{geu}. 877*e4b17023SJohn Marino@end defun 878*e4b17023SJohn Marino 879*e4b17023SJohn Marino@node Defining Predicates 880*e4b17023SJohn Marino@subsection Defining Machine-Specific Predicates 881*e4b17023SJohn Marino@cindex defining predicates 882*e4b17023SJohn Marino@findex define_predicate 883*e4b17023SJohn Marino@findex define_special_predicate 884*e4b17023SJohn Marino 885*e4b17023SJohn MarinoMany machines have requirements for their operands that cannot be 886*e4b17023SJohn Marinoexpressed precisely using the generic predicates. You can define 887*e4b17023SJohn Marinoadditional predicates using @code{define_predicate} and 888*e4b17023SJohn Marino@code{define_special_predicate} expressions. These expressions have 889*e4b17023SJohn Marinothree operands: 890*e4b17023SJohn Marino 891*e4b17023SJohn Marino@itemize @bullet 892*e4b17023SJohn Marino@item 893*e4b17023SJohn MarinoThe name of the predicate, as it will be referred to in 894*e4b17023SJohn Marino@code{match_operand} or @code{match_operator} expressions. 895*e4b17023SJohn Marino 896*e4b17023SJohn Marino@item 897*e4b17023SJohn MarinoAn RTL expression which evaluates to true if the predicate allows the 898*e4b17023SJohn Marinooperand @var{op}, false if it does not. This expression can only use 899*e4b17023SJohn Marinothe following RTL codes: 900*e4b17023SJohn Marino 901*e4b17023SJohn Marino@table @code 902*e4b17023SJohn Marino@item MATCH_OPERAND 903*e4b17023SJohn MarinoWhen written inside a predicate expression, a @code{MATCH_OPERAND} 904*e4b17023SJohn Marinoexpression evaluates to true if the predicate it names would allow 905*e4b17023SJohn Marino@var{op}. The operand number and constraint are ignored. Due to 906*e4b17023SJohn Marinolimitations in @command{genrecog}, you can only refer to generic 907*e4b17023SJohn Marinopredicates and predicates that have already been defined. 908*e4b17023SJohn Marino 909*e4b17023SJohn Marino@item MATCH_CODE 910*e4b17023SJohn MarinoThis expression evaluates to true if @var{op} or a specified 911*e4b17023SJohn Marinosubexpression of @var{op} has one of a given list of RTX codes. 912*e4b17023SJohn Marino 913*e4b17023SJohn MarinoThe first operand of this expression is a string constant containing a 914*e4b17023SJohn Marinocomma-separated list of RTX code names (in lower case). These are the 915*e4b17023SJohn Marinocodes for which the @code{MATCH_CODE} will be true. 916*e4b17023SJohn Marino 917*e4b17023SJohn MarinoThe second operand is a string constant which indicates what 918*e4b17023SJohn Marinosubexpression of @var{op} to examine. If it is absent or the empty 919*e4b17023SJohn Marinostring, @var{op} itself is examined. Otherwise, the string constant 920*e4b17023SJohn Marinomust be a sequence of digits and/or lowercase letters. Each character 921*e4b17023SJohn Marinoindicates a subexpression to extract from the current expression; for 922*e4b17023SJohn Marinothe first character this is @var{op}, for the second and subsequent 923*e4b17023SJohn Marinocharacters it is the result of the previous character. A digit 924*e4b17023SJohn Marino@var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l} 925*e4b17023SJohn Marinoextracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the 926*e4b17023SJohn Marinoalphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The 927*e4b17023SJohn Marino@code{MATCH_CODE} then examines the RTX code of the subexpression 928*e4b17023SJohn Marinoextracted by the complete string. It is not possible to extract 929*e4b17023SJohn Marinocomponents of an @code{rtvec} that is not at position 0 within its RTX 930*e4b17023SJohn Marinoobject. 931*e4b17023SJohn Marino 932*e4b17023SJohn Marino@item MATCH_TEST 933*e4b17023SJohn MarinoThis expression has one operand, a string constant containing a C 934*e4b17023SJohn Marinoexpression. The predicate's arguments, @var{op} and @var{mode}, are 935*e4b17023SJohn Marinoavailable with those names in the C expression. The @code{MATCH_TEST} 936*e4b17023SJohn Marinoevaluates to true if the C expression evaluates to a nonzero value. 937*e4b17023SJohn Marino@code{MATCH_TEST} expressions must not have side effects. 938*e4b17023SJohn Marino 939*e4b17023SJohn Marino@item AND 940*e4b17023SJohn Marino@itemx IOR 941*e4b17023SJohn Marino@itemx NOT 942*e4b17023SJohn Marino@itemx IF_THEN_ELSE 943*e4b17023SJohn MarinoThe basic @samp{MATCH_} expressions can be combined using these 944*e4b17023SJohn Marinological operators, which have the semantics of the C operators 945*e4b17023SJohn Marino@samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As 946*e4b17023SJohn Marinoin Common Lisp, you may give an @code{AND} or @code{IOR} expression an 947*e4b17023SJohn Marinoarbitrary number of arguments; this has exactly the same effect as 948*e4b17023SJohn Marinowriting a chain of two-argument @code{AND} or @code{IOR} expressions. 949*e4b17023SJohn Marino@end table 950*e4b17023SJohn Marino 951*e4b17023SJohn Marino@item 952*e4b17023SJohn MarinoAn optional block of C code, which should execute 953*e4b17023SJohn Marino@samp{@w{return true}} if the predicate is found to match and 954*e4b17023SJohn Marino@samp{@w{return false}} if it does not. It must not have any side 955*e4b17023SJohn Marinoeffects. The predicate arguments, @var{op} and @var{mode}, are 956*e4b17023SJohn Marinoavailable with those names. 957*e4b17023SJohn Marino 958*e4b17023SJohn MarinoIf a code block is present in a predicate definition, then the RTL 959*e4b17023SJohn Marinoexpression must evaluate to true @emph{and} the code block must 960*e4b17023SJohn Marinoexecute @samp{@w{return true}} for the predicate to allow the operand. 961*e4b17023SJohn MarinoThe RTL expression is evaluated first; do not re-check anything in the 962*e4b17023SJohn Marinocode block that was checked in the RTL expression. 963*e4b17023SJohn Marino@end itemize 964*e4b17023SJohn Marino 965*e4b17023SJohn MarinoThe program @command{genrecog} scans @code{define_predicate} and 966*e4b17023SJohn Marino@code{define_special_predicate} expressions to determine which RTX 967*e4b17023SJohn Marinocodes are possibly allowed. You should always make this explicit in 968*e4b17023SJohn Marinothe RTL predicate expression, using @code{MATCH_OPERAND} and 969*e4b17023SJohn Marino@code{MATCH_CODE}. 970*e4b17023SJohn Marino 971*e4b17023SJohn MarinoHere is an example of a simple predicate definition, from the IA64 972*e4b17023SJohn Marinomachine description: 973*e4b17023SJohn Marino 974*e4b17023SJohn Marino@smallexample 975*e4b17023SJohn Marino@group 976*e4b17023SJohn Marino;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.} 977*e4b17023SJohn Marino(define_predicate "small_addr_symbolic_operand" 978*e4b17023SJohn Marino (and (match_code "symbol_ref") 979*e4b17023SJohn Marino (match_test "SYMBOL_REF_SMALL_ADDR_P (op)"))) 980*e4b17023SJohn Marino@end group 981*e4b17023SJohn Marino@end smallexample 982*e4b17023SJohn Marino 983*e4b17023SJohn Marino@noindent 984*e4b17023SJohn MarinoAnd here is another, showing the use of the C block. 985*e4b17023SJohn Marino 986*e4b17023SJohn Marino@smallexample 987*e4b17023SJohn Marino@group 988*e4b17023SJohn Marino;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.} 989*e4b17023SJohn Marino(define_predicate "gr_register_operand" 990*e4b17023SJohn Marino (match_operand 0 "register_operand") 991*e4b17023SJohn Marino@{ 992*e4b17023SJohn Marino unsigned int regno; 993*e4b17023SJohn Marino if (GET_CODE (op) == SUBREG) 994*e4b17023SJohn Marino op = SUBREG_REG (op); 995*e4b17023SJohn Marino 996*e4b17023SJohn Marino regno = REGNO (op); 997*e4b17023SJohn Marino return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno)); 998*e4b17023SJohn Marino@}) 999*e4b17023SJohn Marino@end group 1000*e4b17023SJohn Marino@end smallexample 1001*e4b17023SJohn Marino 1002*e4b17023SJohn MarinoPredicates written with @code{define_predicate} automatically include 1003*e4b17023SJohn Marinoa test that @var{mode} is @code{VOIDmode}, or @var{op} has the same 1004*e4b17023SJohn Marinomode as @var{mode}, or @var{op} is a @code{CONST_INT} or 1005*e4b17023SJohn Marino@code{CONST_DOUBLE}. They do @emph{not} check specifically for 1006*e4b17023SJohn Marinointeger @code{CONST_DOUBLE}, nor do they test that the value of either 1007*e4b17023SJohn Marinokind of constant fits in the requested mode. This is because 1008*e4b17023SJohn Marinotarget-specific predicates that take constants usually have to do more 1009*e4b17023SJohn Marinostringent value checks anyway. If you need the exact same treatment 1010*e4b17023SJohn Marinoof @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates 1011*e4b17023SJohn Marinoprovide, use a @code{MATCH_OPERAND} subexpression to call 1012*e4b17023SJohn Marino@code{const_int_operand}, @code{const_double_operand}, or 1013*e4b17023SJohn Marino@code{immediate_operand}. 1014*e4b17023SJohn Marino 1015*e4b17023SJohn MarinoPredicates written with @code{define_special_predicate} do not get any 1016*e4b17023SJohn Marinoautomatic mode checks, and are treated as having special mode handling 1017*e4b17023SJohn Marinoby @command{genrecog}. 1018*e4b17023SJohn Marino 1019*e4b17023SJohn MarinoThe program @command{genpreds} is responsible for generating code to 1020*e4b17023SJohn Marinotest predicates. It also writes a header file containing function 1021*e4b17023SJohn Marinodeclarations for all machine-specific predicates. It is not necessary 1022*e4b17023SJohn Marinoto declare these predicates in @file{@var{cpu}-protos.h}. 1023*e4b17023SJohn Marino@end ifset 1024*e4b17023SJohn Marino 1025*e4b17023SJohn Marino@c Most of this node appears by itself (in a different place) even 1026*e4b17023SJohn Marino@c when the INTERNALS flag is clear. Passages that require the internals 1027*e4b17023SJohn Marino@c manual's context are conditionalized to appear only in the internals manual. 1028*e4b17023SJohn Marino@ifset INTERNALS 1029*e4b17023SJohn Marino@node Constraints 1030*e4b17023SJohn Marino@section Operand Constraints 1031*e4b17023SJohn Marino@cindex operand constraints 1032*e4b17023SJohn Marino@cindex constraints 1033*e4b17023SJohn Marino 1034*e4b17023SJohn MarinoEach @code{match_operand} in an instruction pattern can specify 1035*e4b17023SJohn Marinoconstraints for the operands allowed. The constraints allow you to 1036*e4b17023SJohn Marinofine-tune matching within the set of operands allowed by the 1037*e4b17023SJohn Marinopredicate. 1038*e4b17023SJohn Marino 1039*e4b17023SJohn Marino@end ifset 1040*e4b17023SJohn Marino@ifclear INTERNALS 1041*e4b17023SJohn Marino@node Constraints 1042*e4b17023SJohn Marino@section Constraints for @code{asm} Operands 1043*e4b17023SJohn Marino@cindex operand constraints, @code{asm} 1044*e4b17023SJohn Marino@cindex constraints, @code{asm} 1045*e4b17023SJohn Marino@cindex @code{asm} constraints 1046*e4b17023SJohn Marino 1047*e4b17023SJohn MarinoHere are specific details on what constraint letters you can use with 1048*e4b17023SJohn Marino@code{asm} operands. 1049*e4b17023SJohn Marino@end ifclear 1050*e4b17023SJohn MarinoConstraints can say whether 1051*e4b17023SJohn Marinoan operand may be in a register, and which kinds of register; whether the 1052*e4b17023SJohn Marinooperand can be a memory reference, and which kinds of address; whether the 1053*e4b17023SJohn Marinooperand may be an immediate constant, and which possible values it may 1054*e4b17023SJohn Marinohave. Constraints can also require two operands to match. 1055*e4b17023SJohn MarinoSide-effects aren't allowed in operands of inline @code{asm}, unless 1056*e4b17023SJohn Marino@samp{<} or @samp{>} constraints are used, because there is no guarantee 1057*e4b17023SJohn Marinothat the side-effects will happen exactly once in an instruction that can update 1058*e4b17023SJohn Marinothe addressing register. 1059*e4b17023SJohn Marino 1060*e4b17023SJohn Marino@ifset INTERNALS 1061*e4b17023SJohn Marino@menu 1062*e4b17023SJohn Marino* Simple Constraints:: Basic use of constraints. 1063*e4b17023SJohn Marino* Multi-Alternative:: When an insn has two alternative constraint-patterns. 1064*e4b17023SJohn Marino* Class Preferences:: Constraints guide which hard register to put things in. 1065*e4b17023SJohn Marino* Modifiers:: More precise control over effects of constraints. 1066*e4b17023SJohn Marino* Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute. 1067*e4b17023SJohn Marino* Machine Constraints:: Existing constraints for some particular machines. 1068*e4b17023SJohn Marino* Define Constraints:: How to define machine-specific constraints. 1069*e4b17023SJohn Marino* C Constraint Interface:: How to test constraints from C code. 1070*e4b17023SJohn Marino@end menu 1071*e4b17023SJohn Marino@end ifset 1072*e4b17023SJohn Marino 1073*e4b17023SJohn Marino@ifclear INTERNALS 1074*e4b17023SJohn Marino@menu 1075*e4b17023SJohn Marino* Simple Constraints:: Basic use of constraints. 1076*e4b17023SJohn Marino* Multi-Alternative:: When an insn has two alternative constraint-patterns. 1077*e4b17023SJohn Marino* Modifiers:: More precise control over effects of constraints. 1078*e4b17023SJohn Marino* Machine Constraints:: Special constraints for some particular machines. 1079*e4b17023SJohn Marino@end menu 1080*e4b17023SJohn Marino@end ifclear 1081*e4b17023SJohn Marino 1082*e4b17023SJohn Marino@node Simple Constraints 1083*e4b17023SJohn Marino@subsection Simple Constraints 1084*e4b17023SJohn Marino@cindex simple constraints 1085*e4b17023SJohn Marino 1086*e4b17023SJohn MarinoThe simplest kind of constraint is a string full of letters, each of 1087*e4b17023SJohn Marinowhich describes one kind of operand that is permitted. Here are 1088*e4b17023SJohn Marinothe letters that are allowed: 1089*e4b17023SJohn Marino 1090*e4b17023SJohn Marino@table @asis 1091*e4b17023SJohn Marino@item whitespace 1092*e4b17023SJohn MarinoWhitespace characters are ignored and can be inserted at any position 1093*e4b17023SJohn Marinoexcept the first. This enables each alternative for different operands to 1094*e4b17023SJohn Marinobe visually aligned in the machine description even if they have different 1095*e4b17023SJohn Marinonumber of constraints and modifiers. 1096*e4b17023SJohn Marino 1097*e4b17023SJohn Marino@cindex @samp{m} in constraint 1098*e4b17023SJohn Marino@cindex memory references in constraints 1099*e4b17023SJohn Marino@item @samp{m} 1100*e4b17023SJohn MarinoA memory operand is allowed, with any kind of address that the machine 1101*e4b17023SJohn Marinosupports in general. 1102*e4b17023SJohn MarinoNote that the letter used for the general memory constraint can be 1103*e4b17023SJohn Marinore-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro. 1104*e4b17023SJohn Marino 1105*e4b17023SJohn Marino@cindex offsettable address 1106*e4b17023SJohn Marino@cindex @samp{o} in constraint 1107*e4b17023SJohn Marino@item @samp{o} 1108*e4b17023SJohn MarinoA memory operand is allowed, but only if the address is 1109*e4b17023SJohn Marino@dfn{offsettable}. This means that adding a small integer (actually, 1110*e4b17023SJohn Marinothe width in bytes of the operand, as determined by its machine mode) 1111*e4b17023SJohn Marinomay be added to the address and the result is also a valid memory 1112*e4b17023SJohn Marinoaddress. 1113*e4b17023SJohn Marino 1114*e4b17023SJohn Marino@cindex autoincrement/decrement addressing 1115*e4b17023SJohn MarinoFor example, an address which is constant is offsettable; so is an 1116*e4b17023SJohn Marinoaddress that is the sum of a register and a constant (as long as a 1117*e4b17023SJohn Marinoslightly larger constant is also within the range of address-offsets 1118*e4b17023SJohn Marinosupported by the machine); but an autoincrement or autodecrement 1119*e4b17023SJohn Marinoaddress is not offsettable. More complicated indirect/indexed 1120*e4b17023SJohn Marinoaddresses may or may not be offsettable depending on the other 1121*e4b17023SJohn Marinoaddressing modes that the machine supports. 1122*e4b17023SJohn Marino 1123*e4b17023SJohn MarinoNote that in an output operand which can be matched by another 1124*e4b17023SJohn Marinooperand, the constraint letter @samp{o} is valid only when accompanied 1125*e4b17023SJohn Marinoby both @samp{<} (if the target machine has predecrement addressing) 1126*e4b17023SJohn Marinoand @samp{>} (if the target machine has preincrement addressing). 1127*e4b17023SJohn Marino 1128*e4b17023SJohn Marino@cindex @samp{V} in constraint 1129*e4b17023SJohn Marino@item @samp{V} 1130*e4b17023SJohn MarinoA memory operand that is not offsettable. In other words, anything that 1131*e4b17023SJohn Marinowould fit the @samp{m} constraint but not the @samp{o} constraint. 1132*e4b17023SJohn Marino 1133*e4b17023SJohn Marino@cindex @samp{<} in constraint 1134*e4b17023SJohn Marino@item @samp{<} 1135*e4b17023SJohn MarinoA memory operand with autodecrement addressing (either predecrement or 1136*e4b17023SJohn Marinopostdecrement) is allowed. In inline @code{asm} this constraint is only 1137*e4b17023SJohn Marinoallowed if the operand is used exactly once in an instruction that can 1138*e4b17023SJohn Marinohandle the side-effects. Not using an operand with @samp{<} in constraint 1139*e4b17023SJohn Marinostring in the inline @code{asm} pattern at all or using it in multiple 1140*e4b17023SJohn Marinoinstructions isn't valid, because the side-effects wouldn't be performed 1141*e4b17023SJohn Marinoor would be performed more than once. Furthermore, on some targets 1142*e4b17023SJohn Marinothe operand with @samp{<} in constraint string must be accompanied by 1143*e4b17023SJohn Marinospecial instruction suffixes like @code{%U0} instruction suffix on PowerPC 1144*e4b17023SJohn Marinoor @code{%P0} on IA-64. 1145*e4b17023SJohn Marino 1146*e4b17023SJohn Marino@cindex @samp{>} in constraint 1147*e4b17023SJohn Marino@item @samp{>} 1148*e4b17023SJohn MarinoA memory operand with autoincrement addressing (either preincrement or 1149*e4b17023SJohn Marinopostincrement) is allowed. In inline @code{asm} the same restrictions 1150*e4b17023SJohn Marinoas for @samp{<} apply. 1151*e4b17023SJohn Marino 1152*e4b17023SJohn Marino@cindex @samp{r} in constraint 1153*e4b17023SJohn Marino@cindex registers in constraints 1154*e4b17023SJohn Marino@item @samp{r} 1155*e4b17023SJohn MarinoA register operand is allowed provided that it is in a general 1156*e4b17023SJohn Marinoregister. 1157*e4b17023SJohn Marino 1158*e4b17023SJohn Marino@cindex constants in constraints 1159*e4b17023SJohn Marino@cindex @samp{i} in constraint 1160*e4b17023SJohn Marino@item @samp{i} 1161*e4b17023SJohn MarinoAn immediate integer operand (one with constant value) is allowed. 1162*e4b17023SJohn MarinoThis includes symbolic constants whose values will be known only at 1163*e4b17023SJohn Marinoassembly time or later. 1164*e4b17023SJohn Marino 1165*e4b17023SJohn Marino@cindex @samp{n} in constraint 1166*e4b17023SJohn Marino@item @samp{n} 1167*e4b17023SJohn MarinoAn immediate integer operand with a known numeric value is allowed. 1168*e4b17023SJohn MarinoMany systems cannot support assembly-time constants for operands less 1169*e4b17023SJohn Marinothan a word wide. Constraints for these operands should use @samp{n} 1170*e4b17023SJohn Marinorather than @samp{i}. 1171*e4b17023SJohn Marino 1172*e4b17023SJohn Marino@cindex @samp{I} in constraint 1173*e4b17023SJohn Marino@item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P} 1174*e4b17023SJohn MarinoOther letters in the range @samp{I} through @samp{P} may be defined in 1175*e4b17023SJohn Marinoa machine-dependent fashion to permit immediate integer operands with 1176*e4b17023SJohn Marinoexplicit integer values in specified ranges. For example, on the 1177*e4b17023SJohn Marino68000, @samp{I} is defined to stand for the range of values 1 to 8. 1178*e4b17023SJohn MarinoThis is the range permitted as a shift count in the shift 1179*e4b17023SJohn Marinoinstructions. 1180*e4b17023SJohn Marino 1181*e4b17023SJohn Marino@cindex @samp{E} in constraint 1182*e4b17023SJohn Marino@item @samp{E} 1183*e4b17023SJohn MarinoAn immediate floating operand (expression code @code{const_double}) is 1184*e4b17023SJohn Marinoallowed, but only if the target floating point format is the same as 1185*e4b17023SJohn Marinothat of the host machine (on which the compiler is running). 1186*e4b17023SJohn Marino 1187*e4b17023SJohn Marino@cindex @samp{F} in constraint 1188*e4b17023SJohn Marino@item @samp{F} 1189*e4b17023SJohn MarinoAn immediate floating operand (expression code @code{const_double} or 1190*e4b17023SJohn Marino@code{const_vector}) is allowed. 1191*e4b17023SJohn Marino 1192*e4b17023SJohn Marino@cindex @samp{G} in constraint 1193*e4b17023SJohn Marino@cindex @samp{H} in constraint 1194*e4b17023SJohn Marino@item @samp{G}, @samp{H} 1195*e4b17023SJohn Marino@samp{G} and @samp{H} may be defined in a machine-dependent fashion to 1196*e4b17023SJohn Marinopermit immediate floating operands in particular ranges of values. 1197*e4b17023SJohn Marino 1198*e4b17023SJohn Marino@cindex @samp{s} in constraint 1199*e4b17023SJohn Marino@item @samp{s} 1200*e4b17023SJohn MarinoAn immediate integer operand whose value is not an explicit integer is 1201*e4b17023SJohn Marinoallowed. 1202*e4b17023SJohn Marino 1203*e4b17023SJohn MarinoThis might appear strange; if an insn allows a constant operand with a 1204*e4b17023SJohn Marinovalue not known at compile time, it certainly must allow any known 1205*e4b17023SJohn Marinovalue. So why use @samp{s} instead of @samp{i}? Sometimes it allows 1206*e4b17023SJohn Marinobetter code to be generated. 1207*e4b17023SJohn Marino 1208*e4b17023SJohn MarinoFor example, on the 68000 in a fullword instruction it is possible to 1209*e4b17023SJohn Marinouse an immediate operand; but if the immediate value is between @minus{}128 1210*e4b17023SJohn Marinoand 127, better code results from loading the value into a register and 1211*e4b17023SJohn Marinousing the register. This is because the load into the register can be 1212*e4b17023SJohn Marinodone with a @samp{moveq} instruction. We arrange for this to happen 1213*e4b17023SJohn Marinoby defining the letter @samp{K} to mean ``any integer outside the 1214*e4b17023SJohn Marinorange @minus{}128 to 127'', and then specifying @samp{Ks} in the operand 1215*e4b17023SJohn Marinoconstraints. 1216*e4b17023SJohn Marino 1217*e4b17023SJohn Marino@cindex @samp{g} in constraint 1218*e4b17023SJohn Marino@item @samp{g} 1219*e4b17023SJohn MarinoAny register, memory or immediate integer operand is allowed, except for 1220*e4b17023SJohn Marinoregisters that are not general registers. 1221*e4b17023SJohn Marino 1222*e4b17023SJohn Marino@cindex @samp{X} in constraint 1223*e4b17023SJohn Marino@item @samp{X} 1224*e4b17023SJohn Marino@ifset INTERNALS 1225*e4b17023SJohn MarinoAny operand whatsoever is allowed, even if it does not satisfy 1226*e4b17023SJohn Marino@code{general_operand}. This is normally used in the constraint of 1227*e4b17023SJohn Marinoa @code{match_scratch} when certain alternatives will not actually 1228*e4b17023SJohn Marinorequire a scratch register. 1229*e4b17023SJohn Marino@end ifset 1230*e4b17023SJohn Marino@ifclear INTERNALS 1231*e4b17023SJohn MarinoAny operand whatsoever is allowed. 1232*e4b17023SJohn Marino@end ifclear 1233*e4b17023SJohn Marino 1234*e4b17023SJohn Marino@cindex @samp{0} in constraint 1235*e4b17023SJohn Marino@cindex digits in constraint 1236*e4b17023SJohn Marino@item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9} 1237*e4b17023SJohn MarinoAn operand that matches the specified operand number is allowed. If a 1238*e4b17023SJohn Marinodigit is used together with letters within the same alternative, the 1239*e4b17023SJohn Marinodigit should come last. 1240*e4b17023SJohn Marino 1241*e4b17023SJohn MarinoThis number is allowed to be more than a single digit. If multiple 1242*e4b17023SJohn Marinodigits are encountered consecutively, they are interpreted as a single 1243*e4b17023SJohn Marinodecimal integer. There is scant chance for ambiguity, since to-date 1244*e4b17023SJohn Marinoit has never been desirable that @samp{10} be interpreted as matching 1245*e4b17023SJohn Marinoeither operand 1 @emph{or} operand 0. Should this be desired, one 1246*e4b17023SJohn Marinocan use multiple alternatives instead. 1247*e4b17023SJohn Marino 1248*e4b17023SJohn Marino@cindex matching constraint 1249*e4b17023SJohn Marino@cindex constraint, matching 1250*e4b17023SJohn MarinoThis is called a @dfn{matching constraint} and what it really means is 1251*e4b17023SJohn Marinothat the assembler has only a single operand that fills two roles 1252*e4b17023SJohn Marino@ifset INTERNALS 1253*e4b17023SJohn Marinoconsidered separate in the RTL insn. For example, an add insn has two 1254*e4b17023SJohn Marinoinput operands and one output operand in the RTL, but on most CISC 1255*e4b17023SJohn Marino@end ifset 1256*e4b17023SJohn Marino@ifclear INTERNALS 1257*e4b17023SJohn Marinowhich @code{asm} distinguishes. For example, an add instruction uses 1258*e4b17023SJohn Marinotwo input operands and an output operand, but on most CISC 1259*e4b17023SJohn Marino@end ifclear 1260*e4b17023SJohn Marinomachines an add instruction really has only two operands, one of them an 1261*e4b17023SJohn Marinoinput-output operand: 1262*e4b17023SJohn Marino 1263*e4b17023SJohn Marino@smallexample 1264*e4b17023SJohn Marinoaddl #35,r12 1265*e4b17023SJohn Marino@end smallexample 1266*e4b17023SJohn Marino 1267*e4b17023SJohn MarinoMatching constraints are used in these circumstances. 1268*e4b17023SJohn MarinoMore precisely, the two operands that match must include one input-only 1269*e4b17023SJohn Marinooperand and one output-only operand. Moreover, the digit must be a 1270*e4b17023SJohn Marinosmaller number than the number of the operand that uses it in the 1271*e4b17023SJohn Marinoconstraint. 1272*e4b17023SJohn Marino 1273*e4b17023SJohn Marino@ifset INTERNALS 1274*e4b17023SJohn MarinoFor operands to match in a particular case usually means that they 1275*e4b17023SJohn Marinoare identical-looking RTL expressions. But in a few special cases 1276*e4b17023SJohn Marinospecific kinds of dissimilarity are allowed. For example, @code{*x} 1277*e4b17023SJohn Marinoas an input operand will match @code{*x++} as an output operand. 1278*e4b17023SJohn MarinoFor proper results in such cases, the output template should always 1279*e4b17023SJohn Marinouse the output-operand's number when printing the operand. 1280*e4b17023SJohn Marino@end ifset 1281*e4b17023SJohn Marino 1282*e4b17023SJohn Marino@cindex load address instruction 1283*e4b17023SJohn Marino@cindex push address instruction 1284*e4b17023SJohn Marino@cindex address constraints 1285*e4b17023SJohn Marino@cindex @samp{p} in constraint 1286*e4b17023SJohn Marino@item @samp{p} 1287*e4b17023SJohn MarinoAn operand that is a valid memory address is allowed. This is 1288*e4b17023SJohn Marinofor ``load address'' and ``push address'' instructions. 1289*e4b17023SJohn Marino 1290*e4b17023SJohn Marino@findex address_operand 1291*e4b17023SJohn Marino@samp{p} in the constraint must be accompanied by @code{address_operand} 1292*e4b17023SJohn Marinoas the predicate in the @code{match_operand}. This predicate interprets 1293*e4b17023SJohn Marinothe mode specified in the @code{match_operand} as the mode of the memory 1294*e4b17023SJohn Marinoreference for which the address would be valid. 1295*e4b17023SJohn Marino 1296*e4b17023SJohn Marino@cindex other register constraints 1297*e4b17023SJohn Marino@cindex extensible constraints 1298*e4b17023SJohn Marino@item @var{other-letters} 1299*e4b17023SJohn MarinoOther letters can be defined in machine-dependent fashion to stand for 1300*e4b17023SJohn Marinoparticular classes of registers or other arbitrary operand types. 1301*e4b17023SJohn Marino@samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand 1302*e4b17023SJohn Marinofor data, address and floating point registers. 1303*e4b17023SJohn Marino@end table 1304*e4b17023SJohn Marino 1305*e4b17023SJohn Marino@ifset INTERNALS 1306*e4b17023SJohn MarinoIn order to have valid assembler code, each operand must satisfy 1307*e4b17023SJohn Marinoits constraint. But a failure to do so does not prevent the pattern 1308*e4b17023SJohn Marinofrom applying to an insn. Instead, it directs the compiler to modify 1309*e4b17023SJohn Marinothe code so that the constraint will be satisfied. Usually this is 1310*e4b17023SJohn Marinodone by copying an operand into a register. 1311*e4b17023SJohn Marino 1312*e4b17023SJohn MarinoContrast, therefore, the two instruction patterns that follow: 1313*e4b17023SJohn Marino 1314*e4b17023SJohn Marino@smallexample 1315*e4b17023SJohn Marino(define_insn "" 1316*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "=r") 1317*e4b17023SJohn Marino (plus:SI (match_dup 0) 1318*e4b17023SJohn Marino (match_operand:SI 1 "general_operand" "r")))] 1319*e4b17023SJohn Marino "" 1320*e4b17023SJohn Marino "@dots{}") 1321*e4b17023SJohn Marino@end smallexample 1322*e4b17023SJohn Marino 1323*e4b17023SJohn Marino@noindent 1324*e4b17023SJohn Marinowhich has two operands, one of which must appear in two places, and 1325*e4b17023SJohn Marino 1326*e4b17023SJohn Marino@smallexample 1327*e4b17023SJohn Marino(define_insn "" 1328*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "=r") 1329*e4b17023SJohn Marino (plus:SI (match_operand:SI 1 "general_operand" "0") 1330*e4b17023SJohn Marino (match_operand:SI 2 "general_operand" "r")))] 1331*e4b17023SJohn Marino "" 1332*e4b17023SJohn Marino "@dots{}") 1333*e4b17023SJohn Marino@end smallexample 1334*e4b17023SJohn Marino 1335*e4b17023SJohn Marino@noindent 1336*e4b17023SJohn Marinowhich has three operands, two of which are required by a constraint to be 1337*e4b17023SJohn Marinoidentical. If we are considering an insn of the form 1338*e4b17023SJohn Marino 1339*e4b17023SJohn Marino@smallexample 1340*e4b17023SJohn Marino(insn @var{n} @var{prev} @var{next} 1341*e4b17023SJohn Marino (set (reg:SI 3) 1342*e4b17023SJohn Marino (plus:SI (reg:SI 6) (reg:SI 109))) 1343*e4b17023SJohn Marino @dots{}) 1344*e4b17023SJohn Marino@end smallexample 1345*e4b17023SJohn Marino 1346*e4b17023SJohn Marino@noindent 1347*e4b17023SJohn Marinothe first pattern would not apply at all, because this insn does not 1348*e4b17023SJohn Marinocontain two identical subexpressions in the right place. The pattern would 1349*e4b17023SJohn Marinosay, ``That does not look like an add instruction; try other patterns''. 1350*e4b17023SJohn MarinoThe second pattern would say, ``Yes, that's an add instruction, but there 1351*e4b17023SJohn Marinois something wrong with it''. It would direct the reload pass of the 1352*e4b17023SJohn Marinocompiler to generate additional insns to make the constraint true. The 1353*e4b17023SJohn Marinoresults might look like this: 1354*e4b17023SJohn Marino 1355*e4b17023SJohn Marino@smallexample 1356*e4b17023SJohn Marino(insn @var{n2} @var{prev} @var{n} 1357*e4b17023SJohn Marino (set (reg:SI 3) (reg:SI 6)) 1358*e4b17023SJohn Marino @dots{}) 1359*e4b17023SJohn Marino 1360*e4b17023SJohn Marino(insn @var{n} @var{n2} @var{next} 1361*e4b17023SJohn Marino (set (reg:SI 3) 1362*e4b17023SJohn Marino (plus:SI (reg:SI 3) (reg:SI 109))) 1363*e4b17023SJohn Marino @dots{}) 1364*e4b17023SJohn Marino@end smallexample 1365*e4b17023SJohn Marino 1366*e4b17023SJohn MarinoIt is up to you to make sure that each operand, in each pattern, has 1367*e4b17023SJohn Marinoconstraints that can handle any RTL expression that could be present for 1368*e4b17023SJohn Marinothat operand. (When multiple alternatives are in use, each pattern must, 1369*e4b17023SJohn Marinofor each possible combination of operand expressions, have at least one 1370*e4b17023SJohn Marinoalternative which can handle that combination of operands.) The 1371*e4b17023SJohn Marinoconstraints don't need to @emph{allow} any possible operand---when this is 1372*e4b17023SJohn Marinothe case, they do not constrain---but they must at least point the way to 1373*e4b17023SJohn Marinoreloading any possible operand so that it will fit. 1374*e4b17023SJohn Marino 1375*e4b17023SJohn Marino@itemize @bullet 1376*e4b17023SJohn Marino@item 1377*e4b17023SJohn MarinoIf the constraint accepts whatever operands the predicate permits, 1378*e4b17023SJohn Marinothere is no problem: reloading is never necessary for this operand. 1379*e4b17023SJohn Marino 1380*e4b17023SJohn MarinoFor example, an operand whose constraints permit everything except 1381*e4b17023SJohn Marinoregisters is safe provided its predicate rejects registers. 1382*e4b17023SJohn Marino 1383*e4b17023SJohn MarinoAn operand whose predicate accepts only constant values is safe 1384*e4b17023SJohn Marinoprovided its constraints include the letter @samp{i}. If any possible 1385*e4b17023SJohn Marinoconstant value is accepted, then nothing less than @samp{i} will do; 1386*e4b17023SJohn Marinoif the predicate is more selective, then the constraints may also be 1387*e4b17023SJohn Marinomore selective. 1388*e4b17023SJohn Marino 1389*e4b17023SJohn Marino@item 1390*e4b17023SJohn MarinoAny operand expression can be reloaded by copying it into a register. 1391*e4b17023SJohn MarinoSo if an operand's constraints allow some kind of register, it is 1392*e4b17023SJohn Marinocertain to be safe. It need not permit all classes of registers; the 1393*e4b17023SJohn Marinocompiler knows how to copy a register into another register of the 1394*e4b17023SJohn Marinoproper class in order to make an instruction valid. 1395*e4b17023SJohn Marino 1396*e4b17023SJohn Marino@cindex nonoffsettable memory reference 1397*e4b17023SJohn Marino@cindex memory reference, nonoffsettable 1398*e4b17023SJohn Marino@item 1399*e4b17023SJohn MarinoA nonoffsettable memory reference can be reloaded by copying the 1400*e4b17023SJohn Marinoaddress into a register. So if the constraint uses the letter 1401*e4b17023SJohn Marino@samp{o}, all memory references are taken care of. 1402*e4b17023SJohn Marino 1403*e4b17023SJohn Marino@item 1404*e4b17023SJohn MarinoA constant operand can be reloaded by allocating space in memory to 1405*e4b17023SJohn Marinohold it as preinitialized data. Then the memory reference can be used 1406*e4b17023SJohn Marinoin place of the constant. So if the constraint uses the letters 1407*e4b17023SJohn Marino@samp{o} or @samp{m}, constant operands are not a problem. 1408*e4b17023SJohn Marino 1409*e4b17023SJohn Marino@item 1410*e4b17023SJohn MarinoIf the constraint permits a constant and a pseudo register used in an insn 1411*e4b17023SJohn Marinowas not allocated to a hard register and is equivalent to a constant, 1412*e4b17023SJohn Marinothe register will be replaced with the constant. If the predicate does 1413*e4b17023SJohn Marinonot permit a constant and the insn is re-recognized for some reason, the 1414*e4b17023SJohn Marinocompiler will crash. Thus the predicate must always recognize any 1415*e4b17023SJohn Marinoobjects allowed by the constraint. 1416*e4b17023SJohn Marino@end itemize 1417*e4b17023SJohn Marino 1418*e4b17023SJohn MarinoIf the operand's predicate can recognize registers, but the constraint does 1419*e4b17023SJohn Marinonot permit them, it can make the compiler crash. When this operand happens 1420*e4b17023SJohn Marinoto be a register, the reload pass will be stymied, because it does not know 1421*e4b17023SJohn Marinohow to copy a register temporarily into memory. 1422*e4b17023SJohn Marino 1423*e4b17023SJohn MarinoIf the predicate accepts a unary operator, the constraint applies to the 1424*e4b17023SJohn Marinooperand. For example, the MIPS processor at ISA level 3 supports an 1425*e4b17023SJohn Marinoinstruction which adds two registers in @code{SImode} to produce a 1426*e4b17023SJohn Marino@code{DImode} result, but only if the registers are correctly sign 1427*e4b17023SJohn Marinoextended. This predicate for the input operands accepts a 1428*e4b17023SJohn Marino@code{sign_extend} of an @code{SImode} register. Write the constraint 1429*e4b17023SJohn Marinoto indicate the type of register that is required for the operand of the 1430*e4b17023SJohn Marino@code{sign_extend}. 1431*e4b17023SJohn Marino@end ifset 1432*e4b17023SJohn Marino 1433*e4b17023SJohn Marino@node Multi-Alternative 1434*e4b17023SJohn Marino@subsection Multiple Alternative Constraints 1435*e4b17023SJohn Marino@cindex multiple alternative constraints 1436*e4b17023SJohn Marino 1437*e4b17023SJohn MarinoSometimes a single instruction has multiple alternative sets of possible 1438*e4b17023SJohn Marinooperands. For example, on the 68000, a logical-or instruction can combine 1439*e4b17023SJohn Marinoregister or an immediate value into memory, or it can combine any kind of 1440*e4b17023SJohn Marinooperand into a register; but it cannot combine one memory location into 1441*e4b17023SJohn Marinoanother. 1442*e4b17023SJohn Marino 1443*e4b17023SJohn MarinoThese constraints are represented as multiple alternatives. An alternative 1444*e4b17023SJohn Marinocan be described by a series of letters for each operand. The overall 1445*e4b17023SJohn Marinoconstraint for an operand is made from the letters for this operand 1446*e4b17023SJohn Marinofrom the first alternative, a comma, the letters for this operand from 1447*e4b17023SJohn Marinothe second alternative, a comma, and so on until the last alternative. 1448*e4b17023SJohn Marino@ifset INTERNALS 1449*e4b17023SJohn MarinoHere is how it is done for fullword logical-or on the 68000: 1450*e4b17023SJohn Marino 1451*e4b17023SJohn Marino@smallexample 1452*e4b17023SJohn Marino(define_insn "iorsi3" 1453*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "=m,d") 1454*e4b17023SJohn Marino (ior:SI (match_operand:SI 1 "general_operand" "%0,0") 1455*e4b17023SJohn Marino (match_operand:SI 2 "general_operand" "dKs,dmKs")))] 1456*e4b17023SJohn Marino @dots{}) 1457*e4b17023SJohn Marino@end smallexample 1458*e4b17023SJohn Marino 1459*e4b17023SJohn MarinoThe first alternative has @samp{m} (memory) for operand 0, @samp{0} for 1460*e4b17023SJohn Marinooperand 1 (meaning it must match operand 0), and @samp{dKs} for operand 1461*e4b17023SJohn Marino2. The second alternative has @samp{d} (data register) for operand 0, 1462*e4b17023SJohn Marino@samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and 1463*e4b17023SJohn Marino@samp{%} in the constraints apply to all the alternatives; their 1464*e4b17023SJohn Marinomeaning is explained in the next section (@pxref{Class Preferences}). 1465*e4b17023SJohn Marino@end ifset 1466*e4b17023SJohn Marino 1467*e4b17023SJohn Marino@c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL 1468*e4b17023SJohn MarinoIf all the operands fit any one alternative, the instruction is valid. 1469*e4b17023SJohn MarinoOtherwise, for each alternative, the compiler counts how many instructions 1470*e4b17023SJohn Marinomust be added to copy the operands so that that alternative applies. 1471*e4b17023SJohn MarinoThe alternative requiring the least copying is chosen. If two alternatives 1472*e4b17023SJohn Marinoneed the same amount of copying, the one that comes first is chosen. 1473*e4b17023SJohn MarinoThese choices can be altered with the @samp{?} and @samp{!} characters: 1474*e4b17023SJohn Marino 1475*e4b17023SJohn Marino@table @code 1476*e4b17023SJohn Marino@cindex @samp{?} in constraint 1477*e4b17023SJohn Marino@cindex question mark 1478*e4b17023SJohn Marino@item ? 1479*e4b17023SJohn MarinoDisparage slightly the alternative that the @samp{?} appears in, 1480*e4b17023SJohn Marinoas a choice when no alternative applies exactly. The compiler regards 1481*e4b17023SJohn Marinothis alternative as one unit more costly for each @samp{?} that appears 1482*e4b17023SJohn Marinoin it. 1483*e4b17023SJohn Marino 1484*e4b17023SJohn Marino@cindex @samp{!} in constraint 1485*e4b17023SJohn Marino@cindex exclamation point 1486*e4b17023SJohn Marino@item ! 1487*e4b17023SJohn MarinoDisparage severely the alternative that the @samp{!} appears in. 1488*e4b17023SJohn MarinoThis alternative can still be used if it fits without reloading, 1489*e4b17023SJohn Marinobut if reloading is needed, some other alternative will be used. 1490*e4b17023SJohn Marino@end table 1491*e4b17023SJohn Marino 1492*e4b17023SJohn Marino@ifset INTERNALS 1493*e4b17023SJohn MarinoWhen an insn pattern has multiple alternatives in its constraints, often 1494*e4b17023SJohn Marinothe appearance of the assembler code is determined mostly by which 1495*e4b17023SJohn Marinoalternative was matched. When this is so, the C code for writing the 1496*e4b17023SJohn Marinoassembler code can use the variable @code{which_alternative}, which is 1497*e4b17023SJohn Marinothe ordinal number of the alternative that was actually satisfied (0 for 1498*e4b17023SJohn Marinothe first, 1 for the second alternative, etc.). @xref{Output Statement}. 1499*e4b17023SJohn Marino@end ifset 1500*e4b17023SJohn Marino 1501*e4b17023SJohn Marino@ifset INTERNALS 1502*e4b17023SJohn Marino@node Class Preferences 1503*e4b17023SJohn Marino@subsection Register Class Preferences 1504*e4b17023SJohn Marino@cindex class preference constraints 1505*e4b17023SJohn Marino@cindex register class preference constraints 1506*e4b17023SJohn Marino 1507*e4b17023SJohn Marino@cindex voting between constraint alternatives 1508*e4b17023SJohn MarinoThe operand constraints have another function: they enable the compiler 1509*e4b17023SJohn Marinoto decide which kind of hardware register a pseudo register is best 1510*e4b17023SJohn Marinoallocated to. The compiler examines the constraints that apply to the 1511*e4b17023SJohn Marinoinsns that use the pseudo register, looking for the machine-dependent 1512*e4b17023SJohn Marinoletters such as @samp{d} and @samp{a} that specify classes of registers. 1513*e4b17023SJohn MarinoThe pseudo register is put in whichever class gets the most ``votes''. 1514*e4b17023SJohn MarinoThe constraint letters @samp{g} and @samp{r} also vote: they vote in 1515*e4b17023SJohn Marinofavor of a general register. The machine description says which registers 1516*e4b17023SJohn Marinoare considered general. 1517*e4b17023SJohn Marino 1518*e4b17023SJohn MarinoOf course, on some machines all registers are equivalent, and no register 1519*e4b17023SJohn Marinoclasses are defined. Then none of this complexity is relevant. 1520*e4b17023SJohn Marino@end ifset 1521*e4b17023SJohn Marino 1522*e4b17023SJohn Marino@node Modifiers 1523*e4b17023SJohn Marino@subsection Constraint Modifier Characters 1524*e4b17023SJohn Marino@cindex modifiers in constraints 1525*e4b17023SJohn Marino@cindex constraint modifier characters 1526*e4b17023SJohn Marino 1527*e4b17023SJohn Marino@c prevent bad page break with this line 1528*e4b17023SJohn MarinoHere are constraint modifier characters. 1529*e4b17023SJohn Marino 1530*e4b17023SJohn Marino@table @samp 1531*e4b17023SJohn Marino@cindex @samp{=} in constraint 1532*e4b17023SJohn Marino@item = 1533*e4b17023SJohn MarinoMeans that this operand is write-only for this instruction: the previous 1534*e4b17023SJohn Marinovalue is discarded and replaced by output data. 1535*e4b17023SJohn Marino 1536*e4b17023SJohn Marino@cindex @samp{+} in constraint 1537*e4b17023SJohn Marino@item + 1538*e4b17023SJohn MarinoMeans that this operand is both read and written by the instruction. 1539*e4b17023SJohn Marino 1540*e4b17023SJohn MarinoWhen the compiler fixes up the operands to satisfy the constraints, 1541*e4b17023SJohn Marinoit needs to know which operands are inputs to the instruction and 1542*e4b17023SJohn Marinowhich are outputs from it. @samp{=} identifies an output; @samp{+} 1543*e4b17023SJohn Marinoidentifies an operand that is both input and output; all other operands 1544*e4b17023SJohn Marinoare assumed to be input only. 1545*e4b17023SJohn Marino 1546*e4b17023SJohn MarinoIf you specify @samp{=} or @samp{+} in a constraint, you put it in the 1547*e4b17023SJohn Marinofirst character of the constraint string. 1548*e4b17023SJohn Marino 1549*e4b17023SJohn Marino@cindex @samp{&} in constraint 1550*e4b17023SJohn Marino@cindex earlyclobber operand 1551*e4b17023SJohn Marino@item & 1552*e4b17023SJohn MarinoMeans (in a particular alternative) that this operand is an 1553*e4b17023SJohn Marino@dfn{earlyclobber} operand, which is modified before the instruction is 1554*e4b17023SJohn Marinofinished using the input operands. Therefore, this operand may not lie 1555*e4b17023SJohn Marinoin a register that is used as an input operand or as part of any memory 1556*e4b17023SJohn Marinoaddress. 1557*e4b17023SJohn Marino 1558*e4b17023SJohn Marino@samp{&} applies only to the alternative in which it is written. In 1559*e4b17023SJohn Marinoconstraints with multiple alternatives, sometimes one alternative 1560*e4b17023SJohn Marinorequires @samp{&} while others do not. See, for example, the 1561*e4b17023SJohn Marino@samp{movdf} insn of the 68000. 1562*e4b17023SJohn Marino 1563*e4b17023SJohn MarinoAn input operand can be tied to an earlyclobber operand if its only 1564*e4b17023SJohn Marinouse as an input occurs before the early result is written. Adding 1565*e4b17023SJohn Marinoalternatives of this form often allows GCC to produce better code 1566*e4b17023SJohn Marinowhen only some of the inputs can be affected by the earlyclobber. 1567*e4b17023SJohn MarinoSee, for example, the @samp{mulsi3} insn of the ARM@. 1568*e4b17023SJohn Marino 1569*e4b17023SJohn Marino@samp{&} does not obviate the need to write @samp{=}. 1570*e4b17023SJohn Marino 1571*e4b17023SJohn Marino@cindex @samp{%} in constraint 1572*e4b17023SJohn Marino@item % 1573*e4b17023SJohn MarinoDeclares the instruction to be commutative for this operand and the 1574*e4b17023SJohn Marinofollowing operand. This means that the compiler may interchange the 1575*e4b17023SJohn Marinotwo operands if that is the cheapest way to make all operands fit the 1576*e4b17023SJohn Marinoconstraints. 1577*e4b17023SJohn Marino@ifset INTERNALS 1578*e4b17023SJohn MarinoThis is often used in patterns for addition instructions 1579*e4b17023SJohn Marinothat really have only two operands: the result must go in one of the 1580*e4b17023SJohn Marinoarguments. Here for example, is how the 68000 halfword-add 1581*e4b17023SJohn Marinoinstruction is defined: 1582*e4b17023SJohn Marino 1583*e4b17023SJohn Marino@smallexample 1584*e4b17023SJohn Marino(define_insn "addhi3" 1585*e4b17023SJohn Marino [(set (match_operand:HI 0 "general_operand" "=m,r") 1586*e4b17023SJohn Marino (plus:HI (match_operand:HI 1 "general_operand" "%0,0") 1587*e4b17023SJohn Marino (match_operand:HI 2 "general_operand" "di,g")))] 1588*e4b17023SJohn Marino @dots{}) 1589*e4b17023SJohn Marino@end smallexample 1590*e4b17023SJohn Marino@end ifset 1591*e4b17023SJohn MarinoGCC can only handle one commutative pair in an asm; if you use more, 1592*e4b17023SJohn Marinothe compiler may fail. Note that you need not use the modifier if 1593*e4b17023SJohn Marinothe two alternatives are strictly identical; this would only waste 1594*e4b17023SJohn Marinotime in the reload pass. The modifier is not operational after 1595*e4b17023SJohn Marinoregister allocation, so the result of @code{define_peephole2} 1596*e4b17023SJohn Marinoand @code{define_split}s performed after reload cannot rely on 1597*e4b17023SJohn Marino@samp{%} to make the intended insn match. 1598*e4b17023SJohn Marino 1599*e4b17023SJohn Marino@cindex @samp{#} in constraint 1600*e4b17023SJohn Marino@item # 1601*e4b17023SJohn MarinoSays that all following characters, up to the next comma, are to be 1602*e4b17023SJohn Marinoignored as a constraint. They are significant only for choosing 1603*e4b17023SJohn Marinoregister preferences. 1604*e4b17023SJohn Marino 1605*e4b17023SJohn Marino@cindex @samp{*} in constraint 1606*e4b17023SJohn Marino@item * 1607*e4b17023SJohn MarinoSays that the following character should be ignored when choosing 1608*e4b17023SJohn Marinoregister preferences. @samp{*} has no effect on the meaning of the 1609*e4b17023SJohn Marinoconstraint as a constraint, and no effect on reloading. 1610*e4b17023SJohn Marino 1611*e4b17023SJohn Marino@ifset INTERNALS 1612*e4b17023SJohn MarinoHere is an example: the 68000 has an instruction to sign-extend a 1613*e4b17023SJohn Marinohalfword in a data register, and can also sign-extend a value by 1614*e4b17023SJohn Marinocopying it into an address register. While either kind of register is 1615*e4b17023SJohn Marinoacceptable, the constraints on an address-register destination are 1616*e4b17023SJohn Marinoless strict, so it is best if register allocation makes an address 1617*e4b17023SJohn Marinoregister its goal. Therefore, @samp{*} is used so that the @samp{d} 1618*e4b17023SJohn Marinoconstraint letter (for data register) is ignored when computing 1619*e4b17023SJohn Marinoregister preferences. 1620*e4b17023SJohn Marino 1621*e4b17023SJohn Marino@smallexample 1622*e4b17023SJohn Marino(define_insn "extendhisi2" 1623*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "=*d,a") 1624*e4b17023SJohn Marino (sign_extend:SI 1625*e4b17023SJohn Marino (match_operand:HI 1 "general_operand" "0,g")))] 1626*e4b17023SJohn Marino @dots{}) 1627*e4b17023SJohn Marino@end smallexample 1628*e4b17023SJohn Marino@end ifset 1629*e4b17023SJohn Marino@end table 1630*e4b17023SJohn Marino 1631*e4b17023SJohn Marino@node Machine Constraints 1632*e4b17023SJohn Marino@subsection Constraints for Particular Machines 1633*e4b17023SJohn Marino@cindex machine specific constraints 1634*e4b17023SJohn Marino@cindex constraints, machine specific 1635*e4b17023SJohn Marino 1636*e4b17023SJohn MarinoWhenever possible, you should use the general-purpose constraint letters 1637*e4b17023SJohn Marinoin @code{asm} arguments, since they will convey meaning more readily to 1638*e4b17023SJohn Marinopeople reading your code. Failing that, use the constraint letters 1639*e4b17023SJohn Marinothat usually have very similar meanings across architectures. The most 1640*e4b17023SJohn Marinocommonly used constraints are @samp{m} and @samp{r} (for memory and 1641*e4b17023SJohn Marinogeneral-purpose registers respectively; @pxref{Simple Constraints}), and 1642*e4b17023SJohn Marino@samp{I}, usually the letter indicating the most common 1643*e4b17023SJohn Marinoimmediate-constant format. 1644*e4b17023SJohn Marino 1645*e4b17023SJohn MarinoEach architecture defines additional constraints. These constraints 1646*e4b17023SJohn Marinoare used by the compiler itself for instruction generation, as well as 1647*e4b17023SJohn Marinofor @code{asm} statements; therefore, some of the constraints are not 1648*e4b17023SJohn Marinoparticularly useful for @code{asm}. Here is a summary of some of the 1649*e4b17023SJohn Marinomachine-dependent constraints available on some particular machines; 1650*e4b17023SJohn Marinoit includes both constraints that are useful for @code{asm} and 1651*e4b17023SJohn Marinoconstraints that aren't. The compiler source file mentioned in the 1652*e4b17023SJohn Marinotable heading for each architecture is the definitive reference for 1653*e4b17023SJohn Marinothe meanings of that architecture's constraints. 1654*e4b17023SJohn Marino 1655*e4b17023SJohn Marino@table @emph 1656*e4b17023SJohn Marino@item ARM family---@file{config/arm/arm.h} 1657*e4b17023SJohn Marino@table @code 1658*e4b17023SJohn Marino@item f 1659*e4b17023SJohn MarinoFloating-point register 1660*e4b17023SJohn Marino 1661*e4b17023SJohn Marino@item w 1662*e4b17023SJohn MarinoVFP floating-point register 1663*e4b17023SJohn Marino 1664*e4b17023SJohn Marino@item F 1665*e4b17023SJohn MarinoOne of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0 1666*e4b17023SJohn Marinoor 10.0 1667*e4b17023SJohn Marino 1668*e4b17023SJohn Marino@item G 1669*e4b17023SJohn MarinoFloating-point constant that would satisfy the constraint @samp{F} if it 1670*e4b17023SJohn Marinowere negated 1671*e4b17023SJohn Marino 1672*e4b17023SJohn Marino@item I 1673*e4b17023SJohn MarinoInteger that is valid as an immediate operand in a data processing 1674*e4b17023SJohn Marinoinstruction. That is, an integer in the range 0 to 255 rotated by a 1675*e4b17023SJohn Marinomultiple of 2 1676*e4b17023SJohn Marino 1677*e4b17023SJohn Marino@item J 1678*e4b17023SJohn MarinoInteger in the range @minus{}4095 to 4095 1679*e4b17023SJohn Marino 1680*e4b17023SJohn Marino@item K 1681*e4b17023SJohn MarinoInteger that satisfies constraint @samp{I} when inverted (ones complement) 1682*e4b17023SJohn Marino 1683*e4b17023SJohn Marino@item L 1684*e4b17023SJohn MarinoInteger that satisfies constraint @samp{I} when negated (twos complement) 1685*e4b17023SJohn Marino 1686*e4b17023SJohn Marino@item M 1687*e4b17023SJohn MarinoInteger in the range 0 to 32 1688*e4b17023SJohn Marino 1689*e4b17023SJohn Marino@item Q 1690*e4b17023SJohn MarinoA memory reference where the exact address is in a single register 1691*e4b17023SJohn Marino(`@samp{m}' is preferable for @code{asm} statements) 1692*e4b17023SJohn Marino 1693*e4b17023SJohn Marino@item R 1694*e4b17023SJohn MarinoAn item in the constant pool 1695*e4b17023SJohn Marino 1696*e4b17023SJohn Marino@item S 1697*e4b17023SJohn MarinoA symbol in the text segment of the current file 1698*e4b17023SJohn Marino 1699*e4b17023SJohn Marino@item Uv 1700*e4b17023SJohn MarinoA memory reference suitable for VFP load/store insns (reg+constant offset) 1701*e4b17023SJohn Marino 1702*e4b17023SJohn Marino@item Uy 1703*e4b17023SJohn MarinoA memory reference suitable for iWMMXt load/store instructions. 1704*e4b17023SJohn Marino 1705*e4b17023SJohn Marino@item Uq 1706*e4b17023SJohn MarinoA memory reference suitable for the ARMv4 ldrsb instruction. 1707*e4b17023SJohn Marino@end table 1708*e4b17023SJohn Marino 1709*e4b17023SJohn Marino@item AVR family---@file{config/avr/constraints.md} 1710*e4b17023SJohn Marino@table @code 1711*e4b17023SJohn Marino@item l 1712*e4b17023SJohn MarinoRegisters from r0 to r15 1713*e4b17023SJohn Marino 1714*e4b17023SJohn Marino@item a 1715*e4b17023SJohn MarinoRegisters from r16 to r23 1716*e4b17023SJohn Marino 1717*e4b17023SJohn Marino@item d 1718*e4b17023SJohn MarinoRegisters from r16 to r31 1719*e4b17023SJohn Marino 1720*e4b17023SJohn Marino@item w 1721*e4b17023SJohn MarinoRegisters from r24 to r31. These registers can be used in @samp{adiw} command 1722*e4b17023SJohn Marino 1723*e4b17023SJohn Marino@item e 1724*e4b17023SJohn MarinoPointer register (r26--r31) 1725*e4b17023SJohn Marino 1726*e4b17023SJohn Marino@item b 1727*e4b17023SJohn MarinoBase pointer register (r28--r31) 1728*e4b17023SJohn Marino 1729*e4b17023SJohn Marino@item q 1730*e4b17023SJohn MarinoStack pointer register (SPH:SPL) 1731*e4b17023SJohn Marino 1732*e4b17023SJohn Marino@item t 1733*e4b17023SJohn MarinoTemporary register r0 1734*e4b17023SJohn Marino 1735*e4b17023SJohn Marino@item x 1736*e4b17023SJohn MarinoRegister pair X (r27:r26) 1737*e4b17023SJohn Marino 1738*e4b17023SJohn Marino@item y 1739*e4b17023SJohn MarinoRegister pair Y (r29:r28) 1740*e4b17023SJohn Marino 1741*e4b17023SJohn Marino@item z 1742*e4b17023SJohn MarinoRegister pair Z (r31:r30) 1743*e4b17023SJohn Marino 1744*e4b17023SJohn Marino@item I 1745*e4b17023SJohn MarinoConstant greater than @minus{}1, less than 64 1746*e4b17023SJohn Marino 1747*e4b17023SJohn Marino@item J 1748*e4b17023SJohn MarinoConstant greater than @minus{}64, less than 1 1749*e4b17023SJohn Marino 1750*e4b17023SJohn Marino@item K 1751*e4b17023SJohn MarinoConstant integer 2 1752*e4b17023SJohn Marino 1753*e4b17023SJohn Marino@item L 1754*e4b17023SJohn MarinoConstant integer 0 1755*e4b17023SJohn Marino 1756*e4b17023SJohn Marino@item M 1757*e4b17023SJohn MarinoConstant that fits in 8 bits 1758*e4b17023SJohn Marino 1759*e4b17023SJohn Marino@item N 1760*e4b17023SJohn MarinoConstant integer @minus{}1 1761*e4b17023SJohn Marino 1762*e4b17023SJohn Marino@item O 1763*e4b17023SJohn MarinoConstant integer 8, 16, or 24 1764*e4b17023SJohn Marino 1765*e4b17023SJohn Marino@item P 1766*e4b17023SJohn MarinoConstant integer 1 1767*e4b17023SJohn Marino 1768*e4b17023SJohn Marino@item G 1769*e4b17023SJohn MarinoA floating point constant 0.0 1770*e4b17023SJohn Marino 1771*e4b17023SJohn Marino@item Q 1772*e4b17023SJohn MarinoA memory address based on Y or Z pointer with displacement. 1773*e4b17023SJohn Marino@end table 1774*e4b17023SJohn Marino 1775*e4b17023SJohn Marino@item Epiphany---@file{config/epiphany/constraints.md} 1776*e4b17023SJohn Marino@table @code 1777*e4b17023SJohn Marino@item U16 1778*e4b17023SJohn MarinoAn unsigned 16-bit constant. 1779*e4b17023SJohn Marino 1780*e4b17023SJohn Marino@item K 1781*e4b17023SJohn MarinoAn unsigned 5-bit constant. 1782*e4b17023SJohn Marino 1783*e4b17023SJohn Marino@item L 1784*e4b17023SJohn MarinoA signed 11-bit constant. 1785*e4b17023SJohn Marino 1786*e4b17023SJohn Marino@item Cm1 1787*e4b17023SJohn MarinoA signed 11-bit constant added to @minus{}1. 1788*e4b17023SJohn MarinoCan only match when the @option{-m1reg-@var{reg}} option is active. 1789*e4b17023SJohn Marino 1790*e4b17023SJohn Marino@item Cl1 1791*e4b17023SJohn MarinoLeft-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest 1792*e4b17023SJohn Marinobeing a block of trailing zeroes. 1793*e4b17023SJohn MarinoCan only match when the @option{-m1reg-@var{reg}} option is active. 1794*e4b17023SJohn Marino 1795*e4b17023SJohn Marino@item Cr1 1796*e4b17023SJohn MarinoRight-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the 1797*e4b17023SJohn Marinorest being zeroes. Or to put it another way, one less than a power of two. 1798*e4b17023SJohn MarinoCan only match when the @option{-m1reg-@var{reg}} option is active. 1799*e4b17023SJohn Marino 1800*e4b17023SJohn Marino@item Cal 1801*e4b17023SJohn MarinoConstant for arithmetic/logical operations. 1802*e4b17023SJohn MarinoThis is like @code{i}, except that for position independent code, 1803*e4b17023SJohn Marinono symbols / expressions needing relocations are allowed. 1804*e4b17023SJohn Marino 1805*e4b17023SJohn Marino@item Csy 1806*e4b17023SJohn MarinoSymbolic constant for call/jump instruction. 1807*e4b17023SJohn Marino 1808*e4b17023SJohn Marino@item Rcs 1809*e4b17023SJohn MarinoThe register class usable in short insns. This is a register class 1810*e4b17023SJohn Marinoconstraint, and can thus drive register allocation. 1811*e4b17023SJohn MarinoThis constraint won't match unless @option{-mprefer-short-insn-regs} is 1812*e4b17023SJohn Marinoin effect. 1813*e4b17023SJohn Marino 1814*e4b17023SJohn Marino@item Rsc 1815*e4b17023SJohn MarinoThe the register class of registers that can be used to hold a 1816*e4b17023SJohn Marinosibcall call address. I.e., a caller-saved register. 1817*e4b17023SJohn Marino 1818*e4b17023SJohn Marino@item Rct 1819*e4b17023SJohn MarinoCore control register class. 1820*e4b17023SJohn Marino 1821*e4b17023SJohn Marino@item Rgs 1822*e4b17023SJohn MarinoThe register group usable in short insns. 1823*e4b17023SJohn MarinoThis constraint does not use a register class, so that it only 1824*e4b17023SJohn Marinopassively matches suitable registers, and doesn't drive register allocation. 1825*e4b17023SJohn Marino 1826*e4b17023SJohn Marino@ifset INTERNALS 1827*e4b17023SJohn Marino@item Car 1828*e4b17023SJohn MarinoConstant suitable for the addsi3_r pattern. This is a valid offset 1829*e4b17023SJohn MarinoFor byte, halfword, or word addressing. 1830*e4b17023SJohn Marino@end ifset 1831*e4b17023SJohn Marino 1832*e4b17023SJohn Marino@item Rra 1833*e4b17023SJohn MarinoMatches the return address if it can be replaced with the link register. 1834*e4b17023SJohn Marino 1835*e4b17023SJohn Marino@item Rcc 1836*e4b17023SJohn MarinoMatches the integer condition code register. 1837*e4b17023SJohn Marino 1838*e4b17023SJohn Marino@item Sra 1839*e4b17023SJohn MarinoMatches the return address if it is in a stack slot. 1840*e4b17023SJohn Marino 1841*e4b17023SJohn Marino@item Cfm 1842*e4b17023SJohn MarinoMatches control register values to switch fp mode, which are encapsulated in 1843*e4b17023SJohn Marino@code{UNSPEC_FP_MODE}. 1844*e4b17023SJohn Marino@end table 1845*e4b17023SJohn Marino 1846*e4b17023SJohn Marino@item CR16 Architecture---@file{config/cr16/cr16.h} 1847*e4b17023SJohn Marino@table @code 1848*e4b17023SJohn Marino 1849*e4b17023SJohn Marino@item b 1850*e4b17023SJohn MarinoRegisters from r0 to r14 (registers without stack pointer) 1851*e4b17023SJohn Marino 1852*e4b17023SJohn Marino@item t 1853*e4b17023SJohn MarinoRegister from r0 to r11 (all 16-bit registers) 1854*e4b17023SJohn Marino 1855*e4b17023SJohn Marino@item p 1856*e4b17023SJohn MarinoRegister from r12 to r15 (all 32-bit registers) 1857*e4b17023SJohn Marino 1858*e4b17023SJohn Marino@item I 1859*e4b17023SJohn MarinoSigned constant that fits in 4 bits 1860*e4b17023SJohn Marino 1861*e4b17023SJohn Marino@item J 1862*e4b17023SJohn MarinoSigned constant that fits in 5 bits 1863*e4b17023SJohn Marino 1864*e4b17023SJohn Marino@item K 1865*e4b17023SJohn MarinoSigned constant that fits in 6 bits 1866*e4b17023SJohn Marino 1867*e4b17023SJohn Marino@item L 1868*e4b17023SJohn MarinoUnsigned constant that fits in 4 bits 1869*e4b17023SJohn Marino 1870*e4b17023SJohn Marino@item M 1871*e4b17023SJohn MarinoSigned constant that fits in 32 bits 1872*e4b17023SJohn Marino 1873*e4b17023SJohn Marino@item N 1874*e4b17023SJohn MarinoCheck for 64 bits wide constants for add/sub instructions 1875*e4b17023SJohn Marino 1876*e4b17023SJohn Marino@item G 1877*e4b17023SJohn MarinoFloating point constant that is legal for store immediate 1878*e4b17023SJohn Marino@end table 1879*e4b17023SJohn Marino 1880*e4b17023SJohn Marino@item Hewlett-Packard PA-RISC---@file{config/pa/pa.h} 1881*e4b17023SJohn Marino@table @code 1882*e4b17023SJohn Marino@item a 1883*e4b17023SJohn MarinoGeneral register 1 1884*e4b17023SJohn Marino 1885*e4b17023SJohn Marino@item f 1886*e4b17023SJohn MarinoFloating point register 1887*e4b17023SJohn Marino 1888*e4b17023SJohn Marino@item q 1889*e4b17023SJohn MarinoShift amount register 1890*e4b17023SJohn Marino 1891*e4b17023SJohn Marino@item x 1892*e4b17023SJohn MarinoFloating point register (deprecated) 1893*e4b17023SJohn Marino 1894*e4b17023SJohn Marino@item y 1895*e4b17023SJohn MarinoUpper floating point register (32-bit), floating point register (64-bit) 1896*e4b17023SJohn Marino 1897*e4b17023SJohn Marino@item Z 1898*e4b17023SJohn MarinoAny register 1899*e4b17023SJohn Marino 1900*e4b17023SJohn Marino@item I 1901*e4b17023SJohn MarinoSigned 11-bit integer constant 1902*e4b17023SJohn Marino 1903*e4b17023SJohn Marino@item J 1904*e4b17023SJohn MarinoSigned 14-bit integer constant 1905*e4b17023SJohn Marino 1906*e4b17023SJohn Marino@item K 1907*e4b17023SJohn MarinoInteger constant that can be deposited with a @code{zdepi} instruction 1908*e4b17023SJohn Marino 1909*e4b17023SJohn Marino@item L 1910*e4b17023SJohn MarinoSigned 5-bit integer constant 1911*e4b17023SJohn Marino 1912*e4b17023SJohn Marino@item M 1913*e4b17023SJohn MarinoInteger constant 0 1914*e4b17023SJohn Marino 1915*e4b17023SJohn Marino@item N 1916*e4b17023SJohn MarinoInteger constant that can be loaded with a @code{ldil} instruction 1917*e4b17023SJohn Marino 1918*e4b17023SJohn Marino@item O 1919*e4b17023SJohn MarinoInteger constant whose value plus one is a power of 2 1920*e4b17023SJohn Marino 1921*e4b17023SJohn Marino@item P 1922*e4b17023SJohn MarinoInteger constant that can be used for @code{and} operations in @code{depi} 1923*e4b17023SJohn Marinoand @code{extru} instructions 1924*e4b17023SJohn Marino 1925*e4b17023SJohn Marino@item S 1926*e4b17023SJohn MarinoInteger constant 31 1927*e4b17023SJohn Marino 1928*e4b17023SJohn Marino@item U 1929*e4b17023SJohn MarinoInteger constant 63 1930*e4b17023SJohn Marino 1931*e4b17023SJohn Marino@item G 1932*e4b17023SJohn MarinoFloating-point constant 0.0 1933*e4b17023SJohn Marino 1934*e4b17023SJohn Marino@item A 1935*e4b17023SJohn MarinoA @code{lo_sum} data-linkage-table memory operand 1936*e4b17023SJohn Marino 1937*e4b17023SJohn Marino@item Q 1938*e4b17023SJohn MarinoA memory operand that can be used as the destination operand of an 1939*e4b17023SJohn Marinointeger store instruction 1940*e4b17023SJohn Marino 1941*e4b17023SJohn Marino@item R 1942*e4b17023SJohn MarinoA scaled or unscaled indexed memory operand 1943*e4b17023SJohn Marino 1944*e4b17023SJohn Marino@item T 1945*e4b17023SJohn MarinoA memory operand for floating-point loads and stores 1946*e4b17023SJohn Marino 1947*e4b17023SJohn Marino@item W 1948*e4b17023SJohn MarinoA register indirect memory operand 1949*e4b17023SJohn Marino@end table 1950*e4b17023SJohn Marino 1951*e4b17023SJohn Marino@item picoChip family---@file{picochip.h} 1952*e4b17023SJohn Marino@table @code 1953*e4b17023SJohn Marino@item k 1954*e4b17023SJohn MarinoStack register. 1955*e4b17023SJohn Marino 1956*e4b17023SJohn Marino@item f 1957*e4b17023SJohn MarinoPointer register. A register which can be used to access memory without 1958*e4b17023SJohn Marinosupplying an offset. Any other register can be used to access memory, 1959*e4b17023SJohn Marinobut will need a constant offset. In the case of the offset being zero, 1960*e4b17023SJohn Marinoit is more efficient to use a pointer register, since this reduces code 1961*e4b17023SJohn Marinosize. 1962*e4b17023SJohn Marino 1963*e4b17023SJohn Marino@item t 1964*e4b17023SJohn MarinoA twin register. A register which may be paired with an adjacent 1965*e4b17023SJohn Marinoregister to create a 32-bit register. 1966*e4b17023SJohn Marino 1967*e4b17023SJohn Marino@item a 1968*e4b17023SJohn MarinoAny absolute memory address (e.g., symbolic constant, symbolic 1969*e4b17023SJohn Marinoconstant + offset). 1970*e4b17023SJohn Marino 1971*e4b17023SJohn Marino@item I 1972*e4b17023SJohn Marino4-bit signed integer. 1973*e4b17023SJohn Marino 1974*e4b17023SJohn Marino@item J 1975*e4b17023SJohn Marino4-bit unsigned integer. 1976*e4b17023SJohn Marino 1977*e4b17023SJohn Marino@item K 1978*e4b17023SJohn Marino8-bit signed integer. 1979*e4b17023SJohn Marino 1980*e4b17023SJohn Marino@item M 1981*e4b17023SJohn MarinoAny constant whose absolute value is no greater than 4-bits. 1982*e4b17023SJohn Marino 1983*e4b17023SJohn Marino@item N 1984*e4b17023SJohn Marino10-bit signed integer 1985*e4b17023SJohn Marino 1986*e4b17023SJohn Marino@item O 1987*e4b17023SJohn Marino16-bit signed integer. 1988*e4b17023SJohn Marino 1989*e4b17023SJohn Marino@end table 1990*e4b17023SJohn Marino 1991*e4b17023SJohn Marino@item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h} 1992*e4b17023SJohn Marino@table @code 1993*e4b17023SJohn Marino@item b 1994*e4b17023SJohn MarinoAddress base register 1995*e4b17023SJohn Marino 1996*e4b17023SJohn Marino@item d 1997*e4b17023SJohn MarinoFloating point register (containing 64-bit value) 1998*e4b17023SJohn Marino 1999*e4b17023SJohn Marino@item f 2000*e4b17023SJohn MarinoFloating point register (containing 32-bit value) 2001*e4b17023SJohn Marino 2002*e4b17023SJohn Marino@item v 2003*e4b17023SJohn MarinoAltivec vector register 2004*e4b17023SJohn Marino 2005*e4b17023SJohn Marino@item wd 2006*e4b17023SJohn MarinoVSX vector register to hold vector double data 2007*e4b17023SJohn Marino 2008*e4b17023SJohn Marino@item wf 2009*e4b17023SJohn MarinoVSX vector register to hold vector float data 2010*e4b17023SJohn Marino 2011*e4b17023SJohn Marino@item ws 2012*e4b17023SJohn MarinoVSX vector register to hold scalar float data 2013*e4b17023SJohn Marino 2014*e4b17023SJohn Marino@item wa 2015*e4b17023SJohn MarinoAny VSX register 2016*e4b17023SJohn Marino 2017*e4b17023SJohn Marino@item h 2018*e4b17023SJohn Marino@samp{MQ}, @samp{CTR}, or @samp{LINK} register 2019*e4b17023SJohn Marino 2020*e4b17023SJohn Marino@item q 2021*e4b17023SJohn Marino@samp{MQ} register 2022*e4b17023SJohn Marino 2023*e4b17023SJohn Marino@item c 2024*e4b17023SJohn Marino@samp{CTR} register 2025*e4b17023SJohn Marino 2026*e4b17023SJohn Marino@item l 2027*e4b17023SJohn Marino@samp{LINK} register 2028*e4b17023SJohn Marino 2029*e4b17023SJohn Marino@item x 2030*e4b17023SJohn Marino@samp{CR} register (condition register) number 0 2031*e4b17023SJohn Marino 2032*e4b17023SJohn Marino@item y 2033*e4b17023SJohn Marino@samp{CR} register (condition register) 2034*e4b17023SJohn Marino 2035*e4b17023SJohn Marino@item z 2036*e4b17023SJohn Marino@samp{XER[CA]} carry bit (part of the XER register) 2037*e4b17023SJohn Marino 2038*e4b17023SJohn Marino@item I 2039*e4b17023SJohn MarinoSigned 16-bit constant 2040*e4b17023SJohn Marino 2041*e4b17023SJohn Marino@item J 2042*e4b17023SJohn MarinoUnsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for 2043*e4b17023SJohn Marino@code{SImode} constants) 2044*e4b17023SJohn Marino 2045*e4b17023SJohn Marino@item K 2046*e4b17023SJohn MarinoUnsigned 16-bit constant 2047*e4b17023SJohn Marino 2048*e4b17023SJohn Marino@item L 2049*e4b17023SJohn MarinoSigned 16-bit constant shifted left 16 bits 2050*e4b17023SJohn Marino 2051*e4b17023SJohn Marino@item M 2052*e4b17023SJohn MarinoConstant larger than 31 2053*e4b17023SJohn Marino 2054*e4b17023SJohn Marino@item N 2055*e4b17023SJohn MarinoExact power of 2 2056*e4b17023SJohn Marino 2057*e4b17023SJohn Marino@item O 2058*e4b17023SJohn MarinoZero 2059*e4b17023SJohn Marino 2060*e4b17023SJohn Marino@item P 2061*e4b17023SJohn MarinoConstant whose negation is a signed 16-bit constant 2062*e4b17023SJohn Marino 2063*e4b17023SJohn Marino@item G 2064*e4b17023SJohn MarinoFloating point constant that can be loaded into a register with one 2065*e4b17023SJohn Marinoinstruction per word 2066*e4b17023SJohn Marino 2067*e4b17023SJohn Marino@item H 2068*e4b17023SJohn MarinoInteger/Floating point constant that can be loaded into a register using 2069*e4b17023SJohn Marinothree instructions 2070*e4b17023SJohn Marino 2071*e4b17023SJohn Marino@item m 2072*e4b17023SJohn MarinoMemory operand. 2073*e4b17023SJohn MarinoNormally, @code{m} does not allow addresses that update the base register. 2074*e4b17023SJohn MarinoIf @samp{<} or @samp{>} constraint is also used, they are allowed and 2075*e4b17023SJohn Marinotherefore on PowerPC targets in that case it is only safe 2076*e4b17023SJohn Marinoto use @samp{m<>} in an @code{asm} statement if that @code{asm} statement 2077*e4b17023SJohn Marinoaccesses the operand exactly once. The @code{asm} statement must also 2078*e4b17023SJohn Marinouse @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the 2079*e4b17023SJohn Marinocorresponding load or store instruction. For example: 2080*e4b17023SJohn Marino 2081*e4b17023SJohn Marino@smallexample 2082*e4b17023SJohn Marinoasm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val)); 2083*e4b17023SJohn Marino@end smallexample 2084*e4b17023SJohn Marino 2085*e4b17023SJohn Marinois correct but: 2086*e4b17023SJohn Marino 2087*e4b17023SJohn Marino@smallexample 2088*e4b17023SJohn Marinoasm ("st %1,%0" : "=m<>" (mem) : "r" (val)); 2089*e4b17023SJohn Marino@end smallexample 2090*e4b17023SJohn Marino 2091*e4b17023SJohn Marinois not. 2092*e4b17023SJohn Marino 2093*e4b17023SJohn Marino@item es 2094*e4b17023SJohn MarinoA ``stable'' memory operand; that is, one which does not include any 2095*e4b17023SJohn Marinoautomodification of the base register. This used to be useful when 2096*e4b17023SJohn Marino@samp{m} allowed automodification of the base register, but as those are now only 2097*e4b17023SJohn Marinoallowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same 2098*e4b17023SJohn Marinoas @samp{m} without @samp{<} and @samp{>}. 2099*e4b17023SJohn Marino 2100*e4b17023SJohn Marino@item Q 2101*e4b17023SJohn MarinoMemory operand that is an offset from a register (it is usually better 2102*e4b17023SJohn Marinoto use @samp{m} or @samp{es} in @code{asm} statements) 2103*e4b17023SJohn Marino 2104*e4b17023SJohn Marino@item Z 2105*e4b17023SJohn MarinoMemory operand that is an indexed or indirect from a register (it is 2106*e4b17023SJohn Marinousually better to use @samp{m} or @samp{es} in @code{asm} statements) 2107*e4b17023SJohn Marino 2108*e4b17023SJohn Marino@item R 2109*e4b17023SJohn MarinoAIX TOC entry 2110*e4b17023SJohn Marino 2111*e4b17023SJohn Marino@item a 2112*e4b17023SJohn MarinoAddress operand that is an indexed or indirect from a register (@samp{p} is 2113*e4b17023SJohn Marinopreferable for @code{asm} statements) 2114*e4b17023SJohn Marino 2115*e4b17023SJohn Marino@item S 2116*e4b17023SJohn MarinoConstant suitable as a 64-bit mask operand 2117*e4b17023SJohn Marino 2118*e4b17023SJohn Marino@item T 2119*e4b17023SJohn MarinoConstant suitable as a 32-bit mask operand 2120*e4b17023SJohn Marino 2121*e4b17023SJohn Marino@item U 2122*e4b17023SJohn MarinoSystem V Release 4 small data area reference 2123*e4b17023SJohn Marino 2124*e4b17023SJohn Marino@item t 2125*e4b17023SJohn MarinoAND masks that can be performed by two rldic@{l, r@} instructions 2126*e4b17023SJohn Marino 2127*e4b17023SJohn Marino@item W 2128*e4b17023SJohn MarinoVector constant that does not require memory 2129*e4b17023SJohn Marino 2130*e4b17023SJohn Marino@item j 2131*e4b17023SJohn MarinoVector constant that is all zeros. 2132*e4b17023SJohn Marino 2133*e4b17023SJohn Marino@end table 2134*e4b17023SJohn Marino 2135*e4b17023SJohn Marino@item Intel 386---@file{config/i386/constraints.md} 2136*e4b17023SJohn Marino@table @code 2137*e4b17023SJohn Marino@item R 2138*e4b17023SJohn MarinoLegacy register---the eight integer registers available on all 2139*e4b17023SJohn Marinoi386 processors (@code{a}, @code{b}, @code{c}, @code{d}, 2140*e4b17023SJohn Marino@code{si}, @code{di}, @code{bp}, @code{sp}). 2141*e4b17023SJohn Marino 2142*e4b17023SJohn Marino@item q 2143*e4b17023SJohn MarinoAny register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, 2144*e4b17023SJohn Marino@code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register. 2145*e4b17023SJohn Marino 2146*e4b17023SJohn Marino@item Q 2147*e4b17023SJohn MarinoAny register accessible as @code{@var{r}h}: @code{a}, @code{b}, 2148*e4b17023SJohn Marino@code{c}, and @code{d}. 2149*e4b17023SJohn Marino 2150*e4b17023SJohn Marino@ifset INTERNALS 2151*e4b17023SJohn Marino@item l 2152*e4b17023SJohn MarinoAny register that can be used as the index in a base+index memory 2153*e4b17023SJohn Marinoaccess: that is, any general register except the stack pointer. 2154*e4b17023SJohn Marino@end ifset 2155*e4b17023SJohn Marino 2156*e4b17023SJohn Marino@item a 2157*e4b17023SJohn MarinoThe @code{a} register. 2158*e4b17023SJohn Marino 2159*e4b17023SJohn Marino@item b 2160*e4b17023SJohn MarinoThe @code{b} register. 2161*e4b17023SJohn Marino 2162*e4b17023SJohn Marino@item c 2163*e4b17023SJohn MarinoThe @code{c} register. 2164*e4b17023SJohn Marino 2165*e4b17023SJohn Marino@item d 2166*e4b17023SJohn MarinoThe @code{d} register. 2167*e4b17023SJohn Marino 2168*e4b17023SJohn Marino@item S 2169*e4b17023SJohn MarinoThe @code{si} register. 2170*e4b17023SJohn Marino 2171*e4b17023SJohn Marino@item D 2172*e4b17023SJohn MarinoThe @code{di} register. 2173*e4b17023SJohn Marino 2174*e4b17023SJohn Marino@item A 2175*e4b17023SJohn MarinoThe @code{a} and @code{d} registers. This class is used for instructions 2176*e4b17023SJohn Marinothat return double word results in the @code{ax:dx} register pair. Single 2177*e4b17023SJohn Marinoword values will be allocated either in @code{ax} or @code{dx}. 2178*e4b17023SJohn MarinoFor example on i386 the following implements @code{rdtsc}: 2179*e4b17023SJohn Marino 2180*e4b17023SJohn Marino@smallexample 2181*e4b17023SJohn Marinounsigned long long rdtsc (void) 2182*e4b17023SJohn Marino@{ 2183*e4b17023SJohn Marino unsigned long long tick; 2184*e4b17023SJohn Marino __asm__ __volatile__("rdtsc":"=A"(tick)); 2185*e4b17023SJohn Marino return tick; 2186*e4b17023SJohn Marino@} 2187*e4b17023SJohn Marino@end smallexample 2188*e4b17023SJohn Marino 2189*e4b17023SJohn MarinoThis is not correct on x86_64 as it would allocate tick in either @code{ax} 2190*e4b17023SJohn Marinoor @code{dx}. You have to use the following variant instead: 2191*e4b17023SJohn Marino 2192*e4b17023SJohn Marino@smallexample 2193*e4b17023SJohn Marinounsigned long long rdtsc (void) 2194*e4b17023SJohn Marino@{ 2195*e4b17023SJohn Marino unsigned int tickl, tickh; 2196*e4b17023SJohn Marino __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh)); 2197*e4b17023SJohn Marino return ((unsigned long long)tickh << 32)|tickl; 2198*e4b17023SJohn Marino@} 2199*e4b17023SJohn Marino@end smallexample 2200*e4b17023SJohn Marino 2201*e4b17023SJohn Marino 2202*e4b17023SJohn Marino@item f 2203*e4b17023SJohn MarinoAny 80387 floating-point (stack) register. 2204*e4b17023SJohn Marino 2205*e4b17023SJohn Marino@item t 2206*e4b17023SJohn MarinoTop of 80387 floating-point stack (@code{%st(0)}). 2207*e4b17023SJohn Marino 2208*e4b17023SJohn Marino@item u 2209*e4b17023SJohn MarinoSecond from top of 80387 floating-point stack (@code{%st(1)}). 2210*e4b17023SJohn Marino 2211*e4b17023SJohn Marino@item y 2212*e4b17023SJohn MarinoAny MMX register. 2213*e4b17023SJohn Marino 2214*e4b17023SJohn Marino@item x 2215*e4b17023SJohn MarinoAny SSE register. 2216*e4b17023SJohn Marino 2217*e4b17023SJohn Marino@item Yz 2218*e4b17023SJohn MarinoFirst SSE register (@code{%xmm0}). 2219*e4b17023SJohn Marino 2220*e4b17023SJohn Marino@ifset INTERNALS 2221*e4b17023SJohn Marino@item Y2 2222*e4b17023SJohn MarinoAny SSE register, when SSE2 is enabled. 2223*e4b17023SJohn Marino 2224*e4b17023SJohn Marino@item Yi 2225*e4b17023SJohn MarinoAny SSE register, when SSE2 and inter-unit moves are enabled. 2226*e4b17023SJohn Marino 2227*e4b17023SJohn Marino@item Ym 2228*e4b17023SJohn MarinoAny MMX register, when inter-unit moves are enabled. 2229*e4b17023SJohn Marino@end ifset 2230*e4b17023SJohn Marino 2231*e4b17023SJohn Marino@item I 2232*e4b17023SJohn MarinoInteger constant in the range 0 @dots{} 31, for 32-bit shifts. 2233*e4b17023SJohn Marino 2234*e4b17023SJohn Marino@item J 2235*e4b17023SJohn MarinoInteger constant in the range 0 @dots{} 63, for 64-bit shifts. 2236*e4b17023SJohn Marino 2237*e4b17023SJohn Marino@item K 2238*e4b17023SJohn MarinoSigned 8-bit integer constant. 2239*e4b17023SJohn Marino 2240*e4b17023SJohn Marino@item L 2241*e4b17023SJohn Marino@code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move. 2242*e4b17023SJohn Marino 2243*e4b17023SJohn Marino@item M 2244*e4b17023SJohn Marino0, 1, 2, or 3 (shifts for the @code{lea} instruction). 2245*e4b17023SJohn Marino 2246*e4b17023SJohn Marino@item N 2247*e4b17023SJohn MarinoUnsigned 8-bit integer constant (for @code{in} and @code{out} 2248*e4b17023SJohn Marinoinstructions). 2249*e4b17023SJohn Marino 2250*e4b17023SJohn Marino@ifset INTERNALS 2251*e4b17023SJohn Marino@item O 2252*e4b17023SJohn MarinoInteger constant in the range 0 @dots{} 127, for 128-bit shifts. 2253*e4b17023SJohn Marino@end ifset 2254*e4b17023SJohn Marino 2255*e4b17023SJohn Marino@item G 2256*e4b17023SJohn MarinoStandard 80387 floating point constant. 2257*e4b17023SJohn Marino 2258*e4b17023SJohn Marino@item C 2259*e4b17023SJohn MarinoStandard SSE floating point constant. 2260*e4b17023SJohn Marino 2261*e4b17023SJohn Marino@item e 2262*e4b17023SJohn Marino32-bit signed integer constant, or a symbolic reference known 2263*e4b17023SJohn Marinoto fit that range (for immediate operands in sign-extending x86-64 2264*e4b17023SJohn Marinoinstructions). 2265*e4b17023SJohn Marino 2266*e4b17023SJohn Marino@item Z 2267*e4b17023SJohn Marino32-bit unsigned integer constant, or a symbolic reference known 2268*e4b17023SJohn Marinoto fit that range (for immediate operands in zero-extending x86-64 2269*e4b17023SJohn Marinoinstructions). 2270*e4b17023SJohn Marino 2271*e4b17023SJohn Marino@end table 2272*e4b17023SJohn Marino 2273*e4b17023SJohn Marino@item Intel IA-64---@file{config/ia64/ia64.h} 2274*e4b17023SJohn Marino@table @code 2275*e4b17023SJohn Marino@item a 2276*e4b17023SJohn MarinoGeneral register @code{r0} to @code{r3} for @code{addl} instruction 2277*e4b17023SJohn Marino 2278*e4b17023SJohn Marino@item b 2279*e4b17023SJohn MarinoBranch register 2280*e4b17023SJohn Marino 2281*e4b17023SJohn Marino@item c 2282*e4b17023SJohn MarinoPredicate register (@samp{c} as in ``conditional'') 2283*e4b17023SJohn Marino 2284*e4b17023SJohn Marino@item d 2285*e4b17023SJohn MarinoApplication register residing in M-unit 2286*e4b17023SJohn Marino 2287*e4b17023SJohn Marino@item e 2288*e4b17023SJohn MarinoApplication register residing in I-unit 2289*e4b17023SJohn Marino 2290*e4b17023SJohn Marino@item f 2291*e4b17023SJohn MarinoFloating-point register 2292*e4b17023SJohn Marino 2293*e4b17023SJohn Marino@item m 2294*e4b17023SJohn MarinoMemory operand. If used together with @samp{<} or @samp{>}, 2295*e4b17023SJohn Marinothe operand can have postincrement and postdecrement which 2296*e4b17023SJohn Marinorequire printing with @samp{%Pn} on IA-64. 2297*e4b17023SJohn Marino 2298*e4b17023SJohn Marino@item G 2299*e4b17023SJohn MarinoFloating-point constant 0.0 or 1.0 2300*e4b17023SJohn Marino 2301*e4b17023SJohn Marino@item I 2302*e4b17023SJohn Marino14-bit signed integer constant 2303*e4b17023SJohn Marino 2304*e4b17023SJohn Marino@item J 2305*e4b17023SJohn Marino22-bit signed integer constant 2306*e4b17023SJohn Marino 2307*e4b17023SJohn Marino@item K 2308*e4b17023SJohn Marino8-bit signed integer constant for logical instructions 2309*e4b17023SJohn Marino 2310*e4b17023SJohn Marino@item L 2311*e4b17023SJohn Marino8-bit adjusted signed integer constant for compare pseudo-ops 2312*e4b17023SJohn Marino 2313*e4b17023SJohn Marino@item M 2314*e4b17023SJohn Marino6-bit unsigned integer constant for shift counts 2315*e4b17023SJohn Marino 2316*e4b17023SJohn Marino@item N 2317*e4b17023SJohn Marino9-bit signed integer constant for load and store postincrements 2318*e4b17023SJohn Marino 2319*e4b17023SJohn Marino@item O 2320*e4b17023SJohn MarinoThe constant zero 2321*e4b17023SJohn Marino 2322*e4b17023SJohn Marino@item P 2323*e4b17023SJohn Marino0 or @minus{}1 for @code{dep} instruction 2324*e4b17023SJohn Marino 2325*e4b17023SJohn Marino@item Q 2326*e4b17023SJohn MarinoNon-volatile memory for floating-point loads and stores 2327*e4b17023SJohn Marino 2328*e4b17023SJohn Marino@item R 2329*e4b17023SJohn MarinoInteger constant in the range 1 to 4 for @code{shladd} instruction 2330*e4b17023SJohn Marino 2331*e4b17023SJohn Marino@item S 2332*e4b17023SJohn MarinoMemory operand except postincrement and postdecrement. This is 2333*e4b17023SJohn Marinonow roughly the same as @samp{m} when not used together with @samp{<} 2334*e4b17023SJohn Marinoor @samp{>}. 2335*e4b17023SJohn Marino@end table 2336*e4b17023SJohn Marino 2337*e4b17023SJohn Marino@item FRV---@file{config/frv/frv.h} 2338*e4b17023SJohn Marino@table @code 2339*e4b17023SJohn Marino@item a 2340*e4b17023SJohn MarinoRegister in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}). 2341*e4b17023SJohn Marino 2342*e4b17023SJohn Marino@item b 2343*e4b17023SJohn MarinoRegister in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}). 2344*e4b17023SJohn Marino 2345*e4b17023SJohn Marino@item c 2346*e4b17023SJohn MarinoRegister in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and 2347*e4b17023SJohn Marino@code{icc0} to @code{icc3}). 2348*e4b17023SJohn Marino 2349*e4b17023SJohn Marino@item d 2350*e4b17023SJohn MarinoRegister in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}). 2351*e4b17023SJohn Marino 2352*e4b17023SJohn Marino@item e 2353*e4b17023SJohn MarinoRegister in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}). 2354*e4b17023SJohn MarinoOdd registers are excluded not in the class but through the use of a machine 2355*e4b17023SJohn Marinomode larger than 4 bytes. 2356*e4b17023SJohn Marino 2357*e4b17023SJohn Marino@item f 2358*e4b17023SJohn MarinoRegister in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}). 2359*e4b17023SJohn Marino 2360*e4b17023SJohn Marino@item h 2361*e4b17023SJohn MarinoRegister in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}). 2362*e4b17023SJohn MarinoOdd registers are excluded not in the class but through the use of a machine 2363*e4b17023SJohn Marinomode larger than 4 bytes. 2364*e4b17023SJohn Marino 2365*e4b17023SJohn Marino@item l 2366*e4b17023SJohn MarinoRegister in the class @code{LR_REG} (the @code{lr} register). 2367*e4b17023SJohn Marino 2368*e4b17023SJohn Marino@item q 2369*e4b17023SJohn MarinoRegister in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}). 2370*e4b17023SJohn MarinoRegister numbers not divisible by 4 are excluded not in the class but through 2371*e4b17023SJohn Marinothe use of a machine mode larger than 8 bytes. 2372*e4b17023SJohn Marino 2373*e4b17023SJohn Marino@item t 2374*e4b17023SJohn MarinoRegister in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}). 2375*e4b17023SJohn Marino 2376*e4b17023SJohn Marino@item u 2377*e4b17023SJohn MarinoRegister in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}). 2378*e4b17023SJohn Marino 2379*e4b17023SJohn Marino@item v 2380*e4b17023SJohn MarinoRegister in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}). 2381*e4b17023SJohn Marino 2382*e4b17023SJohn Marino@item w 2383*e4b17023SJohn MarinoRegister in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}). 2384*e4b17023SJohn Marino 2385*e4b17023SJohn Marino@item x 2386*e4b17023SJohn MarinoRegister in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}). 2387*e4b17023SJohn MarinoRegister numbers not divisible by 4 are excluded not in the class but through 2388*e4b17023SJohn Marinothe use of a machine mode larger than 8 bytes. 2389*e4b17023SJohn Marino 2390*e4b17023SJohn Marino@item z 2391*e4b17023SJohn MarinoRegister in the class @code{SPR_REGS} (@code{lcr} and @code{lr}). 2392*e4b17023SJohn Marino 2393*e4b17023SJohn Marino@item A 2394*e4b17023SJohn MarinoRegister in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}). 2395*e4b17023SJohn Marino 2396*e4b17023SJohn Marino@item B 2397*e4b17023SJohn MarinoRegister in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}). 2398*e4b17023SJohn Marino 2399*e4b17023SJohn Marino@item C 2400*e4b17023SJohn MarinoRegister in the class @code{CR_REGS} (@code{cc0} to @code{cc7}). 2401*e4b17023SJohn Marino 2402*e4b17023SJohn Marino@item G 2403*e4b17023SJohn MarinoFloating point constant zero 2404*e4b17023SJohn Marino 2405*e4b17023SJohn Marino@item I 2406*e4b17023SJohn Marino6-bit signed integer constant 2407*e4b17023SJohn Marino 2408*e4b17023SJohn Marino@item J 2409*e4b17023SJohn Marino10-bit signed integer constant 2410*e4b17023SJohn Marino 2411*e4b17023SJohn Marino@item L 2412*e4b17023SJohn Marino16-bit signed integer constant 2413*e4b17023SJohn Marino 2414*e4b17023SJohn Marino@item M 2415*e4b17023SJohn Marino16-bit unsigned integer constant 2416*e4b17023SJohn Marino 2417*e4b17023SJohn Marino@item N 2418*e4b17023SJohn Marino12-bit signed integer constant that is negative---i.e.@: in the 2419*e4b17023SJohn Marinorange of @minus{}2048 to @minus{}1 2420*e4b17023SJohn Marino 2421*e4b17023SJohn Marino@item O 2422*e4b17023SJohn MarinoConstant zero 2423*e4b17023SJohn Marino 2424*e4b17023SJohn Marino@item P 2425*e4b17023SJohn Marino12-bit signed integer constant that is greater than zero---i.e.@: in the 2426*e4b17023SJohn Marinorange of 1 to 2047. 2427*e4b17023SJohn Marino 2428*e4b17023SJohn Marino@end table 2429*e4b17023SJohn Marino 2430*e4b17023SJohn Marino@item Blackfin family---@file{config/bfin/constraints.md} 2431*e4b17023SJohn Marino@table @code 2432*e4b17023SJohn Marino@item a 2433*e4b17023SJohn MarinoP register 2434*e4b17023SJohn Marino 2435*e4b17023SJohn Marino@item d 2436*e4b17023SJohn MarinoD register 2437*e4b17023SJohn Marino 2438*e4b17023SJohn Marino@item z 2439*e4b17023SJohn MarinoA call clobbered P register. 2440*e4b17023SJohn Marino 2441*e4b17023SJohn Marino@item q@var{n} 2442*e4b17023SJohn MarinoA single register. If @var{n} is in the range 0 to 7, the corresponding D 2443*e4b17023SJohn Marinoregister. If it is @code{A}, then the register P0. 2444*e4b17023SJohn Marino 2445*e4b17023SJohn Marino@item D 2446*e4b17023SJohn MarinoEven-numbered D register 2447*e4b17023SJohn Marino 2448*e4b17023SJohn Marino@item W 2449*e4b17023SJohn MarinoOdd-numbered D register 2450*e4b17023SJohn Marino 2451*e4b17023SJohn Marino@item e 2452*e4b17023SJohn MarinoAccumulator register. 2453*e4b17023SJohn Marino 2454*e4b17023SJohn Marino@item A 2455*e4b17023SJohn MarinoEven-numbered accumulator register. 2456*e4b17023SJohn Marino 2457*e4b17023SJohn Marino@item B 2458*e4b17023SJohn MarinoOdd-numbered accumulator register. 2459*e4b17023SJohn Marino 2460*e4b17023SJohn Marino@item b 2461*e4b17023SJohn MarinoI register 2462*e4b17023SJohn Marino 2463*e4b17023SJohn Marino@item v 2464*e4b17023SJohn MarinoB register 2465*e4b17023SJohn Marino 2466*e4b17023SJohn Marino@item f 2467*e4b17023SJohn MarinoM register 2468*e4b17023SJohn Marino 2469*e4b17023SJohn Marino@item c 2470*e4b17023SJohn MarinoRegisters used for circular buffering, i.e. I, B, or L registers. 2471*e4b17023SJohn Marino 2472*e4b17023SJohn Marino@item C 2473*e4b17023SJohn MarinoThe CC register. 2474*e4b17023SJohn Marino 2475*e4b17023SJohn Marino@item t 2476*e4b17023SJohn MarinoLT0 or LT1. 2477*e4b17023SJohn Marino 2478*e4b17023SJohn Marino@item k 2479*e4b17023SJohn MarinoLC0 or LC1. 2480*e4b17023SJohn Marino 2481*e4b17023SJohn Marino@item u 2482*e4b17023SJohn MarinoLB0 or LB1. 2483*e4b17023SJohn Marino 2484*e4b17023SJohn Marino@item x 2485*e4b17023SJohn MarinoAny D, P, B, M, I or L register. 2486*e4b17023SJohn Marino 2487*e4b17023SJohn Marino@item y 2488*e4b17023SJohn MarinoAdditional registers typically used only in prologues and epilogues: RETS, 2489*e4b17023SJohn MarinoRETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP. 2490*e4b17023SJohn Marino 2491*e4b17023SJohn Marino@item w 2492*e4b17023SJohn MarinoAny register except accumulators or CC. 2493*e4b17023SJohn Marino 2494*e4b17023SJohn Marino@item Ksh 2495*e4b17023SJohn MarinoSigned 16 bit integer (in the range @minus{}32768 to 32767) 2496*e4b17023SJohn Marino 2497*e4b17023SJohn Marino@item Kuh 2498*e4b17023SJohn MarinoUnsigned 16 bit integer (in the range 0 to 65535) 2499*e4b17023SJohn Marino 2500*e4b17023SJohn Marino@item Ks7 2501*e4b17023SJohn MarinoSigned 7 bit integer (in the range @minus{}64 to 63) 2502*e4b17023SJohn Marino 2503*e4b17023SJohn Marino@item Ku7 2504*e4b17023SJohn MarinoUnsigned 7 bit integer (in the range 0 to 127) 2505*e4b17023SJohn Marino 2506*e4b17023SJohn Marino@item Ku5 2507*e4b17023SJohn MarinoUnsigned 5 bit integer (in the range 0 to 31) 2508*e4b17023SJohn Marino 2509*e4b17023SJohn Marino@item Ks4 2510*e4b17023SJohn MarinoSigned 4 bit integer (in the range @minus{}8 to 7) 2511*e4b17023SJohn Marino 2512*e4b17023SJohn Marino@item Ks3 2513*e4b17023SJohn MarinoSigned 3 bit integer (in the range @minus{}3 to 4) 2514*e4b17023SJohn Marino 2515*e4b17023SJohn Marino@item Ku3 2516*e4b17023SJohn MarinoUnsigned 3 bit integer (in the range 0 to 7) 2517*e4b17023SJohn Marino 2518*e4b17023SJohn Marino@item P@var{n} 2519*e4b17023SJohn MarinoConstant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4. 2520*e4b17023SJohn Marino 2521*e4b17023SJohn Marino@item PA 2522*e4b17023SJohn MarinoAn integer equal to one of the MACFLAG_XXX constants that is suitable for 2523*e4b17023SJohn Marinouse with either accumulator. 2524*e4b17023SJohn Marino 2525*e4b17023SJohn Marino@item PB 2526*e4b17023SJohn MarinoAn integer equal to one of the MACFLAG_XXX constants that is suitable for 2527*e4b17023SJohn Marinouse only with accumulator A1. 2528*e4b17023SJohn Marino 2529*e4b17023SJohn Marino@item M1 2530*e4b17023SJohn MarinoConstant 255. 2531*e4b17023SJohn Marino 2532*e4b17023SJohn Marino@item M2 2533*e4b17023SJohn MarinoConstant 65535. 2534*e4b17023SJohn Marino 2535*e4b17023SJohn Marino@item J 2536*e4b17023SJohn MarinoAn integer constant with exactly a single bit set. 2537*e4b17023SJohn Marino 2538*e4b17023SJohn Marino@item L 2539*e4b17023SJohn MarinoAn integer constant with all bits set except exactly one. 2540*e4b17023SJohn Marino 2541*e4b17023SJohn Marino@item H 2542*e4b17023SJohn Marino 2543*e4b17023SJohn Marino@item Q 2544*e4b17023SJohn MarinoAny SYMBOL_REF. 2545*e4b17023SJohn Marino@end table 2546*e4b17023SJohn Marino 2547*e4b17023SJohn Marino@item M32C---@file{config/m32c/m32c.c} 2548*e4b17023SJohn Marino@table @code 2549*e4b17023SJohn Marino@item Rsp 2550*e4b17023SJohn Marino@itemx Rfb 2551*e4b17023SJohn Marino@itemx Rsb 2552*e4b17023SJohn Marino@samp{$sp}, @samp{$fb}, @samp{$sb}. 2553*e4b17023SJohn Marino 2554*e4b17023SJohn Marino@item Rcr 2555*e4b17023SJohn MarinoAny control register, when they're 16 bits wide (nothing if control 2556*e4b17023SJohn Marinoregisters are 24 bits wide) 2557*e4b17023SJohn Marino 2558*e4b17023SJohn Marino@item Rcl 2559*e4b17023SJohn MarinoAny control register, when they're 24 bits wide. 2560*e4b17023SJohn Marino 2561*e4b17023SJohn Marino@item R0w 2562*e4b17023SJohn Marino@itemx R1w 2563*e4b17023SJohn Marino@itemx R2w 2564*e4b17023SJohn Marino@itemx R3w 2565*e4b17023SJohn Marino$r0, $r1, $r2, $r3. 2566*e4b17023SJohn Marino 2567*e4b17023SJohn Marino@item R02 2568*e4b17023SJohn Marino$r0 or $r2, or $r2r0 for 32 bit values. 2569*e4b17023SJohn Marino 2570*e4b17023SJohn Marino@item R13 2571*e4b17023SJohn Marino$r1 or $r3, or $r3r1 for 32 bit values. 2572*e4b17023SJohn Marino 2573*e4b17023SJohn Marino@item Rdi 2574*e4b17023SJohn MarinoA register that can hold a 64 bit value. 2575*e4b17023SJohn Marino 2576*e4b17023SJohn Marino@item Rhl 2577*e4b17023SJohn Marino$r0 or $r1 (registers with addressable high/low bytes) 2578*e4b17023SJohn Marino 2579*e4b17023SJohn Marino@item R23 2580*e4b17023SJohn Marino$r2 or $r3 2581*e4b17023SJohn Marino 2582*e4b17023SJohn Marino@item Raa 2583*e4b17023SJohn MarinoAddress registers 2584*e4b17023SJohn Marino 2585*e4b17023SJohn Marino@item Raw 2586*e4b17023SJohn MarinoAddress registers when they're 16 bits wide. 2587*e4b17023SJohn Marino 2588*e4b17023SJohn Marino@item Ral 2589*e4b17023SJohn MarinoAddress registers when they're 24 bits wide. 2590*e4b17023SJohn Marino 2591*e4b17023SJohn Marino@item Rqi 2592*e4b17023SJohn MarinoRegisters that can hold QI values. 2593*e4b17023SJohn Marino 2594*e4b17023SJohn Marino@item Rad 2595*e4b17023SJohn MarinoRegisters that can be used with displacements ($a0, $a1, $sb). 2596*e4b17023SJohn Marino 2597*e4b17023SJohn Marino@item Rsi 2598*e4b17023SJohn MarinoRegisters that can hold 32 bit values. 2599*e4b17023SJohn Marino 2600*e4b17023SJohn Marino@item Rhi 2601*e4b17023SJohn MarinoRegisters that can hold 16 bit values. 2602*e4b17023SJohn Marino 2603*e4b17023SJohn Marino@item Rhc 2604*e4b17023SJohn MarinoRegisters chat can hold 16 bit values, including all control 2605*e4b17023SJohn Marinoregisters. 2606*e4b17023SJohn Marino 2607*e4b17023SJohn Marino@item Rra 2608*e4b17023SJohn Marino$r0 through R1, plus $a0 and $a1. 2609*e4b17023SJohn Marino 2610*e4b17023SJohn Marino@item Rfl 2611*e4b17023SJohn MarinoThe flags register. 2612*e4b17023SJohn Marino 2613*e4b17023SJohn Marino@item Rmm 2614*e4b17023SJohn MarinoThe memory-based pseudo-registers $mem0 through $mem15. 2615*e4b17023SJohn Marino 2616*e4b17023SJohn Marino@item Rpi 2617*e4b17023SJohn MarinoRegisters that can hold pointers (16 bit registers for r8c, m16c; 24 2618*e4b17023SJohn Marinobit registers for m32cm, m32c). 2619*e4b17023SJohn Marino 2620*e4b17023SJohn Marino@item Rpa 2621*e4b17023SJohn MarinoMatches multiple registers in a PARALLEL to form a larger register. 2622*e4b17023SJohn MarinoUsed to match function return values. 2623*e4b17023SJohn Marino 2624*e4b17023SJohn Marino@item Is3 2625*e4b17023SJohn Marino@minus{}8 @dots{} 7 2626*e4b17023SJohn Marino 2627*e4b17023SJohn Marino@item IS1 2628*e4b17023SJohn Marino@minus{}128 @dots{} 127 2629*e4b17023SJohn Marino 2630*e4b17023SJohn Marino@item IS2 2631*e4b17023SJohn Marino@minus{}32768 @dots{} 32767 2632*e4b17023SJohn Marino 2633*e4b17023SJohn Marino@item IU2 2634*e4b17023SJohn Marino0 @dots{} 65535 2635*e4b17023SJohn Marino 2636*e4b17023SJohn Marino@item In4 2637*e4b17023SJohn Marino@minus{}8 @dots{} @minus{}1 or 1 @dots{} 8 2638*e4b17023SJohn Marino 2639*e4b17023SJohn Marino@item In5 2640*e4b17023SJohn Marino@minus{}16 @dots{} @minus{}1 or 1 @dots{} 16 2641*e4b17023SJohn Marino 2642*e4b17023SJohn Marino@item In6 2643*e4b17023SJohn Marino@minus{}32 @dots{} @minus{}1 or 1 @dots{} 32 2644*e4b17023SJohn Marino 2645*e4b17023SJohn Marino@item IM2 2646*e4b17023SJohn Marino@minus{}65536 @dots{} @minus{}1 2647*e4b17023SJohn Marino 2648*e4b17023SJohn Marino@item Ilb 2649*e4b17023SJohn MarinoAn 8 bit value with exactly one bit set. 2650*e4b17023SJohn Marino 2651*e4b17023SJohn Marino@item Ilw 2652*e4b17023SJohn MarinoA 16 bit value with exactly one bit set. 2653*e4b17023SJohn Marino 2654*e4b17023SJohn Marino@item Sd 2655*e4b17023SJohn MarinoThe common src/dest memory addressing modes. 2656*e4b17023SJohn Marino 2657*e4b17023SJohn Marino@item Sa 2658*e4b17023SJohn MarinoMemory addressed using $a0 or $a1. 2659*e4b17023SJohn Marino 2660*e4b17023SJohn Marino@item Si 2661*e4b17023SJohn MarinoMemory addressed with immediate addresses. 2662*e4b17023SJohn Marino 2663*e4b17023SJohn Marino@item Ss 2664*e4b17023SJohn MarinoMemory addressed using the stack pointer ($sp). 2665*e4b17023SJohn Marino 2666*e4b17023SJohn Marino@item Sf 2667*e4b17023SJohn MarinoMemory addressed using the frame base register ($fb). 2668*e4b17023SJohn Marino 2669*e4b17023SJohn Marino@item Ss 2670*e4b17023SJohn MarinoMemory addressed using the small base register ($sb). 2671*e4b17023SJohn Marino 2672*e4b17023SJohn Marino@item S1 2673*e4b17023SJohn Marino$r1h 2674*e4b17023SJohn Marino@end table 2675*e4b17023SJohn Marino 2676*e4b17023SJohn Marino@item MeP---@file{config/mep/constraints.md} 2677*e4b17023SJohn Marino@table @code 2678*e4b17023SJohn Marino 2679*e4b17023SJohn Marino@item a 2680*e4b17023SJohn MarinoThe $sp register. 2681*e4b17023SJohn Marino 2682*e4b17023SJohn Marino@item b 2683*e4b17023SJohn MarinoThe $tp register. 2684*e4b17023SJohn Marino 2685*e4b17023SJohn Marino@item c 2686*e4b17023SJohn MarinoAny control register. 2687*e4b17023SJohn Marino 2688*e4b17023SJohn Marino@item d 2689*e4b17023SJohn MarinoEither the $hi or the $lo register. 2690*e4b17023SJohn Marino 2691*e4b17023SJohn Marino@item em 2692*e4b17023SJohn MarinoCoprocessor registers that can be directly loaded ($c0-$c15). 2693*e4b17023SJohn Marino 2694*e4b17023SJohn Marino@item ex 2695*e4b17023SJohn MarinoCoprocessor registers that can be moved to each other. 2696*e4b17023SJohn Marino 2697*e4b17023SJohn Marino@item er 2698*e4b17023SJohn MarinoCoprocessor registers that can be moved to core registers. 2699*e4b17023SJohn Marino 2700*e4b17023SJohn Marino@item h 2701*e4b17023SJohn MarinoThe $hi register. 2702*e4b17023SJohn Marino 2703*e4b17023SJohn Marino@item j 2704*e4b17023SJohn MarinoThe $rpc register. 2705*e4b17023SJohn Marino 2706*e4b17023SJohn Marino@item l 2707*e4b17023SJohn MarinoThe $lo register. 2708*e4b17023SJohn Marino 2709*e4b17023SJohn Marino@item t 2710*e4b17023SJohn MarinoRegisters which can be used in $tp-relative addressing. 2711*e4b17023SJohn Marino 2712*e4b17023SJohn Marino@item v 2713*e4b17023SJohn MarinoThe $gp register. 2714*e4b17023SJohn Marino 2715*e4b17023SJohn Marino@item x 2716*e4b17023SJohn MarinoThe coprocessor registers. 2717*e4b17023SJohn Marino 2718*e4b17023SJohn Marino@item y 2719*e4b17023SJohn MarinoThe coprocessor control registers. 2720*e4b17023SJohn Marino 2721*e4b17023SJohn Marino@item z 2722*e4b17023SJohn MarinoThe $0 register. 2723*e4b17023SJohn Marino 2724*e4b17023SJohn Marino@item A 2725*e4b17023SJohn MarinoUser-defined register set A. 2726*e4b17023SJohn Marino 2727*e4b17023SJohn Marino@item B 2728*e4b17023SJohn MarinoUser-defined register set B. 2729*e4b17023SJohn Marino 2730*e4b17023SJohn Marino@item C 2731*e4b17023SJohn MarinoUser-defined register set C. 2732*e4b17023SJohn Marino 2733*e4b17023SJohn Marino@item D 2734*e4b17023SJohn MarinoUser-defined register set D. 2735*e4b17023SJohn Marino 2736*e4b17023SJohn Marino@item I 2737*e4b17023SJohn MarinoOffsets for $gp-rel addressing. 2738*e4b17023SJohn Marino 2739*e4b17023SJohn Marino@item J 2740*e4b17023SJohn MarinoConstants that can be used directly with boolean insns. 2741*e4b17023SJohn Marino 2742*e4b17023SJohn Marino@item K 2743*e4b17023SJohn MarinoConstants that can be moved directly to registers. 2744*e4b17023SJohn Marino 2745*e4b17023SJohn Marino@item L 2746*e4b17023SJohn MarinoSmall constants that can be added to registers. 2747*e4b17023SJohn Marino 2748*e4b17023SJohn Marino@item M 2749*e4b17023SJohn MarinoLong shift counts. 2750*e4b17023SJohn Marino 2751*e4b17023SJohn Marino@item N 2752*e4b17023SJohn MarinoSmall constants that can be compared to registers. 2753*e4b17023SJohn Marino 2754*e4b17023SJohn Marino@item O 2755*e4b17023SJohn MarinoConstants that can be loaded into the top half of registers. 2756*e4b17023SJohn Marino 2757*e4b17023SJohn Marino@item S 2758*e4b17023SJohn MarinoSigned 8-bit immediates. 2759*e4b17023SJohn Marino 2760*e4b17023SJohn Marino@item T 2761*e4b17023SJohn MarinoSymbols encoded for $tp-rel or $gp-rel addressing. 2762*e4b17023SJohn Marino 2763*e4b17023SJohn Marino@item U 2764*e4b17023SJohn MarinoNon-constant addresses for loading/saving coprocessor registers. 2765*e4b17023SJohn Marino 2766*e4b17023SJohn Marino@item W 2767*e4b17023SJohn MarinoThe top half of a symbol's value. 2768*e4b17023SJohn Marino 2769*e4b17023SJohn Marino@item Y 2770*e4b17023SJohn MarinoA register indirect address without offset. 2771*e4b17023SJohn Marino 2772*e4b17023SJohn Marino@item Z 2773*e4b17023SJohn MarinoSymbolic references to the control bus. 2774*e4b17023SJohn Marino 2775*e4b17023SJohn Marino@end table 2776*e4b17023SJohn Marino 2777*e4b17023SJohn Marino@item MicroBlaze---@file{config/microblaze/constraints.md} 2778*e4b17023SJohn Marino@table @code 2779*e4b17023SJohn Marino@item d 2780*e4b17023SJohn MarinoA general register (@code{r0} to @code{r31}). 2781*e4b17023SJohn Marino 2782*e4b17023SJohn Marino@item z 2783*e4b17023SJohn MarinoA status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}). 2784*e4b17023SJohn Marino 2785*e4b17023SJohn Marino@end table 2786*e4b17023SJohn Marino 2787*e4b17023SJohn Marino@item MIPS---@file{config/mips/constraints.md} 2788*e4b17023SJohn Marino@table @code 2789*e4b17023SJohn Marino@item d 2790*e4b17023SJohn MarinoAn address register. This is equivalent to @code{r} unless 2791*e4b17023SJohn Marinogenerating MIPS16 code. 2792*e4b17023SJohn Marino 2793*e4b17023SJohn Marino@item f 2794*e4b17023SJohn MarinoA floating-point register (if available). 2795*e4b17023SJohn Marino 2796*e4b17023SJohn Marino@item h 2797*e4b17023SJohn MarinoFormerly the @code{hi} register. This constraint is no longer supported. 2798*e4b17023SJohn Marino 2799*e4b17023SJohn Marino@item l 2800*e4b17023SJohn MarinoThe @code{lo} register. Use this register to store values that are 2801*e4b17023SJohn Marinono bigger than a word. 2802*e4b17023SJohn Marino 2803*e4b17023SJohn Marino@item x 2804*e4b17023SJohn MarinoThe concatenated @code{hi} and @code{lo} registers. Use this register 2805*e4b17023SJohn Marinoto store doubleword values. 2806*e4b17023SJohn Marino 2807*e4b17023SJohn Marino@item c 2808*e4b17023SJohn MarinoA register suitable for use in an indirect jump. This will always be 2809*e4b17023SJohn Marino@code{$25} for @option{-mabicalls}. 2810*e4b17023SJohn Marino 2811*e4b17023SJohn Marino@item v 2812*e4b17023SJohn MarinoRegister @code{$3}. Do not use this constraint in new code; 2813*e4b17023SJohn Marinoit is retained only for compatibility with glibc. 2814*e4b17023SJohn Marino 2815*e4b17023SJohn Marino@item y 2816*e4b17023SJohn MarinoEquivalent to @code{r}; retained for backwards compatibility. 2817*e4b17023SJohn Marino 2818*e4b17023SJohn Marino@item z 2819*e4b17023SJohn MarinoA floating-point condition code register. 2820*e4b17023SJohn Marino 2821*e4b17023SJohn Marino@item I 2822*e4b17023SJohn MarinoA signed 16-bit constant (for arithmetic instructions). 2823*e4b17023SJohn Marino 2824*e4b17023SJohn Marino@item J 2825*e4b17023SJohn MarinoInteger zero. 2826*e4b17023SJohn Marino 2827*e4b17023SJohn Marino@item K 2828*e4b17023SJohn MarinoAn unsigned 16-bit constant (for logic instructions). 2829*e4b17023SJohn Marino 2830*e4b17023SJohn Marino@item L 2831*e4b17023SJohn MarinoA signed 32-bit constant in which the lower 16 bits are zero. 2832*e4b17023SJohn MarinoSuch constants can be loaded using @code{lui}. 2833*e4b17023SJohn Marino 2834*e4b17023SJohn Marino@item M 2835*e4b17023SJohn MarinoA constant that cannot be loaded using @code{lui}, @code{addiu} 2836*e4b17023SJohn Marinoor @code{ori}. 2837*e4b17023SJohn Marino 2838*e4b17023SJohn Marino@item N 2839*e4b17023SJohn MarinoA constant in the range @minus{}65535 to @minus{}1 (inclusive). 2840*e4b17023SJohn Marino 2841*e4b17023SJohn Marino@item O 2842*e4b17023SJohn MarinoA signed 15-bit constant. 2843*e4b17023SJohn Marino 2844*e4b17023SJohn Marino@item P 2845*e4b17023SJohn MarinoA constant in the range 1 to 65535 (inclusive). 2846*e4b17023SJohn Marino 2847*e4b17023SJohn Marino@item G 2848*e4b17023SJohn MarinoFloating-point zero. 2849*e4b17023SJohn Marino 2850*e4b17023SJohn Marino@item R 2851*e4b17023SJohn MarinoAn address that can be used in a non-macro load or store. 2852*e4b17023SJohn Marino@end table 2853*e4b17023SJohn Marino 2854*e4b17023SJohn Marino@item Motorola 680x0---@file{config/m68k/constraints.md} 2855*e4b17023SJohn Marino@table @code 2856*e4b17023SJohn Marino@item a 2857*e4b17023SJohn MarinoAddress register 2858*e4b17023SJohn Marino 2859*e4b17023SJohn Marino@item d 2860*e4b17023SJohn MarinoData register 2861*e4b17023SJohn Marino 2862*e4b17023SJohn Marino@item f 2863*e4b17023SJohn Marino68881 floating-point register, if available 2864*e4b17023SJohn Marino 2865*e4b17023SJohn Marino@item I 2866*e4b17023SJohn MarinoInteger in the range 1 to 8 2867*e4b17023SJohn Marino 2868*e4b17023SJohn Marino@item J 2869*e4b17023SJohn Marino16-bit signed number 2870*e4b17023SJohn Marino 2871*e4b17023SJohn Marino@item K 2872*e4b17023SJohn MarinoSigned number whose magnitude is greater than 0x80 2873*e4b17023SJohn Marino 2874*e4b17023SJohn Marino@item L 2875*e4b17023SJohn MarinoInteger in the range @minus{}8 to @minus{}1 2876*e4b17023SJohn Marino 2877*e4b17023SJohn Marino@item M 2878*e4b17023SJohn MarinoSigned number whose magnitude is greater than 0x100 2879*e4b17023SJohn Marino 2880*e4b17023SJohn Marino@item N 2881*e4b17023SJohn MarinoRange 24 to 31, rotatert:SI 8 to 1 expressed as rotate 2882*e4b17023SJohn Marino 2883*e4b17023SJohn Marino@item O 2884*e4b17023SJohn Marino16 (for rotate using swap) 2885*e4b17023SJohn Marino 2886*e4b17023SJohn Marino@item P 2887*e4b17023SJohn MarinoRange 8 to 15, rotatert:HI 8 to 1 expressed as rotate 2888*e4b17023SJohn Marino 2889*e4b17023SJohn Marino@item R 2890*e4b17023SJohn MarinoNumbers that mov3q can handle 2891*e4b17023SJohn Marino 2892*e4b17023SJohn Marino@item G 2893*e4b17023SJohn MarinoFloating point constant that is not a 68881 constant 2894*e4b17023SJohn Marino 2895*e4b17023SJohn Marino@item S 2896*e4b17023SJohn MarinoOperands that satisfy 'm' when -mpcrel is in effect 2897*e4b17023SJohn Marino 2898*e4b17023SJohn Marino@item T 2899*e4b17023SJohn MarinoOperands that satisfy 's' when -mpcrel is not in effect 2900*e4b17023SJohn Marino 2901*e4b17023SJohn Marino@item Q 2902*e4b17023SJohn MarinoAddress register indirect addressing mode 2903*e4b17023SJohn Marino 2904*e4b17023SJohn Marino@item U 2905*e4b17023SJohn MarinoRegister offset addressing 2906*e4b17023SJohn Marino 2907*e4b17023SJohn Marino@item W 2908*e4b17023SJohn Marinoconst_call_operand 2909*e4b17023SJohn Marino 2910*e4b17023SJohn Marino@item Cs 2911*e4b17023SJohn Marinosymbol_ref or const 2912*e4b17023SJohn Marino 2913*e4b17023SJohn Marino@item Ci 2914*e4b17023SJohn Marinoconst_int 2915*e4b17023SJohn Marino 2916*e4b17023SJohn Marino@item C0 2917*e4b17023SJohn Marinoconst_int 0 2918*e4b17023SJohn Marino 2919*e4b17023SJohn Marino@item Cj 2920*e4b17023SJohn MarinoRange of signed numbers that don't fit in 16 bits 2921*e4b17023SJohn Marino 2922*e4b17023SJohn Marino@item Cmvq 2923*e4b17023SJohn MarinoIntegers valid for mvq 2924*e4b17023SJohn Marino 2925*e4b17023SJohn Marino@item Capsw 2926*e4b17023SJohn MarinoIntegers valid for a moveq followed by a swap 2927*e4b17023SJohn Marino 2928*e4b17023SJohn Marino@item Cmvz 2929*e4b17023SJohn MarinoIntegers valid for mvz 2930*e4b17023SJohn Marino 2931*e4b17023SJohn Marino@item Cmvs 2932*e4b17023SJohn MarinoIntegers valid for mvs 2933*e4b17023SJohn Marino 2934*e4b17023SJohn Marino@item Ap 2935*e4b17023SJohn Marinopush_operand 2936*e4b17023SJohn Marino 2937*e4b17023SJohn Marino@item Ac 2938*e4b17023SJohn MarinoNon-register operands allowed in clr 2939*e4b17023SJohn Marino 2940*e4b17023SJohn Marino@end table 2941*e4b17023SJohn Marino 2942*e4b17023SJohn Marino@item Moxie---@file{config/moxie/constraints.md} 2943*e4b17023SJohn Marino@table @code 2944*e4b17023SJohn Marino@item A 2945*e4b17023SJohn MarinoAn absolute address 2946*e4b17023SJohn Marino 2947*e4b17023SJohn Marino@item B 2948*e4b17023SJohn MarinoAn offset address 2949*e4b17023SJohn Marino 2950*e4b17023SJohn Marino@item W 2951*e4b17023SJohn MarinoA register indirect memory operand 2952*e4b17023SJohn Marino 2953*e4b17023SJohn Marino@item I 2954*e4b17023SJohn MarinoA constant in the range of 0 to 255. 2955*e4b17023SJohn Marino 2956*e4b17023SJohn Marino@item N 2957*e4b17023SJohn MarinoA constant in the range of 0 to @minus{}255. 2958*e4b17023SJohn Marino 2959*e4b17023SJohn Marino@end table 2960*e4b17023SJohn Marino 2961*e4b17023SJohn Marino@item PDP-11---@file{config/pdp11/constraints.md} 2962*e4b17023SJohn Marino@table @code 2963*e4b17023SJohn Marino@item a 2964*e4b17023SJohn MarinoFloating point registers AC0 through AC3. These can be loaded from/to 2965*e4b17023SJohn Marinomemory with a single instruction. 2966*e4b17023SJohn Marino 2967*e4b17023SJohn Marino@item d 2968*e4b17023SJohn MarinoOdd numbered general registers (R1, R3, R5). These are used for 2969*e4b17023SJohn Marino16-bit multiply operations. 2970*e4b17023SJohn Marino 2971*e4b17023SJohn Marino@item f 2972*e4b17023SJohn MarinoAny of the floating point registers (AC0 through AC5). 2973*e4b17023SJohn Marino 2974*e4b17023SJohn Marino@item G 2975*e4b17023SJohn MarinoFloating point constant 0. 2976*e4b17023SJohn Marino 2977*e4b17023SJohn Marino@item I 2978*e4b17023SJohn MarinoAn integer constant that fits in 16 bits. 2979*e4b17023SJohn Marino 2980*e4b17023SJohn Marino@item J 2981*e4b17023SJohn MarinoAn integer constant whose low order 16 bits are zero. 2982*e4b17023SJohn Marino 2983*e4b17023SJohn Marino@item K 2984*e4b17023SJohn MarinoAn integer constant that does not meet the constraints for codes 2985*e4b17023SJohn Marino@samp{I} or @samp{J}. 2986*e4b17023SJohn Marino 2987*e4b17023SJohn Marino@item L 2988*e4b17023SJohn MarinoThe integer constant 1. 2989*e4b17023SJohn Marino 2990*e4b17023SJohn Marino@item M 2991*e4b17023SJohn MarinoThe integer constant @minus{}1. 2992*e4b17023SJohn Marino 2993*e4b17023SJohn Marino@item N 2994*e4b17023SJohn MarinoThe integer constant 0. 2995*e4b17023SJohn Marino 2996*e4b17023SJohn Marino@item O 2997*e4b17023SJohn MarinoInteger constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these 2998*e4b17023SJohn Marinoamounts are handled as multiple single-bit shifts rather than a single 2999*e4b17023SJohn Marinovariable-length shift. 3000*e4b17023SJohn Marino 3001*e4b17023SJohn Marino@item Q 3002*e4b17023SJohn MarinoA memory reference which requires an additional word (address or 3003*e4b17023SJohn Marinooffset) after the opcode. 3004*e4b17023SJohn Marino 3005*e4b17023SJohn Marino@item R 3006*e4b17023SJohn MarinoA memory reference that is encoded within the opcode. 3007*e4b17023SJohn Marino 3008*e4b17023SJohn Marino@end table 3009*e4b17023SJohn Marino 3010*e4b17023SJohn Marino@item RL78---@file{config/rl78/constraints.md} 3011*e4b17023SJohn Marino@table @code 3012*e4b17023SJohn Marino 3013*e4b17023SJohn Marino@item Int3 3014*e4b17023SJohn MarinoAn integer constant in the range 1 @dots{} 7. 3015*e4b17023SJohn Marino@item Int8 3016*e4b17023SJohn MarinoAn integer constant in the range 0 @dots{} 255. 3017*e4b17023SJohn Marino@item J 3018*e4b17023SJohn MarinoAn integer constant in the range @minus{}255 @dots{} 0 3019*e4b17023SJohn Marino@item K 3020*e4b17023SJohn MarinoThe integer constant 1. 3021*e4b17023SJohn Marino@item L 3022*e4b17023SJohn MarinoThe integer constant -1. 3023*e4b17023SJohn Marino@item M 3024*e4b17023SJohn MarinoThe integer constant 0. 3025*e4b17023SJohn Marino@item N 3026*e4b17023SJohn MarinoThe integer constant 2. 3027*e4b17023SJohn Marino@item O 3028*e4b17023SJohn MarinoThe integer constant -2. 3029*e4b17023SJohn Marino@item P 3030*e4b17023SJohn MarinoAn integer constant in the range 1 @dots{} 15. 3031*e4b17023SJohn Marino@item Qbi 3032*e4b17023SJohn MarinoThe built-in compare types--eq, ne, gtu, ltu, geu, and leu. 3033*e4b17023SJohn Marino@item Qsc 3034*e4b17023SJohn MarinoThe synthetic compare types--gt, lt, ge, and le. 3035*e4b17023SJohn Marino@item Wab 3036*e4b17023SJohn MarinoA memory reference with an absolute address. 3037*e4b17023SJohn Marino@item Wbc 3038*e4b17023SJohn MarinoA memory reference using @code{BC} as a base register, with an optional offset. 3039*e4b17023SJohn Marino@item Wca 3040*e4b17023SJohn MarinoA memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls. 3041*e4b17023SJohn Marino@item Wcv 3042*e4b17023SJohn MarinoA memory reference using any 16-bit register pair for the address, for calls. 3043*e4b17023SJohn Marino@item Wd2 3044*e4b17023SJohn MarinoA memory reference using @code{DE} as a base register, with an optional offset. 3045*e4b17023SJohn Marino@item Wde 3046*e4b17023SJohn MarinoA memory reference using @code{DE} as a base register, without any offset. 3047*e4b17023SJohn Marino@item Wfr 3048*e4b17023SJohn MarinoAny memory reference to an address in the far address space. 3049*e4b17023SJohn Marino@item Wh1 3050*e4b17023SJohn MarinoA memory reference using @code{HL} as a base register, with an optional one-byte offset. 3051*e4b17023SJohn Marino@item Whb 3052*e4b17023SJohn MarinoA memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register. 3053*e4b17023SJohn Marino@item Whl 3054*e4b17023SJohn MarinoA memory reference using @code{HL} as a base register, without any offset. 3055*e4b17023SJohn Marino@item Ws1 3056*e4b17023SJohn MarinoA memory reference using @code{SP} as a base register, with an optional one-byte offset. 3057*e4b17023SJohn Marino@item Y 3058*e4b17023SJohn MarinoAny memory reference to an address in the near address space. 3059*e4b17023SJohn Marino@item A 3060*e4b17023SJohn MarinoThe @code{AX} register. 3061*e4b17023SJohn Marino@item B 3062*e4b17023SJohn MarinoThe @code{BC} register. 3063*e4b17023SJohn Marino@item D 3064*e4b17023SJohn MarinoThe @code{DE} register. 3065*e4b17023SJohn Marino@item R 3066*e4b17023SJohn Marino@code{A} through @code{L} registers. 3067*e4b17023SJohn Marino@item S 3068*e4b17023SJohn MarinoThe @code{SP} register. 3069*e4b17023SJohn Marino@item T 3070*e4b17023SJohn MarinoThe @code{HL} register. 3071*e4b17023SJohn Marino@item Z08W 3072*e4b17023SJohn MarinoThe 16-bit @code{R8} register. 3073*e4b17023SJohn Marino@item Z10W 3074*e4b17023SJohn MarinoThe 16-bit @code{R10} register. 3075*e4b17023SJohn Marino@item Zint 3076*e4b17023SJohn MarinoThe registers reserved for interrupts (@code{R24} to @code{R31}). 3077*e4b17023SJohn Marino@item a 3078*e4b17023SJohn MarinoThe @code{A} register. 3079*e4b17023SJohn Marino@item b 3080*e4b17023SJohn MarinoThe @code{B} register. 3081*e4b17023SJohn Marino@item c 3082*e4b17023SJohn MarinoThe @code{C} register. 3083*e4b17023SJohn Marino@item d 3084*e4b17023SJohn MarinoThe @code{D} register. 3085*e4b17023SJohn Marino@item e 3086*e4b17023SJohn MarinoThe @code{E} register. 3087*e4b17023SJohn Marino@item h 3088*e4b17023SJohn MarinoThe @code{H} register. 3089*e4b17023SJohn Marino@item l 3090*e4b17023SJohn MarinoThe @code{L} register. 3091*e4b17023SJohn Marino@item v 3092*e4b17023SJohn MarinoThe virtual registers. 3093*e4b17023SJohn Marino@item w 3094*e4b17023SJohn MarinoThe @code{PSW} register. 3095*e4b17023SJohn Marino@item x 3096*e4b17023SJohn MarinoThe @code{X} register. 3097*e4b17023SJohn Marino 3098*e4b17023SJohn Marino@end table 3099*e4b17023SJohn Marino 3100*e4b17023SJohn Marino@item RX---@file{config/rx/constraints.md} 3101*e4b17023SJohn Marino@table @code 3102*e4b17023SJohn Marino@item Q 3103*e4b17023SJohn MarinoAn address which does not involve register indirect addressing or 3104*e4b17023SJohn Marinopre/post increment/decrement addressing. 3105*e4b17023SJohn Marino 3106*e4b17023SJohn Marino@item Symbol 3107*e4b17023SJohn MarinoA symbol reference. 3108*e4b17023SJohn Marino 3109*e4b17023SJohn Marino@item Int08 3110*e4b17023SJohn MarinoA constant in the range @minus{}256 to 255, inclusive. 3111*e4b17023SJohn Marino 3112*e4b17023SJohn Marino@item Sint08 3113*e4b17023SJohn MarinoA constant in the range @minus{}128 to 127, inclusive. 3114*e4b17023SJohn Marino 3115*e4b17023SJohn Marino@item Sint16 3116*e4b17023SJohn MarinoA constant in the range @minus{}32768 to 32767, inclusive. 3117*e4b17023SJohn Marino 3118*e4b17023SJohn Marino@item Sint24 3119*e4b17023SJohn MarinoA constant in the range @minus{}8388608 to 8388607, inclusive. 3120*e4b17023SJohn Marino 3121*e4b17023SJohn Marino@item Uint04 3122*e4b17023SJohn MarinoA constant in the range 0 to 15, inclusive. 3123*e4b17023SJohn Marino 3124*e4b17023SJohn Marino@end table 3125*e4b17023SJohn Marino 3126*e4b17023SJohn Marino@need 1000 3127*e4b17023SJohn Marino@item SPARC---@file{config/sparc/sparc.h} 3128*e4b17023SJohn Marino@table @code 3129*e4b17023SJohn Marino@item f 3130*e4b17023SJohn MarinoFloating-point register on the SPARC-V8 architecture and 3131*e4b17023SJohn Marinolower floating-point register on the SPARC-V9 architecture. 3132*e4b17023SJohn Marino 3133*e4b17023SJohn Marino@item e 3134*e4b17023SJohn MarinoFloating-point register. It is equivalent to @samp{f} on the 3135*e4b17023SJohn MarinoSPARC-V8 architecture and contains both lower and upper 3136*e4b17023SJohn Marinofloating-point registers on the SPARC-V9 architecture. 3137*e4b17023SJohn Marino 3138*e4b17023SJohn Marino@item c 3139*e4b17023SJohn MarinoFloating-point condition code register. 3140*e4b17023SJohn Marino 3141*e4b17023SJohn Marino@item d 3142*e4b17023SJohn MarinoLower floating-point register. It is only valid on the SPARC-V9 3143*e4b17023SJohn Marinoarchitecture when the Visual Instruction Set is available. 3144*e4b17023SJohn Marino 3145*e4b17023SJohn Marino@item b 3146*e4b17023SJohn MarinoFloating-point register. It is only valid on the SPARC-V9 architecture 3147*e4b17023SJohn Marinowhen the Visual Instruction Set is available. 3148*e4b17023SJohn Marino 3149*e4b17023SJohn Marino@item h 3150*e4b17023SJohn Marino64-bit global or out register for the SPARC-V8+ architecture. 3151*e4b17023SJohn Marino 3152*e4b17023SJohn Marino@item D 3153*e4b17023SJohn MarinoA vector constant 3154*e4b17023SJohn Marino 3155*e4b17023SJohn Marino@item I 3156*e4b17023SJohn MarinoSigned 13-bit constant 3157*e4b17023SJohn Marino 3158*e4b17023SJohn Marino@item J 3159*e4b17023SJohn MarinoZero 3160*e4b17023SJohn Marino 3161*e4b17023SJohn Marino@item K 3162*e4b17023SJohn Marino32-bit constant with the low 12 bits clear (a constant that can be 3163*e4b17023SJohn Marinoloaded with the @code{sethi} instruction) 3164*e4b17023SJohn Marino 3165*e4b17023SJohn Marino@item L 3166*e4b17023SJohn MarinoA constant in the range supported by @code{movcc} instructions 3167*e4b17023SJohn Marino 3168*e4b17023SJohn Marino@item M 3169*e4b17023SJohn MarinoA constant in the range supported by @code{movrcc} instructions 3170*e4b17023SJohn Marino 3171*e4b17023SJohn Marino@item N 3172*e4b17023SJohn MarinoSame as @samp{K}, except that it verifies that bits that are not in the 3173*e4b17023SJohn Marinolower 32-bit range are all zero. Must be used instead of @samp{K} for 3174*e4b17023SJohn Marinomodes wider than @code{SImode} 3175*e4b17023SJohn Marino 3176*e4b17023SJohn Marino@item O 3177*e4b17023SJohn MarinoThe constant 4096 3178*e4b17023SJohn Marino 3179*e4b17023SJohn Marino@item G 3180*e4b17023SJohn MarinoFloating-point zero 3181*e4b17023SJohn Marino 3182*e4b17023SJohn Marino@item H 3183*e4b17023SJohn MarinoSigned 13-bit constant, sign-extended to 32 or 64 bits 3184*e4b17023SJohn Marino 3185*e4b17023SJohn Marino@item Q 3186*e4b17023SJohn MarinoFloating-point constant whose integral representation can 3187*e4b17023SJohn Marinobe moved into an integer register using a single sethi 3188*e4b17023SJohn Marinoinstruction 3189*e4b17023SJohn Marino 3190*e4b17023SJohn Marino@item R 3191*e4b17023SJohn MarinoFloating-point constant whose integral representation can 3192*e4b17023SJohn Marinobe moved into an integer register using a single mov 3193*e4b17023SJohn Marinoinstruction 3194*e4b17023SJohn Marino 3195*e4b17023SJohn Marino@item S 3196*e4b17023SJohn MarinoFloating-point constant whose integral representation can 3197*e4b17023SJohn Marinobe moved into an integer register using a high/lo_sum 3198*e4b17023SJohn Marinoinstruction sequence 3199*e4b17023SJohn Marino 3200*e4b17023SJohn Marino@item T 3201*e4b17023SJohn MarinoMemory address aligned to an 8-byte boundary 3202*e4b17023SJohn Marino 3203*e4b17023SJohn Marino@item U 3204*e4b17023SJohn MarinoEven register 3205*e4b17023SJohn Marino 3206*e4b17023SJohn Marino@item W 3207*e4b17023SJohn MarinoMemory address for @samp{e} constraint registers 3208*e4b17023SJohn Marino 3209*e4b17023SJohn Marino@item Y 3210*e4b17023SJohn MarinoVector zero 3211*e4b17023SJohn Marino 3212*e4b17023SJohn Marino@end table 3213*e4b17023SJohn Marino 3214*e4b17023SJohn Marino@item SPU---@file{config/spu/spu.h} 3215*e4b17023SJohn Marino@table @code 3216*e4b17023SJohn Marino@item a 3217*e4b17023SJohn MarinoAn immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value. 3218*e4b17023SJohn Marino 3219*e4b17023SJohn Marino@item c 3220*e4b17023SJohn MarinoAn immediate for and/xor/or instructions. const_int is treated as a 64 bit value. 3221*e4b17023SJohn Marino 3222*e4b17023SJohn Marino@item d 3223*e4b17023SJohn MarinoAn immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value. 3224*e4b17023SJohn Marino 3225*e4b17023SJohn Marino@item f 3226*e4b17023SJohn MarinoAn immediate which can be loaded with @code{fsmbi}. 3227*e4b17023SJohn Marino 3228*e4b17023SJohn Marino@item A 3229*e4b17023SJohn MarinoAn immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value. 3230*e4b17023SJohn Marino 3231*e4b17023SJohn Marino@item B 3232*e4b17023SJohn MarinoAn immediate for most arithmetic instructions. const_int is treated as a 32 bit value. 3233*e4b17023SJohn Marino 3234*e4b17023SJohn Marino@item C 3235*e4b17023SJohn MarinoAn immediate for and/xor/or instructions. const_int is treated as a 32 bit value. 3236*e4b17023SJohn Marino 3237*e4b17023SJohn Marino@item D 3238*e4b17023SJohn MarinoAn immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value. 3239*e4b17023SJohn Marino 3240*e4b17023SJohn Marino@item I 3241*e4b17023SJohn MarinoA constant in the range [@minus{}64, 63] for shift/rotate instructions. 3242*e4b17023SJohn Marino 3243*e4b17023SJohn Marino@item J 3244*e4b17023SJohn MarinoAn unsigned 7-bit constant for conversion/nop/channel instructions. 3245*e4b17023SJohn Marino 3246*e4b17023SJohn Marino@item K 3247*e4b17023SJohn MarinoA signed 10-bit constant for most arithmetic instructions. 3248*e4b17023SJohn Marino 3249*e4b17023SJohn Marino@item M 3250*e4b17023SJohn MarinoA signed 16 bit immediate for @code{stop}. 3251*e4b17023SJohn Marino 3252*e4b17023SJohn Marino@item N 3253*e4b17023SJohn MarinoAn unsigned 16-bit constant for @code{iohl} and @code{fsmbi}. 3254*e4b17023SJohn Marino 3255*e4b17023SJohn Marino@item O 3256*e4b17023SJohn MarinoAn unsigned 7-bit constant whose 3 least significant bits are 0. 3257*e4b17023SJohn Marino 3258*e4b17023SJohn Marino@item P 3259*e4b17023SJohn MarinoAn unsigned 3-bit constant for 16-byte rotates and shifts 3260*e4b17023SJohn Marino 3261*e4b17023SJohn Marino@item R 3262*e4b17023SJohn MarinoCall operand, reg, for indirect calls 3263*e4b17023SJohn Marino 3264*e4b17023SJohn Marino@item S 3265*e4b17023SJohn MarinoCall operand, symbol, for relative calls. 3266*e4b17023SJohn Marino 3267*e4b17023SJohn Marino@item T 3268*e4b17023SJohn MarinoCall operand, const_int, for absolute calls. 3269*e4b17023SJohn Marino 3270*e4b17023SJohn Marino@item U 3271*e4b17023SJohn MarinoAn immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit. 3272*e4b17023SJohn Marino 3273*e4b17023SJohn Marino@item W 3274*e4b17023SJohn MarinoAn immediate for shift and rotate instructions. const_int is treated as a 32 bit value. 3275*e4b17023SJohn Marino 3276*e4b17023SJohn Marino@item Y 3277*e4b17023SJohn MarinoAn immediate for and/xor/or instructions. const_int is sign extended as a 128 bit. 3278*e4b17023SJohn Marino 3279*e4b17023SJohn Marino@item Z 3280*e4b17023SJohn MarinoAn immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit. 3281*e4b17023SJohn Marino 3282*e4b17023SJohn Marino@end table 3283*e4b17023SJohn Marino 3284*e4b17023SJohn Marino@item S/390 and zSeries---@file{config/s390/s390.h} 3285*e4b17023SJohn Marino@table @code 3286*e4b17023SJohn Marino@item a 3287*e4b17023SJohn MarinoAddress register (general purpose register except r0) 3288*e4b17023SJohn Marino 3289*e4b17023SJohn Marino@item c 3290*e4b17023SJohn MarinoCondition code register 3291*e4b17023SJohn Marino 3292*e4b17023SJohn Marino@item d 3293*e4b17023SJohn MarinoData register (arbitrary general purpose register) 3294*e4b17023SJohn Marino 3295*e4b17023SJohn Marino@item f 3296*e4b17023SJohn MarinoFloating-point register 3297*e4b17023SJohn Marino 3298*e4b17023SJohn Marino@item I 3299*e4b17023SJohn MarinoUnsigned 8-bit constant (0--255) 3300*e4b17023SJohn Marino 3301*e4b17023SJohn Marino@item J 3302*e4b17023SJohn MarinoUnsigned 12-bit constant (0--4095) 3303*e4b17023SJohn Marino 3304*e4b17023SJohn Marino@item K 3305*e4b17023SJohn MarinoSigned 16-bit constant (@minus{}32768--32767) 3306*e4b17023SJohn Marino 3307*e4b17023SJohn Marino@item L 3308*e4b17023SJohn MarinoValue appropriate as displacement. 3309*e4b17023SJohn Marino@table @code 3310*e4b17023SJohn Marino@item (0..4095) 3311*e4b17023SJohn Marinofor short displacement 3312*e4b17023SJohn Marino@item (@minus{}524288..524287) 3313*e4b17023SJohn Marinofor long displacement 3314*e4b17023SJohn Marino@end table 3315*e4b17023SJohn Marino 3316*e4b17023SJohn Marino@item M 3317*e4b17023SJohn MarinoConstant integer with a value of 0x7fffffff. 3318*e4b17023SJohn Marino 3319*e4b17023SJohn Marino@item N 3320*e4b17023SJohn MarinoMultiple letter constraint followed by 4 parameter letters. 3321*e4b17023SJohn Marino@table @code 3322*e4b17023SJohn Marino@item 0..9: 3323*e4b17023SJohn Marinonumber of the part counting from most to least significant 3324*e4b17023SJohn Marino@item H,Q: 3325*e4b17023SJohn Marinomode of the part 3326*e4b17023SJohn Marino@item D,S,H: 3327*e4b17023SJohn Marinomode of the containing operand 3328*e4b17023SJohn Marino@item 0,F: 3329*e4b17023SJohn Marinovalue of the other parts (F---all bits set) 3330*e4b17023SJohn Marino@end table 3331*e4b17023SJohn MarinoThe constraint matches if the specified part of a constant 3332*e4b17023SJohn Marinohas a value different from its other parts. 3333*e4b17023SJohn Marino 3334*e4b17023SJohn Marino@item Q 3335*e4b17023SJohn MarinoMemory reference without index register and with short displacement. 3336*e4b17023SJohn Marino 3337*e4b17023SJohn Marino@item R 3338*e4b17023SJohn MarinoMemory reference with index register and short displacement. 3339*e4b17023SJohn Marino 3340*e4b17023SJohn Marino@item S 3341*e4b17023SJohn MarinoMemory reference without index register but with long displacement. 3342*e4b17023SJohn Marino 3343*e4b17023SJohn Marino@item T 3344*e4b17023SJohn MarinoMemory reference with index register and long displacement. 3345*e4b17023SJohn Marino 3346*e4b17023SJohn Marino@item U 3347*e4b17023SJohn MarinoPointer with short displacement. 3348*e4b17023SJohn Marino 3349*e4b17023SJohn Marino@item W 3350*e4b17023SJohn MarinoPointer with long displacement. 3351*e4b17023SJohn Marino 3352*e4b17023SJohn Marino@item Y 3353*e4b17023SJohn MarinoShift count operand. 3354*e4b17023SJohn Marino 3355*e4b17023SJohn Marino@end table 3356*e4b17023SJohn Marino 3357*e4b17023SJohn Marino@item Score family---@file{config/score/score.h} 3358*e4b17023SJohn Marino@table @code 3359*e4b17023SJohn Marino@item d 3360*e4b17023SJohn MarinoRegisters from r0 to r32. 3361*e4b17023SJohn Marino 3362*e4b17023SJohn Marino@item e 3363*e4b17023SJohn MarinoRegisters from r0 to r16. 3364*e4b17023SJohn Marino 3365*e4b17023SJohn Marino@item t 3366*e4b17023SJohn Marinor8---r11 or r22---r27 registers. 3367*e4b17023SJohn Marino 3368*e4b17023SJohn Marino@item h 3369*e4b17023SJohn Marinohi register. 3370*e4b17023SJohn Marino 3371*e4b17023SJohn Marino@item l 3372*e4b17023SJohn Marinolo register. 3373*e4b17023SJohn Marino 3374*e4b17023SJohn Marino@item x 3375*e4b17023SJohn Marinohi + lo register. 3376*e4b17023SJohn Marino 3377*e4b17023SJohn Marino@item q 3378*e4b17023SJohn Marinocnt register. 3379*e4b17023SJohn Marino 3380*e4b17023SJohn Marino@item y 3381*e4b17023SJohn Marinolcb register. 3382*e4b17023SJohn Marino 3383*e4b17023SJohn Marino@item z 3384*e4b17023SJohn Marinoscb register. 3385*e4b17023SJohn Marino 3386*e4b17023SJohn Marino@item a 3387*e4b17023SJohn Marinocnt + lcb + scb register. 3388*e4b17023SJohn Marino 3389*e4b17023SJohn Marino@item c 3390*e4b17023SJohn Marinocr0---cr15 register. 3391*e4b17023SJohn Marino 3392*e4b17023SJohn Marino@item b 3393*e4b17023SJohn Marinocp1 registers. 3394*e4b17023SJohn Marino 3395*e4b17023SJohn Marino@item f 3396*e4b17023SJohn Marinocp2 registers. 3397*e4b17023SJohn Marino 3398*e4b17023SJohn Marino@item i 3399*e4b17023SJohn Marinocp3 registers. 3400*e4b17023SJohn Marino 3401*e4b17023SJohn Marino@item j 3402*e4b17023SJohn Marinocp1 + cp2 + cp3 registers. 3403*e4b17023SJohn Marino 3404*e4b17023SJohn Marino@item I 3405*e4b17023SJohn MarinoHigh 16-bit constant (32-bit constant with 16 LSBs zero). 3406*e4b17023SJohn Marino 3407*e4b17023SJohn Marino@item J 3408*e4b17023SJohn MarinoUnsigned 5 bit integer (in the range 0 to 31). 3409*e4b17023SJohn Marino 3410*e4b17023SJohn Marino@item K 3411*e4b17023SJohn MarinoUnsigned 16 bit integer (in the range 0 to 65535). 3412*e4b17023SJohn Marino 3413*e4b17023SJohn Marino@item L 3414*e4b17023SJohn MarinoSigned 16 bit integer (in the range @minus{}32768 to 32767). 3415*e4b17023SJohn Marino 3416*e4b17023SJohn Marino@item M 3417*e4b17023SJohn MarinoUnsigned 14 bit integer (in the range 0 to 16383). 3418*e4b17023SJohn Marino 3419*e4b17023SJohn Marino@item N 3420*e4b17023SJohn MarinoSigned 14 bit integer (in the range @minus{}8192 to 8191). 3421*e4b17023SJohn Marino 3422*e4b17023SJohn Marino@item Z 3423*e4b17023SJohn MarinoAny SYMBOL_REF. 3424*e4b17023SJohn Marino@end table 3425*e4b17023SJohn Marino 3426*e4b17023SJohn Marino@item Xstormy16---@file{config/stormy16/stormy16.h} 3427*e4b17023SJohn Marino@table @code 3428*e4b17023SJohn Marino@item a 3429*e4b17023SJohn MarinoRegister r0. 3430*e4b17023SJohn Marino 3431*e4b17023SJohn Marino@item b 3432*e4b17023SJohn MarinoRegister r1. 3433*e4b17023SJohn Marino 3434*e4b17023SJohn Marino@item c 3435*e4b17023SJohn MarinoRegister r2. 3436*e4b17023SJohn Marino 3437*e4b17023SJohn Marino@item d 3438*e4b17023SJohn MarinoRegister r8. 3439*e4b17023SJohn Marino 3440*e4b17023SJohn Marino@item e 3441*e4b17023SJohn MarinoRegisters r0 through r7. 3442*e4b17023SJohn Marino 3443*e4b17023SJohn Marino@item t 3444*e4b17023SJohn MarinoRegisters r0 and r1. 3445*e4b17023SJohn Marino 3446*e4b17023SJohn Marino@item y 3447*e4b17023SJohn MarinoThe carry register. 3448*e4b17023SJohn Marino 3449*e4b17023SJohn Marino@item z 3450*e4b17023SJohn MarinoRegisters r8 and r9. 3451*e4b17023SJohn Marino 3452*e4b17023SJohn Marino@item I 3453*e4b17023SJohn MarinoA constant between 0 and 3 inclusive. 3454*e4b17023SJohn Marino 3455*e4b17023SJohn Marino@item J 3456*e4b17023SJohn MarinoA constant that has exactly one bit set. 3457*e4b17023SJohn Marino 3458*e4b17023SJohn Marino@item K 3459*e4b17023SJohn MarinoA constant that has exactly one bit clear. 3460*e4b17023SJohn Marino 3461*e4b17023SJohn Marino@item L 3462*e4b17023SJohn MarinoA constant between 0 and 255 inclusive. 3463*e4b17023SJohn Marino 3464*e4b17023SJohn Marino@item M 3465*e4b17023SJohn MarinoA constant between @minus{}255 and 0 inclusive. 3466*e4b17023SJohn Marino 3467*e4b17023SJohn Marino@item N 3468*e4b17023SJohn MarinoA constant between @minus{}3 and 0 inclusive. 3469*e4b17023SJohn Marino 3470*e4b17023SJohn Marino@item O 3471*e4b17023SJohn MarinoA constant between 1 and 4 inclusive. 3472*e4b17023SJohn Marino 3473*e4b17023SJohn Marino@item P 3474*e4b17023SJohn MarinoA constant between @minus{}4 and @minus{}1 inclusive. 3475*e4b17023SJohn Marino 3476*e4b17023SJohn Marino@item Q 3477*e4b17023SJohn MarinoA memory reference that is a stack push. 3478*e4b17023SJohn Marino 3479*e4b17023SJohn Marino@item R 3480*e4b17023SJohn MarinoA memory reference that is a stack pop. 3481*e4b17023SJohn Marino 3482*e4b17023SJohn Marino@item S 3483*e4b17023SJohn MarinoA memory reference that refers to a constant address of known value. 3484*e4b17023SJohn Marino 3485*e4b17023SJohn Marino@item T 3486*e4b17023SJohn MarinoThe register indicated by Rx (not implemented yet). 3487*e4b17023SJohn Marino 3488*e4b17023SJohn Marino@item U 3489*e4b17023SJohn MarinoA constant that is not between 2 and 15 inclusive. 3490*e4b17023SJohn Marino 3491*e4b17023SJohn Marino@item Z 3492*e4b17023SJohn MarinoThe constant 0. 3493*e4b17023SJohn Marino 3494*e4b17023SJohn Marino@end table 3495*e4b17023SJohn Marino 3496*e4b17023SJohn Marino@item TI C6X family---@file{config/c6x/constraints.md} 3497*e4b17023SJohn Marino@table @code 3498*e4b17023SJohn Marino@item a 3499*e4b17023SJohn MarinoRegister file A (A0--A31). 3500*e4b17023SJohn Marino 3501*e4b17023SJohn Marino@item b 3502*e4b17023SJohn MarinoRegister file B (B0--B31). 3503*e4b17023SJohn Marino 3504*e4b17023SJohn Marino@item A 3505*e4b17023SJohn MarinoPredicate registers in register file A (A0--A2 on C64X and 3506*e4b17023SJohn Marinohigher, A1 and A2 otherwise). 3507*e4b17023SJohn Marino 3508*e4b17023SJohn Marino@item B 3509*e4b17023SJohn MarinoPredicate registers in register file B (B0--B2). 3510*e4b17023SJohn Marino 3511*e4b17023SJohn Marino@item C 3512*e4b17023SJohn MarinoA call-used register in register file B (B0--B9, B16--B31). 3513*e4b17023SJohn Marino 3514*e4b17023SJohn Marino@item Da 3515*e4b17023SJohn MarinoRegister file A, excluding predicate registers (A3--A31, 3516*e4b17023SJohn Marinoplus A0 if not C64X or higher). 3517*e4b17023SJohn Marino 3518*e4b17023SJohn Marino@item Db 3519*e4b17023SJohn MarinoRegister file B, excluding predicate registers (B3--B31). 3520*e4b17023SJohn Marino 3521*e4b17023SJohn Marino@item Iu4 3522*e4b17023SJohn MarinoInteger constant in the range 0 @dots{} 15. 3523*e4b17023SJohn Marino 3524*e4b17023SJohn Marino@item Iu5 3525*e4b17023SJohn MarinoInteger constant in the range 0 @dots{} 31. 3526*e4b17023SJohn Marino 3527*e4b17023SJohn Marino@item In5 3528*e4b17023SJohn MarinoInteger constant in the range @minus{}31 @dots{} 0. 3529*e4b17023SJohn Marino 3530*e4b17023SJohn Marino@item Is5 3531*e4b17023SJohn MarinoInteger constant in the range @minus{}16 @dots{} 15. 3532*e4b17023SJohn Marino 3533*e4b17023SJohn Marino@item I5x 3534*e4b17023SJohn MarinoInteger constant that can be the operand of an ADDA or a SUBA insn. 3535*e4b17023SJohn Marino 3536*e4b17023SJohn Marino@item IuB 3537*e4b17023SJohn MarinoInteger constant in the range 0 @dots{} 65535. 3538*e4b17023SJohn Marino 3539*e4b17023SJohn Marino@item IsB 3540*e4b17023SJohn MarinoInteger constant in the range @minus{}32768 @dots{} 32767. 3541*e4b17023SJohn Marino 3542*e4b17023SJohn Marino@item IsC 3543*e4b17023SJohn MarinoInteger constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}. 3544*e4b17023SJohn Marino 3545*e4b17023SJohn Marino@item Jc 3546*e4b17023SJohn MarinoInteger constant that is a valid mask for the clr instruction. 3547*e4b17023SJohn Marino 3548*e4b17023SJohn Marino@item Js 3549*e4b17023SJohn MarinoInteger constant that is a valid mask for the set instruction. 3550*e4b17023SJohn Marino 3551*e4b17023SJohn Marino@item Q 3552*e4b17023SJohn MarinoMemory location with A base register. 3553*e4b17023SJohn Marino 3554*e4b17023SJohn Marino@item R 3555*e4b17023SJohn MarinoMemory location with B base register. 3556*e4b17023SJohn Marino 3557*e4b17023SJohn Marino@ifset INTERNALS 3558*e4b17023SJohn Marino@item S0 3559*e4b17023SJohn MarinoOn C64x+ targets, a GP-relative small data reference. 3560*e4b17023SJohn Marino 3561*e4b17023SJohn Marino@item S1 3562*e4b17023SJohn MarinoAny kind of @code{SYMBOL_REF}, for use in a call address. 3563*e4b17023SJohn Marino 3564*e4b17023SJohn Marino@item Si 3565*e4b17023SJohn MarinoAny kind of immediate operand, unless it matches the S0 constraint. 3566*e4b17023SJohn Marino 3567*e4b17023SJohn Marino@item T 3568*e4b17023SJohn MarinoMemory location with B base register, but not using a long offset. 3569*e4b17023SJohn Marino 3570*e4b17023SJohn Marino@item W 3571*e4b17023SJohn MarinoA memory operand with an address that can't be used in an unaligned access. 3572*e4b17023SJohn Marino 3573*e4b17023SJohn Marino@end ifset 3574*e4b17023SJohn Marino@item Z 3575*e4b17023SJohn MarinoRegister B14 (aka DP). 3576*e4b17023SJohn Marino 3577*e4b17023SJohn Marino@end table 3578*e4b17023SJohn Marino 3579*e4b17023SJohn Marino@item TILE-Gx---@file{config/tilegx/constraints.md} 3580*e4b17023SJohn Marino@table @code 3581*e4b17023SJohn Marino@item R00 3582*e4b17023SJohn Marino@itemx R01 3583*e4b17023SJohn Marino@itemx R02 3584*e4b17023SJohn Marino@itemx R03 3585*e4b17023SJohn Marino@itemx R04 3586*e4b17023SJohn Marino@itemx R05 3587*e4b17023SJohn Marino@itemx R06 3588*e4b17023SJohn Marino@itemx R07 3589*e4b17023SJohn Marino@itemx R08 3590*e4b17023SJohn Marino@itemx R09 3591*e4b17023SJohn Marino@itemx R10 3592*e4b17023SJohn MarinoEach of these represents a register constraint for an individual 3593*e4b17023SJohn Marinoregister, from r0 to r10. 3594*e4b17023SJohn Marino 3595*e4b17023SJohn Marino@item I 3596*e4b17023SJohn MarinoSigned 8-bit integer constant. 3597*e4b17023SJohn Marino 3598*e4b17023SJohn Marino@item J 3599*e4b17023SJohn MarinoSigned 16-bit integer constant. 3600*e4b17023SJohn Marino 3601*e4b17023SJohn Marino@item K 3602*e4b17023SJohn MarinoUnsigned 16-bit integer constant. 3603*e4b17023SJohn Marino 3604*e4b17023SJohn Marino@item L 3605*e4b17023SJohn MarinoInteger constant that fits in one signed byte when incremented by one 3606*e4b17023SJohn Marino(@minus{}129 @dots{} 126). 3607*e4b17023SJohn Marino 3608*e4b17023SJohn Marino@item m 3609*e4b17023SJohn MarinoMemory operand. If used together with @samp{<} or @samp{>}, the 3610*e4b17023SJohn Marinooperand can have postincrement which requires printing with @samp{%In} 3611*e4b17023SJohn Marinoand @samp{%in} on TILE-Gx. For example: 3612*e4b17023SJohn Marino 3613*e4b17023SJohn Marino@smallexample 3614*e4b17023SJohn Marinoasm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val)); 3615*e4b17023SJohn Marino@end smallexample 3616*e4b17023SJohn Marino 3617*e4b17023SJohn Marino@item M 3618*e4b17023SJohn MarinoA bit mask suitable for the BFINS instruction. 3619*e4b17023SJohn Marino 3620*e4b17023SJohn Marino@item N 3621*e4b17023SJohn MarinoInteger constant that is a byte tiled out eight times. 3622*e4b17023SJohn Marino 3623*e4b17023SJohn Marino@item O 3624*e4b17023SJohn MarinoThe integer zero constant. 3625*e4b17023SJohn Marino 3626*e4b17023SJohn Marino@item P 3627*e4b17023SJohn MarinoInteger constant that is a sign-extended byte tiled out as four shorts. 3628*e4b17023SJohn Marino 3629*e4b17023SJohn Marino@item Q 3630*e4b17023SJohn MarinoInteger constant that fits in one signed byte when incremented 3631*e4b17023SJohn Marino(@minus{}129 @dots{} 126), but excluding -1. 3632*e4b17023SJohn Marino 3633*e4b17023SJohn Marino@item S 3634*e4b17023SJohn MarinoInteger constant that has all 1 bits consecutive and starting at bit 0. 3635*e4b17023SJohn Marino 3636*e4b17023SJohn Marino@item T 3637*e4b17023SJohn MarinoA 16-bit fragment of a got, tls, or pc-relative reference. 3638*e4b17023SJohn Marino 3639*e4b17023SJohn Marino@item U 3640*e4b17023SJohn MarinoMemory operand except postincrement. This is roughly the same as 3641*e4b17023SJohn Marino@samp{m} when not used together with @samp{<} or @samp{>}. 3642*e4b17023SJohn Marino 3643*e4b17023SJohn Marino@item W 3644*e4b17023SJohn MarinoAn 8-element vector constant with identical elements. 3645*e4b17023SJohn Marino 3646*e4b17023SJohn Marino@item Y 3647*e4b17023SJohn MarinoA 4-element vector constant with identical elements. 3648*e4b17023SJohn Marino 3649*e4b17023SJohn Marino@item Z0 3650*e4b17023SJohn MarinoThe integer constant 0xffffffff. 3651*e4b17023SJohn Marino 3652*e4b17023SJohn Marino@item Z1 3653*e4b17023SJohn MarinoThe integer constant 0xffffffff00000000. 3654*e4b17023SJohn Marino 3655*e4b17023SJohn Marino@end table 3656*e4b17023SJohn Marino 3657*e4b17023SJohn Marino@item TILEPro---@file{config/tilepro/constraints.md} 3658*e4b17023SJohn Marino@table @code 3659*e4b17023SJohn Marino@item R00 3660*e4b17023SJohn Marino@itemx R01 3661*e4b17023SJohn Marino@itemx R02 3662*e4b17023SJohn Marino@itemx R03 3663*e4b17023SJohn Marino@itemx R04 3664*e4b17023SJohn Marino@itemx R05 3665*e4b17023SJohn Marino@itemx R06 3666*e4b17023SJohn Marino@itemx R07 3667*e4b17023SJohn Marino@itemx R08 3668*e4b17023SJohn Marino@itemx R09 3669*e4b17023SJohn Marino@itemx R10 3670*e4b17023SJohn MarinoEach of these represents a register constraint for an individual 3671*e4b17023SJohn Marinoregister, from r0 to r10. 3672*e4b17023SJohn Marino 3673*e4b17023SJohn Marino@item I 3674*e4b17023SJohn MarinoSigned 8-bit integer constant. 3675*e4b17023SJohn Marino 3676*e4b17023SJohn Marino@item J 3677*e4b17023SJohn MarinoSigned 16-bit integer constant. 3678*e4b17023SJohn Marino 3679*e4b17023SJohn Marino@item K 3680*e4b17023SJohn MarinoNonzero integer constant with low 16 bits zero. 3681*e4b17023SJohn Marino 3682*e4b17023SJohn Marino@item L 3683*e4b17023SJohn MarinoInteger constant that fits in one signed byte when incremented by one 3684*e4b17023SJohn Marino(@minus{}129 @dots{} 126). 3685*e4b17023SJohn Marino 3686*e4b17023SJohn Marino@item m 3687*e4b17023SJohn MarinoMemory operand. If used together with @samp{<} or @samp{>}, the 3688*e4b17023SJohn Marinooperand can have postincrement which requires printing with @samp{%In} 3689*e4b17023SJohn Marinoand @samp{%in} on TILEPro. For example: 3690*e4b17023SJohn Marino 3691*e4b17023SJohn Marino@smallexample 3692*e4b17023SJohn Marinoasm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val)); 3693*e4b17023SJohn Marino@end smallexample 3694*e4b17023SJohn Marino 3695*e4b17023SJohn Marino@item M 3696*e4b17023SJohn MarinoA bit mask suitable for the MM instruction. 3697*e4b17023SJohn Marino 3698*e4b17023SJohn Marino@item N 3699*e4b17023SJohn MarinoInteger constant that is a byte tiled out four times. 3700*e4b17023SJohn Marino 3701*e4b17023SJohn Marino@item O 3702*e4b17023SJohn MarinoThe integer zero constant. 3703*e4b17023SJohn Marino 3704*e4b17023SJohn Marino@item P 3705*e4b17023SJohn MarinoInteger constant that is a sign-extended byte tiled out as two shorts. 3706*e4b17023SJohn Marino 3707*e4b17023SJohn Marino@item Q 3708*e4b17023SJohn MarinoInteger constant that fits in one signed byte when incremented 3709*e4b17023SJohn Marino(@minus{}129 @dots{} 126), but excluding -1. 3710*e4b17023SJohn Marino 3711*e4b17023SJohn Marino@item T 3712*e4b17023SJohn MarinoA symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative 3713*e4b17023SJohn Marinoreference. 3714*e4b17023SJohn Marino 3715*e4b17023SJohn Marino@item U 3716*e4b17023SJohn MarinoMemory operand except postincrement. This is roughly the same as 3717*e4b17023SJohn Marino@samp{m} when not used together with @samp{<} or @samp{>}. 3718*e4b17023SJohn Marino 3719*e4b17023SJohn Marino@item W 3720*e4b17023SJohn MarinoA 4-element vector constant with identical elements. 3721*e4b17023SJohn Marino 3722*e4b17023SJohn Marino@item Y 3723*e4b17023SJohn MarinoA 2-element vector constant with identical elements. 3724*e4b17023SJohn Marino 3725*e4b17023SJohn Marino@end table 3726*e4b17023SJohn Marino 3727*e4b17023SJohn Marino@item Xtensa---@file{config/xtensa/constraints.md} 3728*e4b17023SJohn Marino@table @code 3729*e4b17023SJohn Marino@item a 3730*e4b17023SJohn MarinoGeneral-purpose 32-bit register 3731*e4b17023SJohn Marino 3732*e4b17023SJohn Marino@item b 3733*e4b17023SJohn MarinoOne-bit boolean register 3734*e4b17023SJohn Marino 3735*e4b17023SJohn Marino@item A 3736*e4b17023SJohn MarinoMAC16 40-bit accumulator register 3737*e4b17023SJohn Marino 3738*e4b17023SJohn Marino@item I 3739*e4b17023SJohn MarinoSigned 12-bit integer constant, for use in MOVI instructions 3740*e4b17023SJohn Marino 3741*e4b17023SJohn Marino@item J 3742*e4b17023SJohn MarinoSigned 8-bit integer constant, for use in ADDI instructions 3743*e4b17023SJohn Marino 3744*e4b17023SJohn Marino@item K 3745*e4b17023SJohn MarinoInteger constant valid for BccI instructions 3746*e4b17023SJohn Marino 3747*e4b17023SJohn Marino@item L 3748*e4b17023SJohn MarinoUnsigned constant valid for BccUI instructions 3749*e4b17023SJohn Marino 3750*e4b17023SJohn Marino@end table 3751*e4b17023SJohn Marino 3752*e4b17023SJohn Marino@end table 3753*e4b17023SJohn Marino 3754*e4b17023SJohn Marino@ifset INTERNALS 3755*e4b17023SJohn Marino@node Disable Insn Alternatives 3756*e4b17023SJohn Marino@subsection Disable insn alternatives using the @code{enabled} attribute 3757*e4b17023SJohn Marino@cindex enabled 3758*e4b17023SJohn Marino 3759*e4b17023SJohn MarinoThe @code{enabled} insn attribute may be used to disable certain insn 3760*e4b17023SJohn Marinoalternatives for machine-specific reasons. This is useful when adding 3761*e4b17023SJohn Marinonew instructions to an existing pattern which are only available for 3762*e4b17023SJohn Marinocertain cpu architecture levels as specified with the @code{-march=} 3763*e4b17023SJohn Marinooption. 3764*e4b17023SJohn Marino 3765*e4b17023SJohn MarinoIf an insn alternative is disabled, then it will never be used. The 3766*e4b17023SJohn Marinocompiler treats the constraints for the disabled alternative as 3767*e4b17023SJohn Marinounsatisfiable. 3768*e4b17023SJohn Marino 3769*e4b17023SJohn MarinoIn order to make use of the @code{enabled} attribute a back end has to add 3770*e4b17023SJohn Marinoin the machine description files: 3771*e4b17023SJohn Marino 3772*e4b17023SJohn Marino@enumerate 3773*e4b17023SJohn Marino@item 3774*e4b17023SJohn MarinoA definition of the @code{enabled} insn attribute. The attribute is 3775*e4b17023SJohn Marinodefined as usual using the @code{define_attr} command. This 3776*e4b17023SJohn Marinodefinition should be based on other insn attributes and/or target flags. 3777*e4b17023SJohn MarinoThe @code{enabled} attribute is a numeric attribute and should evaluate to 3778*e4b17023SJohn Marino@code{(const_int 1)} for an enabled alternative and to 3779*e4b17023SJohn Marino@code{(const_int 0)} otherwise. 3780*e4b17023SJohn Marino@item 3781*e4b17023SJohn MarinoA definition of another insn attribute used to describe for what 3782*e4b17023SJohn Marinoreason an insn alternative might be available or 3783*e4b17023SJohn Marinonot. E.g. @code{cpu_facility} as in the example below. 3784*e4b17023SJohn Marino@item 3785*e4b17023SJohn MarinoAn assignment for the second attribute to each insn definition 3786*e4b17023SJohn Marinocombining instructions which are not all available under the same 3787*e4b17023SJohn Marinocircumstances. (Note: It obviously only makes sense for definitions 3788*e4b17023SJohn Marinowith more than one alternative. Otherwise the insn pattern should be 3789*e4b17023SJohn Marinodisabled or enabled using the insn condition.) 3790*e4b17023SJohn Marino@end enumerate 3791*e4b17023SJohn Marino 3792*e4b17023SJohn MarinoE.g. the following two patterns could easily be merged using the @code{enabled} 3793*e4b17023SJohn Marinoattribute: 3794*e4b17023SJohn Marino 3795*e4b17023SJohn Marino@smallexample 3796*e4b17023SJohn Marino 3797*e4b17023SJohn Marino(define_insn "*movdi_old" 3798*e4b17023SJohn Marino [(set (match_operand:DI 0 "register_operand" "=d") 3799*e4b17023SJohn Marino (match_operand:DI 1 "register_operand" " d"))] 3800*e4b17023SJohn Marino "!TARGET_NEW" 3801*e4b17023SJohn Marino "lgr %0,%1") 3802*e4b17023SJohn Marino 3803*e4b17023SJohn Marino(define_insn "*movdi_new" 3804*e4b17023SJohn Marino [(set (match_operand:DI 0 "register_operand" "=d,f,d") 3805*e4b17023SJohn Marino (match_operand:DI 1 "register_operand" " d,d,f"))] 3806*e4b17023SJohn Marino "TARGET_NEW" 3807*e4b17023SJohn Marino "@@ 3808*e4b17023SJohn Marino lgr %0,%1 3809*e4b17023SJohn Marino ldgr %0,%1 3810*e4b17023SJohn Marino lgdr %0,%1") 3811*e4b17023SJohn Marino 3812*e4b17023SJohn Marino@end smallexample 3813*e4b17023SJohn Marino 3814*e4b17023SJohn Marinoto: 3815*e4b17023SJohn Marino 3816*e4b17023SJohn Marino@smallexample 3817*e4b17023SJohn Marino 3818*e4b17023SJohn Marino(define_insn "*movdi_combined" 3819*e4b17023SJohn Marino [(set (match_operand:DI 0 "register_operand" "=d,f,d") 3820*e4b17023SJohn Marino (match_operand:DI 1 "register_operand" " d,d,f"))] 3821*e4b17023SJohn Marino "" 3822*e4b17023SJohn Marino "@@ 3823*e4b17023SJohn Marino lgr %0,%1 3824*e4b17023SJohn Marino ldgr %0,%1 3825*e4b17023SJohn Marino lgdr %0,%1" 3826*e4b17023SJohn Marino [(set_attr "cpu_facility" "*,new,new")]) 3827*e4b17023SJohn Marino 3828*e4b17023SJohn Marino@end smallexample 3829*e4b17023SJohn Marino 3830*e4b17023SJohn Marinowith the @code{enabled} attribute defined like this: 3831*e4b17023SJohn Marino 3832*e4b17023SJohn Marino@smallexample 3833*e4b17023SJohn Marino 3834*e4b17023SJohn Marino(define_attr "cpu_facility" "standard,new" (const_string "standard")) 3835*e4b17023SJohn Marino 3836*e4b17023SJohn Marino(define_attr "enabled" "" 3837*e4b17023SJohn Marino (cond [(eq_attr "cpu_facility" "standard") (const_int 1) 3838*e4b17023SJohn Marino (and (eq_attr "cpu_facility" "new") 3839*e4b17023SJohn Marino (ne (symbol_ref "TARGET_NEW") (const_int 0))) 3840*e4b17023SJohn Marino (const_int 1)] 3841*e4b17023SJohn Marino (const_int 0))) 3842*e4b17023SJohn Marino 3843*e4b17023SJohn Marino@end smallexample 3844*e4b17023SJohn Marino 3845*e4b17023SJohn Marino@end ifset 3846*e4b17023SJohn Marino 3847*e4b17023SJohn Marino@ifset INTERNALS 3848*e4b17023SJohn Marino@node Define Constraints 3849*e4b17023SJohn Marino@subsection Defining Machine-Specific Constraints 3850*e4b17023SJohn Marino@cindex defining constraints 3851*e4b17023SJohn Marino@cindex constraints, defining 3852*e4b17023SJohn Marino 3853*e4b17023SJohn MarinoMachine-specific constraints fall into two categories: register and 3854*e4b17023SJohn Marinonon-register constraints. Within the latter category, constraints 3855*e4b17023SJohn Marinowhich allow subsets of all possible memory or address operands should 3856*e4b17023SJohn Marinobe specially marked, to give @code{reload} more information. 3857*e4b17023SJohn Marino 3858*e4b17023SJohn MarinoMachine-specific constraints can be given names of arbitrary length, 3859*e4b17023SJohn Marinobut they must be entirely composed of letters, digits, underscores 3860*e4b17023SJohn Marino(@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they 3861*e4b17023SJohn Marinomust begin with a letter or underscore. 3862*e4b17023SJohn Marino 3863*e4b17023SJohn MarinoIn order to avoid ambiguity in operand constraint strings, no 3864*e4b17023SJohn Marinoconstraint can have a name that begins with any other constraint's 3865*e4b17023SJohn Marinoname. For example, if @code{x} is defined as a constraint name, 3866*e4b17023SJohn Marino@code{xy} may not be, and vice versa. As a consequence of this rule, 3867*e4b17023SJohn Marinono constraint may begin with one of the generic constraint letters: 3868*e4b17023SJohn Marino@samp{E F V X g i m n o p r s}. 3869*e4b17023SJohn Marino 3870*e4b17023SJohn MarinoRegister constraints correspond directly to register classes. 3871*e4b17023SJohn Marino@xref{Register Classes}. There is thus not much flexibility in their 3872*e4b17023SJohn Marinodefinitions. 3873*e4b17023SJohn Marino 3874*e4b17023SJohn Marino@deffn {MD Expression} define_register_constraint name regclass docstring 3875*e4b17023SJohn MarinoAll three arguments are string constants. 3876*e4b17023SJohn Marino@var{name} is the name of the constraint, as it will appear in 3877*e4b17023SJohn Marino@code{match_operand} expressions. If @var{name} is a multi-letter 3878*e4b17023SJohn Marinoconstraint its length shall be the same for all constraints starting 3879*e4b17023SJohn Marinowith the same letter. @var{regclass} can be either the 3880*e4b17023SJohn Marinoname of the corresponding register class (@pxref{Register Classes}), 3881*e4b17023SJohn Marinoor a C expression which evaluates to the appropriate register class. 3882*e4b17023SJohn MarinoIf it is an expression, it must have no side effects, and it cannot 3883*e4b17023SJohn Marinolook at the operand. The usual use of expressions is to map some 3884*e4b17023SJohn Marinoregister constraints to @code{NO_REGS} when the register class 3885*e4b17023SJohn Marinois not available on a given subarchitecture. 3886*e4b17023SJohn Marino 3887*e4b17023SJohn Marino@var{docstring} is a sentence documenting the meaning of the 3888*e4b17023SJohn Marinoconstraint. Docstrings are explained further below. 3889*e4b17023SJohn Marino@end deffn 3890*e4b17023SJohn Marino 3891*e4b17023SJohn MarinoNon-register constraints are more like predicates: the constraint 3892*e4b17023SJohn Marinodefinition gives a Boolean expression which indicates whether the 3893*e4b17023SJohn Marinoconstraint matches. 3894*e4b17023SJohn Marino 3895*e4b17023SJohn Marino@deffn {MD Expression} define_constraint name docstring exp 3896*e4b17023SJohn MarinoThe @var{name} and @var{docstring} arguments are the same as for 3897*e4b17023SJohn Marino@code{define_register_constraint}, but note that the docstring comes 3898*e4b17023SJohn Marinoimmediately after the name for these expressions. @var{exp} is an RTL 3899*e4b17023SJohn Marinoexpression, obeying the same rules as the RTL expressions in predicate 3900*e4b17023SJohn Marinodefinitions. @xref{Defining Predicates}, for details. If it 3901*e4b17023SJohn Marinoevaluates true, the constraint matches; if it evaluates false, it 3902*e4b17023SJohn Marinodoesn't. Constraint expressions should indicate which RTL codes they 3903*e4b17023SJohn Marinomight match, just like predicate expressions. 3904*e4b17023SJohn Marino 3905*e4b17023SJohn Marino@code{match_test} C expressions have access to the 3906*e4b17023SJohn Marinofollowing variables: 3907*e4b17023SJohn Marino 3908*e4b17023SJohn Marino@table @var 3909*e4b17023SJohn Marino@item op 3910*e4b17023SJohn MarinoThe RTL object defining the operand. 3911*e4b17023SJohn Marino@item mode 3912*e4b17023SJohn MarinoThe machine mode of @var{op}. 3913*e4b17023SJohn Marino@item ival 3914*e4b17023SJohn Marino@samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}. 3915*e4b17023SJohn Marino@item hval 3916*e4b17023SJohn Marino@samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer 3917*e4b17023SJohn Marino@code{const_double}. 3918*e4b17023SJohn Marino@item lval 3919*e4b17023SJohn Marino@samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer 3920*e4b17023SJohn Marino@code{const_double}. 3921*e4b17023SJohn Marino@item rval 3922*e4b17023SJohn Marino@samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point 3923*e4b17023SJohn Marino@code{const_double}. 3924*e4b17023SJohn Marino@end table 3925*e4b17023SJohn Marino 3926*e4b17023SJohn MarinoThe @var{*val} variables should only be used once another piece of the 3927*e4b17023SJohn Marinoexpression has verified that @var{op} is the appropriate kind of RTL 3928*e4b17023SJohn Marinoobject. 3929*e4b17023SJohn Marino@end deffn 3930*e4b17023SJohn Marino 3931*e4b17023SJohn MarinoMost non-register constraints should be defined with 3932*e4b17023SJohn Marino@code{define_constraint}. The remaining two definition expressions 3933*e4b17023SJohn Marinoare only appropriate for constraints that should be handled specially 3934*e4b17023SJohn Marinoby @code{reload} if they fail to match. 3935*e4b17023SJohn Marino 3936*e4b17023SJohn Marino@deffn {MD Expression} define_memory_constraint name docstring exp 3937*e4b17023SJohn MarinoUse this expression for constraints that match a subset of all memory 3938*e4b17023SJohn Marinooperands: that is, @code{reload} can make them match by converting the 3939*e4b17023SJohn Marinooperand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a 3940*e4b17023SJohn Marinobase register (from the register class specified by 3941*e4b17023SJohn Marino@code{BASE_REG_CLASS}, @pxref{Register Classes}). 3942*e4b17023SJohn Marino 3943*e4b17023SJohn MarinoFor example, on the S/390, some instructions do not accept arbitrary 3944*e4b17023SJohn Marinomemory references, but only those that do not make use of an index 3945*e4b17023SJohn Marinoregister. The constraint letter @samp{Q} is defined to represent a 3946*e4b17023SJohn Marinomemory address of this type. If @samp{Q} is defined with 3947*e4b17023SJohn Marino@code{define_memory_constraint}, a @samp{Q} constraint can handle any 3948*e4b17023SJohn Marinomemory operand, because @code{reload} knows it can simply copy the 3949*e4b17023SJohn Marinomemory address into a base register if required. This is analogous to 3950*e4b17023SJohn Marinothe way an @samp{o} constraint can handle any memory operand. 3951*e4b17023SJohn Marino 3952*e4b17023SJohn MarinoThe syntax and semantics are otherwise identical to 3953*e4b17023SJohn Marino@code{define_constraint}. 3954*e4b17023SJohn Marino@end deffn 3955*e4b17023SJohn Marino 3956*e4b17023SJohn Marino@deffn {MD Expression} define_address_constraint name docstring exp 3957*e4b17023SJohn MarinoUse this expression for constraints that match a subset of all address 3958*e4b17023SJohn Marinooperands: that is, @code{reload} can make the constraint match by 3959*e4b17023SJohn Marinoconverting the operand to the form @samp{@w{(reg @var{X})}}, again 3960*e4b17023SJohn Marinowith @var{X} a base register. 3961*e4b17023SJohn Marino 3962*e4b17023SJohn MarinoConstraints defined with @code{define_address_constraint} can only be 3963*e4b17023SJohn Marinoused with the @code{address_operand} predicate, or machine-specific 3964*e4b17023SJohn Marinopredicates that work the same way. They are treated analogously to 3965*e4b17023SJohn Marinothe generic @samp{p} constraint. 3966*e4b17023SJohn Marino 3967*e4b17023SJohn MarinoThe syntax and semantics are otherwise identical to 3968*e4b17023SJohn Marino@code{define_constraint}. 3969*e4b17023SJohn Marino@end deffn 3970*e4b17023SJohn Marino 3971*e4b17023SJohn MarinoFor historical reasons, names beginning with the letters @samp{G H} 3972*e4b17023SJohn Marinoare reserved for constraints that match only @code{const_double}s, and 3973*e4b17023SJohn Marinonames beginning with the letters @samp{I J K L M N O P} are reserved 3974*e4b17023SJohn Marinofor constraints that match only @code{const_int}s. This may change in 3975*e4b17023SJohn Marinothe future. For the time being, constraints with these names must be 3976*e4b17023SJohn Marinowritten in a stylized form, so that @code{genpreds} can tell you did 3977*e4b17023SJohn Marinoit correctly: 3978*e4b17023SJohn Marino 3979*e4b17023SJohn Marino@smallexample 3980*e4b17023SJohn Marino@group 3981*e4b17023SJohn Marino(define_constraint "[@var{GHIJKLMNOP}]@dots{}" 3982*e4b17023SJohn Marino "@var{doc}@dots{}" 3983*e4b17023SJohn Marino (and (match_code "const_int") ; @r{@code{const_double} for G/H} 3984*e4b17023SJohn Marino @var{condition}@dots{})) ; @r{usually a @code{match_test}} 3985*e4b17023SJohn Marino@end group 3986*e4b17023SJohn Marino@end smallexample 3987*e4b17023SJohn Marino@c the semicolons line up in the formatted manual 3988*e4b17023SJohn Marino 3989*e4b17023SJohn MarinoIt is fine to use names beginning with other letters for constraints 3990*e4b17023SJohn Marinothat match @code{const_double}s or @code{const_int}s. 3991*e4b17023SJohn Marino 3992*e4b17023SJohn MarinoEach docstring in a constraint definition should be one or more complete 3993*e4b17023SJohn Marinosentences, marked up in Texinfo format. @emph{They are currently unused.} 3994*e4b17023SJohn MarinoIn the future they will be copied into the GCC manual, in @ref{Machine 3995*e4b17023SJohn MarinoConstraints}, replacing the hand-maintained tables currently found in 3996*e4b17023SJohn Marinothat section. Also, in the future the compiler may use this to give 3997*e4b17023SJohn Marinomore helpful diagnostics when poor choice of @code{asm} constraints 3998*e4b17023SJohn Marinocauses a reload failure. 3999*e4b17023SJohn Marino 4000*e4b17023SJohn MarinoIf you put the pseudo-Texinfo directive @samp{@@internal} at the 4001*e4b17023SJohn Marinobeginning of a docstring, then (in the future) it will appear only in 4002*e4b17023SJohn Marinothe internals manual's version of the machine-specific constraint tables. 4003*e4b17023SJohn MarinoUse this for constraints that should not appear in @code{asm} statements. 4004*e4b17023SJohn Marino 4005*e4b17023SJohn Marino@node C Constraint Interface 4006*e4b17023SJohn Marino@subsection Testing constraints from C 4007*e4b17023SJohn Marino@cindex testing constraints 4008*e4b17023SJohn Marino@cindex constraints, testing 4009*e4b17023SJohn Marino 4010*e4b17023SJohn MarinoIt is occasionally useful to test a constraint from C code rather than 4011*e4b17023SJohn Marinoimplicitly via the constraint string in a @code{match_operand}. The 4012*e4b17023SJohn Marinogenerated file @file{tm_p.h} declares a few interfaces for working 4013*e4b17023SJohn Marinowith machine-specific constraints. None of these interfaces work with 4014*e4b17023SJohn Marinothe generic constraints described in @ref{Simple Constraints}. This 4015*e4b17023SJohn Marinomay change in the future. 4016*e4b17023SJohn Marino 4017*e4b17023SJohn Marino@strong{Warning:} @file{tm_p.h} may declare other functions that 4018*e4b17023SJohn Marinooperate on constraints, besides the ones documented here. Do not use 4019*e4b17023SJohn Marinothose functions from machine-dependent code. They exist to implement 4020*e4b17023SJohn Marinothe old constraint interface that machine-independent components of 4021*e4b17023SJohn Marinothe compiler still expect. They will change or disappear in the 4022*e4b17023SJohn Marinofuture. 4023*e4b17023SJohn Marino 4024*e4b17023SJohn MarinoSome valid constraint names are not valid C identifiers, so there is a 4025*e4b17023SJohn Marinomangling scheme for referring to them from C@. Constraint names that 4026*e4b17023SJohn Marinodo not contain angle brackets or underscores are left unchanged. 4027*e4b17023SJohn MarinoUnderscores are doubled, each @samp{<} is replaced with @samp{_l}, and 4028*e4b17023SJohn Marinoeach @samp{>} with @samp{_g}. Here are some examples: 4029*e4b17023SJohn Marino 4030*e4b17023SJohn Marino@c the @c's prevent double blank lines in the printed manual. 4031*e4b17023SJohn Marino@example 4032*e4b17023SJohn Marino@multitable {Original} {Mangled} 4033*e4b17023SJohn Marino@item @strong{Original} @tab @strong{Mangled} @c 4034*e4b17023SJohn Marino@item @code{x} @tab @code{x} @c 4035*e4b17023SJohn Marino@item @code{P42x} @tab @code{P42x} @c 4036*e4b17023SJohn Marino@item @code{P4_x} @tab @code{P4__x} @c 4037*e4b17023SJohn Marino@item @code{P4>x} @tab @code{P4_gx} @c 4038*e4b17023SJohn Marino@item @code{P4>>} @tab @code{P4_g_g} @c 4039*e4b17023SJohn Marino@item @code{P4_g>} @tab @code{P4__g_g} @c 4040*e4b17023SJohn Marino@end multitable 4041*e4b17023SJohn Marino@end example 4042*e4b17023SJohn Marino 4043*e4b17023SJohn MarinoThroughout this section, the variable @var{c} is either a constraint 4044*e4b17023SJohn Marinoin the abstract sense, or a constant from @code{enum constraint_num}; 4045*e4b17023SJohn Marinothe variable @var{m} is a mangled constraint name (usually as part of 4046*e4b17023SJohn Marinoa larger identifier). 4047*e4b17023SJohn Marino 4048*e4b17023SJohn Marino@deftp Enum constraint_num 4049*e4b17023SJohn MarinoFor each machine-specific constraint, there is a corresponding 4050*e4b17023SJohn Marinoenumeration constant: @samp{CONSTRAINT_} plus the mangled name of the 4051*e4b17023SJohn Marinoconstraint. Functions that take an @code{enum constraint_num} as an 4052*e4b17023SJohn Marinoargument expect one of these constants. 4053*e4b17023SJohn Marino 4054*e4b17023SJohn MarinoMachine-independent constraints do not have associated constants. 4055*e4b17023SJohn MarinoThis may change in the future. 4056*e4b17023SJohn Marino@end deftp 4057*e4b17023SJohn Marino 4058*e4b17023SJohn Marino@deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp}) 4059*e4b17023SJohn MarinoFor each machine-specific, non-register constraint @var{m}, there is 4060*e4b17023SJohn Marinoone of these functions; it returns @code{true} if @var{exp} satisfies the 4061*e4b17023SJohn Marinoconstraint. These functions are only visible if @file{rtl.h} was included 4062*e4b17023SJohn Marinobefore @file{tm_p.h}. 4063*e4b17023SJohn Marino@end deftypefun 4064*e4b17023SJohn Marino 4065*e4b17023SJohn Marino@deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c}) 4066*e4b17023SJohn MarinoLike the @code{satisfies_constraint_@var{m}} functions, but the 4067*e4b17023SJohn Marinoconstraint to test is given as an argument, @var{c}. If @var{c} 4068*e4b17023SJohn Marinospecifies a register constraint, this function will always return 4069*e4b17023SJohn Marino@code{false}. 4070*e4b17023SJohn Marino@end deftypefun 4071*e4b17023SJohn Marino 4072*e4b17023SJohn Marino@deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c}) 4073*e4b17023SJohn MarinoReturns the register class associated with @var{c}. If @var{c} is not 4074*e4b17023SJohn Marinoa register constraint, or those registers are not available for the 4075*e4b17023SJohn Marinocurrently selected subtarget, returns @code{NO_REGS}. 4076*e4b17023SJohn Marino@end deftypefun 4077*e4b17023SJohn Marino 4078*e4b17023SJohn MarinoHere is an example use of @code{satisfies_constraint_@var{m}}. In 4079*e4b17023SJohn Marinopeephole optimizations (@pxref{Peephole Definitions}), operand 4080*e4b17023SJohn Marinoconstraint strings are ignored, so if there are relevant constraints, 4081*e4b17023SJohn Marinothey must be tested in the C condition. In the example, the 4082*e4b17023SJohn Marinooptimization is applied if operand 2 does @emph{not} satisfy the 4083*e4b17023SJohn Marino@samp{K} constraint. (This is a simplified version of a peephole 4084*e4b17023SJohn Marinodefinition from the i386 machine description.) 4085*e4b17023SJohn Marino 4086*e4b17023SJohn Marino@smallexample 4087*e4b17023SJohn Marino(define_peephole2 4088*e4b17023SJohn Marino [(match_scratch:SI 3 "r") 4089*e4b17023SJohn Marino (set (match_operand:SI 0 "register_operand" "") 4090*e4b17023SJohn Marino (mult:SI (match_operand:SI 1 "memory_operand" "") 4091*e4b17023SJohn Marino (match_operand:SI 2 "immediate_operand" "")))] 4092*e4b17023SJohn Marino 4093*e4b17023SJohn Marino "!satisfies_constraint_K (operands[2])" 4094*e4b17023SJohn Marino 4095*e4b17023SJohn Marino [(set (match_dup 3) (match_dup 1)) 4096*e4b17023SJohn Marino (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))] 4097*e4b17023SJohn Marino 4098*e4b17023SJohn Marino "") 4099*e4b17023SJohn Marino@end smallexample 4100*e4b17023SJohn Marino 4101*e4b17023SJohn Marino@node Standard Names 4102*e4b17023SJohn Marino@section Standard Pattern Names For Generation 4103*e4b17023SJohn Marino@cindex standard pattern names 4104*e4b17023SJohn Marino@cindex pattern names 4105*e4b17023SJohn Marino@cindex names, pattern 4106*e4b17023SJohn Marino 4107*e4b17023SJohn MarinoHere is a table of the instruction names that are meaningful in the RTL 4108*e4b17023SJohn Marinogeneration pass of the compiler. Giving one of these names to an 4109*e4b17023SJohn Marinoinstruction pattern tells the RTL generation pass that it can use the 4110*e4b17023SJohn Marinopattern to accomplish a certain task. 4111*e4b17023SJohn Marino 4112*e4b17023SJohn Marino@table @asis 4113*e4b17023SJohn Marino@cindex @code{mov@var{m}} instruction pattern 4114*e4b17023SJohn Marino@item @samp{mov@var{m}} 4115*e4b17023SJohn MarinoHere @var{m} stands for a two-letter machine mode name, in lowercase. 4116*e4b17023SJohn MarinoThis instruction pattern moves data with that machine mode from operand 4117*e4b17023SJohn Marino1 to operand 0. For example, @samp{movsi} moves full-word data. 4118*e4b17023SJohn Marino 4119*e4b17023SJohn MarinoIf operand 0 is a @code{subreg} with mode @var{m} of a register whose 4120*e4b17023SJohn Marinoown mode is wider than @var{m}, the effect of this instruction is 4121*e4b17023SJohn Marinoto store the specified value in the part of the register that corresponds 4122*e4b17023SJohn Marinoto mode @var{m}. Bits outside of @var{m}, but which are within the 4123*e4b17023SJohn Marinosame target word as the @code{subreg} are undefined. Bits which are 4124*e4b17023SJohn Marinooutside the target word are left unchanged. 4125*e4b17023SJohn Marino 4126*e4b17023SJohn MarinoThis class of patterns is special in several ways. First of all, each 4127*e4b17023SJohn Marinoof these names up to and including full word size @emph{must} be defined, 4128*e4b17023SJohn Marinobecause there is no other way to copy a datum from one place to another. 4129*e4b17023SJohn MarinoIf there are patterns accepting operands in larger modes, 4130*e4b17023SJohn Marino@samp{mov@var{m}} must be defined for integer modes of those sizes. 4131*e4b17023SJohn Marino 4132*e4b17023SJohn MarinoSecond, these patterns are not used solely in the RTL generation pass. 4133*e4b17023SJohn MarinoEven the reload pass can generate move insns to copy values from stack 4134*e4b17023SJohn Marinoslots into temporary registers. When it does so, one of the operands is 4135*e4b17023SJohn Marinoa hard register and the other is an operand that can need to be reloaded 4136*e4b17023SJohn Marinointo a register. 4137*e4b17023SJohn Marino 4138*e4b17023SJohn Marino@findex force_reg 4139*e4b17023SJohn MarinoTherefore, when given such a pair of operands, the pattern must generate 4140*e4b17023SJohn MarinoRTL which needs no reloading and needs no temporary registers---no 4141*e4b17023SJohn Marinoregisters other than the operands. For example, if you support the 4142*e4b17023SJohn Marinopattern with a @code{define_expand}, then in such a case the 4143*e4b17023SJohn Marino@code{define_expand} mustn't call @code{force_reg} or any other such 4144*e4b17023SJohn Marinofunction which might generate new pseudo registers. 4145*e4b17023SJohn Marino 4146*e4b17023SJohn MarinoThis requirement exists even for subword modes on a RISC machine where 4147*e4b17023SJohn Marinofetching those modes from memory normally requires several insns and 4148*e4b17023SJohn Marinosome temporary registers. 4149*e4b17023SJohn Marino 4150*e4b17023SJohn Marino@findex change_address 4151*e4b17023SJohn MarinoDuring reload a memory reference with an invalid address may be passed 4152*e4b17023SJohn Marinoas an operand. Such an address will be replaced with a valid address 4153*e4b17023SJohn Marinolater in the reload pass. In this case, nothing may be done with the 4154*e4b17023SJohn Marinoaddress except to use it as it stands. If it is copied, it will not be 4155*e4b17023SJohn Marinoreplaced with a valid address. No attempt should be made to make such 4156*e4b17023SJohn Marinoan address into a valid address and no routine (such as 4157*e4b17023SJohn Marino@code{change_address}) that will do so may be called. Note that 4158*e4b17023SJohn Marino@code{general_operand} will fail when applied to such an address. 4159*e4b17023SJohn Marino 4160*e4b17023SJohn Marino@findex reload_in_progress 4161*e4b17023SJohn MarinoThe global variable @code{reload_in_progress} (which must be explicitly 4162*e4b17023SJohn Marinodeclared if required) can be used to determine whether such special 4163*e4b17023SJohn Marinohandling is required. 4164*e4b17023SJohn Marino 4165*e4b17023SJohn MarinoThe variety of operands that have reloads depends on the rest of the 4166*e4b17023SJohn Marinomachine description, but typically on a RISC machine these can only be 4167*e4b17023SJohn Marinopseudo registers that did not get hard registers, while on other 4168*e4b17023SJohn Marinomachines explicit memory references will get optional reloads. 4169*e4b17023SJohn Marino 4170*e4b17023SJohn MarinoIf a scratch register is required to move an object to or from memory, 4171*e4b17023SJohn Marinoit can be allocated using @code{gen_reg_rtx} prior to life analysis. 4172*e4b17023SJohn Marino 4173*e4b17023SJohn MarinoIf there are cases which need scratch registers during or after reload, 4174*e4b17023SJohn Marinoyou must provide an appropriate secondary_reload target hook. 4175*e4b17023SJohn Marino 4176*e4b17023SJohn Marino@findex can_create_pseudo_p 4177*e4b17023SJohn MarinoThe macro @code{can_create_pseudo_p} can be used to determine if it 4178*e4b17023SJohn Marinois unsafe to create new pseudo registers. If this variable is nonzero, then 4179*e4b17023SJohn Marinoit is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo. 4180*e4b17023SJohn Marino 4181*e4b17023SJohn MarinoThe constraints on a @samp{mov@var{m}} must permit moving any hard 4182*e4b17023SJohn Marinoregister to any other hard register provided that 4183*e4b17023SJohn Marino@code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and 4184*e4b17023SJohn Marino@code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value 4185*e4b17023SJohn Marinoof 2. 4186*e4b17023SJohn Marino 4187*e4b17023SJohn MarinoIt is obligatory to support floating point @samp{mov@var{m}} 4188*e4b17023SJohn Marinoinstructions into and out of any registers that can hold fixed point 4189*e4b17023SJohn Marinovalues, because unions and structures (which have modes @code{SImode} or 4190*e4b17023SJohn Marino@code{DImode}) can be in those registers and they may have floating 4191*e4b17023SJohn Marinopoint members. 4192*e4b17023SJohn Marino 4193*e4b17023SJohn MarinoThere may also be a need to support fixed point @samp{mov@var{m}} 4194*e4b17023SJohn Marinoinstructions in and out of floating point registers. Unfortunately, I 4195*e4b17023SJohn Marinohave forgotten why this was so, and I don't know whether it is still 4196*e4b17023SJohn Marinotrue. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in 4197*e4b17023SJohn Marinofloating point registers, then the constraints of the fixed point 4198*e4b17023SJohn Marino@samp{mov@var{m}} instructions must be designed to avoid ever trying to 4199*e4b17023SJohn Marinoreload into a floating point register. 4200*e4b17023SJohn Marino 4201*e4b17023SJohn Marino@cindex @code{reload_in} instruction pattern 4202*e4b17023SJohn Marino@cindex @code{reload_out} instruction pattern 4203*e4b17023SJohn Marino@item @samp{reload_in@var{m}} 4204*e4b17023SJohn Marino@itemx @samp{reload_out@var{m}} 4205*e4b17023SJohn MarinoThese named patterns have been obsoleted by the target hook 4206*e4b17023SJohn Marino@code{secondary_reload}. 4207*e4b17023SJohn Marino 4208*e4b17023SJohn MarinoLike @samp{mov@var{m}}, but used when a scratch register is required to 4209*e4b17023SJohn Marinomove between operand 0 and operand 1. Operand 2 describes the scratch 4210*e4b17023SJohn Marinoregister. See the discussion of the @code{SECONDARY_RELOAD_CLASS} 4211*e4b17023SJohn Marinomacro in @pxref{Register Classes}. 4212*e4b17023SJohn Marino 4213*e4b17023SJohn MarinoThere are special restrictions on the form of the @code{match_operand}s 4214*e4b17023SJohn Marinoused in these patterns. First, only the predicate for the reload 4215*e4b17023SJohn Marinooperand is examined, i.e., @code{reload_in} examines operand 1, but not 4216*e4b17023SJohn Marinothe predicates for operand 0 or 2. Second, there may be only one 4217*e4b17023SJohn Marinoalternative in the constraints. Third, only a single register class 4218*e4b17023SJohn Marinoletter may be used for the constraint; subsequent constraint letters 4219*e4b17023SJohn Marinoare ignored. As a special exception, an empty constraint string 4220*e4b17023SJohn Marinomatches the @code{ALL_REGS} register class. This may relieve ports 4221*e4b17023SJohn Marinoof the burden of defining an @code{ALL_REGS} constraint letter just 4222*e4b17023SJohn Marinofor these patterns. 4223*e4b17023SJohn Marino 4224*e4b17023SJohn Marino@cindex @code{movstrict@var{m}} instruction pattern 4225*e4b17023SJohn Marino@item @samp{movstrict@var{m}} 4226*e4b17023SJohn MarinoLike @samp{mov@var{m}} except that if operand 0 is a @code{subreg} 4227*e4b17023SJohn Marinowith mode @var{m} of a register whose natural mode is wider, 4228*e4b17023SJohn Marinothe @samp{movstrict@var{m}} instruction is guaranteed not to alter 4229*e4b17023SJohn Marinoany of the register except the part which belongs to mode @var{m}. 4230*e4b17023SJohn Marino 4231*e4b17023SJohn Marino@cindex @code{movmisalign@var{m}} instruction pattern 4232*e4b17023SJohn Marino@item @samp{movmisalign@var{m}} 4233*e4b17023SJohn MarinoThis variant of a move pattern is designed to load or store a value 4234*e4b17023SJohn Marinofrom a memory address that is not naturally aligned for its mode. 4235*e4b17023SJohn MarinoFor a store, the memory will be in operand 0; for a load, the memory 4236*e4b17023SJohn Marinowill be in operand 1. The other operand is guaranteed not to be a 4237*e4b17023SJohn Marinomemory, so that it's easy to tell whether this is a load or store. 4238*e4b17023SJohn Marino 4239*e4b17023SJohn MarinoThis pattern is used by the autovectorizer, and when expanding a 4240*e4b17023SJohn Marino@code{MISALIGNED_INDIRECT_REF} expression. 4241*e4b17023SJohn Marino 4242*e4b17023SJohn Marino@cindex @code{load_multiple} instruction pattern 4243*e4b17023SJohn Marino@item @samp{load_multiple} 4244*e4b17023SJohn MarinoLoad several consecutive memory locations into consecutive registers. 4245*e4b17023SJohn MarinoOperand 0 is the first of the consecutive registers, operand 1 4246*e4b17023SJohn Marinois the first memory location, and operand 2 is a constant: the 4247*e4b17023SJohn Marinonumber of consecutive registers. 4248*e4b17023SJohn Marino 4249*e4b17023SJohn MarinoDefine this only if the target machine really has such an instruction; 4250*e4b17023SJohn Marinodo not define this if the most efficient way of loading consecutive 4251*e4b17023SJohn Marinoregisters from memory is to do them one at a time. 4252*e4b17023SJohn Marino 4253*e4b17023SJohn MarinoOn some machines, there are restrictions as to which consecutive 4254*e4b17023SJohn Marinoregisters can be stored into memory, such as particular starting or 4255*e4b17023SJohn Marinoending register numbers or only a range of valid counts. For those 4256*e4b17023SJohn Marinomachines, use a @code{define_expand} (@pxref{Expander Definitions}) 4257*e4b17023SJohn Marinoand make the pattern fail if the restrictions are not met. 4258*e4b17023SJohn Marino 4259*e4b17023SJohn MarinoWrite the generated insn as a @code{parallel} with elements being a 4260*e4b17023SJohn Marino@code{set} of one register from the appropriate memory location (you may 4261*e4b17023SJohn Marinoalso need @code{use} or @code{clobber} elements). Use a 4262*e4b17023SJohn Marino@code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See 4263*e4b17023SJohn Marino@file{rs6000.md} for examples of the use of this insn pattern. 4264*e4b17023SJohn Marino 4265*e4b17023SJohn Marino@cindex @samp{store_multiple} instruction pattern 4266*e4b17023SJohn Marino@item @samp{store_multiple} 4267*e4b17023SJohn MarinoSimilar to @samp{load_multiple}, but store several consecutive registers 4268*e4b17023SJohn Marinointo consecutive memory locations. Operand 0 is the first of the 4269*e4b17023SJohn Marinoconsecutive memory locations, operand 1 is the first register, and 4270*e4b17023SJohn Marinooperand 2 is a constant: the number of consecutive registers. 4271*e4b17023SJohn Marino 4272*e4b17023SJohn Marino@cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern 4273*e4b17023SJohn Marino@item @samp{vec_load_lanes@var{m}@var{n}} 4274*e4b17023SJohn MarinoPerform an interleaved load of several vectors from memory operand 1 4275*e4b17023SJohn Marinointo register operand 0. Both operands have mode @var{m}. The register 4276*e4b17023SJohn Marinooperand is viewed as holding consecutive vectors of mode @var{n}, 4277*e4b17023SJohn Marinowhile the memory operand is a flat array that contains the same number 4278*e4b17023SJohn Marinoof elements. The operation is equivalent to: 4279*e4b17023SJohn Marino 4280*e4b17023SJohn Marino@smallexample 4281*e4b17023SJohn Marinoint c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); 4282*e4b17023SJohn Marinofor (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) 4283*e4b17023SJohn Marino for (i = 0; i < c; i++) 4284*e4b17023SJohn Marino operand0[i][j] = operand1[j * c + i]; 4285*e4b17023SJohn Marino@end smallexample 4286*e4b17023SJohn Marino 4287*e4b17023SJohn MarinoFor example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values 4288*e4b17023SJohn Marinofrom memory into a register of mode @samp{TI}@. The register 4289*e4b17023SJohn Marinocontains two consecutive vectors of mode @samp{V4HI}@. 4290*e4b17023SJohn Marino 4291*e4b17023SJohn MarinoThis pattern can only be used if: 4292*e4b17023SJohn Marino@smallexample 4293*e4b17023SJohn MarinoTARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c}) 4294*e4b17023SJohn Marino@end smallexample 4295*e4b17023SJohn Marinois true. GCC assumes that, if a target supports this kind of 4296*e4b17023SJohn Marinoinstruction for some mode @var{n}, it also supports unaligned 4297*e4b17023SJohn Marinoloads for vectors of mode @var{n}. 4298*e4b17023SJohn Marino 4299*e4b17023SJohn Marino@cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern 4300*e4b17023SJohn Marino@item @samp{vec_store_lanes@var{m}@var{n}} 4301*e4b17023SJohn MarinoEquivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory 4302*e4b17023SJohn Marinoand register operands reversed. That is, the instruction is 4303*e4b17023SJohn Marinoequivalent to: 4304*e4b17023SJohn Marino 4305*e4b17023SJohn Marino@smallexample 4306*e4b17023SJohn Marinoint c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); 4307*e4b17023SJohn Marinofor (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) 4308*e4b17023SJohn Marino for (i = 0; i < c; i++) 4309*e4b17023SJohn Marino operand0[j * c + i] = operand1[i][j]; 4310*e4b17023SJohn Marino@end smallexample 4311*e4b17023SJohn Marino 4312*e4b17023SJohn Marinofor a memory operand 0 and register operand 1. 4313*e4b17023SJohn Marino 4314*e4b17023SJohn Marino@cindex @code{vec_set@var{m}} instruction pattern 4315*e4b17023SJohn Marino@item @samp{vec_set@var{m}} 4316*e4b17023SJohn MarinoSet given field in the vector value. Operand 0 is the vector to modify, 4317*e4b17023SJohn Marinooperand 1 is new value of field and operand 2 specify the field index. 4318*e4b17023SJohn Marino 4319*e4b17023SJohn Marino@cindex @code{vec_extract@var{m}} instruction pattern 4320*e4b17023SJohn Marino@item @samp{vec_extract@var{m}} 4321*e4b17023SJohn MarinoExtract given field from the vector value. Operand 1 is the vector, operand 2 4322*e4b17023SJohn Marinospecify field index and operand 0 place to store value into. 4323*e4b17023SJohn Marino 4324*e4b17023SJohn Marino@cindex @code{vec_init@var{m}} instruction pattern 4325*e4b17023SJohn Marino@item @samp{vec_init@var{m}} 4326*e4b17023SJohn MarinoInitialize the vector to given values. Operand 0 is the vector to initialize 4327*e4b17023SJohn Marinoand operand 1 is parallel containing values for individual fields. 4328*e4b17023SJohn Marino 4329*e4b17023SJohn Marino@cindex @code{vcond@var{m}@var{n}} instruction pattern 4330*e4b17023SJohn Marino@item @samp{vcond@var{m}@var{n}} 4331*e4b17023SJohn MarinoOutput a conditional vector move. Operand 0 is the destination to 4332*e4b17023SJohn Marinoreceive a combination of operand 1 and operand 2, which are of mode @var{m}, 4333*e4b17023SJohn Marinodependent on the outcome of the predicate in operand 3 which is a 4334*e4b17023SJohn Marinovector comparison with operands of mode @var{n} in operands 4 and 5. The 4335*e4b17023SJohn Marinomodes @var{m} and @var{n} should have the same size. Operand 0 4336*e4b17023SJohn Marinowill be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk} 4337*e4b17023SJohn Marinowhere @var{msk} is computed by element-wise evaluation of the vector 4338*e4b17023SJohn Marinocomparison with a truth value of all-ones and a false value of all-zeros. 4339*e4b17023SJohn Marino 4340*e4b17023SJohn Marino@cindex @code{vec_perm@var{m}} instruction pattern 4341*e4b17023SJohn Marino@item @samp{vec_perm@var{m}} 4342*e4b17023SJohn MarinoOutput a (variable) vector permutation. Operand 0 is the destination 4343*e4b17023SJohn Marinoto receive elements from operand 1 and operand 2, which are of mode 4344*e4b17023SJohn Marino@var{m}. Operand 3 is the @dfn{selector}. It is an integral mode 4345*e4b17023SJohn Marinovector of the same width and number of elements as mode @var{m}. 4346*e4b17023SJohn Marino 4347*e4b17023SJohn MarinoThe input elements are numbered from 0 in operand 1 through 4348*e4b17023SJohn Marino@math{2*@var{N}-1} in operand 2. The elements of the selector must 4349*e4b17023SJohn Marinobe computed modulo @math{2*@var{N}}. Note that if 4350*e4b17023SJohn Marino@code{rtx_equal_p(operand1, operand2)}, this can be implemented 4351*e4b17023SJohn Marinowith just operand 1 and selector elements modulo @var{N}. 4352*e4b17023SJohn Marino 4353*e4b17023SJohn MarinoIn order to make things easy for a number of targets, if there is no 4354*e4b17023SJohn Marino@samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q} 4355*e4b17023SJohn Marinowhere @var{q} is a vector of @code{QImode} of the same width as @var{m}, 4356*e4b17023SJohn Marinothe middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to 4357*e4b17023SJohn Marinomode @var{q}. 4358*e4b17023SJohn Marino 4359*e4b17023SJohn Marino@cindex @code{vec_perm_const@var{m}} instruction pattern 4360*e4b17023SJohn Marino@item @samp{vec_perm_const@var{m}} 4361*e4b17023SJohn MarinoLike @samp{vec_perm} except that the permutation is a compile-time 4362*e4b17023SJohn Marinoconstant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}. 4363*e4b17023SJohn Marino 4364*e4b17023SJohn MarinoSome targets cannot perform a permutation with a variable selector, 4365*e4b17023SJohn Marinobut can efficiently perform a constant permutation. Further, the 4366*e4b17023SJohn Marinotarget hook @code{vec_perm_ok} is queried to determine if the 4367*e4b17023SJohn Marinospecific constant permutation is available efficiently; the named 4368*e4b17023SJohn Marinopattern is never expanded without @code{vec_perm_ok} returning true. 4369*e4b17023SJohn Marino 4370*e4b17023SJohn MarinoThere is no need for a target to supply both @samp{vec_perm@var{m}} 4371*e4b17023SJohn Marinoand @samp{vec_perm_const@var{m}} if the former can trivially implement 4372*e4b17023SJohn Marinothe operation with, say, the vector constant loaded into a register. 4373*e4b17023SJohn Marino 4374*e4b17023SJohn Marino@cindex @code{push@var{m}1} instruction pattern 4375*e4b17023SJohn Marino@item @samp{push@var{m}1} 4376*e4b17023SJohn MarinoOutput a push instruction. Operand 0 is value to push. Used only when 4377*e4b17023SJohn Marino@code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be 4378*e4b17023SJohn Marinomissing and in such case an @code{mov} expander is used instead, with a 4379*e4b17023SJohn Marino@code{MEM} expression forming the push operation. The @code{mov} expander 4380*e4b17023SJohn Marinomethod is deprecated. 4381*e4b17023SJohn Marino 4382*e4b17023SJohn Marino@cindex @code{add@var{m}3} instruction pattern 4383*e4b17023SJohn Marino@item @samp{add@var{m}3} 4384*e4b17023SJohn MarinoAdd operand 2 and operand 1, storing the result in operand 0. All operands 4385*e4b17023SJohn Marinomust have mode @var{m}. This can be used even on two-address machines, by 4386*e4b17023SJohn Marinomeans of constraints requiring operands 1 and 0 to be the same location. 4387*e4b17023SJohn Marino 4388*e4b17023SJohn Marino@cindex @code{ssadd@var{m}3} instruction pattern 4389*e4b17023SJohn Marino@cindex @code{usadd@var{m}3} instruction pattern 4390*e4b17023SJohn Marino@cindex @code{sub@var{m}3} instruction pattern 4391*e4b17023SJohn Marino@cindex @code{sssub@var{m}3} instruction pattern 4392*e4b17023SJohn Marino@cindex @code{ussub@var{m}3} instruction pattern 4393*e4b17023SJohn Marino@cindex @code{mul@var{m}3} instruction pattern 4394*e4b17023SJohn Marino@cindex @code{ssmul@var{m}3} instruction pattern 4395*e4b17023SJohn Marino@cindex @code{usmul@var{m}3} instruction pattern 4396*e4b17023SJohn Marino@cindex @code{div@var{m}3} instruction pattern 4397*e4b17023SJohn Marino@cindex @code{ssdiv@var{m}3} instruction pattern 4398*e4b17023SJohn Marino@cindex @code{udiv@var{m}3} instruction pattern 4399*e4b17023SJohn Marino@cindex @code{usdiv@var{m}3} instruction pattern 4400*e4b17023SJohn Marino@cindex @code{mod@var{m}3} instruction pattern 4401*e4b17023SJohn Marino@cindex @code{umod@var{m}3} instruction pattern 4402*e4b17023SJohn Marino@cindex @code{umin@var{m}3} instruction pattern 4403*e4b17023SJohn Marino@cindex @code{umax@var{m}3} instruction pattern 4404*e4b17023SJohn Marino@cindex @code{and@var{m}3} instruction pattern 4405*e4b17023SJohn Marino@cindex @code{ior@var{m}3} instruction pattern 4406*e4b17023SJohn Marino@cindex @code{xor@var{m}3} instruction pattern 4407*e4b17023SJohn Marino@item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3} 4408*e4b17023SJohn Marino@item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3} 4409*e4b17023SJohn Marino@item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3} 4410*e4b17023SJohn Marino@itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3} 4411*e4b17023SJohn Marino@itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3} 4412*e4b17023SJohn Marino@itemx @samp{mod@var{m}3}, @samp{umod@var{m}3} 4413*e4b17023SJohn Marino@itemx @samp{umin@var{m}3}, @samp{umax@var{m}3} 4414*e4b17023SJohn Marino@itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} 4415*e4b17023SJohn MarinoSimilar, for other arithmetic operations. 4416*e4b17023SJohn Marino 4417*e4b17023SJohn Marino@cindex @code{fma@var{m}4} instruction pattern 4418*e4b17023SJohn Marino@item @samp{fma@var{m}4} 4419*e4b17023SJohn MarinoMultiply operand 2 and operand 1, then add operand 3, storing the 4420*e4b17023SJohn Marinoresult in operand 0. All operands must have mode @var{m}. This 4421*e4b17023SJohn Marinopattern is used to implement the @code{fma}, @code{fmaf}, and 4422*e4b17023SJohn Marino@code{fmal} builtin functions from the ISO C99 standard. The 4423*e4b17023SJohn Marino@code{fma} operation may produce different results than doing the 4424*e4b17023SJohn Marinomultiply followed by the add if the machine does not perform a 4425*e4b17023SJohn Marinorounding step between the operations. 4426*e4b17023SJohn Marino 4427*e4b17023SJohn Marino@cindex @code{fms@var{m}4} instruction pattern 4428*e4b17023SJohn Marino@item @samp{fms@var{m}4} 4429*e4b17023SJohn MarinoLike @code{fma@var{m}4}, except operand 3 subtracted from the 4430*e4b17023SJohn Marinoproduct instead of added to the product. This is represented 4431*e4b17023SJohn Marinoin the rtl as 4432*e4b17023SJohn Marino 4433*e4b17023SJohn Marino@smallexample 4434*e4b17023SJohn Marino(fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3})) 4435*e4b17023SJohn Marino@end smallexample 4436*e4b17023SJohn Marino 4437*e4b17023SJohn Marino@cindex @code{fnma@var{m}4} instruction pattern 4438*e4b17023SJohn Marino@item @samp{fnma@var{m}4} 4439*e4b17023SJohn MarinoLike @code{fma@var{m}4} except that the intermediate product 4440*e4b17023SJohn Marinois negated before being added to operand 3. This is represented 4441*e4b17023SJohn Marinoin the rtl as 4442*e4b17023SJohn Marino 4443*e4b17023SJohn Marino@smallexample 4444*e4b17023SJohn Marino(fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3}) 4445*e4b17023SJohn Marino@end smallexample 4446*e4b17023SJohn Marino 4447*e4b17023SJohn Marino@cindex @code{fnms@var{m}4} instruction pattern 4448*e4b17023SJohn Marino@item @samp{fnms@var{m}4} 4449*e4b17023SJohn MarinoLike @code{fms@var{m}4} except that the intermediate product 4450*e4b17023SJohn Marinois negated before subtracting operand 3. This is represented 4451*e4b17023SJohn Marinoin the rtl as 4452*e4b17023SJohn Marino 4453*e4b17023SJohn Marino@smallexample 4454*e4b17023SJohn Marino(fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3})) 4455*e4b17023SJohn Marino@end smallexample 4456*e4b17023SJohn Marino 4457*e4b17023SJohn Marino@cindex @code{min@var{m}3} instruction pattern 4458*e4b17023SJohn Marino@cindex @code{max@var{m}3} instruction pattern 4459*e4b17023SJohn Marino@item @samp{smin@var{m}3}, @samp{smax@var{m}3} 4460*e4b17023SJohn MarinoSigned minimum and maximum operations. When used with floating point, 4461*e4b17023SJohn Marinoif both operands are zeros, or if either operand is @code{NaN}, then 4462*e4b17023SJohn Marinoit is unspecified which of the two operands is returned as the result. 4463*e4b17023SJohn Marino 4464*e4b17023SJohn Marino@cindex @code{reduc_smin_@var{m}} instruction pattern 4465*e4b17023SJohn Marino@cindex @code{reduc_smax_@var{m}} instruction pattern 4466*e4b17023SJohn Marino@item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}} 4467*e4b17023SJohn MarinoFind the signed minimum/maximum of the elements of a vector. The vector is 4468*e4b17023SJohn Marinooperand 1, and the scalar result is stored in the least significant bits of 4469*e4b17023SJohn Marinooperand 0 (also a vector). The output and input vector should have the same 4470*e4b17023SJohn Marinomodes. 4471*e4b17023SJohn Marino 4472*e4b17023SJohn Marino@cindex @code{reduc_umin_@var{m}} instruction pattern 4473*e4b17023SJohn Marino@cindex @code{reduc_umax_@var{m}} instruction pattern 4474*e4b17023SJohn Marino@item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}} 4475*e4b17023SJohn MarinoFind the unsigned minimum/maximum of the elements of a vector. The vector is 4476*e4b17023SJohn Marinooperand 1, and the scalar result is stored in the least significant bits of 4477*e4b17023SJohn Marinooperand 0 (also a vector). The output and input vector should have the same 4478*e4b17023SJohn Marinomodes. 4479*e4b17023SJohn Marino 4480*e4b17023SJohn Marino@cindex @code{reduc_splus_@var{m}} instruction pattern 4481*e4b17023SJohn Marino@item @samp{reduc_splus_@var{m}} 4482*e4b17023SJohn MarinoCompute the sum of the signed elements of a vector. The vector is operand 1, 4483*e4b17023SJohn Marinoand the scalar result is stored in the least significant bits of operand 0 4484*e4b17023SJohn Marino(also a vector). The output and input vector should have the same modes. 4485*e4b17023SJohn Marino 4486*e4b17023SJohn Marino@cindex @code{reduc_uplus_@var{m}} instruction pattern 4487*e4b17023SJohn Marino@item @samp{reduc_uplus_@var{m}} 4488*e4b17023SJohn MarinoCompute the sum of the unsigned elements of a vector. The vector is operand 1, 4489*e4b17023SJohn Marinoand the scalar result is stored in the least significant bits of operand 0 4490*e4b17023SJohn Marino(also a vector). The output and input vector should have the same modes. 4491*e4b17023SJohn Marino 4492*e4b17023SJohn Marino@cindex @code{sdot_prod@var{m}} instruction pattern 4493*e4b17023SJohn Marino@item @samp{sdot_prod@var{m}} 4494*e4b17023SJohn Marino@cindex @code{udot_prod@var{m}} instruction pattern 4495*e4b17023SJohn Marino@item @samp{udot_prod@var{m}} 4496*e4b17023SJohn MarinoCompute the sum of the products of two signed/unsigned elements. 4497*e4b17023SJohn MarinoOperand 1 and operand 2 are of the same mode. Their product, which is of a 4498*e4b17023SJohn Marinowider mode, is computed and added to operand 3. Operand 3 is of a mode equal or 4499*e4b17023SJohn Marinowider than the mode of the product. The result is placed in operand 0, which 4500*e4b17023SJohn Marinois of the same mode as operand 3. 4501*e4b17023SJohn Marino 4502*e4b17023SJohn Marino@cindex @code{ssum_widen@var{m3}} instruction pattern 4503*e4b17023SJohn Marino@item @samp{ssum_widen@var{m3}} 4504*e4b17023SJohn Marino@cindex @code{usum_widen@var{m3}} instruction pattern 4505*e4b17023SJohn Marino@item @samp{usum_widen@var{m3}} 4506*e4b17023SJohn MarinoOperands 0 and 2 are of the same mode, which is wider than the mode of 4507*e4b17023SJohn Marinooperand 1. Add operand 1 to operand 2 and place the widened result in 4508*e4b17023SJohn Marinooperand 0. (This is used express accumulation of elements into an accumulator 4509*e4b17023SJohn Marinoof a wider mode.) 4510*e4b17023SJohn Marino 4511*e4b17023SJohn Marino@cindex @code{vec_shl_@var{m}} instruction pattern 4512*e4b17023SJohn Marino@cindex @code{vec_shr_@var{m}} instruction pattern 4513*e4b17023SJohn Marino@item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}} 4514*e4b17023SJohn MarinoWhole vector left/right shift in bits. 4515*e4b17023SJohn MarinoOperand 1 is a vector to be shifted. 4516*e4b17023SJohn MarinoOperand 2 is an integer shift amount in bits. 4517*e4b17023SJohn MarinoOperand 0 is where the resulting shifted vector is stored. 4518*e4b17023SJohn MarinoThe output and input vectors should have the same modes. 4519*e4b17023SJohn Marino 4520*e4b17023SJohn Marino@cindex @code{vec_pack_trunc_@var{m}} instruction pattern 4521*e4b17023SJohn Marino@item @samp{vec_pack_trunc_@var{m}} 4522*e4b17023SJohn MarinoNarrow (demote) and merge the elements of two vectors. Operands 1 and 2 4523*e4b17023SJohn Marinoare vectors of the same mode having N integral or floating point elements 4524*e4b17023SJohn Marinoof size S@. Operand 0 is the resulting vector in which 2*N elements of 4525*e4b17023SJohn Marinosize N/2 are concatenated after narrowing them down using truncation. 4526*e4b17023SJohn Marino 4527*e4b17023SJohn Marino@cindex @code{vec_pack_ssat_@var{m}} instruction pattern 4528*e4b17023SJohn Marino@cindex @code{vec_pack_usat_@var{m}} instruction pattern 4529*e4b17023SJohn Marino@item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}} 4530*e4b17023SJohn MarinoNarrow (demote) and merge the elements of two vectors. Operands 1 and 2 4531*e4b17023SJohn Marinoare vectors of the same mode having N integral elements of size S. 4532*e4b17023SJohn MarinoOperand 0 is the resulting vector in which the elements of the two input 4533*e4b17023SJohn Marinovectors are concatenated after narrowing them down using signed/unsigned 4534*e4b17023SJohn Marinosaturating arithmetic. 4535*e4b17023SJohn Marino 4536*e4b17023SJohn Marino@cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern 4537*e4b17023SJohn Marino@cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern 4538*e4b17023SJohn Marino@item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}} 4539*e4b17023SJohn MarinoNarrow, convert to signed/unsigned integral type and merge the elements 4540*e4b17023SJohn Marinoof two vectors. Operands 1 and 2 are vectors of the same mode having N 4541*e4b17023SJohn Marinofloating point elements of size S@. Operand 0 is the resulting vector 4542*e4b17023SJohn Marinoin which 2*N elements of size N/2 are concatenated. 4543*e4b17023SJohn Marino 4544*e4b17023SJohn Marino@cindex @code{vec_unpacks_hi_@var{m}} instruction pattern 4545*e4b17023SJohn Marino@cindex @code{vec_unpacks_lo_@var{m}} instruction pattern 4546*e4b17023SJohn Marino@item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}} 4547*e4b17023SJohn MarinoExtract and widen (promote) the high/low part of a vector of signed 4548*e4b17023SJohn Marinointegral or floating point elements. The input vector (operand 1) has N 4549*e4b17023SJohn Marinoelements of size S@. Widen (promote) the high/low elements of the vector 4550*e4b17023SJohn Marinousing signed or floating point extension and place the resulting N/2 4551*e4b17023SJohn Marinovalues of size 2*S in the output vector (operand 0). 4552*e4b17023SJohn Marino 4553*e4b17023SJohn Marino@cindex @code{vec_unpacku_hi_@var{m}} instruction pattern 4554*e4b17023SJohn Marino@cindex @code{vec_unpacku_lo_@var{m}} instruction pattern 4555*e4b17023SJohn Marino@item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}} 4556*e4b17023SJohn MarinoExtract and widen (promote) the high/low part of a vector of unsigned 4557*e4b17023SJohn Marinointegral elements. The input vector (operand 1) has N elements of size S. 4558*e4b17023SJohn MarinoWiden (promote) the high/low elements of the vector using zero extension and 4559*e4b17023SJohn Marinoplace the resulting N/2 values of size 2*S in the output vector (operand 0). 4560*e4b17023SJohn Marino 4561*e4b17023SJohn Marino@cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern 4562*e4b17023SJohn Marino@cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern 4563*e4b17023SJohn Marino@cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern 4564*e4b17023SJohn Marino@cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern 4565*e4b17023SJohn Marino@item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}} 4566*e4b17023SJohn Marino@itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}} 4567*e4b17023SJohn MarinoExtract, convert to floating point type and widen the high/low part of a 4568*e4b17023SJohn Marinovector of signed/unsigned integral elements. The input vector (operand 1) 4569*e4b17023SJohn Marinohas N elements of size S@. Convert the high/low elements of the vector using 4570*e4b17023SJohn Marinofloating point conversion and place the resulting N/2 values of size 2*S in 4571*e4b17023SJohn Marinothe output vector (operand 0). 4572*e4b17023SJohn Marino 4573*e4b17023SJohn Marino@cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern 4574*e4b17023SJohn Marino@cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern 4575*e4b17023SJohn Marino@cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern 4576*e4b17023SJohn Marino@cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern 4577*e4b17023SJohn Marino@item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}} 4578*e4b17023SJohn Marino@itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}} 4579*e4b17023SJohn MarinoSigned/Unsigned widening multiplication. The two inputs (operands 1 and 2) 4580*e4b17023SJohn Marinoare vectors with N signed/unsigned elements of size S@. Multiply the high/low 4581*e4b17023SJohn Marinoelements of the two vectors, and put the N/2 products of size 2*S in the 4582*e4b17023SJohn Marinooutput vector (operand 0). 4583*e4b17023SJohn Marino 4584*e4b17023SJohn Marino@cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern 4585*e4b17023SJohn Marino@cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern 4586*e4b17023SJohn Marino@cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern 4587*e4b17023SJohn Marino@cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern 4588*e4b17023SJohn Marino@item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}} 4589*e4b17023SJohn Marino@itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}} 4590*e4b17023SJohn MarinoSigned/Unsigned widening shift left. The first input (operand 1) is a vector 4591*e4b17023SJohn Marinowith N signed/unsigned elements of size S@. Operand 2 is a constant. Shift 4592*e4b17023SJohn Marinothe high/low elements of operand 1, and put the N/2 results of size 2*S in the 4593*e4b17023SJohn Marinooutput vector (operand 0). 4594*e4b17023SJohn Marino 4595*e4b17023SJohn Marino@cindex @code{mulhisi3} instruction pattern 4596*e4b17023SJohn Marino@item @samp{mulhisi3} 4597*e4b17023SJohn MarinoMultiply operands 1 and 2, which have mode @code{HImode}, and store 4598*e4b17023SJohn Marinoa @code{SImode} product in operand 0. 4599*e4b17023SJohn Marino 4600*e4b17023SJohn Marino@cindex @code{mulqihi3} instruction pattern 4601*e4b17023SJohn Marino@cindex @code{mulsidi3} instruction pattern 4602*e4b17023SJohn Marino@item @samp{mulqihi3}, @samp{mulsidi3} 4603*e4b17023SJohn MarinoSimilar widening-multiplication instructions of other widths. 4604*e4b17023SJohn Marino 4605*e4b17023SJohn Marino@cindex @code{umulqihi3} instruction pattern 4606*e4b17023SJohn Marino@cindex @code{umulhisi3} instruction pattern 4607*e4b17023SJohn Marino@cindex @code{umulsidi3} instruction pattern 4608*e4b17023SJohn Marino@item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3} 4609*e4b17023SJohn MarinoSimilar widening-multiplication instructions that do unsigned 4610*e4b17023SJohn Marinomultiplication. 4611*e4b17023SJohn Marino 4612*e4b17023SJohn Marino@cindex @code{usmulqihi3} instruction pattern 4613*e4b17023SJohn Marino@cindex @code{usmulhisi3} instruction pattern 4614*e4b17023SJohn Marino@cindex @code{usmulsidi3} instruction pattern 4615*e4b17023SJohn Marino@item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3} 4616*e4b17023SJohn MarinoSimilar widening-multiplication instructions that interpret the first 4617*e4b17023SJohn Marinooperand as unsigned and the second operand as signed, then do a signed 4618*e4b17023SJohn Marinomultiplication. 4619*e4b17023SJohn Marino 4620*e4b17023SJohn Marino@cindex @code{smul@var{m}3_highpart} instruction pattern 4621*e4b17023SJohn Marino@item @samp{smul@var{m}3_highpart} 4622*e4b17023SJohn MarinoPerform a signed multiplication of operands 1 and 2, which have mode 4623*e4b17023SJohn Marino@var{m}, and store the most significant half of the product in operand 0. 4624*e4b17023SJohn MarinoThe least significant half of the product is discarded. 4625*e4b17023SJohn Marino 4626*e4b17023SJohn Marino@cindex @code{umul@var{m}3_highpart} instruction pattern 4627*e4b17023SJohn Marino@item @samp{umul@var{m}3_highpart} 4628*e4b17023SJohn MarinoSimilar, but the multiplication is unsigned. 4629*e4b17023SJohn Marino 4630*e4b17023SJohn Marino@cindex @code{madd@var{m}@var{n}4} instruction pattern 4631*e4b17023SJohn Marino@item @samp{madd@var{m}@var{n}4} 4632*e4b17023SJohn MarinoMultiply operands 1 and 2, sign-extend them to mode @var{n}, add 4633*e4b17023SJohn Marinooperand 3, and store the result in operand 0. Operands 1 and 2 4634*e4b17023SJohn Marinohave mode @var{m} and operands 0 and 3 have mode @var{n}. 4635*e4b17023SJohn MarinoBoth modes must be integer or fixed-point modes and @var{n} must be twice 4636*e4b17023SJohn Marinothe size of @var{m}. 4637*e4b17023SJohn Marino 4638*e4b17023SJohn MarinoIn other words, @code{madd@var{m}@var{n}4} is like 4639*e4b17023SJohn Marino@code{mul@var{m}@var{n}3} except that it also adds operand 3. 4640*e4b17023SJohn Marino 4641*e4b17023SJohn MarinoThese instructions are not allowed to @code{FAIL}. 4642*e4b17023SJohn Marino 4643*e4b17023SJohn Marino@cindex @code{umadd@var{m}@var{n}4} instruction pattern 4644*e4b17023SJohn Marino@item @samp{umadd@var{m}@var{n}4} 4645*e4b17023SJohn MarinoLike @code{madd@var{m}@var{n}4}, but zero-extend the multiplication 4646*e4b17023SJohn Marinooperands instead of sign-extending them. 4647*e4b17023SJohn Marino 4648*e4b17023SJohn Marino@cindex @code{ssmadd@var{m}@var{n}4} instruction pattern 4649*e4b17023SJohn Marino@item @samp{ssmadd@var{m}@var{n}4} 4650*e4b17023SJohn MarinoLike @code{madd@var{m}@var{n}4}, but all involved operations must be 4651*e4b17023SJohn Marinosigned-saturating. 4652*e4b17023SJohn Marino 4653*e4b17023SJohn Marino@cindex @code{usmadd@var{m}@var{n}4} instruction pattern 4654*e4b17023SJohn Marino@item @samp{usmadd@var{m}@var{n}4} 4655*e4b17023SJohn MarinoLike @code{umadd@var{m}@var{n}4}, but all involved operations must be 4656*e4b17023SJohn Marinounsigned-saturating. 4657*e4b17023SJohn Marino 4658*e4b17023SJohn Marino@cindex @code{msub@var{m}@var{n}4} instruction pattern 4659*e4b17023SJohn Marino@item @samp{msub@var{m}@var{n}4} 4660*e4b17023SJohn MarinoMultiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the 4661*e4b17023SJohn Marinoresult from operand 3, and store the result in operand 0. Operands 1 and 2 4662*e4b17023SJohn Marinohave mode @var{m} and operands 0 and 3 have mode @var{n}. 4663*e4b17023SJohn MarinoBoth modes must be integer or fixed-point modes and @var{n} must be twice 4664*e4b17023SJohn Marinothe size of @var{m}. 4665*e4b17023SJohn Marino 4666*e4b17023SJohn MarinoIn other words, @code{msub@var{m}@var{n}4} is like 4667*e4b17023SJohn Marino@code{mul@var{m}@var{n}3} except that it also subtracts the result 4668*e4b17023SJohn Marinofrom operand 3. 4669*e4b17023SJohn Marino 4670*e4b17023SJohn MarinoThese instructions are not allowed to @code{FAIL}. 4671*e4b17023SJohn Marino 4672*e4b17023SJohn Marino@cindex @code{umsub@var{m}@var{n}4} instruction pattern 4673*e4b17023SJohn Marino@item @samp{umsub@var{m}@var{n}4} 4674*e4b17023SJohn MarinoLike @code{msub@var{m}@var{n}4}, but zero-extend the multiplication 4675*e4b17023SJohn Marinooperands instead of sign-extending them. 4676*e4b17023SJohn Marino 4677*e4b17023SJohn Marino@cindex @code{ssmsub@var{m}@var{n}4} instruction pattern 4678*e4b17023SJohn Marino@item @samp{ssmsub@var{m}@var{n}4} 4679*e4b17023SJohn MarinoLike @code{msub@var{m}@var{n}4}, but all involved operations must be 4680*e4b17023SJohn Marinosigned-saturating. 4681*e4b17023SJohn Marino 4682*e4b17023SJohn Marino@cindex @code{usmsub@var{m}@var{n}4} instruction pattern 4683*e4b17023SJohn Marino@item @samp{usmsub@var{m}@var{n}4} 4684*e4b17023SJohn MarinoLike @code{umsub@var{m}@var{n}4}, but all involved operations must be 4685*e4b17023SJohn Marinounsigned-saturating. 4686*e4b17023SJohn Marino 4687*e4b17023SJohn Marino@cindex @code{divmod@var{m}4} instruction pattern 4688*e4b17023SJohn Marino@item @samp{divmod@var{m}4} 4689*e4b17023SJohn MarinoSigned division that produces both a quotient and a remainder. 4690*e4b17023SJohn MarinoOperand 1 is divided by operand 2 to produce a quotient stored 4691*e4b17023SJohn Marinoin operand 0 and a remainder stored in operand 3. 4692*e4b17023SJohn Marino 4693*e4b17023SJohn MarinoFor machines with an instruction that produces both a quotient and a 4694*e4b17023SJohn Marinoremainder, provide a pattern for @samp{divmod@var{m}4} but do not 4695*e4b17023SJohn Marinoprovide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This 4696*e4b17023SJohn Marinoallows optimization in the relatively common case when both the quotient 4697*e4b17023SJohn Marinoand remainder are computed. 4698*e4b17023SJohn Marino 4699*e4b17023SJohn MarinoIf an instruction that just produces a quotient or just a remainder 4700*e4b17023SJohn Marinoexists and is more efficient than the instruction that produces both, 4701*e4b17023SJohn Marinowrite the output routine of @samp{divmod@var{m}4} to call 4702*e4b17023SJohn Marino@code{find_reg_note} and look for a @code{REG_UNUSED} note on the 4703*e4b17023SJohn Marinoquotient or remainder and generate the appropriate instruction. 4704*e4b17023SJohn Marino 4705*e4b17023SJohn Marino@cindex @code{udivmod@var{m}4} instruction pattern 4706*e4b17023SJohn Marino@item @samp{udivmod@var{m}4} 4707*e4b17023SJohn MarinoSimilar, but does unsigned division. 4708*e4b17023SJohn Marino 4709*e4b17023SJohn Marino@anchor{shift patterns} 4710*e4b17023SJohn Marino@cindex @code{ashl@var{m}3} instruction pattern 4711*e4b17023SJohn Marino@cindex @code{ssashl@var{m}3} instruction pattern 4712*e4b17023SJohn Marino@cindex @code{usashl@var{m}3} instruction pattern 4713*e4b17023SJohn Marino@item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3} 4714*e4b17023SJohn MarinoArithmetic-shift operand 1 left by a number of bits specified by operand 4715*e4b17023SJohn Marino2, and store the result in operand 0. Here @var{m} is the mode of 4716*e4b17023SJohn Marinooperand 0 and operand 1; operand 2's mode is specified by the 4717*e4b17023SJohn Marinoinstruction pattern, and the compiler will convert the operand to that 4718*e4b17023SJohn Marinomode before generating the instruction. The meaning of out-of-range shift 4719*e4b17023SJohn Marinocounts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}. 4720*e4b17023SJohn Marino@xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type. 4721*e4b17023SJohn Marino 4722*e4b17023SJohn Marino@cindex @code{ashr@var{m}3} instruction pattern 4723*e4b17023SJohn Marino@cindex @code{lshr@var{m}3} instruction pattern 4724*e4b17023SJohn Marino@cindex @code{rotl@var{m}3} instruction pattern 4725*e4b17023SJohn Marino@cindex @code{rotr@var{m}3} instruction pattern 4726*e4b17023SJohn Marino@item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3} 4727*e4b17023SJohn MarinoOther shift and rotate instructions, analogous to the 4728*e4b17023SJohn Marino@code{ashl@var{m}3} instructions. Operand 2 is always a scalar type. 4729*e4b17023SJohn Marino 4730*e4b17023SJohn Marino@cindex @code{vashl@var{m}3} instruction pattern 4731*e4b17023SJohn Marino@cindex @code{vashr@var{m}3} instruction pattern 4732*e4b17023SJohn Marino@cindex @code{vlshr@var{m}3} instruction pattern 4733*e4b17023SJohn Marino@cindex @code{vrotl@var{m}3} instruction pattern 4734*e4b17023SJohn Marino@cindex @code{vrotr@var{m}3} instruction pattern 4735*e4b17023SJohn Marino@item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3} 4736*e4b17023SJohn MarinoVector shift and rotate instructions that take vectors as operand 2 4737*e4b17023SJohn Marinoinstead of a scalar type. 4738*e4b17023SJohn Marino 4739*e4b17023SJohn Marino@cindex @code{neg@var{m}2} instruction pattern 4740*e4b17023SJohn Marino@cindex @code{ssneg@var{m}2} instruction pattern 4741*e4b17023SJohn Marino@cindex @code{usneg@var{m}2} instruction pattern 4742*e4b17023SJohn Marino@item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2} 4743*e4b17023SJohn MarinoNegate operand 1 and store the result in operand 0. 4744*e4b17023SJohn Marino 4745*e4b17023SJohn Marino@cindex @code{abs@var{m}2} instruction pattern 4746*e4b17023SJohn Marino@item @samp{abs@var{m}2} 4747*e4b17023SJohn MarinoStore the absolute value of operand 1 into operand 0. 4748*e4b17023SJohn Marino 4749*e4b17023SJohn Marino@cindex @code{sqrt@var{m}2} instruction pattern 4750*e4b17023SJohn Marino@item @samp{sqrt@var{m}2} 4751*e4b17023SJohn MarinoStore the square root of operand 1 into operand 0. 4752*e4b17023SJohn Marino 4753*e4b17023SJohn MarinoThe @code{sqrt} built-in function of C always uses the mode which 4754*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{sqrtf} 4755*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4756*e4b17023SJohn Marinotype @code{float}. 4757*e4b17023SJohn Marino 4758*e4b17023SJohn Marino@cindex @code{fmod@var{m}3} instruction pattern 4759*e4b17023SJohn Marino@item @samp{fmod@var{m}3} 4760*e4b17023SJohn MarinoStore the remainder of dividing operand 1 by operand 2 into 4761*e4b17023SJohn Marinooperand 0, rounded towards zero to an integer. 4762*e4b17023SJohn Marino 4763*e4b17023SJohn MarinoThe @code{fmod} built-in function of C always uses the mode which 4764*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{fmodf} 4765*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4766*e4b17023SJohn Marinotype @code{float}. 4767*e4b17023SJohn Marino 4768*e4b17023SJohn Marino@cindex @code{remainder@var{m}3} instruction pattern 4769*e4b17023SJohn Marino@item @samp{remainder@var{m}3} 4770*e4b17023SJohn MarinoStore the remainder of dividing operand 1 by operand 2 into 4771*e4b17023SJohn Marinooperand 0, rounded to the nearest integer. 4772*e4b17023SJohn Marino 4773*e4b17023SJohn MarinoThe @code{remainder} built-in function of C always uses the mode 4774*e4b17023SJohn Marinowhich corresponds to the C data type @code{double} and the 4775*e4b17023SJohn Marino@code{remainderf} built-in function uses the mode which corresponds 4776*e4b17023SJohn Marinoto the C data type @code{float}. 4777*e4b17023SJohn Marino 4778*e4b17023SJohn Marino@cindex @code{cos@var{m}2} instruction pattern 4779*e4b17023SJohn Marino@item @samp{cos@var{m}2} 4780*e4b17023SJohn MarinoStore the cosine of operand 1 into operand 0. 4781*e4b17023SJohn Marino 4782*e4b17023SJohn MarinoThe @code{cos} built-in function of C always uses the mode which 4783*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{cosf} 4784*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4785*e4b17023SJohn Marinotype @code{float}. 4786*e4b17023SJohn Marino 4787*e4b17023SJohn Marino@cindex @code{sin@var{m}2} instruction pattern 4788*e4b17023SJohn Marino@item @samp{sin@var{m}2} 4789*e4b17023SJohn MarinoStore the sine of operand 1 into operand 0. 4790*e4b17023SJohn Marino 4791*e4b17023SJohn MarinoThe @code{sin} built-in function of C always uses the mode which 4792*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{sinf} 4793*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4794*e4b17023SJohn Marinotype @code{float}. 4795*e4b17023SJohn Marino 4796*e4b17023SJohn Marino@cindex @code{exp@var{m}2} instruction pattern 4797*e4b17023SJohn Marino@item @samp{exp@var{m}2} 4798*e4b17023SJohn MarinoStore the exponential of operand 1 into operand 0. 4799*e4b17023SJohn Marino 4800*e4b17023SJohn MarinoThe @code{exp} built-in function of C always uses the mode which 4801*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{expf} 4802*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4803*e4b17023SJohn Marinotype @code{float}. 4804*e4b17023SJohn Marino 4805*e4b17023SJohn Marino@cindex @code{log@var{m}2} instruction pattern 4806*e4b17023SJohn Marino@item @samp{log@var{m}2} 4807*e4b17023SJohn MarinoStore the natural logarithm of operand 1 into operand 0. 4808*e4b17023SJohn Marino 4809*e4b17023SJohn MarinoThe @code{log} built-in function of C always uses the mode which 4810*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{logf} 4811*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4812*e4b17023SJohn Marinotype @code{float}. 4813*e4b17023SJohn Marino 4814*e4b17023SJohn Marino@cindex @code{pow@var{m}3} instruction pattern 4815*e4b17023SJohn Marino@item @samp{pow@var{m}3} 4816*e4b17023SJohn MarinoStore the value of operand 1 raised to the exponent operand 2 4817*e4b17023SJohn Marinointo operand 0. 4818*e4b17023SJohn Marino 4819*e4b17023SJohn MarinoThe @code{pow} built-in function of C always uses the mode which 4820*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{powf} 4821*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4822*e4b17023SJohn Marinotype @code{float}. 4823*e4b17023SJohn Marino 4824*e4b17023SJohn Marino@cindex @code{atan2@var{m}3} instruction pattern 4825*e4b17023SJohn Marino@item @samp{atan2@var{m}3} 4826*e4b17023SJohn MarinoStore the arc tangent (inverse tangent) of operand 1 divided by 4827*e4b17023SJohn Marinooperand 2 into operand 0, using the signs of both arguments to 4828*e4b17023SJohn Marinodetermine the quadrant of the result. 4829*e4b17023SJohn Marino 4830*e4b17023SJohn MarinoThe @code{atan2} built-in function of C always uses the mode which 4831*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{atan2f} 4832*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4833*e4b17023SJohn Marinotype @code{float}. 4834*e4b17023SJohn Marino 4835*e4b17023SJohn Marino@cindex @code{floor@var{m}2} instruction pattern 4836*e4b17023SJohn Marino@item @samp{floor@var{m}2} 4837*e4b17023SJohn MarinoStore the largest integral value not greater than argument. 4838*e4b17023SJohn Marino 4839*e4b17023SJohn MarinoThe @code{floor} built-in function of C always uses the mode which 4840*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{floorf} 4841*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4842*e4b17023SJohn Marinotype @code{float}. 4843*e4b17023SJohn Marino 4844*e4b17023SJohn Marino@cindex @code{btrunc@var{m}2} instruction pattern 4845*e4b17023SJohn Marino@item @samp{btrunc@var{m}2} 4846*e4b17023SJohn MarinoStore the argument rounded to integer towards zero. 4847*e4b17023SJohn Marino 4848*e4b17023SJohn MarinoThe @code{trunc} built-in function of C always uses the mode which 4849*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{truncf} 4850*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4851*e4b17023SJohn Marinotype @code{float}. 4852*e4b17023SJohn Marino 4853*e4b17023SJohn Marino@cindex @code{round@var{m}2} instruction pattern 4854*e4b17023SJohn Marino@item @samp{round@var{m}2} 4855*e4b17023SJohn MarinoStore the argument rounded to integer away from zero. 4856*e4b17023SJohn Marino 4857*e4b17023SJohn MarinoThe @code{round} built-in function of C always uses the mode which 4858*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{roundf} 4859*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4860*e4b17023SJohn Marinotype @code{float}. 4861*e4b17023SJohn Marino 4862*e4b17023SJohn Marino@cindex @code{ceil@var{m}2} instruction pattern 4863*e4b17023SJohn Marino@item @samp{ceil@var{m}2} 4864*e4b17023SJohn MarinoStore the argument rounded to integer away from zero. 4865*e4b17023SJohn Marino 4866*e4b17023SJohn MarinoThe @code{ceil} built-in function of C always uses the mode which 4867*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{ceilf} 4868*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4869*e4b17023SJohn Marinotype @code{float}. 4870*e4b17023SJohn Marino 4871*e4b17023SJohn Marino@cindex @code{nearbyint@var{m}2} instruction pattern 4872*e4b17023SJohn Marino@item @samp{nearbyint@var{m}2} 4873*e4b17023SJohn MarinoStore the argument rounded according to the default rounding mode 4874*e4b17023SJohn Marino 4875*e4b17023SJohn MarinoThe @code{nearbyint} built-in function of C always uses the mode which 4876*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{nearbyintf} 4877*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4878*e4b17023SJohn Marinotype @code{float}. 4879*e4b17023SJohn Marino 4880*e4b17023SJohn Marino@cindex @code{rint@var{m}2} instruction pattern 4881*e4b17023SJohn Marino@item @samp{rint@var{m}2} 4882*e4b17023SJohn MarinoStore the argument rounded according to the default rounding mode and 4883*e4b17023SJohn Marinoraise the inexact exception when the result differs in value from 4884*e4b17023SJohn Marinothe argument 4885*e4b17023SJohn Marino 4886*e4b17023SJohn MarinoThe @code{rint} built-in function of C always uses the mode which 4887*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{rintf} 4888*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4889*e4b17023SJohn Marinotype @code{float}. 4890*e4b17023SJohn Marino 4891*e4b17023SJohn Marino@cindex @code{lrint@var{m}@var{n}2} 4892*e4b17023SJohn Marino@item @samp{lrint@var{m}@var{n}2} 4893*e4b17023SJohn MarinoConvert operand 1 (valid for floating point mode @var{m}) to fixed 4894*e4b17023SJohn Marinopoint mode @var{n} as a signed number according to the current 4895*e4b17023SJohn Marinorounding mode and store in operand 0 (which has mode @var{n}). 4896*e4b17023SJohn Marino 4897*e4b17023SJohn Marino@cindex @code{lround@var{m}@var{n}2} 4898*e4b17023SJohn Marino@item @samp{lround@var{m}@var{n}2} 4899*e4b17023SJohn MarinoConvert operand 1 (valid for floating point mode @var{m}) to fixed 4900*e4b17023SJohn Marinopoint mode @var{n} as a signed number rounding to nearest and away 4901*e4b17023SJohn Marinofrom zero and store in operand 0 (which has mode @var{n}). 4902*e4b17023SJohn Marino 4903*e4b17023SJohn Marino@cindex @code{lfloor@var{m}@var{n}2} 4904*e4b17023SJohn Marino@item @samp{lfloor@var{m}@var{n}2} 4905*e4b17023SJohn MarinoConvert operand 1 (valid for floating point mode @var{m}) to fixed 4906*e4b17023SJohn Marinopoint mode @var{n} as a signed number rounding down and store in 4907*e4b17023SJohn Marinooperand 0 (which has mode @var{n}). 4908*e4b17023SJohn Marino 4909*e4b17023SJohn Marino@cindex @code{lceil@var{m}@var{n}2} 4910*e4b17023SJohn Marino@item @samp{lceil@var{m}@var{n}2} 4911*e4b17023SJohn MarinoConvert operand 1 (valid for floating point mode @var{m}) to fixed 4912*e4b17023SJohn Marinopoint mode @var{n} as a signed number rounding up and store in 4913*e4b17023SJohn Marinooperand 0 (which has mode @var{n}). 4914*e4b17023SJohn Marino 4915*e4b17023SJohn Marino@cindex @code{copysign@var{m}3} instruction pattern 4916*e4b17023SJohn Marino@item @samp{copysign@var{m}3} 4917*e4b17023SJohn MarinoStore a value with the magnitude of operand 1 and the sign of operand 4918*e4b17023SJohn Marino2 into operand 0. 4919*e4b17023SJohn Marino 4920*e4b17023SJohn MarinoThe @code{copysign} built-in function of C always uses the mode which 4921*e4b17023SJohn Marinocorresponds to the C data type @code{double} and the @code{copysignf} 4922*e4b17023SJohn Marinobuilt-in function uses the mode which corresponds to the C data 4923*e4b17023SJohn Marinotype @code{float}. 4924*e4b17023SJohn Marino 4925*e4b17023SJohn Marino@cindex @code{ffs@var{m}2} instruction pattern 4926*e4b17023SJohn Marino@item @samp{ffs@var{m}2} 4927*e4b17023SJohn MarinoStore into operand 0 one plus the index of the least significant 1-bit 4928*e4b17023SJohn Marinoof operand 1. If operand 1 is zero, store zero. @var{m} is the mode 4929*e4b17023SJohn Marinoof operand 0; operand 1's mode is specified by the instruction 4930*e4b17023SJohn Marinopattern, and the compiler will convert the operand to that mode before 4931*e4b17023SJohn Marinogenerating the instruction. 4932*e4b17023SJohn Marino 4933*e4b17023SJohn MarinoThe @code{ffs} built-in function of C always uses the mode which 4934*e4b17023SJohn Marinocorresponds to the C data type @code{int}. 4935*e4b17023SJohn Marino 4936*e4b17023SJohn Marino@cindex @code{clz@var{m}2} instruction pattern 4937*e4b17023SJohn Marino@item @samp{clz@var{m}2} 4938*e4b17023SJohn MarinoStore into operand 0 the number of leading 0-bits in @var{x}, starting 4939*e4b17023SJohn Marinoat the most significant bit position. If @var{x} is 0, the 4940*e4b17023SJohn Marino@code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if 4941*e4b17023SJohn Marinothe result is undefined or has a useful value. 4942*e4b17023SJohn Marino@var{m} is the mode of operand 0; operand 1's mode is 4943*e4b17023SJohn Marinospecified by the instruction pattern, and the compiler will convert the 4944*e4b17023SJohn Marinooperand to that mode before generating the instruction. 4945*e4b17023SJohn Marino 4946*e4b17023SJohn Marino@cindex @code{ctz@var{m}2} instruction pattern 4947*e4b17023SJohn Marino@item @samp{ctz@var{m}2} 4948*e4b17023SJohn MarinoStore into operand 0 the number of trailing 0-bits in @var{x}, starting 4949*e4b17023SJohn Marinoat the least significant bit position. If @var{x} is 0, the 4950*e4b17023SJohn Marino@code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if 4951*e4b17023SJohn Marinothe result is undefined or has a useful value. 4952*e4b17023SJohn Marino@var{m} is the mode of operand 0; operand 1's mode is 4953*e4b17023SJohn Marinospecified by the instruction pattern, and the compiler will convert the 4954*e4b17023SJohn Marinooperand to that mode before generating the instruction. 4955*e4b17023SJohn Marino 4956*e4b17023SJohn Marino@cindex @code{popcount@var{m}2} instruction pattern 4957*e4b17023SJohn Marino@item @samp{popcount@var{m}2} 4958*e4b17023SJohn MarinoStore into operand 0 the number of 1-bits in @var{x}. @var{m} is the 4959*e4b17023SJohn Marinomode of operand 0; operand 1's mode is specified by the instruction 4960*e4b17023SJohn Marinopattern, and the compiler will convert the operand to that mode before 4961*e4b17023SJohn Marinogenerating the instruction. 4962*e4b17023SJohn Marino 4963*e4b17023SJohn Marino@cindex @code{parity@var{m}2} instruction pattern 4964*e4b17023SJohn Marino@item @samp{parity@var{m}2} 4965*e4b17023SJohn MarinoStore into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits 4966*e4b17023SJohn Marinoin @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode 4967*e4b17023SJohn Marinois specified by the instruction pattern, and the compiler will convert 4968*e4b17023SJohn Marinothe operand to that mode before generating the instruction. 4969*e4b17023SJohn Marino 4970*e4b17023SJohn Marino@cindex @code{one_cmpl@var{m}2} instruction pattern 4971*e4b17023SJohn Marino@item @samp{one_cmpl@var{m}2} 4972*e4b17023SJohn MarinoStore the bitwise-complement of operand 1 into operand 0. 4973*e4b17023SJohn Marino 4974*e4b17023SJohn Marino@cindex @code{movmem@var{m}} instruction pattern 4975*e4b17023SJohn Marino@item @samp{movmem@var{m}} 4976*e4b17023SJohn MarinoBlock move instruction. The destination and source blocks of memory 4977*e4b17023SJohn Marinoare the first two operands, and both are @code{mem:BLK}s with an 4978*e4b17023SJohn Marinoaddress in mode @code{Pmode}. 4979*e4b17023SJohn Marino 4980*e4b17023SJohn MarinoThe number of bytes to move is the third operand, in mode @var{m}. 4981*e4b17023SJohn MarinoUsually, you specify @code{word_mode} for @var{m}. However, if you can 4982*e4b17023SJohn Marinogenerate better code knowing the range of valid lengths is smaller than 4983*e4b17023SJohn Marinothose representable in a full word, you should provide a pattern with a 4984*e4b17023SJohn Marinomode corresponding to the range of values you can handle efficiently 4985*e4b17023SJohn Marino(e.g., @code{QImode} for values in the range 0--127; note we avoid numbers 4986*e4b17023SJohn Marinothat appear negative) and also a pattern with @code{word_mode}. 4987*e4b17023SJohn Marino 4988*e4b17023SJohn MarinoThe fourth operand is the known shared alignment of the source and 4989*e4b17023SJohn Marinodestination, in the form of a @code{const_int} rtx. Thus, if the 4990*e4b17023SJohn Marinocompiler knows that both source and destination are word-aligned, 4991*e4b17023SJohn Marinoit may provide the value 4 for this operand. 4992*e4b17023SJohn Marino 4993*e4b17023SJohn MarinoOptional operands 5 and 6 specify expected alignment and size of block 4994*e4b17023SJohn Marinorespectively. The expected alignment differs from alignment in operand 4 4995*e4b17023SJohn Marinoin a way that the blocks are not required to be aligned according to it in 4996*e4b17023SJohn Marinoall cases. This expected alignment is also in bytes, just like operand 4. 4997*e4b17023SJohn MarinoExpected size, when unknown, is set to @code{(const_int -1)}. 4998*e4b17023SJohn Marino 4999*e4b17023SJohn MarinoDescriptions of multiple @code{movmem@var{m}} patterns can only be 5000*e4b17023SJohn Marinobeneficial if the patterns for smaller modes have fewer restrictions 5001*e4b17023SJohn Marinoon their first, second and fourth operands. Note that the mode @var{m} 5002*e4b17023SJohn Marinoin @code{movmem@var{m}} does not impose any restriction on the mode of 5003*e4b17023SJohn Marinoindividually moved data units in the block. 5004*e4b17023SJohn Marino 5005*e4b17023SJohn MarinoThese patterns need not give special consideration to the possibility 5006*e4b17023SJohn Marinothat the source and destination strings might overlap. 5007*e4b17023SJohn Marino 5008*e4b17023SJohn Marino@cindex @code{movstr} instruction pattern 5009*e4b17023SJohn Marino@item @samp{movstr} 5010*e4b17023SJohn MarinoString copy instruction, with @code{stpcpy} semantics. Operand 0 is 5011*e4b17023SJohn Marinoan output operand in mode @code{Pmode}. The addresses of the 5012*e4b17023SJohn Marinodestination and source strings are operands 1 and 2, and both are 5013*e4b17023SJohn Marino@code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of 5014*e4b17023SJohn Marinothe expansion of this pattern should store in operand 0 the address in 5015*e4b17023SJohn Marinowhich the @code{NUL} terminator was stored in the destination string. 5016*e4b17023SJohn Marino 5017*e4b17023SJohn Marino@cindex @code{setmem@var{m}} instruction pattern 5018*e4b17023SJohn Marino@item @samp{setmem@var{m}} 5019*e4b17023SJohn MarinoBlock set instruction. The destination string is the first operand, 5020*e4b17023SJohn Marinogiven as a @code{mem:BLK} whose address is in mode @code{Pmode}. The 5021*e4b17023SJohn Marinonumber of bytes to set is the second operand, in mode @var{m}. The value to 5022*e4b17023SJohn Marinoinitialize the memory with is the third operand. Targets that only support the 5023*e4b17023SJohn Marinoclearing of memory should reject any value that is not the constant 0. See 5024*e4b17023SJohn Marino@samp{movmem@var{m}} for a discussion of the choice of mode. 5025*e4b17023SJohn Marino 5026*e4b17023SJohn MarinoThe fourth operand is the known alignment of the destination, in the form 5027*e4b17023SJohn Marinoof a @code{const_int} rtx. Thus, if the compiler knows that the 5028*e4b17023SJohn Marinodestination is word-aligned, it may provide the value 4 for this 5029*e4b17023SJohn Marinooperand. 5030*e4b17023SJohn Marino 5031*e4b17023SJohn MarinoOptional operands 5 and 6 specify expected alignment and size of block 5032*e4b17023SJohn Marinorespectively. The expected alignment differs from alignment in operand 4 5033*e4b17023SJohn Marinoin a way that the blocks are not required to be aligned according to it in 5034*e4b17023SJohn Marinoall cases. This expected alignment is also in bytes, just like operand 4. 5035*e4b17023SJohn MarinoExpected size, when unknown, is set to @code{(const_int -1)}. 5036*e4b17023SJohn Marino 5037*e4b17023SJohn MarinoThe use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}. 5038*e4b17023SJohn Marino 5039*e4b17023SJohn Marino@cindex @code{cmpstrn@var{m}} instruction pattern 5040*e4b17023SJohn Marino@item @samp{cmpstrn@var{m}} 5041*e4b17023SJohn MarinoString compare instruction, with five operands. Operand 0 is the output; 5042*e4b17023SJohn Marinoit has mode @var{m}. The remaining four operands are like the operands 5043*e4b17023SJohn Marinoof @samp{movmem@var{m}}. The two memory blocks specified are compared 5044*e4b17023SJohn Marinobyte by byte in lexicographic order starting at the beginning of each 5045*e4b17023SJohn Marinostring. The instruction is not allowed to prefetch more than one byte 5046*e4b17023SJohn Marinoat a time since either string may end in the first byte and reading past 5047*e4b17023SJohn Marinothat may access an invalid page or segment and cause a fault. The 5048*e4b17023SJohn Marinocomparison terminates early if the fetched bytes are different or if 5049*e4b17023SJohn Marinothey are equal to zero. The effect of the instruction is to store a 5050*e4b17023SJohn Marinovalue in operand 0 whose sign indicates the result of the comparison. 5051*e4b17023SJohn Marino 5052*e4b17023SJohn Marino@cindex @code{cmpstr@var{m}} instruction pattern 5053*e4b17023SJohn Marino@item @samp{cmpstr@var{m}} 5054*e4b17023SJohn MarinoString compare instruction, without known maximum length. Operand 0 is the 5055*e4b17023SJohn Marinooutput; it has mode @var{m}. The second and third operand are the blocks of 5056*e4b17023SJohn Marinomemory to be compared; both are @code{mem:BLK} with an address in mode 5057*e4b17023SJohn Marino@code{Pmode}. 5058*e4b17023SJohn Marino 5059*e4b17023SJohn MarinoThe fourth operand is the known shared alignment of the source and 5060*e4b17023SJohn Marinodestination, in the form of a @code{const_int} rtx. Thus, if the 5061*e4b17023SJohn Marinocompiler knows that both source and destination are word-aligned, 5062*e4b17023SJohn Marinoit may provide the value 4 for this operand. 5063*e4b17023SJohn Marino 5064*e4b17023SJohn MarinoThe two memory blocks specified are compared byte by byte in lexicographic 5065*e4b17023SJohn Marinoorder starting at the beginning of each string. The instruction is not allowed 5066*e4b17023SJohn Marinoto prefetch more than one byte at a time since either string may end in the 5067*e4b17023SJohn Marinofirst byte and reading past that may access an invalid page or segment and 5068*e4b17023SJohn Marinocause a fault. The comparison will terminate when the fetched bytes 5069*e4b17023SJohn Marinoare different or if they are equal to zero. The effect of the 5070*e4b17023SJohn Marinoinstruction is to store a value in operand 0 whose sign indicates the 5071*e4b17023SJohn Marinoresult of the comparison. 5072*e4b17023SJohn Marino 5073*e4b17023SJohn Marino@cindex @code{cmpmem@var{m}} instruction pattern 5074*e4b17023SJohn Marino@item @samp{cmpmem@var{m}} 5075*e4b17023SJohn MarinoBlock compare instruction, with five operands like the operands 5076*e4b17023SJohn Marinoof @samp{cmpstr@var{m}}. The two memory blocks specified are compared 5077*e4b17023SJohn Marinobyte by byte in lexicographic order starting at the beginning of each 5078*e4b17023SJohn Marinoblock. Unlike @samp{cmpstr@var{m}} the instruction can prefetch 5079*e4b17023SJohn Marinoany bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}} 5080*e4b17023SJohn Marinothe comparison will not stop if both bytes are zero. The effect of 5081*e4b17023SJohn Marinothe instruction is to store a value in operand 0 whose sign indicates 5082*e4b17023SJohn Marinothe result of the comparison. 5083*e4b17023SJohn Marino 5084*e4b17023SJohn Marino@cindex @code{strlen@var{m}} instruction pattern 5085*e4b17023SJohn Marino@item @samp{strlen@var{m}} 5086*e4b17023SJohn MarinoCompute the length of a string, with three operands. 5087*e4b17023SJohn MarinoOperand 0 is the result (of mode @var{m}), operand 1 is 5088*e4b17023SJohn Marinoa @code{mem} referring to the first character of the string, 5089*e4b17023SJohn Marinooperand 2 is the character to search for (normally zero), 5090*e4b17023SJohn Marinoand operand 3 is a constant describing the known alignment 5091*e4b17023SJohn Marinoof the beginning of the string. 5092*e4b17023SJohn Marino 5093*e4b17023SJohn Marino@cindex @code{float@var{m}@var{n}2} instruction pattern 5094*e4b17023SJohn Marino@item @samp{float@var{m}@var{n}2} 5095*e4b17023SJohn MarinoConvert signed integer operand 1 (valid for fixed point mode @var{m}) to 5096*e4b17023SJohn Marinofloating point mode @var{n} and store in operand 0 (which has mode 5097*e4b17023SJohn Marino@var{n}). 5098*e4b17023SJohn Marino 5099*e4b17023SJohn Marino@cindex @code{floatuns@var{m}@var{n}2} instruction pattern 5100*e4b17023SJohn Marino@item @samp{floatuns@var{m}@var{n}2} 5101*e4b17023SJohn MarinoConvert unsigned integer operand 1 (valid for fixed point mode @var{m}) 5102*e4b17023SJohn Marinoto floating point mode @var{n} and store in operand 0 (which has mode 5103*e4b17023SJohn Marino@var{n}). 5104*e4b17023SJohn Marino 5105*e4b17023SJohn Marino@cindex @code{fix@var{m}@var{n}2} instruction pattern 5106*e4b17023SJohn Marino@item @samp{fix@var{m}@var{n}2} 5107*e4b17023SJohn MarinoConvert operand 1 (valid for floating point mode @var{m}) to fixed 5108*e4b17023SJohn Marinopoint mode @var{n} as a signed number and store in operand 0 (which 5109*e4b17023SJohn Marinohas mode @var{n}). This instruction's result is defined only when 5110*e4b17023SJohn Marinothe value of operand 1 is an integer. 5111*e4b17023SJohn Marino 5112*e4b17023SJohn MarinoIf the machine description defines this pattern, it also needs to 5113*e4b17023SJohn Marinodefine the @code{ftrunc} pattern. 5114*e4b17023SJohn Marino 5115*e4b17023SJohn Marino@cindex @code{fixuns@var{m}@var{n}2} instruction pattern 5116*e4b17023SJohn Marino@item @samp{fixuns@var{m}@var{n}2} 5117*e4b17023SJohn MarinoConvert operand 1 (valid for floating point mode @var{m}) to fixed 5118*e4b17023SJohn Marinopoint mode @var{n} as an unsigned number and store in operand 0 (which 5119*e4b17023SJohn Marinohas mode @var{n}). This instruction's result is defined only when the 5120*e4b17023SJohn Marinovalue of operand 1 is an integer. 5121*e4b17023SJohn Marino 5122*e4b17023SJohn Marino@cindex @code{ftrunc@var{m}2} instruction pattern 5123*e4b17023SJohn Marino@item @samp{ftrunc@var{m}2} 5124*e4b17023SJohn MarinoConvert operand 1 (valid for floating point mode @var{m}) to an 5125*e4b17023SJohn Marinointeger value, still represented in floating point mode @var{m}, and 5126*e4b17023SJohn Marinostore it in operand 0 (valid for floating point mode @var{m}). 5127*e4b17023SJohn Marino 5128*e4b17023SJohn Marino@cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern 5129*e4b17023SJohn Marino@item @samp{fix_trunc@var{m}@var{n}2} 5130*e4b17023SJohn MarinoLike @samp{fix@var{m}@var{n}2} but works for any floating point value 5131*e4b17023SJohn Marinoof mode @var{m} by converting the value to an integer. 5132*e4b17023SJohn Marino 5133*e4b17023SJohn Marino@cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern 5134*e4b17023SJohn Marino@item @samp{fixuns_trunc@var{m}@var{n}2} 5135*e4b17023SJohn MarinoLike @samp{fixuns@var{m}@var{n}2} but works for any floating point 5136*e4b17023SJohn Marinovalue of mode @var{m} by converting the value to an integer. 5137*e4b17023SJohn Marino 5138*e4b17023SJohn Marino@cindex @code{trunc@var{m}@var{n}2} instruction pattern 5139*e4b17023SJohn Marino@item @samp{trunc@var{m}@var{n}2} 5140*e4b17023SJohn MarinoTruncate operand 1 (valid for mode @var{m}) to mode @var{n} and 5141*e4b17023SJohn Marinostore in operand 0 (which has mode @var{n}). Both modes must be fixed 5142*e4b17023SJohn Marinopoint or both floating point. 5143*e4b17023SJohn Marino 5144*e4b17023SJohn Marino@cindex @code{extend@var{m}@var{n}2} instruction pattern 5145*e4b17023SJohn Marino@item @samp{extend@var{m}@var{n}2} 5146*e4b17023SJohn MarinoSign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and 5147*e4b17023SJohn Marinostore in operand 0 (which has mode @var{n}). Both modes must be fixed 5148*e4b17023SJohn Marinopoint or both floating point. 5149*e4b17023SJohn Marino 5150*e4b17023SJohn Marino@cindex @code{zero_extend@var{m}@var{n}2} instruction pattern 5151*e4b17023SJohn Marino@item @samp{zero_extend@var{m}@var{n}2} 5152*e4b17023SJohn MarinoZero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and 5153*e4b17023SJohn Marinostore in operand 0 (which has mode @var{n}). Both modes must be fixed 5154*e4b17023SJohn Marinopoint. 5155*e4b17023SJohn Marino 5156*e4b17023SJohn Marino@cindex @code{fract@var{m}@var{n}2} instruction pattern 5157*e4b17023SJohn Marino@item @samp{fract@var{m}@var{n}2} 5158*e4b17023SJohn MarinoConvert operand 1 of mode @var{m} to mode @var{n} and store in 5159*e4b17023SJohn Marinooperand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} 5160*e4b17023SJohn Marinocould be fixed-point to fixed-point, signed integer to fixed-point, 5161*e4b17023SJohn Marinofixed-point to signed integer, floating-point to fixed-point, 5162*e4b17023SJohn Marinoor fixed-point to floating-point. 5163*e4b17023SJohn MarinoWhen overflows or underflows happen, the results are undefined. 5164*e4b17023SJohn Marino 5165*e4b17023SJohn Marino@cindex @code{satfract@var{m}@var{n}2} instruction pattern 5166*e4b17023SJohn Marino@item @samp{satfract@var{m}@var{n}2} 5167*e4b17023SJohn MarinoConvert operand 1 of mode @var{m} to mode @var{n} and store in 5168*e4b17023SJohn Marinooperand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} 5169*e4b17023SJohn Marinocould be fixed-point to fixed-point, signed integer to fixed-point, 5170*e4b17023SJohn Marinoor floating-point to fixed-point. 5171*e4b17023SJohn MarinoWhen overflows or underflows happen, the instruction saturates the 5172*e4b17023SJohn Marinoresults to the maximum or the minimum. 5173*e4b17023SJohn Marino 5174*e4b17023SJohn Marino@cindex @code{fractuns@var{m}@var{n}2} instruction pattern 5175*e4b17023SJohn Marino@item @samp{fractuns@var{m}@var{n}2} 5176*e4b17023SJohn MarinoConvert operand 1 of mode @var{m} to mode @var{n} and store in 5177*e4b17023SJohn Marinooperand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} 5178*e4b17023SJohn Marinocould be unsigned integer to fixed-point, or 5179*e4b17023SJohn Marinofixed-point to unsigned integer. 5180*e4b17023SJohn MarinoWhen overflows or underflows happen, the results are undefined. 5181*e4b17023SJohn Marino 5182*e4b17023SJohn Marino@cindex @code{satfractuns@var{m}@var{n}2} instruction pattern 5183*e4b17023SJohn Marino@item @samp{satfractuns@var{m}@var{n}2} 5184*e4b17023SJohn MarinoConvert unsigned integer operand 1 of mode @var{m} to fixed-point mode 5185*e4b17023SJohn Marino@var{n} and store in operand 0 (which has mode @var{n}). 5186*e4b17023SJohn MarinoWhen overflows or underflows happen, the instruction saturates the 5187*e4b17023SJohn Marinoresults to the maximum or the minimum. 5188*e4b17023SJohn Marino 5189*e4b17023SJohn Marino@cindex @code{extv} instruction pattern 5190*e4b17023SJohn Marino@item @samp{extv} 5191*e4b17023SJohn MarinoExtract a bit-field from operand 1 (a register or memory operand), where 5192*e4b17023SJohn Marinooperand 2 specifies the width in bits and operand 3 the starting bit, 5193*e4b17023SJohn Marinoand store it in operand 0. Operand 0 must have mode @code{word_mode}. 5194*e4b17023SJohn MarinoOperand 1 may have mode @code{byte_mode} or @code{word_mode}; often 5195*e4b17023SJohn Marino@code{word_mode} is allowed only for registers. Operands 2 and 3 must 5196*e4b17023SJohn Marinobe valid for @code{word_mode}. 5197*e4b17023SJohn Marino 5198*e4b17023SJohn MarinoThe RTL generation pass generates this instruction only with constants 5199*e4b17023SJohn Marinofor operands 2 and 3 and the constant is never zero for operand 2. 5200*e4b17023SJohn Marino 5201*e4b17023SJohn MarinoThe bit-field value is sign-extended to a full word integer 5202*e4b17023SJohn Marinobefore it is stored in operand 0. 5203*e4b17023SJohn Marino 5204*e4b17023SJohn Marino@cindex @code{extzv} instruction pattern 5205*e4b17023SJohn Marino@item @samp{extzv} 5206*e4b17023SJohn MarinoLike @samp{extv} except that the bit-field value is zero-extended. 5207*e4b17023SJohn Marino 5208*e4b17023SJohn Marino@cindex @code{insv} instruction pattern 5209*e4b17023SJohn Marino@item @samp{insv} 5210*e4b17023SJohn MarinoStore operand 3 (which must be valid for @code{word_mode}) into a 5211*e4b17023SJohn Marinobit-field in operand 0, where operand 1 specifies the width in bits and 5212*e4b17023SJohn Marinooperand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or 5213*e4b17023SJohn Marino@code{word_mode}; often @code{word_mode} is allowed only for registers. 5214*e4b17023SJohn MarinoOperands 1 and 2 must be valid for @code{word_mode}. 5215*e4b17023SJohn Marino 5216*e4b17023SJohn MarinoThe RTL generation pass generates this instruction only with constants 5217*e4b17023SJohn Marinofor operands 1 and 2 and the constant is never zero for operand 1. 5218*e4b17023SJohn Marino 5219*e4b17023SJohn Marino@cindex @code{mov@var{mode}cc} instruction pattern 5220*e4b17023SJohn Marino@item @samp{mov@var{mode}cc} 5221*e4b17023SJohn MarinoConditionally move operand 2 or operand 3 into operand 0 according to the 5222*e4b17023SJohn Marinocomparison in operand 1. If the comparison is true, operand 2 is moved 5223*e4b17023SJohn Marinointo operand 0, otherwise operand 3 is moved. 5224*e4b17023SJohn Marino 5225*e4b17023SJohn MarinoThe mode of the operands being compared need not be the same as the operands 5226*e4b17023SJohn Marinobeing moved. Some machines, sparc64 for example, have instructions that 5227*e4b17023SJohn Marinoconditionally move an integer value based on the floating point condition 5228*e4b17023SJohn Marinocodes and vice versa. 5229*e4b17023SJohn Marino 5230*e4b17023SJohn MarinoIf the machine does not have conditional move instructions, do not 5231*e4b17023SJohn Marinodefine these patterns. 5232*e4b17023SJohn Marino 5233*e4b17023SJohn Marino@cindex @code{add@var{mode}cc} instruction pattern 5234*e4b17023SJohn Marino@item @samp{add@var{mode}cc} 5235*e4b17023SJohn MarinoSimilar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally 5236*e4b17023SJohn Marinomove operand 2 or (operands 2 + operand 3) into operand 0 according to the 5237*e4b17023SJohn Marinocomparison in operand 1. If the comparison is true, operand 2 is moved into 5238*e4b17023SJohn Marinooperand 0, otherwise (operand 2 + operand 3) is moved. 5239*e4b17023SJohn Marino 5240*e4b17023SJohn Marino@cindex @code{cstore@var{mode}4} instruction pattern 5241*e4b17023SJohn Marino@item @samp{cstore@var{mode}4} 5242*e4b17023SJohn MarinoStore zero or nonzero in operand 0 according to whether a comparison 5243*e4b17023SJohn Marinois true. Operand 1 is a comparison operator. Operand 2 and operand 3 5244*e4b17023SJohn Marinoare the first and second operand of the comparison, respectively. 5245*e4b17023SJohn MarinoYou specify the mode that operand 0 must have when you write the 5246*e4b17023SJohn Marino@code{match_operand} expression. The compiler automatically sees which 5247*e4b17023SJohn Marinomode you have used and supplies an operand of that mode. 5248*e4b17023SJohn Marino 5249*e4b17023SJohn MarinoThe value stored for a true condition must have 1 as its low bit, or 5250*e4b17023SJohn Marinoelse must be negative. Otherwise the instruction is not suitable and 5251*e4b17023SJohn Marinoyou should omit it from the machine description. You describe to the 5252*e4b17023SJohn Marinocompiler exactly which value is stored by defining the macro 5253*e4b17023SJohn Marino@code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be 5254*e4b17023SJohn Marinofound that can be used for all the possible comparison operators, you 5255*e4b17023SJohn Marinoshould pick one and use a @code{define_expand} to map all results 5256*e4b17023SJohn Marinoonto the one you chose. 5257*e4b17023SJohn Marino 5258*e4b17023SJohn MarinoThese operations may @code{FAIL}, but should do so only in relatively 5259*e4b17023SJohn Marinouncommon cases; if they would @code{FAIL} for common cases involving 5260*e4b17023SJohn Marinointeger comparisons, it is best to restrict the predicates to not 5261*e4b17023SJohn Marinoallow these operands. Likewise if a given comparison operator will 5262*e4b17023SJohn Marinoalways fail, independent of the operands (for floating-point modes, the 5263*e4b17023SJohn Marino@code{ordered_comparison_operator} predicate is often useful in this case). 5264*e4b17023SJohn Marino 5265*e4b17023SJohn MarinoIf this pattern is omitted, the compiler will generate a conditional 5266*e4b17023SJohn Marinobranch---for example, it may copy a constant one to the target and branching 5267*e4b17023SJohn Marinoaround an assignment of zero to the target---or a libcall. If the predicate 5268*e4b17023SJohn Marinofor operand 1 only rejects some operators, it will also try reordering the 5269*e4b17023SJohn Marinooperands and/or inverting the result value (e.g.@: by an exclusive OR). 5270*e4b17023SJohn MarinoThese possibilities could be cheaper or equivalent to the instructions 5271*e4b17023SJohn Marinoused for the @samp{cstore@var{mode}4} pattern followed by those required 5272*e4b17023SJohn Marinoto convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this 5273*e4b17023SJohn Marinocase, you can and should make operand 1's predicate reject some operators 5274*e4b17023SJohn Marinoin the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether 5275*e4b17023SJohn Marinofrom the machine description. 5276*e4b17023SJohn Marino 5277*e4b17023SJohn Marino@cindex @code{cbranch@var{mode}4} instruction pattern 5278*e4b17023SJohn Marino@item @samp{cbranch@var{mode}4} 5279*e4b17023SJohn MarinoConditional branch instruction combined with a compare instruction. 5280*e4b17023SJohn MarinoOperand 0 is a comparison operator. Operand 1 and operand 2 are the 5281*e4b17023SJohn Marinofirst and second operands of the comparison, respectively. Operand 3 5282*e4b17023SJohn Marinois a @code{label_ref} that refers to the label to jump to. 5283*e4b17023SJohn Marino 5284*e4b17023SJohn Marino@cindex @code{jump} instruction pattern 5285*e4b17023SJohn Marino@item @samp{jump} 5286*e4b17023SJohn MarinoA jump inside a function; an unconditional branch. Operand 0 is the 5287*e4b17023SJohn Marino@code{label_ref} of the label to jump to. This pattern name is mandatory 5288*e4b17023SJohn Marinoon all machines. 5289*e4b17023SJohn Marino 5290*e4b17023SJohn Marino@cindex @code{call} instruction pattern 5291*e4b17023SJohn Marino@item @samp{call} 5292*e4b17023SJohn MarinoSubroutine call instruction returning no value. Operand 0 is the 5293*e4b17023SJohn Marinofunction to call; operand 1 is the number of bytes of arguments pushed 5294*e4b17023SJohn Marinoas a @code{const_int}; operand 2 is the number of registers used as 5295*e4b17023SJohn Marinooperands. 5296*e4b17023SJohn Marino 5297*e4b17023SJohn MarinoOn most machines, operand 2 is not actually stored into the RTL 5298*e4b17023SJohn Marinopattern. It is supplied for the sake of some RISC machines which need 5299*e4b17023SJohn Marinoto put this information into the assembler code; they can put it in 5300*e4b17023SJohn Marinothe RTL instead of operand 1. 5301*e4b17023SJohn Marino 5302*e4b17023SJohn MarinoOperand 0 should be a @code{mem} RTX whose address is the address of the 5303*e4b17023SJohn Marinofunction. Note, however, that this address can be a @code{symbol_ref} 5304*e4b17023SJohn Marinoexpression even if it would not be a legitimate memory address on the 5305*e4b17023SJohn Marinotarget machine. If it is also not a valid argument for a call 5306*e4b17023SJohn Marinoinstruction, the pattern for this operation should be a 5307*e4b17023SJohn Marino@code{define_expand} (@pxref{Expander Definitions}) that places the 5308*e4b17023SJohn Marinoaddress into a register and uses that register in the call instruction. 5309*e4b17023SJohn Marino 5310*e4b17023SJohn Marino@cindex @code{call_value} instruction pattern 5311*e4b17023SJohn Marino@item @samp{call_value} 5312*e4b17023SJohn MarinoSubroutine call instruction returning a value. Operand 0 is the hard 5313*e4b17023SJohn Marinoregister in which the value is returned. There are three more 5314*e4b17023SJohn Marinooperands, the same as the three operands of the @samp{call} 5315*e4b17023SJohn Marinoinstruction (but with numbers increased by one). 5316*e4b17023SJohn Marino 5317*e4b17023SJohn MarinoSubroutines that return @code{BLKmode} objects use the @samp{call} 5318*e4b17023SJohn Marinoinsn. 5319*e4b17023SJohn Marino 5320*e4b17023SJohn Marino@cindex @code{call_pop} instruction pattern 5321*e4b17023SJohn Marino@cindex @code{call_value_pop} instruction pattern 5322*e4b17023SJohn Marino@item @samp{call_pop}, @samp{call_value_pop} 5323*e4b17023SJohn MarinoSimilar to @samp{call} and @samp{call_value}, except used if defined and 5324*e4b17023SJohn Marinoif @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel} 5325*e4b17023SJohn Marinothat contains both the function call and a @code{set} to indicate the 5326*e4b17023SJohn Marinoadjustment made to the frame pointer. 5327*e4b17023SJohn Marino 5328*e4b17023SJohn MarinoFor machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these 5329*e4b17023SJohn Marinopatterns increases the number of functions for which the frame pointer 5330*e4b17023SJohn Marinocan be eliminated, if desired. 5331*e4b17023SJohn Marino 5332*e4b17023SJohn Marino@cindex @code{untyped_call} instruction pattern 5333*e4b17023SJohn Marino@item @samp{untyped_call} 5334*e4b17023SJohn MarinoSubroutine call instruction returning a value of any type. Operand 0 is 5335*e4b17023SJohn Marinothe function to call; operand 1 is a memory location where the result of 5336*e4b17023SJohn Marinocalling the function is to be stored; operand 2 is a @code{parallel} 5337*e4b17023SJohn Marinoexpression where each element is a @code{set} expression that indicates 5338*e4b17023SJohn Marinothe saving of a function return value into the result block. 5339*e4b17023SJohn Marino 5340*e4b17023SJohn MarinoThis instruction pattern should be defined to support 5341*e4b17023SJohn Marino@code{__builtin_apply} on machines where special instructions are needed 5342*e4b17023SJohn Marinoto call a subroutine with arbitrary arguments or to save the value 5343*e4b17023SJohn Marinoreturned. This instruction pattern is required on machines that have 5344*e4b17023SJohn Marinomultiple registers that can hold a return value 5345*e4b17023SJohn Marino(i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register). 5346*e4b17023SJohn Marino 5347*e4b17023SJohn Marino@cindex @code{return} instruction pattern 5348*e4b17023SJohn Marino@item @samp{return} 5349*e4b17023SJohn MarinoSubroutine return instruction. This instruction pattern name should be 5350*e4b17023SJohn Marinodefined only if a single instruction can do all the work of returning 5351*e4b17023SJohn Marinofrom a function. 5352*e4b17023SJohn Marino 5353*e4b17023SJohn MarinoLike the @samp{mov@var{m}} patterns, this pattern is also used after the 5354*e4b17023SJohn MarinoRTL generation phase. In this case it is to support machines where 5355*e4b17023SJohn Marinomultiple instructions are usually needed to return from a function, but 5356*e4b17023SJohn Marinosome class of functions only requires one instruction to implement a 5357*e4b17023SJohn Marinoreturn. Normally, the applicable functions are those which do not need 5358*e4b17023SJohn Marinoto save any registers or allocate stack space. 5359*e4b17023SJohn Marino 5360*e4b17023SJohn MarinoIt is valid for this pattern to expand to an instruction using 5361*e4b17023SJohn Marino@code{simple_return} if no epilogue is required. 5362*e4b17023SJohn Marino 5363*e4b17023SJohn Marino@cindex @code{simple_return} instruction pattern 5364*e4b17023SJohn Marino@item @samp{simple_return} 5365*e4b17023SJohn MarinoSubroutine return instruction. This instruction pattern name should be 5366*e4b17023SJohn Marinodefined only if a single instruction can do all the work of returning 5367*e4b17023SJohn Marinofrom a function on a path where no epilogue is required. This pattern 5368*e4b17023SJohn Marinois very similar to the @code{return} instruction pattern, but it is emitted 5369*e4b17023SJohn Marinoonly by the shrink-wrapping optimization on paths where the function 5370*e4b17023SJohn Marinoprologue has not been executed, and a function return should occur without 5371*e4b17023SJohn Marinoany of the effects of the epilogue. Additional uses may be introduced on 5372*e4b17023SJohn Marinopaths where both the prologue and the epilogue have executed. 5373*e4b17023SJohn Marino 5374*e4b17023SJohn Marino@findex reload_completed 5375*e4b17023SJohn Marino@findex leaf_function_p 5376*e4b17023SJohn MarinoFor such machines, the condition specified in this pattern should only 5377*e4b17023SJohn Marinobe true when @code{reload_completed} is nonzero and the function's 5378*e4b17023SJohn Marinoepilogue would only be a single instruction. For machines with register 5379*e4b17023SJohn Marinowindows, the routine @code{leaf_function_p} may be used to determine if 5380*e4b17023SJohn Marinoa register window push is required. 5381*e4b17023SJohn Marino 5382*e4b17023SJohn MarinoMachines that have conditional return instructions should define patterns 5383*e4b17023SJohn Marinosuch as 5384*e4b17023SJohn Marino 5385*e4b17023SJohn Marino@smallexample 5386*e4b17023SJohn Marino(define_insn "" 5387*e4b17023SJohn Marino [(set (pc) 5388*e4b17023SJohn Marino (if_then_else (match_operator 5389*e4b17023SJohn Marino 0 "comparison_operator" 5390*e4b17023SJohn Marino [(cc0) (const_int 0)]) 5391*e4b17023SJohn Marino (return) 5392*e4b17023SJohn Marino (pc)))] 5393*e4b17023SJohn Marino "@var{condition}" 5394*e4b17023SJohn Marino "@dots{}") 5395*e4b17023SJohn Marino@end smallexample 5396*e4b17023SJohn Marino 5397*e4b17023SJohn Marinowhere @var{condition} would normally be the same condition specified on the 5398*e4b17023SJohn Marinonamed @samp{return} pattern. 5399*e4b17023SJohn Marino 5400*e4b17023SJohn Marino@cindex @code{untyped_return} instruction pattern 5401*e4b17023SJohn Marino@item @samp{untyped_return} 5402*e4b17023SJohn MarinoUntyped subroutine return instruction. This instruction pattern should 5403*e4b17023SJohn Marinobe defined to support @code{__builtin_return} on machines where special 5404*e4b17023SJohn Marinoinstructions are needed to return a value of any type. 5405*e4b17023SJohn Marino 5406*e4b17023SJohn MarinoOperand 0 is a memory location where the result of calling a function 5407*e4b17023SJohn Marinowith @code{__builtin_apply} is stored; operand 1 is a @code{parallel} 5408*e4b17023SJohn Marinoexpression where each element is a @code{set} expression that indicates 5409*e4b17023SJohn Marinothe restoring of a function return value from the result block. 5410*e4b17023SJohn Marino 5411*e4b17023SJohn Marino@cindex @code{nop} instruction pattern 5412*e4b17023SJohn Marino@item @samp{nop} 5413*e4b17023SJohn MarinoNo-op instruction. This instruction pattern name should always be defined 5414*e4b17023SJohn Marinoto output a no-op in assembler code. @code{(const_int 0)} will do as an 5415*e4b17023SJohn MarinoRTL pattern. 5416*e4b17023SJohn Marino 5417*e4b17023SJohn Marino@cindex @code{indirect_jump} instruction pattern 5418*e4b17023SJohn Marino@item @samp{indirect_jump} 5419*e4b17023SJohn MarinoAn instruction to jump to an address which is operand zero. 5420*e4b17023SJohn MarinoThis pattern name is mandatory on all machines. 5421*e4b17023SJohn Marino 5422*e4b17023SJohn Marino@cindex @code{casesi} instruction pattern 5423*e4b17023SJohn Marino@item @samp{casesi} 5424*e4b17023SJohn MarinoInstruction to jump through a dispatch table, including bounds checking. 5425*e4b17023SJohn MarinoThis instruction takes five operands: 5426*e4b17023SJohn Marino 5427*e4b17023SJohn Marino@enumerate 5428*e4b17023SJohn Marino@item 5429*e4b17023SJohn MarinoThe index to dispatch on, which has mode @code{SImode}. 5430*e4b17023SJohn Marino 5431*e4b17023SJohn Marino@item 5432*e4b17023SJohn MarinoThe lower bound for indices in the table, an integer constant. 5433*e4b17023SJohn Marino 5434*e4b17023SJohn Marino@item 5435*e4b17023SJohn MarinoThe total range of indices in the table---the largest index 5436*e4b17023SJohn Marinominus the smallest one (both inclusive). 5437*e4b17023SJohn Marino 5438*e4b17023SJohn Marino@item 5439*e4b17023SJohn MarinoA label that precedes the table itself. 5440*e4b17023SJohn Marino 5441*e4b17023SJohn Marino@item 5442*e4b17023SJohn MarinoA label to jump to if the index has a value outside the bounds. 5443*e4b17023SJohn Marino@end enumerate 5444*e4b17023SJohn Marino 5445*e4b17023SJohn MarinoThe table is an @code{addr_vec} or @code{addr_diff_vec} inside of a 5446*e4b17023SJohn Marino@code{jump_insn}. The number of elements in the table is one plus the 5447*e4b17023SJohn Marinodifference between the upper bound and the lower bound. 5448*e4b17023SJohn Marino 5449*e4b17023SJohn Marino@cindex @code{tablejump} instruction pattern 5450*e4b17023SJohn Marino@item @samp{tablejump} 5451*e4b17023SJohn MarinoInstruction to jump to a variable address. This is a low-level 5452*e4b17023SJohn Marinocapability which can be used to implement a dispatch table when there 5453*e4b17023SJohn Marinois no @samp{casesi} pattern. 5454*e4b17023SJohn Marino 5455*e4b17023SJohn MarinoThis pattern requires two operands: the address or offset, and a label 5456*e4b17023SJohn Marinowhich should immediately precede the jump table. If the macro 5457*e4b17023SJohn Marino@code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first 5458*e4b17023SJohn Marinooperand is an offset which counts from the address of the table; otherwise, 5459*e4b17023SJohn Marinoit is an absolute address to jump to. In either case, the first operand has 5460*e4b17023SJohn Marinomode @code{Pmode}. 5461*e4b17023SJohn Marino 5462*e4b17023SJohn MarinoThe @samp{tablejump} insn is always the last insn before the jump 5463*e4b17023SJohn Marinotable it uses. Its assembler code normally has no need to use the 5464*e4b17023SJohn Marinosecond operand, but you should incorporate it in the RTL pattern so 5465*e4b17023SJohn Marinothat the jump optimizer will not delete the table as unreachable code. 5466*e4b17023SJohn Marino 5467*e4b17023SJohn Marino 5468*e4b17023SJohn Marino@cindex @code{decrement_and_branch_until_zero} instruction pattern 5469*e4b17023SJohn Marino@item @samp{decrement_and_branch_until_zero} 5470*e4b17023SJohn MarinoConditional branch instruction that decrements a register and 5471*e4b17023SJohn Marinojumps if the register is nonzero. Operand 0 is the register to 5472*e4b17023SJohn Marinodecrement and test; operand 1 is the label to jump to if the 5473*e4b17023SJohn Marinoregister is nonzero. @xref{Looping Patterns}. 5474*e4b17023SJohn Marino 5475*e4b17023SJohn MarinoThis optional instruction pattern is only used by the combiner, 5476*e4b17023SJohn Marinotypically for loops reversed by the loop optimizer when strength 5477*e4b17023SJohn Marinoreduction is enabled. 5478*e4b17023SJohn Marino 5479*e4b17023SJohn Marino@cindex @code{doloop_end} instruction pattern 5480*e4b17023SJohn Marino@item @samp{doloop_end} 5481*e4b17023SJohn MarinoConditional branch instruction that decrements a register and jumps if 5482*e4b17023SJohn Marinothe register is nonzero. This instruction takes five operands: Operand 5483*e4b17023SJohn Marino0 is the register to decrement and test; operand 1 is the number of loop 5484*e4b17023SJohn Marinoiterations as a @code{const_int} or @code{const0_rtx} if this cannot be 5485*e4b17023SJohn Marinodetermined until run-time; operand 2 is the actual or estimated maximum 5486*e4b17023SJohn Marinonumber of iterations as a @code{const_int}; operand 3 is the number of 5487*e4b17023SJohn Marinoenclosed loops as a @code{const_int} (an innermost loop has a value of 5488*e4b17023SJohn Marino1); operand 4 is the label to jump to if the register is nonzero. 5489*e4b17023SJohn Marino@xref{Looping Patterns}. 5490*e4b17023SJohn Marino 5491*e4b17023SJohn MarinoThis optional instruction pattern should be defined for machines with 5492*e4b17023SJohn Marinolow-overhead looping instructions as the loop optimizer will try to 5493*e4b17023SJohn Marinomodify suitable loops to utilize it. If nested low-overhead looping is 5494*e4b17023SJohn Marinonot supported, use a @code{define_expand} (@pxref{Expander Definitions}) 5495*e4b17023SJohn Marinoand make the pattern fail if operand 3 is not @code{const1_rtx}. 5496*e4b17023SJohn MarinoSimilarly, if the actual or estimated maximum number of iterations is 5497*e4b17023SJohn Marinotoo large for this instruction, make it fail. 5498*e4b17023SJohn Marino 5499*e4b17023SJohn Marino@cindex @code{doloop_begin} instruction pattern 5500*e4b17023SJohn Marino@item @samp{doloop_begin} 5501*e4b17023SJohn MarinoCompanion instruction to @code{doloop_end} required for machines that 5502*e4b17023SJohn Marinoneed to perform some initialization, such as loading special registers 5503*e4b17023SJohn Marinoused by a low-overhead looping instruction. If initialization insns do 5504*e4b17023SJohn Marinonot always need to be emitted, use a @code{define_expand} 5505*e4b17023SJohn Marino(@pxref{Expander Definitions}) and make it fail. 5506*e4b17023SJohn Marino 5507*e4b17023SJohn Marino 5508*e4b17023SJohn Marino@cindex @code{canonicalize_funcptr_for_compare} instruction pattern 5509*e4b17023SJohn Marino@item @samp{canonicalize_funcptr_for_compare} 5510*e4b17023SJohn MarinoCanonicalize the function pointer in operand 1 and store the result 5511*e4b17023SJohn Marinointo operand 0. 5512*e4b17023SJohn Marino 5513*e4b17023SJohn MarinoOperand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1 5514*e4b17023SJohn Marinomay be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc 5515*e4b17023SJohn Marinoand also has mode @code{Pmode}. 5516*e4b17023SJohn Marino 5517*e4b17023SJohn MarinoCanonicalization of a function pointer usually involves computing 5518*e4b17023SJohn Marinothe address of the function which would be called if the function 5519*e4b17023SJohn Marinopointer were used in an indirect call. 5520*e4b17023SJohn Marino 5521*e4b17023SJohn MarinoOnly define this pattern if function pointers on the target machine 5522*e4b17023SJohn Marinocan have different values but still call the same function when 5523*e4b17023SJohn Marinoused in an indirect call. 5524*e4b17023SJohn Marino 5525*e4b17023SJohn Marino@cindex @code{save_stack_block} instruction pattern 5526*e4b17023SJohn Marino@cindex @code{save_stack_function} instruction pattern 5527*e4b17023SJohn Marino@cindex @code{save_stack_nonlocal} instruction pattern 5528*e4b17023SJohn Marino@cindex @code{restore_stack_block} instruction pattern 5529*e4b17023SJohn Marino@cindex @code{restore_stack_function} instruction pattern 5530*e4b17023SJohn Marino@cindex @code{restore_stack_nonlocal} instruction pattern 5531*e4b17023SJohn Marino@item @samp{save_stack_block} 5532*e4b17023SJohn Marino@itemx @samp{save_stack_function} 5533*e4b17023SJohn Marino@itemx @samp{save_stack_nonlocal} 5534*e4b17023SJohn Marino@itemx @samp{restore_stack_block} 5535*e4b17023SJohn Marino@itemx @samp{restore_stack_function} 5536*e4b17023SJohn Marino@itemx @samp{restore_stack_nonlocal} 5537*e4b17023SJohn MarinoMost machines save and restore the stack pointer by copying it to or 5538*e4b17023SJohn Marinofrom an object of mode @code{Pmode}. Do not define these patterns on 5539*e4b17023SJohn Marinosuch machines. 5540*e4b17023SJohn Marino 5541*e4b17023SJohn MarinoSome machines require special handling for stack pointer saves and 5542*e4b17023SJohn Marinorestores. On those machines, define the patterns corresponding to the 5543*e4b17023SJohn Marinonon-standard cases by using a @code{define_expand} (@pxref{Expander 5544*e4b17023SJohn MarinoDefinitions}) that produces the required insns. The three types of 5545*e4b17023SJohn Marinosaves and restores are: 5546*e4b17023SJohn Marino 5547*e4b17023SJohn Marino@enumerate 5548*e4b17023SJohn Marino@item 5549*e4b17023SJohn Marino@samp{save_stack_block} saves the stack pointer at the start of a block 5550*e4b17023SJohn Marinothat allocates a variable-sized object, and @samp{restore_stack_block} 5551*e4b17023SJohn Marinorestores the stack pointer when the block is exited. 5552*e4b17023SJohn Marino 5553*e4b17023SJohn Marino@item 5554*e4b17023SJohn Marino@samp{save_stack_function} and @samp{restore_stack_function} do a 5555*e4b17023SJohn Marinosimilar job for the outermost block of a function and are used when the 5556*e4b17023SJohn Marinofunction allocates variable-sized objects or calls @code{alloca}. Only 5557*e4b17023SJohn Marinothe epilogue uses the restored stack pointer, allowing a simpler save or 5558*e4b17023SJohn Marinorestore sequence on some machines. 5559*e4b17023SJohn Marino 5560*e4b17023SJohn Marino@item 5561*e4b17023SJohn Marino@samp{save_stack_nonlocal} is used in functions that contain labels 5562*e4b17023SJohn Marinobranched to by nested functions. It saves the stack pointer in such a 5563*e4b17023SJohn Marinoway that the inner function can use @samp{restore_stack_nonlocal} to 5564*e4b17023SJohn Marinorestore the stack pointer. The compiler generates code to restore the 5565*e4b17023SJohn Marinoframe and argument pointer registers, but some machines require saving 5566*e4b17023SJohn Marinoand restoring additional data such as register window information or 5567*e4b17023SJohn Marinostack backchains. Place insns in these patterns to save and restore any 5568*e4b17023SJohn Marinosuch required data. 5569*e4b17023SJohn Marino@end enumerate 5570*e4b17023SJohn Marino 5571*e4b17023SJohn MarinoWhen saving the stack pointer, operand 0 is the save area and operand 1 5572*e4b17023SJohn Marinois the stack pointer. The mode used to allocate the save area defaults 5573*e4b17023SJohn Marinoto @code{Pmode} but you can override that choice by defining the 5574*e4b17023SJohn Marino@code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must 5575*e4b17023SJohn Marinospecify an integral mode, or @code{VOIDmode} if no save area is needed 5576*e4b17023SJohn Marinofor a particular type of save (either because no save is needed or 5577*e4b17023SJohn Marinobecause a machine-specific save area can be used). Operand 0 is the 5578*e4b17023SJohn Marinostack pointer and operand 1 is the save area for restore operations. If 5579*e4b17023SJohn Marino@samp{save_stack_block} is defined, operand 0 must not be 5580*e4b17023SJohn Marino@code{VOIDmode} since these saves can be arbitrarily nested. 5581*e4b17023SJohn Marino 5582*e4b17023SJohn MarinoA save area is a @code{mem} that is at a constant offset from 5583*e4b17023SJohn Marino@code{virtual_stack_vars_rtx} when the stack pointer is saved for use by 5584*e4b17023SJohn Marinononlocal gotos and a @code{reg} in the other two cases. 5585*e4b17023SJohn Marino 5586*e4b17023SJohn Marino@cindex @code{allocate_stack} instruction pattern 5587*e4b17023SJohn Marino@item @samp{allocate_stack} 5588*e4b17023SJohn MarinoSubtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from 5589*e4b17023SJohn Marinothe stack pointer to create space for dynamically allocated data. 5590*e4b17023SJohn Marino 5591*e4b17023SJohn MarinoStore the resultant pointer to this space into operand 0. If you 5592*e4b17023SJohn Marinoare allocating space from the main stack, do this by emitting a 5593*e4b17023SJohn Marinomove insn to copy @code{virtual_stack_dynamic_rtx} to operand 0. 5594*e4b17023SJohn MarinoIf you are allocating the space elsewhere, generate code to copy the 5595*e4b17023SJohn Marinolocation of the space to operand 0. In the latter case, you must 5596*e4b17023SJohn Marinoensure this space gets freed when the corresponding space on the main 5597*e4b17023SJohn Marinostack is free. 5598*e4b17023SJohn Marino 5599*e4b17023SJohn MarinoDo not define this pattern if all that must be done is the subtraction. 5600*e4b17023SJohn MarinoSome machines require other operations such as stack probes or 5601*e4b17023SJohn Marinomaintaining the back chain. Define this pattern to emit those 5602*e4b17023SJohn Marinooperations in addition to updating the stack pointer. 5603*e4b17023SJohn Marino 5604*e4b17023SJohn Marino@cindex @code{check_stack} instruction pattern 5605*e4b17023SJohn Marino@item @samp{check_stack} 5606*e4b17023SJohn MarinoIf stack checking (@pxref{Stack Checking}) cannot be done on your system by 5607*e4b17023SJohn Marinoprobing the stack, define this pattern to perform the needed check and signal 5608*e4b17023SJohn Marinoan error if the stack has overflowed. The single operand is the address in 5609*e4b17023SJohn Marinothe stack farthest from the current stack pointer that you need to validate. 5610*e4b17023SJohn MarinoNormally, on platforms where this pattern is needed, you would obtain the 5611*e4b17023SJohn Marinostack limit from a global or thread-specific variable or register. 5612*e4b17023SJohn Marino 5613*e4b17023SJohn Marino@cindex @code{probe_stack} instruction pattern 5614*e4b17023SJohn Marino@item @samp{probe_stack} 5615*e4b17023SJohn MarinoIf stack checking (@pxref{Stack Checking}) can be done on your system by 5616*e4b17023SJohn Marinoprobing the stack but doing it with a ``store zero'' instruction is not valid 5617*e4b17023SJohn Marinoor optimal, define this pattern to do the probing differently and signal an 5618*e4b17023SJohn Marinoerror if the stack has overflowed. The single operand is the memory reference 5619*e4b17023SJohn Marinoin the stack that needs to be probed. 5620*e4b17023SJohn Marino 5621*e4b17023SJohn Marino@cindex @code{nonlocal_goto} instruction pattern 5622*e4b17023SJohn Marino@item @samp{nonlocal_goto} 5623*e4b17023SJohn MarinoEmit code to generate a non-local goto, e.g., a jump from one function 5624*e4b17023SJohn Marinoto a label in an outer function. This pattern has four arguments, 5625*e4b17023SJohn Marinoeach representing a value to be used in the jump. The first 5626*e4b17023SJohn Marinoargument is to be loaded into the frame pointer, the second is 5627*e4b17023SJohn Marinothe address to branch to (code to dispatch to the actual label), 5628*e4b17023SJohn Marinothe third is the address of a location where the stack is saved, 5629*e4b17023SJohn Marinoand the last is the address of the label, to be placed in the 5630*e4b17023SJohn Marinolocation for the incoming static chain. 5631*e4b17023SJohn Marino 5632*e4b17023SJohn MarinoOn most machines you need not define this pattern, since GCC will 5633*e4b17023SJohn Marinoalready generate the correct code, which is to load the frame pointer 5634*e4b17023SJohn Marinoand static chain, restore the stack (using the 5635*e4b17023SJohn Marino@samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly 5636*e4b17023SJohn Marinoto the dispatcher. You need only define this pattern if this code will 5637*e4b17023SJohn Marinonot work on your machine. 5638*e4b17023SJohn Marino 5639*e4b17023SJohn Marino@cindex @code{nonlocal_goto_receiver} instruction pattern 5640*e4b17023SJohn Marino@item @samp{nonlocal_goto_receiver} 5641*e4b17023SJohn MarinoThis pattern, if defined, contains code needed at the target of a 5642*e4b17023SJohn Marinononlocal goto after the code already generated by GCC@. You will not 5643*e4b17023SJohn Marinonormally need to define this pattern. A typical reason why you might 5644*e4b17023SJohn Marinoneed this pattern is if some value, such as a pointer to a global table, 5645*e4b17023SJohn Marinomust be restored when the frame pointer is restored. Note that a nonlocal 5646*e4b17023SJohn Marinogoto only occurs within a unit-of-translation, so a global table pointer 5647*e4b17023SJohn Marinothat is shared by all functions of a given module need not be restored. 5648*e4b17023SJohn MarinoThere are no arguments. 5649*e4b17023SJohn Marino 5650*e4b17023SJohn Marino@cindex @code{exception_receiver} instruction pattern 5651*e4b17023SJohn Marino@item @samp{exception_receiver} 5652*e4b17023SJohn MarinoThis pattern, if defined, contains code needed at the site of an 5653*e4b17023SJohn Marinoexception handler that isn't needed at the site of a nonlocal goto. You 5654*e4b17023SJohn Marinowill not normally need to define this pattern. A typical reason why you 5655*e4b17023SJohn Marinomight need this pattern is if some value, such as a pointer to a global 5656*e4b17023SJohn Marinotable, must be restored after control flow is branched to the handler of 5657*e4b17023SJohn Marinoan exception. There are no arguments. 5658*e4b17023SJohn Marino 5659*e4b17023SJohn Marino@cindex @code{builtin_setjmp_setup} instruction pattern 5660*e4b17023SJohn Marino@item @samp{builtin_setjmp_setup} 5661*e4b17023SJohn MarinoThis pattern, if defined, contains additional code needed to initialize 5662*e4b17023SJohn Marinothe @code{jmp_buf}. You will not normally need to define this pattern. 5663*e4b17023SJohn MarinoA typical reason why you might need this pattern is if some value, such 5664*e4b17023SJohn Marinoas a pointer to a global table, must be restored. Though it is 5665*e4b17023SJohn Marinopreferred that the pointer value be recalculated if possible (given the 5666*e4b17023SJohn Marinoaddress of a label for instance). The single argument is a pointer to 5667*e4b17023SJohn Marinothe @code{jmp_buf}. Note that the buffer is five words long and that 5668*e4b17023SJohn Marinothe first three are normally used by the generic mechanism. 5669*e4b17023SJohn Marino 5670*e4b17023SJohn Marino@cindex @code{builtin_setjmp_receiver} instruction pattern 5671*e4b17023SJohn Marino@item @samp{builtin_setjmp_receiver} 5672*e4b17023SJohn MarinoThis pattern, if defined, contains code needed at the site of a 5673*e4b17023SJohn Marinobuilt-in setjmp that isn't needed at the site of a nonlocal goto. You 5674*e4b17023SJohn Marinowill not normally need to define this pattern. A typical reason why you 5675*e4b17023SJohn Marinomight need this pattern is if some value, such as a pointer to a global 5676*e4b17023SJohn Marinotable, must be restored. It takes one argument, which is the label 5677*e4b17023SJohn Marinoto which builtin_longjmp transfered control; this pattern may be emitted 5678*e4b17023SJohn Marinoat a small offset from that label. 5679*e4b17023SJohn Marino 5680*e4b17023SJohn Marino@cindex @code{builtin_longjmp} instruction pattern 5681*e4b17023SJohn Marino@item @samp{builtin_longjmp} 5682*e4b17023SJohn MarinoThis pattern, if defined, performs the entire action of the longjmp. 5683*e4b17023SJohn MarinoYou will not normally need to define this pattern unless you also define 5684*e4b17023SJohn Marino@code{builtin_setjmp_setup}. The single argument is a pointer to the 5685*e4b17023SJohn Marino@code{jmp_buf}. 5686*e4b17023SJohn Marino 5687*e4b17023SJohn Marino@cindex @code{eh_return} instruction pattern 5688*e4b17023SJohn Marino@item @samp{eh_return} 5689*e4b17023SJohn MarinoThis pattern, if defined, affects the way @code{__builtin_eh_return}, 5690*e4b17023SJohn Marinoand thence the call frame exception handling library routines, are 5691*e4b17023SJohn Marinobuilt. It is intended to handle non-trivial actions needed along 5692*e4b17023SJohn Marinothe abnormal return path. 5693*e4b17023SJohn Marino 5694*e4b17023SJohn MarinoThe address of the exception handler to which the function should return 5695*e4b17023SJohn Marinois passed as operand to this pattern. It will normally need to copied by 5696*e4b17023SJohn Marinothe pattern to some special register or memory location. 5697*e4b17023SJohn MarinoIf the pattern needs to determine the location of the target call 5698*e4b17023SJohn Marinoframe in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX}, 5699*e4b17023SJohn Marinoif defined; it will have already been assigned. 5700*e4b17023SJohn Marino 5701*e4b17023SJohn MarinoIf this pattern is not defined, the default action will be to simply 5702*e4b17023SJohn Marinocopy the return address to @code{EH_RETURN_HANDLER_RTX}. Either 5703*e4b17023SJohn Marinothat macro or this pattern needs to be defined if call frame exception 5704*e4b17023SJohn Marinohandling is to be used. 5705*e4b17023SJohn Marino 5706*e4b17023SJohn Marino@cindex @code{prologue} instruction pattern 5707*e4b17023SJohn Marino@anchor{prologue instruction pattern} 5708*e4b17023SJohn Marino@item @samp{prologue} 5709*e4b17023SJohn MarinoThis pattern, if defined, emits RTL for entry to a function. The function 5710*e4b17023SJohn Marinoentry is responsible for setting up the stack frame, initializing the frame 5711*e4b17023SJohn Marinopointer register, saving callee saved registers, etc. 5712*e4b17023SJohn Marino 5713*e4b17023SJohn MarinoUsing a prologue pattern is generally preferred over defining 5714*e4b17023SJohn Marino@code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue. 5715*e4b17023SJohn Marino 5716*e4b17023SJohn MarinoThe @code{prologue} pattern is particularly useful for targets which perform 5717*e4b17023SJohn Marinoinstruction scheduling. 5718*e4b17023SJohn Marino 5719*e4b17023SJohn Marino@cindex @code{window_save} instruction pattern 5720*e4b17023SJohn Marino@anchor{window_save instruction pattern} 5721*e4b17023SJohn Marino@item @samp{window_save} 5722*e4b17023SJohn MarinoThis pattern, if defined, emits RTL for a register window save. It should 5723*e4b17023SJohn Marinobe defined if the target machine has register windows but the window events 5724*e4b17023SJohn Marinoare decoupled from calls to subroutines. The canonical example is the SPARC 5725*e4b17023SJohn Marinoarchitecture. 5726*e4b17023SJohn Marino 5727*e4b17023SJohn Marino@cindex @code{epilogue} instruction pattern 5728*e4b17023SJohn Marino@anchor{epilogue instruction pattern} 5729*e4b17023SJohn Marino@item @samp{epilogue} 5730*e4b17023SJohn MarinoThis pattern emits RTL for exit from a function. The function 5731*e4b17023SJohn Marinoexit is responsible for deallocating the stack frame, restoring callee saved 5732*e4b17023SJohn Marinoregisters and emitting the return instruction. 5733*e4b17023SJohn Marino 5734*e4b17023SJohn MarinoUsing an epilogue pattern is generally preferred over defining 5735*e4b17023SJohn Marino@code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue. 5736*e4b17023SJohn Marino 5737*e4b17023SJohn MarinoThe @code{epilogue} pattern is particularly useful for targets which perform 5738*e4b17023SJohn Marinoinstruction scheduling or which have delay slots for their return instruction. 5739*e4b17023SJohn Marino 5740*e4b17023SJohn Marino@cindex @code{sibcall_epilogue} instruction pattern 5741*e4b17023SJohn Marino@item @samp{sibcall_epilogue} 5742*e4b17023SJohn MarinoThis pattern, if defined, emits RTL for exit from a function without the final 5743*e4b17023SJohn Marinobranch back to the calling function. This pattern will be emitted before any 5744*e4b17023SJohn Marinosibling call (aka tail call) sites. 5745*e4b17023SJohn Marino 5746*e4b17023SJohn MarinoThe @code{sibcall_epilogue} pattern must not clobber any arguments used for 5747*e4b17023SJohn Marinoparameter passing or any stack slots for arguments passed to the current 5748*e4b17023SJohn Marinofunction. 5749*e4b17023SJohn Marino 5750*e4b17023SJohn Marino@cindex @code{trap} instruction pattern 5751*e4b17023SJohn Marino@item @samp{trap} 5752*e4b17023SJohn MarinoThis pattern, if defined, signals an error, typically by causing some 5753*e4b17023SJohn Marinokind of signal to be raised. Among other places, it is used by the Java 5754*e4b17023SJohn Marinofront end to signal `invalid array index' exceptions. 5755*e4b17023SJohn Marino 5756*e4b17023SJohn Marino@cindex @code{ctrap@var{MM}4} instruction pattern 5757*e4b17023SJohn Marino@item @samp{ctrap@var{MM}4} 5758*e4b17023SJohn MarinoConditional trap instruction. Operand 0 is a piece of RTL which 5759*e4b17023SJohn Marinoperforms a comparison, and operands 1 and 2 are the arms of the 5760*e4b17023SJohn Marinocomparison. Operand 3 is the trap code, an integer. 5761*e4b17023SJohn Marino 5762*e4b17023SJohn MarinoA typical @code{ctrap} pattern looks like 5763*e4b17023SJohn Marino 5764*e4b17023SJohn Marino@smallexample 5765*e4b17023SJohn Marino(define_insn "ctrapsi4" 5766*e4b17023SJohn Marino [(trap_if (match_operator 0 "trap_operator" 5767*e4b17023SJohn Marino [(match_operand 1 "register_operand") 5768*e4b17023SJohn Marino (match_operand 2 "immediate_operand")]) 5769*e4b17023SJohn Marino (match_operand 3 "const_int_operand" "i"))] 5770*e4b17023SJohn Marino "" 5771*e4b17023SJohn Marino "@dots{}") 5772*e4b17023SJohn Marino@end smallexample 5773*e4b17023SJohn Marino 5774*e4b17023SJohn Marino@cindex @code{prefetch} instruction pattern 5775*e4b17023SJohn Marino@item @samp{prefetch} 5776*e4b17023SJohn Marino 5777*e4b17023SJohn MarinoThis pattern, if defined, emits code for a non-faulting data prefetch 5778*e4b17023SJohn Marinoinstruction. Operand 0 is the address of the memory to prefetch. Operand 1 5779*e4b17023SJohn Marinois a constant 1 if the prefetch is preparing for a write to the memory 5780*e4b17023SJohn Marinoaddress, or a constant 0 otherwise. Operand 2 is the expected degree of 5781*e4b17023SJohn Marinotemporal locality of the data and is a value between 0 and 3, inclusive; 0 5782*e4b17023SJohn Marinomeans that the data has no temporal locality, so it need not be left in the 5783*e4b17023SJohn Marinocache after the access; 3 means that the data has a high degree of temporal 5784*e4b17023SJohn Marinolocality and should be left in all levels of cache possible; 1 and 2 mean, 5785*e4b17023SJohn Marinorespectively, a low or moderate degree of temporal locality. 5786*e4b17023SJohn Marino 5787*e4b17023SJohn MarinoTargets that do not support write prefetches or locality hints can ignore 5788*e4b17023SJohn Marinothe values of operands 1 and 2. 5789*e4b17023SJohn Marino 5790*e4b17023SJohn Marino@cindex @code{blockage} instruction pattern 5791*e4b17023SJohn Marino@item @samp{blockage} 5792*e4b17023SJohn Marino 5793*e4b17023SJohn MarinoThis pattern defines a pseudo insn that prevents the instruction 5794*e4b17023SJohn Marinoscheduler from moving instructions across the boundary defined by the 5795*e4b17023SJohn Marinoblockage insn. Normally an UNSPEC_VOLATILE pattern. 5796*e4b17023SJohn Marino 5797*e4b17023SJohn Marino@cindex @code{memory_barrier} instruction pattern 5798*e4b17023SJohn Marino@item @samp{memory_barrier} 5799*e4b17023SJohn Marino 5800*e4b17023SJohn MarinoIf the target memory model is not fully synchronous, then this pattern 5801*e4b17023SJohn Marinoshould be defined to an instruction that orders both loads and stores 5802*e4b17023SJohn Marinobefore the instruction with respect to loads and stores after the instruction. 5803*e4b17023SJohn MarinoThis pattern has no operands. 5804*e4b17023SJohn Marino 5805*e4b17023SJohn Marino@cindex @code{sync_compare_and_swap@var{mode}} instruction pattern 5806*e4b17023SJohn Marino@item @samp{sync_compare_and_swap@var{mode}} 5807*e4b17023SJohn Marino 5808*e4b17023SJohn MarinoThis pattern, if defined, emits code for an atomic compare-and-swap 5809*e4b17023SJohn Marinooperation. Operand 1 is the memory on which the atomic operation is 5810*e4b17023SJohn Marinoperformed. Operand 2 is the ``old'' value to be compared against the 5811*e4b17023SJohn Marinocurrent contents of the memory location. Operand 3 is the ``new'' value 5812*e4b17023SJohn Marinoto store in the memory if the compare succeeds. Operand 0 is the result 5813*e4b17023SJohn Marinoof the operation; it should contain the contents of the memory 5814*e4b17023SJohn Marinobefore the operation. If the compare succeeds, this should obviously be 5815*e4b17023SJohn Marinoa copy of operand 2. 5816*e4b17023SJohn Marino 5817*e4b17023SJohn MarinoThis pattern must show that both operand 0 and operand 1 are modified. 5818*e4b17023SJohn Marino 5819*e4b17023SJohn MarinoThis pattern must issue any memory barrier instructions such that all 5820*e4b17023SJohn Marinomemory operations before the atomic operation occur before the atomic 5821*e4b17023SJohn Marinooperation and all memory operations after the atomic operation occur 5822*e4b17023SJohn Marinoafter the atomic operation. 5823*e4b17023SJohn Marino 5824*e4b17023SJohn MarinoFor targets where the success or failure of the compare-and-swap 5825*e4b17023SJohn Marinooperation is available via the status flags, it is possible to 5826*e4b17023SJohn Marinoavoid a separate compare operation and issue the subsequent 5827*e4b17023SJohn Marinobranch or store-flag operation immediately after the compare-and-swap. 5828*e4b17023SJohn MarinoTo this end, GCC will look for a @code{MODE_CC} set in the 5829*e4b17023SJohn Marinooutput of @code{sync_compare_and_swap@var{mode}}; if the machine 5830*e4b17023SJohn Marinodescription includes such a set, the target should also define special 5831*e4b17023SJohn Marino@code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then 5832*e4b17023SJohn Marinobe able to take the destination of the @code{MODE_CC} set and pass it 5833*e4b17023SJohn Marinoto the @code{cbranchcc4} or @code{cstorecc4} pattern as the first 5834*e4b17023SJohn Marinooperand of the comparison (the second will be @code{(const_int 0)}). 5835*e4b17023SJohn Marino 5836*e4b17023SJohn MarinoFor targets where the operating system may provide support for this 5837*e4b17023SJohn Marinooperation via library calls, the @code{sync_compare_and_swap_optab} 5838*e4b17023SJohn Marinomay be initialized to a function with the same interface as the 5839*e4b17023SJohn Marino@code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire 5840*e4b17023SJohn Marinoset of @var{__sync} builtins are supported via library calls, the 5841*e4b17023SJohn Marinotarget can initialize all of the optabs at once with 5842*e4b17023SJohn Marino@code{init_sync_libfuncs}. 5843*e4b17023SJohn MarinoFor the purposes of C++11 @code{std::atomic::is_lock_free}, it is 5844*e4b17023SJohn Marinoassumed that these library calls do @emph{not} use any kind of 5845*e4b17023SJohn Marinointerruptable locking. 5846*e4b17023SJohn Marino 5847*e4b17023SJohn Marino@cindex @code{sync_add@var{mode}} instruction pattern 5848*e4b17023SJohn Marino@cindex @code{sync_sub@var{mode}} instruction pattern 5849*e4b17023SJohn Marino@cindex @code{sync_ior@var{mode}} instruction pattern 5850*e4b17023SJohn Marino@cindex @code{sync_and@var{mode}} instruction pattern 5851*e4b17023SJohn Marino@cindex @code{sync_xor@var{mode}} instruction pattern 5852*e4b17023SJohn Marino@cindex @code{sync_nand@var{mode}} instruction pattern 5853*e4b17023SJohn Marino@item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}} 5854*e4b17023SJohn Marino@itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}} 5855*e4b17023SJohn Marino@itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}} 5856*e4b17023SJohn Marino 5857*e4b17023SJohn MarinoThese patterns emit code for an atomic operation on memory. 5858*e4b17023SJohn MarinoOperand 0 is the memory on which the atomic operation is performed. 5859*e4b17023SJohn MarinoOperand 1 is the second operand to the binary operator. 5860*e4b17023SJohn Marino 5861*e4b17023SJohn MarinoThis pattern must issue any memory barrier instructions such that all 5862*e4b17023SJohn Marinomemory operations before the atomic operation occur before the atomic 5863*e4b17023SJohn Marinooperation and all memory operations after the atomic operation occur 5864*e4b17023SJohn Marinoafter the atomic operation. 5865*e4b17023SJohn Marino 5866*e4b17023SJohn MarinoIf these patterns are not defined, the operation will be constructed 5867*e4b17023SJohn Marinofrom a compare-and-swap operation, if defined. 5868*e4b17023SJohn Marino 5869*e4b17023SJohn Marino@cindex @code{sync_old_add@var{mode}} instruction pattern 5870*e4b17023SJohn Marino@cindex @code{sync_old_sub@var{mode}} instruction pattern 5871*e4b17023SJohn Marino@cindex @code{sync_old_ior@var{mode}} instruction pattern 5872*e4b17023SJohn Marino@cindex @code{sync_old_and@var{mode}} instruction pattern 5873*e4b17023SJohn Marino@cindex @code{sync_old_xor@var{mode}} instruction pattern 5874*e4b17023SJohn Marino@cindex @code{sync_old_nand@var{mode}} instruction pattern 5875*e4b17023SJohn Marino@item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}} 5876*e4b17023SJohn Marino@itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}} 5877*e4b17023SJohn Marino@itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}} 5878*e4b17023SJohn Marino 5879*e4b17023SJohn MarinoThese patterns are emit code for an atomic operation on memory, 5880*e4b17023SJohn Marinoand return the value that the memory contained before the operation. 5881*e4b17023SJohn MarinoOperand 0 is the result value, operand 1 is the memory on which the 5882*e4b17023SJohn Marinoatomic operation is performed, and operand 2 is the second operand 5883*e4b17023SJohn Marinoto the binary operator. 5884*e4b17023SJohn Marino 5885*e4b17023SJohn MarinoThis pattern must issue any memory barrier instructions such that all 5886*e4b17023SJohn Marinomemory operations before the atomic operation occur before the atomic 5887*e4b17023SJohn Marinooperation and all memory operations after the atomic operation occur 5888*e4b17023SJohn Marinoafter the atomic operation. 5889*e4b17023SJohn Marino 5890*e4b17023SJohn MarinoIf these patterns are not defined, the operation will be constructed 5891*e4b17023SJohn Marinofrom a compare-and-swap operation, if defined. 5892*e4b17023SJohn Marino 5893*e4b17023SJohn Marino@cindex @code{sync_new_add@var{mode}} instruction pattern 5894*e4b17023SJohn Marino@cindex @code{sync_new_sub@var{mode}} instruction pattern 5895*e4b17023SJohn Marino@cindex @code{sync_new_ior@var{mode}} instruction pattern 5896*e4b17023SJohn Marino@cindex @code{sync_new_and@var{mode}} instruction pattern 5897*e4b17023SJohn Marino@cindex @code{sync_new_xor@var{mode}} instruction pattern 5898*e4b17023SJohn Marino@cindex @code{sync_new_nand@var{mode}} instruction pattern 5899*e4b17023SJohn Marino@item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}} 5900*e4b17023SJohn Marino@itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}} 5901*e4b17023SJohn Marino@itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}} 5902*e4b17023SJohn Marino 5903*e4b17023SJohn MarinoThese patterns are like their @code{sync_old_@var{op}} counterparts, 5904*e4b17023SJohn Marinoexcept that they return the value that exists in the memory location 5905*e4b17023SJohn Marinoafter the operation, rather than before the operation. 5906*e4b17023SJohn Marino 5907*e4b17023SJohn Marino@cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern 5908*e4b17023SJohn Marino@item @samp{sync_lock_test_and_set@var{mode}} 5909*e4b17023SJohn Marino 5910*e4b17023SJohn MarinoThis pattern takes two forms, based on the capabilities of the target. 5911*e4b17023SJohn MarinoIn either case, operand 0 is the result of the operand, operand 1 is 5912*e4b17023SJohn Marinothe memory on which the atomic operation is performed, and operand 2 5913*e4b17023SJohn Marinois the value to set in the lock. 5914*e4b17023SJohn Marino 5915*e4b17023SJohn MarinoIn the ideal case, this operation is an atomic exchange operation, in 5916*e4b17023SJohn Marinowhich the previous value in memory operand is copied into the result 5917*e4b17023SJohn Marinooperand, and the value operand is stored in the memory operand. 5918*e4b17023SJohn Marino 5919*e4b17023SJohn MarinoFor less capable targets, any value operand that is not the constant 1 5920*e4b17023SJohn Marinoshould be rejected with @code{FAIL}. In this case the target may use 5921*e4b17023SJohn Marinoan atomic test-and-set bit operation. The result operand should contain 5922*e4b17023SJohn Marino1 if the bit was previously set and 0 if the bit was previously clear. 5923*e4b17023SJohn MarinoThe true contents of the memory operand are implementation defined. 5924*e4b17023SJohn Marino 5925*e4b17023SJohn MarinoThis pattern must issue any memory barrier instructions such that the 5926*e4b17023SJohn Marinopattern as a whole acts as an acquire barrier, that is all memory 5927*e4b17023SJohn Marinooperations after the pattern do not occur until the lock is acquired. 5928*e4b17023SJohn Marino 5929*e4b17023SJohn MarinoIf this pattern is not defined, the operation will be constructed from 5930*e4b17023SJohn Marinoa compare-and-swap operation, if defined. 5931*e4b17023SJohn Marino 5932*e4b17023SJohn Marino@cindex @code{sync_lock_release@var{mode}} instruction pattern 5933*e4b17023SJohn Marino@item @samp{sync_lock_release@var{mode}} 5934*e4b17023SJohn Marino 5935*e4b17023SJohn MarinoThis pattern, if defined, releases a lock set by 5936*e4b17023SJohn Marino@code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory 5937*e4b17023SJohn Marinothat contains the lock; operand 1 is the value to store in the lock. 5938*e4b17023SJohn Marino 5939*e4b17023SJohn MarinoIf the target doesn't implement full semantics for 5940*e4b17023SJohn Marino@code{sync_lock_test_and_set@var{mode}}, any value operand which is not 5941*e4b17023SJohn Marinothe constant 0 should be rejected with @code{FAIL}, and the true contents 5942*e4b17023SJohn Marinoof the memory operand are implementation defined. 5943*e4b17023SJohn Marino 5944*e4b17023SJohn MarinoThis pattern must issue any memory barrier instructions such that the 5945*e4b17023SJohn Marinopattern as a whole acts as a release barrier, that is the lock is 5946*e4b17023SJohn Marinoreleased only after all previous memory operations have completed. 5947*e4b17023SJohn Marino 5948*e4b17023SJohn MarinoIf this pattern is not defined, then a @code{memory_barrier} pattern 5949*e4b17023SJohn Marinowill be emitted, followed by a store of the value to the memory operand. 5950*e4b17023SJohn Marino 5951*e4b17023SJohn Marino@cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern 5952*e4b17023SJohn Marino@item @samp{atomic_compare_and_swap@var{mode}} 5953*e4b17023SJohn MarinoThis pattern, if defined, emits code for an atomic compare-and-swap 5954*e4b17023SJohn Marinooperation with memory model semantics. Operand 2 is the memory on which 5955*e4b17023SJohn Marinothe atomic operation is performed. Operand 0 is an output operand which 5956*e4b17023SJohn Marinois set to true or false based on whether the operation succeeded. Operand 5957*e4b17023SJohn Marino1 is an output operand which is set to the contents of the memory before 5958*e4b17023SJohn Marinothe operation was attempted. Operand 3 is the value that is expected to 5959*e4b17023SJohn Marinobe in memory. Operand 4 is the value to put in memory if the expected 5960*e4b17023SJohn Marinovalue is found there. Operand 5 is set to 1 if this compare and swap is to 5961*e4b17023SJohn Marinobe treated as a weak operation. Operand 6 is the memory model to be used 5962*e4b17023SJohn Marinoif the operation is a success. Operand 7 is the memory model to be used 5963*e4b17023SJohn Marinoif the operation fails. 5964*e4b17023SJohn Marino 5965*e4b17023SJohn MarinoIf memory referred to in operand 2 contains the value in operand 3, then 5966*e4b17023SJohn Marinooperand 4 is stored in memory pointed to by operand 2 and fencing based on 5967*e4b17023SJohn Marinothe memory model in operand 6 is issued. 5968*e4b17023SJohn Marino 5969*e4b17023SJohn MarinoIf memory referred to in operand 2 does not contain the value in operand 3, 5970*e4b17023SJohn Marinothen fencing based on the memory model in operand 7 is issued. 5971*e4b17023SJohn Marino 5972*e4b17023SJohn MarinoIf a target does not support weak compare-and-swap operations, or the port 5973*e4b17023SJohn Marinoelects not to implement weak operations, the argument in operand 5 can be 5974*e4b17023SJohn Marinoignored. Note a strong implementation must be provided. 5975*e4b17023SJohn Marino 5976*e4b17023SJohn MarinoIf this pattern is not provided, the @code{__atomic_compare_exchange} 5977*e4b17023SJohn Marinobuilt-in functions will utilize the legacy @code{sync_compare_and_swap} 5978*e4b17023SJohn Marinopattern with an @code{__ATOMIC_SEQ_CST} memory model. 5979*e4b17023SJohn Marino 5980*e4b17023SJohn Marino@cindex @code{atomic_load@var{mode}} instruction pattern 5981*e4b17023SJohn Marino@item @samp{atomic_load@var{mode}} 5982*e4b17023SJohn MarinoThis pattern implements an atomic load operation with memory model 5983*e4b17023SJohn Marinosemantics. Operand 1 is the memory address being loaded from. Operand 0 5984*e4b17023SJohn Marinois the result of the load. Operand 2 is the memory model to be used for 5985*e4b17023SJohn Marinothe load operation. 5986*e4b17023SJohn Marino 5987*e4b17023SJohn MarinoIf not present, the @code{__atomic_load} built-in function will either 5988*e4b17023SJohn Marinoresort to a normal load with memory barriers, or a compare-and-swap 5989*e4b17023SJohn Marinooperation if a normal load would not be atomic. 5990*e4b17023SJohn Marino 5991*e4b17023SJohn Marino@cindex @code{atomic_store@var{mode}} instruction pattern 5992*e4b17023SJohn Marino@item @samp{atomic_store@var{mode}} 5993*e4b17023SJohn MarinoThis pattern implements an atomic store operation with memory model 5994*e4b17023SJohn Marinosemantics. Operand 0 is the memory address being stored to. Operand 1 5995*e4b17023SJohn Marinois the value to be written. Operand 2 is the memory model to be used for 5996*e4b17023SJohn Marinothe operation. 5997*e4b17023SJohn Marino 5998*e4b17023SJohn MarinoIf not present, the @code{__atomic_store} built-in function will attempt to 5999*e4b17023SJohn Marinoperform a normal store and surround it with any required memory fences. If 6000*e4b17023SJohn Marinothe store would not be atomic, then an @code{__atomic_exchange} is 6001*e4b17023SJohn Marinoattempted with the result being ignored. 6002*e4b17023SJohn Marino 6003*e4b17023SJohn Marino@cindex @code{atomic_exchange@var{mode}} instruction pattern 6004*e4b17023SJohn Marino@item @samp{atomic_exchange@var{mode}} 6005*e4b17023SJohn MarinoThis pattern implements an atomic exchange operation with memory model 6006*e4b17023SJohn Marinosemantics. Operand 1 is the memory location the operation is performed on. 6007*e4b17023SJohn MarinoOperand 0 is an output operand which is set to the original value contained 6008*e4b17023SJohn Marinoin the memory pointed to by operand 1. Operand 2 is the value to be 6009*e4b17023SJohn Marinostored. Operand 3 is the memory model to be used. 6010*e4b17023SJohn Marino 6011*e4b17023SJohn MarinoIf this pattern is not present, the built-in function 6012*e4b17023SJohn Marino@code{__atomic_exchange} will attempt to preform the operation with a 6013*e4b17023SJohn Marinocompare and swap loop. 6014*e4b17023SJohn Marino 6015*e4b17023SJohn Marino@cindex @code{atomic_add@var{mode}} instruction pattern 6016*e4b17023SJohn Marino@cindex @code{atomic_sub@var{mode}} instruction pattern 6017*e4b17023SJohn Marino@cindex @code{atomic_or@var{mode}} instruction pattern 6018*e4b17023SJohn Marino@cindex @code{atomic_and@var{mode}} instruction pattern 6019*e4b17023SJohn Marino@cindex @code{atomic_xor@var{mode}} instruction pattern 6020*e4b17023SJohn Marino@cindex @code{atomic_nand@var{mode}} instruction pattern 6021*e4b17023SJohn Marino@item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}} 6022*e4b17023SJohn Marino@itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}} 6023*e4b17023SJohn Marino@itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}} 6024*e4b17023SJohn Marino 6025*e4b17023SJohn MarinoThese patterns emit code for an atomic operation on memory with memory 6026*e4b17023SJohn Marinomodel semantics. Operand 0 is the memory on which the atomic operation is 6027*e4b17023SJohn Marinoperformed. Operand 1 is the second operand to the binary operator. 6028*e4b17023SJohn MarinoOperand 2 is the memory model to be used by the operation. 6029*e4b17023SJohn Marino 6030*e4b17023SJohn MarinoIf these patterns are not defined, attempts will be made to use legacy 6031*e4b17023SJohn Marino@code{sync} patterns, or equivilent patterns which return a result. If 6032*e4b17023SJohn Marinonone of these are available a compare-and-swap loop will be used. 6033*e4b17023SJohn Marino 6034*e4b17023SJohn Marino@cindex @code{atomic_fetch_add@var{mode}} instruction pattern 6035*e4b17023SJohn Marino@cindex @code{atomic_fetch_sub@var{mode}} instruction pattern 6036*e4b17023SJohn Marino@cindex @code{atomic_fetch_or@var{mode}} instruction pattern 6037*e4b17023SJohn Marino@cindex @code{atomic_fetch_and@var{mode}} instruction pattern 6038*e4b17023SJohn Marino@cindex @code{atomic_fetch_xor@var{mode}} instruction pattern 6039*e4b17023SJohn Marino@cindex @code{atomic_fetch_nand@var{mode}} instruction pattern 6040*e4b17023SJohn Marino@item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}} 6041*e4b17023SJohn Marino@itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}} 6042*e4b17023SJohn Marino@itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}} 6043*e4b17023SJohn Marino 6044*e4b17023SJohn MarinoThese patterns emit code for an atomic operation on memory with memory 6045*e4b17023SJohn Marinomodel semantics, and return the original value. Operand 0 is an output 6046*e4b17023SJohn Marinooperand which contains the value of the memory location before the 6047*e4b17023SJohn Marinooperation was performed. Operand 1 is the memory on which the atomic 6048*e4b17023SJohn Marinooperation is performed. Operand 2 is the second operand to the binary 6049*e4b17023SJohn Marinooperator. Operand 3 is the memory model to be used by the operation. 6050*e4b17023SJohn Marino 6051*e4b17023SJohn MarinoIf these patterns are not defined, attempts will be made to use legacy 6052*e4b17023SJohn Marino@code{sync} patterns. If none of these are available a compare-and-swap 6053*e4b17023SJohn Marinoloop will be used. 6054*e4b17023SJohn Marino 6055*e4b17023SJohn Marino@cindex @code{atomic_add_fetch@var{mode}} instruction pattern 6056*e4b17023SJohn Marino@cindex @code{atomic_sub_fetch@var{mode}} instruction pattern 6057*e4b17023SJohn Marino@cindex @code{atomic_or_fetch@var{mode}} instruction pattern 6058*e4b17023SJohn Marino@cindex @code{atomic_and_fetch@var{mode}} instruction pattern 6059*e4b17023SJohn Marino@cindex @code{atomic_xor_fetch@var{mode}} instruction pattern 6060*e4b17023SJohn Marino@cindex @code{atomic_nand_fetch@var{mode}} instruction pattern 6061*e4b17023SJohn Marino@item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}} 6062*e4b17023SJohn Marino@itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}} 6063*e4b17023SJohn Marino@itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}} 6064*e4b17023SJohn Marino 6065*e4b17023SJohn MarinoThese patterns emit code for an atomic operation on memory with memory 6066*e4b17023SJohn Marinomodel semantics and return the result after the operation is performed. 6067*e4b17023SJohn MarinoOperand 0 is an output operand which contains the value after the 6068*e4b17023SJohn Marinooperation. Operand 1 is the memory on which the atomic operation is 6069*e4b17023SJohn Marinoperformed. Operand 2 is the second operand to the binary operator. 6070*e4b17023SJohn MarinoOperand 3 is the memory model to be used by the operation. 6071*e4b17023SJohn Marino 6072*e4b17023SJohn MarinoIf these patterns are not defined, attempts will be made to use legacy 6073*e4b17023SJohn Marino@code{sync} patterns, or equivilent patterns which return the result before 6074*e4b17023SJohn Marinothe operation followed by the arithmetic operation required to produce the 6075*e4b17023SJohn Marinoresult. If none of these are available a compare-and-swap loop will be 6076*e4b17023SJohn Marinoused. 6077*e4b17023SJohn Marino 6078*e4b17023SJohn Marino@cindex @code{atomic_test_and_set} instruction pattern 6079*e4b17023SJohn Marino@item @samp{atomic_test_and_set} 6080*e4b17023SJohn Marino 6081*e4b17023SJohn MarinoThis pattern emits code for @code{__builtin_atomic_test_and_set}. 6082*e4b17023SJohn MarinoOperand 0 is an output operand which is set to true if the previous 6083*e4b17023SJohn Marinoprevious contents of the byte was "set", and false otherwise. Operand 1 6084*e4b17023SJohn Marinois the @code{QImode} memory to be modified. Operand 2 is the memory 6085*e4b17023SJohn Marinomodel to be used. 6086*e4b17023SJohn Marino 6087*e4b17023SJohn MarinoThe specific value that defines "set" is implementation defined, and 6088*e4b17023SJohn Marinois normally based on what is performed by the native atomic test and set 6089*e4b17023SJohn Marinoinstruction. 6090*e4b17023SJohn Marino 6091*e4b17023SJohn Marino@cindex @code{mem_thread_fence@var{mode}} instruction pattern 6092*e4b17023SJohn Marino@item @samp{mem_thread_fence@var{mode}} 6093*e4b17023SJohn MarinoThis pattern emits code required to implement a thread fence with 6094*e4b17023SJohn Marinomemory model semantics. Operand 0 is the memory model to be used. 6095*e4b17023SJohn Marino 6096*e4b17023SJohn MarinoIf this pattern is not specified, all memory models except 6097*e4b17023SJohn Marino@code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize} 6098*e4b17023SJohn Marinobarrier pattern. 6099*e4b17023SJohn Marino 6100*e4b17023SJohn Marino@cindex @code{mem_signal_fence@var{mode}} instruction pattern 6101*e4b17023SJohn Marino@item @samp{mem_signal_fence@var{mode}} 6102*e4b17023SJohn MarinoThis pattern emits code required to implement a signal fence with 6103*e4b17023SJohn Marinomemory model semantics. Operand 0 is the memory model to be used. 6104*e4b17023SJohn Marino 6105*e4b17023SJohn MarinoThis pattern should impact the compiler optimizers the same way that 6106*e4b17023SJohn Marinomem_signal_fence does, but it does not need to issue any barrier 6107*e4b17023SJohn Marinoinstructions. 6108*e4b17023SJohn Marino 6109*e4b17023SJohn MarinoIf this pattern is not specified, all memory models except 6110*e4b17023SJohn Marino@code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize} 6111*e4b17023SJohn Marinobarrier pattern. 6112*e4b17023SJohn Marino 6113*e4b17023SJohn Marino@cindex @code{stack_protect_set} instruction pattern 6114*e4b17023SJohn Marino@item @samp{stack_protect_set} 6115*e4b17023SJohn Marino 6116*e4b17023SJohn MarinoThis pattern, if defined, moves a @code{ptr_mode} value from the memory 6117*e4b17023SJohn Marinoin operand 1 to the memory in operand 0 without leaving the value in 6118*e4b17023SJohn Marinoa register afterward. This is to avoid leaking the value some place 6119*e4b17023SJohn Marinothat an attacker might use to rewrite the stack guard slot after 6120*e4b17023SJohn Marinohaving clobbered it. 6121*e4b17023SJohn Marino 6122*e4b17023SJohn MarinoIf this pattern is not defined, then a plain move pattern is generated. 6123*e4b17023SJohn Marino 6124*e4b17023SJohn Marino@cindex @code{stack_protect_test} instruction pattern 6125*e4b17023SJohn Marino@item @samp{stack_protect_test} 6126*e4b17023SJohn Marino 6127*e4b17023SJohn MarinoThis pattern, if defined, compares a @code{ptr_mode} value from the 6128*e4b17023SJohn Marinomemory in operand 1 with the memory in operand 0 without leaving the 6129*e4b17023SJohn Marinovalue in a register afterward and branches to operand 2 if the values 6130*e4b17023SJohn Marinoweren't equal. 6131*e4b17023SJohn Marino 6132*e4b17023SJohn MarinoIf this pattern is not defined, then a plain compare pattern and 6133*e4b17023SJohn Marinoconditional branch pattern is used. 6134*e4b17023SJohn Marino 6135*e4b17023SJohn Marino@cindex @code{clear_cache} instruction pattern 6136*e4b17023SJohn Marino@item @samp{clear_cache} 6137*e4b17023SJohn Marino 6138*e4b17023SJohn MarinoThis pattern, if defined, flushes the instruction cache for a region of 6139*e4b17023SJohn Marinomemory. The region is bounded to by the Pmode pointers in operand 0 6140*e4b17023SJohn Marinoinclusive and operand 1 exclusive. 6141*e4b17023SJohn Marino 6142*e4b17023SJohn MarinoIf this pattern is not defined, a call to the library function 6143*e4b17023SJohn Marino@code{__clear_cache} is used. 6144*e4b17023SJohn Marino 6145*e4b17023SJohn Marino@end table 6146*e4b17023SJohn Marino 6147*e4b17023SJohn Marino@end ifset 6148*e4b17023SJohn Marino@c Each of the following nodes are wrapped in separate 6149*e4b17023SJohn Marino@c "@ifset INTERNALS" to work around memory limits for the default 6150*e4b17023SJohn Marino@c configuration in older tetex distributions. Known to not work: 6151*e4b17023SJohn Marino@c tetex-1.0.7, known to work: tetex-2.0.2. 6152*e4b17023SJohn Marino@ifset INTERNALS 6153*e4b17023SJohn Marino@node Pattern Ordering 6154*e4b17023SJohn Marino@section When the Order of Patterns Matters 6155*e4b17023SJohn Marino@cindex Pattern Ordering 6156*e4b17023SJohn Marino@cindex Ordering of Patterns 6157*e4b17023SJohn Marino 6158*e4b17023SJohn MarinoSometimes an insn can match more than one instruction pattern. Then the 6159*e4b17023SJohn Marinopattern that appears first in the machine description is the one used. 6160*e4b17023SJohn MarinoTherefore, more specific patterns (patterns that will match fewer things) 6161*e4b17023SJohn Marinoand faster instructions (those that will produce better code when they 6162*e4b17023SJohn Marinodo match) should usually go first in the description. 6163*e4b17023SJohn Marino 6164*e4b17023SJohn MarinoIn some cases the effect of ordering the patterns can be used to hide 6165*e4b17023SJohn Marinoa pattern when it is not valid. For example, the 68000 has an 6166*e4b17023SJohn Marinoinstruction for converting a fullword to floating point and another 6167*e4b17023SJohn Marinofor converting a byte to floating point. An instruction converting 6168*e4b17023SJohn Marinoan integer to floating point could match either one. We put the 6169*e4b17023SJohn Marinopattern to convert the fullword first to make sure that one will 6170*e4b17023SJohn Marinobe used rather than the other. (Otherwise a large integer might 6171*e4b17023SJohn Marinobe generated as a single-byte immediate quantity, which would not work.) 6172*e4b17023SJohn MarinoInstead of using this pattern ordering it would be possible to make the 6173*e4b17023SJohn Marinopattern for convert-a-byte smart enough to deal properly with any 6174*e4b17023SJohn Marinoconstant value. 6175*e4b17023SJohn Marino 6176*e4b17023SJohn Marino@end ifset 6177*e4b17023SJohn Marino@ifset INTERNALS 6178*e4b17023SJohn Marino@node Dependent Patterns 6179*e4b17023SJohn Marino@section Interdependence of Patterns 6180*e4b17023SJohn Marino@cindex Dependent Patterns 6181*e4b17023SJohn Marino@cindex Interdependence of Patterns 6182*e4b17023SJohn Marino 6183*e4b17023SJohn MarinoIn some cases machines support instructions identical except for the 6184*e4b17023SJohn Marinomachine mode of one or more operands. For example, there may be 6185*e4b17023SJohn Marino``sign-extend halfword'' and ``sign-extend byte'' instructions whose 6186*e4b17023SJohn Marinopatterns are 6187*e4b17023SJohn Marino 6188*e4b17023SJohn Marino@smallexample 6189*e4b17023SJohn Marino(set (match_operand:SI 0 @dots{}) 6190*e4b17023SJohn Marino (extend:SI (match_operand:HI 1 @dots{}))) 6191*e4b17023SJohn Marino 6192*e4b17023SJohn Marino(set (match_operand:SI 0 @dots{}) 6193*e4b17023SJohn Marino (extend:SI (match_operand:QI 1 @dots{}))) 6194*e4b17023SJohn Marino@end smallexample 6195*e4b17023SJohn Marino 6196*e4b17023SJohn Marino@noindent 6197*e4b17023SJohn MarinoConstant integers do not specify a machine mode, so an instruction to 6198*e4b17023SJohn Marinoextend a constant value could match either pattern. The pattern it 6199*e4b17023SJohn Marinoactually will match is the one that appears first in the file. For correct 6200*e4b17023SJohn Marinoresults, this must be the one for the widest possible mode (@code{HImode}, 6201*e4b17023SJohn Marinohere). If the pattern matches the @code{QImode} instruction, the results 6202*e4b17023SJohn Marinowill be incorrect if the constant value does not actually fit that mode. 6203*e4b17023SJohn Marino 6204*e4b17023SJohn MarinoSuch instructions to extend constants are rarely generated because they are 6205*e4b17023SJohn Marinooptimized away, but they do occasionally happen in nonoptimized 6206*e4b17023SJohn Marinocompilations. 6207*e4b17023SJohn Marino 6208*e4b17023SJohn MarinoIf a constraint in a pattern allows a constant, the reload pass may 6209*e4b17023SJohn Marinoreplace a register with a constant permitted by the constraint in some 6210*e4b17023SJohn Marinocases. Similarly for memory references. Because of this substitution, 6211*e4b17023SJohn Marinoyou should not provide separate patterns for increment and decrement 6212*e4b17023SJohn Marinoinstructions. Instead, they should be generated from the same pattern 6213*e4b17023SJohn Marinothat supports register-register add insns by examining the operands and 6214*e4b17023SJohn Marinogenerating the appropriate machine instruction. 6215*e4b17023SJohn Marino 6216*e4b17023SJohn Marino@end ifset 6217*e4b17023SJohn Marino@ifset INTERNALS 6218*e4b17023SJohn Marino@node Jump Patterns 6219*e4b17023SJohn Marino@section Defining Jump Instruction Patterns 6220*e4b17023SJohn Marino@cindex jump instruction patterns 6221*e4b17023SJohn Marino@cindex defining jump instruction patterns 6222*e4b17023SJohn Marino 6223*e4b17023SJohn MarinoGCC does not assume anything about how the machine realizes jumps. 6224*e4b17023SJohn MarinoThe machine description should define a single pattern, usually 6225*e4b17023SJohn Marinoa @code{define_expand}, which expands to all the required insns. 6226*e4b17023SJohn Marino 6227*e4b17023SJohn MarinoUsually, this would be a comparison insn to set the condition code 6228*e4b17023SJohn Marinoand a separate branch insn testing the condition code and branching 6229*e4b17023SJohn Marinoor not according to its value. For many machines, however, 6230*e4b17023SJohn Marinoseparating compares and branches is limiting, which is why the 6231*e4b17023SJohn Marinomore flexible approach with one @code{define_expand} is used in GCC. 6232*e4b17023SJohn MarinoThe machine description becomes clearer for architectures that 6233*e4b17023SJohn Marinohave compare-and-branch instructions but no condition code. It also 6234*e4b17023SJohn Marinoworks better when different sets of comparison operators are supported 6235*e4b17023SJohn Marinoby different kinds of conditional branches (e.g. integer vs. floating-point), 6236*e4b17023SJohn Marinoor by conditional branches with respect to conditional stores. 6237*e4b17023SJohn Marino 6238*e4b17023SJohn MarinoTwo separate insns are always used if the machine description represents 6239*e4b17023SJohn Marinoa condition code register using the legacy RTL expression @code{(cc0)}, 6240*e4b17023SJohn Marinoand on most machines that use a separate condition code register 6241*e4b17023SJohn Marino(@pxref{Condition Code}). For machines that use @code{(cc0)}, in 6242*e4b17023SJohn Marinofact, the set and use of the condition code must be separate and 6243*e4b17023SJohn Marinoadjacent@footnote{@code{note} insns can separate them, though.}, thus 6244*e4b17023SJohn Marinoallowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and 6245*e4b17023SJohn Marinoso that the comparison and branch insns could be located from each other 6246*e4b17023SJohn Marinoby using the functions @code{prev_cc0_setter} and @code{next_cc0_user}. 6247*e4b17023SJohn Marino 6248*e4b17023SJohn MarinoEven in this case having a single entry point for conditional branches 6249*e4b17023SJohn Marinois advantageous, because it handles equally well the case where a single 6250*e4b17023SJohn Marinocomparison instruction records the results of both signed and unsigned 6251*e4b17023SJohn Marinocomparison of the given operands (with the branch insns coming in distinct 6252*e4b17023SJohn Marinosigned and unsigned flavors) as in the x86 or SPARC, and the case where 6253*e4b17023SJohn Marinothere are distinct signed and unsigned compare instructions and only 6254*e4b17023SJohn Marinoone set of conditional branch instructions as in the PowerPC. 6255*e4b17023SJohn Marino 6256*e4b17023SJohn Marino@end ifset 6257*e4b17023SJohn Marino@ifset INTERNALS 6258*e4b17023SJohn Marino@node Looping Patterns 6259*e4b17023SJohn Marino@section Defining Looping Instruction Patterns 6260*e4b17023SJohn Marino@cindex looping instruction patterns 6261*e4b17023SJohn Marino@cindex defining looping instruction patterns 6262*e4b17023SJohn Marino 6263*e4b17023SJohn MarinoSome machines have special jump instructions that can be utilized to 6264*e4b17023SJohn Marinomake loops more efficient. A common example is the 68000 @samp{dbra} 6265*e4b17023SJohn Marinoinstruction which performs a decrement of a register and a branch if the 6266*e4b17023SJohn Marinoresult was greater than zero. Other machines, in particular digital 6267*e4b17023SJohn Marinosignal processors (DSPs), have special block repeat instructions to 6268*e4b17023SJohn Marinoprovide low-overhead loop support. For example, the TI TMS320C3x/C4x 6269*e4b17023SJohn MarinoDSPs have a block repeat instruction that loads special registers to 6270*e4b17023SJohn Marinomark the top and end of a loop and to count the number of loop 6271*e4b17023SJohn Marinoiterations. This avoids the need for fetching and executing a 6272*e4b17023SJohn Marino@samp{dbra}-like instruction and avoids pipeline stalls associated with 6273*e4b17023SJohn Marinothe jump. 6274*e4b17023SJohn Marino 6275*e4b17023SJohn MarinoGCC has three special named patterns to support low overhead looping. 6276*e4b17023SJohn MarinoThey are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin}, 6277*e4b17023SJohn Marinoand @samp{doloop_end}. The first pattern, 6278*e4b17023SJohn Marino@samp{decrement_and_branch_until_zero}, is not emitted during RTL 6279*e4b17023SJohn Marinogeneration but may be emitted during the instruction combination phase. 6280*e4b17023SJohn MarinoThis requires the assistance of the loop optimizer, using information 6281*e4b17023SJohn Marinocollected during strength reduction, to reverse a loop to count down to 6282*e4b17023SJohn Marinozero. Some targets also require the loop optimizer to add a 6283*e4b17023SJohn Marino@code{REG_NONNEG} note to indicate that the iteration count is always 6284*e4b17023SJohn Marinopositive. This is needed if the target performs a signed loop 6285*e4b17023SJohn Marinotermination test. For example, the 68000 uses a pattern similar to the 6286*e4b17023SJohn Marinofollowing for its @code{dbra} instruction: 6287*e4b17023SJohn Marino 6288*e4b17023SJohn Marino@smallexample 6289*e4b17023SJohn Marino@group 6290*e4b17023SJohn Marino(define_insn "decrement_and_branch_until_zero" 6291*e4b17023SJohn Marino [(set (pc) 6292*e4b17023SJohn Marino (if_then_else 6293*e4b17023SJohn Marino (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am") 6294*e4b17023SJohn Marino (const_int -1)) 6295*e4b17023SJohn Marino (const_int 0)) 6296*e4b17023SJohn Marino (label_ref (match_operand 1 "" "")) 6297*e4b17023SJohn Marino (pc))) 6298*e4b17023SJohn Marino (set (match_dup 0) 6299*e4b17023SJohn Marino (plus:SI (match_dup 0) 6300*e4b17023SJohn Marino (const_int -1)))] 6301*e4b17023SJohn Marino "find_reg_note (insn, REG_NONNEG, 0)" 6302*e4b17023SJohn Marino "@dots{}") 6303*e4b17023SJohn Marino@end group 6304*e4b17023SJohn Marino@end smallexample 6305*e4b17023SJohn Marino 6306*e4b17023SJohn MarinoNote that since the insn is both a jump insn and has an output, it must 6307*e4b17023SJohn Marinodeal with its own reloads, hence the `m' constraints. Also note that 6308*e4b17023SJohn Marinosince this insn is generated by the instruction combination phase 6309*e4b17023SJohn Marinocombining two sequential insns together into an implicit parallel insn, 6310*e4b17023SJohn Marinothe iteration counter needs to be biased by the same amount as the 6311*e4b17023SJohn Marinodecrement operation, in this case @minus{}1. Note that the following similar 6312*e4b17023SJohn Marinopattern will not be matched by the combiner. 6313*e4b17023SJohn Marino 6314*e4b17023SJohn Marino@smallexample 6315*e4b17023SJohn Marino@group 6316*e4b17023SJohn Marino(define_insn "decrement_and_branch_until_zero" 6317*e4b17023SJohn Marino [(set (pc) 6318*e4b17023SJohn Marino (if_then_else 6319*e4b17023SJohn Marino (ge (match_operand:SI 0 "general_operand" "+d*am") 6320*e4b17023SJohn Marino (const_int 1)) 6321*e4b17023SJohn Marino (label_ref (match_operand 1 "" "")) 6322*e4b17023SJohn Marino (pc))) 6323*e4b17023SJohn Marino (set (match_dup 0) 6324*e4b17023SJohn Marino (plus:SI (match_dup 0) 6325*e4b17023SJohn Marino (const_int -1)))] 6326*e4b17023SJohn Marino "find_reg_note (insn, REG_NONNEG, 0)" 6327*e4b17023SJohn Marino "@dots{}") 6328*e4b17023SJohn Marino@end group 6329*e4b17023SJohn Marino@end smallexample 6330*e4b17023SJohn Marino 6331*e4b17023SJohn MarinoThe other two special looping patterns, @samp{doloop_begin} and 6332*e4b17023SJohn Marino@samp{doloop_end}, are emitted by the loop optimizer for certain 6333*e4b17023SJohn Marinowell-behaved loops with a finite number of loop iterations using 6334*e4b17023SJohn Marinoinformation collected during strength reduction. 6335*e4b17023SJohn Marino 6336*e4b17023SJohn MarinoThe @samp{doloop_end} pattern describes the actual looping instruction 6337*e4b17023SJohn Marino(or the implicit looping operation) and the @samp{doloop_begin} pattern 6338*e4b17023SJohn Marinois an optional companion pattern that can be used for initialization 6339*e4b17023SJohn Marinoneeded for some low-overhead looping instructions. 6340*e4b17023SJohn Marino 6341*e4b17023SJohn MarinoNote that some machines require the actual looping instruction to be 6342*e4b17023SJohn Marinoemitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting 6343*e4b17023SJohn Marinothe true RTL for a looping instruction at the top of the loop can cause 6344*e4b17023SJohn Marinoproblems with flow analysis. So instead, a dummy @code{doloop} insn is 6345*e4b17023SJohn Marinoemitted at the end of the loop. The machine dependent reorg pass checks 6346*e4b17023SJohn Marinofor the presence of this @code{doloop} insn and then searches back to 6347*e4b17023SJohn Marinothe top of the loop, where it inserts the true looping insn (provided 6348*e4b17023SJohn Marinothere are no instructions in the loop which would cause problems). Any 6349*e4b17023SJohn Marinoadditional labels can be emitted at this point. In addition, if the 6350*e4b17023SJohn Marinodesired special iteration counter register was not allocated, this 6351*e4b17023SJohn Marinomachine dependent reorg pass could emit a traditional compare and jump 6352*e4b17023SJohn Marinoinstruction pair. 6353*e4b17023SJohn Marino 6354*e4b17023SJohn MarinoThe essential difference between the 6355*e4b17023SJohn Marino@samp{decrement_and_branch_until_zero} and the @samp{doloop_end} 6356*e4b17023SJohn Marinopatterns is that the loop optimizer allocates an additional pseudo 6357*e4b17023SJohn Marinoregister for the latter as an iteration counter. This pseudo register 6358*e4b17023SJohn Marinocannot be used within the loop (i.e., general induction variables cannot 6359*e4b17023SJohn Marinobe derived from it), however, in many cases the loop induction variable 6360*e4b17023SJohn Marinomay become redundant and removed by the flow pass. 6361*e4b17023SJohn Marino 6362*e4b17023SJohn Marino 6363*e4b17023SJohn Marino@end ifset 6364*e4b17023SJohn Marino@ifset INTERNALS 6365*e4b17023SJohn Marino@node Insn Canonicalizations 6366*e4b17023SJohn Marino@section Canonicalization of Instructions 6367*e4b17023SJohn Marino@cindex canonicalization of instructions 6368*e4b17023SJohn Marino@cindex insn canonicalization 6369*e4b17023SJohn Marino 6370*e4b17023SJohn MarinoThere are often cases where multiple RTL expressions could represent an 6371*e4b17023SJohn Marinooperation performed by a single machine instruction. This situation is 6372*e4b17023SJohn Marinomost commonly encountered with logical, branch, and multiply-accumulate 6373*e4b17023SJohn Marinoinstructions. In such cases, the compiler attempts to convert these 6374*e4b17023SJohn Marinomultiple RTL expressions into a single canonical form to reduce the 6375*e4b17023SJohn Marinonumber of insn patterns required. 6376*e4b17023SJohn Marino 6377*e4b17023SJohn MarinoIn addition to algebraic simplifications, following canonicalizations 6378*e4b17023SJohn Marinoare performed: 6379*e4b17023SJohn Marino 6380*e4b17023SJohn Marino@itemize @bullet 6381*e4b17023SJohn Marino@item 6382*e4b17023SJohn MarinoFor commutative and comparison operators, a constant is always made the 6383*e4b17023SJohn Marinosecond operand. If a machine only supports a constant as the second 6384*e4b17023SJohn Marinooperand, only patterns that match a constant in the second operand need 6385*e4b17023SJohn Marinobe supplied. 6386*e4b17023SJohn Marino 6387*e4b17023SJohn Marino@item 6388*e4b17023SJohn MarinoFor associative operators, a sequence of operators will always chain 6389*e4b17023SJohn Marinoto the left; for instance, only the left operand of an integer @code{plus} 6390*e4b17023SJohn Marinocan itself be a @code{plus}. @code{and}, @code{ior}, @code{xor}, 6391*e4b17023SJohn Marino@code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and 6392*e4b17023SJohn Marino@code{umax} are associative when applied to integers, and sometimes to 6393*e4b17023SJohn Marinofloating-point. 6394*e4b17023SJohn Marino 6395*e4b17023SJohn Marino@item 6396*e4b17023SJohn Marino@cindex @code{neg}, canonicalization of 6397*e4b17023SJohn Marino@cindex @code{not}, canonicalization of 6398*e4b17023SJohn Marino@cindex @code{mult}, canonicalization of 6399*e4b17023SJohn Marino@cindex @code{plus}, canonicalization of 6400*e4b17023SJohn Marino@cindex @code{minus}, canonicalization of 6401*e4b17023SJohn MarinoFor these operators, if only one operand is a @code{neg}, @code{not}, 6402*e4b17023SJohn Marino@code{mult}, @code{plus}, or @code{minus} expression, it will be the 6403*e4b17023SJohn Marinofirst operand. 6404*e4b17023SJohn Marino 6405*e4b17023SJohn Marino@item 6406*e4b17023SJohn MarinoIn combinations of @code{neg}, @code{mult}, @code{plus}, and 6407*e4b17023SJohn Marino@code{minus}, the @code{neg} operations (if any) will be moved inside 6408*e4b17023SJohn Marinothe operations as far as possible. For instance, 6409*e4b17023SJohn Marino@code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but 6410*e4b17023SJohn Marino@code{(plus (mult (neg B) C) A)} is canonicalized as 6411*e4b17023SJohn Marino@code{(minus A (mult B C))}. 6412*e4b17023SJohn Marino 6413*e4b17023SJohn Marino@cindex @code{compare}, canonicalization of 6414*e4b17023SJohn Marino@item 6415*e4b17023SJohn MarinoFor the @code{compare} operator, a constant is always the second operand 6416*e4b17023SJohn Marinoif the first argument is a condition code register or @code{(cc0)}. 6417*e4b17023SJohn Marino 6418*e4b17023SJohn Marino@item 6419*e4b17023SJohn MarinoAn operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or 6420*e4b17023SJohn Marino@code{minus} is made the first operand under the same conditions as 6421*e4b17023SJohn Marinoabove. 6422*e4b17023SJohn Marino 6423*e4b17023SJohn Marino@item 6424*e4b17023SJohn Marino@code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to 6425*e4b17023SJohn Marino@code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead 6426*e4b17023SJohn Marinoof @code{ltu}. 6427*e4b17023SJohn Marino 6428*e4b17023SJohn Marino@item 6429*e4b17023SJohn Marino@code{(minus @var{x} (const_int @var{n}))} is converted to 6430*e4b17023SJohn Marino@code{(plus @var{x} (const_int @var{-n}))}. 6431*e4b17023SJohn Marino 6432*e4b17023SJohn Marino@item 6433*e4b17023SJohn MarinoWithin address computations (i.e., inside @code{mem}), a left shift is 6434*e4b17023SJohn Marinoconverted into the appropriate multiplication by a power of two. 6435*e4b17023SJohn Marino 6436*e4b17023SJohn Marino@cindex @code{ior}, canonicalization of 6437*e4b17023SJohn Marino@cindex @code{and}, canonicalization of 6438*e4b17023SJohn Marino@cindex De Morgan's law 6439*e4b17023SJohn Marino@item 6440*e4b17023SJohn MarinoDe Morgan's Law is used to move bitwise negation inside a bitwise 6441*e4b17023SJohn Marinological-and or logical-or operation. If this results in only one 6442*e4b17023SJohn Marinooperand being a @code{not} expression, it will be the first one. 6443*e4b17023SJohn Marino 6444*e4b17023SJohn MarinoA machine that has an instruction that performs a bitwise logical-and of one 6445*e4b17023SJohn Marinooperand with the bitwise negation of the other should specify the pattern 6446*e4b17023SJohn Marinofor that instruction as 6447*e4b17023SJohn Marino 6448*e4b17023SJohn Marino@smallexample 6449*e4b17023SJohn Marino(define_insn "" 6450*e4b17023SJohn Marino [(set (match_operand:@var{m} 0 @dots{}) 6451*e4b17023SJohn Marino (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) 6452*e4b17023SJohn Marino (match_operand:@var{m} 2 @dots{})))] 6453*e4b17023SJohn Marino "@dots{}" 6454*e4b17023SJohn Marino "@dots{}") 6455*e4b17023SJohn Marino@end smallexample 6456*e4b17023SJohn Marino 6457*e4b17023SJohn Marino@noindent 6458*e4b17023SJohn MarinoSimilarly, a pattern for a ``NAND'' instruction should be written 6459*e4b17023SJohn Marino 6460*e4b17023SJohn Marino@smallexample 6461*e4b17023SJohn Marino(define_insn "" 6462*e4b17023SJohn Marino [(set (match_operand:@var{m} 0 @dots{}) 6463*e4b17023SJohn Marino (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) 6464*e4b17023SJohn Marino (not:@var{m} (match_operand:@var{m} 2 @dots{}))))] 6465*e4b17023SJohn Marino "@dots{}" 6466*e4b17023SJohn Marino "@dots{}") 6467*e4b17023SJohn Marino@end smallexample 6468*e4b17023SJohn Marino 6469*e4b17023SJohn MarinoIn both cases, it is not necessary to include patterns for the many 6470*e4b17023SJohn Marinologically equivalent RTL expressions. 6471*e4b17023SJohn Marino 6472*e4b17023SJohn Marino@cindex @code{xor}, canonicalization of 6473*e4b17023SJohn Marino@item 6474*e4b17023SJohn MarinoThe only possible RTL expressions involving both bitwise exclusive-or 6475*e4b17023SJohn Marinoand bitwise negation are @code{(xor:@var{m} @var{x} @var{y})} 6476*e4b17023SJohn Marinoand @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}. 6477*e4b17023SJohn Marino 6478*e4b17023SJohn Marino@item 6479*e4b17023SJohn MarinoThe sum of three items, one of which is a constant, will only appear in 6480*e4b17023SJohn Marinothe form 6481*e4b17023SJohn Marino 6482*e4b17023SJohn Marino@smallexample 6483*e4b17023SJohn Marino(plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant}) 6484*e4b17023SJohn Marino@end smallexample 6485*e4b17023SJohn Marino 6486*e4b17023SJohn Marino@cindex @code{zero_extract}, canonicalization of 6487*e4b17023SJohn Marino@cindex @code{sign_extract}, canonicalization of 6488*e4b17023SJohn Marino@item 6489*e4b17023SJohn MarinoEquality comparisons of a group of bits (usually a single bit) with zero 6490*e4b17023SJohn Marinowill be written using @code{zero_extract} rather than the equivalent 6491*e4b17023SJohn Marino@code{and} or @code{sign_extract} operations. 6492*e4b17023SJohn Marino 6493*e4b17023SJohn Marino@cindex @code{mult}, canonicalization of 6494*e4b17023SJohn Marino@item 6495*e4b17023SJohn Marino@code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x}) 6496*e4b17023SJohn Marino(sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1} 6497*e4b17023SJohn Marino(sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise 6498*e4b17023SJohn Marinofor @code{zero_extend}. 6499*e4b17023SJohn Marino 6500*e4b17023SJohn Marino@item 6501*e4b17023SJohn Marino@code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2} 6502*e4b17023SJohn Marino@var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted 6503*e4b17023SJohn Marinoto @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2} 6504*e4b17023SJohn Marino@var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for 6505*e4b17023SJohn Marinopatterns using @code{zero_extend} and @code{lshiftrt}. If the second 6506*e4b17023SJohn Marinooperand of @code{mult} is also a shift, then that is extended also. 6507*e4b17023SJohn MarinoThis transformation is only applied when it can be proven that the 6508*e4b17023SJohn Marinooriginal operation had sufficient precision to prevent overflow. 6509*e4b17023SJohn Marino 6510*e4b17023SJohn Marino@end itemize 6511*e4b17023SJohn Marino 6512*e4b17023SJohn MarinoFurther canonicalization rules are defined in the function 6513*e4b17023SJohn Marino@code{commutative_operand_precedence} in @file{gcc/rtlanal.c}. 6514*e4b17023SJohn Marino 6515*e4b17023SJohn Marino@end ifset 6516*e4b17023SJohn Marino@ifset INTERNALS 6517*e4b17023SJohn Marino@node Expander Definitions 6518*e4b17023SJohn Marino@section Defining RTL Sequences for Code Generation 6519*e4b17023SJohn Marino@cindex expander definitions 6520*e4b17023SJohn Marino@cindex code generation RTL sequences 6521*e4b17023SJohn Marino@cindex defining RTL sequences for code generation 6522*e4b17023SJohn Marino 6523*e4b17023SJohn MarinoOn some target machines, some standard pattern names for RTL generation 6524*e4b17023SJohn Marinocannot be handled with single insn, but a sequence of RTL insns can 6525*e4b17023SJohn Marinorepresent them. For these target machines, you can write a 6526*e4b17023SJohn Marino@code{define_expand} to specify how to generate the sequence of RTL@. 6527*e4b17023SJohn Marino 6528*e4b17023SJohn Marino@findex define_expand 6529*e4b17023SJohn MarinoA @code{define_expand} is an RTL expression that looks almost like a 6530*e4b17023SJohn Marino@code{define_insn}; but, unlike the latter, a @code{define_expand} is used 6531*e4b17023SJohn Marinoonly for RTL generation and it can produce more than one RTL insn. 6532*e4b17023SJohn Marino 6533*e4b17023SJohn MarinoA @code{define_expand} RTX has four operands: 6534*e4b17023SJohn Marino 6535*e4b17023SJohn Marino@itemize @bullet 6536*e4b17023SJohn Marino@item 6537*e4b17023SJohn MarinoThe name. Each @code{define_expand} must have a name, since the only 6538*e4b17023SJohn Marinouse for it is to refer to it by name. 6539*e4b17023SJohn Marino 6540*e4b17023SJohn Marino@item 6541*e4b17023SJohn MarinoThe RTL template. This is a vector of RTL expressions representing 6542*e4b17023SJohn Marinoa sequence of separate instructions. Unlike @code{define_insn}, there 6543*e4b17023SJohn Marinois no implicit surrounding @code{PARALLEL}. 6544*e4b17023SJohn Marino 6545*e4b17023SJohn Marino@item 6546*e4b17023SJohn MarinoThe condition, a string containing a C expression. This expression is 6547*e4b17023SJohn Marinoused to express how the availability of this pattern depends on 6548*e4b17023SJohn Marinosubclasses of target machine, selected by command-line options when GCC 6549*e4b17023SJohn Marinois run. This is just like the condition of a @code{define_insn} that 6550*e4b17023SJohn Marinohas a standard name. Therefore, the condition (if present) may not 6551*e4b17023SJohn Marinodepend on the data in the insn being matched, but only the 6552*e4b17023SJohn Marinotarget-machine-type flags. The compiler needs to test these conditions 6553*e4b17023SJohn Marinoduring initialization in order to learn exactly which named instructions 6554*e4b17023SJohn Marinoare available in a particular run. 6555*e4b17023SJohn Marino 6556*e4b17023SJohn Marino@item 6557*e4b17023SJohn MarinoThe preparation statements, a string containing zero or more C 6558*e4b17023SJohn Marinostatements which are to be executed before RTL code is generated from 6559*e4b17023SJohn Marinothe RTL template. 6560*e4b17023SJohn Marino 6561*e4b17023SJohn MarinoUsually these statements prepare temporary registers for use as 6562*e4b17023SJohn Marinointernal operands in the RTL template, but they can also generate RTL 6563*e4b17023SJohn Marinoinsns directly by calling routines such as @code{emit_insn}, etc. 6564*e4b17023SJohn MarinoAny such insns precede the ones that come from the RTL template. 6565*e4b17023SJohn Marino@end itemize 6566*e4b17023SJohn Marino 6567*e4b17023SJohn MarinoEvery RTL insn emitted by a @code{define_expand} must match some 6568*e4b17023SJohn Marino@code{define_insn} in the machine description. Otherwise, the compiler 6569*e4b17023SJohn Marinowill crash when trying to generate code for the insn or trying to optimize 6570*e4b17023SJohn Marinoit. 6571*e4b17023SJohn Marino 6572*e4b17023SJohn MarinoThe RTL template, in addition to controlling generation of RTL insns, 6573*e4b17023SJohn Marinoalso describes the operands that need to be specified when this pattern 6574*e4b17023SJohn Marinois used. In particular, it gives a predicate for each operand. 6575*e4b17023SJohn Marino 6576*e4b17023SJohn MarinoA true operand, which needs to be specified in order to generate RTL from 6577*e4b17023SJohn Marinothe pattern, should be described with a @code{match_operand} in its first 6578*e4b17023SJohn Marinooccurrence in the RTL template. This enters information on the operand's 6579*e4b17023SJohn Marinopredicate into the tables that record such things. GCC uses the 6580*e4b17023SJohn Marinoinformation to preload the operand into a register if that is required for 6581*e4b17023SJohn Marinovalid RTL code. If the operand is referred to more than once, subsequent 6582*e4b17023SJohn Marinoreferences should use @code{match_dup}. 6583*e4b17023SJohn Marino 6584*e4b17023SJohn MarinoThe RTL template may also refer to internal ``operands'' which are 6585*e4b17023SJohn Marinotemporary registers or labels used only within the sequence made by the 6586*e4b17023SJohn Marino@code{define_expand}. Internal operands are substituted into the RTL 6587*e4b17023SJohn Marinotemplate with @code{match_dup}, never with @code{match_operand}. The 6588*e4b17023SJohn Marinovalues of the internal operands are not passed in as arguments by the 6589*e4b17023SJohn Marinocompiler when it requests use of this pattern. Instead, they are computed 6590*e4b17023SJohn Marinowithin the pattern, in the preparation statements. These statements 6591*e4b17023SJohn Marinocompute the values and store them into the appropriate elements of 6592*e4b17023SJohn Marino@code{operands} so that @code{match_dup} can find them. 6593*e4b17023SJohn Marino 6594*e4b17023SJohn MarinoThere are two special macros defined for use in the preparation statements: 6595*e4b17023SJohn Marino@code{DONE} and @code{FAIL}. Use them with a following semicolon, 6596*e4b17023SJohn Marinoas a statement. 6597*e4b17023SJohn Marino 6598*e4b17023SJohn Marino@table @code 6599*e4b17023SJohn Marino 6600*e4b17023SJohn Marino@findex DONE 6601*e4b17023SJohn Marino@item DONE 6602*e4b17023SJohn MarinoUse the @code{DONE} macro to end RTL generation for the pattern. The 6603*e4b17023SJohn Marinoonly RTL insns resulting from the pattern on this occasion will be 6604*e4b17023SJohn Marinothose already emitted by explicit calls to @code{emit_insn} within the 6605*e4b17023SJohn Marinopreparation statements; the RTL template will not be generated. 6606*e4b17023SJohn Marino 6607*e4b17023SJohn Marino@findex FAIL 6608*e4b17023SJohn Marino@item FAIL 6609*e4b17023SJohn MarinoMake the pattern fail on this occasion. When a pattern fails, it means 6610*e4b17023SJohn Marinothat the pattern was not truly available. The calling routines in the 6611*e4b17023SJohn Marinocompiler will try other strategies for code generation using other patterns. 6612*e4b17023SJohn Marino 6613*e4b17023SJohn MarinoFailure is currently supported only for binary (addition, multiplication, 6614*e4b17023SJohn Marinoshifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv}) 6615*e4b17023SJohn Marinooperations. 6616*e4b17023SJohn Marino@end table 6617*e4b17023SJohn Marino 6618*e4b17023SJohn MarinoIf the preparation falls through (invokes neither @code{DONE} nor 6619*e4b17023SJohn Marino@code{FAIL}), then the @code{define_expand} acts like a 6620*e4b17023SJohn Marino@code{define_insn} in that the RTL template is used to generate the 6621*e4b17023SJohn Marinoinsn. 6622*e4b17023SJohn Marino 6623*e4b17023SJohn MarinoThe RTL template is not used for matching, only for generating the 6624*e4b17023SJohn Marinoinitial insn list. If the preparation statement always invokes 6625*e4b17023SJohn Marino@code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple 6626*e4b17023SJohn Marinolist of operands, such as this example: 6627*e4b17023SJohn Marino 6628*e4b17023SJohn Marino@smallexample 6629*e4b17023SJohn Marino@group 6630*e4b17023SJohn Marino(define_expand "addsi3" 6631*e4b17023SJohn Marino [(match_operand:SI 0 "register_operand" "") 6632*e4b17023SJohn Marino (match_operand:SI 1 "register_operand" "") 6633*e4b17023SJohn Marino (match_operand:SI 2 "register_operand" "")] 6634*e4b17023SJohn Marino@end group 6635*e4b17023SJohn Marino@group 6636*e4b17023SJohn Marino "" 6637*e4b17023SJohn Marino " 6638*e4b17023SJohn Marino@{ 6639*e4b17023SJohn Marino handle_add (operands[0], operands[1], operands[2]); 6640*e4b17023SJohn Marino DONE; 6641*e4b17023SJohn Marino@}") 6642*e4b17023SJohn Marino@end group 6643*e4b17023SJohn Marino@end smallexample 6644*e4b17023SJohn Marino 6645*e4b17023SJohn MarinoHere is an example, the definition of left-shift for the SPUR chip: 6646*e4b17023SJohn Marino 6647*e4b17023SJohn Marino@smallexample 6648*e4b17023SJohn Marino@group 6649*e4b17023SJohn Marino(define_expand "ashlsi3" 6650*e4b17023SJohn Marino [(set (match_operand:SI 0 "register_operand" "") 6651*e4b17023SJohn Marino (ashift:SI 6652*e4b17023SJohn Marino@end group 6653*e4b17023SJohn Marino@group 6654*e4b17023SJohn Marino (match_operand:SI 1 "register_operand" "") 6655*e4b17023SJohn Marino (match_operand:SI 2 "nonmemory_operand" "")))] 6656*e4b17023SJohn Marino "" 6657*e4b17023SJohn Marino " 6658*e4b17023SJohn Marino@end group 6659*e4b17023SJohn Marino@end smallexample 6660*e4b17023SJohn Marino 6661*e4b17023SJohn Marino@smallexample 6662*e4b17023SJohn Marino@group 6663*e4b17023SJohn Marino@{ 6664*e4b17023SJohn Marino if (GET_CODE (operands[2]) != CONST_INT 6665*e4b17023SJohn Marino || (unsigned) INTVAL (operands[2]) > 3) 6666*e4b17023SJohn Marino FAIL; 6667*e4b17023SJohn Marino@}") 6668*e4b17023SJohn Marino@end group 6669*e4b17023SJohn Marino@end smallexample 6670*e4b17023SJohn Marino 6671*e4b17023SJohn Marino@noindent 6672*e4b17023SJohn MarinoThis example uses @code{define_expand} so that it can generate an RTL insn 6673*e4b17023SJohn Marinofor shifting when the shift-count is in the supported range of 0 to 3 but 6674*e4b17023SJohn Marinofail in other cases where machine insns aren't available. When it fails, 6675*e4b17023SJohn Marinothe compiler tries another strategy using different patterns (such as, a 6676*e4b17023SJohn Marinolibrary call). 6677*e4b17023SJohn Marino 6678*e4b17023SJohn MarinoIf the compiler were able to handle nontrivial condition-strings in 6679*e4b17023SJohn Marinopatterns with names, then it would be possible to use a 6680*e4b17023SJohn Marino@code{define_insn} in that case. Here is another case (zero-extension 6681*e4b17023SJohn Marinoon the 68000) which makes more use of the power of @code{define_expand}: 6682*e4b17023SJohn Marino 6683*e4b17023SJohn Marino@smallexample 6684*e4b17023SJohn Marino(define_expand "zero_extendhisi2" 6685*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "") 6686*e4b17023SJohn Marino (const_int 0)) 6687*e4b17023SJohn Marino (set (strict_low_part 6688*e4b17023SJohn Marino (subreg:HI 6689*e4b17023SJohn Marino (match_dup 0) 6690*e4b17023SJohn Marino 0)) 6691*e4b17023SJohn Marino (match_operand:HI 1 "general_operand" ""))] 6692*e4b17023SJohn Marino "" 6693*e4b17023SJohn Marino "operands[1] = make_safe_from (operands[1], operands[0]);") 6694*e4b17023SJohn Marino@end smallexample 6695*e4b17023SJohn Marino 6696*e4b17023SJohn Marino@noindent 6697*e4b17023SJohn Marino@findex make_safe_from 6698*e4b17023SJohn MarinoHere two RTL insns are generated, one to clear the entire output operand 6699*e4b17023SJohn Marinoand the other to copy the input operand into its low half. This sequence 6700*e4b17023SJohn Marinois incorrect if the input operand refers to [the old value of] the output 6701*e4b17023SJohn Marinooperand, so the preparation statement makes sure this isn't so. The 6702*e4b17023SJohn Marinofunction @code{make_safe_from} copies the @code{operands[1]} into a 6703*e4b17023SJohn Marinotemporary register if it refers to @code{operands[0]}. It does this 6704*e4b17023SJohn Marinoby emitting another RTL insn. 6705*e4b17023SJohn Marino 6706*e4b17023SJohn MarinoFinally, a third example shows the use of an internal operand. 6707*e4b17023SJohn MarinoZero-extension on the SPUR chip is done by @code{and}-ing the result 6708*e4b17023SJohn Marinoagainst a halfword mask. But this mask cannot be represented by a 6709*e4b17023SJohn Marino@code{const_int} because the constant value is too large to be legitimate 6710*e4b17023SJohn Marinoon this machine. So it must be copied into a register with 6711*e4b17023SJohn Marino@code{force_reg} and then the register used in the @code{and}. 6712*e4b17023SJohn Marino 6713*e4b17023SJohn Marino@smallexample 6714*e4b17023SJohn Marino(define_expand "zero_extendhisi2" 6715*e4b17023SJohn Marino [(set (match_operand:SI 0 "register_operand" "") 6716*e4b17023SJohn Marino (and:SI (subreg:SI 6717*e4b17023SJohn Marino (match_operand:HI 1 "register_operand" "") 6718*e4b17023SJohn Marino 0) 6719*e4b17023SJohn Marino (match_dup 2)))] 6720*e4b17023SJohn Marino "" 6721*e4b17023SJohn Marino "operands[2] 6722*e4b17023SJohn Marino = force_reg (SImode, GEN_INT (65535)); ") 6723*e4b17023SJohn Marino@end smallexample 6724*e4b17023SJohn Marino 6725*e4b17023SJohn Marino@emph{Note:} If the @code{define_expand} is used to serve a 6726*e4b17023SJohn Marinostandard binary or unary arithmetic operation or a bit-field operation, 6727*e4b17023SJohn Marinothen the last insn it generates must not be a @code{code_label}, 6728*e4b17023SJohn Marino@code{barrier} or @code{note}. It must be an @code{insn}, 6729*e4b17023SJohn Marino@code{jump_insn} or @code{call_insn}. If you don't need a real insn 6730*e4b17023SJohn Marinoat the end, emit an insn to copy the result of the operation into 6731*e4b17023SJohn Marinoitself. Such an insn will generate no code, but it can avoid problems 6732*e4b17023SJohn Marinoin the compiler. 6733*e4b17023SJohn Marino 6734*e4b17023SJohn Marino@end ifset 6735*e4b17023SJohn Marino@ifset INTERNALS 6736*e4b17023SJohn Marino@node Insn Splitting 6737*e4b17023SJohn Marino@section Defining How to Split Instructions 6738*e4b17023SJohn Marino@cindex insn splitting 6739*e4b17023SJohn Marino@cindex instruction splitting 6740*e4b17023SJohn Marino@cindex splitting instructions 6741*e4b17023SJohn Marino 6742*e4b17023SJohn MarinoThere are two cases where you should specify how to split a pattern 6743*e4b17023SJohn Marinointo multiple insns. On machines that have instructions requiring 6744*e4b17023SJohn Marinodelay slots (@pxref{Delay Slots}) or that have instructions whose 6745*e4b17023SJohn Marinooutput is not available for multiple cycles (@pxref{Processor pipeline 6746*e4b17023SJohn Marinodescription}), the compiler phases that optimize these cases need to 6747*e4b17023SJohn Marinobe able to move insns into one-instruction delay slots. However, some 6748*e4b17023SJohn Marinoinsns may generate more than one machine instruction. These insns 6749*e4b17023SJohn Marinocannot be placed into a delay slot. 6750*e4b17023SJohn Marino 6751*e4b17023SJohn MarinoOften you can rewrite the single insn as a list of individual insns, 6752*e4b17023SJohn Marinoeach corresponding to one machine instruction. The disadvantage of 6753*e4b17023SJohn Marinodoing so is that it will cause the compilation to be slower and require 6754*e4b17023SJohn Marinomore space. If the resulting insns are too complex, it may also 6755*e4b17023SJohn Marinosuppress some optimizations. The compiler splits the insn if there is a 6756*e4b17023SJohn Marinoreason to believe that it might improve instruction or delay slot 6757*e4b17023SJohn Marinoscheduling. 6758*e4b17023SJohn Marino 6759*e4b17023SJohn MarinoThe insn combiner phase also splits putative insns. If three insns are 6760*e4b17023SJohn Marinomerged into one insn with a complex expression that cannot be matched by 6761*e4b17023SJohn Marinosome @code{define_insn} pattern, the combiner phase attempts to split 6762*e4b17023SJohn Marinothe complex pattern into two insns that are recognized. Usually it can 6763*e4b17023SJohn Marinobreak the complex pattern into two patterns by splitting out some 6764*e4b17023SJohn Marinosubexpression. However, in some other cases, such as performing an 6765*e4b17023SJohn Marinoaddition of a large constant in two insns on a RISC machine, the way to 6766*e4b17023SJohn Marinosplit the addition into two insns is machine-dependent. 6767*e4b17023SJohn Marino 6768*e4b17023SJohn Marino@findex define_split 6769*e4b17023SJohn MarinoThe @code{define_split} definition tells the compiler how to split a 6770*e4b17023SJohn Marinocomplex insn into several simpler insns. It looks like this: 6771*e4b17023SJohn Marino 6772*e4b17023SJohn Marino@smallexample 6773*e4b17023SJohn Marino(define_split 6774*e4b17023SJohn Marino [@var{insn-pattern}] 6775*e4b17023SJohn Marino "@var{condition}" 6776*e4b17023SJohn Marino [@var{new-insn-pattern-1} 6777*e4b17023SJohn Marino @var{new-insn-pattern-2} 6778*e4b17023SJohn Marino @dots{}] 6779*e4b17023SJohn Marino "@var{preparation-statements}") 6780*e4b17023SJohn Marino@end smallexample 6781*e4b17023SJohn Marino 6782*e4b17023SJohn Marino@var{insn-pattern} is a pattern that needs to be split and 6783*e4b17023SJohn Marino@var{condition} is the final condition to be tested, as in a 6784*e4b17023SJohn Marino@code{define_insn}. When an insn matching @var{insn-pattern} and 6785*e4b17023SJohn Marinosatisfying @var{condition} is found, it is replaced in the insn list 6786*e4b17023SJohn Marinowith the insns given by @var{new-insn-pattern-1}, 6787*e4b17023SJohn Marino@var{new-insn-pattern-2}, etc. 6788*e4b17023SJohn Marino 6789*e4b17023SJohn MarinoThe @var{preparation-statements} are similar to those statements that 6790*e4b17023SJohn Marinoare specified for @code{define_expand} (@pxref{Expander Definitions}) 6791*e4b17023SJohn Marinoand are executed before the new RTL is generated to prepare for the 6792*e4b17023SJohn Marinogenerated code or emit some insns whose pattern is not fixed. Unlike 6793*e4b17023SJohn Marinothose in @code{define_expand}, however, these statements must not 6794*e4b17023SJohn Marinogenerate any new pseudo-registers. Once reload has completed, they also 6795*e4b17023SJohn Marinomust not allocate any space in the stack frame. 6796*e4b17023SJohn Marino 6797*e4b17023SJohn MarinoPatterns are matched against @var{insn-pattern} in two different 6798*e4b17023SJohn Marinocircumstances. If an insn needs to be split for delay slot scheduling 6799*e4b17023SJohn Marinoor insn scheduling, the insn is already known to be valid, which means 6800*e4b17023SJohn Marinothat it must have been matched by some @code{define_insn} and, if 6801*e4b17023SJohn Marino@code{reload_completed} is nonzero, is known to satisfy the constraints 6802*e4b17023SJohn Marinoof that @code{define_insn}. In that case, the new insn patterns must 6803*e4b17023SJohn Marinoalso be insns that are matched by some @code{define_insn} and, if 6804*e4b17023SJohn Marino@code{reload_completed} is nonzero, must also satisfy the constraints 6805*e4b17023SJohn Marinoof those definitions. 6806*e4b17023SJohn Marino 6807*e4b17023SJohn MarinoAs an example of this usage of @code{define_split}, consider the following 6808*e4b17023SJohn Marinoexample from @file{a29k.md}, which splits a @code{sign_extend} from 6809*e4b17023SJohn Marino@code{HImode} to @code{SImode} into a pair of shift insns: 6810*e4b17023SJohn Marino 6811*e4b17023SJohn Marino@smallexample 6812*e4b17023SJohn Marino(define_split 6813*e4b17023SJohn Marino [(set (match_operand:SI 0 "gen_reg_operand" "") 6814*e4b17023SJohn Marino (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] 6815*e4b17023SJohn Marino "" 6816*e4b17023SJohn Marino [(set (match_dup 0) 6817*e4b17023SJohn Marino (ashift:SI (match_dup 1) 6818*e4b17023SJohn Marino (const_int 16))) 6819*e4b17023SJohn Marino (set (match_dup 0) 6820*e4b17023SJohn Marino (ashiftrt:SI (match_dup 0) 6821*e4b17023SJohn Marino (const_int 16)))] 6822*e4b17023SJohn Marino " 6823*e4b17023SJohn Marino@{ operands[1] = gen_lowpart (SImode, operands[1]); @}") 6824*e4b17023SJohn Marino@end smallexample 6825*e4b17023SJohn Marino 6826*e4b17023SJohn MarinoWhen the combiner phase tries to split an insn pattern, it is always the 6827*e4b17023SJohn Marinocase that the pattern is @emph{not} matched by any @code{define_insn}. 6828*e4b17023SJohn MarinoThe combiner pass first tries to split a single @code{set} expression 6829*e4b17023SJohn Marinoand then the same @code{set} expression inside a @code{parallel}, but 6830*e4b17023SJohn Marinofollowed by a @code{clobber} of a pseudo-reg to use as a scratch 6831*e4b17023SJohn Marinoregister. In these cases, the combiner expects exactly two new insn 6832*e4b17023SJohn Marinopatterns to be generated. It will verify that these patterns match some 6833*e4b17023SJohn Marino@code{define_insn} definitions, so you need not do this test in the 6834*e4b17023SJohn Marino@code{define_split} (of course, there is no point in writing a 6835*e4b17023SJohn Marino@code{define_split} that will never produce insns that match). 6836*e4b17023SJohn Marino 6837*e4b17023SJohn MarinoHere is an example of this use of @code{define_split}, taken from 6838*e4b17023SJohn Marino@file{rs6000.md}: 6839*e4b17023SJohn Marino 6840*e4b17023SJohn Marino@smallexample 6841*e4b17023SJohn Marino(define_split 6842*e4b17023SJohn Marino [(set (match_operand:SI 0 "gen_reg_operand" "") 6843*e4b17023SJohn Marino (plus:SI (match_operand:SI 1 "gen_reg_operand" "") 6844*e4b17023SJohn Marino (match_operand:SI 2 "non_add_cint_operand" "")))] 6845*e4b17023SJohn Marino "" 6846*e4b17023SJohn Marino [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 6847*e4b17023SJohn Marino (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 6848*e4b17023SJohn Marino" 6849*e4b17023SJohn Marino@{ 6850*e4b17023SJohn Marino int low = INTVAL (operands[2]) & 0xffff; 6851*e4b17023SJohn Marino int high = (unsigned) INTVAL (operands[2]) >> 16; 6852*e4b17023SJohn Marino 6853*e4b17023SJohn Marino if (low & 0x8000) 6854*e4b17023SJohn Marino high++, low |= 0xffff0000; 6855*e4b17023SJohn Marino 6856*e4b17023SJohn Marino operands[3] = GEN_INT (high << 16); 6857*e4b17023SJohn Marino operands[4] = GEN_INT (low); 6858*e4b17023SJohn Marino@}") 6859*e4b17023SJohn Marino@end smallexample 6860*e4b17023SJohn Marino 6861*e4b17023SJohn MarinoHere the predicate @code{non_add_cint_operand} matches any 6862*e4b17023SJohn Marino@code{const_int} that is @emph{not} a valid operand of a single add 6863*e4b17023SJohn Marinoinsn. The add with the smaller displacement is written so that it 6864*e4b17023SJohn Marinocan be substituted into the address of a subsequent operation. 6865*e4b17023SJohn Marino 6866*e4b17023SJohn MarinoAn example that uses a scratch register, from the same file, generates 6867*e4b17023SJohn Marinoan equality comparison of a register and a large constant: 6868*e4b17023SJohn Marino 6869*e4b17023SJohn Marino@smallexample 6870*e4b17023SJohn Marino(define_split 6871*e4b17023SJohn Marino [(set (match_operand:CC 0 "cc_reg_operand" "") 6872*e4b17023SJohn Marino (compare:CC (match_operand:SI 1 "gen_reg_operand" "") 6873*e4b17023SJohn Marino (match_operand:SI 2 "non_short_cint_operand" ""))) 6874*e4b17023SJohn Marino (clobber (match_operand:SI 3 "gen_reg_operand" ""))] 6875*e4b17023SJohn Marino "find_single_use (operands[0], insn, 0) 6876*e4b17023SJohn Marino && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ 6877*e4b17023SJohn Marino || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" 6878*e4b17023SJohn Marino [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) 6879*e4b17023SJohn Marino (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] 6880*e4b17023SJohn Marino " 6881*e4b17023SJohn Marino@{ 6882*e4b17023SJohn Marino /* @r{Get the constant we are comparing against, C, and see what it 6883*e4b17023SJohn Marino looks like sign-extended to 16 bits. Then see what constant 6884*e4b17023SJohn Marino could be XOR'ed with C to get the sign-extended value.} */ 6885*e4b17023SJohn Marino 6886*e4b17023SJohn Marino int c = INTVAL (operands[2]); 6887*e4b17023SJohn Marino int sextc = (c << 16) >> 16; 6888*e4b17023SJohn Marino int xorv = c ^ sextc; 6889*e4b17023SJohn Marino 6890*e4b17023SJohn Marino operands[4] = GEN_INT (xorv); 6891*e4b17023SJohn Marino operands[5] = GEN_INT (sextc); 6892*e4b17023SJohn Marino@}") 6893*e4b17023SJohn Marino@end smallexample 6894*e4b17023SJohn Marino 6895*e4b17023SJohn MarinoTo avoid confusion, don't write a single @code{define_split} that 6896*e4b17023SJohn Marinoaccepts some insns that match some @code{define_insn} as well as some 6897*e4b17023SJohn Marinoinsns that don't. Instead, write two separate @code{define_split} 6898*e4b17023SJohn Marinodefinitions, one for the insns that are valid and one for the insns that 6899*e4b17023SJohn Marinoare not valid. 6900*e4b17023SJohn Marino 6901*e4b17023SJohn MarinoThe splitter is allowed to split jump instructions into sequence of 6902*e4b17023SJohn Marinojumps or create new jumps in while splitting non-jump instructions. As 6903*e4b17023SJohn Marinothe central flowgraph and branch prediction information needs to be updated, 6904*e4b17023SJohn Marinoseveral restriction apply. 6905*e4b17023SJohn Marino 6906*e4b17023SJohn MarinoSplitting of jump instruction into sequence that over by another jump 6907*e4b17023SJohn Marinoinstruction is always valid, as compiler expect identical behavior of new 6908*e4b17023SJohn Marinojump. When new sequence contains multiple jump instructions or new labels, 6909*e4b17023SJohn Marinomore assistance is needed. Splitter is required to create only unconditional 6910*e4b17023SJohn Marinojumps, or simple conditional jump instructions. Additionally it must attach a 6911*e4b17023SJohn Marino@code{REG_BR_PROB} note to each conditional jump. A global variable 6912*e4b17023SJohn Marino@code{split_branch_probability} holds the probability of the original branch in case 6913*e4b17023SJohn Marinoit was a simple conditional jump, @minus{}1 otherwise. To simplify 6914*e4b17023SJohn Marinorecomputing of edge frequencies, the new sequence is required to have only 6915*e4b17023SJohn Marinoforward jumps to the newly created labels. 6916*e4b17023SJohn Marino 6917*e4b17023SJohn Marino@findex define_insn_and_split 6918*e4b17023SJohn MarinoFor the common case where the pattern of a define_split exactly matches the 6919*e4b17023SJohn Marinopattern of a define_insn, use @code{define_insn_and_split}. It looks like 6920*e4b17023SJohn Marinothis: 6921*e4b17023SJohn Marino 6922*e4b17023SJohn Marino@smallexample 6923*e4b17023SJohn Marino(define_insn_and_split 6924*e4b17023SJohn Marino [@var{insn-pattern}] 6925*e4b17023SJohn Marino "@var{condition}" 6926*e4b17023SJohn Marino "@var{output-template}" 6927*e4b17023SJohn Marino "@var{split-condition}" 6928*e4b17023SJohn Marino [@var{new-insn-pattern-1} 6929*e4b17023SJohn Marino @var{new-insn-pattern-2} 6930*e4b17023SJohn Marino @dots{}] 6931*e4b17023SJohn Marino "@var{preparation-statements}" 6932*e4b17023SJohn Marino [@var{insn-attributes}]) 6933*e4b17023SJohn Marino 6934*e4b17023SJohn Marino@end smallexample 6935*e4b17023SJohn Marino 6936*e4b17023SJohn Marino@var{insn-pattern}, @var{condition}, @var{output-template}, and 6937*e4b17023SJohn Marino@var{insn-attributes} are used as in @code{define_insn}. The 6938*e4b17023SJohn Marino@var{new-insn-pattern} vector and the @var{preparation-statements} are used as 6939*e4b17023SJohn Marinoin a @code{define_split}. The @var{split-condition} is also used as in 6940*e4b17023SJohn Marino@code{define_split}, with the additional behavior that if the condition starts 6941*e4b17023SJohn Marinowith @samp{&&}, the condition used for the split will be the constructed as a 6942*e4b17023SJohn Marinological ``and'' of the split condition with the insn condition. For example, 6943*e4b17023SJohn Marinofrom i386.md: 6944*e4b17023SJohn Marino 6945*e4b17023SJohn Marino@smallexample 6946*e4b17023SJohn Marino(define_insn_and_split "zero_extendhisi2_and" 6947*e4b17023SJohn Marino [(set (match_operand:SI 0 "register_operand" "=r") 6948*e4b17023SJohn Marino (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) 6949*e4b17023SJohn Marino (clobber (reg:CC 17))] 6950*e4b17023SJohn Marino "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" 6951*e4b17023SJohn Marino "#" 6952*e4b17023SJohn Marino "&& reload_completed" 6953*e4b17023SJohn Marino [(parallel [(set (match_dup 0) 6954*e4b17023SJohn Marino (and:SI (match_dup 0) (const_int 65535))) 6955*e4b17023SJohn Marino (clobber (reg:CC 17))])] 6956*e4b17023SJohn Marino "" 6957*e4b17023SJohn Marino [(set_attr "type" "alu1")]) 6958*e4b17023SJohn Marino 6959*e4b17023SJohn Marino@end smallexample 6960*e4b17023SJohn Marino 6961*e4b17023SJohn MarinoIn this case, the actual split condition will be 6962*e4b17023SJohn Marino@samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}. 6963*e4b17023SJohn Marino 6964*e4b17023SJohn MarinoThe @code{define_insn_and_split} construction provides exactly the same 6965*e4b17023SJohn Marinofunctionality as two separate @code{define_insn} and @code{define_split} 6966*e4b17023SJohn Marinopatterns. It exists for compactness, and as a maintenance tool to prevent 6967*e4b17023SJohn Marinohaving to ensure the two patterns' templates match. 6968*e4b17023SJohn Marino 6969*e4b17023SJohn Marino@end ifset 6970*e4b17023SJohn Marino@ifset INTERNALS 6971*e4b17023SJohn Marino@node Including Patterns 6972*e4b17023SJohn Marino@section Including Patterns in Machine Descriptions. 6973*e4b17023SJohn Marino@cindex insn includes 6974*e4b17023SJohn Marino 6975*e4b17023SJohn Marino@findex include 6976*e4b17023SJohn MarinoThe @code{include} pattern tells the compiler tools where to 6977*e4b17023SJohn Marinolook for patterns that are in files other than in the file 6978*e4b17023SJohn Marino@file{.md}. This is used only at build time and there is no preprocessing allowed. 6979*e4b17023SJohn Marino 6980*e4b17023SJohn MarinoIt looks like: 6981*e4b17023SJohn Marino 6982*e4b17023SJohn Marino@smallexample 6983*e4b17023SJohn Marino 6984*e4b17023SJohn Marino(include 6985*e4b17023SJohn Marino @var{pathname}) 6986*e4b17023SJohn Marino@end smallexample 6987*e4b17023SJohn Marino 6988*e4b17023SJohn MarinoFor example: 6989*e4b17023SJohn Marino 6990*e4b17023SJohn Marino@smallexample 6991*e4b17023SJohn Marino 6992*e4b17023SJohn Marino(include "filestuff") 6993*e4b17023SJohn Marino 6994*e4b17023SJohn Marino@end smallexample 6995*e4b17023SJohn Marino 6996*e4b17023SJohn MarinoWhere @var{pathname} is a string that specifies the location of the file, 6997*e4b17023SJohn Marinospecifies the include file to be in @file{gcc/config/target/filestuff}. The 6998*e4b17023SJohn Marinodirectory @file{gcc/config/target} is regarded as the default directory. 6999*e4b17023SJohn Marino 7000*e4b17023SJohn Marino 7001*e4b17023SJohn MarinoMachine descriptions may be split up into smaller more manageable subsections 7002*e4b17023SJohn Marinoand placed into subdirectories. 7003*e4b17023SJohn Marino 7004*e4b17023SJohn MarinoBy specifying: 7005*e4b17023SJohn Marino 7006*e4b17023SJohn Marino@smallexample 7007*e4b17023SJohn Marino 7008*e4b17023SJohn Marino(include "BOGUS/filestuff") 7009*e4b17023SJohn Marino 7010*e4b17023SJohn Marino@end smallexample 7011*e4b17023SJohn Marino 7012*e4b17023SJohn Marinothe include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}. 7013*e4b17023SJohn Marino 7014*e4b17023SJohn MarinoSpecifying an absolute path for the include file such as; 7015*e4b17023SJohn Marino@smallexample 7016*e4b17023SJohn Marino 7017*e4b17023SJohn Marino(include "/u2/BOGUS/filestuff") 7018*e4b17023SJohn Marino 7019*e4b17023SJohn Marino@end smallexample 7020*e4b17023SJohn Marinois permitted but is not encouraged. 7021*e4b17023SJohn Marino 7022*e4b17023SJohn Marino@subsection RTL Generation Tool Options for Directory Search 7023*e4b17023SJohn Marino@cindex directory options .md 7024*e4b17023SJohn Marino@cindex options, directory search 7025*e4b17023SJohn Marino@cindex search options 7026*e4b17023SJohn Marino 7027*e4b17023SJohn MarinoThe @option{-I@var{dir}} option specifies directories to search for machine descriptions. 7028*e4b17023SJohn MarinoFor example: 7029*e4b17023SJohn Marino 7030*e4b17023SJohn Marino@smallexample 7031*e4b17023SJohn Marino 7032*e4b17023SJohn Marinogenrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md 7033*e4b17023SJohn Marino 7034*e4b17023SJohn Marino@end smallexample 7035*e4b17023SJohn Marino 7036*e4b17023SJohn Marino 7037*e4b17023SJohn MarinoAdd the directory @var{dir} to the head of the list of directories to be 7038*e4b17023SJohn Marinosearched for header files. This can be used to override a system machine definition 7039*e4b17023SJohn Marinofile, substituting your own version, since these directories are 7040*e4b17023SJohn Marinosearched before the default machine description file directories. If you use more than 7041*e4b17023SJohn Marinoone @option{-I} option, the directories are scanned in left-to-right 7042*e4b17023SJohn Marinoorder; the standard default directory come after. 7043*e4b17023SJohn Marino 7044*e4b17023SJohn Marino 7045*e4b17023SJohn Marino@end ifset 7046*e4b17023SJohn Marino@ifset INTERNALS 7047*e4b17023SJohn Marino@node Peephole Definitions 7048*e4b17023SJohn Marino@section Machine-Specific Peephole Optimizers 7049*e4b17023SJohn Marino@cindex peephole optimizer definitions 7050*e4b17023SJohn Marino@cindex defining peephole optimizers 7051*e4b17023SJohn Marino 7052*e4b17023SJohn MarinoIn addition to instruction patterns the @file{md} file may contain 7053*e4b17023SJohn Marinodefinitions of machine-specific peephole optimizations. 7054*e4b17023SJohn Marino 7055*e4b17023SJohn MarinoThe combiner does not notice certain peephole optimizations when the data 7056*e4b17023SJohn Marinoflow in the program does not suggest that it should try them. For example, 7057*e4b17023SJohn Marinosometimes two consecutive insns related in purpose can be combined even 7058*e4b17023SJohn Marinothough the second one does not appear to use a register computed in the 7059*e4b17023SJohn Marinofirst one. A machine-specific peephole optimizer can detect such 7060*e4b17023SJohn Marinoopportunities. 7061*e4b17023SJohn Marino 7062*e4b17023SJohn MarinoThere are two forms of peephole definitions that may be used. The 7063*e4b17023SJohn Marinooriginal @code{define_peephole} is run at assembly output time to 7064*e4b17023SJohn Marinomatch insns and substitute assembly text. Use of @code{define_peephole} 7065*e4b17023SJohn Marinois deprecated. 7066*e4b17023SJohn Marino 7067*e4b17023SJohn MarinoA newer @code{define_peephole2} matches insns and substitutes new 7068*e4b17023SJohn Marinoinsns. The @code{peephole2} pass is run after register allocation 7069*e4b17023SJohn Marinobut before scheduling, which may result in much better code for 7070*e4b17023SJohn Marinotargets that do scheduling. 7071*e4b17023SJohn Marino 7072*e4b17023SJohn Marino@menu 7073*e4b17023SJohn Marino* define_peephole:: RTL to Text Peephole Optimizers 7074*e4b17023SJohn Marino* define_peephole2:: RTL to RTL Peephole Optimizers 7075*e4b17023SJohn Marino@end menu 7076*e4b17023SJohn Marino 7077*e4b17023SJohn Marino@end ifset 7078*e4b17023SJohn Marino@ifset INTERNALS 7079*e4b17023SJohn Marino@node define_peephole 7080*e4b17023SJohn Marino@subsection RTL to Text Peephole Optimizers 7081*e4b17023SJohn Marino@findex define_peephole 7082*e4b17023SJohn Marino 7083*e4b17023SJohn Marino@need 1000 7084*e4b17023SJohn MarinoA definition looks like this: 7085*e4b17023SJohn Marino 7086*e4b17023SJohn Marino@smallexample 7087*e4b17023SJohn Marino(define_peephole 7088*e4b17023SJohn Marino [@var{insn-pattern-1} 7089*e4b17023SJohn Marino @var{insn-pattern-2} 7090*e4b17023SJohn Marino @dots{}] 7091*e4b17023SJohn Marino "@var{condition}" 7092*e4b17023SJohn Marino "@var{template}" 7093*e4b17023SJohn Marino "@var{optional-insn-attributes}") 7094*e4b17023SJohn Marino@end smallexample 7095*e4b17023SJohn Marino 7096*e4b17023SJohn Marino@noindent 7097*e4b17023SJohn MarinoThe last string operand may be omitted if you are not using any 7098*e4b17023SJohn Marinomachine-specific information in this machine description. If present, 7099*e4b17023SJohn Marinoit must obey the same rules as in a @code{define_insn}. 7100*e4b17023SJohn Marino 7101*e4b17023SJohn MarinoIn this skeleton, @var{insn-pattern-1} and so on are patterns to match 7102*e4b17023SJohn Marinoconsecutive insns. The optimization applies to a sequence of insns when 7103*e4b17023SJohn Marino@var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches 7104*e4b17023SJohn Marinothe next, and so on. 7105*e4b17023SJohn Marino 7106*e4b17023SJohn MarinoEach of the insns matched by a peephole must also match a 7107*e4b17023SJohn Marino@code{define_insn}. Peepholes are checked only at the last stage just 7108*e4b17023SJohn Marinobefore code generation, and only optionally. Therefore, any insn which 7109*e4b17023SJohn Marinowould match a peephole but no @code{define_insn} will cause a crash in code 7110*e4b17023SJohn Marinogeneration in an unoptimized compilation, or at various optimization 7111*e4b17023SJohn Marinostages. 7112*e4b17023SJohn Marino 7113*e4b17023SJohn MarinoThe operands of the insns are matched with @code{match_operands}, 7114*e4b17023SJohn Marino@code{match_operator}, and @code{match_dup}, as usual. What is not 7115*e4b17023SJohn Marinousual is that the operand numbers apply to all the insn patterns in the 7116*e4b17023SJohn Marinodefinition. So, you can check for identical operands in two insns by 7117*e4b17023SJohn Marinousing @code{match_operand} in one insn and @code{match_dup} in the 7118*e4b17023SJohn Marinoother. 7119*e4b17023SJohn Marino 7120*e4b17023SJohn MarinoThe operand constraints used in @code{match_operand} patterns do not have 7121*e4b17023SJohn Marinoany direct effect on the applicability of the peephole, but they will 7122*e4b17023SJohn Marinobe validated afterward, so make sure your constraints are general enough 7123*e4b17023SJohn Marinoto apply whenever the peephole matches. If the peephole matches 7124*e4b17023SJohn Marinobut the constraints are not satisfied, the compiler will crash. 7125*e4b17023SJohn Marino 7126*e4b17023SJohn MarinoIt is safe to omit constraints in all the operands of the peephole; or 7127*e4b17023SJohn Marinoyou can write constraints which serve as a double-check on the criteria 7128*e4b17023SJohn Marinopreviously tested. 7129*e4b17023SJohn Marino 7130*e4b17023SJohn MarinoOnce a sequence of insns matches the patterns, the @var{condition} is 7131*e4b17023SJohn Marinochecked. This is a C expression which makes the final decision whether to 7132*e4b17023SJohn Marinoperform the optimization (we do so if the expression is nonzero). If 7133*e4b17023SJohn Marino@var{condition} is omitted (in other words, the string is empty) then the 7134*e4b17023SJohn Marinooptimization is applied to every sequence of insns that matches the 7135*e4b17023SJohn Marinopatterns. 7136*e4b17023SJohn Marino 7137*e4b17023SJohn MarinoThe defined peephole optimizations are applied after register allocation 7138*e4b17023SJohn Marinois complete. Therefore, the peephole definition can check which 7139*e4b17023SJohn Marinooperands have ended up in which kinds of registers, just by looking at 7140*e4b17023SJohn Marinothe operands. 7141*e4b17023SJohn Marino 7142*e4b17023SJohn Marino@findex prev_active_insn 7143*e4b17023SJohn MarinoThe way to refer to the operands in @var{condition} is to write 7144*e4b17023SJohn Marino@code{operands[@var{i}]} for operand number @var{i} (as matched by 7145*e4b17023SJohn Marino@code{(match_operand @var{i} @dots{})}). Use the variable @code{insn} 7146*e4b17023SJohn Marinoto refer to the last of the insns being matched; use 7147*e4b17023SJohn Marino@code{prev_active_insn} to find the preceding insns. 7148*e4b17023SJohn Marino 7149*e4b17023SJohn Marino@findex dead_or_set_p 7150*e4b17023SJohn MarinoWhen optimizing computations with intermediate results, you can use 7151*e4b17023SJohn Marino@var{condition} to match only when the intermediate results are not used 7152*e4b17023SJohn Marinoelsewhere. Use the C expression @code{dead_or_set_p (@var{insn}, 7153*e4b17023SJohn Marino@var{op})}, where @var{insn} is the insn in which you expect the value 7154*e4b17023SJohn Marinoto be used for the last time (from the value of @code{insn}, together 7155*e4b17023SJohn Marinowith use of @code{prev_nonnote_insn}), and @var{op} is the intermediate 7156*e4b17023SJohn Marinovalue (from @code{operands[@var{i}]}). 7157*e4b17023SJohn Marino 7158*e4b17023SJohn MarinoApplying the optimization means replacing the sequence of insns with one 7159*e4b17023SJohn Marinonew insn. The @var{template} controls ultimate output of assembler code 7160*e4b17023SJohn Marinofor this combined insn. It works exactly like the template of a 7161*e4b17023SJohn Marino@code{define_insn}. Operand numbers in this template are the same ones 7162*e4b17023SJohn Marinoused in matching the original sequence of insns. 7163*e4b17023SJohn Marino 7164*e4b17023SJohn MarinoThe result of a defined peephole optimizer does not need to match any of 7165*e4b17023SJohn Marinothe insn patterns in the machine description; it does not even have an 7166*e4b17023SJohn Marinoopportunity to match them. The peephole optimizer definition itself serves 7167*e4b17023SJohn Marinoas the insn pattern to control how the insn is output. 7168*e4b17023SJohn Marino 7169*e4b17023SJohn MarinoDefined peephole optimizers are run as assembler code is being output, 7170*e4b17023SJohn Marinoso the insns they produce are never combined or rearranged in any way. 7171*e4b17023SJohn Marino 7172*e4b17023SJohn MarinoHere is an example, taken from the 68000 machine description: 7173*e4b17023SJohn Marino 7174*e4b17023SJohn Marino@smallexample 7175*e4b17023SJohn Marino(define_peephole 7176*e4b17023SJohn Marino [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) 7177*e4b17023SJohn Marino (set (match_operand:DF 0 "register_operand" "=f") 7178*e4b17023SJohn Marino (match_operand:DF 1 "register_operand" "ad"))] 7179*e4b17023SJohn Marino "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" 7180*e4b17023SJohn Marino@{ 7181*e4b17023SJohn Marino rtx xoperands[2]; 7182*e4b17023SJohn Marino xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 7183*e4b17023SJohn Marino#ifdef MOTOROLA 7184*e4b17023SJohn Marino output_asm_insn ("move.l %1,(sp)", xoperands); 7185*e4b17023SJohn Marino output_asm_insn ("move.l %1,-(sp)", operands); 7186*e4b17023SJohn Marino return "fmove.d (sp)+,%0"; 7187*e4b17023SJohn Marino#else 7188*e4b17023SJohn Marino output_asm_insn ("movel %1,sp@@", xoperands); 7189*e4b17023SJohn Marino output_asm_insn ("movel %1,sp@@-", operands); 7190*e4b17023SJohn Marino return "fmoved sp@@+,%0"; 7191*e4b17023SJohn Marino#endif 7192*e4b17023SJohn Marino@}) 7193*e4b17023SJohn Marino@end smallexample 7194*e4b17023SJohn Marino 7195*e4b17023SJohn Marino@need 1000 7196*e4b17023SJohn MarinoThe effect of this optimization is to change 7197*e4b17023SJohn Marino 7198*e4b17023SJohn Marino@smallexample 7199*e4b17023SJohn Marino@group 7200*e4b17023SJohn Marinojbsr _foobar 7201*e4b17023SJohn Marinoaddql #4,sp 7202*e4b17023SJohn Marinomovel d1,sp@@- 7203*e4b17023SJohn Marinomovel d0,sp@@- 7204*e4b17023SJohn Marinofmoved sp@@+,fp0 7205*e4b17023SJohn Marino@end group 7206*e4b17023SJohn Marino@end smallexample 7207*e4b17023SJohn Marino 7208*e4b17023SJohn Marino@noindent 7209*e4b17023SJohn Marinointo 7210*e4b17023SJohn Marino 7211*e4b17023SJohn Marino@smallexample 7212*e4b17023SJohn Marino@group 7213*e4b17023SJohn Marinojbsr _foobar 7214*e4b17023SJohn Marinomovel d1,sp@@ 7215*e4b17023SJohn Marinomovel d0,sp@@- 7216*e4b17023SJohn Marinofmoved sp@@+,fp0 7217*e4b17023SJohn Marino@end group 7218*e4b17023SJohn Marino@end smallexample 7219*e4b17023SJohn Marino 7220*e4b17023SJohn Marino@ignore 7221*e4b17023SJohn Marino@findex CC_REVERSED 7222*e4b17023SJohn MarinoIf a peephole matches a sequence including one or more jump insns, you must 7223*e4b17023SJohn Marinotake account of the flags such as @code{CC_REVERSED} which specify that the 7224*e4b17023SJohn Marinocondition codes are represented in an unusual manner. The compiler 7225*e4b17023SJohn Marinoautomatically alters any ordinary conditional jumps which occur in such 7226*e4b17023SJohn Marinosituations, but the compiler cannot alter jumps which have been replaced by 7227*e4b17023SJohn Marinopeephole optimizations. So it is up to you to alter the assembler code 7228*e4b17023SJohn Marinothat the peephole produces. Supply C code to write the assembler output, 7229*e4b17023SJohn Marinoand in this C code check the condition code status flags and change the 7230*e4b17023SJohn Marinoassembler code as appropriate. 7231*e4b17023SJohn Marino@end ignore 7232*e4b17023SJohn Marino 7233*e4b17023SJohn Marino@var{insn-pattern-1} and so on look @emph{almost} like the second 7234*e4b17023SJohn Marinooperand of @code{define_insn}. There is one important difference: the 7235*e4b17023SJohn Marinosecond operand of @code{define_insn} consists of one or more RTX's 7236*e4b17023SJohn Marinoenclosed in square brackets. Usually, there is only one: then the same 7237*e4b17023SJohn Marinoaction can be written as an element of a @code{define_peephole}. But 7238*e4b17023SJohn Marinowhen there are multiple actions in a @code{define_insn}, they are 7239*e4b17023SJohn Marinoimplicitly enclosed in a @code{parallel}. Then you must explicitly 7240*e4b17023SJohn Marinowrite the @code{parallel}, and the square brackets within it, in the 7241*e4b17023SJohn Marino@code{define_peephole}. Thus, if an insn pattern looks like this, 7242*e4b17023SJohn Marino 7243*e4b17023SJohn Marino@smallexample 7244*e4b17023SJohn Marino(define_insn "divmodsi4" 7245*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "=d") 7246*e4b17023SJohn Marino (div:SI (match_operand:SI 1 "general_operand" "0") 7247*e4b17023SJohn Marino (match_operand:SI 2 "general_operand" "dmsK"))) 7248*e4b17023SJohn Marino (set (match_operand:SI 3 "general_operand" "=d") 7249*e4b17023SJohn Marino (mod:SI (match_dup 1) (match_dup 2)))] 7250*e4b17023SJohn Marino "TARGET_68020" 7251*e4b17023SJohn Marino "divsl%.l %2,%3:%0") 7252*e4b17023SJohn Marino@end smallexample 7253*e4b17023SJohn Marino 7254*e4b17023SJohn Marino@noindent 7255*e4b17023SJohn Marinothen the way to mention this insn in a peephole is as follows: 7256*e4b17023SJohn Marino 7257*e4b17023SJohn Marino@smallexample 7258*e4b17023SJohn Marino(define_peephole 7259*e4b17023SJohn Marino [@dots{} 7260*e4b17023SJohn Marino (parallel 7261*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "=d") 7262*e4b17023SJohn Marino (div:SI (match_operand:SI 1 "general_operand" "0") 7263*e4b17023SJohn Marino (match_operand:SI 2 "general_operand" "dmsK"))) 7264*e4b17023SJohn Marino (set (match_operand:SI 3 "general_operand" "=d") 7265*e4b17023SJohn Marino (mod:SI (match_dup 1) (match_dup 2)))]) 7266*e4b17023SJohn Marino @dots{}] 7267*e4b17023SJohn Marino @dots{}) 7268*e4b17023SJohn Marino@end smallexample 7269*e4b17023SJohn Marino 7270*e4b17023SJohn Marino@end ifset 7271*e4b17023SJohn Marino@ifset INTERNALS 7272*e4b17023SJohn Marino@node define_peephole2 7273*e4b17023SJohn Marino@subsection RTL to RTL Peephole Optimizers 7274*e4b17023SJohn Marino@findex define_peephole2 7275*e4b17023SJohn Marino 7276*e4b17023SJohn MarinoThe @code{define_peephole2} definition tells the compiler how to 7277*e4b17023SJohn Marinosubstitute one sequence of instructions for another sequence, 7278*e4b17023SJohn Marinowhat additional scratch registers may be needed and what their 7279*e4b17023SJohn Marinolifetimes must be. 7280*e4b17023SJohn Marino 7281*e4b17023SJohn Marino@smallexample 7282*e4b17023SJohn Marino(define_peephole2 7283*e4b17023SJohn Marino [@var{insn-pattern-1} 7284*e4b17023SJohn Marino @var{insn-pattern-2} 7285*e4b17023SJohn Marino @dots{}] 7286*e4b17023SJohn Marino "@var{condition}" 7287*e4b17023SJohn Marino [@var{new-insn-pattern-1} 7288*e4b17023SJohn Marino @var{new-insn-pattern-2} 7289*e4b17023SJohn Marino @dots{}] 7290*e4b17023SJohn Marino "@var{preparation-statements}") 7291*e4b17023SJohn Marino@end smallexample 7292*e4b17023SJohn Marino 7293*e4b17023SJohn MarinoThe definition is almost identical to @code{define_split} 7294*e4b17023SJohn Marino(@pxref{Insn Splitting}) except that the pattern to match is not a 7295*e4b17023SJohn Marinosingle instruction, but a sequence of instructions. 7296*e4b17023SJohn Marino 7297*e4b17023SJohn MarinoIt is possible to request additional scratch registers for use in the 7298*e4b17023SJohn Marinooutput template. If appropriate registers are not free, the pattern 7299*e4b17023SJohn Marinowill simply not match. 7300*e4b17023SJohn Marino 7301*e4b17023SJohn Marino@findex match_scratch 7302*e4b17023SJohn Marino@findex match_dup 7303*e4b17023SJohn MarinoScratch registers are requested with a @code{match_scratch} pattern at 7304*e4b17023SJohn Marinothe top level of the input pattern. The allocated register (initially) will 7305*e4b17023SJohn Marinobe dead at the point requested within the original sequence. If the scratch 7306*e4b17023SJohn Marinois used at more than a single point, a @code{match_dup} pattern at the 7307*e4b17023SJohn Marinotop level of the input pattern marks the last position in the input sequence 7308*e4b17023SJohn Marinoat which the register must be available. 7309*e4b17023SJohn Marino 7310*e4b17023SJohn MarinoHere is an example from the IA-32 machine description: 7311*e4b17023SJohn Marino 7312*e4b17023SJohn Marino@smallexample 7313*e4b17023SJohn Marino(define_peephole2 7314*e4b17023SJohn Marino [(match_scratch:SI 2 "r") 7315*e4b17023SJohn Marino (parallel [(set (match_operand:SI 0 "register_operand" "") 7316*e4b17023SJohn Marino (match_operator:SI 3 "arith_or_logical_operator" 7317*e4b17023SJohn Marino [(match_dup 0) 7318*e4b17023SJohn Marino (match_operand:SI 1 "memory_operand" "")])) 7319*e4b17023SJohn Marino (clobber (reg:CC 17))])] 7320*e4b17023SJohn Marino "! optimize_size && ! TARGET_READ_MODIFY" 7321*e4b17023SJohn Marino [(set (match_dup 2) (match_dup 1)) 7322*e4b17023SJohn Marino (parallel [(set (match_dup 0) 7323*e4b17023SJohn Marino (match_op_dup 3 [(match_dup 0) (match_dup 2)])) 7324*e4b17023SJohn Marino (clobber (reg:CC 17))])] 7325*e4b17023SJohn Marino "") 7326*e4b17023SJohn Marino@end smallexample 7327*e4b17023SJohn Marino 7328*e4b17023SJohn Marino@noindent 7329*e4b17023SJohn MarinoThis pattern tries to split a load from its use in the hopes that we'll be 7330*e4b17023SJohn Marinoable to schedule around the memory load latency. It allocates a single 7331*e4b17023SJohn Marino@code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs 7332*e4b17023SJohn Marinoto be live only at the point just before the arithmetic. 7333*e4b17023SJohn Marino 7334*e4b17023SJohn MarinoA real example requiring extended scratch lifetimes is harder to come by, 7335*e4b17023SJohn Marinoso here's a silly made-up example: 7336*e4b17023SJohn Marino 7337*e4b17023SJohn Marino@smallexample 7338*e4b17023SJohn Marino(define_peephole2 7339*e4b17023SJohn Marino [(match_scratch:SI 4 "r") 7340*e4b17023SJohn Marino (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) 7341*e4b17023SJohn Marino (set (match_operand:SI 2 "" "") (match_dup 1)) 7342*e4b17023SJohn Marino (match_dup 4) 7343*e4b17023SJohn Marino (set (match_operand:SI 3 "" "") (match_dup 1))] 7344*e4b17023SJohn Marino "/* @r{determine 1 does not overlap 0 and 2} */" 7345*e4b17023SJohn Marino [(set (match_dup 4) (match_dup 1)) 7346*e4b17023SJohn Marino (set (match_dup 0) (match_dup 4)) 7347*e4b17023SJohn Marino (set (match_dup 2) (match_dup 4))] 7348*e4b17023SJohn Marino (set (match_dup 3) (match_dup 4))] 7349*e4b17023SJohn Marino "") 7350*e4b17023SJohn Marino@end smallexample 7351*e4b17023SJohn Marino 7352*e4b17023SJohn Marino@noindent 7353*e4b17023SJohn MarinoIf we had not added the @code{(match_dup 4)} in the middle of the input 7354*e4b17023SJohn Marinosequence, it might have been the case that the register we chose at the 7355*e4b17023SJohn Marinobeginning of the sequence is killed by the first or second @code{set}. 7356*e4b17023SJohn Marino 7357*e4b17023SJohn Marino@end ifset 7358*e4b17023SJohn Marino@ifset INTERNALS 7359*e4b17023SJohn Marino@node Insn Attributes 7360*e4b17023SJohn Marino@section Instruction Attributes 7361*e4b17023SJohn Marino@cindex insn attributes 7362*e4b17023SJohn Marino@cindex instruction attributes 7363*e4b17023SJohn Marino 7364*e4b17023SJohn MarinoIn addition to describing the instruction supported by the target machine, 7365*e4b17023SJohn Marinothe @file{md} file also defines a group of @dfn{attributes} and a set of 7366*e4b17023SJohn Marinovalues for each. Every generated insn is assigned a value for each attribute. 7367*e4b17023SJohn MarinoOne possible attribute would be the effect that the insn has on the machine's 7368*e4b17023SJohn Marinocondition code. This attribute can then be used by @code{NOTICE_UPDATE_CC} 7369*e4b17023SJohn Marinoto track the condition codes. 7370*e4b17023SJohn Marino 7371*e4b17023SJohn Marino@menu 7372*e4b17023SJohn Marino* Defining Attributes:: Specifying attributes and their values. 7373*e4b17023SJohn Marino* Expressions:: Valid expressions for attribute values. 7374*e4b17023SJohn Marino* Tagging Insns:: Assigning attribute values to insns. 7375*e4b17023SJohn Marino* Attr Example:: An example of assigning attributes. 7376*e4b17023SJohn Marino* Insn Lengths:: Computing the length of insns. 7377*e4b17023SJohn Marino* Constant Attributes:: Defining attributes that are constant. 7378*e4b17023SJohn Marino* Delay Slots:: Defining delay slots required for a machine. 7379*e4b17023SJohn Marino* Processor pipeline description:: Specifying information for insn scheduling. 7380*e4b17023SJohn Marino@end menu 7381*e4b17023SJohn Marino 7382*e4b17023SJohn Marino@end ifset 7383*e4b17023SJohn Marino@ifset INTERNALS 7384*e4b17023SJohn Marino@node Defining Attributes 7385*e4b17023SJohn Marino@subsection Defining Attributes and their Values 7386*e4b17023SJohn Marino@cindex defining attributes and their values 7387*e4b17023SJohn Marino@cindex attributes, defining 7388*e4b17023SJohn Marino 7389*e4b17023SJohn Marino@findex define_attr 7390*e4b17023SJohn MarinoThe @code{define_attr} expression is used to define each attribute required 7391*e4b17023SJohn Marinoby the target machine. It looks like: 7392*e4b17023SJohn Marino 7393*e4b17023SJohn Marino@smallexample 7394*e4b17023SJohn Marino(define_attr @var{name} @var{list-of-values} @var{default}) 7395*e4b17023SJohn Marino@end smallexample 7396*e4b17023SJohn Marino 7397*e4b17023SJohn Marino@var{name} is a string specifying the name of the attribute being defined. 7398*e4b17023SJohn MarinoSome attributes are used in a special way by the rest of the compiler. The 7399*e4b17023SJohn Marino@code{enabled} attribute can be used to conditionally enable or disable 7400*e4b17023SJohn Marinoinsn alternatives (@pxref{Disable Insn Alternatives}). The @code{predicable} 7401*e4b17023SJohn Marinoattribute, together with a suitable @code{define_cond_exec} 7402*e4b17023SJohn Marino(@pxref{Conditional Execution}), can be used to automatically generate 7403*e4b17023SJohn Marinoconditional variants of instruction patterns. The compiler internally uses 7404*e4b17023SJohn Marinothe names @code{ce_enabled} and @code{nonce_enabled}, so they should not be 7405*e4b17023SJohn Marinoused elsewhere as alternative names. 7406*e4b17023SJohn Marino 7407*e4b17023SJohn Marino@var{list-of-values} is either a string that specifies a comma-separated 7408*e4b17023SJohn Marinolist of values that can be assigned to the attribute, or a null string to 7409*e4b17023SJohn Marinoindicate that the attribute takes numeric values. 7410*e4b17023SJohn Marino 7411*e4b17023SJohn Marino@var{default} is an attribute expression that gives the value of this 7412*e4b17023SJohn Marinoattribute for insns that match patterns whose definition does not include 7413*e4b17023SJohn Marinoan explicit value for this attribute. @xref{Attr Example}, for more 7414*e4b17023SJohn Marinoinformation on the handling of defaults. @xref{Constant Attributes}, 7415*e4b17023SJohn Marinofor information on attributes that do not depend on any particular insn. 7416*e4b17023SJohn Marino 7417*e4b17023SJohn Marino@findex insn-attr.h 7418*e4b17023SJohn MarinoFor each defined attribute, a number of definitions are written to the 7419*e4b17023SJohn Marino@file{insn-attr.h} file. For cases where an explicit set of values is 7420*e4b17023SJohn Marinospecified for an attribute, the following are defined: 7421*e4b17023SJohn Marino 7422*e4b17023SJohn Marino@itemize @bullet 7423*e4b17023SJohn Marino@item 7424*e4b17023SJohn MarinoA @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}. 7425*e4b17023SJohn Marino 7426*e4b17023SJohn Marino@item 7427*e4b17023SJohn MarinoAn enumerated class is defined for @samp{attr_@var{name}} with 7428*e4b17023SJohn Marinoelements of the form @samp{@var{upper-name}_@var{upper-value}} where 7429*e4b17023SJohn Marinothe attribute name and value are first converted to uppercase. 7430*e4b17023SJohn Marino 7431*e4b17023SJohn Marino@item 7432*e4b17023SJohn MarinoA function @samp{get_attr_@var{name}} is defined that is passed an insn and 7433*e4b17023SJohn Marinoreturns the attribute value for that insn. 7434*e4b17023SJohn Marino@end itemize 7435*e4b17023SJohn Marino 7436*e4b17023SJohn MarinoFor example, if the following is present in the @file{md} file: 7437*e4b17023SJohn Marino 7438*e4b17023SJohn Marino@smallexample 7439*e4b17023SJohn Marino(define_attr "type" "branch,fp,load,store,arith" @dots{}) 7440*e4b17023SJohn Marino@end smallexample 7441*e4b17023SJohn Marino 7442*e4b17023SJohn Marino@noindent 7443*e4b17023SJohn Marinothe following lines will be written to the file @file{insn-attr.h}. 7444*e4b17023SJohn Marino 7445*e4b17023SJohn Marino@smallexample 7446*e4b17023SJohn Marino#define HAVE_ATTR_type 7447*e4b17023SJohn Marinoenum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD, 7448*e4b17023SJohn Marino TYPE_STORE, TYPE_ARITH@}; 7449*e4b17023SJohn Marinoextern enum attr_type get_attr_type (); 7450*e4b17023SJohn Marino@end smallexample 7451*e4b17023SJohn Marino 7452*e4b17023SJohn MarinoIf the attribute takes numeric values, no @code{enum} type will be 7453*e4b17023SJohn Marinodefined and the function to obtain the attribute's value will return 7454*e4b17023SJohn Marino@code{int}. 7455*e4b17023SJohn Marino 7456*e4b17023SJohn MarinoThere are attributes which are tied to a specific meaning. These 7457*e4b17023SJohn Marinoattributes are not free to use for other purposes: 7458*e4b17023SJohn Marino 7459*e4b17023SJohn Marino@table @code 7460*e4b17023SJohn Marino@item length 7461*e4b17023SJohn MarinoThe @code{length} attribute is used to calculate the length of emitted 7462*e4b17023SJohn Marinocode chunks. This is especially important when verifying branch 7463*e4b17023SJohn Marinodistances. @xref{Insn Lengths}. 7464*e4b17023SJohn Marino 7465*e4b17023SJohn Marino@item enabled 7466*e4b17023SJohn MarinoThe @code{enabled} attribute can be defined to prevent certain 7467*e4b17023SJohn Marinoalternatives of an insn definition from being used during code 7468*e4b17023SJohn Marinogeneration. @xref{Disable Insn Alternatives}. 7469*e4b17023SJohn Marino@end table 7470*e4b17023SJohn Marino 7471*e4b17023SJohn Marino@findex define_enum_attr 7472*e4b17023SJohn Marino@anchor{define_enum_attr} 7473*e4b17023SJohn MarinoAnother way of defining an attribute is to use: 7474*e4b17023SJohn Marino 7475*e4b17023SJohn Marino@smallexample 7476*e4b17023SJohn Marino(define_enum_attr "@var{attr}" "@var{enum}" @var{default}) 7477*e4b17023SJohn Marino@end smallexample 7478*e4b17023SJohn Marino 7479*e4b17023SJohn MarinoThis works in just the same way as @code{define_attr}, except that 7480*e4b17023SJohn Marinothe list of values is taken from a separate enumeration called 7481*e4b17023SJohn Marino@var{enum} (@pxref{define_enum}). This form allows you to use 7482*e4b17023SJohn Marinothe same list of values for several attributes without having to 7483*e4b17023SJohn Marinorepeat the list each time. For example: 7484*e4b17023SJohn Marino 7485*e4b17023SJohn Marino@smallexample 7486*e4b17023SJohn Marino(define_enum "processor" [ 7487*e4b17023SJohn Marino model_a 7488*e4b17023SJohn Marino model_b 7489*e4b17023SJohn Marino @dots{} 7490*e4b17023SJohn Marino]) 7491*e4b17023SJohn Marino(define_enum_attr "arch" "processor" 7492*e4b17023SJohn Marino (const (symbol_ref "target_arch"))) 7493*e4b17023SJohn Marino(define_enum_attr "tune" "processor" 7494*e4b17023SJohn Marino (const (symbol_ref "target_tune"))) 7495*e4b17023SJohn Marino@end smallexample 7496*e4b17023SJohn Marino 7497*e4b17023SJohn Marinodefines the same attributes as: 7498*e4b17023SJohn Marino 7499*e4b17023SJohn Marino@smallexample 7500*e4b17023SJohn Marino(define_attr "arch" "model_a,model_b,@dots{}" 7501*e4b17023SJohn Marino (const (symbol_ref "target_arch"))) 7502*e4b17023SJohn Marino(define_attr "tune" "model_a,model_b,@dots{}" 7503*e4b17023SJohn Marino (const (symbol_ref "target_tune"))) 7504*e4b17023SJohn Marino@end smallexample 7505*e4b17023SJohn Marino 7506*e4b17023SJohn Marinobut without duplicating the processor list. The second example defines two 7507*e4b17023SJohn Marinoseparate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first 7508*e4b17023SJohn Marinodefines a single C enum (@code{processor}). 7509*e4b17023SJohn Marino@end ifset 7510*e4b17023SJohn Marino@ifset INTERNALS 7511*e4b17023SJohn Marino@node Expressions 7512*e4b17023SJohn Marino@subsection Attribute Expressions 7513*e4b17023SJohn Marino@cindex attribute expressions 7514*e4b17023SJohn Marino 7515*e4b17023SJohn MarinoRTL expressions used to define attributes use the codes described above 7516*e4b17023SJohn Marinoplus a few specific to attribute definitions, to be discussed below. 7517*e4b17023SJohn MarinoAttribute value expressions must have one of the following forms: 7518*e4b17023SJohn Marino 7519*e4b17023SJohn Marino@table @code 7520*e4b17023SJohn Marino@cindex @code{const_int} and attributes 7521*e4b17023SJohn Marino@item (const_int @var{i}) 7522*e4b17023SJohn MarinoThe integer @var{i} specifies the value of a numeric attribute. @var{i} 7523*e4b17023SJohn Marinomust be non-negative. 7524*e4b17023SJohn Marino 7525*e4b17023SJohn MarinoThe value of a numeric attribute can be specified either with a 7526*e4b17023SJohn Marino@code{const_int}, or as an integer represented as a string in 7527*e4b17023SJohn Marino@code{const_string}, @code{eq_attr} (see below), @code{attr}, 7528*e4b17023SJohn Marino@code{symbol_ref}, simple arithmetic expressions, and @code{set_attr} 7529*e4b17023SJohn Marinooverrides on specific instructions (@pxref{Tagging Insns}). 7530*e4b17023SJohn Marino 7531*e4b17023SJohn Marino@cindex @code{const_string} and attributes 7532*e4b17023SJohn Marino@item (const_string @var{value}) 7533*e4b17023SJohn MarinoThe string @var{value} specifies a constant attribute value. 7534*e4b17023SJohn MarinoIf @var{value} is specified as @samp{"*"}, it means that the default value of 7535*e4b17023SJohn Marinothe attribute is to be used for the insn containing this expression. 7536*e4b17023SJohn Marino@samp{"*"} obviously cannot be used in the @var{default} expression 7537*e4b17023SJohn Marinoof a @code{define_attr}. 7538*e4b17023SJohn Marino 7539*e4b17023SJohn MarinoIf the attribute whose value is being specified is numeric, @var{value} 7540*e4b17023SJohn Marinomust be a string containing a non-negative integer (normally 7541*e4b17023SJohn Marino@code{const_int} would be used in this case). Otherwise, it must 7542*e4b17023SJohn Marinocontain one of the valid values for the attribute. 7543*e4b17023SJohn Marino 7544*e4b17023SJohn Marino@cindex @code{if_then_else} and attributes 7545*e4b17023SJohn Marino@item (if_then_else @var{test} @var{true-value} @var{false-value}) 7546*e4b17023SJohn Marino@var{test} specifies an attribute test, whose format is defined below. 7547*e4b17023SJohn MarinoThe value of this expression is @var{true-value} if @var{test} is true, 7548*e4b17023SJohn Marinootherwise it is @var{false-value}. 7549*e4b17023SJohn Marino 7550*e4b17023SJohn Marino@cindex @code{cond} and attributes 7551*e4b17023SJohn Marino@item (cond [@var{test1} @var{value1} @dots{}] @var{default}) 7552*e4b17023SJohn MarinoThe first operand of this expression is a vector containing an even 7553*e4b17023SJohn Marinonumber of expressions and consisting of pairs of @var{test} and @var{value} 7554*e4b17023SJohn Marinoexpressions. The value of the @code{cond} expression is that of the 7555*e4b17023SJohn Marino@var{value} corresponding to the first true @var{test} expression. If 7556*e4b17023SJohn Marinonone of the @var{test} expressions are true, the value of the @code{cond} 7557*e4b17023SJohn Marinoexpression is that of the @var{default} expression. 7558*e4b17023SJohn Marino@end table 7559*e4b17023SJohn Marino 7560*e4b17023SJohn Marino@var{test} expressions can have one of the following forms: 7561*e4b17023SJohn Marino 7562*e4b17023SJohn Marino@table @code 7563*e4b17023SJohn Marino@cindex @code{const_int} and attribute tests 7564*e4b17023SJohn Marino@item (const_int @var{i}) 7565*e4b17023SJohn MarinoThis test is true if @var{i} is nonzero and false otherwise. 7566*e4b17023SJohn Marino 7567*e4b17023SJohn Marino@cindex @code{not} and attributes 7568*e4b17023SJohn Marino@cindex @code{ior} and attributes 7569*e4b17023SJohn Marino@cindex @code{and} and attributes 7570*e4b17023SJohn Marino@item (not @var{test}) 7571*e4b17023SJohn Marino@itemx (ior @var{test1} @var{test2}) 7572*e4b17023SJohn Marino@itemx (and @var{test1} @var{test2}) 7573*e4b17023SJohn MarinoThese tests are true if the indicated logical function is true. 7574*e4b17023SJohn Marino 7575*e4b17023SJohn Marino@cindex @code{match_operand} and attributes 7576*e4b17023SJohn Marino@item (match_operand:@var{m} @var{n} @var{pred} @var{constraints}) 7577*e4b17023SJohn MarinoThis test is true if operand @var{n} of the insn whose attribute value 7578*e4b17023SJohn Marinois being determined has mode @var{m} (this part of the test is ignored 7579*e4b17023SJohn Marinoif @var{m} is @code{VOIDmode}) and the function specified by the string 7580*e4b17023SJohn Marino@var{pred} returns a nonzero value when passed operand @var{n} and mode 7581*e4b17023SJohn Marino@var{m} (this part of the test is ignored if @var{pred} is the null 7582*e4b17023SJohn Marinostring). 7583*e4b17023SJohn Marino 7584*e4b17023SJohn MarinoThe @var{constraints} operand is ignored and should be the null string. 7585*e4b17023SJohn Marino 7586*e4b17023SJohn Marino@cindex @code{match_test} and attributes 7587*e4b17023SJohn Marino@item (match_test @var{c-expr}) 7588*e4b17023SJohn MarinoThe test is true if C expression @var{c-expr} is true. In non-constant 7589*e4b17023SJohn Marinoattributes, @var{c-expr} has access to the following variables: 7590*e4b17023SJohn Marino 7591*e4b17023SJohn Marino@table @var 7592*e4b17023SJohn Marino@item insn 7593*e4b17023SJohn MarinoThe rtl instruction under test. 7594*e4b17023SJohn Marino@item which_alternative 7595*e4b17023SJohn MarinoThe @code{define_insn} alternative that @var{insn} matches. 7596*e4b17023SJohn Marino@xref{Output Statement}. 7597*e4b17023SJohn Marino@item operands 7598*e4b17023SJohn MarinoAn array of @var{insn}'s rtl operands. 7599*e4b17023SJohn Marino@end table 7600*e4b17023SJohn Marino 7601*e4b17023SJohn Marino@var{c-expr} behaves like the condition in a C @code{if} statement, 7602*e4b17023SJohn Marinoso there is no need to explicitly convert the expression into a boolean 7603*e4b17023SJohn Marino0 or 1 value. For example, the following two tests are equivalent: 7604*e4b17023SJohn Marino 7605*e4b17023SJohn Marino@smallexample 7606*e4b17023SJohn Marino(match_test "x & 2") 7607*e4b17023SJohn Marino(match_test "(x & 2) != 0") 7608*e4b17023SJohn Marino@end smallexample 7609*e4b17023SJohn Marino 7610*e4b17023SJohn Marino@cindex @code{le} and attributes 7611*e4b17023SJohn Marino@cindex @code{leu} and attributes 7612*e4b17023SJohn Marino@cindex @code{lt} and attributes 7613*e4b17023SJohn Marino@cindex @code{gt} and attributes 7614*e4b17023SJohn Marino@cindex @code{gtu} and attributes 7615*e4b17023SJohn Marino@cindex @code{ge} and attributes 7616*e4b17023SJohn Marino@cindex @code{geu} and attributes 7617*e4b17023SJohn Marino@cindex @code{ne} and attributes 7618*e4b17023SJohn Marino@cindex @code{eq} and attributes 7619*e4b17023SJohn Marino@cindex @code{plus} and attributes 7620*e4b17023SJohn Marino@cindex @code{minus} and attributes 7621*e4b17023SJohn Marino@cindex @code{mult} and attributes 7622*e4b17023SJohn Marino@cindex @code{div} and attributes 7623*e4b17023SJohn Marino@cindex @code{mod} and attributes 7624*e4b17023SJohn Marino@cindex @code{abs} and attributes 7625*e4b17023SJohn Marino@cindex @code{neg} and attributes 7626*e4b17023SJohn Marino@cindex @code{ashift} and attributes 7627*e4b17023SJohn Marino@cindex @code{lshiftrt} and attributes 7628*e4b17023SJohn Marino@cindex @code{ashiftrt} and attributes 7629*e4b17023SJohn Marino@item (le @var{arith1} @var{arith2}) 7630*e4b17023SJohn Marino@itemx (leu @var{arith1} @var{arith2}) 7631*e4b17023SJohn Marino@itemx (lt @var{arith1} @var{arith2}) 7632*e4b17023SJohn Marino@itemx (ltu @var{arith1} @var{arith2}) 7633*e4b17023SJohn Marino@itemx (gt @var{arith1} @var{arith2}) 7634*e4b17023SJohn Marino@itemx (gtu @var{arith1} @var{arith2}) 7635*e4b17023SJohn Marino@itemx (ge @var{arith1} @var{arith2}) 7636*e4b17023SJohn Marino@itemx (geu @var{arith1} @var{arith2}) 7637*e4b17023SJohn Marino@itemx (ne @var{arith1} @var{arith2}) 7638*e4b17023SJohn Marino@itemx (eq @var{arith1} @var{arith2}) 7639*e4b17023SJohn MarinoThese tests are true if the indicated comparison of the two arithmetic 7640*e4b17023SJohn Marinoexpressions is true. Arithmetic expressions are formed with 7641*e4b17023SJohn Marino@code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod}, 7642*e4b17023SJohn Marino@code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not}, 7643*e4b17023SJohn Marino@code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions. 7644*e4b17023SJohn Marino 7645*e4b17023SJohn Marino@findex get_attr 7646*e4b17023SJohn Marino@code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn 7647*e4b17023SJohn MarinoLengths},for additional forms). @code{symbol_ref} is a string 7648*e4b17023SJohn Marinodenoting a C expression that yields an @code{int} when evaluated by the 7649*e4b17023SJohn Marino@samp{get_attr_@dots{}} routine. It should normally be a global 7650*e4b17023SJohn Marinovariable. 7651*e4b17023SJohn Marino 7652*e4b17023SJohn Marino@findex eq_attr 7653*e4b17023SJohn Marino@item (eq_attr @var{name} @var{value}) 7654*e4b17023SJohn Marino@var{name} is a string specifying the name of an attribute. 7655*e4b17023SJohn Marino 7656*e4b17023SJohn Marino@var{value} is a string that is either a valid value for attribute 7657*e4b17023SJohn Marino@var{name}, a comma-separated list of values, or @samp{!} followed by a 7658*e4b17023SJohn Marinovalue or list. If @var{value} does not begin with a @samp{!}, this 7659*e4b17023SJohn Marinotest is true if the value of the @var{name} attribute of the current 7660*e4b17023SJohn Marinoinsn is in the list specified by @var{value}. If @var{value} begins 7661*e4b17023SJohn Marinowith a @samp{!}, this test is true if the attribute's value is 7662*e4b17023SJohn Marino@emph{not} in the specified list. 7663*e4b17023SJohn Marino 7664*e4b17023SJohn MarinoFor example, 7665*e4b17023SJohn Marino 7666*e4b17023SJohn Marino@smallexample 7667*e4b17023SJohn Marino(eq_attr "type" "load,store") 7668*e4b17023SJohn Marino@end smallexample 7669*e4b17023SJohn Marino 7670*e4b17023SJohn Marino@noindent 7671*e4b17023SJohn Marinois equivalent to 7672*e4b17023SJohn Marino 7673*e4b17023SJohn Marino@smallexample 7674*e4b17023SJohn Marino(ior (eq_attr "type" "load") (eq_attr "type" "store")) 7675*e4b17023SJohn Marino@end smallexample 7676*e4b17023SJohn Marino 7677*e4b17023SJohn MarinoIf @var{name} specifies an attribute of @samp{alternative}, it refers to the 7678*e4b17023SJohn Marinovalue of the compiler variable @code{which_alternative} 7679*e4b17023SJohn Marino(@pxref{Output Statement}) and the values must be small integers. For 7680*e4b17023SJohn Marinoexample, 7681*e4b17023SJohn Marino 7682*e4b17023SJohn Marino@smallexample 7683*e4b17023SJohn Marino(eq_attr "alternative" "2,3") 7684*e4b17023SJohn Marino@end smallexample 7685*e4b17023SJohn Marino 7686*e4b17023SJohn Marino@noindent 7687*e4b17023SJohn Marinois equivalent to 7688*e4b17023SJohn Marino 7689*e4b17023SJohn Marino@smallexample 7690*e4b17023SJohn Marino(ior (eq (symbol_ref "which_alternative") (const_int 2)) 7691*e4b17023SJohn Marino (eq (symbol_ref "which_alternative") (const_int 3))) 7692*e4b17023SJohn Marino@end smallexample 7693*e4b17023SJohn Marino 7694*e4b17023SJohn MarinoNote that, for most attributes, an @code{eq_attr} test is simplified in cases 7695*e4b17023SJohn Marinowhere the value of the attribute being tested is known for all insns matching 7696*e4b17023SJohn Marinoa particular pattern. This is by far the most common case. 7697*e4b17023SJohn Marino 7698*e4b17023SJohn Marino@findex attr_flag 7699*e4b17023SJohn Marino@item (attr_flag @var{name}) 7700*e4b17023SJohn MarinoThe value of an @code{attr_flag} expression is true if the flag 7701*e4b17023SJohn Marinospecified by @var{name} is true for the @code{insn} currently being 7702*e4b17023SJohn Marinoscheduled. 7703*e4b17023SJohn Marino 7704*e4b17023SJohn Marino@var{name} is a string specifying one of a fixed set of flags to test. 7705*e4b17023SJohn MarinoTest the flags @code{forward} and @code{backward} to determine the 7706*e4b17023SJohn Marinodirection of a conditional branch. Test the flags @code{very_likely}, 7707*e4b17023SJohn Marino@code{likely}, @code{very_unlikely}, and @code{unlikely} to determine 7708*e4b17023SJohn Marinoif a conditional branch is expected to be taken. 7709*e4b17023SJohn Marino 7710*e4b17023SJohn MarinoIf the @code{very_likely} flag is true, then the @code{likely} flag is also 7711*e4b17023SJohn Marinotrue. Likewise for the @code{very_unlikely} and @code{unlikely} flags. 7712*e4b17023SJohn Marino 7713*e4b17023SJohn MarinoThis example describes a conditional branch delay slot which 7714*e4b17023SJohn Marinocan be nullified for forward branches that are taken (annul-true) or 7715*e4b17023SJohn Marinofor backward branches which are not taken (annul-false). 7716*e4b17023SJohn Marino 7717*e4b17023SJohn Marino@smallexample 7718*e4b17023SJohn Marino(define_delay (eq_attr "type" "cbranch") 7719*e4b17023SJohn Marino [(eq_attr "in_branch_delay" "true") 7720*e4b17023SJohn Marino (and (eq_attr "in_branch_delay" "true") 7721*e4b17023SJohn Marino (attr_flag "forward")) 7722*e4b17023SJohn Marino (and (eq_attr "in_branch_delay" "true") 7723*e4b17023SJohn Marino (attr_flag "backward"))]) 7724*e4b17023SJohn Marino@end smallexample 7725*e4b17023SJohn Marino 7726*e4b17023SJohn MarinoThe @code{forward} and @code{backward} flags are false if the current 7727*e4b17023SJohn Marino@code{insn} being scheduled is not a conditional branch. 7728*e4b17023SJohn Marino 7729*e4b17023SJohn MarinoThe @code{very_likely} and @code{likely} flags are true if the 7730*e4b17023SJohn Marino@code{insn} being scheduled is not a conditional branch. 7731*e4b17023SJohn MarinoThe @code{very_unlikely} and @code{unlikely} flags are false if the 7732*e4b17023SJohn Marino@code{insn} being scheduled is not a conditional branch. 7733*e4b17023SJohn Marino 7734*e4b17023SJohn Marino@code{attr_flag} is only used during delay slot scheduling and has no 7735*e4b17023SJohn Marinomeaning to other passes of the compiler. 7736*e4b17023SJohn Marino 7737*e4b17023SJohn Marino@findex attr 7738*e4b17023SJohn Marino@item (attr @var{name}) 7739*e4b17023SJohn MarinoThe value of another attribute is returned. This is most useful 7740*e4b17023SJohn Marinofor numeric attributes, as @code{eq_attr} and @code{attr_flag} 7741*e4b17023SJohn Marinoproduce more efficient code for non-numeric attributes. 7742*e4b17023SJohn Marino@end table 7743*e4b17023SJohn Marino 7744*e4b17023SJohn Marino@end ifset 7745*e4b17023SJohn Marino@ifset INTERNALS 7746*e4b17023SJohn Marino@node Tagging Insns 7747*e4b17023SJohn Marino@subsection Assigning Attribute Values to Insns 7748*e4b17023SJohn Marino@cindex tagging insns 7749*e4b17023SJohn Marino@cindex assigning attribute values to insns 7750*e4b17023SJohn Marino 7751*e4b17023SJohn MarinoThe value assigned to an attribute of an insn is primarily determined by 7752*e4b17023SJohn Marinowhich pattern is matched by that insn (or which @code{define_peephole} 7753*e4b17023SJohn Marinogenerated it). Every @code{define_insn} and @code{define_peephole} can 7754*e4b17023SJohn Marinohave an optional last argument to specify the values of attributes for 7755*e4b17023SJohn Marinomatching insns. The value of any attribute not specified in a particular 7756*e4b17023SJohn Marinoinsn is set to the default value for that attribute, as specified in its 7757*e4b17023SJohn Marino@code{define_attr}. Extensive use of default values for attributes 7758*e4b17023SJohn Marinopermits the specification of the values for only one or two attributes 7759*e4b17023SJohn Marinoin the definition of most insn patterns, as seen in the example in the 7760*e4b17023SJohn Marinonext section. 7761*e4b17023SJohn Marino 7762*e4b17023SJohn MarinoThe optional last argument of @code{define_insn} and 7763*e4b17023SJohn Marino@code{define_peephole} is a vector of expressions, each of which defines 7764*e4b17023SJohn Marinothe value for a single attribute. The most general way of assigning an 7765*e4b17023SJohn Marinoattribute's value is to use a @code{set} expression whose first operand is an 7766*e4b17023SJohn Marino@code{attr} expression giving the name of the attribute being set. The 7767*e4b17023SJohn Marinosecond operand of the @code{set} is an attribute expression 7768*e4b17023SJohn Marino(@pxref{Expressions}) giving the value of the attribute. 7769*e4b17023SJohn Marino 7770*e4b17023SJohn MarinoWhen the attribute value depends on the @samp{alternative} attribute 7771*e4b17023SJohn Marino(i.e., which is the applicable alternative in the constraint of the 7772*e4b17023SJohn Marinoinsn), the @code{set_attr_alternative} expression can be used. It 7773*e4b17023SJohn Marinoallows the specification of a vector of attribute expressions, one for 7774*e4b17023SJohn Marinoeach alternative. 7775*e4b17023SJohn Marino 7776*e4b17023SJohn Marino@findex set_attr 7777*e4b17023SJohn MarinoWhen the generality of arbitrary attribute expressions is not required, 7778*e4b17023SJohn Marinothe simpler @code{set_attr} expression can be used, which allows 7779*e4b17023SJohn Marinospecifying a string giving either a single attribute value or a list 7780*e4b17023SJohn Marinoof attribute values, one for each alternative. 7781*e4b17023SJohn Marino 7782*e4b17023SJohn MarinoThe form of each of the above specifications is shown below. In each case, 7783*e4b17023SJohn Marino@var{name} is a string specifying the attribute to be set. 7784*e4b17023SJohn Marino 7785*e4b17023SJohn Marino@table @code 7786*e4b17023SJohn Marino@item (set_attr @var{name} @var{value-string}) 7787*e4b17023SJohn Marino@var{value-string} is either a string giving the desired attribute value, 7788*e4b17023SJohn Marinoor a string containing a comma-separated list giving the values for 7789*e4b17023SJohn Marinosucceeding alternatives. The number of elements must match the number 7790*e4b17023SJohn Marinoof alternatives in the constraint of the insn pattern. 7791*e4b17023SJohn Marino 7792*e4b17023SJohn MarinoNote that it may be useful to specify @samp{*} for some alternative, in 7793*e4b17023SJohn Marinowhich case the attribute will assume its default value for insns matching 7794*e4b17023SJohn Marinothat alternative. 7795*e4b17023SJohn Marino 7796*e4b17023SJohn Marino@findex set_attr_alternative 7797*e4b17023SJohn Marino@item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}]) 7798*e4b17023SJohn MarinoDepending on the alternative of the insn, the value will be one of the 7799*e4b17023SJohn Marinospecified values. This is a shorthand for using a @code{cond} with 7800*e4b17023SJohn Marinotests on the @samp{alternative} attribute. 7801*e4b17023SJohn Marino 7802*e4b17023SJohn Marino@findex attr 7803*e4b17023SJohn Marino@item (set (attr @var{name}) @var{value}) 7804*e4b17023SJohn MarinoThe first operand of this @code{set} must be the special RTL expression 7805*e4b17023SJohn Marino@code{attr}, whose sole operand is a string giving the name of the 7806*e4b17023SJohn Marinoattribute being set. @var{value} is the value of the attribute. 7807*e4b17023SJohn Marino@end table 7808*e4b17023SJohn Marino 7809*e4b17023SJohn MarinoThe following shows three different ways of representing the same 7810*e4b17023SJohn Marinoattribute value specification: 7811*e4b17023SJohn Marino 7812*e4b17023SJohn Marino@smallexample 7813*e4b17023SJohn Marino(set_attr "type" "load,store,arith") 7814*e4b17023SJohn Marino 7815*e4b17023SJohn Marino(set_attr_alternative "type" 7816*e4b17023SJohn Marino [(const_string "load") (const_string "store") 7817*e4b17023SJohn Marino (const_string "arith")]) 7818*e4b17023SJohn Marino 7819*e4b17023SJohn Marino(set (attr "type") 7820*e4b17023SJohn Marino (cond [(eq_attr "alternative" "1") (const_string "load") 7821*e4b17023SJohn Marino (eq_attr "alternative" "2") (const_string "store")] 7822*e4b17023SJohn Marino (const_string "arith"))) 7823*e4b17023SJohn Marino@end smallexample 7824*e4b17023SJohn Marino 7825*e4b17023SJohn Marino@need 1000 7826*e4b17023SJohn Marino@findex define_asm_attributes 7827*e4b17023SJohn MarinoThe @code{define_asm_attributes} expression provides a mechanism to 7828*e4b17023SJohn Marinospecify the attributes assigned to insns produced from an @code{asm} 7829*e4b17023SJohn Marinostatement. It has the form: 7830*e4b17023SJohn Marino 7831*e4b17023SJohn Marino@smallexample 7832*e4b17023SJohn Marino(define_asm_attributes [@var{attr-sets}]) 7833*e4b17023SJohn Marino@end smallexample 7834*e4b17023SJohn Marino 7835*e4b17023SJohn Marino@noindent 7836*e4b17023SJohn Marinowhere @var{attr-sets} is specified the same as for both the 7837*e4b17023SJohn Marino@code{define_insn} and the @code{define_peephole} expressions. 7838*e4b17023SJohn Marino 7839*e4b17023SJohn MarinoThese values will typically be the ``worst case'' attribute values. For 7840*e4b17023SJohn Marinoexample, they might indicate that the condition code will be clobbered. 7841*e4b17023SJohn Marino 7842*e4b17023SJohn MarinoA specification for a @code{length} attribute is handled specially. The 7843*e4b17023SJohn Marinoway to compute the length of an @code{asm} insn is to multiply the 7844*e4b17023SJohn Marinolength specified in the expression @code{define_asm_attributes} by the 7845*e4b17023SJohn Marinonumber of machine instructions specified in the @code{asm} statement, 7846*e4b17023SJohn Marinodetermined by counting the number of semicolons and newlines in the 7847*e4b17023SJohn Marinostring. Therefore, the value of the @code{length} attribute specified 7848*e4b17023SJohn Marinoin a @code{define_asm_attributes} should be the maximum possible length 7849*e4b17023SJohn Marinoof a single machine instruction. 7850*e4b17023SJohn Marino 7851*e4b17023SJohn Marino@end ifset 7852*e4b17023SJohn Marino@ifset INTERNALS 7853*e4b17023SJohn Marino@node Attr Example 7854*e4b17023SJohn Marino@subsection Example of Attribute Specifications 7855*e4b17023SJohn Marino@cindex attribute specifications example 7856*e4b17023SJohn Marino@cindex attribute specifications 7857*e4b17023SJohn Marino 7858*e4b17023SJohn MarinoThe judicious use of defaulting is important in the efficient use of 7859*e4b17023SJohn Marinoinsn attributes. Typically, insns are divided into @dfn{types} and an 7860*e4b17023SJohn Marinoattribute, customarily called @code{type}, is used to represent this 7861*e4b17023SJohn Marinovalue. This attribute is normally used only to define the default value 7862*e4b17023SJohn Marinofor other attributes. An example will clarify this usage. 7863*e4b17023SJohn Marino 7864*e4b17023SJohn MarinoAssume we have a RISC machine with a condition code and in which only 7865*e4b17023SJohn Marinofull-word operations are performed in registers. Let us assume that we 7866*e4b17023SJohn Marinocan divide all insns into loads, stores, (integer) arithmetic 7867*e4b17023SJohn Marinooperations, floating point operations, and branches. 7868*e4b17023SJohn Marino 7869*e4b17023SJohn MarinoHere we will concern ourselves with determining the effect of an insn on 7870*e4b17023SJohn Marinothe condition code and will limit ourselves to the following possible 7871*e4b17023SJohn Marinoeffects: The condition code can be set unpredictably (clobbered), not 7872*e4b17023SJohn Marinobe changed, be set to agree with the results of the operation, or only 7873*e4b17023SJohn Marinochanged if the item previously set into the condition code has been 7874*e4b17023SJohn Marinomodified. 7875*e4b17023SJohn Marino 7876*e4b17023SJohn MarinoHere is part of a sample @file{md} file for such a machine: 7877*e4b17023SJohn Marino 7878*e4b17023SJohn Marino@smallexample 7879*e4b17023SJohn Marino(define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) 7880*e4b17023SJohn Marino 7881*e4b17023SJohn Marino(define_attr "cc" "clobber,unchanged,set,change0" 7882*e4b17023SJohn Marino (cond [(eq_attr "type" "load") 7883*e4b17023SJohn Marino (const_string "change0") 7884*e4b17023SJohn Marino (eq_attr "type" "store,branch") 7885*e4b17023SJohn Marino (const_string "unchanged") 7886*e4b17023SJohn Marino (eq_attr "type" "arith") 7887*e4b17023SJohn Marino (if_then_else (match_operand:SI 0 "" "") 7888*e4b17023SJohn Marino (const_string "set") 7889*e4b17023SJohn Marino (const_string "clobber"))] 7890*e4b17023SJohn Marino (const_string "clobber"))) 7891*e4b17023SJohn Marino 7892*e4b17023SJohn Marino(define_insn "" 7893*e4b17023SJohn Marino [(set (match_operand:SI 0 "general_operand" "=r,r,m") 7894*e4b17023SJohn Marino (match_operand:SI 1 "general_operand" "r,m,r"))] 7895*e4b17023SJohn Marino "" 7896*e4b17023SJohn Marino "@@ 7897*e4b17023SJohn Marino move %0,%1 7898*e4b17023SJohn Marino load %0,%1 7899*e4b17023SJohn Marino store %0,%1" 7900*e4b17023SJohn Marino [(set_attr "type" "arith,load,store")]) 7901*e4b17023SJohn Marino@end smallexample 7902*e4b17023SJohn Marino 7903*e4b17023SJohn MarinoNote that we assume in the above example that arithmetic operations 7904*e4b17023SJohn Marinoperformed on quantities smaller than a machine word clobber the condition 7905*e4b17023SJohn Marinocode since they will set the condition code to a value corresponding to the 7906*e4b17023SJohn Marinofull-word result. 7907*e4b17023SJohn Marino 7908*e4b17023SJohn Marino@end ifset 7909*e4b17023SJohn Marino@ifset INTERNALS 7910*e4b17023SJohn Marino@node Insn Lengths 7911*e4b17023SJohn Marino@subsection Computing the Length of an Insn 7912*e4b17023SJohn Marino@cindex insn lengths, computing 7913*e4b17023SJohn Marino@cindex computing the length of an insn 7914*e4b17023SJohn Marino 7915*e4b17023SJohn MarinoFor many machines, multiple types of branch instructions are provided, each 7916*e4b17023SJohn Marinofor different length branch displacements. In most cases, the assembler 7917*e4b17023SJohn Marinowill choose the correct instruction to use. However, when the assembler 7918*e4b17023SJohn Marinocannot do so, GCC can when a special attribute, the @code{length} 7919*e4b17023SJohn Marinoattribute, is defined. This attribute must be defined to have numeric 7920*e4b17023SJohn Marinovalues by specifying a null string in its @code{define_attr}. 7921*e4b17023SJohn Marino 7922*e4b17023SJohn MarinoIn the case of the @code{length} attribute, two additional forms of 7923*e4b17023SJohn Marinoarithmetic terms are allowed in test expressions: 7924*e4b17023SJohn Marino 7925*e4b17023SJohn Marino@table @code 7926*e4b17023SJohn Marino@cindex @code{match_dup} and attributes 7927*e4b17023SJohn Marino@item (match_dup @var{n}) 7928*e4b17023SJohn MarinoThis refers to the address of operand @var{n} of the current insn, which 7929*e4b17023SJohn Marinomust be a @code{label_ref}. 7930*e4b17023SJohn Marino 7931*e4b17023SJohn Marino@cindex @code{pc} and attributes 7932*e4b17023SJohn Marino@item (pc) 7933*e4b17023SJohn MarinoThis refers to the address of the @emph{current} insn. It might have 7934*e4b17023SJohn Marinobeen more consistent with other usage to make this the address of the 7935*e4b17023SJohn Marino@emph{next} insn but this would be confusing because the length of the 7936*e4b17023SJohn Marinocurrent insn is to be computed. 7937*e4b17023SJohn Marino@end table 7938*e4b17023SJohn Marino 7939*e4b17023SJohn Marino@cindex @code{addr_vec}, length of 7940*e4b17023SJohn Marino@cindex @code{addr_diff_vec}, length of 7941*e4b17023SJohn MarinoFor normal insns, the length will be determined by value of the 7942*e4b17023SJohn Marino@code{length} attribute. In the case of @code{addr_vec} and 7943*e4b17023SJohn Marino@code{addr_diff_vec} insn patterns, the length is computed as 7944*e4b17023SJohn Marinothe number of vectors multiplied by the size of each vector. 7945*e4b17023SJohn Marino 7946*e4b17023SJohn MarinoLengths are measured in addressable storage units (bytes). 7947*e4b17023SJohn Marino 7948*e4b17023SJohn MarinoThe following macros can be used to refine the length computation: 7949*e4b17023SJohn Marino 7950*e4b17023SJohn Marino@table @code 7951*e4b17023SJohn Marino@findex ADJUST_INSN_LENGTH 7952*e4b17023SJohn Marino@item ADJUST_INSN_LENGTH (@var{insn}, @var{length}) 7953*e4b17023SJohn MarinoIf defined, modifies the length assigned to instruction @var{insn} as a 7954*e4b17023SJohn Marinofunction of the context in which it is used. @var{length} is an lvalue 7955*e4b17023SJohn Marinothat contains the initially computed length of the insn and should be 7956*e4b17023SJohn Marinoupdated with the correct length of the insn. 7957*e4b17023SJohn Marino 7958*e4b17023SJohn MarinoThis macro will normally not be required. A case in which it is 7959*e4b17023SJohn Marinorequired is the ROMP@. On this machine, the size of an @code{addr_vec} 7960*e4b17023SJohn Marinoinsn must be increased by two to compensate for the fact that alignment 7961*e4b17023SJohn Marinomay be required. 7962*e4b17023SJohn Marino@end table 7963*e4b17023SJohn Marino 7964*e4b17023SJohn Marino@findex get_attr_length 7965*e4b17023SJohn MarinoThe routine that returns @code{get_attr_length} (the value of the 7966*e4b17023SJohn Marino@code{length} attribute) can be used by the output routine to 7967*e4b17023SJohn Marinodetermine the form of the branch instruction to be written, as the 7968*e4b17023SJohn Marinoexample below illustrates. 7969*e4b17023SJohn Marino 7970*e4b17023SJohn MarinoAs an example of the specification of variable-length branches, consider 7971*e4b17023SJohn Marinothe IBM 360. If we adopt the convention that a register will be set to 7972*e4b17023SJohn Marinothe starting address of a function, we can jump to labels within 4k of 7973*e4b17023SJohn Marinothe start using a four-byte instruction. Otherwise, we need a six-byte 7974*e4b17023SJohn Marinosequence to load the address from memory and then branch to it. 7975*e4b17023SJohn Marino 7976*e4b17023SJohn MarinoOn such a machine, a pattern for a branch instruction might be specified 7977*e4b17023SJohn Marinoas follows: 7978*e4b17023SJohn Marino 7979*e4b17023SJohn Marino@smallexample 7980*e4b17023SJohn Marino(define_insn "jump" 7981*e4b17023SJohn Marino [(set (pc) 7982*e4b17023SJohn Marino (label_ref (match_operand 0 "" "")))] 7983*e4b17023SJohn Marino "" 7984*e4b17023SJohn Marino@{ 7985*e4b17023SJohn Marino return (get_attr_length (insn) == 4 7986*e4b17023SJohn Marino ? "b %l0" : "l r15,=a(%l0); br r15"); 7987*e4b17023SJohn Marino@} 7988*e4b17023SJohn Marino [(set (attr "length") 7989*e4b17023SJohn Marino (if_then_else (lt (match_dup 0) (const_int 4096)) 7990*e4b17023SJohn Marino (const_int 4) 7991*e4b17023SJohn Marino (const_int 6)))]) 7992*e4b17023SJohn Marino@end smallexample 7993*e4b17023SJohn Marino 7994*e4b17023SJohn Marino@end ifset 7995*e4b17023SJohn Marino@ifset INTERNALS 7996*e4b17023SJohn Marino@node Constant Attributes 7997*e4b17023SJohn Marino@subsection Constant Attributes 7998*e4b17023SJohn Marino@cindex constant attributes 7999*e4b17023SJohn Marino 8000*e4b17023SJohn MarinoA special form of @code{define_attr}, where the expression for the 8001*e4b17023SJohn Marinodefault value is a @code{const} expression, indicates an attribute that 8002*e4b17023SJohn Marinois constant for a given run of the compiler. Constant attributes may be 8003*e4b17023SJohn Marinoused to specify which variety of processor is used. For example, 8004*e4b17023SJohn Marino 8005*e4b17023SJohn Marino@smallexample 8006*e4b17023SJohn Marino(define_attr "cpu" "m88100,m88110,m88000" 8007*e4b17023SJohn Marino (const 8008*e4b17023SJohn Marino (cond [(symbol_ref "TARGET_88100") (const_string "m88100") 8009*e4b17023SJohn Marino (symbol_ref "TARGET_88110") (const_string "m88110")] 8010*e4b17023SJohn Marino (const_string "m88000")))) 8011*e4b17023SJohn Marino 8012*e4b17023SJohn Marino(define_attr "memory" "fast,slow" 8013*e4b17023SJohn Marino (const 8014*e4b17023SJohn Marino (if_then_else (symbol_ref "TARGET_FAST_MEM") 8015*e4b17023SJohn Marino (const_string "fast") 8016*e4b17023SJohn Marino (const_string "slow")))) 8017*e4b17023SJohn Marino@end smallexample 8018*e4b17023SJohn Marino 8019*e4b17023SJohn MarinoThe routine generated for constant attributes has no parameters as it 8020*e4b17023SJohn Marinodoes not depend on any particular insn. RTL expressions used to define 8021*e4b17023SJohn Marinothe value of a constant attribute may use the @code{symbol_ref} form, 8022*e4b17023SJohn Marinobut may not use either the @code{match_operand} form or @code{eq_attr} 8023*e4b17023SJohn Marinoforms involving insn attributes. 8024*e4b17023SJohn Marino 8025*e4b17023SJohn Marino@end ifset 8026*e4b17023SJohn Marino@ifset INTERNALS 8027*e4b17023SJohn Marino@node Delay Slots 8028*e4b17023SJohn Marino@subsection Delay Slot Scheduling 8029*e4b17023SJohn Marino@cindex delay slots, defining 8030*e4b17023SJohn Marino 8031*e4b17023SJohn MarinoThe insn attribute mechanism can be used to specify the requirements for 8032*e4b17023SJohn Marinodelay slots, if any, on a target machine. An instruction is said to 8033*e4b17023SJohn Marinorequire a @dfn{delay slot} if some instructions that are physically 8034*e4b17023SJohn Marinoafter the instruction are executed as if they were located before it. 8035*e4b17023SJohn MarinoClassic examples are branch and call instructions, which often execute 8036*e4b17023SJohn Marinothe following instruction before the branch or call is performed. 8037*e4b17023SJohn Marino 8038*e4b17023SJohn MarinoOn some machines, conditional branch instructions can optionally 8039*e4b17023SJohn Marino@dfn{annul} instructions in the delay slot. This means that the 8040*e4b17023SJohn Marinoinstruction will not be executed for certain branch outcomes. Both 8041*e4b17023SJohn Marinoinstructions that annul if the branch is true and instructions that 8042*e4b17023SJohn Marinoannul if the branch is false are supported. 8043*e4b17023SJohn Marino 8044*e4b17023SJohn MarinoDelay slot scheduling differs from instruction scheduling in that 8045*e4b17023SJohn Marinodetermining whether an instruction needs a delay slot is dependent only 8046*e4b17023SJohn Marinoon the type of instruction being generated, not on data flow between the 8047*e4b17023SJohn Marinoinstructions. See the next section for a discussion of data-dependent 8048*e4b17023SJohn Marinoinstruction scheduling. 8049*e4b17023SJohn Marino 8050*e4b17023SJohn Marino@findex define_delay 8051*e4b17023SJohn MarinoThe requirement of an insn needing one or more delay slots is indicated 8052*e4b17023SJohn Marinovia the @code{define_delay} expression. It has the following form: 8053*e4b17023SJohn Marino 8054*e4b17023SJohn Marino@smallexample 8055*e4b17023SJohn Marino(define_delay @var{test} 8056*e4b17023SJohn Marino [@var{delay-1} @var{annul-true-1} @var{annul-false-1} 8057*e4b17023SJohn Marino @var{delay-2} @var{annul-true-2} @var{annul-false-2} 8058*e4b17023SJohn Marino @dots{}]) 8059*e4b17023SJohn Marino@end smallexample 8060*e4b17023SJohn Marino 8061*e4b17023SJohn Marino@var{test} is an attribute test that indicates whether this 8062*e4b17023SJohn Marino@code{define_delay} applies to a particular insn. If so, the number of 8063*e4b17023SJohn Marinorequired delay slots is determined by the length of the vector specified 8064*e4b17023SJohn Marinoas the second argument. An insn placed in delay slot @var{n} must 8065*e4b17023SJohn Marinosatisfy attribute test @var{delay-n}. @var{annul-true-n} is an 8066*e4b17023SJohn Marinoattribute test that specifies which insns may be annulled if the branch 8067*e4b17023SJohn Marinois true. Similarly, @var{annul-false-n} specifies which insns in the 8068*e4b17023SJohn Marinodelay slot may be annulled if the branch is false. If annulling is not 8069*e4b17023SJohn Marinosupported for that delay slot, @code{(nil)} should be coded. 8070*e4b17023SJohn Marino 8071*e4b17023SJohn MarinoFor example, in the common case where branch and call insns require 8072*e4b17023SJohn Marinoa single delay slot, which may contain any insn other than a branch or 8073*e4b17023SJohn Marinocall, the following would be placed in the @file{md} file: 8074*e4b17023SJohn Marino 8075*e4b17023SJohn Marino@smallexample 8076*e4b17023SJohn Marino(define_delay (eq_attr "type" "branch,call") 8077*e4b17023SJohn Marino [(eq_attr "type" "!branch,call") (nil) (nil)]) 8078*e4b17023SJohn Marino@end smallexample 8079*e4b17023SJohn Marino 8080*e4b17023SJohn MarinoMultiple @code{define_delay} expressions may be specified. In this 8081*e4b17023SJohn Marinocase, each such expression specifies different delay slot requirements 8082*e4b17023SJohn Marinoand there must be no insn for which tests in two @code{define_delay} 8083*e4b17023SJohn Marinoexpressions are both true. 8084*e4b17023SJohn Marino 8085*e4b17023SJohn MarinoFor example, if we have a machine that requires one delay slot for branches 8086*e4b17023SJohn Marinobut two for calls, no delay slot can contain a branch or call insn, 8087*e4b17023SJohn Marinoand any valid insn in the delay slot for the branch can be annulled if the 8088*e4b17023SJohn Marinobranch is true, we might represent this as follows: 8089*e4b17023SJohn Marino 8090*e4b17023SJohn Marino@smallexample 8091*e4b17023SJohn Marino(define_delay (eq_attr "type" "branch") 8092*e4b17023SJohn Marino [(eq_attr "type" "!branch,call") 8093*e4b17023SJohn Marino (eq_attr "type" "!branch,call") 8094*e4b17023SJohn Marino (nil)]) 8095*e4b17023SJohn Marino 8096*e4b17023SJohn Marino(define_delay (eq_attr "type" "call") 8097*e4b17023SJohn Marino [(eq_attr "type" "!branch,call") (nil) (nil) 8098*e4b17023SJohn Marino (eq_attr "type" "!branch,call") (nil) (nil)]) 8099*e4b17023SJohn Marino@end smallexample 8100*e4b17023SJohn Marino@c the above is *still* too long. --mew 4feb93 8101*e4b17023SJohn Marino 8102*e4b17023SJohn Marino@end ifset 8103*e4b17023SJohn Marino@ifset INTERNALS 8104*e4b17023SJohn Marino@node Processor pipeline description 8105*e4b17023SJohn Marino@subsection Specifying processor pipeline description 8106*e4b17023SJohn Marino@cindex processor pipeline description 8107*e4b17023SJohn Marino@cindex processor functional units 8108*e4b17023SJohn Marino@cindex instruction latency time 8109*e4b17023SJohn Marino@cindex interlock delays 8110*e4b17023SJohn Marino@cindex data dependence delays 8111*e4b17023SJohn Marino@cindex reservation delays 8112*e4b17023SJohn Marino@cindex pipeline hazard recognizer 8113*e4b17023SJohn Marino@cindex automaton based pipeline description 8114*e4b17023SJohn Marino@cindex regular expressions 8115*e4b17023SJohn Marino@cindex deterministic finite state automaton 8116*e4b17023SJohn Marino@cindex automaton based scheduler 8117*e4b17023SJohn Marino@cindex RISC 8118*e4b17023SJohn Marino@cindex VLIW 8119*e4b17023SJohn Marino 8120*e4b17023SJohn MarinoTo achieve better performance, most modern processors 8121*e4b17023SJohn Marino(super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW} 8122*e4b17023SJohn Marinoprocessors) have many @dfn{functional units} on which several 8123*e4b17023SJohn Marinoinstructions can be executed simultaneously. An instruction starts 8124*e4b17023SJohn Marinoexecution if its issue conditions are satisfied. If not, the 8125*e4b17023SJohn Marinoinstruction is stalled until its conditions are satisfied. Such 8126*e4b17023SJohn Marino@dfn{interlock (pipeline) delay} causes interruption of the fetching 8127*e4b17023SJohn Marinoof successor instructions (or demands nop instructions, e.g.@: for some 8128*e4b17023SJohn MarinoMIPS processors). 8129*e4b17023SJohn Marino 8130*e4b17023SJohn MarinoThere are two major kinds of interlock delays in modern processors. 8131*e4b17023SJohn MarinoThe first one is a data dependence delay determining @dfn{instruction 8132*e4b17023SJohn Marinolatency time}. The instruction execution is not started until all 8133*e4b17023SJohn Marinosource data have been evaluated by prior instructions (there are more 8134*e4b17023SJohn Marinocomplex cases when the instruction execution starts even when the data 8135*e4b17023SJohn Marinoare not available but will be ready in given time after the 8136*e4b17023SJohn Marinoinstruction execution start). Taking the data dependence delays into 8137*e4b17023SJohn Marinoaccount is simple. The data dependence (true, output, and 8138*e4b17023SJohn Marinoanti-dependence) delay between two instructions is given by a 8139*e4b17023SJohn Marinoconstant. In most cases this approach is adequate. The second kind 8140*e4b17023SJohn Marinoof interlock delays is a reservation delay. The reservation delay 8141*e4b17023SJohn Marinomeans that two instructions under execution will be in need of shared 8142*e4b17023SJohn Marinoprocessors resources, i.e.@: buses, internal registers, and/or 8143*e4b17023SJohn Marinofunctional units, which are reserved for some time. Taking this kind 8144*e4b17023SJohn Marinoof delay into account is complex especially for modern @acronym{RISC} 8145*e4b17023SJohn Marinoprocessors. 8146*e4b17023SJohn Marino 8147*e4b17023SJohn MarinoThe task of exploiting more processor parallelism is solved by an 8148*e4b17023SJohn Marinoinstruction scheduler. For a better solution to this problem, the 8149*e4b17023SJohn Marinoinstruction scheduler has to have an adequate description of the 8150*e4b17023SJohn Marinoprocessor parallelism (or @dfn{pipeline description}). GCC 8151*e4b17023SJohn Marinomachine descriptions describe processor parallelism and functional 8152*e4b17023SJohn Marinounit reservations for groups of instructions with the aid of 8153*e4b17023SJohn Marino@dfn{regular expressions}. 8154*e4b17023SJohn Marino 8155*e4b17023SJohn MarinoThe GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to 8156*e4b17023SJohn Marinofigure out the possibility of the instruction issue by the processor 8157*e4b17023SJohn Marinoon a given simulated processor cycle. The pipeline hazard recognizer is 8158*e4b17023SJohn Marinoautomatically generated from the processor pipeline description. The 8159*e4b17023SJohn Marinopipeline hazard recognizer generated from the machine description 8160*e4b17023SJohn Marinois based on a deterministic finite state automaton (@acronym{DFA}): 8161*e4b17023SJohn Marinothe instruction issue is possible if there is a transition from one 8162*e4b17023SJohn Marinoautomaton state to another one. This algorithm is very fast, and 8163*e4b17023SJohn Marinofurthermore, its speed is not dependent on processor 8164*e4b17023SJohn Marinocomplexity@footnote{However, the size of the automaton depends on 8165*e4b17023SJohn Marinoprocessor complexity. To limit this effect, machine descriptions 8166*e4b17023SJohn Marinocan split orthogonal parts of the machine description among several 8167*e4b17023SJohn Marinoautomata: but then, since each of these must be stepped independently, 8168*e4b17023SJohn Marinothis does cause a small decrease in the algorithm's performance.}. 8169*e4b17023SJohn Marino 8170*e4b17023SJohn Marino@cindex automaton based pipeline description 8171*e4b17023SJohn MarinoThe rest of this section describes the directives that constitute 8172*e4b17023SJohn Marinoan automaton-based processor pipeline description. The order of 8173*e4b17023SJohn Marinothese constructions within the machine description file is not 8174*e4b17023SJohn Marinoimportant. 8175*e4b17023SJohn Marino 8176*e4b17023SJohn Marino@findex define_automaton 8177*e4b17023SJohn Marino@cindex pipeline hazard recognizer 8178*e4b17023SJohn MarinoThe following optional construction describes names of automata 8179*e4b17023SJohn Marinogenerated and used for the pipeline hazards recognition. Sometimes 8180*e4b17023SJohn Marinothe generated finite state automaton used by the pipeline hazard 8181*e4b17023SJohn Marinorecognizer is large. If we use more than one automaton and bind functional 8182*e4b17023SJohn Marinounits to the automata, the total size of the automata is usually 8183*e4b17023SJohn Marinoless than the size of the single automaton. If there is no one such 8184*e4b17023SJohn Marinoconstruction, only one finite state automaton is generated. 8185*e4b17023SJohn Marino 8186*e4b17023SJohn Marino@smallexample 8187*e4b17023SJohn Marino(define_automaton @var{automata-names}) 8188*e4b17023SJohn Marino@end smallexample 8189*e4b17023SJohn Marino 8190*e4b17023SJohn Marino@var{automata-names} is a string giving names of the automata. The 8191*e4b17023SJohn Marinonames are separated by commas. All the automata should have unique names. 8192*e4b17023SJohn MarinoThe automaton name is used in the constructions @code{define_cpu_unit} and 8193*e4b17023SJohn Marino@code{define_query_cpu_unit}. 8194*e4b17023SJohn Marino 8195*e4b17023SJohn Marino@findex define_cpu_unit 8196*e4b17023SJohn Marino@cindex processor functional units 8197*e4b17023SJohn MarinoEach processor functional unit used in the description of instruction 8198*e4b17023SJohn Marinoreservations should be described by the following construction. 8199*e4b17023SJohn Marino 8200*e4b17023SJohn Marino@smallexample 8201*e4b17023SJohn Marino(define_cpu_unit @var{unit-names} [@var{automaton-name}]) 8202*e4b17023SJohn Marino@end smallexample 8203*e4b17023SJohn Marino 8204*e4b17023SJohn Marino@var{unit-names} is a string giving the names of the functional units 8205*e4b17023SJohn Marinoseparated by commas. Don't use name @samp{nothing}, it is reserved 8206*e4b17023SJohn Marinofor other goals. 8207*e4b17023SJohn Marino 8208*e4b17023SJohn Marino@var{automaton-name} is a string giving the name of the automaton with 8209*e4b17023SJohn Marinowhich the unit is bound. The automaton should be described in 8210*e4b17023SJohn Marinoconstruction @code{define_automaton}. You should give 8211*e4b17023SJohn Marino@dfn{automaton-name}, if there is a defined automaton. 8212*e4b17023SJohn Marino 8213*e4b17023SJohn MarinoThe assignment of units to automata are constrained by the uses of the 8214*e4b17023SJohn Marinounits in insn reservations. The most important constraint is: if a 8215*e4b17023SJohn Marinounit reservation is present on a particular cycle of an alternative 8216*e4b17023SJohn Marinofor an insn reservation, then some unit from the same automaton must 8217*e4b17023SJohn Marinobe present on the same cycle for the other alternatives of the insn 8218*e4b17023SJohn Marinoreservation. The rest of the constraints are mentioned in the 8219*e4b17023SJohn Marinodescription of the subsequent constructions. 8220*e4b17023SJohn Marino 8221*e4b17023SJohn Marino@findex define_query_cpu_unit 8222*e4b17023SJohn Marino@cindex querying function unit reservations 8223*e4b17023SJohn MarinoThe following construction describes CPU functional units analogously 8224*e4b17023SJohn Marinoto @code{define_cpu_unit}. The reservation of such units can be 8225*e4b17023SJohn Marinoqueried for an automaton state. The instruction scheduler never 8226*e4b17023SJohn Marinoqueries reservation of functional units for given automaton state. So 8227*e4b17023SJohn Marinoas a rule, you don't need this construction. This construction could 8228*e4b17023SJohn Marinobe used for future code generation goals (e.g.@: to generate 8229*e4b17023SJohn Marino@acronym{VLIW} insn templates). 8230*e4b17023SJohn Marino 8231*e4b17023SJohn Marino@smallexample 8232*e4b17023SJohn Marino(define_query_cpu_unit @var{unit-names} [@var{automaton-name}]) 8233*e4b17023SJohn Marino@end smallexample 8234*e4b17023SJohn Marino 8235*e4b17023SJohn Marino@var{unit-names} is a string giving names of the functional units 8236*e4b17023SJohn Marinoseparated by commas. 8237*e4b17023SJohn Marino 8238*e4b17023SJohn Marino@var{automaton-name} is a string giving the name of the automaton with 8239*e4b17023SJohn Marinowhich the unit is bound. 8240*e4b17023SJohn Marino 8241*e4b17023SJohn Marino@findex define_insn_reservation 8242*e4b17023SJohn Marino@cindex instruction latency time 8243*e4b17023SJohn Marino@cindex regular expressions 8244*e4b17023SJohn Marino@cindex data bypass 8245*e4b17023SJohn MarinoThe following construction is the major one to describe pipeline 8246*e4b17023SJohn Marinocharacteristics of an instruction. 8247*e4b17023SJohn Marino 8248*e4b17023SJohn Marino@smallexample 8249*e4b17023SJohn Marino(define_insn_reservation @var{insn-name} @var{default_latency} 8250*e4b17023SJohn Marino @var{condition} @var{regexp}) 8251*e4b17023SJohn Marino@end smallexample 8252*e4b17023SJohn Marino 8253*e4b17023SJohn Marino@var{default_latency} is a number giving latency time of the 8254*e4b17023SJohn Marinoinstruction. There is an important difference between the old 8255*e4b17023SJohn Marinodescription and the automaton based pipeline description. The latency 8256*e4b17023SJohn Marinotime is used for all dependencies when we use the old description. In 8257*e4b17023SJohn Marinothe automaton based pipeline description, the given latency time is only 8258*e4b17023SJohn Marinoused for true dependencies. The cost of anti-dependencies is always 8259*e4b17023SJohn Marinozero and the cost of output dependencies is the difference between 8260*e4b17023SJohn Marinolatency times of the producing and consuming insns (if the difference 8261*e4b17023SJohn Marinois negative, the cost is considered to be zero). You can always 8262*e4b17023SJohn Marinochange the default costs for any description by using the target hook 8263*e4b17023SJohn Marino@code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}). 8264*e4b17023SJohn Marino 8265*e4b17023SJohn Marino@var{insn-name} is a string giving the internal name of the insn. The 8266*e4b17023SJohn Marinointernal names are used in constructions @code{define_bypass} and in 8267*e4b17023SJohn Marinothe automaton description file generated for debugging. The internal 8268*e4b17023SJohn Marinoname has nothing in common with the names in @code{define_insn}. It is a 8269*e4b17023SJohn Marinogood practice to use insn classes described in the processor manual. 8270*e4b17023SJohn Marino 8271*e4b17023SJohn Marino@var{condition} defines what RTL insns are described by this 8272*e4b17023SJohn Marinoconstruction. You should remember that you will be in trouble if 8273*e4b17023SJohn Marino@var{condition} for two or more different 8274*e4b17023SJohn Marino@code{define_insn_reservation} constructions is TRUE for an insn. In 8275*e4b17023SJohn Marinothis case what reservation will be used for the insn is not defined. 8276*e4b17023SJohn MarinoSuch cases are not checked during generation of the pipeline hazards 8277*e4b17023SJohn Marinorecognizer because in general recognizing that two conditions may have 8278*e4b17023SJohn Marinothe same value is quite difficult (especially if the conditions 8279*e4b17023SJohn Marinocontain @code{symbol_ref}). It is also not checked during the 8280*e4b17023SJohn Marinopipeline hazard recognizer work because it would slow down the 8281*e4b17023SJohn Marinorecognizer considerably. 8282*e4b17023SJohn Marino 8283*e4b17023SJohn Marino@var{regexp} is a string describing the reservation of the cpu's functional 8284*e4b17023SJohn Marinounits by the instruction. The reservations are described by a regular 8285*e4b17023SJohn Marinoexpression according to the following syntax: 8286*e4b17023SJohn Marino 8287*e4b17023SJohn Marino@smallexample 8288*e4b17023SJohn Marino regexp = regexp "," oneof 8289*e4b17023SJohn Marino | oneof 8290*e4b17023SJohn Marino 8291*e4b17023SJohn Marino oneof = oneof "|" allof 8292*e4b17023SJohn Marino | allof 8293*e4b17023SJohn Marino 8294*e4b17023SJohn Marino allof = allof "+" repeat 8295*e4b17023SJohn Marino | repeat 8296*e4b17023SJohn Marino 8297*e4b17023SJohn Marino repeat = element "*" number 8298*e4b17023SJohn Marino | element 8299*e4b17023SJohn Marino 8300*e4b17023SJohn Marino element = cpu_function_unit_name 8301*e4b17023SJohn Marino | reservation_name 8302*e4b17023SJohn Marino | result_name 8303*e4b17023SJohn Marino | "nothing" 8304*e4b17023SJohn Marino | "(" regexp ")" 8305*e4b17023SJohn Marino@end smallexample 8306*e4b17023SJohn Marino 8307*e4b17023SJohn Marino@itemize @bullet 8308*e4b17023SJohn Marino@item 8309*e4b17023SJohn Marino@samp{,} is used for describing the start of the next cycle in 8310*e4b17023SJohn Marinothe reservation. 8311*e4b17023SJohn Marino 8312*e4b17023SJohn Marino@item 8313*e4b17023SJohn Marino@samp{|} is used for describing a reservation described by the first 8314*e4b17023SJohn Marinoregular expression @strong{or} a reservation described by the second 8315*e4b17023SJohn Marinoregular expression @strong{or} etc. 8316*e4b17023SJohn Marino 8317*e4b17023SJohn Marino@item 8318*e4b17023SJohn Marino@samp{+} is used for describing a reservation described by the first 8319*e4b17023SJohn Marinoregular expression @strong{and} a reservation described by the 8320*e4b17023SJohn Marinosecond regular expression @strong{and} etc. 8321*e4b17023SJohn Marino 8322*e4b17023SJohn Marino@item 8323*e4b17023SJohn Marino@samp{*} is used for convenience and simply means a sequence in which 8324*e4b17023SJohn Marinothe regular expression are repeated @var{number} times with cycle 8325*e4b17023SJohn Marinoadvancing (see @samp{,}). 8326*e4b17023SJohn Marino 8327*e4b17023SJohn Marino@item 8328*e4b17023SJohn Marino@samp{cpu_function_unit_name} denotes reservation of the named 8329*e4b17023SJohn Marinofunctional unit. 8330*e4b17023SJohn Marino 8331*e4b17023SJohn Marino@item 8332*e4b17023SJohn Marino@samp{reservation_name} --- see description of construction 8333*e4b17023SJohn Marino@samp{define_reservation}. 8334*e4b17023SJohn Marino 8335*e4b17023SJohn Marino@item 8336*e4b17023SJohn Marino@samp{nothing} denotes no unit reservations. 8337*e4b17023SJohn Marino@end itemize 8338*e4b17023SJohn Marino 8339*e4b17023SJohn Marino@findex define_reservation 8340*e4b17023SJohn MarinoSometimes unit reservations for different insns contain common parts. 8341*e4b17023SJohn MarinoIn such case, you can simplify the pipeline description by describing 8342*e4b17023SJohn Marinothe common part by the following construction 8343*e4b17023SJohn Marino 8344*e4b17023SJohn Marino@smallexample 8345*e4b17023SJohn Marino(define_reservation @var{reservation-name} @var{regexp}) 8346*e4b17023SJohn Marino@end smallexample 8347*e4b17023SJohn Marino 8348*e4b17023SJohn Marino@var{reservation-name} is a string giving name of @var{regexp}. 8349*e4b17023SJohn MarinoFunctional unit names and reservation names are in the same name 8350*e4b17023SJohn Marinospace. So the reservation names should be different from the 8351*e4b17023SJohn Marinofunctional unit names and can not be the reserved name @samp{nothing}. 8352*e4b17023SJohn Marino 8353*e4b17023SJohn Marino@findex define_bypass 8354*e4b17023SJohn Marino@cindex instruction latency time 8355*e4b17023SJohn Marino@cindex data bypass 8356*e4b17023SJohn MarinoThe following construction is used to describe exceptions in the 8357*e4b17023SJohn Marinolatency time for given instruction pair. This is so called bypasses. 8358*e4b17023SJohn Marino 8359*e4b17023SJohn Marino@smallexample 8360*e4b17023SJohn Marino(define_bypass @var{number} @var{out_insn_names} @var{in_insn_names} 8361*e4b17023SJohn Marino [@var{guard}]) 8362*e4b17023SJohn Marino@end smallexample 8363*e4b17023SJohn Marino 8364*e4b17023SJohn Marino@var{number} defines when the result generated by the instructions 8365*e4b17023SJohn Marinogiven in string @var{out_insn_names} will be ready for the 8366*e4b17023SJohn Marinoinstructions given in string @var{in_insn_names}. Each of these 8367*e4b17023SJohn Marinostrings is a comma-separated list of filename-style globs and 8368*e4b17023SJohn Marinothey refer to the names of @code{define_insn_reservation}s. 8369*e4b17023SJohn MarinoFor example: 8370*e4b17023SJohn Marino@smallexample 8371*e4b17023SJohn Marino(define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*") 8372*e4b17023SJohn Marino@end smallexample 8373*e4b17023SJohn Marinodefines a bypass between instructions that start with 8374*e4b17023SJohn Marino@samp{cpu1_load_} or @samp{cpu1_store_} and those that start with 8375*e4b17023SJohn Marino@samp{cpu1_load_}. 8376*e4b17023SJohn Marino 8377*e4b17023SJohn Marino@var{guard} is an optional string giving the name of a C function which 8378*e4b17023SJohn Marinodefines an additional guard for the bypass. The function will get the 8379*e4b17023SJohn Marinotwo insns as parameters. If the function returns zero the bypass will 8380*e4b17023SJohn Marinobe ignored for this case. The additional guard is necessary to 8381*e4b17023SJohn Marinorecognize complicated bypasses, e.g.@: when the consumer is only an address 8382*e4b17023SJohn Marinoof insn @samp{store} (not a stored value). 8383*e4b17023SJohn Marino 8384*e4b17023SJohn MarinoIf there are more one bypass with the same output and input insns, the 8385*e4b17023SJohn Marinochosen bypass is the first bypass with a guard in description whose 8386*e4b17023SJohn Marinoguard function returns nonzero. If there is no such bypass, then 8387*e4b17023SJohn Marinobypass without the guard function is chosen. 8388*e4b17023SJohn Marino 8389*e4b17023SJohn Marino@findex exclusion_set 8390*e4b17023SJohn Marino@findex presence_set 8391*e4b17023SJohn Marino@findex final_presence_set 8392*e4b17023SJohn Marino@findex absence_set 8393*e4b17023SJohn Marino@findex final_absence_set 8394*e4b17023SJohn Marino@cindex VLIW 8395*e4b17023SJohn Marino@cindex RISC 8396*e4b17023SJohn MarinoThe following five constructions are usually used to describe 8397*e4b17023SJohn Marino@acronym{VLIW} processors, or more precisely, to describe a placement 8398*e4b17023SJohn Marinoof small instructions into @acronym{VLIW} instruction slots. They 8399*e4b17023SJohn Marinocan be used for @acronym{RISC} processors, too. 8400*e4b17023SJohn Marino 8401*e4b17023SJohn Marino@smallexample 8402*e4b17023SJohn Marino(exclusion_set @var{unit-names} @var{unit-names}) 8403*e4b17023SJohn Marino(presence_set @var{unit-names} @var{patterns}) 8404*e4b17023SJohn Marino(final_presence_set @var{unit-names} @var{patterns}) 8405*e4b17023SJohn Marino(absence_set @var{unit-names} @var{patterns}) 8406*e4b17023SJohn Marino(final_absence_set @var{unit-names} @var{patterns}) 8407*e4b17023SJohn Marino@end smallexample 8408*e4b17023SJohn Marino 8409*e4b17023SJohn Marino@var{unit-names} is a string giving names of functional units 8410*e4b17023SJohn Marinoseparated by commas. 8411*e4b17023SJohn Marino 8412*e4b17023SJohn Marino@var{patterns} is a string giving patterns of functional units 8413*e4b17023SJohn Marinoseparated by comma. Currently pattern is one unit or units 8414*e4b17023SJohn Marinoseparated by white-spaces. 8415*e4b17023SJohn Marino 8416*e4b17023SJohn MarinoThe first construction (@samp{exclusion_set}) means that each 8417*e4b17023SJohn Marinofunctional unit in the first string can not be reserved simultaneously 8418*e4b17023SJohn Marinowith a unit whose name is in the second string and vice versa. For 8419*e4b17023SJohn Marinoexample, the construction is useful for describing processors 8420*e4b17023SJohn Marino(e.g.@: some SPARC processors) with a fully pipelined floating point 8421*e4b17023SJohn Marinofunctional unit which can execute simultaneously only single floating 8422*e4b17023SJohn Marinopoint insns or only double floating point insns. 8423*e4b17023SJohn Marino 8424*e4b17023SJohn MarinoThe second construction (@samp{presence_set}) means that each 8425*e4b17023SJohn Marinofunctional unit in the first string can not be reserved unless at 8426*e4b17023SJohn Marinoleast one of pattern of units whose names are in the second string is 8427*e4b17023SJohn Marinoreserved. This is an asymmetric relation. For example, it is useful 8428*e4b17023SJohn Marinofor description that @acronym{VLIW} @samp{slot1} is reserved after 8429*e4b17023SJohn Marino@samp{slot0} reservation. We could describe it by the following 8430*e4b17023SJohn Marinoconstruction 8431*e4b17023SJohn Marino 8432*e4b17023SJohn Marino@smallexample 8433*e4b17023SJohn Marino(presence_set "slot1" "slot0") 8434*e4b17023SJohn Marino@end smallexample 8435*e4b17023SJohn Marino 8436*e4b17023SJohn MarinoOr @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0} 8437*e4b17023SJohn Marinoreservation. In this case we could write 8438*e4b17023SJohn Marino 8439*e4b17023SJohn Marino@smallexample 8440*e4b17023SJohn Marino(presence_set "slot1" "slot0 b0") 8441*e4b17023SJohn Marino@end smallexample 8442*e4b17023SJohn Marino 8443*e4b17023SJohn MarinoThe third construction (@samp{final_presence_set}) is analogous to 8444*e4b17023SJohn Marino@samp{presence_set}. The difference between them is when checking is 8445*e4b17023SJohn Marinodone. When an instruction is issued in given automaton state 8446*e4b17023SJohn Marinoreflecting all current and planned unit reservations, the automaton 8447*e4b17023SJohn Marinostate is changed. The first state is a source state, the second one 8448*e4b17023SJohn Marinois a result state. Checking for @samp{presence_set} is done on the 8449*e4b17023SJohn Marinosource state reservation, checking for @samp{final_presence_set} is 8450*e4b17023SJohn Marinodone on the result reservation. This construction is useful to 8451*e4b17023SJohn Marinodescribe a reservation which is actually two subsequent reservations. 8452*e4b17023SJohn MarinoFor example, if we use 8453*e4b17023SJohn Marino 8454*e4b17023SJohn Marino@smallexample 8455*e4b17023SJohn Marino(presence_set "slot1" "slot0") 8456*e4b17023SJohn Marino@end smallexample 8457*e4b17023SJohn Marino 8458*e4b17023SJohn Marinothe following insn will be never issued (because @samp{slot1} requires 8459*e4b17023SJohn Marino@samp{slot0} which is absent in the source state). 8460*e4b17023SJohn Marino 8461*e4b17023SJohn Marino@smallexample 8462*e4b17023SJohn Marino(define_reservation "insn_and_nop" "slot0 + slot1") 8463*e4b17023SJohn Marino@end smallexample 8464*e4b17023SJohn Marino 8465*e4b17023SJohn Marinobut it can be issued if we use analogous @samp{final_presence_set}. 8466*e4b17023SJohn Marino 8467*e4b17023SJohn MarinoThe forth construction (@samp{absence_set}) means that each functional 8468*e4b17023SJohn Marinounit in the first string can be reserved only if each pattern of units 8469*e4b17023SJohn Marinowhose names are in the second string is not reserved. This is an 8470*e4b17023SJohn Marinoasymmetric relation (actually @samp{exclusion_set} is analogous to 8471*e4b17023SJohn Marinothis one but it is symmetric). For example it might be useful in a 8472*e4b17023SJohn Marino@acronym{VLIW} description to say that @samp{slot0} cannot be reserved 8473*e4b17023SJohn Marinoafter either @samp{slot1} or @samp{slot2} have been reserved. This 8474*e4b17023SJohn Marinocan be described as: 8475*e4b17023SJohn Marino 8476*e4b17023SJohn Marino@smallexample 8477*e4b17023SJohn Marino(absence_set "slot0" "slot1, slot2") 8478*e4b17023SJohn Marino@end smallexample 8479*e4b17023SJohn Marino 8480*e4b17023SJohn MarinoOr @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0} 8481*e4b17023SJohn Marinoare reserved or @samp{slot1} and unit @samp{b1} are reserved. In 8482*e4b17023SJohn Marinothis case we could write 8483*e4b17023SJohn Marino 8484*e4b17023SJohn Marino@smallexample 8485*e4b17023SJohn Marino(absence_set "slot2" "slot0 b0, slot1 b1") 8486*e4b17023SJohn Marino@end smallexample 8487*e4b17023SJohn Marino 8488*e4b17023SJohn MarinoAll functional units mentioned in a set should belong to the same 8489*e4b17023SJohn Marinoautomaton. 8490*e4b17023SJohn Marino 8491*e4b17023SJohn MarinoThe last construction (@samp{final_absence_set}) is analogous to 8492*e4b17023SJohn Marino@samp{absence_set} but checking is done on the result (state) 8493*e4b17023SJohn Marinoreservation. See comments for @samp{final_presence_set}. 8494*e4b17023SJohn Marino 8495*e4b17023SJohn Marino@findex automata_option 8496*e4b17023SJohn Marino@cindex deterministic finite state automaton 8497*e4b17023SJohn Marino@cindex nondeterministic finite state automaton 8498*e4b17023SJohn Marino@cindex finite state automaton minimization 8499*e4b17023SJohn MarinoYou can control the generator of the pipeline hazard recognizer with 8500*e4b17023SJohn Marinothe following construction. 8501*e4b17023SJohn Marino 8502*e4b17023SJohn Marino@smallexample 8503*e4b17023SJohn Marino(automata_option @var{options}) 8504*e4b17023SJohn Marino@end smallexample 8505*e4b17023SJohn Marino 8506*e4b17023SJohn Marino@var{options} is a string giving options which affect the generated 8507*e4b17023SJohn Marinocode. Currently there are the following options: 8508*e4b17023SJohn Marino 8509*e4b17023SJohn Marino@itemize @bullet 8510*e4b17023SJohn Marino@item 8511*e4b17023SJohn Marino@dfn{no-minimization} makes no minimization of the automaton. This is 8512*e4b17023SJohn Marinoonly worth to do when we are debugging the description and need to 8513*e4b17023SJohn Marinolook more accurately at reservations of states. 8514*e4b17023SJohn Marino 8515*e4b17023SJohn Marino@item 8516*e4b17023SJohn Marino@dfn{time} means printing time statistics about the generation of 8517*e4b17023SJohn Marinoautomata. 8518*e4b17023SJohn Marino 8519*e4b17023SJohn Marino@item 8520*e4b17023SJohn Marino@dfn{stats} means printing statistics about the generated automata 8521*e4b17023SJohn Marinosuch as the number of DFA states, NDFA states and arcs. 8522*e4b17023SJohn Marino 8523*e4b17023SJohn Marino@item 8524*e4b17023SJohn Marino@dfn{v} means a generation of the file describing the result automata. 8525*e4b17023SJohn MarinoThe file has suffix @samp{.dfa} and can be used for the description 8526*e4b17023SJohn Marinoverification and debugging. 8527*e4b17023SJohn Marino 8528*e4b17023SJohn Marino@item 8529*e4b17023SJohn Marino@dfn{w} means a generation of warning instead of error for 8530*e4b17023SJohn Marinonon-critical errors. 8531*e4b17023SJohn Marino 8532*e4b17023SJohn Marino@item 8533*e4b17023SJohn Marino@dfn{no-comb-vect} prevents the automaton generator from generating 8534*e4b17023SJohn Marinotwo data structures and comparing them for space efficiency. Using 8535*e4b17023SJohn Marinoa comb vector to represent transitions may be better, but it can be 8536*e4b17023SJohn Marinovery expensive to construct. This option is useful if the build 8537*e4b17023SJohn Marinoprocess spends an unacceptably long time in genautomata. 8538*e4b17023SJohn Marino 8539*e4b17023SJohn Marino@item 8540*e4b17023SJohn Marino@dfn{ndfa} makes nondeterministic finite state automata. This affects 8541*e4b17023SJohn Marinothe treatment of operator @samp{|} in the regular expressions. The 8542*e4b17023SJohn Marinousual treatment of the operator is to try the first alternative and, 8543*e4b17023SJohn Marinoif the reservation is not possible, the second alternative. The 8544*e4b17023SJohn Marinonondeterministic treatment means trying all alternatives, some of them 8545*e4b17023SJohn Marinomay be rejected by reservations in the subsequent insns. 8546*e4b17023SJohn Marino 8547*e4b17023SJohn Marino@item 8548*e4b17023SJohn Marino@dfn{collapse-ndfa} modifies the behaviour of the generator when 8549*e4b17023SJohn Marinoproducing an automaton. An additional state transition to collapse a 8550*e4b17023SJohn Marinonondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA} 8551*e4b17023SJohn Marinostate is generated. It can be triggered by passing @code{const0_rtx} to 8552*e4b17023SJohn Marinostate_transition. In such an automaton, cycle advance transitions are 8553*e4b17023SJohn Marinoavailable only for these collapsed states. This option is useful for 8554*e4b17023SJohn Marinoports that want to use the @code{ndfa} option, but also want to use 8555*e4b17023SJohn Marino@code{define_query_cpu_unit} to assign units to insns issued in a cycle. 8556*e4b17023SJohn Marino 8557*e4b17023SJohn Marino@item 8558*e4b17023SJohn Marino@dfn{progress} means output of a progress bar showing how many states 8559*e4b17023SJohn Marinowere generated so far for automaton being processed. This is useful 8560*e4b17023SJohn Marinoduring debugging a @acronym{DFA} description. If you see too many 8561*e4b17023SJohn Marinogenerated states, you could interrupt the generator of the pipeline 8562*e4b17023SJohn Marinohazard recognizer and try to figure out a reason for generation of the 8563*e4b17023SJohn Marinohuge automaton. 8564*e4b17023SJohn Marino@end itemize 8565*e4b17023SJohn Marino 8566*e4b17023SJohn MarinoAs an example, consider a superscalar @acronym{RISC} machine which can 8567*e4b17023SJohn Marinoissue three insns (two integer insns and one floating point insn) on 8568*e4b17023SJohn Marinothe cycle but can finish only two insns. To describe this, we define 8569*e4b17023SJohn Marinothe following functional units. 8570*e4b17023SJohn Marino 8571*e4b17023SJohn Marino@smallexample 8572*e4b17023SJohn Marino(define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline") 8573*e4b17023SJohn Marino(define_cpu_unit "port0, port1") 8574*e4b17023SJohn Marino@end smallexample 8575*e4b17023SJohn Marino 8576*e4b17023SJohn MarinoAll simple integer insns can be executed in any integer pipeline and 8577*e4b17023SJohn Marinotheir result is ready in two cycles. The simple integer insns are 8578*e4b17023SJohn Marinoissued into the first pipeline unless it is reserved, otherwise they 8579*e4b17023SJohn Marinoare issued into the second pipeline. Integer division and 8580*e4b17023SJohn Marinomultiplication insns can be executed only in the second integer 8581*e4b17023SJohn Marinopipeline and their results are ready correspondingly in 8 and 4 8582*e4b17023SJohn Marinocycles. The integer division is not pipelined, i.e.@: the subsequent 8583*e4b17023SJohn Marinointeger division insn can not be issued until the current division 8584*e4b17023SJohn Marinoinsn finished. Floating point insns are fully pipelined and their 8585*e4b17023SJohn Marinoresults are ready in 3 cycles. Where the result of a floating point 8586*e4b17023SJohn Marinoinsn is used by an integer insn, an additional delay of one cycle is 8587*e4b17023SJohn Marinoincurred. To describe all of this we could specify 8588*e4b17023SJohn Marino 8589*e4b17023SJohn Marino@smallexample 8590*e4b17023SJohn Marino(define_cpu_unit "div") 8591*e4b17023SJohn Marino 8592*e4b17023SJohn Marino(define_insn_reservation "simple" 2 (eq_attr "type" "int") 8593*e4b17023SJohn Marino "(i0_pipeline | i1_pipeline), (port0 | port1)") 8594*e4b17023SJohn Marino 8595*e4b17023SJohn Marino(define_insn_reservation "mult" 4 (eq_attr "type" "mult") 8596*e4b17023SJohn Marino "i1_pipeline, nothing*2, (port0 | port1)") 8597*e4b17023SJohn Marino 8598*e4b17023SJohn Marino(define_insn_reservation "div" 8 (eq_attr "type" "div") 8599*e4b17023SJohn Marino "i1_pipeline, div*7, div + (port0 | port1)") 8600*e4b17023SJohn Marino 8601*e4b17023SJohn Marino(define_insn_reservation "float" 3 (eq_attr "type" "float") 8602*e4b17023SJohn Marino "f_pipeline, nothing, (port0 | port1)) 8603*e4b17023SJohn Marino 8604*e4b17023SJohn Marino(define_bypass 4 "float" "simple,mult,div") 8605*e4b17023SJohn Marino@end smallexample 8606*e4b17023SJohn Marino 8607*e4b17023SJohn MarinoTo simplify the description we could describe the following reservation 8608*e4b17023SJohn Marino 8609*e4b17023SJohn Marino@smallexample 8610*e4b17023SJohn Marino(define_reservation "finish" "port0|port1") 8611*e4b17023SJohn Marino@end smallexample 8612*e4b17023SJohn Marino 8613*e4b17023SJohn Marinoand use it in all @code{define_insn_reservation} as in the following 8614*e4b17023SJohn Marinoconstruction 8615*e4b17023SJohn Marino 8616*e4b17023SJohn Marino@smallexample 8617*e4b17023SJohn Marino(define_insn_reservation "simple" 2 (eq_attr "type" "int") 8618*e4b17023SJohn Marino "(i0_pipeline | i1_pipeline), finish") 8619*e4b17023SJohn Marino@end smallexample 8620*e4b17023SJohn Marino 8621*e4b17023SJohn Marino 8622*e4b17023SJohn Marino@end ifset 8623*e4b17023SJohn Marino@ifset INTERNALS 8624*e4b17023SJohn Marino@node Conditional Execution 8625*e4b17023SJohn Marino@section Conditional Execution 8626*e4b17023SJohn Marino@cindex conditional execution 8627*e4b17023SJohn Marino@cindex predication 8628*e4b17023SJohn Marino 8629*e4b17023SJohn MarinoA number of architectures provide for some form of conditional 8630*e4b17023SJohn Marinoexecution, or predication. The hallmark of this feature is the 8631*e4b17023SJohn Marinoability to nullify most of the instructions in the instruction set. 8632*e4b17023SJohn MarinoWhen the instruction set is large and not entirely symmetric, it 8633*e4b17023SJohn Marinocan be quite tedious to describe these forms directly in the 8634*e4b17023SJohn Marino@file{.md} file. An alternative is the @code{define_cond_exec} template. 8635*e4b17023SJohn Marino 8636*e4b17023SJohn Marino@findex define_cond_exec 8637*e4b17023SJohn Marino@smallexample 8638*e4b17023SJohn Marino(define_cond_exec 8639*e4b17023SJohn Marino [@var{predicate-pattern}] 8640*e4b17023SJohn Marino "@var{condition}" 8641*e4b17023SJohn Marino "@var{output-template}") 8642*e4b17023SJohn Marino@end smallexample 8643*e4b17023SJohn Marino 8644*e4b17023SJohn Marino@var{predicate-pattern} is the condition that must be true for the 8645*e4b17023SJohn Marinoinsn to be executed at runtime and should match a relational operator. 8646*e4b17023SJohn MarinoOne can use @code{match_operator} to match several relational operators 8647*e4b17023SJohn Marinoat once. Any @code{match_operand} operands must have no more than one 8648*e4b17023SJohn Marinoalternative. 8649*e4b17023SJohn Marino 8650*e4b17023SJohn Marino@var{condition} is a C expression that must be true for the generated 8651*e4b17023SJohn Marinopattern to match. 8652*e4b17023SJohn Marino 8653*e4b17023SJohn Marino@findex current_insn_predicate 8654*e4b17023SJohn Marino@var{output-template} is a string similar to the @code{define_insn} 8655*e4b17023SJohn Marinooutput template (@pxref{Output Template}), except that the @samp{*} 8656*e4b17023SJohn Marinoand @samp{@@} special cases do not apply. This is only useful if the 8657*e4b17023SJohn Marinoassembly text for the predicate is a simple prefix to the main insn. 8658*e4b17023SJohn MarinoIn order to handle the general case, there is a global variable 8659*e4b17023SJohn Marino@code{current_insn_predicate} that will contain the entire predicate 8660*e4b17023SJohn Marinoif the current insn is predicated, and will otherwise be @code{NULL}. 8661*e4b17023SJohn Marino 8662*e4b17023SJohn MarinoWhen @code{define_cond_exec} is used, an implicit reference to 8663*e4b17023SJohn Marinothe @code{predicable} instruction attribute is made. 8664*e4b17023SJohn Marino@xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have 8665*e4b17023SJohn Marinoexactly two elements in its @var{list-of-values}), with the possible 8666*e4b17023SJohn Marinovalues being @code{no} and @code{yes}. The default and all uses in 8667*e4b17023SJohn Marinothe insns must be a simple constant, not a complex expressions. It 8668*e4b17023SJohn Marinomay, however, depend on the alternative, by using a comma-separated 8669*e4b17023SJohn Marinolist of values. If that is the case, the port should also define an 8670*e4b17023SJohn Marino@code{enabled} attribute (@pxref{Disable Insn Alternatives}), which 8671*e4b17023SJohn Marinoshould also allow only @code{no} and @code{yes} as its values. 8672*e4b17023SJohn Marino 8673*e4b17023SJohn MarinoFor each @code{define_insn} for which the @code{predicable} 8674*e4b17023SJohn Marinoattribute is true, a new @code{define_insn} pattern will be 8675*e4b17023SJohn Marinogenerated that matches a predicated version of the instruction. 8676*e4b17023SJohn MarinoFor example, 8677*e4b17023SJohn Marino 8678*e4b17023SJohn Marino@smallexample 8679*e4b17023SJohn Marino(define_insn "addsi" 8680*e4b17023SJohn Marino [(set (match_operand:SI 0 "register_operand" "r") 8681*e4b17023SJohn Marino (plus:SI (match_operand:SI 1 "register_operand" "r") 8682*e4b17023SJohn Marino (match_operand:SI 2 "register_operand" "r")))] 8683*e4b17023SJohn Marino "@var{test1}" 8684*e4b17023SJohn Marino "add %2,%1,%0") 8685*e4b17023SJohn Marino 8686*e4b17023SJohn Marino(define_cond_exec 8687*e4b17023SJohn Marino [(ne (match_operand:CC 0 "register_operand" "c") 8688*e4b17023SJohn Marino (const_int 0))] 8689*e4b17023SJohn Marino "@var{test2}" 8690*e4b17023SJohn Marino "(%0)") 8691*e4b17023SJohn Marino@end smallexample 8692*e4b17023SJohn Marino 8693*e4b17023SJohn Marino@noindent 8694*e4b17023SJohn Marinogenerates a new pattern 8695*e4b17023SJohn Marino 8696*e4b17023SJohn Marino@smallexample 8697*e4b17023SJohn Marino(define_insn "" 8698*e4b17023SJohn Marino [(cond_exec 8699*e4b17023SJohn Marino (ne (match_operand:CC 3 "register_operand" "c") (const_int 0)) 8700*e4b17023SJohn Marino (set (match_operand:SI 0 "register_operand" "r") 8701*e4b17023SJohn Marino (plus:SI (match_operand:SI 1 "register_operand" "r") 8702*e4b17023SJohn Marino (match_operand:SI 2 "register_operand" "r"))))] 8703*e4b17023SJohn Marino "(@var{test2}) && (@var{test1})" 8704*e4b17023SJohn Marino "(%3) add %2,%1,%0") 8705*e4b17023SJohn Marino@end smallexample 8706*e4b17023SJohn Marino 8707*e4b17023SJohn Marino@end ifset 8708*e4b17023SJohn Marino@ifset INTERNALS 8709*e4b17023SJohn Marino@node Constant Definitions 8710*e4b17023SJohn Marino@section Constant Definitions 8711*e4b17023SJohn Marino@cindex constant definitions 8712*e4b17023SJohn Marino@findex define_constants 8713*e4b17023SJohn Marino 8714*e4b17023SJohn MarinoUsing literal constants inside instruction patterns reduces legibility and 8715*e4b17023SJohn Marinocan be a maintenance problem. 8716*e4b17023SJohn Marino 8717*e4b17023SJohn MarinoTo overcome this problem, you may use the @code{define_constants} 8718*e4b17023SJohn Marinoexpression. It contains a vector of name-value pairs. From that 8719*e4b17023SJohn Marinopoint on, wherever any of the names appears in the MD file, it is as 8720*e4b17023SJohn Marinoif the corresponding value had been written instead. You may use 8721*e4b17023SJohn Marino@code{define_constants} multiple times; each appearance adds more 8722*e4b17023SJohn Marinoconstants to the table. It is an error to redefine a constant with 8723*e4b17023SJohn Marinoa different value. 8724*e4b17023SJohn Marino 8725*e4b17023SJohn MarinoTo come back to the a29k load multiple example, instead of 8726*e4b17023SJohn Marino 8727*e4b17023SJohn Marino@smallexample 8728*e4b17023SJohn Marino(define_insn "" 8729*e4b17023SJohn Marino [(match_parallel 0 "load_multiple_operation" 8730*e4b17023SJohn Marino [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 8731*e4b17023SJohn Marino (match_operand:SI 2 "memory_operand" "m")) 8732*e4b17023SJohn Marino (use (reg:SI 179)) 8733*e4b17023SJohn Marino (clobber (reg:SI 179))])] 8734*e4b17023SJohn Marino "" 8735*e4b17023SJohn Marino "loadm 0,0,%1,%2") 8736*e4b17023SJohn Marino@end smallexample 8737*e4b17023SJohn Marino 8738*e4b17023SJohn MarinoYou could write: 8739*e4b17023SJohn Marino 8740*e4b17023SJohn Marino@smallexample 8741*e4b17023SJohn Marino(define_constants [ 8742*e4b17023SJohn Marino (R_BP 177) 8743*e4b17023SJohn Marino (R_FC 178) 8744*e4b17023SJohn Marino (R_CR 179) 8745*e4b17023SJohn Marino (R_Q 180) 8746*e4b17023SJohn Marino]) 8747*e4b17023SJohn Marino 8748*e4b17023SJohn Marino(define_insn "" 8749*e4b17023SJohn Marino [(match_parallel 0 "load_multiple_operation" 8750*e4b17023SJohn Marino [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 8751*e4b17023SJohn Marino (match_operand:SI 2 "memory_operand" "m")) 8752*e4b17023SJohn Marino (use (reg:SI R_CR)) 8753*e4b17023SJohn Marino (clobber (reg:SI R_CR))])] 8754*e4b17023SJohn Marino "" 8755*e4b17023SJohn Marino "loadm 0,0,%1,%2") 8756*e4b17023SJohn Marino@end smallexample 8757*e4b17023SJohn Marino 8758*e4b17023SJohn MarinoThe constants that are defined with a define_constant are also output 8759*e4b17023SJohn Marinoin the insn-codes.h header file as #defines. 8760*e4b17023SJohn Marino 8761*e4b17023SJohn Marino@cindex enumerations 8762*e4b17023SJohn Marino@findex define_c_enum 8763*e4b17023SJohn MarinoYou can also use the machine description file to define enumerations. 8764*e4b17023SJohn MarinoLike the constants defined by @code{define_constant}, these enumerations 8765*e4b17023SJohn Marinoare visible to both the machine description file and the main C code. 8766*e4b17023SJohn Marino 8767*e4b17023SJohn MarinoThe syntax is as follows: 8768*e4b17023SJohn Marino 8769*e4b17023SJohn Marino@smallexample 8770*e4b17023SJohn Marino(define_c_enum "@var{name}" [ 8771*e4b17023SJohn Marino @var{value0} 8772*e4b17023SJohn Marino @var{value1} 8773*e4b17023SJohn Marino @dots{} 8774*e4b17023SJohn Marino @var{valuen} 8775*e4b17023SJohn Marino]) 8776*e4b17023SJohn Marino@end smallexample 8777*e4b17023SJohn Marino 8778*e4b17023SJohn MarinoThis definition causes the equivalent of the following C code to appear 8779*e4b17023SJohn Marinoin @file{insn-constants.h}: 8780*e4b17023SJohn Marino 8781*e4b17023SJohn Marino@smallexample 8782*e4b17023SJohn Marinoenum @var{name} @{ 8783*e4b17023SJohn Marino @var{value0} = 0, 8784*e4b17023SJohn Marino @var{value1} = 1, 8785*e4b17023SJohn Marino @dots{} 8786*e4b17023SJohn Marino @var{valuen} = @var{n} 8787*e4b17023SJohn Marino@}; 8788*e4b17023SJohn Marino#define NUM_@var{cname}_VALUES (@var{n} + 1) 8789*e4b17023SJohn Marino@end smallexample 8790*e4b17023SJohn Marino 8791*e4b17023SJohn Marinowhere @var{cname} is the capitalized form of @var{name}. 8792*e4b17023SJohn MarinoIt also makes each @var{valuei} available in the machine description 8793*e4b17023SJohn Marinofile, just as if it had been declared with: 8794*e4b17023SJohn Marino 8795*e4b17023SJohn Marino@smallexample 8796*e4b17023SJohn Marino(define_constants [(@var{valuei} @var{i})]) 8797*e4b17023SJohn Marino@end smallexample 8798*e4b17023SJohn Marino 8799*e4b17023SJohn MarinoEach @var{valuei} is usually an upper-case identifier and usually 8800*e4b17023SJohn Marinobegins with @var{cname}. 8801*e4b17023SJohn Marino 8802*e4b17023SJohn MarinoYou can split the enumeration definition into as many statements as 8803*e4b17023SJohn Marinoyou like. The above example is directly equivalent to: 8804*e4b17023SJohn Marino 8805*e4b17023SJohn Marino@smallexample 8806*e4b17023SJohn Marino(define_c_enum "@var{name}" [@var{value0}]) 8807*e4b17023SJohn Marino(define_c_enum "@var{name}" [@var{value1}]) 8808*e4b17023SJohn Marino@dots{} 8809*e4b17023SJohn Marino(define_c_enum "@var{name}" [@var{valuen}]) 8810*e4b17023SJohn Marino@end smallexample 8811*e4b17023SJohn Marino 8812*e4b17023SJohn MarinoSplitting the enumeration helps to improve the modularity of each 8813*e4b17023SJohn Marinoindividual @code{.md} file. For example, if a port defines its 8814*e4b17023SJohn Marinosynchronization instructions in a separate @file{sync.md} file, 8815*e4b17023SJohn Marinoit is convenient to define all synchronization-specific enumeration 8816*e4b17023SJohn Marinovalues in @file{sync.md} rather than in the main @file{.md} file. 8817*e4b17023SJohn Marino 8818*e4b17023SJohn MarinoSome enumeration names have special significance to GCC: 8819*e4b17023SJohn Marino 8820*e4b17023SJohn Marino@table @code 8821*e4b17023SJohn Marino@item unspecv 8822*e4b17023SJohn Marino@findex unspec_volatile 8823*e4b17023SJohn MarinoIf an enumeration called @code{unspecv} is defined, GCC will use it 8824*e4b17023SJohn Marinowhen printing out @code{unspec_volatile} expressions. For example: 8825*e4b17023SJohn Marino 8826*e4b17023SJohn Marino@smallexample 8827*e4b17023SJohn Marino(define_c_enum "unspecv" [ 8828*e4b17023SJohn Marino UNSPECV_BLOCKAGE 8829*e4b17023SJohn Marino]) 8830*e4b17023SJohn Marino@end smallexample 8831*e4b17023SJohn Marino 8832*e4b17023SJohn Marinocauses GCC to print @samp{(unspec_volatile @dots{} 0)} as: 8833*e4b17023SJohn Marino 8834*e4b17023SJohn Marino@smallexample 8835*e4b17023SJohn Marino(unspec_volatile ... UNSPECV_BLOCKAGE) 8836*e4b17023SJohn Marino@end smallexample 8837*e4b17023SJohn Marino 8838*e4b17023SJohn Marino@item unspec 8839*e4b17023SJohn Marino@findex unspec 8840*e4b17023SJohn MarinoIf an enumeration called @code{unspec} is defined, GCC will use 8841*e4b17023SJohn Marinoit when printing out @code{unspec} expressions. GCC will also use 8842*e4b17023SJohn Marinoit when printing out @code{unspec_volatile} expressions unless an 8843*e4b17023SJohn Marino@code{unspecv} enumeration is also defined. You can therefore 8844*e4b17023SJohn Marinodecide whether to keep separate enumerations for volatile and 8845*e4b17023SJohn Marinonon-volatile expressions or whether to use the same enumeration 8846*e4b17023SJohn Marinofor both. 8847*e4b17023SJohn Marino@end table 8848*e4b17023SJohn Marino 8849*e4b17023SJohn Marino@findex define_enum 8850*e4b17023SJohn Marino@anchor{define_enum} 8851*e4b17023SJohn MarinoAnother way of defining an enumeration is to use @code{define_enum}: 8852*e4b17023SJohn Marino 8853*e4b17023SJohn Marino@smallexample 8854*e4b17023SJohn Marino(define_enum "@var{name}" [ 8855*e4b17023SJohn Marino @var{value0} 8856*e4b17023SJohn Marino @var{value1} 8857*e4b17023SJohn Marino @dots{} 8858*e4b17023SJohn Marino @var{valuen} 8859*e4b17023SJohn Marino]) 8860*e4b17023SJohn Marino@end smallexample 8861*e4b17023SJohn Marino 8862*e4b17023SJohn MarinoThis directive implies: 8863*e4b17023SJohn Marino 8864*e4b17023SJohn Marino@smallexample 8865*e4b17023SJohn Marino(define_c_enum "@var{name}" [ 8866*e4b17023SJohn Marino @var{cname}_@var{cvalue0} 8867*e4b17023SJohn Marino @var{cname}_@var{cvalue1} 8868*e4b17023SJohn Marino @dots{} 8869*e4b17023SJohn Marino @var{cname}_@var{cvaluen} 8870*e4b17023SJohn Marino]) 8871*e4b17023SJohn Marino@end smallexample 8872*e4b17023SJohn Marino 8873*e4b17023SJohn Marino@findex define_enum_attr 8874*e4b17023SJohn Marinowhere @var{cvaluei} is the capitalized form of @var{valuei}. 8875*e4b17023SJohn MarinoHowever, unlike @code{define_c_enum}, the enumerations defined 8876*e4b17023SJohn Marinoby @code{define_enum} can be used in attribute specifications 8877*e4b17023SJohn Marino(@pxref{define_enum_attr}). 8878*e4b17023SJohn Marino@end ifset 8879*e4b17023SJohn Marino@ifset INTERNALS 8880*e4b17023SJohn Marino@node Iterators 8881*e4b17023SJohn Marino@section Iterators 8882*e4b17023SJohn Marino@cindex iterators in @file{.md} files 8883*e4b17023SJohn Marino 8884*e4b17023SJohn MarinoPorts often need to define similar patterns for more than one machine 8885*e4b17023SJohn Marinomode or for more than one rtx code. GCC provides some simple iterator 8886*e4b17023SJohn Marinofacilities to make this process easier. 8887*e4b17023SJohn Marino 8888*e4b17023SJohn Marino@menu 8889*e4b17023SJohn Marino* Mode Iterators:: Generating variations of patterns for different modes. 8890*e4b17023SJohn Marino* Code Iterators:: Doing the same for codes. 8891*e4b17023SJohn Marino@end menu 8892*e4b17023SJohn Marino 8893*e4b17023SJohn Marino@node Mode Iterators 8894*e4b17023SJohn Marino@subsection Mode Iterators 8895*e4b17023SJohn Marino@cindex mode iterators in @file{.md} files 8896*e4b17023SJohn Marino 8897*e4b17023SJohn MarinoPorts often need to define similar patterns for two or more different modes. 8898*e4b17023SJohn MarinoFor example: 8899*e4b17023SJohn Marino 8900*e4b17023SJohn Marino@itemize @bullet 8901*e4b17023SJohn Marino@item 8902*e4b17023SJohn MarinoIf a processor has hardware support for both single and double 8903*e4b17023SJohn Marinofloating-point arithmetic, the @code{SFmode} patterns tend to be 8904*e4b17023SJohn Marinovery similar to the @code{DFmode} ones. 8905*e4b17023SJohn Marino 8906*e4b17023SJohn Marino@item 8907*e4b17023SJohn MarinoIf a port uses @code{SImode} pointers in one configuration and 8908*e4b17023SJohn Marino@code{DImode} pointers in another, it will usually have very similar 8909*e4b17023SJohn Marino@code{SImode} and @code{DImode} patterns for manipulating pointers. 8910*e4b17023SJohn Marino@end itemize 8911*e4b17023SJohn Marino 8912*e4b17023SJohn MarinoMode iterators allow several patterns to be instantiated from one 8913*e4b17023SJohn Marino@file{.md} file template. They can be used with any type of 8914*e4b17023SJohn Marinortx-based construct, such as a @code{define_insn}, 8915*e4b17023SJohn Marino@code{define_split}, or @code{define_peephole2}. 8916*e4b17023SJohn Marino 8917*e4b17023SJohn Marino@menu 8918*e4b17023SJohn Marino* Defining Mode Iterators:: Defining a new mode iterator. 8919*e4b17023SJohn Marino* Substitutions:: Combining mode iterators with substitutions 8920*e4b17023SJohn Marino* Examples:: Examples 8921*e4b17023SJohn Marino@end menu 8922*e4b17023SJohn Marino 8923*e4b17023SJohn Marino@node Defining Mode Iterators 8924*e4b17023SJohn Marino@subsubsection Defining Mode Iterators 8925*e4b17023SJohn Marino@findex define_mode_iterator 8926*e4b17023SJohn Marino 8927*e4b17023SJohn MarinoThe syntax for defining a mode iterator is: 8928*e4b17023SJohn Marino 8929*e4b17023SJohn Marino@smallexample 8930*e4b17023SJohn Marino(define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")]) 8931*e4b17023SJohn Marino@end smallexample 8932*e4b17023SJohn Marino 8933*e4b17023SJohn MarinoThis allows subsequent @file{.md} file constructs to use the mode suffix 8934*e4b17023SJohn Marino@code{:@var{name}}. Every construct that does so will be expanded 8935*e4b17023SJohn Marino@var{n} times, once with every use of @code{:@var{name}} replaced by 8936*e4b17023SJohn Marino@code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}}, 8937*e4b17023SJohn Marinoand so on. In the expansion for a particular @var{modei}, every 8938*e4b17023SJohn MarinoC condition will also require that @var{condi} be true. 8939*e4b17023SJohn Marino 8940*e4b17023SJohn MarinoFor example: 8941*e4b17023SJohn Marino 8942*e4b17023SJohn Marino@smallexample 8943*e4b17023SJohn Marino(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) 8944*e4b17023SJohn Marino@end smallexample 8945*e4b17023SJohn Marino 8946*e4b17023SJohn Marinodefines a new mode suffix @code{:P}. Every construct that uses 8947*e4b17023SJohn Marino@code{:P} will be expanded twice, once with every @code{:P} replaced 8948*e4b17023SJohn Marinoby @code{:SI} and once with every @code{:P} replaced by @code{:DI}. 8949*e4b17023SJohn MarinoThe @code{:SI} version will only apply if @code{Pmode == SImode} and 8950*e4b17023SJohn Marinothe @code{:DI} version will only apply if @code{Pmode == DImode}. 8951*e4b17023SJohn Marino 8952*e4b17023SJohn MarinoAs with other @file{.md} conditions, an empty string is treated 8953*e4b17023SJohn Marinoas ``always true''. @code{(@var{mode} "")} can also be abbreviated 8954*e4b17023SJohn Marinoto @code{@var{mode}}. For example: 8955*e4b17023SJohn Marino 8956*e4b17023SJohn Marino@smallexample 8957*e4b17023SJohn Marino(define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) 8958*e4b17023SJohn Marino@end smallexample 8959*e4b17023SJohn Marino 8960*e4b17023SJohn Marinomeans that the @code{:DI} expansion only applies if @code{TARGET_64BIT} 8961*e4b17023SJohn Marinobut that the @code{:SI} expansion has no such constraint. 8962*e4b17023SJohn Marino 8963*e4b17023SJohn MarinoIterators are applied in the order they are defined. This can be 8964*e4b17023SJohn Marinosignificant if two iterators are used in a construct that requires 8965*e4b17023SJohn Marinosubstitutions. @xref{Substitutions}. 8966*e4b17023SJohn Marino 8967*e4b17023SJohn Marino@node Substitutions 8968*e4b17023SJohn Marino@subsubsection Substitution in Mode Iterators 8969*e4b17023SJohn Marino@findex define_mode_attr 8970*e4b17023SJohn Marino 8971*e4b17023SJohn MarinoIf an @file{.md} file construct uses mode iterators, each version of the 8972*e4b17023SJohn Marinoconstruct will often need slightly different strings or modes. For 8973*e4b17023SJohn Marinoexample: 8974*e4b17023SJohn Marino 8975*e4b17023SJohn Marino@itemize @bullet 8976*e4b17023SJohn Marino@item 8977*e4b17023SJohn MarinoWhen a @code{define_expand} defines several @code{add@var{m}3} patterns 8978*e4b17023SJohn Marino(@pxref{Standard Names}), each expander will need to use the 8979*e4b17023SJohn Marinoappropriate mode name for @var{m}. 8980*e4b17023SJohn Marino 8981*e4b17023SJohn Marino@item 8982*e4b17023SJohn MarinoWhen a @code{define_insn} defines several instruction patterns, 8983*e4b17023SJohn Marinoeach instruction will often use a different assembler mnemonic. 8984*e4b17023SJohn Marino 8985*e4b17023SJohn Marino@item 8986*e4b17023SJohn MarinoWhen a @code{define_insn} requires operands with different modes, 8987*e4b17023SJohn Marinousing an iterator for one of the operand modes usually requires a specific 8988*e4b17023SJohn Marinomode for the other operand(s). 8989*e4b17023SJohn Marino@end itemize 8990*e4b17023SJohn Marino 8991*e4b17023SJohn MarinoGCC supports such variations through a system of ``mode attributes''. 8992*e4b17023SJohn MarinoThere are two standard attributes: @code{mode}, which is the name of 8993*e4b17023SJohn Marinothe mode in lower case, and @code{MODE}, which is the same thing in 8994*e4b17023SJohn Marinoupper case. You can define other attributes using: 8995*e4b17023SJohn Marino 8996*e4b17023SJohn Marino@smallexample 8997*e4b17023SJohn Marino(define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")]) 8998*e4b17023SJohn Marino@end smallexample 8999*e4b17023SJohn Marino 9000*e4b17023SJohn Marinowhere @var{name} is the name of the attribute and @var{valuei} 9001*e4b17023SJohn Marinois the value associated with @var{modei}. 9002*e4b17023SJohn Marino 9003*e4b17023SJohn MarinoWhen GCC replaces some @var{:iterator} with @var{:mode}, it will scan 9004*e4b17023SJohn Marinoeach string and mode in the pattern for sequences of the form 9005*e4b17023SJohn Marino@code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a 9006*e4b17023SJohn Marinomode attribute. If the attribute is defined for @var{mode}, the whole 9007*e4b17023SJohn Marino@code{<@dots{}>} sequence will be replaced by the appropriate attribute 9008*e4b17023SJohn Marinovalue. 9009*e4b17023SJohn Marino 9010*e4b17023SJohn MarinoFor example, suppose an @file{.md} file has: 9011*e4b17023SJohn Marino 9012*e4b17023SJohn Marino@smallexample 9013*e4b17023SJohn Marino(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) 9014*e4b17023SJohn Marino(define_mode_attr load [(SI "lw") (DI "ld")]) 9015*e4b17023SJohn Marino@end smallexample 9016*e4b17023SJohn Marino 9017*e4b17023SJohn MarinoIf one of the patterns that uses @code{:P} contains the string 9018*e4b17023SJohn Marino@code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern 9019*e4b17023SJohn Marinowill use @code{"lw\t%0,%1"} and the @code{DI} version will use 9020*e4b17023SJohn Marino@code{"ld\t%0,%1"}. 9021*e4b17023SJohn Marino 9022*e4b17023SJohn MarinoHere is an example of using an attribute for a mode: 9023*e4b17023SJohn Marino 9024*e4b17023SJohn Marino@smallexample 9025*e4b17023SJohn Marino(define_mode_iterator LONG [SI DI]) 9026*e4b17023SJohn Marino(define_mode_attr SHORT [(SI "HI") (DI "SI")]) 9027*e4b17023SJohn Marino(define_insn @dots{} 9028*e4b17023SJohn Marino (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{}) 9029*e4b17023SJohn Marino@end smallexample 9030*e4b17023SJohn Marino 9031*e4b17023SJohn MarinoThe @code{@var{iterator}:} prefix may be omitted, in which case the 9032*e4b17023SJohn Marinosubstitution will be attempted for every iterator expansion. 9033*e4b17023SJohn Marino 9034*e4b17023SJohn Marino@node Examples 9035*e4b17023SJohn Marino@subsubsection Mode Iterator Examples 9036*e4b17023SJohn Marino 9037*e4b17023SJohn MarinoHere is an example from the MIPS port. It defines the following 9038*e4b17023SJohn Marinomodes and attributes (among others): 9039*e4b17023SJohn Marino 9040*e4b17023SJohn Marino@smallexample 9041*e4b17023SJohn Marino(define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) 9042*e4b17023SJohn Marino(define_mode_attr d [(SI "") (DI "d")]) 9043*e4b17023SJohn Marino@end smallexample 9044*e4b17023SJohn Marino 9045*e4b17023SJohn Marinoand uses the following template to define both @code{subsi3} 9046*e4b17023SJohn Marinoand @code{subdi3}: 9047*e4b17023SJohn Marino 9048*e4b17023SJohn Marino@smallexample 9049*e4b17023SJohn Marino(define_insn "sub<mode>3" 9050*e4b17023SJohn Marino [(set (match_operand:GPR 0 "register_operand" "=d") 9051*e4b17023SJohn Marino (minus:GPR (match_operand:GPR 1 "register_operand" "d") 9052*e4b17023SJohn Marino (match_operand:GPR 2 "register_operand" "d")))] 9053*e4b17023SJohn Marino "" 9054*e4b17023SJohn Marino "<d>subu\t%0,%1,%2" 9055*e4b17023SJohn Marino [(set_attr "type" "arith") 9056*e4b17023SJohn Marino (set_attr "mode" "<MODE>")]) 9057*e4b17023SJohn Marino@end smallexample 9058*e4b17023SJohn Marino 9059*e4b17023SJohn MarinoThis is exactly equivalent to: 9060*e4b17023SJohn Marino 9061*e4b17023SJohn Marino@smallexample 9062*e4b17023SJohn Marino(define_insn "subsi3" 9063*e4b17023SJohn Marino [(set (match_operand:SI 0 "register_operand" "=d") 9064*e4b17023SJohn Marino (minus:SI (match_operand:SI 1 "register_operand" "d") 9065*e4b17023SJohn Marino (match_operand:SI 2 "register_operand" "d")))] 9066*e4b17023SJohn Marino "" 9067*e4b17023SJohn Marino "subu\t%0,%1,%2" 9068*e4b17023SJohn Marino [(set_attr "type" "arith") 9069*e4b17023SJohn Marino (set_attr "mode" "SI")]) 9070*e4b17023SJohn Marino 9071*e4b17023SJohn Marino(define_insn "subdi3" 9072*e4b17023SJohn Marino [(set (match_operand:DI 0 "register_operand" "=d") 9073*e4b17023SJohn Marino (minus:DI (match_operand:DI 1 "register_operand" "d") 9074*e4b17023SJohn Marino (match_operand:DI 2 "register_operand" "d")))] 9075*e4b17023SJohn Marino "" 9076*e4b17023SJohn Marino "dsubu\t%0,%1,%2" 9077*e4b17023SJohn Marino [(set_attr "type" "arith") 9078*e4b17023SJohn Marino (set_attr "mode" "DI")]) 9079*e4b17023SJohn Marino@end smallexample 9080*e4b17023SJohn Marino 9081*e4b17023SJohn Marino@node Code Iterators 9082*e4b17023SJohn Marino@subsection Code Iterators 9083*e4b17023SJohn Marino@cindex code iterators in @file{.md} files 9084*e4b17023SJohn Marino@findex define_code_iterator 9085*e4b17023SJohn Marino@findex define_code_attr 9086*e4b17023SJohn Marino 9087*e4b17023SJohn MarinoCode iterators operate in a similar way to mode iterators. @xref{Mode Iterators}. 9088*e4b17023SJohn Marino 9089*e4b17023SJohn MarinoThe construct: 9090*e4b17023SJohn Marino 9091*e4b17023SJohn Marino@smallexample 9092*e4b17023SJohn Marino(define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")]) 9093*e4b17023SJohn Marino@end smallexample 9094*e4b17023SJohn Marino 9095*e4b17023SJohn Marinodefines a pseudo rtx code @var{name} that can be instantiated as 9096*e4b17023SJohn Marino@var{codei} if condition @var{condi} is true. Each @var{codei} 9097*e4b17023SJohn Marinomust have the same rtx format. @xref{RTL Classes}. 9098*e4b17023SJohn Marino 9099*e4b17023SJohn MarinoAs with mode iterators, each pattern that uses @var{name} will be 9100*e4b17023SJohn Marinoexpanded @var{n} times, once with all uses of @var{name} replaced by 9101*e4b17023SJohn Marino@var{code1}, once with all uses replaced by @var{code2}, and so on. 9102*e4b17023SJohn Marino@xref{Defining Mode Iterators}. 9103*e4b17023SJohn Marino 9104*e4b17023SJohn MarinoIt is possible to define attributes for codes as well as for modes. 9105*e4b17023SJohn MarinoThere are two standard code attributes: @code{code}, the name of the 9106*e4b17023SJohn Marinocode in lower case, and @code{CODE}, the name of the code in upper case. 9107*e4b17023SJohn MarinoOther attributes are defined using: 9108*e4b17023SJohn Marino 9109*e4b17023SJohn Marino@smallexample 9110*e4b17023SJohn Marino(define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")]) 9111*e4b17023SJohn Marino@end smallexample 9112*e4b17023SJohn Marino 9113*e4b17023SJohn MarinoHere's an example of code iterators in action, taken from the MIPS port: 9114*e4b17023SJohn Marino 9115*e4b17023SJohn Marino@smallexample 9116*e4b17023SJohn Marino(define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt 9117*e4b17023SJohn Marino eq ne gt ge lt le gtu geu ltu leu]) 9118*e4b17023SJohn Marino 9119*e4b17023SJohn Marino(define_expand "b<code>" 9120*e4b17023SJohn Marino [(set (pc) 9121*e4b17023SJohn Marino (if_then_else (any_cond:CC (cc0) 9122*e4b17023SJohn Marino (const_int 0)) 9123*e4b17023SJohn Marino (label_ref (match_operand 0 "")) 9124*e4b17023SJohn Marino (pc)))] 9125*e4b17023SJohn Marino "" 9126*e4b17023SJohn Marino@{ 9127*e4b17023SJohn Marino gen_conditional_branch (operands, <CODE>); 9128*e4b17023SJohn Marino DONE; 9129*e4b17023SJohn Marino@}) 9130*e4b17023SJohn Marino@end smallexample 9131*e4b17023SJohn Marino 9132*e4b17023SJohn MarinoThis is equivalent to: 9133*e4b17023SJohn Marino 9134*e4b17023SJohn Marino@smallexample 9135*e4b17023SJohn Marino(define_expand "bunordered" 9136*e4b17023SJohn Marino [(set (pc) 9137*e4b17023SJohn Marino (if_then_else (unordered:CC (cc0) 9138*e4b17023SJohn Marino (const_int 0)) 9139*e4b17023SJohn Marino (label_ref (match_operand 0 "")) 9140*e4b17023SJohn Marino (pc)))] 9141*e4b17023SJohn Marino "" 9142*e4b17023SJohn Marino@{ 9143*e4b17023SJohn Marino gen_conditional_branch (operands, UNORDERED); 9144*e4b17023SJohn Marino DONE; 9145*e4b17023SJohn Marino@}) 9146*e4b17023SJohn Marino 9147*e4b17023SJohn Marino(define_expand "bordered" 9148*e4b17023SJohn Marino [(set (pc) 9149*e4b17023SJohn Marino (if_then_else (ordered:CC (cc0) 9150*e4b17023SJohn Marino (const_int 0)) 9151*e4b17023SJohn Marino (label_ref (match_operand 0 "")) 9152*e4b17023SJohn Marino (pc)))] 9153*e4b17023SJohn Marino "" 9154*e4b17023SJohn Marino@{ 9155*e4b17023SJohn Marino gen_conditional_branch (operands, ORDERED); 9156*e4b17023SJohn Marino DONE; 9157*e4b17023SJohn Marino@}) 9158*e4b17023SJohn Marino 9159*e4b17023SJohn Marino@dots{} 9160*e4b17023SJohn Marino@end smallexample 9161*e4b17023SJohn Marino 9162*e4b17023SJohn Marino@end ifset 9163