1 /* IA-32 common hooks. 2 Copyright (C) 1988-2018 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "diagnostic-core.h" 24 #include "tm.h" 25 #include "memmodel.h" 26 #include "tm_p.h" 27 #include "common/common-target.h" 28 #include "common/common-target-def.h" 29 #include "opts.h" 30 #include "flags.h" 31 32 /* Define a set of ISAs which are available when a given ISA is 33 enabled. MMX and SSE ISAs are handled separately. */ 34 35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX 36 #define OPTION_MASK_ISA_3DNOW_SET \ 37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET) 38 #define OPTION_MASK_ISA_3DNOW_A_SET \ 39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET) 40 41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE 42 #define OPTION_MASK_ISA_SSE2_SET \ 43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET) 44 #define OPTION_MASK_ISA_SSE3_SET \ 45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET) 46 #define OPTION_MASK_ISA_SSSE3_SET \ 47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET) 48 #define OPTION_MASK_ISA_SSE4_1_SET \ 49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET) 50 #define OPTION_MASK_ISA_SSE4_2_SET \ 51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET) 52 #define OPTION_MASK_ISA_AVX_SET \ 53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \ 54 | OPTION_MASK_ISA_XSAVE_SET) 55 #define OPTION_MASK_ISA_FMA_SET \ 56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) 57 #define OPTION_MASK_ISA_AVX2_SET \ 58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) 59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR 60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE 61 #define OPTION_MASK_ISA_XSAVEOPT_SET \ 62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET) 63 #define OPTION_MASK_ISA_AVX512F_SET \ 64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET) 65 #define OPTION_MASK_ISA_AVX512CD_SET \ 66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET) 67 #define OPTION_MASK_ISA_AVX512PF_SET \ 68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET) 69 #define OPTION_MASK_ISA_AVX512ER_SET \ 70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET) 71 #define OPTION_MASK_ISA_AVX512DQ_SET \ 72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET) 73 #define OPTION_MASK_ISA_AVX512BW_SET \ 74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET) 75 #define OPTION_MASK_ISA_AVX512VL_SET \ 76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET) 77 #define OPTION_MASK_ISA_AVX512IFMA_SET \ 78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) 79 #define OPTION_MASK_ISA_AVX512VBMI_SET \ 80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) 81 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS 82 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW 83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \ 84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) 85 #define OPTION_MASK_ISA_AVX512VNNI_SET \ 86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET) 87 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ 88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) 89 #define OPTION_MASK_ISA_AVX512BITALG_SET \ 90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) 91 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM 92 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW 93 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED 94 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX 95 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1 96 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT 97 #define OPTION_MASK_ISA_XSAVES_SET \ 98 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET) 99 #define OPTION_MASK_ISA_XSAVEC_SET \ 100 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET) 101 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB 102 103 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same 104 as -msse4.2. */ 105 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET 106 107 #define OPTION_MASK_ISA_SSE4A_SET \ 108 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET) 109 #define OPTION_MASK_ISA_FMA4_SET \ 110 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \ 111 | OPTION_MASK_ISA_AVX_SET) 112 #define OPTION_MASK_ISA_XOP_SET \ 113 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET) 114 #define OPTION_MASK_ISA_LWP_SET \ 115 OPTION_MASK_ISA_LWP 116 117 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */ 118 #define OPTION_MASK_ISA_AES_SET \ 119 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET) 120 #define OPTION_MASK_ISA_SHA_SET \ 121 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET) 122 #define OPTION_MASK_ISA_PCLMUL_SET \ 123 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) 124 125 #define OPTION_MASK_ISA_ABM_SET \ 126 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) 127 128 #define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG 129 #define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD 130 #define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX 131 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI 132 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 133 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT 134 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM 135 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT 136 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16 137 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF 138 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE 139 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 140 141 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE 142 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND 143 #define OPTION_MASK_ISA_F16C_SET \ 144 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) 145 #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX 146 #define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO 147 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU 148 #define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID 149 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI 150 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK 151 #define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES 152 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ 153 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI 154 #define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B 155 156 /* Define a set of ISAs which aren't available when a given ISA is 157 disabled. MMX and SSE ISAs are handled separately. */ 158 159 #define OPTION_MASK_ISA_MMX_UNSET \ 160 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET) 161 #define OPTION_MASK_ISA_3DNOW_UNSET \ 162 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET) 163 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A 164 165 #define OPTION_MASK_ISA_SSE_UNSET \ 166 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET) 167 #define OPTION_MASK_ISA_SSE2_UNSET \ 168 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET) 169 #define OPTION_MASK_ISA_SSE3_UNSET \ 170 (OPTION_MASK_ISA_SSE3 \ 171 | OPTION_MASK_ISA_SSSE3_UNSET \ 172 | OPTION_MASK_ISA_SSE4A_UNSET ) 173 #define OPTION_MASK_ISA_SSSE3_UNSET \ 174 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET) 175 #define OPTION_MASK_ISA_SSE4_1_UNSET \ 176 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET) 177 #define OPTION_MASK_ISA_SSE4_2_UNSET \ 178 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) 179 #define OPTION_MASK_ISA_AVX_UNSET \ 180 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ 181 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ 182 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET) 183 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA 184 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR 185 #define OPTION_MASK_ISA_XSAVE_UNSET \ 186 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \ 187 | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET) 188 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT 189 #define OPTION_MASK_ISA_AVX2_UNSET \ 190 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET) 191 #define OPTION_MASK_ISA_AVX512F_UNSET \ 192 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ 193 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ 194 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \ 195 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512VBMI2_UNSET \ 196 | OPTION_MASK_ISA_AVX512VNNI_UNSET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \ 197 | OPTION_MASK_ISA_AVX512BITALG_UNSET) 198 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD 199 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF 200 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER 201 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ 202 #define OPTION_MASK_ISA_AVX512BW_UNSET \ 203 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) 204 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL 205 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA 206 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI 207 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS 208 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW 209 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 210 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI 211 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ 212 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG 213 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM 214 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW 215 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED 216 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX 217 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1 218 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT 219 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC 220 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES 221 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB 222 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX 223 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO 224 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU 225 #define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID 226 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI 227 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK 228 #define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES 229 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ 230 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI 231 #define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B 232 233 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same 234 as -mno-sse4.1. */ 235 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET 236 237 #define OPTION_MASK_ISA_SSE4A_UNSET \ 238 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET) 239 240 #define OPTION_MASK_ISA_FMA4_UNSET \ 241 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET) 242 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP 243 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP 244 245 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES 246 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA 247 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL 248 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM 249 #define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG 250 #define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD 251 #define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX 252 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI 253 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 254 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT 255 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM 256 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT 257 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16 258 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF 259 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE 260 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 261 262 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE 263 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND 264 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C 265 266 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ 267 (OPTION_MASK_ISA_MMX_UNSET \ 268 | OPTION_MASK_ISA_SSE_UNSET) 269 270 #define OPTION_MASK_ISA2_AVX512F_UNSET \ 271 (OPTION_MASK_ISA_AVX5124FMAPS_UNSET | OPTION_MASK_ISA_AVX5124VNNIW_UNSET) 272 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ 273 (OPTION_MASK_ISA2_AVX512F_UNSET | OPTION_MASK_ISA_MPX) 274 275 /* Implement TARGET_HANDLE_OPTION. */ 276 277 bool 278 ix86_handle_option (struct gcc_options *opts, 279 struct gcc_options *opts_set ATTRIBUTE_UNUSED, 280 const struct cl_decoded_option *decoded, 281 location_t loc) 282 { 283 size_t code = decoded->opt_index; 284 int value = decoded->value; 285 286 switch (code) 287 { 288 case OPT_mgeneral_regs_only: 289 if (value) 290 { 291 /* Disable MPX, MMX, SSE and x87 instructions if only 292 general registers are allowed. */ 293 opts->x_ix86_isa_flags 294 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; 295 opts->x_ix86_isa_flags2 296 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; 297 opts->x_ix86_isa_flags_explicit 298 |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; 299 opts->x_ix86_isa_flags2_explicit 300 |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; 301 302 opts->x_target_flags &= ~MASK_80387; 303 } 304 else 305 gcc_unreachable (); 306 return true; 307 308 case OPT_mmmx: 309 if (value) 310 { 311 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET; 312 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET; 313 } 314 else 315 { 316 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET; 317 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET; 318 } 319 return true; 320 321 case OPT_m3dnow: 322 if (value) 323 { 324 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET; 325 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET; 326 } 327 else 328 { 329 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET; 330 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET; 331 } 332 return true; 333 334 case OPT_m3dnowa: 335 if (value) 336 { 337 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET; 338 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET; 339 } 340 else 341 { 342 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET; 343 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET; 344 } 345 return true; 346 347 case OPT_msse: 348 if (value) 349 { 350 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET; 351 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET; 352 } 353 else 354 { 355 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET; 356 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET; 357 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 358 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 359 } 360 return true; 361 362 case OPT_msse2: 363 if (value) 364 { 365 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET; 366 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET; 367 } 368 else 369 { 370 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET; 371 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET; 372 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 373 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 374 } 375 return true; 376 377 case OPT_msse3: 378 if (value) 379 { 380 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET; 381 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET; 382 } 383 else 384 { 385 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET; 386 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET; 387 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 388 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 389 } 390 return true; 391 392 case OPT_mssse3: 393 if (value) 394 { 395 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET; 396 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET; 397 } 398 else 399 { 400 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET; 401 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET; 402 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 403 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 404 } 405 return true; 406 407 case OPT_msse4_1: 408 if (value) 409 { 410 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET; 411 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET; 412 } 413 else 414 { 415 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET; 416 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET; 417 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 418 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 419 } 420 return true; 421 422 case OPT_msse4_2: 423 if (value) 424 { 425 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET; 426 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET; 427 } 428 else 429 { 430 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET; 431 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET; 432 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 433 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 434 } 435 return true; 436 437 case OPT_mavx: 438 if (value) 439 { 440 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; 441 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; 442 } 443 else 444 { 445 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET; 446 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET; 447 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 448 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 449 } 450 return true; 451 452 case OPT_mavx2: 453 if (value) 454 { 455 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; 456 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; 457 } 458 else 459 { 460 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET; 461 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET; 462 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 463 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 464 } 465 return true; 466 467 case OPT_mavx512f: 468 if (value) 469 { 470 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; 471 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; 472 } 473 else 474 { 475 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET; 476 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET; 477 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 478 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 479 } 480 return true; 481 482 case OPT_mavx512cd: 483 if (value) 484 { 485 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET; 486 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET; 487 } 488 else 489 { 490 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET; 491 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET; 492 } 493 return true; 494 495 case OPT_mavx512pf: 496 if (value) 497 { 498 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET; 499 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET; 500 } 501 else 502 { 503 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET; 504 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET; 505 } 506 return true; 507 508 case OPT_mavx512er: 509 if (value) 510 { 511 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET; 512 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET; 513 } 514 else 515 { 516 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET; 517 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET; 518 } 519 return true; 520 521 case OPT_mrdpid: 522 if (value) 523 { 524 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET; 525 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET; 526 } 527 else 528 { 529 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET; 530 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET; 531 } 532 return true; 533 534 case OPT_mgfni: 535 if (value) 536 { 537 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET; 538 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET; 539 } 540 else 541 { 542 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET; 543 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET; 544 } 545 return true; 546 547 case OPT_mshstk: 548 if (value) 549 { 550 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET; 551 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET; 552 } 553 else 554 { 555 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET; 556 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET; 557 } 558 return true; 559 560 case OPT_mvaes: 561 if (value) 562 { 563 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET; 564 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET; 565 } 566 else 567 { 568 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET; 569 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET; 570 } 571 return true; 572 573 case OPT_mvpclmulqdq: 574 if (value) 575 { 576 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET; 577 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET; 578 } 579 else 580 { 581 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET; 582 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET; 583 } 584 return true; 585 586 case OPT_mmovdiri: 587 if (value) 588 { 589 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET; 590 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET; 591 } 592 else 593 { 594 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET; 595 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET; 596 } 597 return true; 598 599 case OPT_mmovdir64b: 600 if (value) 601 { 602 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B_SET; 603 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_SET; 604 } 605 else 606 { 607 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVDIR64B_UNSET; 608 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_UNSET; 609 } 610 return true; 611 612 case OPT_mavx5124fmaps: 613 if (value) 614 { 615 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET; 616 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET; 617 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; 618 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; 619 } 620 else 621 { 622 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET; 623 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET; 624 } 625 return true; 626 627 case OPT_mavx5124vnniw: 628 if (value) 629 { 630 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET; 631 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET; 632 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; 633 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; 634 } 635 else 636 { 637 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET; 638 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET; 639 } 640 return true; 641 642 case OPT_mavx512vbmi2: 643 if (value) 644 { 645 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET; 646 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET; 647 } 648 else 649 { 650 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET; 651 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET; 652 } 653 return true; 654 655 case OPT_mavx512vnni: 656 if (value) 657 { 658 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET; 659 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET; 660 } 661 else 662 { 663 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET; 664 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET; 665 } 666 return true; 667 668 case OPT_mavx512vpopcntdq: 669 if (value) 670 { 671 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; 672 opts->x_ix86_isa_flags_explicit 673 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; 674 } 675 else 676 { 677 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; 678 opts->x_ix86_isa_flags_explicit 679 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; 680 } 681 return true; 682 683 case OPT_mavx512bitalg: 684 if (value) 685 { 686 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET; 687 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET; 688 } 689 else 690 { 691 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET; 692 opts->x_ix86_isa_flags_explicit 693 |= OPTION_MASK_ISA_AVX512BITALG_UNSET; 694 } 695 return true; 696 697 case OPT_msgx: 698 if (value) 699 { 700 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET; 701 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET; 702 } 703 else 704 { 705 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET; 706 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET; 707 } 708 return true; 709 710 case OPT_mpconfig: 711 if (value) 712 { 713 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG_SET; 714 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_SET; 715 } 716 else 717 { 718 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PCONFIG_UNSET; 719 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_UNSET; 720 } 721 return true; 722 723 case OPT_mwbnoinvd: 724 if (value) 725 { 726 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD_SET; 727 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_SET; 728 } 729 else 730 { 731 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WBNOINVD_UNSET; 732 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_UNSET; 733 } 734 return true; 735 736 case OPT_mavx512dq: 737 if (value) 738 { 739 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET; 740 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET; 741 } 742 else 743 { 744 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET; 745 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET; 746 } 747 return true; 748 749 case OPT_mavx512bw: 750 if (value) 751 { 752 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET; 753 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET; 754 } 755 else 756 { 757 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET; 758 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET; 759 } 760 return true; 761 762 case OPT_mavx512vl: 763 if (value) 764 { 765 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET; 766 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET; 767 } 768 else 769 { 770 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET; 771 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET; 772 } 773 return true; 774 775 case OPT_mavx512ifma: 776 if (value) 777 { 778 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET; 779 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET; 780 } 781 else 782 { 783 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET; 784 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET; 785 } 786 return true; 787 788 case OPT_mavx512vbmi: 789 if (value) 790 { 791 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET; 792 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET; 793 } 794 else 795 { 796 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET; 797 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET; 798 } 799 return true; 800 801 case OPT_mfma: 802 if (value) 803 { 804 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET; 805 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET; 806 } 807 else 808 { 809 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET; 810 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET; 811 } 812 return true; 813 814 case OPT_mrtm: 815 if (value) 816 { 817 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET; 818 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET; 819 } 820 else 821 { 822 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET; 823 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET; 824 } 825 return true; 826 827 case OPT_msse4: 828 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET; 829 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET; 830 return true; 831 832 case OPT_mno_sse4: 833 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET; 834 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET; 835 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 836 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 837 return true; 838 839 case OPT_msse4a: 840 if (value) 841 { 842 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET; 843 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET; 844 } 845 else 846 { 847 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET; 848 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET; 849 } 850 return true; 851 852 case OPT_mfma4: 853 if (value) 854 { 855 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET; 856 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET; 857 } 858 else 859 { 860 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET; 861 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET; 862 } 863 return true; 864 865 case OPT_mxop: 866 if (value) 867 { 868 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET; 869 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET; 870 } 871 else 872 { 873 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET; 874 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET; 875 } 876 return true; 877 878 case OPT_mlwp: 879 if (value) 880 { 881 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET; 882 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET; 883 } 884 else 885 { 886 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET; 887 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET; 888 } 889 return true; 890 891 case OPT_mabm: 892 if (value) 893 { 894 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET; 895 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET; 896 } 897 else 898 { 899 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET; 900 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET; 901 } 902 return true; 903 904 case OPT_mbmi: 905 if (value) 906 { 907 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET; 908 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET; 909 } 910 else 911 { 912 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET; 913 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET; 914 } 915 return true; 916 917 case OPT_mbmi2: 918 if (value) 919 { 920 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET; 921 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET; 922 } 923 else 924 { 925 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET; 926 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET; 927 } 928 return true; 929 930 case OPT_mlzcnt: 931 if (value) 932 { 933 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET; 934 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET; 935 } 936 else 937 { 938 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET; 939 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET; 940 } 941 return true; 942 943 case OPT_mtbm: 944 if (value) 945 { 946 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET; 947 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET; 948 } 949 else 950 { 951 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET; 952 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET; 953 } 954 return true; 955 956 case OPT_mpopcnt: 957 if (value) 958 { 959 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET; 960 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET; 961 } 962 else 963 { 964 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET; 965 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET; 966 } 967 return true; 968 969 case OPT_msahf: 970 if (value) 971 { 972 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET; 973 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET; 974 } 975 else 976 { 977 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET; 978 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET; 979 } 980 return true; 981 982 case OPT_mcx16: 983 if (value) 984 { 985 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16_SET; 986 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_SET; 987 } 988 else 989 { 990 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CX16_UNSET; 991 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_UNSET; 992 } 993 return true; 994 995 case OPT_mmovbe: 996 if (value) 997 { 998 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE_SET; 999 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_SET; 1000 } 1001 else 1002 { 1003 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVBE_UNSET; 1004 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_UNSET; 1005 } 1006 return true; 1007 1008 case OPT_mcrc32: 1009 if (value) 1010 { 1011 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET; 1012 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET; 1013 } 1014 else 1015 { 1016 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET; 1017 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET; 1018 } 1019 return true; 1020 1021 case OPT_maes: 1022 if (value) 1023 { 1024 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET; 1025 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET; 1026 } 1027 else 1028 { 1029 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET; 1030 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET; 1031 } 1032 return true; 1033 1034 case OPT_msha: 1035 if (value) 1036 { 1037 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET; 1038 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET; 1039 } 1040 else 1041 { 1042 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET; 1043 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET; 1044 } 1045 return true; 1046 1047 case OPT_mpclmul: 1048 if (value) 1049 { 1050 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET; 1051 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET; 1052 } 1053 else 1054 { 1055 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET; 1056 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET; 1057 } 1058 return true; 1059 1060 case OPT_mfsgsbase: 1061 if (value) 1062 { 1063 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET; 1064 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET; 1065 } 1066 else 1067 { 1068 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET; 1069 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET; 1070 } 1071 return true; 1072 1073 case OPT_mrdrnd: 1074 if (value) 1075 { 1076 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET; 1077 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET; 1078 } 1079 else 1080 { 1081 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET; 1082 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET; 1083 } 1084 return true; 1085 1086 case OPT_mf16c: 1087 if (value) 1088 { 1089 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET; 1090 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET; 1091 } 1092 else 1093 { 1094 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET; 1095 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET; 1096 } 1097 return true; 1098 1099 case OPT_mfxsr: 1100 if (value) 1101 { 1102 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET; 1103 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET; 1104 } 1105 else 1106 { 1107 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET; 1108 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET; 1109 } 1110 return true; 1111 1112 case OPT_mxsave: 1113 if (value) 1114 { 1115 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET; 1116 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET; 1117 } 1118 else 1119 { 1120 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET; 1121 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET; 1122 } 1123 return true; 1124 1125 case OPT_mxsaveopt: 1126 if (value) 1127 { 1128 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET; 1129 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET; 1130 } 1131 else 1132 { 1133 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET; 1134 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET; 1135 } 1136 return true; 1137 1138 case OPT_mxsavec: 1139 if (value) 1140 { 1141 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET; 1142 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET; 1143 } 1144 else 1145 { 1146 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET; 1147 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET; 1148 } 1149 return true; 1150 1151 case OPT_mxsaves: 1152 if (value) 1153 { 1154 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET; 1155 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET; 1156 } 1157 else 1158 { 1159 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET; 1160 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET; 1161 } 1162 return true; 1163 1164 case OPT_mrdseed: 1165 if (value) 1166 { 1167 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET; 1168 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET; 1169 } 1170 else 1171 { 1172 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET; 1173 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET; 1174 } 1175 return true; 1176 1177 case OPT_mprfchw: 1178 if (value) 1179 { 1180 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET; 1181 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET; 1182 } 1183 else 1184 { 1185 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET; 1186 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET; 1187 } 1188 return true; 1189 1190 case OPT_madx: 1191 if (value) 1192 { 1193 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET; 1194 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET; 1195 } 1196 else 1197 { 1198 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET; 1199 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET; 1200 } 1201 return true; 1202 1203 case OPT_mprefetchwt1: 1204 if (value) 1205 { 1206 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET; 1207 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET; 1208 } 1209 else 1210 { 1211 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET; 1212 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET; 1213 } 1214 return true; 1215 1216 case OPT_mclflushopt: 1217 if (value) 1218 { 1219 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET; 1220 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET; 1221 } 1222 else 1223 { 1224 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET; 1225 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET; 1226 } 1227 return true; 1228 1229 case OPT_mclwb: 1230 if (value) 1231 { 1232 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET; 1233 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET; 1234 } 1235 else 1236 { 1237 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET; 1238 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET; 1239 } 1240 return true; 1241 1242 case OPT_mmwaitx: 1243 if (value) 1244 { 1245 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX_SET; 1246 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_SET; 1247 } 1248 else 1249 { 1250 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MWAITX_UNSET; 1251 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_UNSET; 1252 } 1253 return true; 1254 1255 case OPT_mclzero: 1256 if (value) 1257 { 1258 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO_SET; 1259 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_SET; 1260 } 1261 else 1262 { 1263 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLZERO_UNSET; 1264 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_UNSET; 1265 } 1266 return true; 1267 1268 case OPT_mpku: 1269 if (value) 1270 { 1271 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET; 1272 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET; 1273 } 1274 else 1275 { 1276 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET; 1277 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET; 1278 } 1279 return true; 1280 1281 1282 /* Comes from final.c -- no real reason to change it. */ 1283 #define MAX_CODE_ALIGN 16 1284 1285 case OPT_malign_loops_: 1286 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops"); 1287 if (value > MAX_CODE_ALIGN) 1288 error_at (loc, "-malign-loops=%d is not between 0 and %d", 1289 value, MAX_CODE_ALIGN); 1290 else 1291 opts->x_align_loops = 1 << value; 1292 return true; 1293 1294 case OPT_malign_jumps_: 1295 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps"); 1296 if (value > MAX_CODE_ALIGN) 1297 error_at (loc, "-malign-jumps=%d is not between 0 and %d", 1298 value, MAX_CODE_ALIGN); 1299 else 1300 opts->x_align_jumps = 1 << value; 1301 return true; 1302 1303 case OPT_malign_functions_: 1304 warning_at (loc, 0, 1305 "-malign-functions is obsolete, use -falign-functions"); 1306 if (value > MAX_CODE_ALIGN) 1307 error_at (loc, "-malign-functions=%d is not between 0 and %d", 1308 value, MAX_CODE_ALIGN); 1309 else 1310 opts->x_align_functions = 1 << value; 1311 return true; 1312 1313 case OPT_mbranch_cost_: 1314 if (value > 5) 1315 { 1316 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value); 1317 opts->x_ix86_branch_cost = 5; 1318 } 1319 return true; 1320 1321 default: 1322 return true; 1323 } 1324 } 1325 1326 static const struct default_options ix86_option_optimization_table[] = 1327 { 1328 /* Enable redundant extension instructions removal at -O2 and higher. */ 1329 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, 1330 /* Enable function splitting at -O2 and higher. */ 1331 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 }, 1332 /* The STC algorithm produces the smallest code at -Os, for x86. */ 1333 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL, 1334 REORDER_BLOCKS_ALGORITHM_STC }, 1335 /* Turn off -fschedule-insns by default. It tends to make the 1336 problem with not enough registers even worse. */ 1337 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 }, 1338 1339 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS 1340 SUBTARGET_OPTIMIZATION_OPTIONS, 1341 #endif 1342 { OPT_LEVELS_NONE, 0, NULL, 0 } 1343 }; 1344 1345 /* Implement TARGET_OPTION_INIT_STRUCT. */ 1346 1347 static void 1348 ix86_option_init_struct (struct gcc_options *opts) 1349 { 1350 if (TARGET_MACHO) 1351 /* The Darwin libraries never set errno, so we might as well 1352 avoid calling them when that's the only reason we would. */ 1353 opts->x_flag_errno_math = 0; 1354 1355 opts->x_flag_pcc_struct_return = 2; 1356 opts->x_flag_asynchronous_unwind_tables = 2; 1357 } 1358 1359 /* On the x86 -fsplit-stack and -fstack-protector both use the same 1360 field in the TCB, so they can not be used together. */ 1361 1362 static bool 1363 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED, 1364 struct gcc_options *opts ATTRIBUTE_UNUSED) 1365 { 1366 bool ret = true; 1367 1368 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET 1369 if (report) 1370 error ("%<-fsplit-stack%> currently only supported on GNU/Linux"); 1371 ret = false; 1372 #else 1373 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) 1374 { 1375 if (report) 1376 error ("%<-fsplit-stack%> requires " 1377 "assembler support for CFI directives"); 1378 ret = false; 1379 } 1380 #endif 1381 1382 return ret; 1383 } 1384 1385 /* Implement TARGET_EXCEPT_UNWIND_INFO. */ 1386 1387 static enum unwind_info_type 1388 i386_except_unwind_info (struct gcc_options *opts) 1389 { 1390 /* Honor the --enable-sjlj-exceptions configure switch. */ 1391 #ifdef CONFIG_SJLJ_EXCEPTIONS 1392 if (CONFIG_SJLJ_EXCEPTIONS) 1393 return UI_SJLJ; 1394 #endif 1395 1396 /* On windows 64, prefer SEH exceptions over anything else. */ 1397 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables) 1398 return UI_SEH; 1399 1400 if (DWARF2_UNWIND_INFO) 1401 return UI_DWARF2; 1402 1403 return UI_SJLJ; 1404 } 1405 1406 #undef TARGET_EXCEPT_UNWIND_INFO 1407 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info 1408 1409 #undef TARGET_DEFAULT_TARGET_FLAGS 1410 #define TARGET_DEFAULT_TARGET_FLAGS \ 1411 (TARGET_DEFAULT \ 1412 | TARGET_SUBTARGET_DEFAULT \ 1413 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT) 1414 1415 #undef TARGET_HANDLE_OPTION 1416 #define TARGET_HANDLE_OPTION ix86_handle_option 1417 1418 #undef TARGET_OPTION_OPTIMIZATION_TABLE 1419 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table 1420 #undef TARGET_OPTION_INIT_STRUCT 1421 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct 1422 1423 #undef TARGET_SUPPORTS_SPLIT_STACK 1424 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack 1425 1426 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; 1427