1 /* IA-32 common hooks. 2 Copyright (C) 1988-2018 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "diagnostic-core.h" 24 #include "tm.h" 25 #include "memmodel.h" 26 #include "tm_p.h" 27 #include "common/common-target.h" 28 #include "common/common-target-def.h" 29 #include "opts.h" 30 #include "flags.h" 31 32 /* Define a set of ISAs which are available when a given ISA is 33 enabled. MMX and SSE ISAs are handled separately. */ 34 35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX 36 #define OPTION_MASK_ISA_3DNOW_SET \ 37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET) 38 #define OPTION_MASK_ISA_3DNOW_A_SET \ 39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET) 40 41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE 42 #define OPTION_MASK_ISA_SSE2_SET \ 43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET) 44 #define OPTION_MASK_ISA_SSE3_SET \ 45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET) 46 #define OPTION_MASK_ISA_SSSE3_SET \ 47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET) 48 #define OPTION_MASK_ISA_SSE4_1_SET \ 49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET) 50 #define OPTION_MASK_ISA_SSE4_2_SET \ 51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET) 52 #define OPTION_MASK_ISA_AVX_SET \ 53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \ 54 | OPTION_MASK_ISA_XSAVE_SET) 55 #define OPTION_MASK_ISA_FMA_SET \ 56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) 57 #define OPTION_MASK_ISA_AVX2_SET \ 58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) 59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR 60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE 61 #define OPTION_MASK_ISA_XSAVEOPT_SET \ 62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE) 63 #define OPTION_MASK_ISA_AVX512F_SET \ 64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET) 65 #define OPTION_MASK_ISA_AVX512CD_SET \ 66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET) 67 #define OPTION_MASK_ISA_AVX512PF_SET \ 68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET) 69 #define OPTION_MASK_ISA_AVX512ER_SET \ 70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET) 71 #define OPTION_MASK_ISA_AVX512DQ_SET \ 72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET) 73 #define OPTION_MASK_ISA_AVX512BW_SET \ 74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET) 75 #define OPTION_MASK_ISA_AVX512VL_SET \ 76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET) 77 #define OPTION_MASK_ISA_AVX512IFMA_SET \ 78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) 79 #define OPTION_MASK_ISA_AVX512VBMI_SET \ 80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) 81 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS 82 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW 83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \ 84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) 85 #define OPTION_MASK_ISA_AVX512VNNI_SET \ 86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET) 87 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ 88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) 89 #define OPTION_MASK_ISA_AVX512BITALG_SET \ 90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) 91 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM 92 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW 93 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED 94 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX 95 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1 96 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT 97 #define OPTION_MASK_ISA_XSAVES_SET \ 98 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE) 99 #define OPTION_MASK_ISA_XSAVEC_SET \ 100 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE) 101 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB 102 103 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same 104 as -msse4.2. */ 105 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET 106 107 #define OPTION_MASK_ISA_SSE4A_SET \ 108 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET) 109 #define OPTION_MASK_ISA_FMA4_SET \ 110 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \ 111 | OPTION_MASK_ISA_AVX_SET) 112 #define OPTION_MASK_ISA_XOP_SET \ 113 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET) 114 #define OPTION_MASK_ISA_LWP_SET \ 115 OPTION_MASK_ISA_LWP 116 117 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */ 118 #define OPTION_MASK_ISA_AES_SET \ 119 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET) 120 #define OPTION_MASK_ISA_SHA_SET \ 121 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET) 122 #define OPTION_MASK_ISA_PCLMUL_SET \ 123 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) 124 125 #define OPTION_MASK_ISA_ABM_SET \ 126 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) 127 128 #define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG 129 #define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD 130 #define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX 131 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI 132 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 133 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT 134 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM 135 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT 136 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16 137 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF 138 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE 139 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 140 141 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE 142 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND 143 #define OPTION_MASK_ISA_F16C_SET \ 144 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) 145 #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX 146 #define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO 147 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU 148 #define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID 149 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI 150 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK 151 #define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES 152 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ 153 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI 154 #define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B 155 156 /* Define a set of ISAs which aren't available when a given ISA is 157 disabled. MMX and SSE ISAs are handled separately. */ 158 159 #define OPTION_MASK_ISA_MMX_UNSET \ 160 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET) 161 #define OPTION_MASK_ISA_3DNOW_UNSET \ 162 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET) 163 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A 164 165 #define OPTION_MASK_ISA_SSE_UNSET \ 166 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET) 167 #define OPTION_MASK_ISA_SSE2_UNSET \ 168 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET) 169 #define OPTION_MASK_ISA_SSE3_UNSET \ 170 (OPTION_MASK_ISA_SSE3 \ 171 | OPTION_MASK_ISA_SSSE3_UNSET \ 172 | OPTION_MASK_ISA_SSE4A_UNSET ) 173 #define OPTION_MASK_ISA_SSSE3_UNSET \ 174 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET) 175 #define OPTION_MASK_ISA_SSE4_1_UNSET \ 176 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET) 177 #define OPTION_MASK_ISA_SSE4_2_UNSET \ 178 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) 179 #define OPTION_MASK_ISA_AVX_UNSET \ 180 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ 181 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ 182 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET) 183 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA 184 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR 185 #define OPTION_MASK_ISA_XSAVE_UNSET \ 186 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET) 187 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT 188 #define OPTION_MASK_ISA_AVX2_UNSET \ 189 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET) 190 #define OPTION_MASK_ISA_AVX512F_UNSET \ 191 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ 192 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ 193 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \ 194 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512VBMI2_UNSET \ 195 | OPTION_MASK_ISA_AVX512VNNI_UNSET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \ 196 | OPTION_MASK_ISA_AVX512BITALG_UNSET) 197 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD 198 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF 199 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER 200 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ 201 #define OPTION_MASK_ISA_AVX512BW_UNSET \ 202 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET) 203 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL 204 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA 205 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI 206 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS 207 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW 208 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 209 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI 210 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ 211 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG 212 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM 213 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW 214 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED 215 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX 216 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1 217 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT 218 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC 219 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES 220 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB 221 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX 222 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO 223 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU 224 #define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID 225 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI 226 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK 227 #define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES 228 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ 229 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI 230 #define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B 231 232 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same 233 as -mno-sse4.1. */ 234 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET 235 236 #define OPTION_MASK_ISA_SSE4A_UNSET \ 237 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET) 238 239 #define OPTION_MASK_ISA_FMA4_UNSET \ 240 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET) 241 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP 242 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP 243 244 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES 245 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA 246 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL 247 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM 248 #define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG 249 #define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD 250 #define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX 251 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI 252 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 253 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT 254 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM 255 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT 256 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16 257 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF 258 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE 259 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 260 261 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE 262 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND 263 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C 264 265 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ 266 (OPTION_MASK_ISA_MMX_UNSET \ 267 | OPTION_MASK_ISA_SSE_UNSET) 268 269 #define OPTION_MASK_ISA2_AVX512F_UNSET \ 270 (OPTION_MASK_ISA_AVX5124FMAPS_UNSET | OPTION_MASK_ISA_AVX5124VNNIW_UNSET) 271 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ 272 (OPTION_MASK_ISA2_AVX512F_UNSET | OPTION_MASK_ISA_MPX) 273 274 /* Implement TARGET_HANDLE_OPTION. */ 275 276 bool 277 ix86_handle_option (struct gcc_options *opts, 278 struct gcc_options *opts_set ATTRIBUTE_UNUSED, 279 const struct cl_decoded_option *decoded, 280 location_t loc) 281 { 282 size_t code = decoded->opt_index; 283 int value = decoded->value; 284 285 switch (code) 286 { 287 case OPT_mgeneral_regs_only: 288 if (value) 289 { 290 /* Disable MPX, MMX, SSE and x87 instructions if only 291 general registers are allowed. */ 292 opts->x_ix86_isa_flags 293 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; 294 opts->x_ix86_isa_flags2 295 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; 296 opts->x_ix86_isa_flags_explicit 297 |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; 298 opts->x_ix86_isa_flags2_explicit 299 |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; 300 301 opts->x_target_flags &= ~MASK_80387; 302 } 303 else 304 gcc_unreachable (); 305 return true; 306 307 case OPT_mmmx: 308 if (value) 309 { 310 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET; 311 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET; 312 } 313 else 314 { 315 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET; 316 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET; 317 } 318 return true; 319 320 case OPT_m3dnow: 321 if (value) 322 { 323 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET; 324 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET; 325 } 326 else 327 { 328 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET; 329 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET; 330 } 331 return true; 332 333 case OPT_m3dnowa: 334 if (value) 335 { 336 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET; 337 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET; 338 } 339 else 340 { 341 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET; 342 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET; 343 } 344 return true; 345 346 case OPT_msse: 347 if (value) 348 { 349 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET; 350 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET; 351 } 352 else 353 { 354 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET; 355 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET; 356 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 357 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 358 } 359 return true; 360 361 case OPT_msse2: 362 if (value) 363 { 364 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET; 365 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET; 366 } 367 else 368 { 369 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET; 370 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET; 371 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 372 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 373 } 374 return true; 375 376 case OPT_msse3: 377 if (value) 378 { 379 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET; 380 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET; 381 } 382 else 383 { 384 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET; 385 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET; 386 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 387 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 388 } 389 return true; 390 391 case OPT_mssse3: 392 if (value) 393 { 394 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET; 395 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET; 396 } 397 else 398 { 399 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET; 400 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET; 401 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 402 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 403 } 404 return true; 405 406 case OPT_msse4_1: 407 if (value) 408 { 409 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET; 410 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET; 411 } 412 else 413 { 414 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET; 415 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET; 416 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 417 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 418 } 419 return true; 420 421 case OPT_msse4_2: 422 if (value) 423 { 424 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET; 425 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET; 426 } 427 else 428 { 429 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET; 430 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET; 431 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 432 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 433 } 434 return true; 435 436 case OPT_mavx: 437 if (value) 438 { 439 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; 440 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; 441 } 442 else 443 { 444 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET; 445 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET; 446 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 447 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 448 } 449 return true; 450 451 case OPT_mavx2: 452 if (value) 453 { 454 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; 455 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; 456 } 457 else 458 { 459 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET; 460 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET; 461 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 462 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 463 } 464 return true; 465 466 case OPT_mavx512f: 467 if (value) 468 { 469 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; 470 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; 471 } 472 else 473 { 474 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET; 475 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET; 476 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 477 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 478 } 479 return true; 480 481 case OPT_mavx512cd: 482 if (value) 483 { 484 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET; 485 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET; 486 } 487 else 488 { 489 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET; 490 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET; 491 } 492 return true; 493 494 case OPT_mavx512pf: 495 if (value) 496 { 497 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET; 498 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET; 499 } 500 else 501 { 502 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET; 503 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET; 504 } 505 return true; 506 507 case OPT_mavx512er: 508 if (value) 509 { 510 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET; 511 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET; 512 } 513 else 514 { 515 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET; 516 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET; 517 } 518 return true; 519 520 case OPT_mrdpid: 521 if (value) 522 { 523 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET; 524 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET; 525 } 526 else 527 { 528 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET; 529 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET; 530 } 531 return true; 532 533 case OPT_mgfni: 534 if (value) 535 { 536 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET; 537 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET; 538 } 539 else 540 { 541 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET; 542 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET; 543 } 544 return true; 545 546 case OPT_mshstk: 547 if (value) 548 { 549 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET; 550 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET; 551 } 552 else 553 { 554 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET; 555 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET; 556 } 557 return true; 558 559 case OPT_mvaes: 560 if (value) 561 { 562 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET; 563 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET; 564 } 565 else 566 { 567 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET; 568 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET; 569 } 570 return true; 571 572 case OPT_mvpclmulqdq: 573 if (value) 574 { 575 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET; 576 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET; 577 } 578 else 579 { 580 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET; 581 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET; 582 } 583 return true; 584 585 case OPT_mmovdiri: 586 if (value) 587 { 588 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET; 589 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET; 590 } 591 else 592 { 593 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET; 594 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET; 595 } 596 return true; 597 598 case OPT_mmovdir64b: 599 if (value) 600 { 601 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B_SET; 602 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_SET; 603 } 604 else 605 { 606 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVDIR64B_UNSET; 607 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_UNSET; 608 } 609 return true; 610 611 case OPT_mavx5124fmaps: 612 if (value) 613 { 614 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET; 615 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET; 616 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; 617 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; 618 } 619 else 620 { 621 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET; 622 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET; 623 } 624 return true; 625 626 case OPT_mavx5124vnniw: 627 if (value) 628 { 629 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET; 630 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET; 631 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; 632 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; 633 } 634 else 635 { 636 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET; 637 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET; 638 } 639 return true; 640 641 case OPT_mavx512vbmi2: 642 if (value) 643 { 644 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET; 645 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET; 646 } 647 else 648 { 649 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET; 650 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET; 651 } 652 return true; 653 654 case OPT_mavx512vnni: 655 if (value) 656 { 657 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET; 658 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET; 659 } 660 else 661 { 662 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET; 663 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET; 664 } 665 return true; 666 667 case OPT_mavx512vpopcntdq: 668 if (value) 669 { 670 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; 671 opts->x_ix86_isa_flags_explicit 672 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; 673 } 674 else 675 { 676 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; 677 opts->x_ix86_isa_flags_explicit 678 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; 679 } 680 return true; 681 682 case OPT_mavx512bitalg: 683 if (value) 684 { 685 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET; 686 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET; 687 } 688 else 689 { 690 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET; 691 opts->x_ix86_isa_flags_explicit 692 |= OPTION_MASK_ISA_AVX512BITALG_UNSET; 693 } 694 return true; 695 696 case OPT_msgx: 697 if (value) 698 { 699 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET; 700 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET; 701 } 702 else 703 { 704 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET; 705 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET; 706 } 707 return true; 708 709 case OPT_mpconfig: 710 if (value) 711 { 712 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG_SET; 713 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_SET; 714 } 715 else 716 { 717 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PCONFIG_UNSET; 718 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_UNSET; 719 } 720 return true; 721 722 case OPT_mwbnoinvd: 723 if (value) 724 { 725 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD_SET; 726 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_SET; 727 } 728 else 729 { 730 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WBNOINVD_UNSET; 731 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_UNSET; 732 } 733 return true; 734 735 case OPT_mavx512dq: 736 if (value) 737 { 738 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET; 739 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET; 740 } 741 else 742 { 743 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET; 744 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET; 745 } 746 return true; 747 748 case OPT_mavx512bw: 749 if (value) 750 { 751 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET; 752 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET; 753 } 754 else 755 { 756 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET; 757 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET; 758 } 759 return true; 760 761 case OPT_mavx512vl: 762 if (value) 763 { 764 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET; 765 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET; 766 } 767 else 768 { 769 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET; 770 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET; 771 } 772 return true; 773 774 case OPT_mavx512ifma: 775 if (value) 776 { 777 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET; 778 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET; 779 } 780 else 781 { 782 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET; 783 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET; 784 } 785 return true; 786 787 case OPT_mavx512vbmi: 788 if (value) 789 { 790 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET; 791 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET; 792 } 793 else 794 { 795 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET; 796 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET; 797 } 798 return true; 799 800 case OPT_mfma: 801 if (value) 802 { 803 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET; 804 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET; 805 } 806 else 807 { 808 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET; 809 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET; 810 } 811 return true; 812 813 case OPT_mrtm: 814 if (value) 815 { 816 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET; 817 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET; 818 } 819 else 820 { 821 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET; 822 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET; 823 } 824 return true; 825 826 case OPT_msse4: 827 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET; 828 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET; 829 return true; 830 831 case OPT_mno_sse4: 832 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET; 833 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET; 834 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; 835 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; 836 return true; 837 838 case OPT_msse4a: 839 if (value) 840 { 841 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET; 842 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET; 843 } 844 else 845 { 846 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET; 847 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET; 848 } 849 return true; 850 851 case OPT_mfma4: 852 if (value) 853 { 854 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET; 855 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET; 856 } 857 else 858 { 859 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET; 860 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET; 861 } 862 return true; 863 864 case OPT_mxop: 865 if (value) 866 { 867 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET; 868 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET; 869 } 870 else 871 { 872 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET; 873 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET; 874 } 875 return true; 876 877 case OPT_mlwp: 878 if (value) 879 { 880 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET; 881 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET; 882 } 883 else 884 { 885 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET; 886 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET; 887 } 888 return true; 889 890 case OPT_mabm: 891 if (value) 892 { 893 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET; 894 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET; 895 } 896 else 897 { 898 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET; 899 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET; 900 } 901 return true; 902 903 case OPT_mbmi: 904 if (value) 905 { 906 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET; 907 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET; 908 } 909 else 910 { 911 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET; 912 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET; 913 } 914 return true; 915 916 case OPT_mbmi2: 917 if (value) 918 { 919 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET; 920 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET; 921 } 922 else 923 { 924 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET; 925 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET; 926 } 927 return true; 928 929 case OPT_mlzcnt: 930 if (value) 931 { 932 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET; 933 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET; 934 } 935 else 936 { 937 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET; 938 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET; 939 } 940 return true; 941 942 case OPT_mtbm: 943 if (value) 944 { 945 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET; 946 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET; 947 } 948 else 949 { 950 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET; 951 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET; 952 } 953 return true; 954 955 case OPT_mpopcnt: 956 if (value) 957 { 958 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET; 959 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET; 960 } 961 else 962 { 963 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET; 964 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET; 965 } 966 return true; 967 968 case OPT_msahf: 969 if (value) 970 { 971 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET; 972 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET; 973 } 974 else 975 { 976 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET; 977 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET; 978 } 979 return true; 980 981 case OPT_mcx16: 982 if (value) 983 { 984 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16_SET; 985 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_SET; 986 } 987 else 988 { 989 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CX16_UNSET; 990 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_UNSET; 991 } 992 return true; 993 994 case OPT_mmovbe: 995 if (value) 996 { 997 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE_SET; 998 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_SET; 999 } 1000 else 1001 { 1002 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVBE_UNSET; 1003 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_UNSET; 1004 } 1005 return true; 1006 1007 case OPT_mcrc32: 1008 if (value) 1009 { 1010 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET; 1011 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET; 1012 } 1013 else 1014 { 1015 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET; 1016 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET; 1017 } 1018 return true; 1019 1020 case OPT_maes: 1021 if (value) 1022 { 1023 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET; 1024 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET; 1025 } 1026 else 1027 { 1028 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET; 1029 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET; 1030 } 1031 return true; 1032 1033 case OPT_msha: 1034 if (value) 1035 { 1036 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET; 1037 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET; 1038 } 1039 else 1040 { 1041 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET; 1042 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET; 1043 } 1044 return true; 1045 1046 case OPT_mpclmul: 1047 if (value) 1048 { 1049 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET; 1050 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET; 1051 } 1052 else 1053 { 1054 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET; 1055 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET; 1056 } 1057 return true; 1058 1059 case OPT_mfsgsbase: 1060 if (value) 1061 { 1062 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET; 1063 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET; 1064 } 1065 else 1066 { 1067 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET; 1068 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET; 1069 } 1070 return true; 1071 1072 case OPT_mrdrnd: 1073 if (value) 1074 { 1075 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET; 1076 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET; 1077 } 1078 else 1079 { 1080 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET; 1081 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET; 1082 } 1083 return true; 1084 1085 case OPT_mf16c: 1086 if (value) 1087 { 1088 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET; 1089 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET; 1090 } 1091 else 1092 { 1093 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET; 1094 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET; 1095 } 1096 return true; 1097 1098 case OPT_mfxsr: 1099 if (value) 1100 { 1101 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET; 1102 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET; 1103 } 1104 else 1105 { 1106 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET; 1107 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET; 1108 } 1109 return true; 1110 1111 case OPT_mxsave: 1112 if (value) 1113 { 1114 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET; 1115 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET; 1116 } 1117 else 1118 { 1119 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET; 1120 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET; 1121 } 1122 return true; 1123 1124 case OPT_mxsaveopt: 1125 if (value) 1126 { 1127 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET; 1128 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET; 1129 } 1130 else 1131 { 1132 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET; 1133 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET; 1134 } 1135 return true; 1136 1137 case OPT_mxsavec: 1138 if (value) 1139 { 1140 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET; 1141 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET; 1142 } 1143 else 1144 { 1145 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET; 1146 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET; 1147 } 1148 return true; 1149 1150 case OPT_mxsaves: 1151 if (value) 1152 { 1153 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET; 1154 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET; 1155 } 1156 else 1157 { 1158 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET; 1159 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET; 1160 } 1161 return true; 1162 1163 case OPT_mrdseed: 1164 if (value) 1165 { 1166 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET; 1167 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET; 1168 } 1169 else 1170 { 1171 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET; 1172 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET; 1173 } 1174 return true; 1175 1176 case OPT_mprfchw: 1177 if (value) 1178 { 1179 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET; 1180 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET; 1181 } 1182 else 1183 { 1184 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET; 1185 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET; 1186 } 1187 return true; 1188 1189 case OPT_madx: 1190 if (value) 1191 { 1192 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET; 1193 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET; 1194 } 1195 else 1196 { 1197 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET; 1198 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET; 1199 } 1200 return true; 1201 1202 case OPT_mprefetchwt1: 1203 if (value) 1204 { 1205 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET; 1206 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET; 1207 } 1208 else 1209 { 1210 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET; 1211 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET; 1212 } 1213 return true; 1214 1215 case OPT_mclflushopt: 1216 if (value) 1217 { 1218 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET; 1219 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET; 1220 } 1221 else 1222 { 1223 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET; 1224 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET; 1225 } 1226 return true; 1227 1228 case OPT_mclwb: 1229 if (value) 1230 { 1231 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET; 1232 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET; 1233 } 1234 else 1235 { 1236 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET; 1237 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET; 1238 } 1239 return true; 1240 1241 case OPT_mmwaitx: 1242 if (value) 1243 { 1244 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX_SET; 1245 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_SET; 1246 } 1247 else 1248 { 1249 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MWAITX_UNSET; 1250 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_UNSET; 1251 } 1252 return true; 1253 1254 case OPT_mclzero: 1255 if (value) 1256 { 1257 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO_SET; 1258 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_SET; 1259 } 1260 else 1261 { 1262 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLZERO_UNSET; 1263 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_UNSET; 1264 } 1265 return true; 1266 1267 case OPT_mpku: 1268 if (value) 1269 { 1270 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET; 1271 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET; 1272 } 1273 else 1274 { 1275 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET; 1276 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET; 1277 } 1278 return true; 1279 1280 1281 /* Comes from final.c -- no real reason to change it. */ 1282 #define MAX_CODE_ALIGN 16 1283 1284 case OPT_malign_loops_: 1285 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops"); 1286 if (value > MAX_CODE_ALIGN) 1287 error_at (loc, "-malign-loops=%d is not between 0 and %d", 1288 value, MAX_CODE_ALIGN); 1289 else 1290 opts->x_align_loops = 1 << value; 1291 return true; 1292 1293 case OPT_malign_jumps_: 1294 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps"); 1295 if (value > MAX_CODE_ALIGN) 1296 error_at (loc, "-malign-jumps=%d is not between 0 and %d", 1297 value, MAX_CODE_ALIGN); 1298 else 1299 opts->x_align_jumps = 1 << value; 1300 return true; 1301 1302 case OPT_malign_functions_: 1303 warning_at (loc, 0, 1304 "-malign-functions is obsolete, use -falign-functions"); 1305 if (value > MAX_CODE_ALIGN) 1306 error_at (loc, "-malign-functions=%d is not between 0 and %d", 1307 value, MAX_CODE_ALIGN); 1308 else 1309 opts->x_align_functions = 1 << value; 1310 return true; 1311 1312 case OPT_mbranch_cost_: 1313 if (value > 5) 1314 { 1315 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value); 1316 opts->x_ix86_branch_cost = 5; 1317 } 1318 return true; 1319 1320 default: 1321 return true; 1322 } 1323 } 1324 1325 static const struct default_options ix86_option_optimization_table[] = 1326 { 1327 /* Enable redundant extension instructions removal at -O2 and higher. */ 1328 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 }, 1329 /* Enable function splitting at -O2 and higher. */ 1330 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 }, 1331 /* The STC algorithm produces the smallest code at -Os, for x86. */ 1332 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL, 1333 REORDER_BLOCKS_ALGORITHM_STC }, 1334 /* Turn off -fschedule-insns by default. It tends to make the 1335 problem with not enough registers even worse. */ 1336 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 }, 1337 1338 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS 1339 SUBTARGET_OPTIMIZATION_OPTIONS, 1340 #endif 1341 { OPT_LEVELS_NONE, 0, NULL, 0 } 1342 }; 1343 1344 /* Implement TARGET_OPTION_INIT_STRUCT. */ 1345 1346 static void 1347 ix86_option_init_struct (struct gcc_options *opts) 1348 { 1349 if (TARGET_MACHO) 1350 /* The Darwin libraries never set errno, so we might as well 1351 avoid calling them when that's the only reason we would. */ 1352 opts->x_flag_errno_math = 0; 1353 1354 opts->x_flag_pcc_struct_return = 2; 1355 opts->x_flag_asynchronous_unwind_tables = 2; 1356 } 1357 1358 /* On the x86 -fsplit-stack and -fstack-protector both use the same 1359 field in the TCB, so they can not be used together. */ 1360 1361 static bool 1362 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED, 1363 struct gcc_options *opts ATTRIBUTE_UNUSED) 1364 { 1365 bool ret = true; 1366 1367 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET 1368 if (report) 1369 error ("%<-fsplit-stack%> currently only supported on GNU/Linux"); 1370 ret = false; 1371 #else 1372 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) 1373 { 1374 if (report) 1375 error ("%<-fsplit-stack%> requires " 1376 "assembler support for CFI directives"); 1377 ret = false; 1378 } 1379 #endif 1380 1381 return ret; 1382 } 1383 1384 /* Implement TARGET_EXCEPT_UNWIND_INFO. */ 1385 1386 static enum unwind_info_type 1387 i386_except_unwind_info (struct gcc_options *opts) 1388 { 1389 /* Honor the --enable-sjlj-exceptions configure switch. */ 1390 #ifdef CONFIG_SJLJ_EXCEPTIONS 1391 if (CONFIG_SJLJ_EXCEPTIONS) 1392 return UI_SJLJ; 1393 #endif 1394 1395 /* On windows 64, prefer SEH exceptions over anything else. */ 1396 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables) 1397 return UI_SEH; 1398 1399 if (DWARF2_UNWIND_INFO) 1400 return UI_DWARF2; 1401 1402 return UI_SJLJ; 1403 } 1404 1405 #undef TARGET_EXCEPT_UNWIND_INFO 1406 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info 1407 1408 #undef TARGET_DEFAULT_TARGET_FLAGS 1409 #define TARGET_DEFAULT_TARGET_FLAGS \ 1410 (TARGET_DEFAULT \ 1411 | TARGET_SUBTARGET_DEFAULT \ 1412 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT) 1413 1414 #undef TARGET_HANDLE_OPTION 1415 #define TARGET_HANDLE_OPTION ix86_handle_option 1416 1417 #undef TARGET_OPTION_OPTIMIZATION_TABLE 1418 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table 1419 #undef TARGET_OPTION_INIT_STRUCT 1420 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct 1421 1422 #undef TARGET_SUPPORTS_SPLIT_STACK 1423 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack 1424 1425 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; 1426