1*38fd1498Szrj;; Atom Scheduling 2*38fd1498Szrj;; Copyright (C) 2009-2018 Free Software Foundation, Inc. 3*38fd1498Szrj;; 4*38fd1498Szrj;; This file is part of GCC. 5*38fd1498Szrj;; 6*38fd1498Szrj;; GCC is free software; you can redistribute it and/or modify 7*38fd1498Szrj;; it under the terms of the GNU General Public License as published by 8*38fd1498Szrj;; the Free Software Foundation; either version 3, or (at your option) 9*38fd1498Szrj;; any later version. 10*38fd1498Szrj;; 11*38fd1498Szrj;; GCC is distributed in the hope that it will be useful, 12*38fd1498Szrj;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13*38fd1498Szrj;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*38fd1498Szrj;; GNU General Public License for more details. 15*38fd1498Szrj;; 16*38fd1498Szrj;; You should have received a copy of the GNU General Public License 17*38fd1498Szrj;; along with GCC; see the file COPYING3. If not see 18*38fd1498Szrj;; <http://www.gnu.org/licenses/>. 19*38fd1498Szrj;; 20*38fd1498Szrj;; Atom is an in-order core with two integer pipelines. 21*38fd1498Szrj 22*38fd1498Szrj 23*38fd1498Szrj(define_attr "atom_unit" "sishuf,simul,jeu,complex,other" 24*38fd1498Szrj (const_string "other")) 25*38fd1498Szrj 26*38fd1498Szrj(define_attr "atom_sse_attr" "rcp,movdup,lfence,fence,prefetch,sqrt,mxcsr,other" 27*38fd1498Szrj (const_string "other")) 28*38fd1498Szrj 29*38fd1498Szrj(define_automaton "atom") 30*38fd1498Szrj 31*38fd1498Szrj;; Atom has two ports: port 0 and port 1 connecting to all execution units 32*38fd1498Szrj(define_cpu_unit "atom-port-0,atom-port-1" "atom") 33*38fd1498Szrj 34*38fd1498Szrj;; EU: Execution Unit 35*38fd1498Szrj;; Atom EUs are connected by port 0 or port 1. 36*38fd1498Szrj 37*38fd1498Szrj(define_cpu_unit "atom-eu-0, atom-eu-1, 38*38fd1498Szrj atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4" 39*38fd1498Szrj "atom") 40*38fd1498Szrj 41*38fd1498Szrj;; Some EUs have duplicated copied and can be accessed via either 42*38fd1498Szrj;; port 0 or port 1 43*38fd1498Szrj;; (define_reservation "atom-port-either" "(atom-port-0 | atom-port-1)") 44*38fd1498Szrj 45*38fd1498Szrj;;; Some instructions is dual-pipe execution, need both ports 46*38fd1498Szrj;;; Complex multi-op macro-instructoins need both ports and all EUs 47*38fd1498Szrj(define_reservation "atom-port-dual" "(atom-port-0 + atom-port-1)") 48*38fd1498Szrj(define_reservation "atom-all-eu" "(atom-eu-0 + atom-eu-1 + 49*38fd1498Szrj atom-imul-1 + atom-imul-2 + atom-imul-3 + 50*38fd1498Szrj atom-imul-4)") 51*38fd1498Szrj 52*38fd1498Szrj;;; Most of simple instructions have 1 cycle latency. Some of them 53*38fd1498Szrj;;; issue in port 0, some in port 0 and some in either port. 54*38fd1498Szrj(define_reservation "atom-simple-0" "(atom-port-0 + atom-eu-0)") 55*38fd1498Szrj(define_reservation "atom-simple-1" "(atom-port-1 + atom-eu-1)") 56*38fd1498Szrj(define_reservation "atom-simple-either" "(atom-simple-0 | atom-simple-1)") 57*38fd1498Szrj 58*38fd1498Szrj;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput 59*38fd1498Szrj(define_reservation "atom-eu-0-3-1" "(atom-port-0 + atom-eu-0, nothing*2)") 60*38fd1498Szrj 61*38fd1498Szrj;;; fmul insn can have 4 or 5 cycles latency 62*38fd1498Szrj(define_reservation "atom-fmul-5c" "(atom-port-0 + atom-eu-0), nothing*4") 63*38fd1498Szrj(define_reservation "atom-fmul-4c" "(atom-port-0 + atom-eu-0), nothing*3") 64*38fd1498Szrj 65*38fd1498Szrj;;; fadd can has 5 cycles latency depends on instruction forms 66*38fd1498Szrj(define_reservation "atom-fadd-5c" "(atom-port-1 + atom-eu-1), nothing*5") 67*38fd1498Szrj 68*38fd1498Szrj;;; imul insn has 5 cycles latency 69*38fd1498Szrj(define_reservation "atom-imul-32" 70*38fd1498Szrj "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4, 71*38fd1498Szrj atom-port-0") 72*38fd1498Szrj;;; imul instruction excludes other non-FP instructions. 73*38fd1498Szrj(exclusion_set "atom-eu-0, atom-eu-1" 74*38fd1498Szrj "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4") 75*38fd1498Szrj 76*38fd1498Szrj;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on 77*38fd1498Szrj;;; instruction forms 78*38fd1498Szrj(define_reservation "atom-dual-1c" "(atom-port-dual + atom-eu-0 + atom-eu-1)") 79*38fd1498Szrj(define_reservation "atom-dual-2c" 80*38fd1498Szrj "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing)") 81*38fd1498Szrj(define_reservation "atom-dual-5c" 82*38fd1498Szrj "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing*4)") 83*38fd1498Szrj 84*38fd1498Szrj;;; Complex macro-instruction has variants of latency, and uses both ports. 85*38fd1498Szrj(define_reservation "atom-complex" "(atom-port-dual + atom-all-eu)") 86*38fd1498Szrj 87*38fd1498Szrj(define_insn_reservation "atom_other" 9 88*38fd1498Szrj (and (eq_attr "cpu" "atom") 89*38fd1498Szrj (and (eq_attr "type" "other") 90*38fd1498Szrj (eq_attr "atom_unit" "!jeu"))) 91*38fd1498Szrj "atom-complex, atom-all-eu*8") 92*38fd1498Szrj 93*38fd1498Szrj;; return has type "other" with atom_unit "jeu" 94*38fd1498Szrj(define_insn_reservation "atom_other_2" 1 95*38fd1498Szrj (and (eq_attr "cpu" "atom") 96*38fd1498Szrj (and (eq_attr "type" "other") 97*38fd1498Szrj (eq_attr "atom_unit" "jeu"))) 98*38fd1498Szrj "atom-dual-1c") 99*38fd1498Szrj 100*38fd1498Szrj(define_insn_reservation "atom_multi" 9 101*38fd1498Szrj (and (eq_attr "cpu" "atom") 102*38fd1498Szrj (eq_attr "type" "multi")) 103*38fd1498Szrj "atom-complex, atom-all-eu*8") 104*38fd1498Szrj 105*38fd1498Szrj;; Normal alu insns without carry 106*38fd1498Szrj(define_insn_reservation "atom_alu" 1 107*38fd1498Szrj (and (eq_attr "cpu" "atom") 108*38fd1498Szrj (and (eq_attr "type" "alu") 109*38fd1498Szrj (and (eq_attr "memory" "none") 110*38fd1498Szrj (eq_attr "use_carry" "0")))) 111*38fd1498Szrj "atom-simple-either") 112*38fd1498Szrj 113*38fd1498Szrj;; Normal alu insns without carry 114*38fd1498Szrj(define_insn_reservation "atom_alu_mem" 1 115*38fd1498Szrj (and (eq_attr "cpu" "atom") 116*38fd1498Szrj (and (eq_attr "type" "alu") 117*38fd1498Szrj (and (eq_attr "memory" "!none") 118*38fd1498Szrj (eq_attr "use_carry" "0")))) 119*38fd1498Szrj "atom-simple-either") 120*38fd1498Szrj 121*38fd1498Szrj;; Alu insn consuming CF, such as add/sbb 122*38fd1498Szrj(define_insn_reservation "atom_alu_carry" 1 123*38fd1498Szrj (and (eq_attr "cpu" "atom") 124*38fd1498Szrj (and (eq_attr "type" "alu") 125*38fd1498Szrj (and (eq_attr "memory" "none") 126*38fd1498Szrj (eq_attr "use_carry" "1")))) 127*38fd1498Szrj "atom-simple-either") 128*38fd1498Szrj 129*38fd1498Szrj;; Alu insn consuming CF, such as add/sbb 130*38fd1498Szrj(define_insn_reservation "atom_alu_carry_mem" 1 131*38fd1498Szrj (and (eq_attr "cpu" "atom") 132*38fd1498Szrj (and (eq_attr "type" "alu") 133*38fd1498Szrj (and (eq_attr "memory" "!none") 134*38fd1498Szrj (eq_attr "use_carry" "1")))) 135*38fd1498Szrj "atom-simple-either") 136*38fd1498Szrj 137*38fd1498Szrj(define_insn_reservation "atom_alu1" 1 138*38fd1498Szrj (and (eq_attr "cpu" "atom") 139*38fd1498Szrj (and (eq_attr "type" "alu1") 140*38fd1498Szrj (eq_attr "memory" "none"))) 141*38fd1498Szrj "atom-simple-either") 142*38fd1498Szrj 143*38fd1498Szrj(define_insn_reservation "atom_alu1_mem" 1 144*38fd1498Szrj (and (eq_attr "cpu" "atom") 145*38fd1498Szrj (and (eq_attr "type" "alu1") 146*38fd1498Szrj (eq_attr "memory" "!none"))) 147*38fd1498Szrj "atom-simple-either") 148*38fd1498Szrj 149*38fd1498Szrj(define_insn_reservation "atom_negnot" 1 150*38fd1498Szrj (and (eq_attr "cpu" "atom") 151*38fd1498Szrj (and (eq_attr "type" "negnot") 152*38fd1498Szrj (eq_attr "memory" "none"))) 153*38fd1498Szrj "atom-simple-either") 154*38fd1498Szrj 155*38fd1498Szrj(define_insn_reservation "atom_negnot_mem" 1 156*38fd1498Szrj (and (eq_attr "cpu" "atom") 157*38fd1498Szrj (and (eq_attr "type" "negnot") 158*38fd1498Szrj (eq_attr "memory" "!none"))) 159*38fd1498Szrj "atom-simple-either") 160*38fd1498Szrj 161*38fd1498Szrj(define_insn_reservation "atom_imov" 1 162*38fd1498Szrj (and (eq_attr "cpu" "atom") 163*38fd1498Szrj (and (eq_attr "type" "imov") 164*38fd1498Szrj (eq_attr "memory" "none"))) 165*38fd1498Szrj "atom-simple-either") 166*38fd1498Szrj 167*38fd1498Szrj(define_insn_reservation "atom_imov_mem" 1 168*38fd1498Szrj (and (eq_attr "cpu" "atom") 169*38fd1498Szrj (and (eq_attr "type" "imov") 170*38fd1498Szrj (eq_attr "memory" "!none"))) 171*38fd1498Szrj "atom-simple-either") 172*38fd1498Szrj 173*38fd1498Szrj;; 16<-16, 32<-32 174*38fd1498Szrj(define_insn_reservation "atom_imovx" 1 175*38fd1498Szrj (and (eq_attr "cpu" "atom") 176*38fd1498Szrj (and (eq_attr "type" "imovx") 177*38fd1498Szrj (and (eq_attr "memory" "none") 178*38fd1498Szrj (ior (and (match_operand:HI 0 "register_operand") 179*38fd1498Szrj (match_operand:HI 1 "general_operand")) 180*38fd1498Szrj (and (match_operand:SI 0 "register_operand") 181*38fd1498Szrj (match_operand:SI 1 "general_operand")))))) 182*38fd1498Szrj "atom-simple-either") 183*38fd1498Szrj 184*38fd1498Szrj;; 16<-16, 32<-32, mem 185*38fd1498Szrj(define_insn_reservation "atom_imovx_mem" 1 186*38fd1498Szrj (and (eq_attr "cpu" "atom") 187*38fd1498Szrj (and (eq_attr "type" "imovx") 188*38fd1498Szrj (and (eq_attr "memory" "!none") 189*38fd1498Szrj (ior (and (match_operand:HI 0 "register_operand") 190*38fd1498Szrj (match_operand:HI 1 "general_operand")) 191*38fd1498Szrj (and (match_operand:SI 0 "register_operand") 192*38fd1498Szrj (match_operand:SI 1 "general_operand")))))) 193*38fd1498Szrj "atom-simple-either") 194*38fd1498Szrj 195*38fd1498Szrj;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8 196*38fd1498Szrj(define_insn_reservation "atom_imovx_2" 1 197*38fd1498Szrj (and (eq_attr "cpu" "atom") 198*38fd1498Szrj (and (eq_attr "type" "imovx") 199*38fd1498Szrj (and (eq_attr "memory" "none") 200*38fd1498Szrj (ior (match_operand:QI 0 "register_operand") 201*38fd1498Szrj (ior (and (match_operand:SI 0 "register_operand") 202*38fd1498Szrj (not (match_operand:SI 1 "general_operand"))) 203*38fd1498Szrj (match_operand:DI 0 "register_operand")))))) 204*38fd1498Szrj "atom-simple-0") 205*38fd1498Szrj 206*38fd1498Szrj;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem 207*38fd1498Szrj(define_insn_reservation "atom_imovx_2_mem" 1 208*38fd1498Szrj (and (eq_attr "cpu" "atom") 209*38fd1498Szrj (and (eq_attr "type" "imovx") 210*38fd1498Szrj (and (eq_attr "memory" "!none") 211*38fd1498Szrj (ior (match_operand:QI 0 "register_operand") 212*38fd1498Szrj (ior (and (match_operand:SI 0 "register_operand") 213*38fd1498Szrj (not (match_operand:SI 1 "general_operand"))) 214*38fd1498Szrj (match_operand:DI 0 "register_operand")))))) 215*38fd1498Szrj "atom-simple-0") 216*38fd1498Szrj 217*38fd1498Szrj;; 16<-8 218*38fd1498Szrj(define_insn_reservation "atom_imovx_3" 3 219*38fd1498Szrj (and (eq_attr "cpu" "atom") 220*38fd1498Szrj (and (eq_attr "type" "imovx") 221*38fd1498Szrj (and (match_operand:HI 0 "register_operand") 222*38fd1498Szrj (match_operand:QI 1 "general_operand")))) 223*38fd1498Szrj "atom-complex, atom-all-eu*2") 224*38fd1498Szrj 225*38fd1498Szrj(define_insn_reservation "atom_lea" 1 226*38fd1498Szrj (and (eq_attr "cpu" "atom") 227*38fd1498Szrj (and (eq_attr "type" "lea") 228*38fd1498Szrj (eq_attr "mode" "!HI"))) 229*38fd1498Szrj "atom-simple-either") 230*38fd1498Szrj 231*38fd1498Szrj;; lea 16bit address is complex insn 232*38fd1498Szrj(define_insn_reservation "atom_lea_2" 2 233*38fd1498Szrj (and (eq_attr "cpu" "atom") 234*38fd1498Szrj (and (eq_attr "type" "lea") 235*38fd1498Szrj (eq_attr "mode" "HI"))) 236*38fd1498Szrj "atom-complex, atom-all-eu") 237*38fd1498Szrj 238*38fd1498Szrj(define_insn_reservation "atom_incdec" 1 239*38fd1498Szrj (and (eq_attr "cpu" "atom") 240*38fd1498Szrj (and (eq_attr "type" "incdec") 241*38fd1498Szrj (eq_attr "memory" "none"))) 242*38fd1498Szrj "atom-simple-either") 243*38fd1498Szrj 244*38fd1498Szrj(define_insn_reservation "atom_incdec_mem" 1 245*38fd1498Szrj (and (eq_attr "cpu" "atom") 246*38fd1498Szrj (and (eq_attr "type" "incdec") 247*38fd1498Szrj (eq_attr "memory" "!none"))) 248*38fd1498Szrj "atom-simple-either") 249*38fd1498Szrj 250*38fd1498Szrj;; simple shift instruction use SHIFT eu, none memory 251*38fd1498Szrj(define_insn_reservation "atom_ishift" 1 252*38fd1498Szrj (and (eq_attr "cpu" "atom") 253*38fd1498Szrj (and (eq_attr "type" "ishift") 254*38fd1498Szrj (and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0")))) 255*38fd1498Szrj "atom-simple-0") 256*38fd1498Szrj 257*38fd1498Szrj;; simple shift instruction use SHIFT eu, memory 258*38fd1498Szrj(define_insn_reservation "atom_ishift_mem" 1 259*38fd1498Szrj (and (eq_attr "cpu" "atom") 260*38fd1498Szrj (and (eq_attr "type" "ishift") 261*38fd1498Szrj (and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0")))) 262*38fd1498Szrj "atom-simple-0") 263*38fd1498Szrj 264*38fd1498Szrj;; DF shift (prefixed with 0f) is complex insn with latency of 7 cycles 265*38fd1498Szrj(define_insn_reservation "atom_ishift_3" 7 266*38fd1498Szrj (and (eq_attr "cpu" "atom") 267*38fd1498Szrj (and (eq_attr "type" "ishift") 268*38fd1498Szrj (eq_attr "prefix_0f" "1"))) 269*38fd1498Szrj "atom-complex, atom-all-eu*6") 270*38fd1498Szrj 271*38fd1498Szrj(define_insn_reservation "atom_ishift1" 1 272*38fd1498Szrj (and (eq_attr "cpu" "atom") 273*38fd1498Szrj (and (eq_attr "type" "ishift1") 274*38fd1498Szrj (eq_attr "memory" "none"))) 275*38fd1498Szrj "atom-simple-0") 276*38fd1498Szrj 277*38fd1498Szrj(define_insn_reservation "atom_ishift1_mem" 1 278*38fd1498Szrj (and (eq_attr "cpu" "atom") 279*38fd1498Szrj (and (eq_attr "type" "ishift1") 280*38fd1498Szrj (eq_attr "memory" "!none"))) 281*38fd1498Szrj "atom-simple-0") 282*38fd1498Szrj 283*38fd1498Szrj(define_insn_reservation "atom_rotate" 1 284*38fd1498Szrj (and (eq_attr "cpu" "atom") 285*38fd1498Szrj (and (eq_attr "type" "rotate") 286*38fd1498Szrj (eq_attr "memory" "none"))) 287*38fd1498Szrj "atom-simple-0") 288*38fd1498Szrj 289*38fd1498Szrj(define_insn_reservation "atom_rotate_mem" 1 290*38fd1498Szrj (and (eq_attr "cpu" "atom") 291*38fd1498Szrj (and (eq_attr "type" "rotate") 292*38fd1498Szrj (eq_attr "memory" "!none"))) 293*38fd1498Szrj "atom-simple-0") 294*38fd1498Szrj 295*38fd1498Szrj(define_insn_reservation "atom_rotate1" 1 296*38fd1498Szrj (and (eq_attr "cpu" "atom") 297*38fd1498Szrj (and (eq_attr "type" "rotate1") 298*38fd1498Szrj (eq_attr "memory" "none"))) 299*38fd1498Szrj "atom-simple-0") 300*38fd1498Szrj 301*38fd1498Szrj(define_insn_reservation "atom_rotate1_mem" 1 302*38fd1498Szrj (and (eq_attr "cpu" "atom") 303*38fd1498Szrj (and (eq_attr "type" "rotate1") 304*38fd1498Szrj (eq_attr "memory" "!none"))) 305*38fd1498Szrj "atom-simple-0") 306*38fd1498Szrj 307*38fd1498Szrj(define_insn_reservation "atom_imul" 5 308*38fd1498Szrj (and (eq_attr "cpu" "atom") 309*38fd1498Szrj (and (eq_attr "type" "imul") 310*38fd1498Szrj (and (eq_attr "memory" "none") (eq_attr "mode" "SI")))) 311*38fd1498Szrj "atom-imul-32") 312*38fd1498Szrj 313*38fd1498Szrj(define_insn_reservation "atom_imul_mem" 5 314*38fd1498Szrj (and (eq_attr "cpu" "atom") 315*38fd1498Szrj (and (eq_attr "type" "imul") 316*38fd1498Szrj (and (eq_attr "memory" "!none") (eq_attr "mode" "SI")))) 317*38fd1498Szrj "atom-imul-32") 318*38fd1498Szrj 319*38fd1498Szrj;; latency set to 10 as common 64x64 imul 320*38fd1498Szrj(define_insn_reservation "atom_imul_3" 10 321*38fd1498Szrj (and (eq_attr "cpu" "atom") 322*38fd1498Szrj (and (eq_attr "type" "imul") 323*38fd1498Szrj (eq_attr "mode" "!SI"))) 324*38fd1498Szrj "atom-complex, atom-all-eu*9") 325*38fd1498Szrj 326*38fd1498Szrj(define_insn_reservation "atom_idiv" 65 327*38fd1498Szrj (and (eq_attr "cpu" "atom") 328*38fd1498Szrj (eq_attr "type" "idiv")) 329*38fd1498Szrj "atom-complex, atom-all-eu*32, nothing*32") 330*38fd1498Szrj 331*38fd1498Szrj(define_insn_reservation "atom_icmp" 1 332*38fd1498Szrj (and (eq_attr "cpu" "atom") 333*38fd1498Szrj (and (eq_attr "type" "icmp") 334*38fd1498Szrj (eq_attr "memory" "none"))) 335*38fd1498Szrj "atom-simple-either") 336*38fd1498Szrj 337*38fd1498Szrj(define_insn_reservation "atom_icmp_mem" 1 338*38fd1498Szrj (and (eq_attr "cpu" "atom") 339*38fd1498Szrj (and (eq_attr "type" "icmp") 340*38fd1498Szrj (eq_attr "memory" "!none"))) 341*38fd1498Szrj "atom-simple-either") 342*38fd1498Szrj 343*38fd1498Szrj(define_insn_reservation "atom_test" 1 344*38fd1498Szrj (and (eq_attr "cpu" "atom") 345*38fd1498Szrj (and (eq_attr "type" "test") 346*38fd1498Szrj (eq_attr "memory" "none"))) 347*38fd1498Szrj "atom-simple-either") 348*38fd1498Szrj 349*38fd1498Szrj(define_insn_reservation "atom_test_mem" 1 350*38fd1498Szrj (and (eq_attr "cpu" "atom") 351*38fd1498Szrj (and (eq_attr "type" "test") 352*38fd1498Szrj (eq_attr "memory" "!none"))) 353*38fd1498Szrj "atom-simple-either") 354*38fd1498Szrj 355*38fd1498Szrj(define_insn_reservation "atom_ibr" 1 356*38fd1498Szrj (and (eq_attr "cpu" "atom") 357*38fd1498Szrj (and (eq_attr "type" "ibr") 358*38fd1498Szrj (eq_attr "memory" "!load"))) 359*38fd1498Szrj "atom-simple-1") 360*38fd1498Szrj 361*38fd1498Szrj;; complex if jump target is from address 362*38fd1498Szrj(define_insn_reservation "atom_ibr_2" 2 363*38fd1498Szrj (and (eq_attr "cpu" "atom") 364*38fd1498Szrj (and (eq_attr "type" "ibr") 365*38fd1498Szrj (eq_attr "memory" "load"))) 366*38fd1498Szrj "atom-complex, atom-all-eu") 367*38fd1498Szrj 368*38fd1498Szrj(define_insn_reservation "atom_setcc" 1 369*38fd1498Szrj (and (eq_attr "cpu" "atom") 370*38fd1498Szrj (and (eq_attr "type" "setcc") 371*38fd1498Szrj (eq_attr "memory" "!store"))) 372*38fd1498Szrj "atom-simple-either") 373*38fd1498Szrj 374*38fd1498Szrj;; 2 cycles complex if target is in memory 375*38fd1498Szrj(define_insn_reservation "atom_setcc_2" 2 376*38fd1498Szrj (and (eq_attr "cpu" "atom") 377*38fd1498Szrj (and (eq_attr "type" "setcc") 378*38fd1498Szrj (eq_attr "memory" "store"))) 379*38fd1498Szrj "atom-complex, atom-all-eu") 380*38fd1498Szrj 381*38fd1498Szrj(define_insn_reservation "atom_icmov" 1 382*38fd1498Szrj (and (eq_attr "cpu" "atom") 383*38fd1498Szrj (and (eq_attr "type" "icmov") 384*38fd1498Szrj (eq_attr "memory" "none"))) 385*38fd1498Szrj "atom-simple-either") 386*38fd1498Szrj 387*38fd1498Szrj(define_insn_reservation "atom_icmov_mem" 1 388*38fd1498Szrj (and (eq_attr "cpu" "atom") 389*38fd1498Szrj (and (eq_attr "type" "icmov") 390*38fd1498Szrj (eq_attr "memory" "!none"))) 391*38fd1498Szrj "atom-simple-either") 392*38fd1498Szrj 393*38fd1498Szrj;; UCODE if segreg, ignored 394*38fd1498Szrj(define_insn_reservation "atom_push" 2 395*38fd1498Szrj (and (eq_attr "cpu" "atom") 396*38fd1498Szrj (eq_attr "type" "push")) 397*38fd1498Szrj "atom-dual-2c") 398*38fd1498Szrj 399*38fd1498Szrj;; pop r64 is 1 cycle. UCODE if segreg, ignored 400*38fd1498Szrj(define_insn_reservation "atom_pop" 1 401*38fd1498Szrj (and (eq_attr "cpu" "atom") 402*38fd1498Szrj (and (eq_attr "type" "pop") 403*38fd1498Szrj (eq_attr "mode" "DI"))) 404*38fd1498Szrj "atom-dual-1c") 405*38fd1498Szrj 406*38fd1498Szrj;; pop non-r64 is 2 cycles. UCODE if segreg, ignored 407*38fd1498Szrj(define_insn_reservation "atom_pop_2" 2 408*38fd1498Szrj (and (eq_attr "cpu" "atom") 409*38fd1498Szrj (and (eq_attr "type" "pop") 410*38fd1498Szrj (eq_attr "mode" "!DI"))) 411*38fd1498Szrj "atom-dual-2c") 412*38fd1498Szrj 413*38fd1498Szrj;; UCODE if segreg, ignored 414*38fd1498Szrj(define_insn_reservation "atom_call" 1 415*38fd1498Szrj (and (eq_attr "cpu" "atom") 416*38fd1498Szrj (eq_attr "type" "call")) 417*38fd1498Szrj "atom-dual-1c") 418*38fd1498Szrj 419*38fd1498Szrj(define_insn_reservation "atom_callv" 1 420*38fd1498Szrj (and (eq_attr "cpu" "atom") 421*38fd1498Szrj (eq_attr "type" "callv")) 422*38fd1498Szrj "atom-dual-1c") 423*38fd1498Szrj 424*38fd1498Szrj(define_insn_reservation "atom_leave" 3 425*38fd1498Szrj (and (eq_attr "cpu" "atom") 426*38fd1498Szrj (eq_attr "type" "leave")) 427*38fd1498Szrj "atom-complex, atom-all-eu*2") 428*38fd1498Szrj 429*38fd1498Szrj(define_insn_reservation "atom_str" 3 430*38fd1498Szrj (and (eq_attr "cpu" "atom") 431*38fd1498Szrj (eq_attr "type" "str")) 432*38fd1498Szrj "atom-complex, atom-all-eu*2") 433*38fd1498Szrj 434*38fd1498Szrj(define_insn_reservation "atom_sselog" 1 435*38fd1498Szrj (and (eq_attr "cpu" "atom") 436*38fd1498Szrj (and (eq_attr "type" "sselog,sseshuf") 437*38fd1498Szrj (eq_attr "memory" "none"))) 438*38fd1498Szrj "atom-simple-either") 439*38fd1498Szrj 440*38fd1498Szrj(define_insn_reservation "atom_sselog_mem" 1 441*38fd1498Szrj (and (eq_attr "cpu" "atom") 442*38fd1498Szrj (and (eq_attr "type" "sselog,sseshuf") 443*38fd1498Szrj (eq_attr "memory" "!none"))) 444*38fd1498Szrj "atom-simple-either") 445*38fd1498Szrj 446*38fd1498Szrj(define_insn_reservation "atom_sselog1" 1 447*38fd1498Szrj (and (eq_attr "cpu" "atom") 448*38fd1498Szrj (and (eq_attr "type" "sselog1,sseshuf1") 449*38fd1498Szrj (eq_attr "memory" "none"))) 450*38fd1498Szrj "atom-simple-0") 451*38fd1498Szrj 452*38fd1498Szrj(define_insn_reservation "atom_sselog1_mem" 1 453*38fd1498Szrj (and (eq_attr "cpu" "atom") 454*38fd1498Szrj (and (eq_attr "type" "sselog1,sseshuf1") 455*38fd1498Szrj (eq_attr "memory" "!none"))) 456*38fd1498Szrj "atom-simple-0") 457*38fd1498Szrj 458*38fd1498Szrj;; not pmad, not psad 459*38fd1498Szrj(define_insn_reservation "atom_sseiadd" 1 460*38fd1498Szrj (and (eq_attr "cpu" "atom") 461*38fd1498Szrj (and (eq_attr "type" "sseiadd") 462*38fd1498Szrj (and (not (match_operand:V2DI 0 "register_operand")) 463*38fd1498Szrj (and (eq_attr "atom_unit" "!simul") 464*38fd1498Szrj (eq_attr "atom_unit" "!complex"))))) 465*38fd1498Szrj "atom-simple-either") 466*38fd1498Szrj 467*38fd1498Szrj;; pmad, psad and 64 468*38fd1498Szrj(define_insn_reservation "atom_sseiadd_2" 4 469*38fd1498Szrj (and (eq_attr "cpu" "atom") 470*38fd1498Szrj (and (eq_attr "type" "sseiadd") 471*38fd1498Szrj (and (not (match_operand:V2DI 0 "register_operand")) 472*38fd1498Szrj (and (eq_attr "atom_unit" "simul" ) 473*38fd1498Szrj (eq_attr "mode" "DI"))))) 474*38fd1498Szrj "atom-fmul-4c") 475*38fd1498Szrj 476*38fd1498Szrj;; pmad, psad and 128 477*38fd1498Szrj(define_insn_reservation "atom_sseiadd_3" 5 478*38fd1498Szrj (and (eq_attr "cpu" "atom") 479*38fd1498Szrj (and (eq_attr "type" "sseiadd") 480*38fd1498Szrj (and (not (match_operand:V2DI 0 "register_operand")) 481*38fd1498Szrj (and (eq_attr "atom_unit" "simul" ) 482*38fd1498Szrj (eq_attr "mode" "TI"))))) 483*38fd1498Szrj "atom-fmul-5c") 484*38fd1498Szrj 485*38fd1498Szrj;; if paddq(64 bit op), phadd/phsub 486*38fd1498Szrj(define_insn_reservation "atom_sseiadd_4" 6 487*38fd1498Szrj (and (eq_attr "cpu" "atom") 488*38fd1498Szrj (and (eq_attr "type" "sseiadd") 489*38fd1498Szrj (ior (match_operand:V2DI 0 "register_operand") 490*38fd1498Szrj (eq_attr "atom_unit" "complex")))) 491*38fd1498Szrj "atom-complex, atom-all-eu*5") 492*38fd1498Szrj 493*38fd1498Szrj;; if immediate op. 494*38fd1498Szrj(define_insn_reservation "atom_sseishft" 1 495*38fd1498Szrj (and (eq_attr "cpu" "atom") 496*38fd1498Szrj (and (eq_attr "type" "sseishft") 497*38fd1498Szrj (and (eq_attr "atom_unit" "!sishuf") 498*38fd1498Szrj (match_operand 2 "immediate_operand")))) 499*38fd1498Szrj "atom-simple-either") 500*38fd1498Szrj 501*38fd1498Szrj;; if palignr or psrldq 502*38fd1498Szrj(define_insn_reservation "atom_sseishft_2" 1 503*38fd1498Szrj (and (eq_attr "cpu" "atom") 504*38fd1498Szrj (ior (eq_attr "type" "sseishft1") 505*38fd1498Szrj (and (eq_attr "type" "sseishft") 506*38fd1498Szrj (and (eq_attr "atom_unit" "sishuf") 507*38fd1498Szrj (match_operand 2 "immediate_operand"))))) 508*38fd1498Szrj "atom-simple-0") 509*38fd1498Szrj 510*38fd1498Szrj;; if reg/mem op 511*38fd1498Szrj(define_insn_reservation "atom_sseishft_3" 2 512*38fd1498Szrj (and (eq_attr "cpu" "atom") 513*38fd1498Szrj (and (eq_attr "type" "sseishft") 514*38fd1498Szrj (not (match_operand 2 "immediate_operand")))) 515*38fd1498Szrj "atom-complex, atom-all-eu") 516*38fd1498Szrj 517*38fd1498Szrj(define_insn_reservation "atom_sseimul" 1 518*38fd1498Szrj (and (eq_attr "cpu" "atom") 519*38fd1498Szrj (eq_attr "type" "sseimul")) 520*38fd1498Szrj "atom-simple-0") 521*38fd1498Szrj 522*38fd1498Szrj;; rcpss or rsqrtss 523*38fd1498Szrj(define_insn_reservation "atom_sse" 4 524*38fd1498Szrj (and (eq_attr "cpu" "atom") 525*38fd1498Szrj (and (eq_attr "type" "sse") 526*38fd1498Szrj (and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF")))) 527*38fd1498Szrj "atom-fmul-4c") 528*38fd1498Szrj 529*38fd1498Szrj;; movshdup, movsldup. Suggest to type sseishft 530*38fd1498Szrj(define_insn_reservation "atom_sse_2" 1 531*38fd1498Szrj (and (eq_attr "cpu" "atom") 532*38fd1498Szrj (and (eq_attr "type" "sse") 533*38fd1498Szrj (eq_attr "atom_sse_attr" "movdup"))) 534*38fd1498Szrj "atom-simple-0") 535*38fd1498Szrj 536*38fd1498Szrj;; lfence 537*38fd1498Szrj(define_insn_reservation "atom_sse_3" 1 538*38fd1498Szrj (and (eq_attr "cpu" "atom") 539*38fd1498Szrj (and (eq_attr "type" "sse") 540*38fd1498Szrj (eq_attr "atom_sse_attr" "lfence"))) 541*38fd1498Szrj "atom-simple-either") 542*38fd1498Szrj 543*38fd1498Szrj;; sfence,clflush,mfence, prefetch 544*38fd1498Szrj(define_insn_reservation "atom_sse_4" 1 545*38fd1498Szrj (and (eq_attr "cpu" "atom") 546*38fd1498Szrj (and (eq_attr "type" "sse") 547*38fd1498Szrj (eq_attr "atom_sse_attr" "fence,prefetch"))) 548*38fd1498Szrj "atom-simple-0") 549*38fd1498Szrj 550*38fd1498Szrj;; rcpps, rsqrtss, sqrt, ldmxcsr 551*38fd1498Szrj(define_insn_reservation "atom_sse_5" 7 552*38fd1498Szrj (and (eq_attr "cpu" "atom") 553*38fd1498Szrj (and (eq_attr "type" "sse") 554*38fd1498Szrj (ior (eq_attr "atom_sse_attr" "sqrt,mxcsr") 555*38fd1498Szrj (and (eq_attr "atom_sse_attr" "rcp") 556*38fd1498Szrj (eq_attr "mode" "V4SF"))))) 557*38fd1498Szrj "atom-complex, atom-all-eu*6") 558*38fd1498Szrj 559*38fd1498Szrj;; xmm->xmm 560*38fd1498Szrj(define_insn_reservation "atom_ssemov" 1 561*38fd1498Szrj (and (eq_attr "cpu" "atom") 562*38fd1498Szrj (and (eq_attr "type" "ssemov") 563*38fd1498Szrj (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "xy")))) 564*38fd1498Szrj "atom-simple-either") 565*38fd1498Szrj 566*38fd1498Szrj;; reg->xmm 567*38fd1498Szrj(define_insn_reservation "atom_ssemov_2" 1 568*38fd1498Szrj (and (eq_attr "cpu" "atom") 569*38fd1498Szrj (and (eq_attr "type" "ssemov") 570*38fd1498Szrj (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "r")))) 571*38fd1498Szrj "atom-simple-0") 572*38fd1498Szrj 573*38fd1498Szrj;; xmm->reg 574*38fd1498Szrj(define_insn_reservation "atom_ssemov_3" 3 575*38fd1498Szrj (and (eq_attr "cpu" "atom") 576*38fd1498Szrj (and (eq_attr "type" "ssemov") 577*38fd1498Szrj (and (match_operand 0 "register_operand" "r") (match_operand 1 "register_operand" "xy")))) 578*38fd1498Szrj "atom-eu-0-3-1") 579*38fd1498Szrj 580*38fd1498Szrj;; mov mem 581*38fd1498Szrj(define_insn_reservation "atom_ssemov_4" 1 582*38fd1498Szrj (and (eq_attr "cpu" "atom") 583*38fd1498Szrj (and (eq_attr "type" "ssemov") 584*38fd1498Szrj (and (eq_attr "movu" "0") (eq_attr "memory" "!none")))) 585*38fd1498Szrj "atom-simple-0") 586*38fd1498Szrj 587*38fd1498Szrj;; movu mem 588*38fd1498Szrj(define_insn_reservation "atom_ssemov_5" 2 589*38fd1498Szrj (and (eq_attr "cpu" "atom") 590*38fd1498Szrj (and (eq_attr "type" "ssemov") 591*38fd1498Szrj (ior (eq_attr "movu" "1") (eq_attr "memory" "!none")))) 592*38fd1498Szrj "atom-complex, atom-all-eu") 593*38fd1498Szrj 594*38fd1498Szrj;; no memory simple 595*38fd1498Szrj(define_insn_reservation "atom_sseadd" 5 596*38fd1498Szrj (and (eq_attr "cpu" "atom") 597*38fd1498Szrj (and (eq_attr "type" "sseadd,sseadd1") 598*38fd1498Szrj (and (eq_attr "memory" "none") 599*38fd1498Szrj (and (eq_attr "mode" "!V2DF") 600*38fd1498Szrj (eq_attr "atom_unit" "!complex"))))) 601*38fd1498Szrj "atom-fadd-5c") 602*38fd1498Szrj 603*38fd1498Szrj;; memory simple 604*38fd1498Szrj(define_insn_reservation "atom_sseadd_mem" 5 605*38fd1498Szrj (and (eq_attr "cpu" "atom") 606*38fd1498Szrj (and (eq_attr "type" "sseadd,sseadd1") 607*38fd1498Szrj (and (eq_attr "memory" "!none") 608*38fd1498Szrj (and (eq_attr "mode" "!V2DF") 609*38fd1498Szrj (eq_attr "atom_unit" "!complex"))))) 610*38fd1498Szrj "atom-dual-5c") 611*38fd1498Szrj 612*38fd1498Szrj;; maxps, minps, *pd, hadd, hsub 613*38fd1498Szrj(define_insn_reservation "atom_sseadd_3" 8 614*38fd1498Szrj (and (eq_attr "cpu" "atom") 615*38fd1498Szrj (and (eq_attr "type" "sseadd,sseadd1") 616*38fd1498Szrj (ior (eq_attr "mode" "V2DF") (eq_attr "atom_unit" "complex")))) 617*38fd1498Szrj "atom-complex, atom-all-eu*7") 618*38fd1498Szrj 619*38fd1498Szrj;; Except dppd/dpps 620*38fd1498Szrj(define_insn_reservation "atom_ssemul" 5 621*38fd1498Szrj (and (eq_attr "cpu" "atom") 622*38fd1498Szrj (and (eq_attr "type" "ssemul") 623*38fd1498Szrj (eq_attr "mode" "!SF"))) 624*38fd1498Szrj "atom-fmul-5c") 625*38fd1498Szrj 626*38fd1498Szrj;; Except dppd/dpps, 4 cycle if mulss 627*38fd1498Szrj(define_insn_reservation "atom_ssemul_2" 4 628*38fd1498Szrj (and (eq_attr "cpu" "atom") 629*38fd1498Szrj (and (eq_attr "type" "ssemul") 630*38fd1498Szrj (eq_attr "mode" "SF"))) 631*38fd1498Szrj "atom-fmul-4c") 632*38fd1498Szrj 633*38fd1498Szrj(define_insn_reservation "atom_ssecmp" 1 634*38fd1498Szrj (and (eq_attr "cpu" "atom") 635*38fd1498Szrj (eq_attr "type" "ssecmp")) 636*38fd1498Szrj "atom-simple-either") 637*38fd1498Szrj 638*38fd1498Szrj(define_insn_reservation "atom_ssecomi" 10 639*38fd1498Szrj (and (eq_attr "cpu" "atom") 640*38fd1498Szrj (eq_attr "type" "ssecomi")) 641*38fd1498Szrj "atom-complex, atom-all-eu*9") 642*38fd1498Szrj 643*38fd1498Szrj;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi 644*38fd1498Szrj(define_insn_reservation "atom_ssecvt" 5 645*38fd1498Szrj (and (eq_attr "cpu" "atom") 646*38fd1498Szrj (and (eq_attr "type" "ssecvt") 647*38fd1498Szrj (ior (and (match_operand:V2SI 0 "register_operand") 648*38fd1498Szrj (match_operand:V4SF 1 "register_operand")) 649*38fd1498Szrj (and (match_operand:V4SF 0 "register_operand") 650*38fd1498Szrj (match_operand:V2SI 1 "register_operand"))))) 651*38fd1498Szrj "atom-fadd-5c") 652*38fd1498Szrj 653*38fd1498Szrj;; memory and cvtpi2ps, cvtps2pi, cvttps2pi 654*38fd1498Szrj(define_insn_reservation "atom_ssecvt_2" 5 655*38fd1498Szrj (and (eq_attr "cpu" "atom") 656*38fd1498Szrj (and (eq_attr "type" "ssecvt") 657*38fd1498Szrj (ior (and (match_operand:V2SI 0 "register_operand") 658*38fd1498Szrj (match_operand:V4SF 1 "memory_operand")) 659*38fd1498Szrj (and (match_operand:V4SF 0 "register_operand") 660*38fd1498Szrj (match_operand:V2SI 1 "memory_operand"))))) 661*38fd1498Szrj "atom-dual-5c") 662*38fd1498Szrj 663*38fd1498Szrj;; otherwise. 7 cycles average for cvtss2sd 664*38fd1498Szrj(define_insn_reservation "atom_ssecvt_3" 7 665*38fd1498Szrj (and (eq_attr "cpu" "atom") 666*38fd1498Szrj (and (eq_attr "type" "ssecvt") 667*38fd1498Szrj (not (ior (and (match_operand:V2SI 0 "register_operand") 668*38fd1498Szrj (match_operand:V4SF 1 "nonimmediate_operand")) 669*38fd1498Szrj (and (match_operand:V4SF 0 "register_operand") 670*38fd1498Szrj (match_operand:V2SI 1 "nonimmediate_operand")))))) 671*38fd1498Szrj "atom-complex, atom-all-eu*6") 672*38fd1498Szrj 673*38fd1498Szrj;; memory and cvtsi2sd 674*38fd1498Szrj(define_insn_reservation "atom_sseicvt" 5 675*38fd1498Szrj (and (eq_attr "cpu" "atom") 676*38fd1498Szrj (and (eq_attr "type" "sseicvt") 677*38fd1498Szrj (and (match_operand:V2DF 0 "register_operand") 678*38fd1498Szrj (match_operand:SI 1 "memory_operand")))) 679*38fd1498Szrj "atom-dual-5c") 680*38fd1498Szrj 681*38fd1498Szrj;; otherwise. 8 cycles average for cvtsd2si 682*38fd1498Szrj(define_insn_reservation "atom_sseicvt_2" 8 683*38fd1498Szrj (and (eq_attr "cpu" "atom") 684*38fd1498Szrj (and (eq_attr "type" "sseicvt") 685*38fd1498Szrj (not (and (match_operand:V2DF 0 "register_operand") 686*38fd1498Szrj (match_operand:SI 1 "memory_operand"))))) 687*38fd1498Szrj "atom-complex, atom-all-eu*7") 688*38fd1498Szrj 689*38fd1498Szrj(define_insn_reservation "atom_ssediv" 62 690*38fd1498Szrj (and (eq_attr "cpu" "atom") 691*38fd1498Szrj (eq_attr "type" "ssediv")) 692*38fd1498Szrj "atom-complex, atom-all-eu*12, nothing*49") 693*38fd1498Szrj 694*38fd1498Szrj;; simple for fmov 695*38fd1498Szrj(define_insn_reservation "atom_fmov" 1 696*38fd1498Szrj (and (eq_attr "cpu" "atom") 697*38fd1498Szrj (and (eq_attr "type" "fmov") 698*38fd1498Szrj (eq_attr "memory" "none"))) 699*38fd1498Szrj "atom-simple-either") 700*38fd1498Szrj 701*38fd1498Szrj;; simple for fmov 702*38fd1498Szrj(define_insn_reservation "atom_fmov_mem" 1 703*38fd1498Szrj (and (eq_attr "cpu" "atom") 704*38fd1498Szrj (and (eq_attr "type" "fmov") 705*38fd1498Szrj (eq_attr "memory" "!none"))) 706*38fd1498Szrj "atom-simple-either") 707*38fd1498Szrj 708*38fd1498Szrj;; Define bypass here 709*38fd1498Szrj 710*38fd1498Szrj;; There will be no stall from lea to non-mem EX insns 711*38fd1498Szrj(define_bypass 0 "atom_lea" 712*38fd1498Szrj "atom_alu_carry, 713*38fd1498Szrj atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, 714*38fd1498Szrj atom_incdec, atom_setcc, atom_icmov, atom_pop") 715*38fd1498Szrj 716*38fd1498Szrj(define_bypass 0 "atom_lea" 717*38fd1498Szrj "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, 718*38fd1498Szrj atom_imovx_mem, atom_imovx_2_mem, 719*38fd1498Szrj atom_imov_mem, atom_icmov_mem, atom_fmov_mem" 720*38fd1498Szrj "!ix86_agi_dependent") 721*38fd1498Szrj 722*38fd1498Szrj;; There will be 3 cycles stall from EX insns to AGAN insns LEA 723*38fd1498Szrj(define_bypass 4 "atom_alu_carry, 724*38fd1498Szrj atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, 725*38fd1498Szrj atom_incdec,atom_ishift,atom_ishift1,atom_rotate, 726*38fd1498Szrj atom_rotate1, atom_setcc, atom_icmov, atom_pop, 727*38fd1498Szrj atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, 728*38fd1498Szrj atom_imovx_mem, atom_imovx_2_mem, 729*38fd1498Szrj atom_imov_mem, atom_icmov_mem, atom_fmov_mem" 730*38fd1498Szrj "atom_lea") 731*38fd1498Szrj 732*38fd1498Szrj;; There will be 3 cycles stall from EX insns to insns need addr calculation 733*38fd1498Szrj(define_bypass 4 "atom_alu_carry, 734*38fd1498Szrj atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, 735*38fd1498Szrj atom_incdec,atom_ishift,atom_ishift1,atom_rotate, 736*38fd1498Szrj atom_rotate1, atom_setcc, atom_icmov, atom_pop, 737*38fd1498Szrj atom_imovx_mem, atom_imovx_2_mem, 738*38fd1498Szrj atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, 739*38fd1498Szrj atom_imov_mem, atom_icmov_mem, atom_fmov_mem" 740*38fd1498Szrj "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, 741*38fd1498Szrj atom_negnot_mem, atom_imov_mem, atom_incdec_mem, 742*38fd1498Szrj atom_imovx_mem, atom_imovx_2_mem, 743*38fd1498Szrj atom_imul_mem, atom_icmp_mem, 744*38fd1498Szrj atom_test_mem, atom_icmov_mem, atom_sselog_mem, 745*38fd1498Szrj atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem, 746*38fd1498Szrj atom_ishift_mem, atom_ishift1_mem, 747*38fd1498Szrj atom_rotate_mem, atom_rotate1_mem" 748*38fd1498Szrj "ix86_agi_dependent") 749*38fd1498Szrj 750*38fd1498Szrj;; Stall from imul to lea is 8 cycles. 751*38fd1498Szrj(define_bypass 9 "atom_imul, atom_imul_mem" "atom_lea") 752*38fd1498Szrj 753*38fd1498Szrj;; Stall from imul to memory address is 8 cycles. 754*38fd1498Szrj(define_bypass 9 "atom_imul, atom_imul_mem" 755*38fd1498Szrj "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, 756*38fd1498Szrj atom_negnot_mem, atom_imov_mem, atom_incdec_mem, 757*38fd1498Szrj atom_ishift_mem, atom_ishift1_mem, atom_rotate_mem, 758*38fd1498Szrj atom_rotate1_mem, atom_imul_mem, atom_icmp_mem, 759*38fd1498Szrj atom_test_mem, atom_icmov_mem, atom_sselog_mem, 760*38fd1498Szrj atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem" 761*38fd1498Szrj "ix86_agi_dependent") 762*38fd1498Szrj 763*38fd1498Szrj;; There will be 0 cycle stall from cmp/test to jcc 764*38fd1498Szrj 765*38fd1498Szrj;; There will be 1 cycle stall from flag producer to cmov and adc/sbb 766*38fd1498Szrj(define_bypass 2 "atom_icmp, atom_test, atom_alu, atom_alu_carry, 767*38fd1498Szrj atom_alu1, atom_negnot, atom_incdec, atom_ishift, 768*38fd1498Szrj atom_ishift1, atom_rotate, atom_rotate1" 769*38fd1498Szrj "atom_icmov, atom_alu_carry") 770*38fd1498Szrj 771*38fd1498Szrj;; lea to shift count stall is 2 cycles 772*38fd1498Szrj(define_bypass 3 "atom_lea" 773*38fd1498Szrj "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1, 774*38fd1498Szrj atom_ishift_mem, atom_ishift1_mem, 775*38fd1498Szrj atom_rotate_mem, atom_rotate1_mem" 776*38fd1498Szrj "ix86_dep_by_shift_count") 777*38fd1498Szrj 778*38fd1498Szrj;; lea to shift source stall is 1 cycle 779*38fd1498Szrj(define_bypass 2 "atom_lea" 780*38fd1498Szrj "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1" 781*38fd1498Szrj "!ix86_dep_by_shift_count") 782*38fd1498Szrj 783*38fd1498Szrj;; non-lea to shift count stall is 1 cycle 784*38fd1498Szrj(define_bypass 2 "atom_alu_carry, 785*38fd1498Szrj atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, 786*38fd1498Szrj atom_incdec,atom_ishift,atom_ishift1,atom_rotate, 787*38fd1498Szrj atom_rotate1, atom_setcc, atom_icmov, atom_pop, 788*38fd1498Szrj atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, 789*38fd1498Szrj atom_imovx_mem, atom_imovx_2_mem, 790*38fd1498Szrj atom_imov_mem, atom_icmov_mem, atom_fmov_mem" 791*38fd1498Szrj "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1, 792*38fd1498Szrj atom_ishift_mem, atom_ishift1_mem, 793*38fd1498Szrj atom_rotate_mem, atom_rotate1_mem" 794*38fd1498Szrj "ix86_dep_by_shift_count") 795