1;; Constraint definitions for IA-32 and x86-64.
2;; Copyright (C) 2006-2018 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3.  If not see
18;; <http://www.gnu.org/licenses/>.
19
20;;; Unused letters:
21;;;           H
22;;;           h j               z
23
24;; Integer register constraints.
25;; It is not necessary to define 'r' here.
26(define_register_constraint "R" "LEGACY_REGS"
27 "Legacy register---the eight integer registers available on all
28  i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
29  @code{si}, @code{di}, @code{bp}, @code{sp}).")
30
31(define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
32 "Any register accessible as @code{@var{r}l}.  In 32-bit mode, @code{a},
33  @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
34
35(define_register_constraint "Q" "Q_REGS"
36 "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
37  @code{c}, and @code{d}.")
38
39(define_register_constraint "l" "INDEX_REGS"
40 "@internal Any register that can be used as the index in a base+index
41  memory access: that is, any general register except the stack pointer.")
42
43(define_register_constraint "a" "AREG"
44 "The @code{a} register.")
45
46(define_register_constraint "b" "BREG"
47 "The @code{b} register.")
48
49(define_register_constraint "c" "CREG"
50 "The @code{c} register.")
51
52(define_register_constraint "d" "DREG"
53 "The @code{d} register.")
54
55(define_register_constraint "S" "SIREG"
56 "The @code{si} register.")
57
58(define_register_constraint "D" "DIREG"
59 "The @code{di} register.")
60
61(define_register_constraint "A" "AD_REGS"
62 "The @code{a} and @code{d} registers, as a pair (for instructions
63  that return half the result in one and half in the other).")
64
65(define_register_constraint "U" "CLOBBERED_REGS"
66 "The call-clobbered integer registers.")
67
68;; Floating-point register constraints.
69(define_register_constraint "f"
70 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
71 "Any 80387 floating-point (stack) register.")
72
73(define_register_constraint "t"
74 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
75 "Top of 80387 floating-point stack (@code{%st(0)}).")
76
77(define_register_constraint "u"
78 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
79 "Second from top of 80387 floating-point stack (@code{%st(1)}).")
80
81(define_register_constraint "Yk" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS"
82"@internal Any mask register that can be used as predicate, i.e. k1-k7.")
83
84(define_register_constraint "k" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
85"@internal Any mask register.")
86
87;; Vector registers (also used for plain floating point nowadays).
88(define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
89 "Any MMX register.")
90
91(define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
92 "Any SSE register.")
93
94(define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
95 "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
96
97(define_register_constraint "w" "TARGET_MPX ? BND_REGS : NO_REGS"
98 "@internal Any bound register.")
99
100;; We use the Y prefix to denote any number of conditional register sets:
101;;  z	First SSE register.
102;;  i	SSE2 inter-unit moves to SSE register enabled
103;;  j	SSE2 inter-unit moves from SSE register enabled
104;;  d	any EVEX encodable SSE register for AVX512BW target or any SSE register
105;;	for SSE4_1 target, when inter-unit moves to SSE register are enabled
106;;  e	any EVEX encodable SSE register for AVX512BW target or any SSE register
107;;	for SSE4_1 target, when inter-unit moves from SSE register are enabled
108;;  m	MMX inter-unit moves to MMX register enabled
109;;  n	MMX inter-unit moves from MMX register enabled
110;;  p	Integer register when TARGET_PARTIAL_REG_STALL is disabled
111;;  a	Integer register when zero extensions with AND are disabled
112;;  b	Any register that can be used as the GOT base when calling
113;;	___tls_get_addr: that is, any general register except EAX
114;;	and ESP, for -fno-plt if linker supports it.  Otherwise,
115;;	EBX.
116;;  f	x87 register when 80387 floating point arithmetic is enabled
117;;  r	SSE regs not requiring REX prefix when prefixes avoidance is enabled
118;;	and all SSE regs otherwise
119;;  v	any EVEX encodable SSE register for AVX512VL target,
120;;	otherwise any SSE register
121;;  h	EVEX encodable SSE register with number factor of four
122
123(define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
124 "First SSE register (@code{%xmm0}).")
125
126(define_register_constraint "Yi"
127 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
128 "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.")
129
130(define_register_constraint "Yj"
131 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS"
132 "@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.")
133
134(define_register_constraint "Yd"
135 "TARGET_INTER_UNIT_MOVES_TO_VEC
136  ? (TARGET_AVX512DQ
137     ? ALL_SSE_REGS
138     : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
139  : NO_REGS"
140 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.")
141
142(define_register_constraint "Ye"
143 "TARGET_INTER_UNIT_MOVES_FROM_VEC
144  ? (TARGET_AVX512DQ
145     ? ALL_SSE_REGS
146     : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS))
147  : NO_REGS"
148 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.")
149
150(define_register_constraint "Ym"
151 "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS"
152 "@internal Any MMX register, when inter-unit moves to vector registers are enabled.")
153
154(define_register_constraint "Yn"
155 "TARGET_MMX && TARGET_INTER_UNIT_MOVES_FROM_VEC ? MMX_REGS : NO_REGS"
156 "@internal Any MMX register, when inter-unit moves from vector registers are enabled.")
157
158(define_register_constraint "Yp"
159 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
160 "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
161
162(define_register_constraint "Ya"
163 "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)
164  ? NO_REGS : GENERAL_REGS"
165 "@internal Any integer register when zero extensions with AND are disabled.")
166
167(define_register_constraint "Yb"
168 "(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG"
169 "@internal Any register that can be used as the GOT base when calling
170  ___tls_get_addr: that is, any general register except @code{a} and
171  @code{sp} registers, for -fno-plt if linker supports it.  Otherwise,
172  @code{b} register.")
173
174(define_register_constraint "Yf"
175 "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
176 "@internal Any x87 register when 80387 FP arithmetic is enabled.")
177
178(define_register_constraint "Yr"
179 "TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS"
180 "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.")
181
182(define_register_constraint "Yv"
183 "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
184 "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
185
186(define_register_constraint "Yh" "TARGET_AVX512F ? MOD4_SSE_REGS : NO_REGS"
187 "@internal Any EVEX encodable SSE register, which has number factor of four.")
188
189;; We use the B prefix to denote any number of internal operands:
190;;  f  FLAGS_REG
191;;  g  GOT memory operand.
192;;  m  Vector memory operand
193;;  c  Constant memory operand
194;;  n  Memory operand without REX prefix
195;;  s  Sibcall memory operand, not valid for TARGET_X32
196;;  w  Call memory operand, not valid for TARGET_X32
197;;  z  Constant call address operand.
198;;  C  SSE constant operand.
199
200(define_constraint "Bf"
201  "@internal Flags register operand."
202  (match_operand 0 "flags_reg_operand"))
203
204(define_constraint "Bg"
205  "@internal GOT memory operand."
206  (match_operand 0 "GOT_memory_operand"))
207
208(define_special_memory_constraint "Bm"
209  "@internal Vector memory operand."
210  (match_operand 0 "vector_memory_operand"))
211
212(define_special_memory_constraint "Bc"
213  "@internal Constant memory operand."
214  (and (match_operand 0 "memory_operand")
215       (match_test "constant_address_p (XEXP (op, 0))")))
216
217(define_special_memory_constraint "Bn"
218  "@internal Memory operand without REX prefix."
219  (match_operand 0 "norex_memory_operand"))
220
221(define_constraint "Bs"
222  "@internal Sibcall memory operand."
223  (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
224	    (not (match_test "TARGET_X32"))
225	    (match_operand 0 "sibcall_memory_operand"))
226       (and (match_test "TARGET_X32 && Pmode == DImode")
227	    (match_operand 0 "GOT_memory_operand"))))
228
229(define_constraint "Bw"
230  "@internal Call memory operand."
231  (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
232	    (not (match_test "TARGET_X32"))
233	    (match_operand 0 "memory_operand"))
234       (and (match_test "TARGET_X32 && Pmode == DImode")
235	    (match_operand 0 "GOT_memory_operand"))))
236
237(define_constraint "Bz"
238  "@internal Constant call address operand."
239  (match_operand 0 "constant_call_address_operand"))
240
241(define_constraint "BC"
242  "@internal SSE constant -1 operand."
243  (and (match_test "TARGET_SSE")
244       (ior (match_test "op == constm1_rtx")
245	    (match_operand 0 "vector_all_ones_operand"))))
246
247;; Integer constant constraints.
248(define_constraint "I"
249  "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
250  (and (match_code "const_int")
251       (match_test "IN_RANGE (ival, 0, 31)")))
252
253(define_constraint "J"
254  "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
255  (and (match_code "const_int")
256       (match_test "IN_RANGE (ival, 0, 63)")))
257
258(define_constraint "K"
259  "Signed 8-bit integer constant."
260  (and (match_code "const_int")
261       (match_test "IN_RANGE (ival, -128, 127)")))
262
263(define_constraint "L"
264  "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF}
265   for AND as a zero-extending move."
266  (and (match_code "const_int")
267       (match_test "ival == 0xff || ival == 0xffff
268		    || ival == (HOST_WIDE_INT) 0xffffffff")))
269
270(define_constraint "M"
271  "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
272  (and (match_code "const_int")
273       (match_test "IN_RANGE (ival, 0, 3)")))
274
275(define_constraint "N"
276  "Unsigned 8-bit integer constant (for @code{in} and @code{out}
277   instructions)."
278  (and (match_code "const_int")
279       (match_test "IN_RANGE (ival, 0, 255)")))
280
281(define_constraint "O"
282  "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
283  (and (match_code "const_int")
284       (match_test "IN_RANGE (ival, 0, 127)")))
285
286;; Floating-point constant constraints.
287;; We allow constants even if TARGET_80387 isn't set, because the
288;; stack register converter may need to load 0.0 into the function
289;; value register (top of stack).
290(define_constraint "G"
291  "Standard 80387 floating point constant."
292  (and (match_code "const_double")
293       (match_test "standard_80387_constant_p (op) > 0")))
294
295;; This can theoretically be any mode's CONST0_RTX.
296(define_constraint "C"
297  "SSE constant zero operand."
298  (and (match_test "TARGET_SSE")
299       (ior (match_test "op == const0_rtx")
300	    (match_operand 0 "const0_operand"))))
301
302;; Constant-or-symbol-reference constraints.
303
304(define_constraint "e"
305  "32-bit signed integer constant, or a symbolic reference known
306   to fit that range (for immediate operands in sign-extending x86-64
307   instructions)."
308  (match_operand 0 "x86_64_immediate_operand"))
309
310;; We use W prefix to denote any number of
311;; constant-or-symbol-reference constraints
312
313(define_constraint "We"
314  "32-bit signed integer constant, or a symbolic reference known
315   to fit that range (for sign-extending conversion operations that
316   require non-VOIDmode immediate operands)."
317  (and (match_operand 0 "x86_64_immediate_operand")
318       (match_test "GET_MODE (op) != VOIDmode")))
319
320(define_constraint "Wz"
321  "32-bit unsigned integer constant, or a symbolic reference known
322   to fit that range (for zero-extending conversion operations that
323   require non-VOIDmode immediate operands)."
324  (and (match_operand 0 "x86_64_zext_immediate_operand")
325       (match_test "GET_MODE (op) != VOIDmode")))
326
327(define_constraint "Wd"
328  "128-bit integer constant where both the high and low 64-bit word
329   of it satisfies the e constraint."
330  (match_operand 0 "x86_64_hilo_int_operand"))
331
332(define_constraint "Wf"
333  "32-bit signed integer constant zero extended from word size
334   to double word size."
335  (match_operand 0 "x86_64_dwzext_immediate_operand"))
336
337(define_constraint "Z"
338  "32-bit unsigned integer constant, or a symbolic reference known
339   to fit that range (for immediate operands in zero-extending x86-64
340   instructions)."
341  (match_operand 0 "x86_64_zext_immediate_operand"))
342
343;; T prefix is used for different address constraints
344;;   v - VSIB address
345;;   s - address with no segment register
346;;   i - address with no index and no rip
347;;   b - address with no base and no rip
348
349(define_address_constraint "Tv"
350  "VSIB address operand"
351  (match_operand 0 "vsib_address_operand"))
352
353(define_address_constraint "Ts"
354  "Address operand without segment register"
355  (match_operand 0 "address_no_seg_operand"))
356
357(define_address_constraint "Ti"
358  "MPX address operand without index"
359  (match_operand 0 "address_mpx_no_index_operand"))
360
361(define_address_constraint "Tb"
362  "MPX address operand without base"
363  (match_operand 0 "address_mpx_no_base_operand"))
364