138fd1498Szrj /* Definitions of target machine for GCC for IA-32. 238fd1498Szrj Copyright (C) 1988-2018 Free Software Foundation, Inc. 338fd1498Szrj 438fd1498Szrj This file is part of GCC. 538fd1498Szrj 638fd1498Szrj GCC is free software; you can redistribute it and/or modify 738fd1498Szrj it under the terms of the GNU General Public License as published by 838fd1498Szrj the Free Software Foundation; either version 3, or (at your option) 938fd1498Szrj any later version. 1038fd1498Szrj 1138fd1498Szrj GCC is distributed in the hope that it will be useful, 1238fd1498Szrj but WITHOUT ANY WARRANTY; without even the implied warranty of 1338fd1498Szrj MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1438fd1498Szrj GNU General Public License for more details. 1538fd1498Szrj 1638fd1498Szrj Under Section 7 of GPL version 3, you are granted additional 1738fd1498Szrj permissions described in the GCC Runtime Library Exception, version 1838fd1498Szrj 3.1, as published by the Free Software Foundation. 1938fd1498Szrj 2038fd1498Szrj You should have received a copy of the GNU General Public License and 2138fd1498Szrj a copy of the GCC Runtime Library Exception along with this program; 2238fd1498Szrj see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 2338fd1498Szrj <http://www.gnu.org/licenses/>. */ 2438fd1498Szrj 2538fd1498Szrj /* The purpose of this file is to define the characteristics of the i386, 2638fd1498Szrj independent of assembler syntax or operating system. 2738fd1498Szrj 2838fd1498Szrj Three other files build on this one to describe a specific assembler syntax: 2938fd1498Szrj bsd386.h, att386.h, and sun386.h. 3038fd1498Szrj 3138fd1498Szrj The actual tm.h file for a particular system should include 3238fd1498Szrj this file, and then the file for the appropriate assembler syntax. 3338fd1498Szrj 3438fd1498Szrj Many macros that specify assembler syntax are omitted entirely from 3538fd1498Szrj this file because they really belong in the files for particular 3638fd1498Szrj assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 3738fd1498Szrj ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 3838fd1498Szrj that start with ASM_ or end in ASM_OP. */ 3938fd1498Szrj 4038fd1498Szrj /* Redefines for option macros. */ 4138fd1498Szrj 4238fd1498Szrj #define TARGET_64BIT TARGET_ISA_64BIT 4338fd1498Szrj #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) 4438fd1498Szrj #define TARGET_MMX TARGET_ISA_MMX 4538fd1498Szrj #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) 4638fd1498Szrj #define TARGET_3DNOW TARGET_ISA_3DNOW 4738fd1498Szrj #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) 4838fd1498Szrj #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A 4938fd1498Szrj #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) 5038fd1498Szrj #define TARGET_SSE TARGET_ISA_SSE 5138fd1498Szrj #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) 5238fd1498Szrj #define TARGET_SSE2 TARGET_ISA_SSE2 5338fd1498Szrj #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) 5438fd1498Szrj #define TARGET_SSE3 TARGET_ISA_SSE3 5538fd1498Szrj #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) 5638fd1498Szrj #define TARGET_SSSE3 TARGET_ISA_SSSE3 5738fd1498Szrj #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) 5838fd1498Szrj #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 5938fd1498Szrj #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) 6038fd1498Szrj #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 6138fd1498Szrj #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) 6238fd1498Szrj #define TARGET_AVX TARGET_ISA_AVX 6338fd1498Szrj #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) 6438fd1498Szrj #define TARGET_AVX2 TARGET_ISA_AVX2 6538fd1498Szrj #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) 6638fd1498Szrj #define TARGET_AVX512F TARGET_ISA_AVX512F 6738fd1498Szrj #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) 6838fd1498Szrj #define TARGET_AVX512PF TARGET_ISA_AVX512PF 6938fd1498Szrj #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) 7038fd1498Szrj #define TARGET_AVX512ER TARGET_ISA_AVX512ER 7138fd1498Szrj #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) 7238fd1498Szrj #define TARGET_AVX512CD TARGET_ISA_AVX512CD 7338fd1498Szrj #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) 7438fd1498Szrj #define TARGET_AVX512DQ TARGET_ISA_AVX512DQ 7538fd1498Szrj #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) 7638fd1498Szrj #define TARGET_AVX512BW TARGET_ISA_AVX512BW 7738fd1498Szrj #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) 7838fd1498Szrj #define TARGET_AVX512VL TARGET_ISA_AVX512VL 7938fd1498Szrj #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) 8038fd1498Szrj #define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI 8138fd1498Szrj #define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) 8238fd1498Szrj #define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA 8338fd1498Szrj #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) 8438fd1498Szrj #define TARGET_AVX5124FMAPS TARGET_ISA_AVX5124FMAPS 8538fd1498Szrj #define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x) 8638fd1498Szrj #define TARGET_AVX5124VNNIW TARGET_ISA_AVX5124VNNIW 8738fd1498Szrj #define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x) 8838fd1498Szrj #define TARGET_AVX512VBMI2 TARGET_ISA_AVX512VBMI2 8938fd1498Szrj #define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x) 9038fd1498Szrj #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ 9138fd1498Szrj #define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x) 9238fd1498Szrj #define TARGET_AVX512VNNI TARGET_ISA_AVX512VNNI 9338fd1498Szrj #define TARGET_AVX512VNNI_P(x) TARGET_ISA_AVX512VNNI_P(x) 9438fd1498Szrj #define TARGET_AVX512BITALG TARGET_ISA_AVX512BITALG 9538fd1498Szrj #define TARGET_AVX512BITALG_P(x) TARGET_ISA_AVX512BITALG_P(x) 9638fd1498Szrj #define TARGET_FMA TARGET_ISA_FMA 9738fd1498Szrj #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) 9838fd1498Szrj #define TARGET_SSE4A TARGET_ISA_SSE4A 9938fd1498Szrj #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) 10038fd1498Szrj #define TARGET_FMA4 TARGET_ISA_FMA4 10138fd1498Szrj #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) 10238fd1498Szrj #define TARGET_XOP TARGET_ISA_XOP 10338fd1498Szrj #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) 10438fd1498Szrj #define TARGET_LWP TARGET_ISA_LWP 10538fd1498Szrj #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) 10638fd1498Szrj #define TARGET_ABM TARGET_ISA_ABM 10738fd1498Szrj #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) 10838fd1498Szrj #define TARGET_PCONFIG TARGET_ISA_PCONFIG 10938fd1498Szrj #define TARGET_PCONFIG_P(x) TARGET_ISA_PCONFIG_P(x) 11038fd1498Szrj #define TARGET_WBNOINVD TARGET_ISA_WBNOINVD 11138fd1498Szrj #define TARGET_WBNOINVD_P(x) TARGET_ISA_WBNOINVD_P(x) 11238fd1498Szrj #define TARGET_SGX TARGET_ISA_SGX 11338fd1498Szrj #define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x) 11438fd1498Szrj #define TARGET_RDPID TARGET_ISA_RDPID 11538fd1498Szrj #define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x) 11638fd1498Szrj #define TARGET_GFNI TARGET_ISA_GFNI 11738fd1498Szrj #define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x) 11838fd1498Szrj #define TARGET_VAES TARGET_ISA_VAES 11938fd1498Szrj #define TARGET_VAES_P(x) TARGET_ISA_VAES_P(x) 12038fd1498Szrj #define TARGET_VPCLMULQDQ TARGET_ISA_VPCLMULQDQ 12138fd1498Szrj #define TARGET_VPCLMULQDQ_P(x) TARGET_ISA_VPCLMULQDQ_P(x) 12238fd1498Szrj #define TARGET_BMI TARGET_ISA_BMI 12338fd1498Szrj #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) 12438fd1498Szrj #define TARGET_BMI2 TARGET_ISA_BMI2 12538fd1498Szrj #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) 12638fd1498Szrj #define TARGET_LZCNT TARGET_ISA_LZCNT 12738fd1498Szrj #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) 12838fd1498Szrj #define TARGET_TBM TARGET_ISA_TBM 12938fd1498Szrj #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) 13038fd1498Szrj #define TARGET_POPCNT TARGET_ISA_POPCNT 13138fd1498Szrj #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) 13238fd1498Szrj #define TARGET_SAHF TARGET_ISA_SAHF 13338fd1498Szrj #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) 13438fd1498Szrj #define TARGET_MOVBE TARGET_ISA_MOVBE 13538fd1498Szrj #define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x) 13638fd1498Szrj #define TARGET_CRC32 TARGET_ISA_CRC32 13738fd1498Szrj #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) 13838fd1498Szrj #define TARGET_AES TARGET_ISA_AES 13938fd1498Szrj #define TARGET_AES_P(x) TARGET_ISA_AES_P(x) 14038fd1498Szrj #define TARGET_SHA TARGET_ISA_SHA 14138fd1498Szrj #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) 14238fd1498Szrj #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT 14338fd1498Szrj #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) 14438fd1498Szrj #define TARGET_CLZERO TARGET_ISA_CLZERO 14538fd1498Szrj #define TARGET_CLZERO_P(x) TARGET_ISA_CLZERO_P(x) 14638fd1498Szrj #define TARGET_XSAVEC TARGET_ISA_XSAVEC 14738fd1498Szrj #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) 14838fd1498Szrj #define TARGET_XSAVES TARGET_ISA_XSAVES 14938fd1498Szrj #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) 15038fd1498Szrj #define TARGET_PCLMUL TARGET_ISA_PCLMUL 15138fd1498Szrj #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) 15238fd1498Szrj #define TARGET_CMPXCHG16B TARGET_ISA_CX16 15338fd1498Szrj #define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x) 15438fd1498Szrj #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE 15538fd1498Szrj #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) 15638fd1498Szrj #define TARGET_RDRND TARGET_ISA_RDRND 15738fd1498Szrj #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) 15838fd1498Szrj #define TARGET_F16C TARGET_ISA_F16C 15938fd1498Szrj #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) 16038fd1498Szrj #define TARGET_RTM TARGET_ISA_RTM 16138fd1498Szrj #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) 16238fd1498Szrj #define TARGET_HLE TARGET_ISA_HLE 16338fd1498Szrj #define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x) 16438fd1498Szrj #define TARGET_RDSEED TARGET_ISA_RDSEED 16538fd1498Szrj #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) 16638fd1498Szrj #define TARGET_PRFCHW TARGET_ISA_PRFCHW 16738fd1498Szrj #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) 16838fd1498Szrj #define TARGET_ADX TARGET_ISA_ADX 16938fd1498Szrj #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) 17038fd1498Szrj #define TARGET_FXSR TARGET_ISA_FXSR 17138fd1498Szrj #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) 17238fd1498Szrj #define TARGET_XSAVE TARGET_ISA_XSAVE 17338fd1498Szrj #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) 17438fd1498Szrj #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT 17538fd1498Szrj #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) 17638fd1498Szrj #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 17738fd1498Szrj #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) 17838fd1498Szrj #define TARGET_MPX TARGET_ISA_MPX 17938fd1498Szrj #define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x) 18038fd1498Szrj #define TARGET_CLWB TARGET_ISA_CLWB 18138fd1498Szrj #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) 18238fd1498Szrj #define TARGET_MWAITX TARGET_ISA_MWAITX 18338fd1498Szrj #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) 18438fd1498Szrj #define TARGET_PKU TARGET_ISA_PKU 18538fd1498Szrj #define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) 18638fd1498Szrj #define TARGET_SHSTK TARGET_ISA_SHSTK 18738fd1498Szrj #define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x) 18838fd1498Szrj #define TARGET_MOVDIRI TARGET_ISA_MOVDIRI 18938fd1498Szrj #define TARGET_MOVDIRI_P(x) TARGET_ISA_MOVDIRI_P(x) 19038fd1498Szrj #define TARGET_MOVDIR64B TARGET_ISA_MOVDIR64B 19138fd1498Szrj #define TARGET_MOVDIR64B_P(x) TARGET_ISA_MOVDIR64B_P(x) 19238fd1498Szrj 19338fd1498Szrj #define TARGET_LP64 TARGET_ABI_64 19438fd1498Szrj #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) 19538fd1498Szrj #define TARGET_X32 TARGET_ABI_X32 19638fd1498Szrj #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) 19738fd1498Szrj #define TARGET_16BIT TARGET_CODE16 19838fd1498Szrj #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) 19938fd1498Szrj 20038fd1498Szrj #include "config/vxworks-dummy.h" 20138fd1498Szrj 20238fd1498Szrj #include "config/i386/i386-opts.h" 20338fd1498Szrj 20438fd1498Szrj #define MAX_STRINGOP_ALGS 4 20538fd1498Szrj 20638fd1498Szrj /* Specify what algorithm to use for stringops on known size. 20738fd1498Szrj When size is unknown, the UNKNOWN_SIZE alg is used. When size is 20838fd1498Szrj known at compile time or estimated via feedback, the SIZE array 20938fd1498Szrj is walked in order until MAX is greater then the estimate (or -1 21038fd1498Szrj means infinity). Corresponding ALG is used then. 21138fd1498Szrj When NOALIGN is true the code guaranting the alignment of the memory 21238fd1498Szrj block is skipped. 21338fd1498Szrj 21438fd1498Szrj For example initializer: 21538fd1498Szrj {{256, loop}, {-1, rep_prefix_4_byte}} 21638fd1498Szrj will use loop for blocks smaller or equal to 256 bytes, rep prefix will 21738fd1498Szrj be used otherwise. */ 21838fd1498Szrj struct stringop_algs 21938fd1498Szrj { 22038fd1498Szrj const enum stringop_alg unknown_size; 22138fd1498Szrj const struct stringop_strategy { 22238fd1498Szrj const int max; 22338fd1498Szrj const enum stringop_alg alg; 22438fd1498Szrj int noalign; 22538fd1498Szrj } size [MAX_STRINGOP_ALGS]; 22638fd1498Szrj }; 22738fd1498Szrj 22838fd1498Szrj /* Define the specific costs for a given cpu */ 22938fd1498Szrj 23038fd1498Szrj struct processor_costs { 23138fd1498Szrj const int add; /* cost of an add instruction */ 23238fd1498Szrj const int lea; /* cost of a lea instruction */ 23338fd1498Szrj const int shift_var; /* variable shift costs */ 23438fd1498Szrj const int shift_const; /* constant shift costs */ 23538fd1498Szrj const int mult_init[5]; /* cost of starting a multiply 23638fd1498Szrj in QImode, HImode, SImode, DImode, TImode*/ 23738fd1498Szrj const int mult_bit; /* cost of multiply per each bit set */ 23838fd1498Szrj const int divide[5]; /* cost of a divide/mod 23938fd1498Szrj in QImode, HImode, SImode, DImode, TImode*/ 24038fd1498Szrj int movsx; /* The cost of movsx operation. */ 24138fd1498Szrj int movzx; /* The cost of movzx operation. */ 24238fd1498Szrj const int large_insn; /* insns larger than this cost more */ 24338fd1498Szrj const int move_ratio; /* The threshold of number of scalar 24438fd1498Szrj memory-to-memory move insns. */ 24538fd1498Szrj const int movzbl_load; /* cost of loading using movzbl */ 24638fd1498Szrj const int int_load[3]; /* cost of loading integer registers 24738fd1498Szrj in QImode, HImode and SImode relative 24838fd1498Szrj to reg-reg move (2). */ 24938fd1498Szrj const int int_store[3]; /* cost of storing integer register 25038fd1498Szrj in QImode, HImode and SImode */ 25138fd1498Szrj const int fp_move; /* cost of reg,reg fld/fst */ 25238fd1498Szrj const int fp_load[3]; /* cost of loading FP register 25338fd1498Szrj in SFmode, DFmode and XFmode */ 25438fd1498Szrj const int fp_store[3]; /* cost of storing FP register 25538fd1498Szrj in SFmode, DFmode and XFmode */ 25638fd1498Szrj const int mmx_move; /* cost of moving MMX register. */ 25738fd1498Szrj const int mmx_load[2]; /* cost of loading MMX register 25838fd1498Szrj in SImode and DImode */ 25938fd1498Szrj const int mmx_store[2]; /* cost of storing MMX register 26038fd1498Szrj in SImode and DImode */ 26138fd1498Szrj const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */ 26238fd1498Szrj zmm_move; 26338fd1498Szrj const int sse_load[5]; /* cost of loading SSE register 26438fd1498Szrj in 32bit, 64bit, 128bit, 256bit and 512bit */ 26538fd1498Szrj const int sse_unaligned_load[5];/* cost of unaligned load. */ 26638fd1498Szrj const int sse_store[5]; /* cost of storing SSE register 26738fd1498Szrj in SImode, DImode and TImode. */ 26838fd1498Szrj const int sse_unaligned_store[5];/* cost of unaligned store. */ 26938fd1498Szrj const int mmxsse_to_integer; /* cost of moving mmxsse register to 27038fd1498Szrj integer. */ 27138fd1498Szrj const int ssemmx_to_integer; /* cost of moving integer to mmxsse register. */ 27238fd1498Szrj const int gather_static, gather_per_elt; /* Cost of gather load is computed 27338fd1498Szrj as static + per_item * nelts. */ 27438fd1498Szrj const int scatter_static, scatter_per_elt; /* Cost of gather store is 27538fd1498Szrj computed as static + per_item * nelts. */ 27638fd1498Szrj const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 27738fd1498Szrj const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 27838fd1498Szrj const int prefetch_block; /* bytes moved to cache for prefetch. */ 27938fd1498Szrj const int simultaneous_prefetches; /* number of parallel prefetch 28038fd1498Szrj operations. */ 28138fd1498Szrj const int branch_cost; /* Default value for BRANCH_COST. */ 28238fd1498Szrj const int fadd; /* cost of FADD and FSUB instructions. */ 28338fd1498Szrj const int fmul; /* cost of FMUL instruction. */ 28438fd1498Szrj const int fdiv; /* cost of FDIV instruction. */ 28538fd1498Szrj const int fabs; /* cost of FABS instruction. */ 28638fd1498Szrj const int fchs; /* cost of FCHS instruction. */ 28738fd1498Szrj const int fsqrt; /* cost of FSQRT instruction. */ 28838fd1498Szrj /* Specify what algorithm 28938fd1498Szrj to use for stringops on unknown size. */ 29038fd1498Szrj const int sse_op; /* cost of cheap SSE instruction. */ 29138fd1498Szrj const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */ 29238fd1498Szrj const int mulss; /* cost of MULSS instructions. */ 29338fd1498Szrj const int mulsd; /* cost of MULSD instructions. */ 29438fd1498Szrj const int fmass; /* cost of FMASS instructions. */ 29538fd1498Szrj const int fmasd; /* cost of FMASD instructions. */ 29638fd1498Szrj const int divss; /* cost of DIVSS instructions. */ 29738fd1498Szrj const int divsd; /* cost of DIVSD instructions. */ 29838fd1498Szrj const int sqrtss; /* cost of SQRTSS instructions. */ 29938fd1498Szrj const int sqrtsd; /* cost of SQRTSD instructions. */ 30038fd1498Szrj const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp; 30138fd1498Szrj /* Specify reassociation width for integer, 30238fd1498Szrj fp, vector integer and vector fp 30338fd1498Szrj operations. Generally should correspond 30438fd1498Szrj to number of instructions executed in 30538fd1498Szrj parallel. See also 30638fd1498Szrj ix86_reassociation_width. */ 30738fd1498Szrj struct stringop_algs *memcpy, *memset; 30838fd1498Szrj const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 30938fd1498Szrj cost model. */ 31038fd1498Szrj const int cond_not_taken_branch_cost;/* Cost of not taken branch for 31138fd1498Szrj vectorizer cost model. */ 31238fd1498Szrj }; 31338fd1498Szrj 31438fd1498Szrj extern const struct processor_costs *ix86_cost; 31538fd1498Szrj extern const struct processor_costs ix86_size_cost; 31638fd1498Szrj 31738fd1498Szrj #define ix86_cur_cost() \ 31838fd1498Szrj (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) 31938fd1498Szrj 32038fd1498Szrj /* Macros used in the machine description to test the flags. */ 32138fd1498Szrj 32238fd1498Szrj /* configure can arrange to change it. */ 32338fd1498Szrj 32438fd1498Szrj #ifndef TARGET_CPU_DEFAULT 32538fd1498Szrj #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC 32638fd1498Szrj #endif 32738fd1498Szrj 32838fd1498Szrj #ifndef TARGET_FPMATH_DEFAULT 32938fd1498Szrj #define TARGET_FPMATH_DEFAULT \ 33038fd1498Szrj (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 33138fd1498Szrj #endif 33238fd1498Szrj 33338fd1498Szrj #ifndef TARGET_FPMATH_DEFAULT_P 33438fd1498Szrj #define TARGET_FPMATH_DEFAULT_P(x) \ 33538fd1498Szrj (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) 33638fd1498Szrj #endif 33738fd1498Szrj 33838fd1498Szrj /* If the i387 is disabled or -miamcu is used , then do not return 33938fd1498Szrj values in it. */ 34038fd1498Szrj #define TARGET_FLOAT_RETURNS_IN_80387 \ 34138fd1498Szrj (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU) 34238fd1498Szrj #define TARGET_FLOAT_RETURNS_IN_80387_P(x) \ 34338fd1498Szrj (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x)) 34438fd1498Szrj 34538fd1498Szrj /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 34638fd1498Szrj compile-time constant. */ 34738fd1498Szrj #ifdef IN_LIBGCC2 34838fd1498Szrj #undef TARGET_64BIT 34938fd1498Szrj #ifdef __x86_64__ 35038fd1498Szrj #define TARGET_64BIT 1 35138fd1498Szrj #else 35238fd1498Szrj #define TARGET_64BIT 0 35338fd1498Szrj #endif 35438fd1498Szrj #else 35538fd1498Szrj #ifndef TARGET_BI_ARCH 35638fd1498Szrj #undef TARGET_64BIT 35738fd1498Szrj #undef TARGET_64BIT_P 35838fd1498Szrj #if TARGET_64BIT_DEFAULT 35938fd1498Szrj #define TARGET_64BIT 1 36038fd1498Szrj #define TARGET_64BIT_P(x) 1 36138fd1498Szrj #else 36238fd1498Szrj #define TARGET_64BIT 0 36338fd1498Szrj #define TARGET_64BIT_P(x) 0 36438fd1498Szrj #endif 36538fd1498Szrj #endif 36638fd1498Szrj #endif 36738fd1498Szrj 36838fd1498Szrj #define HAS_LONG_COND_BRANCH 1 36938fd1498Szrj #define HAS_LONG_UNCOND_BRANCH 1 37038fd1498Szrj 37138fd1498Szrj #define TARGET_386 (ix86_tune == PROCESSOR_I386) 37238fd1498Szrj #define TARGET_486 (ix86_tune == PROCESSOR_I486) 37338fd1498Szrj #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 37438fd1498Szrj #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 37538fd1498Szrj #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 37638fd1498Szrj #define TARGET_K6 (ix86_tune == PROCESSOR_K6) 37738fd1498Szrj #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 37838fd1498Szrj #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 37938fd1498Szrj #define TARGET_K8 (ix86_tune == PROCESSOR_K8) 38038fd1498Szrj #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 38138fd1498Szrj #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 38238fd1498Szrj #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 38338fd1498Szrj #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) 38438fd1498Szrj #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) 38538fd1498Szrj #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) 38638fd1498Szrj #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) 38738fd1498Szrj #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) 38838fd1498Szrj #define TARGET_KNL (ix86_tune == PROCESSOR_KNL) 38938fd1498Szrj #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) 39038fd1498Szrj #define TARGET_SKYLAKE (ix86_tune == PROCESSOR_SKYLAKE) 39138fd1498Szrj #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) 39238fd1498Szrj #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE) 39338fd1498Szrj #define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT) 39438fd1498Szrj #define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER) 39538fd1498Szrj #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) 39638fd1498Szrj #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) 39738fd1498Szrj #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 39838fd1498Szrj #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) 39938fd1498Szrj #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) 40038fd1498Szrj #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) 40138fd1498Szrj #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) 40238fd1498Szrj #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) 40338fd1498Szrj #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) 40438fd1498Szrj #define TARGET_ZNVER1 (ix86_tune == PROCESSOR_ZNVER1) 40538fd1498Szrj 40638fd1498Szrj /* Feature tests against the various tunings. */ 40738fd1498Szrj enum ix86_tune_indices { 40838fd1498Szrj #undef DEF_TUNE 40938fd1498Szrj #define DEF_TUNE(tune, name, selector) tune, 41038fd1498Szrj #include "x86-tune.def" 41138fd1498Szrj #undef DEF_TUNE 41238fd1498Szrj X86_TUNE_LAST 41338fd1498Szrj }; 41438fd1498Szrj 41538fd1498Szrj extern unsigned char ix86_tune_features[X86_TUNE_LAST]; 41638fd1498Szrj 41738fd1498Szrj #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] 41838fd1498Szrj #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] 41938fd1498Szrj #define TARGET_ZERO_EXTEND_WITH_AND \ 42038fd1498Szrj ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] 42138fd1498Szrj #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] 42238fd1498Szrj #define TARGET_BRANCH_PREDICTION_HINTS \ 42338fd1498Szrj ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] 42438fd1498Szrj #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] 42538fd1498Szrj #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] 42638fd1498Szrj #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] 42738fd1498Szrj #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] 42838fd1498Szrj #define TARGET_PARTIAL_FLAG_REG_STALL \ 42938fd1498Szrj ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] 43038fd1498Szrj #define TARGET_LCP_STALL \ 43138fd1498Szrj ix86_tune_features[X86_TUNE_LCP_STALL] 43238fd1498Szrj #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] 43338fd1498Szrj #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] 43438fd1498Szrj #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] 43538fd1498Szrj #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] 43638fd1498Szrj #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] 43738fd1498Szrj #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] 43838fd1498Szrj #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] 43938fd1498Szrj #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] 44038fd1498Szrj #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] 44138fd1498Szrj #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] 44238fd1498Szrj #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] 44338fd1498Szrj #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ 44438fd1498Szrj ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] 44538fd1498Szrj #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] 44638fd1498Szrj #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] 44738fd1498Szrj #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] 44838fd1498Szrj #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] 44938fd1498Szrj #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] 45038fd1498Szrj #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] 45138fd1498Szrj #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] 45238fd1498Szrj #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] 45338fd1498Szrj #define TARGET_INTEGER_DFMODE_MOVES \ 45438fd1498Szrj ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] 45538fd1498Szrj #define TARGET_PARTIAL_REG_DEPENDENCY \ 45638fd1498Szrj ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] 45738fd1498Szrj #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 45838fd1498Szrj ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] 45938fd1498Szrj #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 46038fd1498Szrj ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] 46138fd1498Szrj #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ 46238fd1498Szrj ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] 46338fd1498Szrj #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ 46438fd1498Szrj ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] 46538fd1498Szrj #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] 46638fd1498Szrj #define TARGET_SSE_TYPELESS_STORES \ 46738fd1498Szrj ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] 46838fd1498Szrj #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] 46938fd1498Szrj #define TARGET_MEMORY_MISMATCH_STALL \ 47038fd1498Szrj ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] 47138fd1498Szrj #define TARGET_PROLOGUE_USING_MOVE \ 47238fd1498Szrj ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] 47338fd1498Szrj #define TARGET_EPILOGUE_USING_MOVE \ 47438fd1498Szrj ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] 47538fd1498Szrj #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] 47638fd1498Szrj #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] 47738fd1498Szrj #define TARGET_INTER_UNIT_MOVES_TO_VEC \ 47838fd1498Szrj ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] 47938fd1498Szrj #define TARGET_INTER_UNIT_MOVES_FROM_VEC \ 48038fd1498Szrj ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] 48138fd1498Szrj #define TARGET_INTER_UNIT_CONVERSIONS \ 48238fd1498Szrj ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] 48338fd1498Szrj #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] 48438fd1498Szrj #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] 48538fd1498Szrj #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] 48638fd1498Szrj #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] 48738fd1498Szrj #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] 48838fd1498Szrj #define TARGET_PAD_SHORT_FUNCTION \ 48938fd1498Szrj ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] 49038fd1498Szrj #define TARGET_EXT_80387_CONSTANTS \ 49138fd1498Szrj ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] 49238fd1498Szrj #define TARGET_AVOID_VECTOR_DECODE \ 49338fd1498Szrj ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] 49438fd1498Szrj #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ 49538fd1498Szrj ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] 49638fd1498Szrj #define TARGET_SLOW_IMUL_IMM32_MEM \ 49738fd1498Szrj ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] 49838fd1498Szrj #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] 49938fd1498Szrj #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] 50038fd1498Szrj #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] 50138fd1498Szrj #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] 50238fd1498Szrj #define TARGET_USE_VECTOR_FP_CONVERTS \ 50338fd1498Szrj ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] 50438fd1498Szrj #define TARGET_USE_VECTOR_CONVERTS \ 50538fd1498Szrj ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 50638fd1498Szrj #define TARGET_SLOW_PSHUFB \ 50738fd1498Szrj ix86_tune_features[X86_TUNE_SLOW_PSHUFB] 50838fd1498Szrj #define TARGET_AVOID_4BYTE_PREFIXES \ 50938fd1498Szrj ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] 51038fd1498Szrj #define TARGET_USE_GATHER \ 51138fd1498Szrj ix86_tune_features[X86_TUNE_USE_GATHER] 51238fd1498Szrj #define TARGET_FUSE_CMP_AND_BRANCH_32 \ 51338fd1498Szrj ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] 51438fd1498Szrj #define TARGET_FUSE_CMP_AND_BRANCH_64 \ 51538fd1498Szrj ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] 51638fd1498Szrj #define TARGET_FUSE_CMP_AND_BRANCH \ 51738fd1498Szrj (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ 51838fd1498Szrj : TARGET_FUSE_CMP_AND_BRANCH_32) 51938fd1498Szrj #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ 52038fd1498Szrj ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] 52138fd1498Szrj #define TARGET_FUSE_ALU_AND_BRANCH \ 52238fd1498Szrj ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] 52338fd1498Szrj #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] 52438fd1498Szrj #define TARGET_AVOID_LEA_FOR_ADDR \ 52538fd1498Szrj ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] 52638fd1498Szrj #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ 52738fd1498Szrj ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] 52838fd1498Szrj #define TARGET_AVX128_OPTIMAL \ 52938fd1498Szrj ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] 53038fd1498Szrj #define TARGET_GENERAL_REGS_SSE_SPILL \ 53138fd1498Szrj ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] 53238fd1498Szrj #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ 53338fd1498Szrj ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] 53438fd1498Szrj #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ 53538fd1498Szrj ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] 53638fd1498Szrj #define TARGET_ADJUST_UNROLL \ 53738fd1498Szrj ix86_tune_features[X86_TUNE_ADJUST_UNROLL] 53838fd1498Szrj #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ 53938fd1498Szrj ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] 54038fd1498Szrj #define TARGET_ONE_IF_CONV_INSN \ 54138fd1498Szrj ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] 54238fd1498Szrj #define TARGET_EMIT_VZEROUPPER \ 54338fd1498Szrj ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER] 54438fd1498Szrj 54538fd1498Szrj /* Feature tests against the various architecture variations. */ 54638fd1498Szrj enum ix86_arch_indices { 54738fd1498Szrj X86_ARCH_CMOV, 54838fd1498Szrj X86_ARCH_CMPXCHG, 54938fd1498Szrj X86_ARCH_CMPXCHG8B, 55038fd1498Szrj X86_ARCH_XADD, 55138fd1498Szrj X86_ARCH_BSWAP, 55238fd1498Szrj 55338fd1498Szrj X86_ARCH_LAST 55438fd1498Szrj }; 55538fd1498Szrj 55638fd1498Szrj extern unsigned char ix86_arch_features[X86_ARCH_LAST]; 55738fd1498Szrj 55838fd1498Szrj #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] 55938fd1498Szrj #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] 56038fd1498Szrj #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] 56138fd1498Szrj #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] 56238fd1498Szrj #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] 56338fd1498Szrj 56438fd1498Szrj /* For sane SSE instruction set generation we need fcomi instruction. 56538fd1498Szrj It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic 56638fd1498Szrj expands to a sequence that includes conditional move. */ 56738fd1498Szrj #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) 56838fd1498Szrj 56938fd1498Szrj #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 57038fd1498Szrj 57138fd1498Szrj extern unsigned char x86_prefetch_sse; 57238fd1498Szrj #define TARGET_PREFETCH_SSE x86_prefetch_sse 57338fd1498Szrj 57438fd1498Szrj #define ASSEMBLER_DIALECT (ix86_asm_dialect) 57538fd1498Szrj 57638fd1498Szrj #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 57738fd1498Szrj #define TARGET_MIX_SSE_I387 \ 57838fd1498Szrj ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) 57938fd1498Szrj 58038fd1498Szrj #define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE) 58138fd1498Szrj #define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE) 58238fd1498Szrj #define TARGET_HARD_XF_REGS (TARGET_80387) 58338fd1498Szrj 58438fd1498Szrj #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 58538fd1498Szrj #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 58638fd1498Szrj #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 58738fd1498Szrj #define TARGET_SUN_TLS 0 58838fd1498Szrj 58938fd1498Szrj #ifndef TARGET_64BIT_DEFAULT 59038fd1498Szrj #define TARGET_64BIT_DEFAULT 0 59138fd1498Szrj #endif 59238fd1498Szrj #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 59338fd1498Szrj #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 59438fd1498Szrj #endif 59538fd1498Szrj 59638fd1498Szrj #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) 59738fd1498Szrj #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) 59838fd1498Szrj 59938fd1498Szrj /* Fence to use after loop using storent. */ 60038fd1498Szrj 60138fd1498Szrj extern tree x86_mfence; 60238fd1498Szrj #define FENCE_FOLLOWING_MOVNT x86_mfence 60338fd1498Szrj 60438fd1498Szrj /* Once GDB has been enhanced to deal with functions without frame 60538fd1498Szrj pointers, we can change this to allow for elimination of 60638fd1498Szrj the frame pointer in leaf functions. */ 60738fd1498Szrj #define TARGET_DEFAULT 0 60838fd1498Szrj 60938fd1498Szrj /* Extra bits to force. */ 61038fd1498Szrj #define TARGET_SUBTARGET_DEFAULT 0 61138fd1498Szrj #define TARGET_SUBTARGET_ISA_DEFAULT 0 61238fd1498Szrj 61338fd1498Szrj /* Extra bits to force on w/ 32-bit mode. */ 61438fd1498Szrj #define TARGET_SUBTARGET32_DEFAULT 0 61538fd1498Szrj #define TARGET_SUBTARGET32_ISA_DEFAULT 0 61638fd1498Szrj 61738fd1498Szrj /* Extra bits to force on w/ 64-bit mode. */ 61838fd1498Szrj #define TARGET_SUBTARGET64_DEFAULT 0 61938fd1498Szrj #define TARGET_SUBTARGET64_ISA_DEFAULT 0 62038fd1498Szrj 62138fd1498Szrj /* Replace MACH-O, ifdefs by in-line tests, where possible. 62238fd1498Szrj (a) Macros defined in config/i386/darwin.h */ 62338fd1498Szrj #define TARGET_MACHO 0 62438fd1498Szrj #define TARGET_MACHO_BRANCH_ISLANDS 0 62538fd1498Szrj #define MACHOPIC_ATT_STUB 0 62638fd1498Szrj /* (b) Macros defined in config/darwin.h */ 62738fd1498Szrj #define MACHO_DYNAMIC_NO_PIC_P 0 62838fd1498Szrj #define MACHOPIC_INDIRECT 0 62938fd1498Szrj #define MACHOPIC_PURE 0 63038fd1498Szrj 63138fd1498Szrj /* For the RDOS */ 63238fd1498Szrj #define TARGET_RDOS 0 63338fd1498Szrj 63438fd1498Szrj /* For the Windows 64-bit ABI. */ 63538fd1498Szrj #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 63638fd1498Szrj 63738fd1498Szrj /* For the Windows 32-bit ABI. */ 63838fd1498Szrj #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 63938fd1498Szrj 64038fd1498Szrj /* This is re-defined by cygming.h. */ 64138fd1498Szrj #define TARGET_SEH 0 64238fd1498Szrj 64338fd1498Szrj /* The default abi used by target. */ 64438fd1498Szrj #define DEFAULT_ABI SYSV_ABI 64538fd1498Szrj 64638fd1498Szrj /* The default TLS segment register used by target. */ 64738fd1498Szrj #define DEFAULT_TLS_SEG_REG \ 64838fd1498Szrj (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS) 64938fd1498Szrj 65038fd1498Szrj /* Subtargets may reset this to 1 in order to enable 96-bit long double 65138fd1498Szrj with the rounding mode forced to 53 bits. */ 65238fd1498Szrj #define TARGET_96_ROUND_53_LONG_DOUBLE 0 65338fd1498Szrj 65438fd1498Szrj /* -march=native handling only makes sense with compiler running on 65538fd1498Szrj an x86 or x86_64 chip. If changing this condition, also change 65638fd1498Szrj the condition in driver-i386.c. */ 65738fd1498Szrj #if defined(__i386__) || defined(__x86_64__) 65838fd1498Szrj /* In driver-i386.c. */ 65938fd1498Szrj extern const char *host_detect_local_cpu (int argc, const char **argv); 66038fd1498Szrj #define EXTRA_SPEC_FUNCTIONS \ 66138fd1498Szrj { "local_cpu_detect", host_detect_local_cpu }, 66238fd1498Szrj #define HAVE_LOCAL_CPU_DETECT 66338fd1498Szrj #endif 66438fd1498Szrj 66538fd1498Szrj #if TARGET_64BIT_DEFAULT 66638fd1498Szrj #define OPT_ARCH64 "!m32" 66738fd1498Szrj #define OPT_ARCH32 "m32" 66838fd1498Szrj #else 66938fd1498Szrj #define OPT_ARCH64 "m64|mx32" 67038fd1498Szrj #define OPT_ARCH32 "m64|mx32:;" 67138fd1498Szrj #endif 67238fd1498Szrj 67338fd1498Szrj /* Support for configure-time defaults of some command line options. 67438fd1498Szrj The order here is important so that -march doesn't squash the 67538fd1498Szrj tune or cpu values. */ 67638fd1498Szrj #define OPTION_DEFAULT_SPECS \ 67738fd1498Szrj {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 67838fd1498Szrj {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 67938fd1498Szrj {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 68038fd1498Szrj {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 68138fd1498Szrj {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 68238fd1498Szrj {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 68338fd1498Szrj {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 68438fd1498Szrj {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ 68538fd1498Szrj {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, 68638fd1498Szrj 68738fd1498Szrj /* Specs for the compiler proper */ 68838fd1498Szrj 68938fd1498Szrj #ifndef CC1_CPU_SPEC 69038fd1498Szrj #define CC1_CPU_SPEC_1 "" 69138fd1498Szrj 69238fd1498Szrj #ifndef HAVE_LOCAL_CPU_DETECT 69338fd1498Szrj #define CC1_CPU_SPEC CC1_CPU_SPEC_1 69438fd1498Szrj #else 69538fd1498Szrj #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 69638fd1498Szrj "%{march=native:%>march=native %:local_cpu_detect(arch) \ 69738fd1498Szrj %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ 69838fd1498Szrj %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" 69938fd1498Szrj #endif 70038fd1498Szrj #endif 70138fd1498Szrj 70238fd1498Szrj /* Target CPU builtins. */ 70338fd1498Szrj #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () 70438fd1498Szrj 70538fd1498Szrj /* Target Pragmas. */ 70638fd1498Szrj #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () 70738fd1498Szrj 70838fd1498Szrj #ifndef CC1_SPEC 70938fd1498Szrj #define CC1_SPEC "%(cc1_cpu) " 71038fd1498Szrj #endif 71138fd1498Szrj 71238fd1498Szrj /* This macro defines names of additional specifications to put in the 71338fd1498Szrj specs that can be used in various specifications like CC1_SPEC. Its 71438fd1498Szrj definition is an initializer with a subgrouping for each command option. 71538fd1498Szrj 71638fd1498Szrj Each subgrouping contains a string constant, that defines the 71738fd1498Szrj specification name, and a string constant that used by the GCC driver 71838fd1498Szrj program. 71938fd1498Szrj 72038fd1498Szrj Do not define this macro if it does not need to do anything. */ 72138fd1498Szrj 72238fd1498Szrj #ifndef SUBTARGET_EXTRA_SPECS 72338fd1498Szrj #define SUBTARGET_EXTRA_SPECS 72438fd1498Szrj #endif 72538fd1498Szrj 72638fd1498Szrj #define EXTRA_SPECS \ 72738fd1498Szrj { "cc1_cpu", CC1_CPU_SPEC }, \ 72838fd1498Szrj SUBTARGET_EXTRA_SPECS 72938fd1498Szrj 73038fd1498Szrj 73138fd1498Szrj /* Whether to allow x87 floating-point arithmetic on MODE (one of 73238fd1498Szrj SFmode, DFmode and XFmode) in the current excess precision 73338fd1498Szrj configuration. */ 73438fd1498Szrj #define X87_ENABLE_ARITH(MODE) \ 73538fd1498Szrj (flag_unsafe_math_optimizations \ 73638fd1498Szrj || flag_excess_precision == EXCESS_PRECISION_FAST \ 73738fd1498Szrj || (MODE) == XFmode) 73838fd1498Szrj 73938fd1498Szrj /* Likewise, whether to allow direct conversions from integer mode 74038fd1498Szrj IMODE (HImode, SImode or DImode) to MODE. */ 74138fd1498Szrj #define X87_ENABLE_FLOAT(MODE, IMODE) \ 74238fd1498Szrj (flag_unsafe_math_optimizations \ 74338fd1498Szrj || flag_excess_precision == EXCESS_PRECISION_FAST \ 74438fd1498Szrj || (MODE) == XFmode \ 74538fd1498Szrj || ((MODE) == DFmode && (IMODE) == SImode) \ 74638fd1498Szrj || (IMODE) == HImode) 74738fd1498Szrj 74838fd1498Szrj /* target machine storage layout */ 74938fd1498Szrj 75038fd1498Szrj #define SHORT_TYPE_SIZE 16 75138fd1498Szrj #define INT_TYPE_SIZE 32 75238fd1498Szrj #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 75338fd1498Szrj #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 75438fd1498Szrj #define LONG_LONG_TYPE_SIZE 64 75538fd1498Szrj #define FLOAT_TYPE_SIZE 32 75638fd1498Szrj #define DOUBLE_TYPE_SIZE 64 75738fd1498Szrj #define LONG_DOUBLE_TYPE_SIZE \ 75838fd1498Szrj (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) 75938fd1498Szrj 76038fd1498Szrj #define WIDEST_HARDWARE_FP_SIZE 80 76138fd1498Szrj 76238fd1498Szrj #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 76338fd1498Szrj #define MAX_BITS_PER_WORD 64 76438fd1498Szrj #else 76538fd1498Szrj #define MAX_BITS_PER_WORD 32 76638fd1498Szrj #endif 76738fd1498Szrj 76838fd1498Szrj /* Define this if most significant byte of a word is the lowest numbered. */ 76938fd1498Szrj /* That is true on the 80386. */ 77038fd1498Szrj 77138fd1498Szrj #define BITS_BIG_ENDIAN 0 77238fd1498Szrj 77338fd1498Szrj /* Define this if most significant byte of a word is the lowest numbered. */ 77438fd1498Szrj /* That is not true on the 80386. */ 77538fd1498Szrj #define BYTES_BIG_ENDIAN 0 77638fd1498Szrj 77738fd1498Szrj /* Define this if most significant word of a multiword number is the lowest 77838fd1498Szrj numbered. */ 77938fd1498Szrj /* Not true for 80386 */ 78038fd1498Szrj #define WORDS_BIG_ENDIAN 0 78138fd1498Szrj 78238fd1498Szrj /* Width of a word, in units (bytes). */ 78338fd1498Szrj #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 78438fd1498Szrj 78538fd1498Szrj #ifndef IN_LIBGCC2 78638fd1498Szrj #define MIN_UNITS_PER_WORD 4 78738fd1498Szrj #endif 78838fd1498Szrj 78938fd1498Szrj /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 79038fd1498Szrj #define PARM_BOUNDARY BITS_PER_WORD 79138fd1498Szrj 79238fd1498Szrj /* Boundary (in *bits*) on which stack pointer should be aligned. */ 793*58e805e6Szrj #define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD) 79438fd1498Szrj 79538fd1498Szrj /* Stack boundary of the main function guaranteed by OS. */ 79638fd1498Szrj #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 79738fd1498Szrj 79838fd1498Szrj /* Minimum stack boundary. */ 79938fd1498Szrj #define MIN_STACK_BOUNDARY BITS_PER_WORD 80038fd1498Szrj 80138fd1498Szrj /* Boundary (in *bits*) on which the stack pointer prefers to be 80238fd1498Szrj aligned; the compiler cannot rely on having this alignment. */ 80338fd1498Szrj #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 80438fd1498Szrj 80538fd1498Szrj /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for 80638fd1498Szrj both 32bit and 64bit, to support codes that need 128 bit stack 80738fd1498Szrj alignment for SSE instructions, but can't realign the stack. */ 80838fd1498Szrj #define PREFERRED_STACK_BOUNDARY_DEFAULT \ 80938fd1498Szrj (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128) 81038fd1498Szrj 81138fd1498Szrj /* 1 if -mstackrealign should be turned on by default. It will 81238fd1498Szrj generate an alternate prologue and epilogue that realigns the 81338fd1498Szrj runtime stack if nessary. This supports mixing codes that keep a 81438fd1498Szrj 4-byte aligned stack, as specified by i386 psABI, with codes that 81538fd1498Szrj need a 16-byte aligned stack, as required by SSE instructions. */ 81638fd1498Szrj #define STACK_REALIGN_DEFAULT 0 81738fd1498Szrj 81838fd1498Szrj /* Boundary (in *bits*) on which the incoming stack is aligned. */ 81938fd1498Szrj #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary 82038fd1498Szrj 82138fd1498Szrj /* According to Windows x64 software convention, the maximum stack allocatable 82238fd1498Szrj in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of 82338fd1498Szrj instructions allowed to adjust the stack pointer in the epilog, forcing the 82438fd1498Szrj use of frame pointer for frames larger than 2 GB. This theorical limit 82538fd1498Szrj is reduced by 256, an over-estimated upper bound for the stack use by the 82638fd1498Szrj prologue. 82738fd1498Szrj We define only one threshold for both the prolog and the epilog. When the 82838fd1498Szrj frame size is larger than this threshold, we allocate the area to save SSE 82938fd1498Szrj regs, then save them, and then allocate the remaining. There is no SEH 83038fd1498Szrj unwind info for this later allocation. */ 83138fd1498Szrj #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) 83238fd1498Szrj 83338fd1498Szrj /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is 83438fd1498Szrj mandatory for the 64-bit ABI, and may or may not be true for other 83538fd1498Szrj operating systems. */ 83638fd1498Szrj #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT 83738fd1498Szrj 83838fd1498Szrj /* Minimum allocation boundary for the code of a function. */ 83938fd1498Szrj #define FUNCTION_BOUNDARY 8 84038fd1498Szrj 84138fd1498Szrj /* C++ stores the virtual bit in the lowest bit of function pointers. */ 84238fd1498Szrj #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 84338fd1498Szrj 84438fd1498Szrj /* Minimum size in bits of the largest boundary to which any 84538fd1498Szrj and all fundamental data types supported by the hardware 84638fd1498Szrj might need to be aligned. No data type wants to be aligned 84738fd1498Szrj rounder than this. 84838fd1498Szrj 84938fd1498Szrj Pentium+ prefers DFmode values to be aligned to 64 bit boundary 85038fd1498Szrj and Pentium Pro XFmode values at 128 bit boundaries. 85138fd1498Szrj 85238fd1498Szrj When increasing the maximum, also update 85338fd1498Szrj TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ 85438fd1498Szrj 85538fd1498Szrj #define BIGGEST_ALIGNMENT \ 85638fd1498Szrj (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))) 85738fd1498Szrj 85838fd1498Szrj /* Maximum stack alignment. */ 85938fd1498Szrj #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT 86038fd1498Szrj 86138fd1498Szrj /* Alignment value for attribute ((aligned)). It is a constant since 86238fd1498Szrj it is the part of the ABI. We shouldn't change it with -mavx. */ 86338fd1498Szrj #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128) 86438fd1498Szrj 86538fd1498Szrj /* Decide whether a variable of mode MODE should be 128 bit aligned. */ 86638fd1498Szrj #define ALIGN_MODE_128(MODE) \ 86738fd1498Szrj ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 86838fd1498Szrj 86938fd1498Szrj /* The published ABIs say that doubles should be aligned on word 87038fd1498Szrj boundaries, so lower the alignment for structure fields unless 87138fd1498Szrj -malign-double is set. */ 87238fd1498Szrj 87338fd1498Szrj /* ??? Blah -- this macro is used directly by libobjc. Since it 87438fd1498Szrj supports no vector modes, cut out the complexity and fall back 87538fd1498Szrj on BIGGEST_FIELD_ALIGNMENT. */ 87638fd1498Szrj #ifdef IN_TARGET_LIBS 87738fd1498Szrj #ifdef __x86_64__ 87838fd1498Szrj #define BIGGEST_FIELD_ALIGNMENT 128 87938fd1498Szrj #else 88038fd1498Szrj #define BIGGEST_FIELD_ALIGNMENT 32 88138fd1498Szrj #endif 88238fd1498Szrj #else 88338fd1498Szrj #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ 88438fd1498Szrj x86_field_alignment ((TYPE), (COMPUTED)) 88538fd1498Szrj #endif 88638fd1498Szrj 88738fd1498Szrj /* If defined, a C expression to compute the alignment for a static 88838fd1498Szrj variable. TYPE is the data type, and ALIGN is the alignment that 88938fd1498Szrj the object would ordinarily have. The value of this macro is used 89038fd1498Szrj instead of that alignment to align the object. 89138fd1498Szrj 89238fd1498Szrj If this macro is not defined, then ALIGN is used. 89338fd1498Szrj 89438fd1498Szrj One use of this macro is to increase alignment of medium-size 89538fd1498Szrj data to make it all fit in fewer cache lines. Another is to 89638fd1498Szrj cause character arrays to be word-aligned so that `strcpy' calls 89738fd1498Szrj that copy constants to character arrays can be done inline. */ 89838fd1498Szrj 89938fd1498Szrj #define DATA_ALIGNMENT(TYPE, ALIGN) \ 90038fd1498Szrj ix86_data_alignment ((TYPE), (ALIGN), true) 90138fd1498Szrj 90238fd1498Szrj /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates 90338fd1498Szrj some alignment increase, instead of optimization only purposes. E.g. 90438fd1498Szrj AMD x86-64 psABI says that variables with array type larger than 15 bytes 90538fd1498Szrj must be aligned to 16 byte boundaries. 90638fd1498Szrj 90738fd1498Szrj If this macro is not defined, then ALIGN is used. */ 90838fd1498Szrj 90938fd1498Szrj #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 91038fd1498Szrj ix86_data_alignment ((TYPE), (ALIGN), false) 91138fd1498Szrj 91238fd1498Szrj /* If defined, a C expression to compute the alignment for a local 91338fd1498Szrj variable. TYPE is the data type, and ALIGN is the alignment that 91438fd1498Szrj the object would ordinarily have. The value of this macro is used 91538fd1498Szrj instead of that alignment to align the object. 91638fd1498Szrj 91738fd1498Szrj If this macro is not defined, then ALIGN is used. 91838fd1498Szrj 91938fd1498Szrj One use of this macro is to increase alignment of medium-size 92038fd1498Szrj data to make it all fit in fewer cache lines. */ 92138fd1498Szrj 92238fd1498Szrj #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 92338fd1498Szrj ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) 92438fd1498Szrj 92538fd1498Szrj /* If defined, a C expression to compute the alignment for stack slot. 92638fd1498Szrj TYPE is the data type, MODE is the widest mode available, and ALIGN 92738fd1498Szrj is the alignment that the slot would ordinarily have. The value of 92838fd1498Szrj this macro is used instead of that alignment to align the slot. 92938fd1498Szrj 93038fd1498Szrj If this macro is not defined, then ALIGN is used when TYPE is NULL, 93138fd1498Szrj Otherwise, LOCAL_ALIGNMENT will be used. 93238fd1498Szrj 93338fd1498Szrj One use of this macro is to set alignment of stack slot to the 93438fd1498Szrj maximum alignment of all possible modes which the slot may have. */ 93538fd1498Szrj 93638fd1498Szrj #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ 93738fd1498Szrj ix86_local_alignment ((TYPE), (MODE), (ALIGN)) 93838fd1498Szrj 93938fd1498Szrj /* If defined, a C expression to compute the alignment for a local 94038fd1498Szrj variable DECL. 94138fd1498Szrj 94238fd1498Szrj If this macro is not defined, then 94338fd1498Szrj LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. 94438fd1498Szrj 94538fd1498Szrj One use of this macro is to increase alignment of medium-size 94638fd1498Szrj data to make it all fit in fewer cache lines. */ 94738fd1498Szrj 94838fd1498Szrj #define LOCAL_DECL_ALIGNMENT(DECL) \ 94938fd1498Szrj ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 95038fd1498Szrj 95138fd1498Szrj /* If defined, a C expression to compute the minimum required alignment 95238fd1498Szrj for dynamic stack realignment purposes for EXP (a TYPE or DECL), 95338fd1498Szrj MODE, assuming normal alignment ALIGN. 95438fd1498Szrj 95538fd1498Szrj If this macro is not defined, then (ALIGN) will be used. */ 95638fd1498Szrj 95738fd1498Szrj #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ 95838fd1498Szrj ix86_minimum_alignment ((EXP), (MODE), (ALIGN)) 95938fd1498Szrj 96038fd1498Szrj 96138fd1498Szrj /* Set this nonzero if move instructions will actually fail to work 96238fd1498Szrj when given unaligned data. */ 96338fd1498Szrj #define STRICT_ALIGNMENT 0 96438fd1498Szrj 96538fd1498Szrj /* If bit field type is int, don't let it cross an int, 96638fd1498Szrj and give entire struct the alignment of an int. */ 96738fd1498Szrj /* Required on the 386 since it doesn't have bit-field insns. */ 96838fd1498Szrj #define PCC_BITFIELD_TYPE_MATTERS 1 96938fd1498Szrj 97038fd1498Szrj /* Standard register usage. */ 97138fd1498Szrj 97238fd1498Szrj /* This processor has special stack-like registers. See reg-stack.c 97338fd1498Szrj for details. */ 97438fd1498Szrj 97538fd1498Szrj #define STACK_REGS 97638fd1498Szrj 97738fd1498Szrj #define IS_STACK_MODE(MODE) \ 97838fd1498Szrj (X87_FLOAT_MODE_P (MODE) \ 97938fd1498Szrj && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ 98038fd1498Szrj || TARGET_MIX_SSE_I387)) 98138fd1498Szrj 98238fd1498Szrj /* Number of actual hardware registers. 98338fd1498Szrj The hardware registers are assigned numbers for the compiler 98438fd1498Szrj from 0 to just below FIRST_PSEUDO_REGISTER. 98538fd1498Szrj All registers that the compiler knows about must be given numbers, 98638fd1498Szrj even those that are not normally considered general registers. 98738fd1498Szrj 98838fd1498Szrj In the 80386 we give the 8 general purpose registers the numbers 0-7. 98938fd1498Szrj We number the floating point registers 8-15. 99038fd1498Szrj Note that registers 0-7 can be accessed as a short or int, 99138fd1498Szrj while only 0-3 may be used with byte `mov' instructions. 99238fd1498Szrj 99338fd1498Szrj Reg 16 does not correspond to any hardware register, but instead 99438fd1498Szrj appears in the RTL as an argument pointer prior to reload, and is 99538fd1498Szrj eliminated during reloading in favor of either the stack or frame 99638fd1498Szrj pointer. */ 99738fd1498Szrj 99838fd1498Szrj #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG 99938fd1498Szrj 100038fd1498Szrj /* Number of hardware registers that go into the DWARF-2 unwind info. 100138fd1498Szrj If not defined, equals FIRST_PSEUDO_REGISTER. */ 100238fd1498Szrj 100338fd1498Szrj #define DWARF_FRAME_REGISTERS 17 100438fd1498Szrj 100538fd1498Szrj /* 1 for registers that have pervasive standard uses 100638fd1498Szrj and are not available for the register allocator. 100738fd1498Szrj On the 80386, the stack pointer is such, as is the arg pointer. 100838fd1498Szrj 100938fd1498Szrj REX registers are disabled for 32bit targets in 101038fd1498Szrj TARGET_CONDITIONAL_REGISTER_USAGE. */ 101138fd1498Szrj 101238fd1498Szrj #define FIXED_REGISTERS \ 101338fd1498Szrj /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 101438fd1498Szrj { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 101538fd1498Szrj /*arg,flags,fpsr,fpcr,frame*/ \ 101638fd1498Szrj 1, 1, 1, 1, 1, \ 101738fd1498Szrj /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 101838fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 101938fd1498Szrj /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 102038fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 102138fd1498Szrj /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 102238fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 102338fd1498Szrj /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 102438fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 102538fd1498Szrj /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 102638fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 102738fd1498Szrj /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 102838fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 102938fd1498Szrj /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 103038fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 103138fd1498Szrj /* b0, b1, b2, b3*/ \ 103238fd1498Szrj 0, 0, 0, 0 } 103338fd1498Szrj 103438fd1498Szrj /* 1 for registers not available across function calls. 103538fd1498Szrj These must include the FIXED_REGISTERS and also any 103638fd1498Szrj registers that can be used without being saved. 103738fd1498Szrj The latter must include the registers where values are returned 103838fd1498Szrj and the register where structure-value addresses are passed. 103938fd1498Szrj Aside from that, you can include as many other registers as you like. 104038fd1498Szrj 104138fd1498Szrj Value is set to 1 if the register is call used unconditionally. 104238fd1498Szrj Bit one is set if the register is call used on TARGET_32BIT ABI. 104338fd1498Szrj Bit two is set if the register is call used on TARGET_64BIT ABI. 104438fd1498Szrj Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. 104538fd1498Szrj 104638fd1498Szrj Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ 104738fd1498Szrj 104838fd1498Szrj #define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \ 104938fd1498Szrj ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1)) 105038fd1498Szrj 105138fd1498Szrj #define CALL_USED_REGISTERS \ 105238fd1498Szrj /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 105338fd1498Szrj { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 105438fd1498Szrj /*arg,flags,fpsr,fpcr,frame*/ \ 105538fd1498Szrj 1, 1, 1, 1, 1, \ 105638fd1498Szrj /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 105738fd1498Szrj 1, 1, 1, 1, 1, 1, 6, 6, \ 105838fd1498Szrj /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 105938fd1498Szrj 1, 1, 1, 1, 1, 1, 1, 1, \ 106038fd1498Szrj /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 106138fd1498Szrj 1, 1, 1, 1, 2, 2, 2, 2, \ 106238fd1498Szrj /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 106338fd1498Szrj 6, 6, 6, 6, 6, 6, 6, 6, \ 106438fd1498Szrj /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 106538fd1498Szrj 6, 6, 6, 6, 6, 6, 6, 6, \ 106638fd1498Szrj /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 106738fd1498Szrj 6, 6, 6, 6, 6, 6, 6, 6, \ 106838fd1498Szrj /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 106938fd1498Szrj 1, 1, 1, 1, 1, 1, 1, 1, \ 107038fd1498Szrj /* b0, b1, b2, b3*/ \ 107138fd1498Szrj 1, 1, 1, 1 } 107238fd1498Szrj 107338fd1498Szrj /* Order in which to allocate registers. Each register must be 107438fd1498Szrj listed once, even those in FIXED_REGISTERS. List frame pointer 107538fd1498Szrj late and fixed registers last. Note that, in general, we prefer 107638fd1498Szrj registers listed in CALL_USED_REGISTERS, keeping the others 107738fd1498Szrj available for storage of persistent values. 107838fd1498Szrj 107938fd1498Szrj The ADJUST_REG_ALLOC_ORDER actually overwrite the order, 108038fd1498Szrj so this is just empty initializer for array. */ 108138fd1498Szrj 108238fd1498Szrj #define REG_ALLOC_ORDER \ 108338fd1498Szrj { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 108438fd1498Szrj 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 108538fd1498Szrj 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 108638fd1498Szrj 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ 108738fd1498Szrj 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \ 108838fd1498Szrj 78, 79, 80 } 108938fd1498Szrj 109038fd1498Szrj /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 109138fd1498Szrj to be rearranged based on a particular function. When using sse math, 109238fd1498Szrj we want to allocate SSE before x87 registers and vice versa. */ 109338fd1498Szrj 109438fd1498Szrj #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () 109538fd1498Szrj 109638fd1498Szrj 109738fd1498Szrj #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 109838fd1498Szrj 109938fd1498Szrj #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 110038fd1498Szrj (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \ 110138fd1498Szrj && GENERAL_REGNO_P (REGNO) \ 110238fd1498Szrj && ((MODE) == XFmode || (MODE) == XCmode)) 110338fd1498Szrj 110438fd1498Szrj #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 110538fd1498Szrj 110638fd1498Szrj #define VALID_AVX256_REG_MODE(MODE) \ 110738fd1498Szrj ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 110838fd1498Szrj || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ 110938fd1498Szrj || (MODE) == V4DFmode) 111038fd1498Szrj 111138fd1498Szrj #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ 111238fd1498Szrj (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) 111338fd1498Szrj 111438fd1498Szrj #define VALID_AVX512F_SCALAR_MODE(MODE) \ 111538fd1498Szrj ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ 111638fd1498Szrj || (MODE) == SFmode) 111738fd1498Szrj 111838fd1498Szrj #define VALID_AVX512F_REG_MODE(MODE) \ 111938fd1498Szrj ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ 112038fd1498Szrj || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ 112138fd1498Szrj || (MODE) == V4TImode) 112238fd1498Szrj 112338fd1498Szrj #define VALID_AVX512F_REG_OR_XI_MODE(MODE) \ 112438fd1498Szrj (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode) 112538fd1498Szrj 112638fd1498Szrj #define VALID_AVX512VL_128_REG_MODE(MODE) \ 112738fd1498Szrj ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ 112838fd1498Szrj || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \ 112938fd1498Szrj || (MODE) == TFmode || (MODE) == V1TImode) 113038fd1498Szrj 113138fd1498Szrj #define VALID_SSE2_REG_MODE(MODE) \ 113238fd1498Szrj ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 113338fd1498Szrj || (MODE) == V2DImode || (MODE) == DFmode) 113438fd1498Szrj 113538fd1498Szrj #define VALID_SSE_REG_MODE(MODE) \ 113638fd1498Szrj ((MODE) == V1TImode || (MODE) == TImode \ 113738fd1498Szrj || (MODE) == V4SFmode || (MODE) == V4SImode \ 113838fd1498Szrj || (MODE) == SFmode || (MODE) == TFmode) 113938fd1498Szrj 114038fd1498Szrj #define VALID_MMX_REG_MODE_3DNOW(MODE) \ 114138fd1498Szrj ((MODE) == V2SFmode || (MODE) == SFmode) 114238fd1498Szrj 114338fd1498Szrj #define VALID_MMX_REG_MODE(MODE) \ 114438fd1498Szrj ((MODE == V1DImode) || (MODE) == DImode \ 114538fd1498Szrj || (MODE) == V2SImode || (MODE) == SImode \ 114638fd1498Szrj || (MODE) == V4HImode || (MODE) == V8QImode) 114738fd1498Szrj 114838fd1498Szrj #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) 114938fd1498Szrj 115038fd1498Szrj #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) 115138fd1498Szrj 115238fd1498Szrj #define VALID_BND_REG_MODE(MODE) \ 115338fd1498Szrj (TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode) 115438fd1498Szrj 115538fd1498Szrj #define VALID_DFP_MODE_P(MODE) \ 115638fd1498Szrj ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 115738fd1498Szrj 115838fd1498Szrj #define VALID_FP_MODE_P(MODE) \ 115938fd1498Szrj ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 116038fd1498Szrj || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 116138fd1498Szrj 116238fd1498Szrj #define VALID_INT_MODE_P(MODE) \ 116338fd1498Szrj ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 116438fd1498Szrj || (MODE) == DImode \ 116538fd1498Szrj || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 116638fd1498Szrj || (MODE) == CDImode \ 116738fd1498Szrj || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 116838fd1498Szrj || (MODE) == TFmode || (MODE) == TCmode))) 116938fd1498Szrj 117038fd1498Szrj /* Return true for modes passed in SSE registers. */ 117138fd1498Szrj #define SSE_REG_MODE_P(MODE) \ 117238fd1498Szrj ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ 117338fd1498Szrj || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ 117438fd1498Szrj || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 117538fd1498Szrj || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 117638fd1498Szrj || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ 117738fd1498Szrj || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ 117838fd1498Szrj || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ 117938fd1498Szrj || (MODE) == V16SFmode) 118038fd1498Szrj 118138fd1498Szrj #define X87_FLOAT_MODE_P(MODE) \ 118238fd1498Szrj (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) 118338fd1498Szrj 118438fd1498Szrj #define SSE_FLOAT_MODE_P(MODE) \ 118538fd1498Szrj ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 118638fd1498Szrj 118738fd1498Szrj #define FMA4_VEC_FLOAT_MODE_P(MODE) \ 118838fd1498Szrj (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 118938fd1498Szrj || (MODE) == V8SFmode || (MODE) == V4DFmode)) 119038fd1498Szrj 119138fd1498Szrj /* It is possible to write patterns to move flags; but until someone 119238fd1498Szrj does it, */ 119338fd1498Szrj #define AVOID_CCMODE_COPIES 119438fd1498Szrj 119538fd1498Szrj /* Specify the modes required to caller save a given hard regno. 119638fd1498Szrj We do this on i386 to prevent flags from being saved at all. 119738fd1498Szrj 119838fd1498Szrj Kill any attempts to combine saving of modes. */ 119938fd1498Szrj 120038fd1498Szrj #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 120138fd1498Szrj (CC_REGNO_P (REGNO) ? VOIDmode \ 120238fd1498Szrj : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 120338fd1498Szrj : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ 120438fd1498Szrj : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \ 120538fd1498Szrj && TARGET_PARTIAL_REG_STALL) \ 120638fd1498Szrj || MASK_REGNO_P (REGNO)) ? SImode \ 120738fd1498Szrj : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \ 120838fd1498Szrj || MASK_REGNO_P (REGNO)) ? SImode \ 120938fd1498Szrj : (MODE)) 121038fd1498Szrj 121138fd1498Szrj /* Specify the registers used for certain standard purposes. 121238fd1498Szrj The values of these macros are register numbers. */ 121338fd1498Szrj 121438fd1498Szrj /* on the 386 the pc register is %eip, and is not usable as a general 121538fd1498Szrj register. The ordinary mov instructions won't work */ 121638fd1498Szrj /* #define PC_REGNUM */ 121738fd1498Szrj 121838fd1498Szrj /* Base register for access to arguments of the function. */ 121938fd1498Szrj #define ARG_POINTER_REGNUM ARGP_REG 122038fd1498Szrj 122138fd1498Szrj /* Register to use for pushing function arguments. */ 122238fd1498Szrj #define STACK_POINTER_REGNUM SP_REG 122338fd1498Szrj 122438fd1498Szrj /* Base register for access to local variables of the function. */ 122538fd1498Szrj #define FRAME_POINTER_REGNUM FRAME_REG 122638fd1498Szrj #define HARD_FRAME_POINTER_REGNUM BP_REG 122738fd1498Szrj 122838fd1498Szrj #define FIRST_INT_REG AX_REG 122938fd1498Szrj #define LAST_INT_REG SP_REG 123038fd1498Szrj 123138fd1498Szrj #define FIRST_QI_REG AX_REG 123238fd1498Szrj #define LAST_QI_REG BX_REG 123338fd1498Szrj 123438fd1498Szrj /* First & last stack-like regs */ 123538fd1498Szrj #define FIRST_STACK_REG ST0_REG 123638fd1498Szrj #define LAST_STACK_REG ST7_REG 123738fd1498Szrj 123838fd1498Szrj #define FIRST_SSE_REG XMM0_REG 123938fd1498Szrj #define LAST_SSE_REG XMM7_REG 124038fd1498Szrj 124138fd1498Szrj #define FIRST_MMX_REG MM0_REG 124238fd1498Szrj #define LAST_MMX_REG MM7_REG 124338fd1498Szrj 124438fd1498Szrj #define FIRST_REX_INT_REG R8_REG 124538fd1498Szrj #define LAST_REX_INT_REG R15_REG 124638fd1498Szrj 124738fd1498Szrj #define FIRST_REX_SSE_REG XMM8_REG 124838fd1498Szrj #define LAST_REX_SSE_REG XMM15_REG 124938fd1498Szrj 125038fd1498Szrj #define FIRST_EXT_REX_SSE_REG XMM16_REG 125138fd1498Szrj #define LAST_EXT_REX_SSE_REG XMM31_REG 125238fd1498Szrj 125338fd1498Szrj #define FIRST_MASK_REG MASK0_REG 125438fd1498Szrj #define LAST_MASK_REG MASK7_REG 125538fd1498Szrj 125638fd1498Szrj #define FIRST_BND_REG BND0_REG 125738fd1498Szrj #define LAST_BND_REG BND3_REG 125838fd1498Szrj 125938fd1498Szrj /* Override this in other tm.h files to cope with various OS lossage 126038fd1498Szrj requiring a frame pointer. */ 126138fd1498Szrj #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 126238fd1498Szrj #define SUBTARGET_FRAME_POINTER_REQUIRED 0 126338fd1498Szrj #endif 126438fd1498Szrj 126538fd1498Szrj /* Make sure we can access arbitrary call frames. */ 126638fd1498Szrj #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 126738fd1498Szrj 126838fd1498Szrj /* Register to hold the addressing base for position independent 126938fd1498Szrj code access to data items. We don't use PIC pointer for 64bit 127038fd1498Szrj mode. Define the regnum to dummy value to prevent gcc from 127138fd1498Szrj pessimizing code dealing with EBX. 127238fd1498Szrj 127338fd1498Szrj To avoid clobbering a call-saved register unnecessarily, we renumber 127438fd1498Szrj the pic register when possible. The change is visible after the 127538fd1498Szrj prologue has been emitted. */ 127638fd1498Szrj 127738fd1498Szrj #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) 127838fd1498Szrj 127938fd1498Szrj #define PIC_OFFSET_TABLE_REGNUM \ 128038fd1498Szrj (ix86_use_pseudo_pic_reg () \ 128138fd1498Szrj ? (pic_offset_table_rtx \ 128238fd1498Szrj ? INVALID_REGNUM \ 128338fd1498Szrj : REAL_PIC_OFFSET_TABLE_REGNUM) \ 128438fd1498Szrj : INVALID_REGNUM) 128538fd1498Szrj 128638fd1498Szrj #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 128738fd1498Szrj 128838fd1498Szrj /* This is overridden by <cygwin.h>. */ 128938fd1498Szrj #define MS_AGGREGATE_RETURN 0 129038fd1498Szrj 129138fd1498Szrj #define KEEP_AGGREGATE_RETURN_POINTER 0 129238fd1498Szrj 129338fd1498Szrj /* Define the classes of registers for register constraints in the 129438fd1498Szrj machine description. Also define ranges of constants. 129538fd1498Szrj 129638fd1498Szrj One of the classes must always be named ALL_REGS and include all hard regs. 129738fd1498Szrj If there is more than one class, another class must be named NO_REGS 129838fd1498Szrj and contain no registers. 129938fd1498Szrj 130038fd1498Szrj The name GENERAL_REGS must be the name of a class (or an alias for 130138fd1498Szrj another name such as ALL_REGS). This is the class of registers 130238fd1498Szrj that is allowed by "g" or "r" in a register constraint. 130338fd1498Szrj Also, registers outside this class are allocated only when 130438fd1498Szrj instructions express preferences for them. 130538fd1498Szrj 130638fd1498Szrj The classes must be numbered in nondecreasing order; that is, 130738fd1498Szrj a larger-numbered class must never be contained completely 130838fd1498Szrj in a smaller-numbered class. This is why CLOBBERED_REGS class 130938fd1498Szrj is listed early, even though in 64-bit mode it contains more 131038fd1498Szrj registers than just %eax, %ecx, %edx. 131138fd1498Szrj 131238fd1498Szrj For any two classes, it is very desirable that there be another 131338fd1498Szrj class that represents their union. 131438fd1498Szrj 131538fd1498Szrj It might seem that class BREG is unnecessary, since no useful 386 131638fd1498Szrj opcode needs reg %ebx. But some systems pass args to the OS in ebx, 131738fd1498Szrj and the "b" register constraint is useful in asms for syscalls. 131838fd1498Szrj 131938fd1498Szrj The flags, fpsr and fpcr registers are in no class. */ 132038fd1498Szrj 132138fd1498Szrj enum reg_class 132238fd1498Szrj { 132338fd1498Szrj NO_REGS, 132438fd1498Szrj AREG, DREG, CREG, BREG, SIREG, DIREG, 132538fd1498Szrj AD_REGS, /* %eax/%edx for DImode */ 132638fd1498Szrj CLOBBERED_REGS, /* call-clobbered integer registers */ 132738fd1498Szrj Q_REGS, /* %eax %ebx %ecx %edx */ 132838fd1498Szrj NON_Q_REGS, /* %esi %edi %ebp %esp */ 132938fd1498Szrj TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */ 133038fd1498Szrj INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 133138fd1498Szrj LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 133238fd1498Szrj GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp 133338fd1498Szrj %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ 133438fd1498Szrj FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 133538fd1498Szrj FLOAT_REGS, 133638fd1498Szrj SSE_FIRST_REG, 133738fd1498Szrj NO_REX_SSE_REGS, 133838fd1498Szrj SSE_REGS, 133938fd1498Szrj EVEX_SSE_REGS, 134038fd1498Szrj BND_REGS, 134138fd1498Szrj ALL_SSE_REGS, 134238fd1498Szrj MMX_REGS, 134338fd1498Szrj FP_TOP_SSE_REGS, 134438fd1498Szrj FP_SECOND_SSE_REGS, 134538fd1498Szrj FLOAT_SSE_REGS, 134638fd1498Szrj FLOAT_INT_REGS, 134738fd1498Szrj INT_SSE_REGS, 134838fd1498Szrj FLOAT_INT_SSE_REGS, 134938fd1498Szrj MASK_EVEX_REGS, 135038fd1498Szrj MASK_REGS, 135138fd1498Szrj MOD4_SSE_REGS, 135238fd1498Szrj ALL_REGS, LIM_REG_CLASSES 135338fd1498Szrj }; 135438fd1498Szrj 135538fd1498Szrj #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 135638fd1498Szrj 135738fd1498Szrj #define INTEGER_CLASS_P(CLASS) \ 135838fd1498Szrj reg_class_subset_p ((CLASS), GENERAL_REGS) 135938fd1498Szrj #define FLOAT_CLASS_P(CLASS) \ 136038fd1498Szrj reg_class_subset_p ((CLASS), FLOAT_REGS) 136138fd1498Szrj #define SSE_CLASS_P(CLASS) \ 136238fd1498Szrj reg_class_subset_p ((CLASS), ALL_SSE_REGS) 136338fd1498Szrj #define MMX_CLASS_P(CLASS) \ 136438fd1498Szrj ((CLASS) == MMX_REGS) 136538fd1498Szrj #define MASK_CLASS_P(CLASS) \ 136638fd1498Szrj reg_class_subset_p ((CLASS), MASK_REGS) 136738fd1498Szrj #define MAYBE_INTEGER_CLASS_P(CLASS) \ 136838fd1498Szrj reg_classes_intersect_p ((CLASS), GENERAL_REGS) 136938fd1498Szrj #define MAYBE_FLOAT_CLASS_P(CLASS) \ 137038fd1498Szrj reg_classes_intersect_p ((CLASS), FLOAT_REGS) 137138fd1498Szrj #define MAYBE_SSE_CLASS_P(CLASS) \ 137238fd1498Szrj reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) 137338fd1498Szrj #define MAYBE_MMX_CLASS_P(CLASS) \ 137438fd1498Szrj reg_classes_intersect_p ((CLASS), MMX_REGS) 137538fd1498Szrj #define MAYBE_MASK_CLASS_P(CLASS) \ 137638fd1498Szrj reg_classes_intersect_p ((CLASS), MASK_REGS) 137738fd1498Szrj 137838fd1498Szrj #define Q_CLASS_P(CLASS) \ 137938fd1498Szrj reg_class_subset_p ((CLASS), Q_REGS) 138038fd1498Szrj 138138fd1498Szrj #define MAYBE_NON_Q_CLASS_P(CLASS) \ 138238fd1498Szrj reg_classes_intersect_p ((CLASS), NON_Q_REGS) 138338fd1498Szrj 138438fd1498Szrj /* Give names of register classes as strings for dump file. */ 138538fd1498Szrj 138638fd1498Szrj #define REG_CLASS_NAMES \ 138738fd1498Szrj { "NO_REGS", \ 138838fd1498Szrj "AREG", "DREG", "CREG", "BREG", \ 138938fd1498Szrj "SIREG", "DIREG", \ 139038fd1498Szrj "AD_REGS", \ 139138fd1498Szrj "CLOBBERED_REGS", \ 139238fd1498Szrj "Q_REGS", "NON_Q_REGS", \ 139338fd1498Szrj "TLS_GOTBASE_REGS", \ 139438fd1498Szrj "INDEX_REGS", \ 139538fd1498Szrj "LEGACY_REGS", \ 139638fd1498Szrj "GENERAL_REGS", \ 139738fd1498Szrj "FP_TOP_REG", "FP_SECOND_REG", \ 139838fd1498Szrj "FLOAT_REGS", \ 139938fd1498Szrj "SSE_FIRST_REG", \ 140038fd1498Szrj "NO_REX_SSE_REGS", \ 140138fd1498Szrj "SSE_REGS", \ 140238fd1498Szrj "EVEX_SSE_REGS", \ 140338fd1498Szrj "BND_REGS", \ 140438fd1498Szrj "ALL_SSE_REGS", \ 140538fd1498Szrj "MMX_REGS", \ 140638fd1498Szrj "FP_TOP_SSE_REGS", \ 140738fd1498Szrj "FP_SECOND_SSE_REGS", \ 140838fd1498Szrj "FLOAT_SSE_REGS", \ 140938fd1498Szrj "FLOAT_INT_REGS", \ 141038fd1498Szrj "INT_SSE_REGS", \ 141138fd1498Szrj "FLOAT_INT_SSE_REGS", \ 141238fd1498Szrj "MASK_EVEX_REGS", \ 141338fd1498Szrj "MASK_REGS", \ 141438fd1498Szrj "MOD4_SSE_REGS", \ 141538fd1498Szrj "ALL_REGS" } 141638fd1498Szrj 141738fd1498Szrj /* Define which registers fit in which classes. This is an initializer 141838fd1498Szrj for a vector of HARD_REG_SET of length N_REG_CLASSES. 141938fd1498Szrj 142038fd1498Szrj Note that CLOBBERED_REGS are calculated by 142138fd1498Szrj TARGET_CONDITIONAL_REGISTER_USAGE. */ 142238fd1498Szrj 142338fd1498Szrj #define REG_CLASS_CONTENTS \ 142438fd1498Szrj { { 0x00, 0x0, 0x0 }, \ 142538fd1498Szrj { 0x01, 0x0, 0x0 }, /* AREG */ \ 142638fd1498Szrj { 0x02, 0x0, 0x0 }, /* DREG */ \ 142738fd1498Szrj { 0x04, 0x0, 0x0 }, /* CREG */ \ 142838fd1498Szrj { 0x08, 0x0, 0x0 }, /* BREG */ \ 142938fd1498Szrj { 0x10, 0x0, 0x0 }, /* SIREG */ \ 143038fd1498Szrj { 0x20, 0x0, 0x0 }, /* DIREG */ \ 143138fd1498Szrj { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ 143238fd1498Szrj { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ 143338fd1498Szrj { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ 143438fd1498Szrj { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \ 143538fd1498Szrj { 0x7e, 0x1fe0, 0x0 }, /* TLS_GOTBASE_REGS */ \ 143638fd1498Szrj { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \ 143738fd1498Szrj { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ 143838fd1498Szrj { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \ 143938fd1498Szrj { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ 144038fd1498Szrj { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ 144138fd1498Szrj { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ 144238fd1498Szrj { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ 144338fd1498Szrj { 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \ 144438fd1498Szrj { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ 144538fd1498Szrj { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \ 144638fd1498Szrj { 0x0, 0x0,0x1e000 }, /* BND_REGS */ \ 144738fd1498Szrj { 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ 144838fd1498Szrj { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ 144938fd1498Szrj { 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ 145038fd1498Szrj { 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ 145138fd1498Szrj { 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ 145238fd1498Szrj { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ 145338fd1498Szrj { 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ 145438fd1498Szrj { 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \ 145538fd1498Szrj { 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \ 145638fd1498Szrj { 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \ 145738fd1498Szrj { 0x1fe00000,0xffffe000, 0x1f }, /* MOD4_SSE_REGS */ \ 145838fd1498Szrj { 0xffffffff,0xffffffff,0x1ffff } \ 145938fd1498Szrj } 146038fd1498Szrj 146138fd1498Szrj /* The same information, inverted: 146238fd1498Szrj Return the class number of the smallest class containing 146338fd1498Szrj reg number REGNO. This could be a conditional expression 146438fd1498Szrj or could index an array. */ 146538fd1498Szrj 146638fd1498Szrj #define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)]) 146738fd1498Szrj 146838fd1498Szrj /* When this hook returns true for MODE, the compiler allows 146938fd1498Szrj registers explicitly used in the rtl to be used as spill registers 147038fd1498Szrj but prevents the compiler from extending the lifetime of these 147138fd1498Szrj registers. */ 147238fd1498Szrj #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 147338fd1498Szrj 147438fd1498Szrj #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) 147538fd1498Szrj #define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG) 147638fd1498Szrj 147738fd1498Szrj #define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X))) 147838fd1498Szrj #define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)) 147938fd1498Szrj 148038fd1498Szrj #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 148138fd1498Szrj #define REX_INT_REGNO_P(N) \ 148238fd1498Szrj IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) 148338fd1498Szrj 148438fd1498Szrj #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 148538fd1498Szrj #define GENERAL_REGNO_P(N) \ 148638fd1498Szrj (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N)) 148738fd1498Szrj 148838fd1498Szrj #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) 148938fd1498Szrj #define ANY_QI_REGNO_P(N) \ 149038fd1498Szrj (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) 149138fd1498Szrj 149238fd1498Szrj #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) 149338fd1498Szrj #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 149438fd1498Szrj 149538fd1498Szrj #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) 149638fd1498Szrj #define SSE_REGNO_P(N) \ 149738fd1498Szrj (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ 149838fd1498Szrj || REX_SSE_REGNO_P (N) \ 149938fd1498Szrj || EXT_REX_SSE_REGNO_P (N)) 150038fd1498Szrj 150138fd1498Szrj #define REX_SSE_REGNO_P(N) \ 150238fd1498Szrj IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) 150338fd1498Szrj 150438fd1498Szrj #define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X))) 150538fd1498Szrj 150638fd1498Szrj #define EXT_REX_SSE_REGNO_P(N) \ 150738fd1498Szrj IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) 150838fd1498Szrj 150938fd1498Szrj #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 151038fd1498Szrj #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) 151138fd1498Szrj 151238fd1498Szrj #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) 151338fd1498Szrj #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) 151438fd1498Szrj 151538fd1498Szrj #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) 151638fd1498Szrj #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 151738fd1498Szrj 151838fd1498Szrj #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 151938fd1498Szrj #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 152038fd1498Szrj 152138fd1498Szrj #define BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X))) 152238fd1498Szrj #define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG) 152338fd1498Szrj 152438fd1498Szrj #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X))) 152538fd1498Szrj #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \ 152638fd1498Szrj || (N) == XMM4_REG \ 152738fd1498Szrj || (N) == XMM8_REG \ 152838fd1498Szrj || (N) == XMM12_REG \ 152938fd1498Szrj || (N) == XMM16_REG \ 153038fd1498Szrj || (N) == XMM20_REG \ 153138fd1498Szrj || (N) == XMM24_REG \ 153238fd1498Szrj || (N) == XMM28_REG) 153338fd1498Szrj 153438fd1498Szrj /* First floating point reg */ 153538fd1498Szrj #define FIRST_FLOAT_REG FIRST_STACK_REG 153638fd1498Szrj #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) 153738fd1498Szrj 1538*58e805e6Szrj #define GET_SSE_REGNO(N) \ 153938fd1498Szrj ((N) < 8 ? FIRST_SSE_REG + (N) \ 1540*58e805e6Szrj : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \ 1541*58e805e6Szrj : FIRST_EXT_REX_SSE_REG + (N) - 16) 154238fd1498Szrj 154338fd1498Szrj /* The class value for index registers, and the one for base regs. */ 154438fd1498Szrj 154538fd1498Szrj #define INDEX_REG_CLASS INDEX_REGS 154638fd1498Szrj #define BASE_REG_CLASS GENERAL_REGS 154738fd1498Szrj 154838fd1498Szrj /* Stack layout; function entry, exit and calling. */ 154938fd1498Szrj 155038fd1498Szrj /* Define this if pushing a word on the stack 155138fd1498Szrj makes the stack pointer a smaller address. */ 155238fd1498Szrj #define STACK_GROWS_DOWNWARD 1 155338fd1498Szrj 155438fd1498Szrj /* Define this to nonzero if the nominal address of the stack frame 155538fd1498Szrj is at the high-address end of the local variables; 155638fd1498Szrj that is, each additional local variable allocated 155738fd1498Szrj goes at a more negative offset in the frame. */ 155838fd1498Szrj #define FRAME_GROWS_DOWNWARD 1 155938fd1498Szrj 156038fd1498Szrj #define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES) 156138fd1498Szrj 156238fd1498Szrj /* If defined, the maximum amount of space required for outgoing arguments 156338fd1498Szrj will be computed and placed into the variable `crtl->outgoing_args_size'. 156438fd1498Szrj No space will be pushed onto the stack for each call; instead, the 156538fd1498Szrj function prologue should increase the stack frame size by this amount. 156638fd1498Szrj 156738fd1498Szrj In 32bit mode enabling argument accumulation results in about 5% code size 156838fd1498Szrj growth because move instructions are less compact than push. In 64bit 156938fd1498Szrj mode the difference is less drastic but visible. 157038fd1498Szrj 157138fd1498Szrj FIXME: Unlike earlier implementations, the size of unwind info seems to 157238fd1498Szrj actually grow with accumulation. Is that because accumulated args 157338fd1498Szrj unwind info became unnecesarily bloated? 157438fd1498Szrj 157538fd1498Szrj With the 64-bit MS ABI, we can generate correct code with or without 157638fd1498Szrj accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code 157738fd1498Szrj generated without accumulated args is terrible. 157838fd1498Szrj 157938fd1498Szrj If stack probes are required, the space used for large function 158038fd1498Szrj arguments on the stack must also be probed, so enable 158138fd1498Szrj -maccumulate-outgoing-args so this happens in the prologue. 158238fd1498Szrj 158338fd1498Szrj We must use argument accumulation in interrupt function if stack 158438fd1498Szrj may be realigned to avoid DRAP. */ 158538fd1498Szrj 158638fd1498Szrj #define ACCUMULATE_OUTGOING_ARGS \ 158738fd1498Szrj ((TARGET_ACCUMULATE_OUTGOING_ARGS \ 158838fd1498Szrj && optimize_function_for_speed_p (cfun)) \ 158938fd1498Szrj || (cfun->machine->func_type != TYPE_NORMAL \ 159038fd1498Szrj && crtl->stack_realign_needed) \ 159138fd1498Szrj || TARGET_STACK_PROBE \ 159238fd1498Szrj || TARGET_64BIT_MS_ABI \ 159338fd1498Szrj || (TARGET_MACHO && crtl->profile)) 159438fd1498Szrj 159538fd1498Szrj /* If defined, a C expression whose value is nonzero when we want to use PUSH 159638fd1498Szrj instructions to pass outgoing arguments. */ 159738fd1498Szrj 159838fd1498Szrj #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 159938fd1498Szrj 160038fd1498Szrj /* We want the stack and args grow in opposite directions, even if 160138fd1498Szrj PUSH_ARGS is 0. */ 160238fd1498Szrj #define PUSH_ARGS_REVERSED 1 160338fd1498Szrj 160438fd1498Szrj /* Offset of first parameter from the argument pointer register value. */ 160538fd1498Szrj #define FIRST_PARM_OFFSET(FNDECL) 0 160638fd1498Szrj 160738fd1498Szrj /* Define this macro if functions should assume that stack space has been 160838fd1498Szrj allocated for arguments even when their values are passed in registers. 160938fd1498Szrj 161038fd1498Szrj The value of this macro is the size, in bytes, of the area reserved for 161138fd1498Szrj arguments passed in registers for the function represented by FNDECL. 161238fd1498Szrj 161338fd1498Szrj This space can be allocated by the caller, or be a part of the 161438fd1498Szrj machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 161538fd1498Szrj which. */ 161638fd1498Szrj #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) 161738fd1498Szrj 161838fd1498Szrj #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ 161938fd1498Szrj (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) 162038fd1498Szrj 162138fd1498Szrj /* Define how to find the value returned by a library function 162238fd1498Szrj assuming the value has mode MODE. */ 162338fd1498Szrj 162438fd1498Szrj #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) 162538fd1498Szrj 162638fd1498Szrj /* Define the size of the result block used for communication between 162738fd1498Szrj untyped_call and untyped_return. The block contains a DImode value 162838fd1498Szrj followed by the block used by fnsave and frstor. */ 162938fd1498Szrj 163038fd1498Szrj #define APPLY_RESULT_SIZE (8+108) 163138fd1498Szrj 163238fd1498Szrj /* 1 if N is a possible register number for function argument passing. */ 163338fd1498Szrj #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 163438fd1498Szrj 163538fd1498Szrj /* Define a data type for recording info about an argument list 163638fd1498Szrj during the scan of that argument list. This data type should 163738fd1498Szrj hold all necessary information about the function itself 163838fd1498Szrj and about the args processed so far, enough to enable macros 163938fd1498Szrj such as FUNCTION_ARG to determine where the next arg should go. */ 164038fd1498Szrj 164138fd1498Szrj typedef struct ix86_args { 164238fd1498Szrj int words; /* # words passed so far */ 164338fd1498Szrj int nregs; /* # registers available for passing */ 164438fd1498Szrj int regno; /* next available register number */ 164538fd1498Szrj int fastcall; /* fastcall or thiscall calling convention 164638fd1498Szrj is used */ 164738fd1498Szrj int sse_words; /* # sse words passed so far */ 164838fd1498Szrj int sse_nregs; /* # sse registers available for passing */ 164938fd1498Szrj int warn_avx512f; /* True when we want to warn 165038fd1498Szrj about AVX512F ABI. */ 165138fd1498Szrj int warn_avx; /* True when we want to warn about AVX ABI. */ 165238fd1498Szrj int warn_sse; /* True when we want to warn about SSE ABI. */ 165338fd1498Szrj int warn_mmx; /* True when we want to warn about MMX ABI. */ 165438fd1498Szrj int warn_empty; /* True when we want to warn about empty classes 165538fd1498Szrj passing ABI change. */ 165638fd1498Szrj int sse_regno; /* next available sse register number */ 165738fd1498Szrj int mmx_words; /* # mmx words passed so far */ 165838fd1498Szrj int mmx_nregs; /* # mmx registers available for passing */ 165938fd1498Szrj int mmx_regno; /* next available mmx register number */ 166038fd1498Szrj int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 166138fd1498Szrj int caller; /* true if it is caller. */ 166238fd1498Szrj int float_in_sse; /* Set to 1 or 2 for 32bit targets if 166338fd1498Szrj SFmode/DFmode arguments should be passed 166438fd1498Szrj in SSE registers. Otherwise 0. */ 166538fd1498Szrj int bnd_regno; /* next available bnd register number */ 166638fd1498Szrj int bnds_in_bt; /* number of bounds expected in BT. */ 166738fd1498Szrj int force_bnd_pass; /* number of bounds expected for stdarg arg. */ 166838fd1498Szrj int stdarg; /* Set to 1 if function is stdarg. */ 166938fd1498Szrj enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 167038fd1498Szrj MS_ABI for ms abi. */ 167138fd1498Szrj tree decl; /* Callee decl. */ 167238fd1498Szrj } CUMULATIVE_ARGS; 167338fd1498Szrj 167438fd1498Szrj /* Initialize a variable CUM of type CUMULATIVE_ARGS 167538fd1498Szrj for a call to a function whose data type is FNTYPE. 167638fd1498Szrj For a library call, FNTYPE is 0. */ 167738fd1498Szrj 167838fd1498Szrj #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 167938fd1498Szrj init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ 168038fd1498Szrj (N_NAMED_ARGS) != -1) 168138fd1498Szrj 168238fd1498Szrj /* Output assembler code to FILE to increment profiler label # LABELNO 168338fd1498Szrj for profiling a function entry. */ 168438fd1498Szrj 168538fd1498Szrj #define FUNCTION_PROFILER(FILE, LABELNO) \ 168638fd1498Szrj x86_function_profiler ((FILE), (LABELNO)) 168738fd1498Szrj 168838fd1498Szrj #define MCOUNT_NAME "_mcount" 168938fd1498Szrj 169038fd1498Szrj #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" 169138fd1498Szrj 169238fd1498Szrj #define PROFILE_COUNT_REGISTER "edx" 169338fd1498Szrj 169438fd1498Szrj /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 169538fd1498Szrj the stack pointer does not matter. The value is tested only in 169638fd1498Szrj functions that have frame pointers. 169738fd1498Szrj No definition is equivalent to always zero. */ 169838fd1498Szrj /* Note on the 386 it might be more efficient not to define this since 169938fd1498Szrj we have to restore it ourselves from the frame pointer, in order to 170038fd1498Szrj use pop */ 170138fd1498Szrj 170238fd1498Szrj #define EXIT_IGNORE_STACK 1 170338fd1498Szrj 170438fd1498Szrj /* Define this macro as a C expression that is nonzero for registers 170538fd1498Szrj used by the epilogue or the `return' pattern. */ 170638fd1498Szrj 170738fd1498Szrj #define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO) 170838fd1498Szrj 170938fd1498Szrj /* Output assembler code for a block containing the constant parts 171038fd1498Szrj of a trampoline, leaving space for the variable parts. */ 171138fd1498Szrj 171238fd1498Szrj /* On the 386, the trampoline contains two instructions: 171338fd1498Szrj mov #STATIC,ecx 171438fd1498Szrj jmp FUNCTION 171538fd1498Szrj The trampoline is generated entirely at runtime. The operand of JMP 171638fd1498Szrj is the address of FUNCTION relative to the instruction following the 171738fd1498Szrj JMP (which is 5 bytes long). */ 171838fd1498Szrj 171938fd1498Szrj /* Length in units of the trampoline for entering a nested function. */ 172038fd1498Szrj 172138fd1498Szrj #define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14) 172238fd1498Szrj 172338fd1498Szrj /* Definitions for register eliminations. 172438fd1498Szrj 172538fd1498Szrj This is an array of structures. Each structure initializes one pair 172638fd1498Szrj of eliminable registers. The "from" register number is given first, 172738fd1498Szrj followed by "to". Eliminations of the same "from" register are listed 172838fd1498Szrj in order of preference. 172938fd1498Szrj 173038fd1498Szrj There are two registers that can always be eliminated on the i386. 173138fd1498Szrj The frame pointer and the arg pointer can be replaced by either the 173238fd1498Szrj hard frame pointer or to the stack pointer, depending upon the 173338fd1498Szrj circumstances. The hard frame pointer is not used before reload and 173438fd1498Szrj so it is not eligible for elimination. */ 173538fd1498Szrj 173638fd1498Szrj #define ELIMINABLE_REGS \ 173738fd1498Szrj {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 173838fd1498Szrj { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 173938fd1498Szrj { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 174038fd1498Szrj { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 174138fd1498Szrj 174238fd1498Szrj /* Define the offset between two registers, one to be eliminated, and the other 174338fd1498Szrj its replacement, at the start of a routine. */ 174438fd1498Szrj 174538fd1498Szrj #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 174638fd1498Szrj ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 174738fd1498Szrj 174838fd1498Szrj /* Addressing modes, and classification of registers for them. */ 174938fd1498Szrj 175038fd1498Szrj /* Macros to check register numbers against specific register classes. */ 175138fd1498Szrj 175238fd1498Szrj /* These assume that REGNO is a hard or pseudo reg number. 175338fd1498Szrj They give nonzero only if REGNO is a hard reg of the suitable class 175438fd1498Szrj or a pseudo reg currently allocated to a suitable hard reg. 175538fd1498Szrj Since they use reg_renumber, they are safe only once reg_renumber 175638fd1498Szrj has been allocated, which happens in reginfo.c during register 175738fd1498Szrj allocation. */ 175838fd1498Szrj 175938fd1498Szrj #define REGNO_OK_FOR_INDEX_P(REGNO) \ 176038fd1498Szrj ((REGNO) < STACK_POINTER_REGNUM \ 176138fd1498Szrj || REX_INT_REGNO_P (REGNO) \ 176238fd1498Szrj || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ 176338fd1498Szrj || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 176438fd1498Szrj 176538fd1498Szrj #define REGNO_OK_FOR_BASE_P(REGNO) \ 176638fd1498Szrj (GENERAL_REGNO_P (REGNO) \ 176738fd1498Szrj || (REGNO) == ARG_POINTER_REGNUM \ 176838fd1498Szrj || (REGNO) == FRAME_POINTER_REGNUM \ 176938fd1498Szrj || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 177038fd1498Szrj 177138fd1498Szrj /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 177238fd1498Szrj and check its validity for a certain class. 177338fd1498Szrj We have two alternate definitions for each of them. 177438fd1498Szrj The usual definition accepts all pseudo regs; the other rejects 177538fd1498Szrj them unless they have been allocated suitable hard regs. 177638fd1498Szrj The symbol REG_OK_STRICT causes the latter definition to be used. 177738fd1498Szrj 177838fd1498Szrj Most source files want to accept pseudo regs in the hope that 177938fd1498Szrj they will get allocated to the class that the insn wants them to be in. 178038fd1498Szrj Source files for reload pass need to be strict. 178138fd1498Szrj After reload, it makes no difference, since pseudo regs have 178238fd1498Szrj been eliminated by then. */ 178338fd1498Szrj 178438fd1498Szrj 178538fd1498Szrj /* Non strict versions, pseudos are ok. */ 178638fd1498Szrj #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 178738fd1498Szrj (REGNO (X) < STACK_POINTER_REGNUM \ 178838fd1498Szrj || REX_INT_REGNO_P (REGNO (X)) \ 178938fd1498Szrj || REGNO (X) >= FIRST_PSEUDO_REGISTER) 179038fd1498Szrj 179138fd1498Szrj #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 179238fd1498Szrj (GENERAL_REGNO_P (REGNO (X)) \ 179338fd1498Szrj || REGNO (X) == ARG_POINTER_REGNUM \ 179438fd1498Szrj || REGNO (X) == FRAME_POINTER_REGNUM \ 179538fd1498Szrj || REGNO (X) >= FIRST_PSEUDO_REGISTER) 179638fd1498Szrj 179738fd1498Szrj /* Strict versions, hard registers only */ 179838fd1498Szrj #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 179938fd1498Szrj #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 180038fd1498Szrj 180138fd1498Szrj #ifndef REG_OK_STRICT 180238fd1498Szrj #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 180338fd1498Szrj #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 180438fd1498Szrj 180538fd1498Szrj #else 180638fd1498Szrj #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 180738fd1498Szrj #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 180838fd1498Szrj #endif 180938fd1498Szrj 181038fd1498Szrj /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 181138fd1498Szrj that is a valid memory address for an instruction. 181238fd1498Szrj The MODE argument is the machine mode for the MEM expression 181338fd1498Szrj that wants to use this address. 181438fd1498Szrj 181538fd1498Szrj The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, 181638fd1498Szrj except for CONSTANT_ADDRESS_P which is usually machine-independent. 181738fd1498Szrj 181838fd1498Szrj See legitimize_pic_address in i386.c for details as to what 181938fd1498Szrj constitutes a legitimate address when -fpic is used. */ 182038fd1498Szrj 182138fd1498Szrj #define MAX_REGS_PER_ADDRESS 2 182238fd1498Szrj 182338fd1498Szrj #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 182438fd1498Szrj 182538fd1498Szrj /* If defined, a C expression to determine the base term of address X. 182638fd1498Szrj This macro is used in only one place: `find_base_term' in alias.c. 182738fd1498Szrj 182838fd1498Szrj It is always safe for this macro to not be defined. It exists so 182938fd1498Szrj that alias analysis can understand machine-dependent addresses. 183038fd1498Szrj 183138fd1498Szrj The typical use of this macro is to handle addresses containing 183238fd1498Szrj a label_ref or symbol_ref within an UNSPEC. */ 183338fd1498Szrj 183438fd1498Szrj #define FIND_BASE_TERM(X) ix86_find_base_term (X) 183538fd1498Szrj 183638fd1498Szrj /* Nonzero if the constant value X is a legitimate general operand 183738fd1498Szrj when generating PIC code. It is given that flag_pic is on and 183838fd1498Szrj that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 183938fd1498Szrj 184038fd1498Szrj #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 184138fd1498Szrj 184238fd1498Szrj #define SYMBOLIC_CONST(X) \ 184338fd1498Szrj (GET_CODE (X) == SYMBOL_REF \ 184438fd1498Szrj || GET_CODE (X) == LABEL_REF \ 184538fd1498Szrj || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 184638fd1498Szrj 184738fd1498Szrj /* Max number of args passed in registers. If this is more than 3, we will 184838fd1498Szrj have problems with ebx (register #4), since it is a caller save register and 184938fd1498Szrj is also used as the pic register in ELF. So for now, don't allow more than 185038fd1498Szrj 3 registers to be passed in registers. */ 185138fd1498Szrj 185238fd1498Szrj /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ 185338fd1498Szrj #define X86_64_REGPARM_MAX 6 185438fd1498Szrj #define X86_64_MS_REGPARM_MAX 4 185538fd1498Szrj 185638fd1498Szrj #define X86_32_REGPARM_MAX 3 185738fd1498Szrj 185838fd1498Szrj #define REGPARM_MAX \ 185938fd1498Szrj (TARGET_64BIT \ 186038fd1498Szrj ? (TARGET_64BIT_MS_ABI \ 186138fd1498Szrj ? X86_64_MS_REGPARM_MAX \ 186238fd1498Szrj : X86_64_REGPARM_MAX) \ 186338fd1498Szrj : X86_32_REGPARM_MAX) 186438fd1498Szrj 186538fd1498Szrj #define X86_64_SSE_REGPARM_MAX 8 186638fd1498Szrj #define X86_64_MS_SSE_REGPARM_MAX 4 186738fd1498Szrj 186838fd1498Szrj #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) 186938fd1498Szrj 187038fd1498Szrj #define SSE_REGPARM_MAX \ 187138fd1498Szrj (TARGET_64BIT \ 187238fd1498Szrj ? (TARGET_64BIT_MS_ABI \ 187338fd1498Szrj ? X86_64_MS_SSE_REGPARM_MAX \ 187438fd1498Szrj : X86_64_SSE_REGPARM_MAX) \ 187538fd1498Szrj : X86_32_SSE_REGPARM_MAX) 187638fd1498Szrj 187738fd1498Szrj #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 187838fd1498Szrj 187938fd1498Szrj /* Specify the machine mode that this machine uses 188038fd1498Szrj for the index in the tablejump instruction. */ 188138fd1498Szrj #define CASE_VECTOR_MODE \ 188238fd1498Szrj (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) 188338fd1498Szrj 188438fd1498Szrj /* Define this as 1 if `char' should by default be signed; else as 0. */ 188538fd1498Szrj #define DEFAULT_SIGNED_CHAR 1 188638fd1498Szrj 188738fd1498Szrj /* Max number of bytes we can move from memory to memory 188838fd1498Szrj in one reasonably fast instruction. */ 188938fd1498Szrj #define MOVE_MAX 16 189038fd1498Szrj 189138fd1498Szrj /* MOVE_MAX_PIECES is the number of bytes at a time which we can 189238fd1498Szrj move efficiently, as opposed to MOVE_MAX which is the maximum 189338fd1498Szrj number of bytes we can move with a single instruction. 189438fd1498Szrj 189538fd1498Szrj ??? We should use TImode in 32-bit mode and use OImode or XImode 189638fd1498Szrj if they are available. But since by_pieces_ninsns determines the 189738fd1498Szrj widest mode with MAX_FIXED_MODE_SIZE, we can only use TImode in 189838fd1498Szrj 64-bit mode. */ 189938fd1498Szrj #define MOVE_MAX_PIECES \ 190038fd1498Szrj ((TARGET_64BIT \ 190138fd1498Szrj && TARGET_SSE2 \ 190238fd1498Szrj && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 190338fd1498Szrj && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ 190438fd1498Szrj ? GET_MODE_SIZE (TImode) : UNITS_PER_WORD) 190538fd1498Szrj 190638fd1498Szrj /* If a memory-to-memory move would take MOVE_RATIO or more simple 190738fd1498Szrj move-instruction pairs, we will do a movmem or libcall instead. 190838fd1498Szrj Increasing the value will always make code faster, but eventually 190938fd1498Szrj incurs high cost in increased code size. 191038fd1498Szrj 191138fd1498Szrj If you don't define this, a reasonable default is used. */ 191238fd1498Szrj 191338fd1498Szrj #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) 191438fd1498Szrj 191538fd1498Szrj /* If a clear memory operation would take CLEAR_RATIO or more simple 191638fd1498Szrj move-instruction sequences, we will do a clrmem or libcall instead. */ 191738fd1498Szrj 191838fd1498Szrj #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) 191938fd1498Szrj 192038fd1498Szrj /* Define if shifts truncate the shift count which implies one can 192138fd1498Szrj omit a sign-extension or zero-extension of a shift count. 192238fd1498Szrj 192338fd1498Szrj On i386, shifts do truncate the count. But bit test instructions 192438fd1498Szrj take the modulo of the bit offset operand. */ 192538fd1498Szrj 192638fd1498Szrj /* #define SHIFT_COUNT_TRUNCATED */ 192738fd1498Szrj 192838fd1498Szrj /* A macro to update M and UNSIGNEDP when an object whose type is 192938fd1498Szrj TYPE and which has the specified mode and signedness is to be 193038fd1498Szrj stored in a register. This macro is only called when TYPE is a 193138fd1498Szrj scalar type. 193238fd1498Szrj 193338fd1498Szrj On i386 it is sometimes useful to promote HImode and QImode 193438fd1498Szrj quantities to SImode. The choice depends on target type. */ 193538fd1498Szrj 193638fd1498Szrj #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 193738fd1498Szrj do { \ 193838fd1498Szrj if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 193938fd1498Szrj || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 194038fd1498Szrj (MODE) = SImode; \ 194138fd1498Szrj } while (0) 194238fd1498Szrj 194338fd1498Szrj /* Specify the machine mode that pointers have. 194438fd1498Szrj After generation of rtl, the compiler makes no further distinction 194538fd1498Szrj between pointers and any other objects of this machine mode. */ 194638fd1498Szrj #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) 194738fd1498Szrj 194838fd1498Szrj /* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save. 194938fd1498Szrj NONLOCAL needs space to save both shadow stack and stack pointers. 195038fd1498Szrj 195138fd1498Szrj FIXME: We only need to save and restore stack pointer in ptr_mode. 195238fd1498Szrj But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode 195338fd1498Szrj to save and restore stack pointer. See 195438fd1498Szrj https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150 195538fd1498Szrj */ 195638fd1498Szrj #define STACK_SAVEAREA_MODE(LEVEL) \ 195738fd1498Szrj ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) 195838fd1498Szrj 195938fd1498Szrj /* Specify the machine mode that bounds have. */ 196038fd1498Szrj #define BNDmode (ix86_pmode == PMODE_DI ? BND64mode : BND32mode) 196138fd1498Szrj 196238fd1498Szrj /* A C expression whose value is zero if pointers that need to be extended 196338fd1498Szrj from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 196438fd1498Szrj greater then zero if they are zero-extended and less then zero if the 196538fd1498Szrj ptr_extend instruction should be used. */ 196638fd1498Szrj 196738fd1498Szrj #define POINTERS_EXTEND_UNSIGNED 1 196838fd1498Szrj 196938fd1498Szrj /* A function address in a call instruction 197038fd1498Szrj is a byte address (for indexing purposes) 197138fd1498Szrj so give the MEM rtx a byte's mode. */ 197238fd1498Szrj #define FUNCTION_MODE QImode 197338fd1498Szrj 197438fd1498Szrj 197538fd1498Szrj /* A C expression for the cost of a branch instruction. A value of 1 197638fd1498Szrj is the default; other values are interpreted relative to that. */ 197738fd1498Szrj 197838fd1498Szrj #define BRANCH_COST(speed_p, predictable_p) \ 197938fd1498Szrj (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) 198038fd1498Szrj 198138fd1498Szrj /* An integer expression for the size in bits of the largest integer machine 198238fd1498Szrj mode that should actually be used. We allow pairs of registers. */ 198338fd1498Szrj #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 198438fd1498Szrj 198538fd1498Szrj /* Define this macro as a C expression which is nonzero if accessing 198638fd1498Szrj less than a word of memory (i.e. a `char' or a `short') is no 198738fd1498Szrj faster than accessing a word of memory, i.e., if such access 198838fd1498Szrj require more than one instruction or if there is no difference in 198938fd1498Szrj cost between byte and (aligned) word loads. 199038fd1498Szrj 199138fd1498Szrj When this macro is not defined, the compiler will access a field by 199238fd1498Szrj finding the smallest containing object; when it is defined, a 199338fd1498Szrj fullword load will be used if alignment permits. Unless bytes 199438fd1498Szrj accesses are faster than word accesses, using word accesses is 199538fd1498Szrj preferable since it may eliminate subsequent memory access if 199638fd1498Szrj subsequent accesses occur to other fields in the same word of the 199738fd1498Szrj structure, but to different bytes. */ 199838fd1498Szrj 199938fd1498Szrj #define SLOW_BYTE_ACCESS 0 200038fd1498Szrj 200138fd1498Szrj /* Nonzero if access to memory by shorts is slow and undesirable. */ 200238fd1498Szrj #define SLOW_SHORT_ACCESS 0 200338fd1498Szrj 200438fd1498Szrj /* Define this macro if it is as good or better to call a constant 200538fd1498Szrj function address than to call an address kept in a register. 200638fd1498Szrj 200738fd1498Szrj Desirable on the 386 because a CALL with a constant address is 200838fd1498Szrj faster than one with a register address. */ 200938fd1498Szrj 201038fd1498Szrj #define NO_FUNCTION_CSE 1 201138fd1498Szrj 201238fd1498Szrj /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 201338fd1498Szrj return the mode to be used for the comparison. 201438fd1498Szrj 201538fd1498Szrj For floating-point equality comparisons, CCFPEQmode should be used. 201638fd1498Szrj VOIDmode should be used in all other cases. 201738fd1498Szrj 201838fd1498Szrj For integer comparisons against zero, reduce to CCNOmode or CCZmode if 201938fd1498Szrj possible, to allow for more combinations. */ 202038fd1498Szrj 202138fd1498Szrj #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 202238fd1498Szrj 202338fd1498Szrj /* Return nonzero if MODE implies a floating point inequality can be 202438fd1498Szrj reversed. */ 202538fd1498Szrj 202638fd1498Szrj #define REVERSIBLE_CC_MODE(MODE) 1 202738fd1498Szrj 202838fd1498Szrj /* A C expression whose value is reversed condition code of the CODE for 202938fd1498Szrj comparison done in CC_MODE mode. */ 203038fd1498Szrj #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 203138fd1498Szrj 203238fd1498Szrj 203338fd1498Szrj /* Control the assembler format that we output, to the extent 203438fd1498Szrj this does not vary between assemblers. */ 203538fd1498Szrj 203638fd1498Szrj /* How to refer to registers in assembler output. 203738fd1498Szrj This sequence is indexed by compiler's hard-register-number (see above). */ 203838fd1498Szrj 203938fd1498Szrj /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". 204038fd1498Szrj For non floating point regs, the following are the HImode names. 204138fd1498Szrj 204238fd1498Szrj For float regs, the stack top is sometimes referred to as "%st(0)" 204338fd1498Szrj instead of just "%st". TARGET_PRINT_OPERAND handles this with the 204438fd1498Szrj "y" code. */ 204538fd1498Szrj 204638fd1498Szrj #define HI_REGISTER_NAMES \ 204738fd1498Szrj {"ax","dx","cx","bx","si","di","bp","sp", \ 204838fd1498Szrj "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 204938fd1498Szrj "argp", "flags", "fpsr", "fpcr", "frame", \ 205038fd1498Szrj "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 205138fd1498Szrj "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 205238fd1498Szrj "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 205338fd1498Szrj "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ 205438fd1498Szrj "xmm16", "xmm17", "xmm18", "xmm19", \ 205538fd1498Szrj "xmm20", "xmm21", "xmm22", "xmm23", \ 205638fd1498Szrj "xmm24", "xmm25", "xmm26", "xmm27", \ 205738fd1498Szrj "xmm28", "xmm29", "xmm30", "xmm31", \ 205838fd1498Szrj "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \ 205938fd1498Szrj "bnd0", "bnd1", "bnd2", "bnd3" } 206038fd1498Szrj 206138fd1498Szrj #define REGISTER_NAMES HI_REGISTER_NAMES 206238fd1498Szrj 206338fd1498Szrj /* Table of additional register names to use in user input. */ 206438fd1498Szrj 206538fd1498Szrj #define ADDITIONAL_REGISTER_NAMES \ 206638fd1498Szrj { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 206738fd1498Szrj { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 206838fd1498Szrj { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 206938fd1498Szrj { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 207038fd1498Szrj { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 207138fd1498Szrj { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 207238fd1498Szrj { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \ 207338fd1498Szrj { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \ 207438fd1498Szrj { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \ 207538fd1498Szrj { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \ 207638fd1498Szrj { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \ 207738fd1498Szrj { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \ 207838fd1498Szrj { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \ 207938fd1498Szrj { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \ 208038fd1498Szrj { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \ 208138fd1498Szrj { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \ 208238fd1498Szrj { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \ 208338fd1498Szrj { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \ 208438fd1498Szrj { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \ 208538fd1498Szrj { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \ 208638fd1498Szrj { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \ 208738fd1498Szrj { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} } 208838fd1498Szrj 208938fd1498Szrj /* Note we are omitting these since currently I don't know how 209038fd1498Szrj to get gcc to use these, since they want the same but different 209138fd1498Szrj number as al, and ax. 209238fd1498Szrj */ 209338fd1498Szrj 209438fd1498Szrj #define QI_REGISTER_NAMES \ 209538fd1498Szrj {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 209638fd1498Szrj 209738fd1498Szrj /* These parallel the array above, and can be used to access bits 8:15 209838fd1498Szrj of regs 0 through 3. */ 209938fd1498Szrj 210038fd1498Szrj #define QI_HIGH_REGISTER_NAMES \ 210138fd1498Szrj {"ah", "dh", "ch", "bh", } 210238fd1498Szrj 210338fd1498Szrj /* How to renumber registers for dbx and gdb. */ 210438fd1498Szrj 210538fd1498Szrj #define DBX_REGISTER_NUMBER(N) \ 210638fd1498Szrj (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 210738fd1498Szrj 210838fd1498Szrj extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 210938fd1498Szrj extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 211038fd1498Szrj extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 211138fd1498Szrj 211238fd1498Szrj /* Before the prologue, RA is at 0(%esp). */ 211338fd1498Szrj #define INCOMING_RETURN_ADDR_RTX \ 211438fd1498Szrj gen_rtx_MEM (Pmode, stack_pointer_rtx) 211538fd1498Szrj 211638fd1498Szrj /* After the prologue, RA is at -4(AP) in the current frame. */ 211738fd1498Szrj #define RETURN_ADDR_RTX(COUNT, FRAME) \ 211838fd1498Szrj ((COUNT) == 0 \ 211938fd1498Szrj ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ 212038fd1498Szrj -UNITS_PER_WORD)) \ 212138fd1498Szrj : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD))) 212238fd1498Szrj 212338fd1498Szrj /* PC is dbx register 8; let's use that column for RA. */ 212438fd1498Szrj #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 212538fd1498Szrj 212638fd1498Szrj /* Before the prologue, there are return address and error code for 212738fd1498Szrj exception handler on the top of the frame. */ 212838fd1498Szrj #define INCOMING_FRAME_SP_OFFSET \ 212938fd1498Szrj (cfun->machine->func_type == TYPE_EXCEPTION \ 213038fd1498Szrj ? 2 * UNITS_PER_WORD : UNITS_PER_WORD) 213138fd1498Szrj 213238fd1498Szrj /* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in 213338fd1498Szrj .cfi_startproc. */ 213438fd1498Szrj #define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 213538fd1498Szrj 213638fd1498Szrj /* Describe how we implement __builtin_eh_return. */ 213738fd1498Szrj #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) 213838fd1498Szrj #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) 213938fd1498Szrj 214038fd1498Szrj 214138fd1498Szrj /* Select a format to encode pointers in exception handling data. CODE 214238fd1498Szrj is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 214338fd1498Szrj true if the symbol may be affected by dynamic relocations. 214438fd1498Szrj 214538fd1498Szrj ??? All x86 object file formats are capable of representing this. 214638fd1498Szrj After all, the relocation needed is the same as for the call insn. 214738fd1498Szrj Whether or not a particular assembler allows us to enter such, I 214838fd1498Szrj guess we'll have to see. */ 214938fd1498Szrj #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 215038fd1498Szrj asm_preferred_eh_data_format ((CODE), (GLOBAL)) 215138fd1498Szrj 215238fd1498Szrj /* These are a couple of extensions to the formats accepted 215338fd1498Szrj by asm_fprintf: 215438fd1498Szrj %z prints out opcode suffix for word-mode instruction 215538fd1498Szrj %r prints out word-mode name for reg_names[arg] */ 215638fd1498Szrj #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 215738fd1498Szrj case 'z': \ 215838fd1498Szrj fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \ 215938fd1498Szrj break; \ 216038fd1498Szrj \ 216138fd1498Szrj case 'r': \ 216238fd1498Szrj { \ 216338fd1498Szrj unsigned int regno = va_arg ((ARGS), int); \ 216438fd1498Szrj if (LEGACY_INT_REGNO_P (regno)) \ 216538fd1498Szrj fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \ 216638fd1498Szrj fputs (reg_names[regno], (FILE)); \ 216738fd1498Szrj break; \ 216838fd1498Szrj } 216938fd1498Szrj 217038fd1498Szrj /* This is how to output an insn to push a register on the stack. */ 217138fd1498Szrj 217238fd1498Szrj #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 217338fd1498Szrj asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO)) 217438fd1498Szrj 217538fd1498Szrj /* This is how to output an insn to pop a register from the stack. */ 217638fd1498Szrj 217738fd1498Szrj #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 217838fd1498Szrj asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO)) 217938fd1498Szrj 218038fd1498Szrj /* This is how to output an element of a case-vector that is absolute. */ 218138fd1498Szrj 218238fd1498Szrj #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 218338fd1498Szrj ix86_output_addr_vec_elt ((FILE), (VALUE)) 218438fd1498Szrj 218538fd1498Szrj /* This is how to output an element of a case-vector that is relative. */ 218638fd1498Szrj 218738fd1498Szrj #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 218838fd1498Szrj ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 218938fd1498Szrj 219038fd1498Szrj /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ 219138fd1498Szrj 219238fd1498Szrj #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ 219338fd1498Szrj { \ 219438fd1498Szrj if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ 219538fd1498Szrj (PTR) += TARGET_AVX ? 1 : 2; \ 219638fd1498Szrj } 219738fd1498Szrj 219838fd1498Szrj /* A C statement or statements which output an assembler instruction 219938fd1498Szrj opcode to the stdio stream STREAM. The macro-operand PTR is a 220038fd1498Szrj variable of type `char *' which points to the opcode name in 220138fd1498Szrj its "internal" form--the form that is written in the machine 220238fd1498Szrj description. */ 220338fd1498Szrj 220438fd1498Szrj #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 220538fd1498Szrj ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) 220638fd1498Szrj 220738fd1498Szrj /* A C statement to output to the stdio stream FILE an assembler 220838fd1498Szrj command to pad the location counter to a multiple of 1<<LOG 220938fd1498Szrj bytes if it is within MAX_SKIP bytes. */ 221038fd1498Szrj 221138fd1498Szrj #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 221238fd1498Szrj #undef ASM_OUTPUT_MAX_SKIP_PAD 221338fd1498Szrj #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 221438fd1498Szrj if ((LOG) != 0) \ 221538fd1498Szrj { \ 221638fd1498Szrj if ((MAX_SKIP) == 0) \ 221738fd1498Szrj fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 221838fd1498Szrj else \ 221938fd1498Szrj fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 222038fd1498Szrj } 222138fd1498Szrj #endif 222238fd1498Szrj 222338fd1498Szrj /* Write the extra assembler code needed to declare a function 222438fd1498Szrj properly. */ 222538fd1498Szrj 222638fd1498Szrj #undef ASM_OUTPUT_FUNCTION_LABEL 222738fd1498Szrj #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 222838fd1498Szrj ix86_asm_output_function_label ((FILE), (NAME), (DECL)) 222938fd1498Szrj 223038fd1498Szrj /* Under some conditions we need jump tables in the text section, 223138fd1498Szrj because the assembler cannot handle label differences between 223238fd1498Szrj sections. This is the case for x86_64 on Mach-O for example. */ 223338fd1498Szrj 223438fd1498Szrj #define JUMP_TABLES_IN_TEXT_SECTION \ 223538fd1498Szrj (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 223638fd1498Szrj || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 223738fd1498Szrj 223838fd1498Szrj /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 223938fd1498Szrj and switch back. For x86 we do this only to save a few bytes that 224038fd1498Szrj would otherwise be unused in the text section. */ 224138fd1498Szrj #define CRT_MKSTR2(VAL) #VAL 224238fd1498Szrj #define CRT_MKSTR(x) CRT_MKSTR2(x) 224338fd1498Szrj 224438fd1498Szrj #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 224538fd1498Szrj asm (SECTION_OP "\n\t" \ 224638fd1498Szrj "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ 224738fd1498Szrj TEXT_SECTION_ASM_OP); 224838fd1498Szrj 224938fd1498Szrj /* Default threshold for putting data in large sections 225038fd1498Szrj with x86-64 medium memory model */ 225138fd1498Szrj #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 225238fd1498Szrj 225338fd1498Szrj /* Adjust the length of the insn with the length of BND prefix. */ 225438fd1498Szrj 225538fd1498Szrj #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 225638fd1498Szrj do { \ 225738fd1498Szrj if (NONDEBUG_INSN_P (INSN) && INSN_CODE (INSN) >= 0 \ 225838fd1498Szrj && get_attr_maybe_prefix_bnd (INSN)) \ 225938fd1498Szrj LENGTH += ix86_bnd_prefixed_insn_p (INSN); \ 226038fd1498Szrj } while (0) 226138fd1498Szrj 226238fd1498Szrj /* Which processor to tune code generation for. These must be in sync 226338fd1498Szrj with processor_target_table in i386.c. */ 226438fd1498Szrj 226538fd1498Szrj enum processor_type 226638fd1498Szrj { 226738fd1498Szrj PROCESSOR_GENERIC = 0, 226838fd1498Szrj PROCESSOR_I386, /* 80386 */ 226938fd1498Szrj PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 227038fd1498Szrj PROCESSOR_PENTIUM, 227138fd1498Szrj PROCESSOR_LAKEMONT, 227238fd1498Szrj PROCESSOR_PENTIUMPRO, 227338fd1498Szrj PROCESSOR_PENTIUM4, 227438fd1498Szrj PROCESSOR_NOCONA, 227538fd1498Szrj PROCESSOR_CORE2, 227638fd1498Szrj PROCESSOR_NEHALEM, 227738fd1498Szrj PROCESSOR_SANDYBRIDGE, 227838fd1498Szrj PROCESSOR_HASWELL, 227938fd1498Szrj PROCESSOR_BONNELL, 228038fd1498Szrj PROCESSOR_SILVERMONT, 228138fd1498Szrj PROCESSOR_KNL, 228238fd1498Szrj PROCESSOR_KNM, 228338fd1498Szrj PROCESSOR_SKYLAKE, 228438fd1498Szrj PROCESSOR_SKYLAKE_AVX512, 228538fd1498Szrj PROCESSOR_CANNONLAKE, 228638fd1498Szrj PROCESSOR_ICELAKE_CLIENT, 228738fd1498Szrj PROCESSOR_ICELAKE_SERVER, 228838fd1498Szrj PROCESSOR_INTEL, 228938fd1498Szrj PROCESSOR_GEODE, 229038fd1498Szrj PROCESSOR_K6, 229138fd1498Szrj PROCESSOR_ATHLON, 229238fd1498Szrj PROCESSOR_K8, 229338fd1498Szrj PROCESSOR_AMDFAM10, 229438fd1498Szrj PROCESSOR_BDVER1, 229538fd1498Szrj PROCESSOR_BDVER2, 229638fd1498Szrj PROCESSOR_BDVER3, 229738fd1498Szrj PROCESSOR_BDVER4, 229838fd1498Szrj PROCESSOR_BTVER1, 229938fd1498Szrj PROCESSOR_BTVER2, 230038fd1498Szrj PROCESSOR_ZNVER1, 230138fd1498Szrj PROCESSOR_max 230238fd1498Szrj }; 230338fd1498Szrj 230438fd1498Szrj extern enum processor_type ix86_tune; 230538fd1498Szrj extern enum processor_type ix86_arch; 230638fd1498Szrj 230738fd1498Szrj /* Size of the RED_ZONE area. */ 230838fd1498Szrj #define RED_ZONE_SIZE 128 230938fd1498Szrj /* Reserved area of the red zone for temporaries. */ 231038fd1498Szrj #define RED_ZONE_RESERVE 8 231138fd1498Szrj 231238fd1498Szrj extern unsigned int ix86_preferred_stack_boundary; 231338fd1498Szrj extern unsigned int ix86_incoming_stack_boundary; 231438fd1498Szrj 231538fd1498Szrj /* Smallest class containing REGNO. */ 231638fd1498Szrj extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 231738fd1498Szrj 231838fd1498Szrj enum ix86_fpcmp_strategy { 231938fd1498Szrj IX86_FPCMP_SAHF, 232038fd1498Szrj IX86_FPCMP_COMI, 232138fd1498Szrj IX86_FPCMP_ARITH 232238fd1498Szrj }; 232338fd1498Szrj 232438fd1498Szrj /* To properly truncate FP values into integers, we need to set i387 control 232538fd1498Szrj word. We can't emit proper mode switching code before reload, as spills 232638fd1498Szrj generated by reload may truncate values incorrectly, but we still can avoid 232738fd1498Szrj redundant computation of new control word by the mode switching pass. 232838fd1498Szrj The fldcw instructions are still emitted redundantly, but this is probably 232938fd1498Szrj not going to be noticeable problem, as most CPUs do have fast path for 233038fd1498Szrj the sequence. 233138fd1498Szrj 233238fd1498Szrj The machinery is to emit simple truncation instructions and split them 233338fd1498Szrj before reload to instructions having USEs of two memory locations that 233438fd1498Szrj are filled by this code to old and new control word. 233538fd1498Szrj 233638fd1498Szrj Post-reload pass may be later used to eliminate the redundant fildcw if 233738fd1498Szrj needed. */ 233838fd1498Szrj 233938fd1498Szrj enum ix86_stack_slot 234038fd1498Szrj { 234138fd1498Szrj SLOT_TEMP = 0, 234238fd1498Szrj SLOT_CW_STORED, 234338fd1498Szrj SLOT_CW_TRUNC, 234438fd1498Szrj SLOT_CW_FLOOR, 234538fd1498Szrj SLOT_CW_CEIL, 234638fd1498Szrj SLOT_CW_MASK_PM, 234738fd1498Szrj SLOT_STV_TEMP, 234838fd1498Szrj MAX_386_STACK_LOCALS 234938fd1498Szrj }; 235038fd1498Szrj 235138fd1498Szrj enum ix86_entity 235238fd1498Szrj { 235338fd1498Szrj X86_DIRFLAG = 0, 235438fd1498Szrj AVX_U128, 235538fd1498Szrj I387_TRUNC, 235638fd1498Szrj I387_FLOOR, 235738fd1498Szrj I387_CEIL, 235838fd1498Szrj I387_MASK_PM, 235938fd1498Szrj MAX_386_ENTITIES 236038fd1498Szrj }; 236138fd1498Szrj 236238fd1498Szrj enum x86_dirflag_state 236338fd1498Szrj { 236438fd1498Szrj X86_DIRFLAG_RESET, 236538fd1498Szrj X86_DIRFLAG_ANY 236638fd1498Szrj }; 236738fd1498Szrj 236838fd1498Szrj enum avx_u128_state 236938fd1498Szrj { 237038fd1498Szrj AVX_U128_CLEAN, 237138fd1498Szrj AVX_U128_DIRTY, 237238fd1498Szrj AVX_U128_ANY 237338fd1498Szrj }; 237438fd1498Szrj 237538fd1498Szrj /* Define this macro if the port needs extra instructions inserted 237638fd1498Szrj for mode switching in an optimizing compilation. */ 237738fd1498Szrj 237838fd1498Szrj #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 237938fd1498Szrj ix86_optimize_mode_switching[(ENTITY)] 238038fd1498Szrj 238138fd1498Szrj /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 238238fd1498Szrj initializer for an array of integers. Each initializer element N 238338fd1498Szrj refers to an entity that needs mode switching, and specifies the 238438fd1498Szrj number of different modes that might need to be set for this 238538fd1498Szrj entity. The position of the initializer in the initializer - 238638fd1498Szrj starting counting at zero - determines the integer that is used to 238738fd1498Szrj refer to the mode-switched entity in question. */ 238838fd1498Szrj 238938fd1498Szrj #define NUM_MODES_FOR_MODE_SWITCHING \ 239038fd1498Szrj { X86_DIRFLAG_ANY, AVX_U128_ANY, \ 239138fd1498Szrj I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 239238fd1498Szrj 239338fd1498Szrj 239438fd1498Szrj /* Avoid renaming of stack registers, as doing so in combination with 239538fd1498Szrj scheduling just increases amount of live registers at time and in 239638fd1498Szrj the turn amount of fxch instructions needed. 239738fd1498Szrj 239838fd1498Szrj ??? Maybe Pentium chips benefits from renaming, someone can try.... 239938fd1498Szrj 240038fd1498Szrj Don't rename evex to non-evex sse registers. */ 240138fd1498Szrj 240238fd1498Szrj #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 240338fd1498Szrj (!STACK_REGNO_P (SRC) \ 240438fd1498Szrj && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET)) 240538fd1498Szrj 240638fd1498Szrj 240738fd1498Szrj #define FASTCALL_PREFIX '@' 240838fd1498Szrj 240938fd1498Szrj #ifndef USED_FOR_TARGET 241038fd1498Szrj /* Structure describing stack frame layout. 241138fd1498Szrj Stack grows downward: 241238fd1498Szrj 241338fd1498Szrj [arguments] 241438fd1498Szrj <- ARG_POINTER 241538fd1498Szrj saved pc 241638fd1498Szrj 241738fd1498Szrj saved static chain if ix86_static_chain_on_stack 241838fd1498Szrj 241938fd1498Szrj saved frame pointer if frame_pointer_needed 242038fd1498Szrj <- HARD_FRAME_POINTER 242138fd1498Szrj [saved regs] 242238fd1498Szrj <- reg_save_offset 242338fd1498Szrj [padding0] 242438fd1498Szrj <- stack_realign_offset 242538fd1498Szrj [saved SSE regs] 242638fd1498Szrj OR 242738fd1498Szrj [stub-saved registers for ms x64 --> sysv clobbers 242838fd1498Szrj <- Start of out-of-line, stub-saved/restored regs 242938fd1498Szrj (see libgcc/config/i386/(sav|res)ms64*.S) 243038fd1498Szrj [XMM6-15] 243138fd1498Szrj [RSI] 243238fd1498Szrj [RDI] 243338fd1498Szrj [?RBX] only if RBX is clobbered 243438fd1498Szrj [?RBP] only if RBP and RBX are clobbered 243538fd1498Szrj [?R12] only if R12 and all previous regs are clobbered 243638fd1498Szrj [?R13] only if R13 and all previous regs are clobbered 243738fd1498Szrj [?R14] only if R14 and all previous regs are clobbered 243838fd1498Szrj [?R15] only if R15 and all previous regs are clobbered 243938fd1498Szrj <- end of stub-saved/restored regs 244038fd1498Szrj [padding1] 244138fd1498Szrj ] 244238fd1498Szrj <- sse_reg_save_offset 244338fd1498Szrj [padding2] 244438fd1498Szrj | <- FRAME_POINTER 244538fd1498Szrj [va_arg registers] | 244638fd1498Szrj | 244738fd1498Szrj [frame] | 244838fd1498Szrj | 244938fd1498Szrj [padding2] | = to_allocate 245038fd1498Szrj <- STACK_POINTER 245138fd1498Szrj */ 245238fd1498Szrj struct GTY(()) ix86_frame 245338fd1498Szrj { 245438fd1498Szrj int nsseregs; 245538fd1498Szrj int nregs; 245638fd1498Szrj int va_arg_size; 245738fd1498Szrj int red_zone_size; 245838fd1498Szrj int outgoing_arguments_size; 245938fd1498Szrj 246038fd1498Szrj /* The offsets relative to ARG_POINTER. */ 246138fd1498Szrj HOST_WIDE_INT frame_pointer_offset; 246238fd1498Szrj HOST_WIDE_INT hard_frame_pointer_offset; 246338fd1498Szrj HOST_WIDE_INT stack_pointer_offset; 246438fd1498Szrj HOST_WIDE_INT hfp_save_offset; 246538fd1498Szrj HOST_WIDE_INT reg_save_offset; 246638fd1498Szrj HOST_WIDE_INT stack_realign_allocate; 246738fd1498Szrj HOST_WIDE_INT stack_realign_offset; 246838fd1498Szrj HOST_WIDE_INT sse_reg_save_offset; 246938fd1498Szrj 247038fd1498Szrj /* When save_regs_using_mov is set, emit prologue using 247138fd1498Szrj move instead of push instructions. */ 247238fd1498Szrj bool save_regs_using_mov; 247338fd1498Szrj }; 247438fd1498Szrj 247538fd1498Szrj /* Machine specific frame tracking during prologue/epilogue generation. All 247638fd1498Szrj values are positive, but since the x86 stack grows downward, are subtratced 247738fd1498Szrj from the CFA to produce a valid address. */ 247838fd1498Szrj 247938fd1498Szrj struct GTY(()) machine_frame_state 248038fd1498Szrj { 248138fd1498Szrj /* This pair tracks the currently active CFA as reg+offset. When reg 248238fd1498Szrj is drap_reg, we don't bother trying to record here the real CFA when 248338fd1498Szrj it might really be a DW_CFA_def_cfa_expression. */ 248438fd1498Szrj rtx cfa_reg; 248538fd1498Szrj HOST_WIDE_INT cfa_offset; 248638fd1498Szrj 248738fd1498Szrj /* The current offset (canonically from the CFA) of ESP and EBP. 248838fd1498Szrj When stack frame re-alignment is active, these may not be relative 248938fd1498Szrj to the CFA. However, in all cases they are relative to the offsets 249038fd1498Szrj of the saved registers stored in ix86_frame. */ 249138fd1498Szrj HOST_WIDE_INT sp_offset; 249238fd1498Szrj HOST_WIDE_INT fp_offset; 249338fd1498Szrj 249438fd1498Szrj /* The size of the red-zone that may be assumed for the purposes of 249538fd1498Szrj eliding register restore notes in the epilogue. This may be zero 249638fd1498Szrj if no red-zone is in effect, or may be reduced from the real 249738fd1498Szrj red-zone value by a maximum runtime stack re-alignment value. */ 249838fd1498Szrj int red_zone_offset; 249938fd1498Szrj 250038fd1498Szrj /* Indicate whether each of ESP, EBP or DRAP currently holds a valid 250138fd1498Szrj value within the frame. If false then the offset above should be 250238fd1498Szrj ignored. Note that DRAP, if valid, *always* points to the CFA and 250338fd1498Szrj thus has an offset of zero. */ 250438fd1498Szrj BOOL_BITFIELD sp_valid : 1; 250538fd1498Szrj BOOL_BITFIELD fp_valid : 1; 250638fd1498Szrj BOOL_BITFIELD drap_valid : 1; 250738fd1498Szrj 250838fd1498Szrj /* Indicate whether the local stack frame has been re-aligned. When 250938fd1498Szrj set, the SP/FP offsets above are relative to the aligned frame 251038fd1498Szrj and not the CFA. */ 251138fd1498Szrj BOOL_BITFIELD realigned : 1; 251238fd1498Szrj 251338fd1498Szrj /* Indicates whether the stack pointer has been re-aligned. When set, 251438fd1498Szrj SP/FP continue to be relative to the CFA, but the stack pointer 251538fd1498Szrj should only be used for offsets > sp_realigned_offset, while 251638fd1498Szrj the frame pointer should be used for offsets <= sp_realigned_fp_last. 251738fd1498Szrj The flags realigned and sp_realigned are mutually exclusive. */ 251838fd1498Szrj BOOL_BITFIELD sp_realigned : 1; 251938fd1498Szrj 252038fd1498Szrj /* If sp_realigned is set, this is the last valid offset from the CFA 252138fd1498Szrj that can be used for access with the frame pointer. */ 252238fd1498Szrj HOST_WIDE_INT sp_realigned_fp_last; 252338fd1498Szrj 252438fd1498Szrj /* If sp_realigned is set, this is the offset from the CFA that the stack 252538fd1498Szrj pointer was realigned, and may or may not be equal to sp_realigned_fp_last. 252638fd1498Szrj Access via the stack pointer is only valid for offsets that are greater than 252738fd1498Szrj this value. */ 252838fd1498Szrj HOST_WIDE_INT sp_realigned_offset; 252938fd1498Szrj }; 253038fd1498Szrj 253138fd1498Szrj /* Private to winnt.c. */ 253238fd1498Szrj struct seh_frame_state; 253338fd1498Szrj 253438fd1498Szrj enum function_type 253538fd1498Szrj { 253638fd1498Szrj TYPE_UNKNOWN = 0, 253738fd1498Szrj TYPE_NORMAL, 253838fd1498Szrj /* The current function is an interrupt service routine with a 253938fd1498Szrj pointer argument as specified by the "interrupt" attribute. */ 254038fd1498Szrj TYPE_INTERRUPT, 254138fd1498Szrj /* The current function is an interrupt service routine with a 254238fd1498Szrj pointer argument and an integer argument as specified by the 254338fd1498Szrj "interrupt" attribute. */ 254438fd1498Szrj TYPE_EXCEPTION 254538fd1498Szrj }; 254638fd1498Szrj 254738fd1498Szrj struct GTY(()) machine_function { 254838fd1498Szrj struct stack_local_entry *stack_locals; 254938fd1498Szrj int varargs_gpr_size; 255038fd1498Szrj int varargs_fpr_size; 255138fd1498Szrj int optimize_mode_switching[MAX_386_ENTITIES]; 255238fd1498Szrj 255338fd1498Szrj /* Cached initial frame layout for the current function. */ 255438fd1498Szrj struct ix86_frame frame; 255538fd1498Szrj 255638fd1498Szrj /* For -fsplit-stack support: A stack local which holds a pointer to 255738fd1498Szrj the stack arguments for a function with a variable number of 255838fd1498Szrj arguments. This is set at the start of the function and is used 255938fd1498Szrj to initialize the overflow_arg_area field of the va_list 256038fd1498Szrj structure. */ 256138fd1498Szrj rtx split_stack_varargs_pointer; 256238fd1498Szrj 256338fd1498Szrj /* This value is used for amd64 targets and specifies the current abi 256438fd1498Szrj to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ 256538fd1498Szrj ENUM_BITFIELD(calling_abi) call_abi : 8; 256638fd1498Szrj 256738fd1498Szrj /* Nonzero if the function accesses a previous frame. */ 256838fd1498Szrj BOOL_BITFIELD accesses_prev_frame : 1; 256938fd1498Szrj 257038fd1498Szrj /* Set by ix86_compute_frame_layout and used by prologue/epilogue 257138fd1498Szrj expander to determine the style used. */ 257238fd1498Szrj BOOL_BITFIELD use_fast_prologue_epilogue : 1; 257338fd1498Szrj 257438fd1498Szrj /* Nonzero if the current function calls pc thunk and 257538fd1498Szrj must not use the red zone. */ 257638fd1498Szrj BOOL_BITFIELD pc_thunk_call_expanded : 1; 257738fd1498Szrj 257838fd1498Szrj /* If true, the current function needs the default PIC register, not 257938fd1498Szrj an alternate register (on x86) and must not use the red zone (on 258038fd1498Szrj x86_64), even if it's a leaf function. We don't want the 258138fd1498Szrj function to be regarded as non-leaf because TLS calls need not 258238fd1498Szrj affect register allocation. This flag is set when a TLS call 258338fd1498Szrj instruction is expanded within a function, and never reset, even 258438fd1498Szrj if all such instructions are optimized away. Use the 258538fd1498Szrj ix86_current_function_calls_tls_descriptor macro for a better 258638fd1498Szrj approximation. */ 258738fd1498Szrj BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; 258838fd1498Szrj 258938fd1498Szrj /* If true, the current function has a STATIC_CHAIN is placed on the 259038fd1498Szrj stack below the return address. */ 259138fd1498Szrj BOOL_BITFIELD static_chain_on_stack : 1; 259238fd1498Szrj 259338fd1498Szrj /* If true, it is safe to not save/restore DRAP register. */ 259438fd1498Szrj BOOL_BITFIELD no_drap_save_restore : 1; 259538fd1498Szrj 259638fd1498Szrj /* Function type. */ 259738fd1498Szrj ENUM_BITFIELD(function_type) func_type : 2; 259838fd1498Szrj 259938fd1498Szrj /* How to generate indirec branch. */ 260038fd1498Szrj ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3; 260138fd1498Szrj 260238fd1498Szrj /* If true, the current function has local indirect jumps, like 260338fd1498Szrj "indirect_jump" or "tablejump". */ 260438fd1498Szrj BOOL_BITFIELD has_local_indirect_jump : 1; 260538fd1498Szrj 260638fd1498Szrj /* How to generate function return. */ 260738fd1498Szrj ENUM_BITFIELD(indirect_branch) function_return_type : 3; 260838fd1498Szrj 260938fd1498Szrj /* If true, the current function is a function specified with 261038fd1498Szrj the "interrupt" or "no_caller_saved_registers" attribute. */ 261138fd1498Szrj BOOL_BITFIELD no_caller_saved_registers : 1; 261238fd1498Szrj 261338fd1498Szrj /* If true, there is register available for argument passing. This 261438fd1498Szrj is used only in ix86_function_ok_for_sibcall by 32-bit to determine 261538fd1498Szrj if there is scratch register available for indirect sibcall. In 261638fd1498Szrj 64-bit, rax, r10 and r11 are scratch registers which aren't used to 261738fd1498Szrj pass arguments and can be used for indirect sibcall. */ 261838fd1498Szrj BOOL_BITFIELD arg_reg_available : 1; 261938fd1498Szrj 262038fd1498Szrj /* If true, we're out-of-lining reg save/restore for regs clobbered 262138fd1498Szrj by 64-bit ms_abi functions calling a sysv_abi function. */ 262238fd1498Szrj BOOL_BITFIELD call_ms2sysv : 1; 262338fd1498Szrj 262438fd1498Szrj /* If true, the incoming 16-byte aligned stack has an offset (of 8) and 262538fd1498Szrj needs padding prior to out-of-line stub save/restore area. */ 262638fd1498Szrj BOOL_BITFIELD call_ms2sysv_pad_in : 1; 262738fd1498Szrj 262838fd1498Szrj /* This is the number of extra registers saved by stub (valid range is 262938fd1498Szrj 0-6). Each additional register is only saved/restored by the stubs 263038fd1498Szrj if all successive ones are. (Will always be zero when using a hard 263138fd1498Szrj frame pointer.) */ 263238fd1498Szrj unsigned int call_ms2sysv_extra_regs:3; 263338fd1498Szrj 263438fd1498Szrj /* Nonzero if the function places outgoing arguments on stack. */ 263538fd1498Szrj BOOL_BITFIELD outgoing_args_on_stack : 1; 263638fd1498Szrj 2637*58e805e6Szrj /* If true, ENDBR is queued at function entrance. */ 2638*58e805e6Szrj BOOL_BITFIELD endbr_queued_at_entrance : 1; 2639*58e805e6Szrj 264038fd1498Szrj /* The largest alignment, in bytes, of stack slot actually used. */ 264138fd1498Szrj unsigned int max_used_stack_alignment; 264238fd1498Szrj 264338fd1498Szrj /* During prologue/epilogue generation, the current frame state. 264438fd1498Szrj Otherwise, the frame state at the end of the prologue. */ 264538fd1498Szrj struct machine_frame_state fs; 264638fd1498Szrj 264738fd1498Szrj /* During SEH output, this is non-null. */ 264838fd1498Szrj struct seh_frame_state * GTY((skip(""))) seh; 264938fd1498Szrj }; 265038fd1498Szrj #endif 265138fd1498Szrj 265238fd1498Szrj #define ix86_stack_locals (cfun->machine->stack_locals) 265338fd1498Szrj #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) 265438fd1498Szrj #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) 265538fd1498Szrj #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 265638fd1498Szrj #define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded) 265738fd1498Szrj #define ix86_tls_descriptor_calls_expanded_in_cfun \ 265838fd1498Szrj (cfun->machine->tls_descriptor_call_expanded_p) 265938fd1498Szrj /* Since tls_descriptor_call_expanded is not cleared, even if all TLS 266038fd1498Szrj calls are optimized away, we try to detect cases in which it was 266138fd1498Szrj optimized away. Since such instructions (use (reg REG_SP)), we can 266238fd1498Szrj verify whether there's any such instruction live by testing that 266338fd1498Szrj REG_SP is live. */ 266438fd1498Szrj #define ix86_current_function_calls_tls_descriptor \ 266538fd1498Szrj (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) 266638fd1498Szrj #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) 266738fd1498Szrj #define ix86_red_zone_size (cfun->machine->frame.red_zone_size) 266838fd1498Szrj 266938fd1498Szrj /* Control behavior of x86_file_start. */ 267038fd1498Szrj #define X86_FILE_START_VERSION_DIRECTIVE false 267138fd1498Szrj #define X86_FILE_START_FLTUSED false 267238fd1498Szrj 267338fd1498Szrj /* Flag to mark data that is in the large address area. */ 267438fd1498Szrj #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 267538fd1498Szrj #define SYMBOL_REF_FAR_ADDR_P(X) \ 267638fd1498Szrj ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 267738fd1498Szrj 267838fd1498Szrj /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to 267938fd1498Szrj have defined always, to avoid ifdefing. */ 268038fd1498Szrj #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) 268138fd1498Szrj #define SYMBOL_REF_DLLIMPORT_P(X) \ 268238fd1498Szrj ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) 268338fd1498Szrj 268438fd1498Szrj #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) 268538fd1498Szrj #define SYMBOL_REF_DLLEXPORT_P(X) \ 268638fd1498Szrj ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) 268738fd1498Szrj 268838fd1498Szrj #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) 268938fd1498Szrj #define SYMBOL_REF_STUBVAR_P(X) \ 269038fd1498Szrj ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) 269138fd1498Szrj 269238fd1498Szrj extern void debug_ready_dispatch (void); 269338fd1498Szrj extern void debug_dispatch_window (int); 269438fd1498Szrj 269538fd1498Szrj /* The value at zero is only defined for the BMI instructions 269638fd1498Szrj LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ 269738fd1498Szrj #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 269838fd1498Szrj ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0) 269938fd1498Szrj #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 270038fd1498Szrj ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0) 270138fd1498Szrj 270238fd1498Szrj 270338fd1498Szrj /* Flags returned by ix86_get_callcvt (). */ 270438fd1498Szrj #define IX86_CALLCVT_CDECL 0x1 270538fd1498Szrj #define IX86_CALLCVT_STDCALL 0x2 270638fd1498Szrj #define IX86_CALLCVT_FASTCALL 0x4 270738fd1498Szrj #define IX86_CALLCVT_THISCALL 0x8 270838fd1498Szrj #define IX86_CALLCVT_REGPARM 0x10 270938fd1498Szrj #define IX86_CALLCVT_SSEREGPARM 0x20 271038fd1498Szrj 271138fd1498Szrj #define IX86_BASE_CALLCVT(FLAGS) \ 271238fd1498Szrj ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ 271338fd1498Szrj | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) 271438fd1498Szrj 271538fd1498Szrj #define RECIP_MASK_NONE 0x00 271638fd1498Szrj #define RECIP_MASK_DIV 0x01 271738fd1498Szrj #define RECIP_MASK_SQRT 0x02 271838fd1498Szrj #define RECIP_MASK_VEC_DIV 0x04 271938fd1498Szrj #define RECIP_MASK_VEC_SQRT 0x08 272038fd1498Szrj #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ 272138fd1498Szrj | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 272238fd1498Szrj #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 272338fd1498Szrj 272438fd1498Szrj #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) 272538fd1498Szrj #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) 272638fd1498Szrj #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) 272738fd1498Szrj #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) 272838fd1498Szrj 272938fd1498Szrj /* Use 128-bit AVX instructions in the auto-vectorizer. */ 273038fd1498Szrj #define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128) 273138fd1498Szrj /* Use 256-bit AVX instructions in the auto-vectorizer. */ 273238fd1498Szrj #define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \ 273338fd1498Szrj || prefer_vector_width_type == PVW_AVX256) 273438fd1498Szrj 273538fd1498Szrj #define TARGET_INDIRECT_BRANCH_REGISTER \ 273638fd1498Szrj (ix86_indirect_branch_register \ 273738fd1498Szrj || cfun->machine->indirect_branch_type != indirect_branch_keep) 273838fd1498Szrj 273938fd1498Szrj #define IX86_HLE_ACQUIRE (1 << 16) 274038fd1498Szrj #define IX86_HLE_RELEASE (1 << 17) 274138fd1498Szrj 274238fd1498Szrj /* For switching between functions with different target attributes. */ 274338fd1498Szrj #define SWITCHABLE_TARGET 1 274438fd1498Szrj 274538fd1498Szrj #define TARGET_SUPPORTS_WIDE_INT 1 274638fd1498Szrj 274738fd1498Szrj /* 274838fd1498Szrj Local variables: 274938fd1498Szrj version-control: t 275038fd1498Szrj End: 275138fd1498Szrj */ 2752