1*38fd1498Szrj /* Definitions of target machine for GCC for IA-32. 2*38fd1498Szrj Copyright (C) 1988-2018 Free Software Foundation, Inc. 3*38fd1498Szrj 4*38fd1498Szrj This file is part of GCC. 5*38fd1498Szrj 6*38fd1498Szrj GCC is free software; you can redistribute it and/or modify 7*38fd1498Szrj it under the terms of the GNU General Public License as published by 8*38fd1498Szrj the Free Software Foundation; either version 3, or (at your option) 9*38fd1498Szrj any later version. 10*38fd1498Szrj 11*38fd1498Szrj GCC is distributed in the hope that it will be useful, 12*38fd1498Szrj but WITHOUT ANY WARRANTY; without even the implied warranty of 13*38fd1498Szrj MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*38fd1498Szrj GNU General Public License for more details. 15*38fd1498Szrj 16*38fd1498Szrj Under Section 7 of GPL version 3, you are granted additional 17*38fd1498Szrj permissions described in the GCC Runtime Library Exception, version 18*38fd1498Szrj 3.1, as published by the Free Software Foundation. 19*38fd1498Szrj 20*38fd1498Szrj You should have received a copy of the GNU General Public License and 21*38fd1498Szrj a copy of the GCC Runtime Library Exception along with this program; 22*38fd1498Szrj see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 23*38fd1498Szrj <http://www.gnu.org/licenses/>. */ 24*38fd1498Szrj 25*38fd1498Szrj /* The purpose of this file is to define the characteristics of the i386, 26*38fd1498Szrj independent of assembler syntax or operating system. 27*38fd1498Szrj 28*38fd1498Szrj Three other files build on this one to describe a specific assembler syntax: 29*38fd1498Szrj bsd386.h, att386.h, and sun386.h. 30*38fd1498Szrj 31*38fd1498Szrj The actual tm.h file for a particular system should include 32*38fd1498Szrj this file, and then the file for the appropriate assembler syntax. 33*38fd1498Szrj 34*38fd1498Szrj Many macros that specify assembler syntax are omitted entirely from 35*38fd1498Szrj this file because they really belong in the files for particular 36*38fd1498Szrj assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 37*38fd1498Szrj ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 38*38fd1498Szrj that start with ASM_ or end in ASM_OP. */ 39*38fd1498Szrj 40*38fd1498Szrj /* Redefines for option macros. */ 41*38fd1498Szrj 42*38fd1498Szrj #define TARGET_64BIT TARGET_ISA_64BIT 43*38fd1498Szrj #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) 44*38fd1498Szrj #define TARGET_MMX TARGET_ISA_MMX 45*38fd1498Szrj #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) 46*38fd1498Szrj #define TARGET_3DNOW TARGET_ISA_3DNOW 47*38fd1498Szrj #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) 48*38fd1498Szrj #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A 49*38fd1498Szrj #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) 50*38fd1498Szrj #define TARGET_SSE TARGET_ISA_SSE 51*38fd1498Szrj #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) 52*38fd1498Szrj #define TARGET_SSE2 TARGET_ISA_SSE2 53*38fd1498Szrj #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) 54*38fd1498Szrj #define TARGET_SSE3 TARGET_ISA_SSE3 55*38fd1498Szrj #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) 56*38fd1498Szrj #define TARGET_SSSE3 TARGET_ISA_SSSE3 57*38fd1498Szrj #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) 58*38fd1498Szrj #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 59*38fd1498Szrj #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) 60*38fd1498Szrj #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 61*38fd1498Szrj #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) 62*38fd1498Szrj #define TARGET_AVX TARGET_ISA_AVX 63*38fd1498Szrj #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) 64*38fd1498Szrj #define TARGET_AVX2 TARGET_ISA_AVX2 65*38fd1498Szrj #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) 66*38fd1498Szrj #define TARGET_AVX512F TARGET_ISA_AVX512F 67*38fd1498Szrj #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) 68*38fd1498Szrj #define TARGET_AVX512PF TARGET_ISA_AVX512PF 69*38fd1498Szrj #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) 70*38fd1498Szrj #define TARGET_AVX512ER TARGET_ISA_AVX512ER 71*38fd1498Szrj #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) 72*38fd1498Szrj #define TARGET_AVX512CD TARGET_ISA_AVX512CD 73*38fd1498Szrj #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) 74*38fd1498Szrj #define TARGET_AVX512DQ TARGET_ISA_AVX512DQ 75*38fd1498Szrj #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) 76*38fd1498Szrj #define TARGET_AVX512BW TARGET_ISA_AVX512BW 77*38fd1498Szrj #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) 78*38fd1498Szrj #define TARGET_AVX512VL TARGET_ISA_AVX512VL 79*38fd1498Szrj #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) 80*38fd1498Szrj #define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI 81*38fd1498Szrj #define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) 82*38fd1498Szrj #define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA 83*38fd1498Szrj #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) 84*38fd1498Szrj #define TARGET_AVX5124FMAPS TARGET_ISA_AVX5124FMAPS 85*38fd1498Szrj #define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x) 86*38fd1498Szrj #define TARGET_AVX5124VNNIW TARGET_ISA_AVX5124VNNIW 87*38fd1498Szrj #define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x) 88*38fd1498Szrj #define TARGET_AVX512VBMI2 TARGET_ISA_AVX512VBMI2 89*38fd1498Szrj #define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x) 90*38fd1498Szrj #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ 91*38fd1498Szrj #define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x) 92*38fd1498Szrj #define TARGET_AVX512VNNI TARGET_ISA_AVX512VNNI 93*38fd1498Szrj #define TARGET_AVX512VNNI_P(x) TARGET_ISA_AVX512VNNI_P(x) 94*38fd1498Szrj #define TARGET_AVX512BITALG TARGET_ISA_AVX512BITALG 95*38fd1498Szrj #define TARGET_AVX512BITALG_P(x) TARGET_ISA_AVX512BITALG_P(x) 96*38fd1498Szrj #define TARGET_FMA TARGET_ISA_FMA 97*38fd1498Szrj #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) 98*38fd1498Szrj #define TARGET_SSE4A TARGET_ISA_SSE4A 99*38fd1498Szrj #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) 100*38fd1498Szrj #define TARGET_FMA4 TARGET_ISA_FMA4 101*38fd1498Szrj #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) 102*38fd1498Szrj #define TARGET_XOP TARGET_ISA_XOP 103*38fd1498Szrj #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) 104*38fd1498Szrj #define TARGET_LWP TARGET_ISA_LWP 105*38fd1498Szrj #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) 106*38fd1498Szrj #define TARGET_ABM TARGET_ISA_ABM 107*38fd1498Szrj #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) 108*38fd1498Szrj #define TARGET_PCONFIG TARGET_ISA_PCONFIG 109*38fd1498Szrj #define TARGET_PCONFIG_P(x) TARGET_ISA_PCONFIG_P(x) 110*38fd1498Szrj #define TARGET_WBNOINVD TARGET_ISA_WBNOINVD 111*38fd1498Szrj #define TARGET_WBNOINVD_P(x) TARGET_ISA_WBNOINVD_P(x) 112*38fd1498Szrj #define TARGET_SGX TARGET_ISA_SGX 113*38fd1498Szrj #define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x) 114*38fd1498Szrj #define TARGET_RDPID TARGET_ISA_RDPID 115*38fd1498Szrj #define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x) 116*38fd1498Szrj #define TARGET_GFNI TARGET_ISA_GFNI 117*38fd1498Szrj #define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x) 118*38fd1498Szrj #define TARGET_VAES TARGET_ISA_VAES 119*38fd1498Szrj #define TARGET_VAES_P(x) TARGET_ISA_VAES_P(x) 120*38fd1498Szrj #define TARGET_VPCLMULQDQ TARGET_ISA_VPCLMULQDQ 121*38fd1498Szrj #define TARGET_VPCLMULQDQ_P(x) TARGET_ISA_VPCLMULQDQ_P(x) 122*38fd1498Szrj #define TARGET_BMI TARGET_ISA_BMI 123*38fd1498Szrj #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) 124*38fd1498Szrj #define TARGET_BMI2 TARGET_ISA_BMI2 125*38fd1498Szrj #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) 126*38fd1498Szrj #define TARGET_LZCNT TARGET_ISA_LZCNT 127*38fd1498Szrj #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) 128*38fd1498Szrj #define TARGET_TBM TARGET_ISA_TBM 129*38fd1498Szrj #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) 130*38fd1498Szrj #define TARGET_POPCNT TARGET_ISA_POPCNT 131*38fd1498Szrj #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) 132*38fd1498Szrj #define TARGET_SAHF TARGET_ISA_SAHF 133*38fd1498Szrj #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) 134*38fd1498Szrj #define TARGET_MOVBE TARGET_ISA_MOVBE 135*38fd1498Szrj #define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x) 136*38fd1498Szrj #define TARGET_CRC32 TARGET_ISA_CRC32 137*38fd1498Szrj #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) 138*38fd1498Szrj #define TARGET_AES TARGET_ISA_AES 139*38fd1498Szrj #define TARGET_AES_P(x) TARGET_ISA_AES_P(x) 140*38fd1498Szrj #define TARGET_SHA TARGET_ISA_SHA 141*38fd1498Szrj #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) 142*38fd1498Szrj #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT 143*38fd1498Szrj #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) 144*38fd1498Szrj #define TARGET_CLZERO TARGET_ISA_CLZERO 145*38fd1498Szrj #define TARGET_CLZERO_P(x) TARGET_ISA_CLZERO_P(x) 146*38fd1498Szrj #define TARGET_XSAVEC TARGET_ISA_XSAVEC 147*38fd1498Szrj #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) 148*38fd1498Szrj #define TARGET_XSAVES TARGET_ISA_XSAVES 149*38fd1498Szrj #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) 150*38fd1498Szrj #define TARGET_PCLMUL TARGET_ISA_PCLMUL 151*38fd1498Szrj #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) 152*38fd1498Szrj #define TARGET_CMPXCHG16B TARGET_ISA_CX16 153*38fd1498Szrj #define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x) 154*38fd1498Szrj #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE 155*38fd1498Szrj #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) 156*38fd1498Szrj #define TARGET_RDRND TARGET_ISA_RDRND 157*38fd1498Szrj #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) 158*38fd1498Szrj #define TARGET_F16C TARGET_ISA_F16C 159*38fd1498Szrj #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) 160*38fd1498Szrj #define TARGET_RTM TARGET_ISA_RTM 161*38fd1498Szrj #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) 162*38fd1498Szrj #define TARGET_HLE TARGET_ISA_HLE 163*38fd1498Szrj #define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x) 164*38fd1498Szrj #define TARGET_RDSEED TARGET_ISA_RDSEED 165*38fd1498Szrj #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) 166*38fd1498Szrj #define TARGET_PRFCHW TARGET_ISA_PRFCHW 167*38fd1498Szrj #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) 168*38fd1498Szrj #define TARGET_ADX TARGET_ISA_ADX 169*38fd1498Szrj #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) 170*38fd1498Szrj #define TARGET_FXSR TARGET_ISA_FXSR 171*38fd1498Szrj #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) 172*38fd1498Szrj #define TARGET_XSAVE TARGET_ISA_XSAVE 173*38fd1498Szrj #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) 174*38fd1498Szrj #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT 175*38fd1498Szrj #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) 176*38fd1498Szrj #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 177*38fd1498Szrj #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) 178*38fd1498Szrj #define TARGET_MPX TARGET_ISA_MPX 179*38fd1498Szrj #define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x) 180*38fd1498Szrj #define TARGET_CLWB TARGET_ISA_CLWB 181*38fd1498Szrj #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) 182*38fd1498Szrj #define TARGET_MWAITX TARGET_ISA_MWAITX 183*38fd1498Szrj #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) 184*38fd1498Szrj #define TARGET_PKU TARGET_ISA_PKU 185*38fd1498Szrj #define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) 186*38fd1498Szrj #define TARGET_SHSTK TARGET_ISA_SHSTK 187*38fd1498Szrj #define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x) 188*38fd1498Szrj #define TARGET_MOVDIRI TARGET_ISA_MOVDIRI 189*38fd1498Szrj #define TARGET_MOVDIRI_P(x) TARGET_ISA_MOVDIRI_P(x) 190*38fd1498Szrj #define TARGET_MOVDIR64B TARGET_ISA_MOVDIR64B 191*38fd1498Szrj #define TARGET_MOVDIR64B_P(x) TARGET_ISA_MOVDIR64B_P(x) 192*38fd1498Szrj 193*38fd1498Szrj #define TARGET_LP64 TARGET_ABI_64 194*38fd1498Szrj #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) 195*38fd1498Szrj #define TARGET_X32 TARGET_ABI_X32 196*38fd1498Szrj #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) 197*38fd1498Szrj #define TARGET_16BIT TARGET_CODE16 198*38fd1498Szrj #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) 199*38fd1498Szrj 200*38fd1498Szrj #include "config/vxworks-dummy.h" 201*38fd1498Szrj 202*38fd1498Szrj #include "config/i386/i386-opts.h" 203*38fd1498Szrj 204*38fd1498Szrj #define MAX_STRINGOP_ALGS 4 205*38fd1498Szrj 206*38fd1498Szrj /* Specify what algorithm to use for stringops on known size. 207*38fd1498Szrj When size is unknown, the UNKNOWN_SIZE alg is used. When size is 208*38fd1498Szrj known at compile time or estimated via feedback, the SIZE array 209*38fd1498Szrj is walked in order until MAX is greater then the estimate (or -1 210*38fd1498Szrj means infinity). Corresponding ALG is used then. 211*38fd1498Szrj When NOALIGN is true the code guaranting the alignment of the memory 212*38fd1498Szrj block is skipped. 213*38fd1498Szrj 214*38fd1498Szrj For example initializer: 215*38fd1498Szrj {{256, loop}, {-1, rep_prefix_4_byte}} 216*38fd1498Szrj will use loop for blocks smaller or equal to 256 bytes, rep prefix will 217*38fd1498Szrj be used otherwise. */ 218*38fd1498Szrj struct stringop_algs 219*38fd1498Szrj { 220*38fd1498Szrj const enum stringop_alg unknown_size; 221*38fd1498Szrj const struct stringop_strategy { 222*38fd1498Szrj const int max; 223*38fd1498Szrj const enum stringop_alg alg; 224*38fd1498Szrj int noalign; 225*38fd1498Szrj } size [MAX_STRINGOP_ALGS]; 226*38fd1498Szrj }; 227*38fd1498Szrj 228*38fd1498Szrj /* Define the specific costs for a given cpu */ 229*38fd1498Szrj 230*38fd1498Szrj struct processor_costs { 231*38fd1498Szrj const int add; /* cost of an add instruction */ 232*38fd1498Szrj const int lea; /* cost of a lea instruction */ 233*38fd1498Szrj const int shift_var; /* variable shift costs */ 234*38fd1498Szrj const int shift_const; /* constant shift costs */ 235*38fd1498Szrj const int mult_init[5]; /* cost of starting a multiply 236*38fd1498Szrj in QImode, HImode, SImode, DImode, TImode*/ 237*38fd1498Szrj const int mult_bit; /* cost of multiply per each bit set */ 238*38fd1498Szrj const int divide[5]; /* cost of a divide/mod 239*38fd1498Szrj in QImode, HImode, SImode, DImode, TImode*/ 240*38fd1498Szrj int movsx; /* The cost of movsx operation. */ 241*38fd1498Szrj int movzx; /* The cost of movzx operation. */ 242*38fd1498Szrj const int large_insn; /* insns larger than this cost more */ 243*38fd1498Szrj const int move_ratio; /* The threshold of number of scalar 244*38fd1498Szrj memory-to-memory move insns. */ 245*38fd1498Szrj const int movzbl_load; /* cost of loading using movzbl */ 246*38fd1498Szrj const int int_load[3]; /* cost of loading integer registers 247*38fd1498Szrj in QImode, HImode and SImode relative 248*38fd1498Szrj to reg-reg move (2). */ 249*38fd1498Szrj const int int_store[3]; /* cost of storing integer register 250*38fd1498Szrj in QImode, HImode and SImode */ 251*38fd1498Szrj const int fp_move; /* cost of reg,reg fld/fst */ 252*38fd1498Szrj const int fp_load[3]; /* cost of loading FP register 253*38fd1498Szrj in SFmode, DFmode and XFmode */ 254*38fd1498Szrj const int fp_store[3]; /* cost of storing FP register 255*38fd1498Szrj in SFmode, DFmode and XFmode */ 256*38fd1498Szrj const int mmx_move; /* cost of moving MMX register. */ 257*38fd1498Szrj const int mmx_load[2]; /* cost of loading MMX register 258*38fd1498Szrj in SImode and DImode */ 259*38fd1498Szrj const int mmx_store[2]; /* cost of storing MMX register 260*38fd1498Szrj in SImode and DImode */ 261*38fd1498Szrj const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */ 262*38fd1498Szrj zmm_move; 263*38fd1498Szrj const int sse_load[5]; /* cost of loading SSE register 264*38fd1498Szrj in 32bit, 64bit, 128bit, 256bit and 512bit */ 265*38fd1498Szrj const int sse_unaligned_load[5];/* cost of unaligned load. */ 266*38fd1498Szrj const int sse_store[5]; /* cost of storing SSE register 267*38fd1498Szrj in SImode, DImode and TImode. */ 268*38fd1498Szrj const int sse_unaligned_store[5];/* cost of unaligned store. */ 269*38fd1498Szrj const int mmxsse_to_integer; /* cost of moving mmxsse register to 270*38fd1498Szrj integer. */ 271*38fd1498Szrj const int ssemmx_to_integer; /* cost of moving integer to mmxsse register. */ 272*38fd1498Szrj const int gather_static, gather_per_elt; /* Cost of gather load is computed 273*38fd1498Szrj as static + per_item * nelts. */ 274*38fd1498Szrj const int scatter_static, scatter_per_elt; /* Cost of gather store is 275*38fd1498Szrj computed as static + per_item * nelts. */ 276*38fd1498Szrj const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 277*38fd1498Szrj const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 278*38fd1498Szrj const int prefetch_block; /* bytes moved to cache for prefetch. */ 279*38fd1498Szrj const int simultaneous_prefetches; /* number of parallel prefetch 280*38fd1498Szrj operations. */ 281*38fd1498Szrj const int branch_cost; /* Default value for BRANCH_COST. */ 282*38fd1498Szrj const int fadd; /* cost of FADD and FSUB instructions. */ 283*38fd1498Szrj const int fmul; /* cost of FMUL instruction. */ 284*38fd1498Szrj const int fdiv; /* cost of FDIV instruction. */ 285*38fd1498Szrj const int fabs; /* cost of FABS instruction. */ 286*38fd1498Szrj const int fchs; /* cost of FCHS instruction. */ 287*38fd1498Szrj const int fsqrt; /* cost of FSQRT instruction. */ 288*38fd1498Szrj /* Specify what algorithm 289*38fd1498Szrj to use for stringops on unknown size. */ 290*38fd1498Szrj const int sse_op; /* cost of cheap SSE instruction. */ 291*38fd1498Szrj const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */ 292*38fd1498Szrj const int mulss; /* cost of MULSS instructions. */ 293*38fd1498Szrj const int mulsd; /* cost of MULSD instructions. */ 294*38fd1498Szrj const int fmass; /* cost of FMASS instructions. */ 295*38fd1498Szrj const int fmasd; /* cost of FMASD instructions. */ 296*38fd1498Szrj const int divss; /* cost of DIVSS instructions. */ 297*38fd1498Szrj const int divsd; /* cost of DIVSD instructions. */ 298*38fd1498Szrj const int sqrtss; /* cost of SQRTSS instructions. */ 299*38fd1498Szrj const int sqrtsd; /* cost of SQRTSD instructions. */ 300*38fd1498Szrj const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp; 301*38fd1498Szrj /* Specify reassociation width for integer, 302*38fd1498Szrj fp, vector integer and vector fp 303*38fd1498Szrj operations. Generally should correspond 304*38fd1498Szrj to number of instructions executed in 305*38fd1498Szrj parallel. See also 306*38fd1498Szrj ix86_reassociation_width. */ 307*38fd1498Szrj struct stringop_algs *memcpy, *memset; 308*38fd1498Szrj const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 309*38fd1498Szrj cost model. */ 310*38fd1498Szrj const int cond_not_taken_branch_cost;/* Cost of not taken branch for 311*38fd1498Szrj vectorizer cost model. */ 312*38fd1498Szrj }; 313*38fd1498Szrj 314*38fd1498Szrj extern const struct processor_costs *ix86_cost; 315*38fd1498Szrj extern const struct processor_costs ix86_size_cost; 316*38fd1498Szrj 317*38fd1498Szrj #define ix86_cur_cost() \ 318*38fd1498Szrj (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) 319*38fd1498Szrj 320*38fd1498Szrj /* Macros used in the machine description to test the flags. */ 321*38fd1498Szrj 322*38fd1498Szrj /* configure can arrange to change it. */ 323*38fd1498Szrj 324*38fd1498Szrj #ifndef TARGET_CPU_DEFAULT 325*38fd1498Szrj #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC 326*38fd1498Szrj #endif 327*38fd1498Szrj 328*38fd1498Szrj #ifndef TARGET_FPMATH_DEFAULT 329*38fd1498Szrj #define TARGET_FPMATH_DEFAULT \ 330*38fd1498Szrj (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 331*38fd1498Szrj #endif 332*38fd1498Szrj 333*38fd1498Szrj #ifndef TARGET_FPMATH_DEFAULT_P 334*38fd1498Szrj #define TARGET_FPMATH_DEFAULT_P(x) \ 335*38fd1498Szrj (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) 336*38fd1498Szrj #endif 337*38fd1498Szrj 338*38fd1498Szrj /* If the i387 is disabled or -miamcu is used , then do not return 339*38fd1498Szrj values in it. */ 340*38fd1498Szrj #define TARGET_FLOAT_RETURNS_IN_80387 \ 341*38fd1498Szrj (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU) 342*38fd1498Szrj #define TARGET_FLOAT_RETURNS_IN_80387_P(x) \ 343*38fd1498Szrj (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x)) 344*38fd1498Szrj 345*38fd1498Szrj /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 346*38fd1498Szrj compile-time constant. */ 347*38fd1498Szrj #ifdef IN_LIBGCC2 348*38fd1498Szrj #undef TARGET_64BIT 349*38fd1498Szrj #ifdef __x86_64__ 350*38fd1498Szrj #define TARGET_64BIT 1 351*38fd1498Szrj #else 352*38fd1498Szrj #define TARGET_64BIT 0 353*38fd1498Szrj #endif 354*38fd1498Szrj #else 355*38fd1498Szrj #ifndef TARGET_BI_ARCH 356*38fd1498Szrj #undef TARGET_64BIT 357*38fd1498Szrj #undef TARGET_64BIT_P 358*38fd1498Szrj #if TARGET_64BIT_DEFAULT 359*38fd1498Szrj #define TARGET_64BIT 1 360*38fd1498Szrj #define TARGET_64BIT_P(x) 1 361*38fd1498Szrj #else 362*38fd1498Szrj #define TARGET_64BIT 0 363*38fd1498Szrj #define TARGET_64BIT_P(x) 0 364*38fd1498Szrj #endif 365*38fd1498Szrj #endif 366*38fd1498Szrj #endif 367*38fd1498Szrj 368*38fd1498Szrj #define HAS_LONG_COND_BRANCH 1 369*38fd1498Szrj #define HAS_LONG_UNCOND_BRANCH 1 370*38fd1498Szrj 371*38fd1498Szrj #define TARGET_386 (ix86_tune == PROCESSOR_I386) 372*38fd1498Szrj #define TARGET_486 (ix86_tune == PROCESSOR_I486) 373*38fd1498Szrj #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 374*38fd1498Szrj #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 375*38fd1498Szrj #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 376*38fd1498Szrj #define TARGET_K6 (ix86_tune == PROCESSOR_K6) 377*38fd1498Szrj #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 378*38fd1498Szrj #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 379*38fd1498Szrj #define TARGET_K8 (ix86_tune == PROCESSOR_K8) 380*38fd1498Szrj #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 381*38fd1498Szrj #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 382*38fd1498Szrj #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 383*38fd1498Szrj #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) 384*38fd1498Szrj #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) 385*38fd1498Szrj #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) 386*38fd1498Szrj #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) 387*38fd1498Szrj #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) 388*38fd1498Szrj #define TARGET_KNL (ix86_tune == PROCESSOR_KNL) 389*38fd1498Szrj #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) 390*38fd1498Szrj #define TARGET_SKYLAKE (ix86_tune == PROCESSOR_SKYLAKE) 391*38fd1498Szrj #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) 392*38fd1498Szrj #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE) 393*38fd1498Szrj #define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT) 394*38fd1498Szrj #define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER) 395*38fd1498Szrj #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) 396*38fd1498Szrj #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) 397*38fd1498Szrj #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 398*38fd1498Szrj #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) 399*38fd1498Szrj #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) 400*38fd1498Szrj #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) 401*38fd1498Szrj #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) 402*38fd1498Szrj #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) 403*38fd1498Szrj #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) 404*38fd1498Szrj #define TARGET_ZNVER1 (ix86_tune == PROCESSOR_ZNVER1) 405*38fd1498Szrj 406*38fd1498Szrj /* Feature tests against the various tunings. */ 407*38fd1498Szrj enum ix86_tune_indices { 408*38fd1498Szrj #undef DEF_TUNE 409*38fd1498Szrj #define DEF_TUNE(tune, name, selector) tune, 410*38fd1498Szrj #include "x86-tune.def" 411*38fd1498Szrj #undef DEF_TUNE 412*38fd1498Szrj X86_TUNE_LAST 413*38fd1498Szrj }; 414*38fd1498Szrj 415*38fd1498Szrj extern unsigned char ix86_tune_features[X86_TUNE_LAST]; 416*38fd1498Szrj 417*38fd1498Szrj #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] 418*38fd1498Szrj #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] 419*38fd1498Szrj #define TARGET_ZERO_EXTEND_WITH_AND \ 420*38fd1498Szrj ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] 421*38fd1498Szrj #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] 422*38fd1498Szrj #define TARGET_BRANCH_PREDICTION_HINTS \ 423*38fd1498Szrj ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] 424*38fd1498Szrj #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] 425*38fd1498Szrj #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] 426*38fd1498Szrj #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] 427*38fd1498Szrj #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] 428*38fd1498Szrj #define TARGET_PARTIAL_FLAG_REG_STALL \ 429*38fd1498Szrj ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] 430*38fd1498Szrj #define TARGET_LCP_STALL \ 431*38fd1498Szrj ix86_tune_features[X86_TUNE_LCP_STALL] 432*38fd1498Szrj #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] 433*38fd1498Szrj #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] 434*38fd1498Szrj #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] 435*38fd1498Szrj #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] 436*38fd1498Szrj #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] 437*38fd1498Szrj #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] 438*38fd1498Szrj #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] 439*38fd1498Szrj #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] 440*38fd1498Szrj #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] 441*38fd1498Szrj #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] 442*38fd1498Szrj #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] 443*38fd1498Szrj #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ 444*38fd1498Szrj ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] 445*38fd1498Szrj #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] 446*38fd1498Szrj #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] 447*38fd1498Szrj #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] 448*38fd1498Szrj #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] 449*38fd1498Szrj #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] 450*38fd1498Szrj #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] 451*38fd1498Szrj #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] 452*38fd1498Szrj #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] 453*38fd1498Szrj #define TARGET_INTEGER_DFMODE_MOVES \ 454*38fd1498Szrj ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] 455*38fd1498Szrj #define TARGET_PARTIAL_REG_DEPENDENCY \ 456*38fd1498Szrj ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] 457*38fd1498Szrj #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 458*38fd1498Szrj ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] 459*38fd1498Szrj #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 460*38fd1498Szrj ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] 461*38fd1498Szrj #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ 462*38fd1498Szrj ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] 463*38fd1498Szrj #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ 464*38fd1498Szrj ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] 465*38fd1498Szrj #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] 466*38fd1498Szrj #define TARGET_SSE_TYPELESS_STORES \ 467*38fd1498Szrj ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] 468*38fd1498Szrj #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] 469*38fd1498Szrj #define TARGET_MEMORY_MISMATCH_STALL \ 470*38fd1498Szrj ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] 471*38fd1498Szrj #define TARGET_PROLOGUE_USING_MOVE \ 472*38fd1498Szrj ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] 473*38fd1498Szrj #define TARGET_EPILOGUE_USING_MOVE \ 474*38fd1498Szrj ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] 475*38fd1498Szrj #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] 476*38fd1498Szrj #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] 477*38fd1498Szrj #define TARGET_INTER_UNIT_MOVES_TO_VEC \ 478*38fd1498Szrj ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] 479*38fd1498Szrj #define TARGET_INTER_UNIT_MOVES_FROM_VEC \ 480*38fd1498Szrj ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] 481*38fd1498Szrj #define TARGET_INTER_UNIT_CONVERSIONS \ 482*38fd1498Szrj ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] 483*38fd1498Szrj #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] 484*38fd1498Szrj #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] 485*38fd1498Szrj #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] 486*38fd1498Szrj #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] 487*38fd1498Szrj #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] 488*38fd1498Szrj #define TARGET_PAD_SHORT_FUNCTION \ 489*38fd1498Szrj ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] 490*38fd1498Szrj #define TARGET_EXT_80387_CONSTANTS \ 491*38fd1498Szrj ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] 492*38fd1498Szrj #define TARGET_AVOID_VECTOR_DECODE \ 493*38fd1498Szrj ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] 494*38fd1498Szrj #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ 495*38fd1498Szrj ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] 496*38fd1498Szrj #define TARGET_SLOW_IMUL_IMM32_MEM \ 497*38fd1498Szrj ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] 498*38fd1498Szrj #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] 499*38fd1498Szrj #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] 500*38fd1498Szrj #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] 501*38fd1498Szrj #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] 502*38fd1498Szrj #define TARGET_USE_VECTOR_FP_CONVERTS \ 503*38fd1498Szrj ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] 504*38fd1498Szrj #define TARGET_USE_VECTOR_CONVERTS \ 505*38fd1498Szrj ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 506*38fd1498Szrj #define TARGET_SLOW_PSHUFB \ 507*38fd1498Szrj ix86_tune_features[X86_TUNE_SLOW_PSHUFB] 508*38fd1498Szrj #define TARGET_AVOID_4BYTE_PREFIXES \ 509*38fd1498Szrj ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] 510*38fd1498Szrj #define TARGET_USE_GATHER \ 511*38fd1498Szrj ix86_tune_features[X86_TUNE_USE_GATHER] 512*38fd1498Szrj #define TARGET_FUSE_CMP_AND_BRANCH_32 \ 513*38fd1498Szrj ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] 514*38fd1498Szrj #define TARGET_FUSE_CMP_AND_BRANCH_64 \ 515*38fd1498Szrj ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] 516*38fd1498Szrj #define TARGET_FUSE_CMP_AND_BRANCH \ 517*38fd1498Szrj (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ 518*38fd1498Szrj : TARGET_FUSE_CMP_AND_BRANCH_32) 519*38fd1498Szrj #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ 520*38fd1498Szrj ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] 521*38fd1498Szrj #define TARGET_FUSE_ALU_AND_BRANCH \ 522*38fd1498Szrj ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] 523*38fd1498Szrj #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] 524*38fd1498Szrj #define TARGET_AVOID_LEA_FOR_ADDR \ 525*38fd1498Szrj ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] 526*38fd1498Szrj #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ 527*38fd1498Szrj ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] 528*38fd1498Szrj #define TARGET_AVX128_OPTIMAL \ 529*38fd1498Szrj ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] 530*38fd1498Szrj #define TARGET_GENERAL_REGS_SSE_SPILL \ 531*38fd1498Szrj ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] 532*38fd1498Szrj #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ 533*38fd1498Szrj ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] 534*38fd1498Szrj #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ 535*38fd1498Szrj ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] 536*38fd1498Szrj #define TARGET_ADJUST_UNROLL \ 537*38fd1498Szrj ix86_tune_features[X86_TUNE_ADJUST_UNROLL] 538*38fd1498Szrj #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ 539*38fd1498Szrj ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] 540*38fd1498Szrj #define TARGET_ONE_IF_CONV_INSN \ 541*38fd1498Szrj ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] 542*38fd1498Szrj #define TARGET_EMIT_VZEROUPPER \ 543*38fd1498Szrj ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER] 544*38fd1498Szrj 545*38fd1498Szrj /* Feature tests against the various architecture variations. */ 546*38fd1498Szrj enum ix86_arch_indices { 547*38fd1498Szrj X86_ARCH_CMOV, 548*38fd1498Szrj X86_ARCH_CMPXCHG, 549*38fd1498Szrj X86_ARCH_CMPXCHG8B, 550*38fd1498Szrj X86_ARCH_XADD, 551*38fd1498Szrj X86_ARCH_BSWAP, 552*38fd1498Szrj 553*38fd1498Szrj X86_ARCH_LAST 554*38fd1498Szrj }; 555*38fd1498Szrj 556*38fd1498Szrj extern unsigned char ix86_arch_features[X86_ARCH_LAST]; 557*38fd1498Szrj 558*38fd1498Szrj #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] 559*38fd1498Szrj #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] 560*38fd1498Szrj #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] 561*38fd1498Szrj #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] 562*38fd1498Szrj #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] 563*38fd1498Szrj 564*38fd1498Szrj /* For sane SSE instruction set generation we need fcomi instruction. 565*38fd1498Szrj It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic 566*38fd1498Szrj expands to a sequence that includes conditional move. */ 567*38fd1498Szrj #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) 568*38fd1498Szrj 569*38fd1498Szrj #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 570*38fd1498Szrj 571*38fd1498Szrj extern unsigned char x86_prefetch_sse; 572*38fd1498Szrj #define TARGET_PREFETCH_SSE x86_prefetch_sse 573*38fd1498Szrj 574*38fd1498Szrj #define ASSEMBLER_DIALECT (ix86_asm_dialect) 575*38fd1498Szrj 576*38fd1498Szrj #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 577*38fd1498Szrj #define TARGET_MIX_SSE_I387 \ 578*38fd1498Szrj ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) 579*38fd1498Szrj 580*38fd1498Szrj #define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE) 581*38fd1498Szrj #define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE) 582*38fd1498Szrj #define TARGET_HARD_XF_REGS (TARGET_80387) 583*38fd1498Szrj 584*38fd1498Szrj #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 585*38fd1498Szrj #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 586*38fd1498Szrj #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 587*38fd1498Szrj #define TARGET_SUN_TLS 0 588*38fd1498Szrj 589*38fd1498Szrj #ifndef TARGET_64BIT_DEFAULT 590*38fd1498Szrj #define TARGET_64BIT_DEFAULT 0 591*38fd1498Szrj #endif 592*38fd1498Szrj #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 593*38fd1498Szrj #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 594*38fd1498Szrj #endif 595*38fd1498Szrj 596*38fd1498Szrj #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) 597*38fd1498Szrj #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) 598*38fd1498Szrj 599*38fd1498Szrj /* Fence to use after loop using storent. */ 600*38fd1498Szrj 601*38fd1498Szrj extern tree x86_mfence; 602*38fd1498Szrj #define FENCE_FOLLOWING_MOVNT x86_mfence 603*38fd1498Szrj 604*38fd1498Szrj /* Once GDB has been enhanced to deal with functions without frame 605*38fd1498Szrj pointers, we can change this to allow for elimination of 606*38fd1498Szrj the frame pointer in leaf functions. */ 607*38fd1498Szrj #define TARGET_DEFAULT 0 608*38fd1498Szrj 609*38fd1498Szrj /* Extra bits to force. */ 610*38fd1498Szrj #define TARGET_SUBTARGET_DEFAULT 0 611*38fd1498Szrj #define TARGET_SUBTARGET_ISA_DEFAULT 0 612*38fd1498Szrj 613*38fd1498Szrj /* Extra bits to force on w/ 32-bit mode. */ 614*38fd1498Szrj #define TARGET_SUBTARGET32_DEFAULT 0 615*38fd1498Szrj #define TARGET_SUBTARGET32_ISA_DEFAULT 0 616*38fd1498Szrj 617*38fd1498Szrj /* Extra bits to force on w/ 64-bit mode. */ 618*38fd1498Szrj #define TARGET_SUBTARGET64_DEFAULT 0 619*38fd1498Szrj #define TARGET_SUBTARGET64_ISA_DEFAULT 0 620*38fd1498Szrj 621*38fd1498Szrj /* Replace MACH-O, ifdefs by in-line tests, where possible. 622*38fd1498Szrj (a) Macros defined in config/i386/darwin.h */ 623*38fd1498Szrj #define TARGET_MACHO 0 624*38fd1498Szrj #define TARGET_MACHO_BRANCH_ISLANDS 0 625*38fd1498Szrj #define MACHOPIC_ATT_STUB 0 626*38fd1498Szrj /* (b) Macros defined in config/darwin.h */ 627*38fd1498Szrj #define MACHO_DYNAMIC_NO_PIC_P 0 628*38fd1498Szrj #define MACHOPIC_INDIRECT 0 629*38fd1498Szrj #define MACHOPIC_PURE 0 630*38fd1498Szrj 631*38fd1498Szrj /* For the RDOS */ 632*38fd1498Szrj #define TARGET_RDOS 0 633*38fd1498Szrj 634*38fd1498Szrj /* For the Windows 64-bit ABI. */ 635*38fd1498Szrj #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 636*38fd1498Szrj 637*38fd1498Szrj /* For the Windows 32-bit ABI. */ 638*38fd1498Szrj #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 639*38fd1498Szrj 640*38fd1498Szrj /* This is re-defined by cygming.h. */ 641*38fd1498Szrj #define TARGET_SEH 0 642*38fd1498Szrj 643*38fd1498Szrj /* The default abi used by target. */ 644*38fd1498Szrj #define DEFAULT_ABI SYSV_ABI 645*38fd1498Szrj 646*38fd1498Szrj /* The default TLS segment register used by target. */ 647*38fd1498Szrj #define DEFAULT_TLS_SEG_REG \ 648*38fd1498Szrj (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS) 649*38fd1498Szrj 650*38fd1498Szrj /* Subtargets may reset this to 1 in order to enable 96-bit long double 651*38fd1498Szrj with the rounding mode forced to 53 bits. */ 652*38fd1498Szrj #define TARGET_96_ROUND_53_LONG_DOUBLE 0 653*38fd1498Szrj 654*38fd1498Szrj /* -march=native handling only makes sense with compiler running on 655*38fd1498Szrj an x86 or x86_64 chip. If changing this condition, also change 656*38fd1498Szrj the condition in driver-i386.c. */ 657*38fd1498Szrj #if defined(__i386__) || defined(__x86_64__) 658*38fd1498Szrj /* In driver-i386.c. */ 659*38fd1498Szrj extern const char *host_detect_local_cpu (int argc, const char **argv); 660*38fd1498Szrj #define EXTRA_SPEC_FUNCTIONS \ 661*38fd1498Szrj { "local_cpu_detect", host_detect_local_cpu }, 662*38fd1498Szrj #define HAVE_LOCAL_CPU_DETECT 663*38fd1498Szrj #endif 664*38fd1498Szrj 665*38fd1498Szrj #if TARGET_64BIT_DEFAULT 666*38fd1498Szrj #define OPT_ARCH64 "!m32" 667*38fd1498Szrj #define OPT_ARCH32 "m32" 668*38fd1498Szrj #else 669*38fd1498Szrj #define OPT_ARCH64 "m64|mx32" 670*38fd1498Szrj #define OPT_ARCH32 "m64|mx32:;" 671*38fd1498Szrj #endif 672*38fd1498Szrj 673*38fd1498Szrj /* Support for configure-time defaults of some command line options. 674*38fd1498Szrj The order here is important so that -march doesn't squash the 675*38fd1498Szrj tune or cpu values. */ 676*38fd1498Szrj #define OPTION_DEFAULT_SPECS \ 677*38fd1498Szrj {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 678*38fd1498Szrj {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 679*38fd1498Szrj {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 680*38fd1498Szrj {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 681*38fd1498Szrj {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 682*38fd1498Szrj {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 683*38fd1498Szrj {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 684*38fd1498Szrj {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ 685*38fd1498Szrj {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, 686*38fd1498Szrj 687*38fd1498Szrj /* Specs for the compiler proper */ 688*38fd1498Szrj 689*38fd1498Szrj #ifndef CC1_CPU_SPEC 690*38fd1498Szrj #define CC1_CPU_SPEC_1 "" 691*38fd1498Szrj 692*38fd1498Szrj #ifndef HAVE_LOCAL_CPU_DETECT 693*38fd1498Szrj #define CC1_CPU_SPEC CC1_CPU_SPEC_1 694*38fd1498Szrj #else 695*38fd1498Szrj #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 696*38fd1498Szrj "%{march=native:%>march=native %:local_cpu_detect(arch) \ 697*38fd1498Szrj %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ 698*38fd1498Szrj %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" 699*38fd1498Szrj #endif 700*38fd1498Szrj #endif 701*38fd1498Szrj 702*38fd1498Szrj /* Target CPU builtins. */ 703*38fd1498Szrj #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () 704*38fd1498Szrj 705*38fd1498Szrj /* Target Pragmas. */ 706*38fd1498Szrj #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () 707*38fd1498Szrj 708*38fd1498Szrj #ifndef CC1_SPEC 709*38fd1498Szrj #define CC1_SPEC "%(cc1_cpu) " 710*38fd1498Szrj #endif 711*38fd1498Szrj 712*38fd1498Szrj /* This macro defines names of additional specifications to put in the 713*38fd1498Szrj specs that can be used in various specifications like CC1_SPEC. Its 714*38fd1498Szrj definition is an initializer with a subgrouping for each command option. 715*38fd1498Szrj 716*38fd1498Szrj Each subgrouping contains a string constant, that defines the 717*38fd1498Szrj specification name, and a string constant that used by the GCC driver 718*38fd1498Szrj program. 719*38fd1498Szrj 720*38fd1498Szrj Do not define this macro if it does not need to do anything. */ 721*38fd1498Szrj 722*38fd1498Szrj #ifndef SUBTARGET_EXTRA_SPECS 723*38fd1498Szrj #define SUBTARGET_EXTRA_SPECS 724*38fd1498Szrj #endif 725*38fd1498Szrj 726*38fd1498Szrj #define EXTRA_SPECS \ 727*38fd1498Szrj { "cc1_cpu", CC1_CPU_SPEC }, \ 728*38fd1498Szrj SUBTARGET_EXTRA_SPECS 729*38fd1498Szrj 730*38fd1498Szrj 731*38fd1498Szrj /* Whether to allow x87 floating-point arithmetic on MODE (one of 732*38fd1498Szrj SFmode, DFmode and XFmode) in the current excess precision 733*38fd1498Szrj configuration. */ 734*38fd1498Szrj #define X87_ENABLE_ARITH(MODE) \ 735*38fd1498Szrj (flag_unsafe_math_optimizations \ 736*38fd1498Szrj || flag_excess_precision == EXCESS_PRECISION_FAST \ 737*38fd1498Szrj || (MODE) == XFmode) 738*38fd1498Szrj 739*38fd1498Szrj /* Likewise, whether to allow direct conversions from integer mode 740*38fd1498Szrj IMODE (HImode, SImode or DImode) to MODE. */ 741*38fd1498Szrj #define X87_ENABLE_FLOAT(MODE, IMODE) \ 742*38fd1498Szrj (flag_unsafe_math_optimizations \ 743*38fd1498Szrj || flag_excess_precision == EXCESS_PRECISION_FAST \ 744*38fd1498Szrj || (MODE) == XFmode \ 745*38fd1498Szrj || ((MODE) == DFmode && (IMODE) == SImode) \ 746*38fd1498Szrj || (IMODE) == HImode) 747*38fd1498Szrj 748*38fd1498Szrj /* target machine storage layout */ 749*38fd1498Szrj 750*38fd1498Szrj #define SHORT_TYPE_SIZE 16 751*38fd1498Szrj #define INT_TYPE_SIZE 32 752*38fd1498Szrj #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 753*38fd1498Szrj #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 754*38fd1498Szrj #define LONG_LONG_TYPE_SIZE 64 755*38fd1498Szrj #define FLOAT_TYPE_SIZE 32 756*38fd1498Szrj #define DOUBLE_TYPE_SIZE 64 757*38fd1498Szrj #define LONG_DOUBLE_TYPE_SIZE \ 758*38fd1498Szrj (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) 759*38fd1498Szrj 760*38fd1498Szrj #define WIDEST_HARDWARE_FP_SIZE 80 761*38fd1498Szrj 762*38fd1498Szrj #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 763*38fd1498Szrj #define MAX_BITS_PER_WORD 64 764*38fd1498Szrj #else 765*38fd1498Szrj #define MAX_BITS_PER_WORD 32 766*38fd1498Szrj #endif 767*38fd1498Szrj 768*38fd1498Szrj /* Define this if most significant byte of a word is the lowest numbered. */ 769*38fd1498Szrj /* That is true on the 80386. */ 770*38fd1498Szrj 771*38fd1498Szrj #define BITS_BIG_ENDIAN 0 772*38fd1498Szrj 773*38fd1498Szrj /* Define this if most significant byte of a word is the lowest numbered. */ 774*38fd1498Szrj /* That is not true on the 80386. */ 775*38fd1498Szrj #define BYTES_BIG_ENDIAN 0 776*38fd1498Szrj 777*38fd1498Szrj /* Define this if most significant word of a multiword number is the lowest 778*38fd1498Szrj numbered. */ 779*38fd1498Szrj /* Not true for 80386 */ 780*38fd1498Szrj #define WORDS_BIG_ENDIAN 0 781*38fd1498Szrj 782*38fd1498Szrj /* Width of a word, in units (bytes). */ 783*38fd1498Szrj #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 784*38fd1498Szrj 785*38fd1498Szrj #ifndef IN_LIBGCC2 786*38fd1498Szrj #define MIN_UNITS_PER_WORD 4 787*38fd1498Szrj #endif 788*38fd1498Szrj 789*38fd1498Szrj /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 790*38fd1498Szrj #define PARM_BOUNDARY BITS_PER_WORD 791*38fd1498Szrj 792*38fd1498Szrj /* Boundary (in *bits*) on which stack pointer should be aligned. */ 793*38fd1498Szrj #define STACK_BOUNDARY \ 794*38fd1498Szrj (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) 795*38fd1498Szrj 796*38fd1498Szrj /* Stack boundary of the main function guaranteed by OS. */ 797*38fd1498Szrj #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 798*38fd1498Szrj 799*38fd1498Szrj /* Minimum stack boundary. */ 800*38fd1498Szrj #define MIN_STACK_BOUNDARY BITS_PER_WORD 801*38fd1498Szrj 802*38fd1498Szrj /* Boundary (in *bits*) on which the stack pointer prefers to be 803*38fd1498Szrj aligned; the compiler cannot rely on having this alignment. */ 804*38fd1498Szrj #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 805*38fd1498Szrj 806*38fd1498Szrj /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for 807*38fd1498Szrj both 32bit and 64bit, to support codes that need 128 bit stack 808*38fd1498Szrj alignment for SSE instructions, but can't realign the stack. */ 809*38fd1498Szrj #define PREFERRED_STACK_BOUNDARY_DEFAULT \ 810*38fd1498Szrj (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128) 811*38fd1498Szrj 812*38fd1498Szrj /* 1 if -mstackrealign should be turned on by default. It will 813*38fd1498Szrj generate an alternate prologue and epilogue that realigns the 814*38fd1498Szrj runtime stack if nessary. This supports mixing codes that keep a 815*38fd1498Szrj 4-byte aligned stack, as specified by i386 psABI, with codes that 816*38fd1498Szrj need a 16-byte aligned stack, as required by SSE instructions. */ 817*38fd1498Szrj #define STACK_REALIGN_DEFAULT 0 818*38fd1498Szrj 819*38fd1498Szrj /* Boundary (in *bits*) on which the incoming stack is aligned. */ 820*38fd1498Szrj #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary 821*38fd1498Szrj 822*38fd1498Szrj /* According to Windows x64 software convention, the maximum stack allocatable 823*38fd1498Szrj in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of 824*38fd1498Szrj instructions allowed to adjust the stack pointer in the epilog, forcing the 825*38fd1498Szrj use of frame pointer for frames larger than 2 GB. This theorical limit 826*38fd1498Szrj is reduced by 256, an over-estimated upper bound for the stack use by the 827*38fd1498Szrj prologue. 828*38fd1498Szrj We define only one threshold for both the prolog and the epilog. When the 829*38fd1498Szrj frame size is larger than this threshold, we allocate the area to save SSE 830*38fd1498Szrj regs, then save them, and then allocate the remaining. There is no SEH 831*38fd1498Szrj unwind info for this later allocation. */ 832*38fd1498Szrj #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) 833*38fd1498Szrj 834*38fd1498Szrj /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is 835*38fd1498Szrj mandatory for the 64-bit ABI, and may or may not be true for other 836*38fd1498Szrj operating systems. */ 837*38fd1498Szrj #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT 838*38fd1498Szrj 839*38fd1498Szrj /* Minimum allocation boundary for the code of a function. */ 840*38fd1498Szrj #define FUNCTION_BOUNDARY 8 841*38fd1498Szrj 842*38fd1498Szrj /* C++ stores the virtual bit in the lowest bit of function pointers. */ 843*38fd1498Szrj #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 844*38fd1498Szrj 845*38fd1498Szrj /* Minimum size in bits of the largest boundary to which any 846*38fd1498Szrj and all fundamental data types supported by the hardware 847*38fd1498Szrj might need to be aligned. No data type wants to be aligned 848*38fd1498Szrj rounder than this. 849*38fd1498Szrj 850*38fd1498Szrj Pentium+ prefers DFmode values to be aligned to 64 bit boundary 851*38fd1498Szrj and Pentium Pro XFmode values at 128 bit boundaries. 852*38fd1498Szrj 853*38fd1498Szrj When increasing the maximum, also update 854*38fd1498Szrj TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ 855*38fd1498Szrj 856*38fd1498Szrj #define BIGGEST_ALIGNMENT \ 857*38fd1498Szrj (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))) 858*38fd1498Szrj 859*38fd1498Szrj /* Maximum stack alignment. */ 860*38fd1498Szrj #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT 861*38fd1498Szrj 862*38fd1498Szrj /* Alignment value for attribute ((aligned)). It is a constant since 863*38fd1498Szrj it is the part of the ABI. We shouldn't change it with -mavx. */ 864*38fd1498Szrj #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128) 865*38fd1498Szrj 866*38fd1498Szrj /* Decide whether a variable of mode MODE should be 128 bit aligned. */ 867*38fd1498Szrj #define ALIGN_MODE_128(MODE) \ 868*38fd1498Szrj ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 869*38fd1498Szrj 870*38fd1498Szrj /* The published ABIs say that doubles should be aligned on word 871*38fd1498Szrj boundaries, so lower the alignment for structure fields unless 872*38fd1498Szrj -malign-double is set. */ 873*38fd1498Szrj 874*38fd1498Szrj /* ??? Blah -- this macro is used directly by libobjc. Since it 875*38fd1498Szrj supports no vector modes, cut out the complexity and fall back 876*38fd1498Szrj on BIGGEST_FIELD_ALIGNMENT. */ 877*38fd1498Szrj #ifdef IN_TARGET_LIBS 878*38fd1498Szrj #ifdef __x86_64__ 879*38fd1498Szrj #define BIGGEST_FIELD_ALIGNMENT 128 880*38fd1498Szrj #else 881*38fd1498Szrj #define BIGGEST_FIELD_ALIGNMENT 32 882*38fd1498Szrj #endif 883*38fd1498Szrj #else 884*38fd1498Szrj #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ 885*38fd1498Szrj x86_field_alignment ((TYPE), (COMPUTED)) 886*38fd1498Szrj #endif 887*38fd1498Szrj 888*38fd1498Szrj /* If defined, a C expression to compute the alignment for a static 889*38fd1498Szrj variable. TYPE is the data type, and ALIGN is the alignment that 890*38fd1498Szrj the object would ordinarily have. The value of this macro is used 891*38fd1498Szrj instead of that alignment to align the object. 892*38fd1498Szrj 893*38fd1498Szrj If this macro is not defined, then ALIGN is used. 894*38fd1498Szrj 895*38fd1498Szrj One use of this macro is to increase alignment of medium-size 896*38fd1498Szrj data to make it all fit in fewer cache lines. Another is to 897*38fd1498Szrj cause character arrays to be word-aligned so that `strcpy' calls 898*38fd1498Szrj that copy constants to character arrays can be done inline. */ 899*38fd1498Szrj 900*38fd1498Szrj #define DATA_ALIGNMENT(TYPE, ALIGN) \ 901*38fd1498Szrj ix86_data_alignment ((TYPE), (ALIGN), true) 902*38fd1498Szrj 903*38fd1498Szrj /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates 904*38fd1498Szrj some alignment increase, instead of optimization only purposes. E.g. 905*38fd1498Szrj AMD x86-64 psABI says that variables with array type larger than 15 bytes 906*38fd1498Szrj must be aligned to 16 byte boundaries. 907*38fd1498Szrj 908*38fd1498Szrj If this macro is not defined, then ALIGN is used. */ 909*38fd1498Szrj 910*38fd1498Szrj #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 911*38fd1498Szrj ix86_data_alignment ((TYPE), (ALIGN), false) 912*38fd1498Szrj 913*38fd1498Szrj /* If defined, a C expression to compute the alignment for a local 914*38fd1498Szrj variable. TYPE is the data type, and ALIGN is the alignment that 915*38fd1498Szrj the object would ordinarily have. The value of this macro is used 916*38fd1498Szrj instead of that alignment to align the object. 917*38fd1498Szrj 918*38fd1498Szrj If this macro is not defined, then ALIGN is used. 919*38fd1498Szrj 920*38fd1498Szrj One use of this macro is to increase alignment of medium-size 921*38fd1498Szrj data to make it all fit in fewer cache lines. */ 922*38fd1498Szrj 923*38fd1498Szrj #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 924*38fd1498Szrj ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) 925*38fd1498Szrj 926*38fd1498Szrj /* If defined, a C expression to compute the alignment for stack slot. 927*38fd1498Szrj TYPE is the data type, MODE is the widest mode available, and ALIGN 928*38fd1498Szrj is the alignment that the slot would ordinarily have. The value of 929*38fd1498Szrj this macro is used instead of that alignment to align the slot. 930*38fd1498Szrj 931*38fd1498Szrj If this macro is not defined, then ALIGN is used when TYPE is NULL, 932*38fd1498Szrj Otherwise, LOCAL_ALIGNMENT will be used. 933*38fd1498Szrj 934*38fd1498Szrj One use of this macro is to set alignment of stack slot to the 935*38fd1498Szrj maximum alignment of all possible modes which the slot may have. */ 936*38fd1498Szrj 937*38fd1498Szrj #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ 938*38fd1498Szrj ix86_local_alignment ((TYPE), (MODE), (ALIGN)) 939*38fd1498Szrj 940*38fd1498Szrj /* If defined, a C expression to compute the alignment for a local 941*38fd1498Szrj variable DECL. 942*38fd1498Szrj 943*38fd1498Szrj If this macro is not defined, then 944*38fd1498Szrj LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. 945*38fd1498Szrj 946*38fd1498Szrj One use of this macro is to increase alignment of medium-size 947*38fd1498Szrj data to make it all fit in fewer cache lines. */ 948*38fd1498Szrj 949*38fd1498Szrj #define LOCAL_DECL_ALIGNMENT(DECL) \ 950*38fd1498Szrj ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 951*38fd1498Szrj 952*38fd1498Szrj /* If defined, a C expression to compute the minimum required alignment 953*38fd1498Szrj for dynamic stack realignment purposes for EXP (a TYPE or DECL), 954*38fd1498Szrj MODE, assuming normal alignment ALIGN. 955*38fd1498Szrj 956*38fd1498Szrj If this macro is not defined, then (ALIGN) will be used. */ 957*38fd1498Szrj 958*38fd1498Szrj #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ 959*38fd1498Szrj ix86_minimum_alignment ((EXP), (MODE), (ALIGN)) 960*38fd1498Szrj 961*38fd1498Szrj 962*38fd1498Szrj /* Set this nonzero if move instructions will actually fail to work 963*38fd1498Szrj when given unaligned data. */ 964*38fd1498Szrj #define STRICT_ALIGNMENT 0 965*38fd1498Szrj 966*38fd1498Szrj /* If bit field type is int, don't let it cross an int, 967*38fd1498Szrj and give entire struct the alignment of an int. */ 968*38fd1498Szrj /* Required on the 386 since it doesn't have bit-field insns. */ 969*38fd1498Szrj #define PCC_BITFIELD_TYPE_MATTERS 1 970*38fd1498Szrj 971*38fd1498Szrj /* Standard register usage. */ 972*38fd1498Szrj 973*38fd1498Szrj /* This processor has special stack-like registers. See reg-stack.c 974*38fd1498Szrj for details. */ 975*38fd1498Szrj 976*38fd1498Szrj #define STACK_REGS 977*38fd1498Szrj 978*38fd1498Szrj #define IS_STACK_MODE(MODE) \ 979*38fd1498Szrj (X87_FLOAT_MODE_P (MODE) \ 980*38fd1498Szrj && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ 981*38fd1498Szrj || TARGET_MIX_SSE_I387)) 982*38fd1498Szrj 983*38fd1498Szrj /* Number of actual hardware registers. 984*38fd1498Szrj The hardware registers are assigned numbers for the compiler 985*38fd1498Szrj from 0 to just below FIRST_PSEUDO_REGISTER. 986*38fd1498Szrj All registers that the compiler knows about must be given numbers, 987*38fd1498Szrj even those that are not normally considered general registers. 988*38fd1498Szrj 989*38fd1498Szrj In the 80386 we give the 8 general purpose registers the numbers 0-7. 990*38fd1498Szrj We number the floating point registers 8-15. 991*38fd1498Szrj Note that registers 0-7 can be accessed as a short or int, 992*38fd1498Szrj while only 0-3 may be used with byte `mov' instructions. 993*38fd1498Szrj 994*38fd1498Szrj Reg 16 does not correspond to any hardware register, but instead 995*38fd1498Szrj appears in the RTL as an argument pointer prior to reload, and is 996*38fd1498Szrj eliminated during reloading in favor of either the stack or frame 997*38fd1498Szrj pointer. */ 998*38fd1498Szrj 999*38fd1498Szrj #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG 1000*38fd1498Szrj 1001*38fd1498Szrj /* Number of hardware registers that go into the DWARF-2 unwind info. 1002*38fd1498Szrj If not defined, equals FIRST_PSEUDO_REGISTER. */ 1003*38fd1498Szrj 1004*38fd1498Szrj #define DWARF_FRAME_REGISTERS 17 1005*38fd1498Szrj 1006*38fd1498Szrj /* 1 for registers that have pervasive standard uses 1007*38fd1498Szrj and are not available for the register allocator. 1008*38fd1498Szrj On the 80386, the stack pointer is such, as is the arg pointer. 1009*38fd1498Szrj 1010*38fd1498Szrj REX registers are disabled for 32bit targets in 1011*38fd1498Szrj TARGET_CONDITIONAL_REGISTER_USAGE. */ 1012*38fd1498Szrj 1013*38fd1498Szrj #define FIXED_REGISTERS \ 1014*38fd1498Szrj /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 1015*38fd1498Szrj { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 1016*38fd1498Szrj /*arg,flags,fpsr,fpcr,frame*/ \ 1017*38fd1498Szrj 1, 1, 1, 1, 1, \ 1018*38fd1498Szrj /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1019*38fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 1020*38fd1498Szrj /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1021*38fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 1022*38fd1498Szrj /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1023*38fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 1024*38fd1498Szrj /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 1025*38fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 1026*38fd1498Szrj /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 1027*38fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 1028*38fd1498Szrj /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 1029*38fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 1030*38fd1498Szrj /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1031*38fd1498Szrj 0, 0, 0, 0, 0, 0, 0, 0, \ 1032*38fd1498Szrj /* b0, b1, b2, b3*/ \ 1033*38fd1498Szrj 0, 0, 0, 0 } 1034*38fd1498Szrj 1035*38fd1498Szrj /* 1 for registers not available across function calls. 1036*38fd1498Szrj These must include the FIXED_REGISTERS and also any 1037*38fd1498Szrj registers that can be used without being saved. 1038*38fd1498Szrj The latter must include the registers where values are returned 1039*38fd1498Szrj and the register where structure-value addresses are passed. 1040*38fd1498Szrj Aside from that, you can include as many other registers as you like. 1041*38fd1498Szrj 1042*38fd1498Szrj Value is set to 1 if the register is call used unconditionally. 1043*38fd1498Szrj Bit one is set if the register is call used on TARGET_32BIT ABI. 1044*38fd1498Szrj Bit two is set if the register is call used on TARGET_64BIT ABI. 1045*38fd1498Szrj Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. 1046*38fd1498Szrj 1047*38fd1498Szrj Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ 1048*38fd1498Szrj 1049*38fd1498Szrj #define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \ 1050*38fd1498Szrj ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1)) 1051*38fd1498Szrj 1052*38fd1498Szrj #define CALL_USED_REGISTERS \ 1053*38fd1498Szrj /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 1054*38fd1498Szrj { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1055*38fd1498Szrj /*arg,flags,fpsr,fpcr,frame*/ \ 1056*38fd1498Szrj 1, 1, 1, 1, 1, \ 1057*38fd1498Szrj /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1058*38fd1498Szrj 1, 1, 1, 1, 1, 1, 6, 6, \ 1059*38fd1498Szrj /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1060*38fd1498Szrj 1, 1, 1, 1, 1, 1, 1, 1, \ 1061*38fd1498Szrj /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1062*38fd1498Szrj 1, 1, 1, 1, 2, 2, 2, 2, \ 1063*38fd1498Szrj /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 1064*38fd1498Szrj 6, 6, 6, 6, 6, 6, 6, 6, \ 1065*38fd1498Szrj /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 1066*38fd1498Szrj 6, 6, 6, 6, 6, 6, 6, 6, \ 1067*38fd1498Szrj /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 1068*38fd1498Szrj 6, 6, 6, 6, 6, 6, 6, 6, \ 1069*38fd1498Szrj /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1070*38fd1498Szrj 1, 1, 1, 1, 1, 1, 1, 1, \ 1071*38fd1498Szrj /* b0, b1, b2, b3*/ \ 1072*38fd1498Szrj 1, 1, 1, 1 } 1073*38fd1498Szrj 1074*38fd1498Szrj /* Order in which to allocate registers. Each register must be 1075*38fd1498Szrj listed once, even those in FIXED_REGISTERS. List frame pointer 1076*38fd1498Szrj late and fixed registers last. Note that, in general, we prefer 1077*38fd1498Szrj registers listed in CALL_USED_REGISTERS, keeping the others 1078*38fd1498Szrj available for storage of persistent values. 1079*38fd1498Szrj 1080*38fd1498Szrj The ADJUST_REG_ALLOC_ORDER actually overwrite the order, 1081*38fd1498Szrj so this is just empty initializer for array. */ 1082*38fd1498Szrj 1083*38fd1498Szrj #define REG_ALLOC_ORDER \ 1084*38fd1498Szrj { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 1085*38fd1498Szrj 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 1086*38fd1498Szrj 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1087*38fd1498Szrj 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ 1088*38fd1498Szrj 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \ 1089*38fd1498Szrj 78, 79, 80 } 1090*38fd1498Szrj 1091*38fd1498Szrj /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 1092*38fd1498Szrj to be rearranged based on a particular function. When using sse math, 1093*38fd1498Szrj we want to allocate SSE before x87 registers and vice versa. */ 1094*38fd1498Szrj 1095*38fd1498Szrj #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () 1096*38fd1498Szrj 1097*38fd1498Szrj 1098*38fd1498Szrj #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 1099*38fd1498Szrj 1100*38fd1498Szrj #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 1101*38fd1498Szrj (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \ 1102*38fd1498Szrj && GENERAL_REGNO_P (REGNO) \ 1103*38fd1498Szrj && ((MODE) == XFmode || (MODE) == XCmode)) 1104*38fd1498Szrj 1105*38fd1498Szrj #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 1106*38fd1498Szrj 1107*38fd1498Szrj #define VALID_AVX256_REG_MODE(MODE) \ 1108*38fd1498Szrj ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1109*38fd1498Szrj || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ 1110*38fd1498Szrj || (MODE) == V4DFmode) 1111*38fd1498Szrj 1112*38fd1498Szrj #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ 1113*38fd1498Szrj (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) 1114*38fd1498Szrj 1115*38fd1498Szrj #define VALID_AVX512F_SCALAR_MODE(MODE) \ 1116*38fd1498Szrj ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ 1117*38fd1498Szrj || (MODE) == SFmode) 1118*38fd1498Szrj 1119*38fd1498Szrj #define VALID_AVX512F_REG_MODE(MODE) \ 1120*38fd1498Szrj ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ 1121*38fd1498Szrj || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ 1122*38fd1498Szrj || (MODE) == V4TImode) 1123*38fd1498Szrj 1124*38fd1498Szrj #define VALID_AVX512F_REG_OR_XI_MODE(MODE) \ 1125*38fd1498Szrj (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode) 1126*38fd1498Szrj 1127*38fd1498Szrj #define VALID_AVX512VL_128_REG_MODE(MODE) \ 1128*38fd1498Szrj ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ 1129*38fd1498Szrj || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \ 1130*38fd1498Szrj || (MODE) == TFmode || (MODE) == V1TImode) 1131*38fd1498Szrj 1132*38fd1498Szrj #define VALID_SSE2_REG_MODE(MODE) \ 1133*38fd1498Szrj ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1134*38fd1498Szrj || (MODE) == V2DImode || (MODE) == DFmode) 1135*38fd1498Szrj 1136*38fd1498Szrj #define VALID_SSE_REG_MODE(MODE) \ 1137*38fd1498Szrj ((MODE) == V1TImode || (MODE) == TImode \ 1138*38fd1498Szrj || (MODE) == V4SFmode || (MODE) == V4SImode \ 1139*38fd1498Szrj || (MODE) == SFmode || (MODE) == TFmode) 1140*38fd1498Szrj 1141*38fd1498Szrj #define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1142*38fd1498Szrj ((MODE) == V2SFmode || (MODE) == SFmode) 1143*38fd1498Szrj 1144*38fd1498Szrj #define VALID_MMX_REG_MODE(MODE) \ 1145*38fd1498Szrj ((MODE == V1DImode) || (MODE) == DImode \ 1146*38fd1498Szrj || (MODE) == V2SImode || (MODE) == SImode \ 1147*38fd1498Szrj || (MODE) == V4HImode || (MODE) == V8QImode) 1148*38fd1498Szrj 1149*38fd1498Szrj #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) 1150*38fd1498Szrj 1151*38fd1498Szrj #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) 1152*38fd1498Szrj 1153*38fd1498Szrj #define VALID_BND_REG_MODE(MODE) \ 1154*38fd1498Szrj (TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode) 1155*38fd1498Szrj 1156*38fd1498Szrj #define VALID_DFP_MODE_P(MODE) \ 1157*38fd1498Szrj ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 1158*38fd1498Szrj 1159*38fd1498Szrj #define VALID_FP_MODE_P(MODE) \ 1160*38fd1498Szrj ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1161*38fd1498Szrj || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1162*38fd1498Szrj 1163*38fd1498Szrj #define VALID_INT_MODE_P(MODE) \ 1164*38fd1498Szrj ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1165*38fd1498Szrj || (MODE) == DImode \ 1166*38fd1498Szrj || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1167*38fd1498Szrj || (MODE) == CDImode \ 1168*38fd1498Szrj || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1169*38fd1498Szrj || (MODE) == TFmode || (MODE) == TCmode))) 1170*38fd1498Szrj 1171*38fd1498Szrj /* Return true for modes passed in SSE registers. */ 1172*38fd1498Szrj #define SSE_REG_MODE_P(MODE) \ 1173*38fd1498Szrj ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ 1174*38fd1498Szrj || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1175*38fd1498Szrj || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1176*38fd1498Szrj || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1177*38fd1498Szrj || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ 1178*38fd1498Szrj || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ 1179*38fd1498Szrj || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ 1180*38fd1498Szrj || (MODE) == V16SFmode) 1181*38fd1498Szrj 1182*38fd1498Szrj #define X87_FLOAT_MODE_P(MODE) \ 1183*38fd1498Szrj (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) 1184*38fd1498Szrj 1185*38fd1498Szrj #define SSE_FLOAT_MODE_P(MODE) \ 1186*38fd1498Szrj ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1187*38fd1498Szrj 1188*38fd1498Szrj #define FMA4_VEC_FLOAT_MODE_P(MODE) \ 1189*38fd1498Szrj (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1190*38fd1498Szrj || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1191*38fd1498Szrj 1192*38fd1498Szrj /* It is possible to write patterns to move flags; but until someone 1193*38fd1498Szrj does it, */ 1194*38fd1498Szrj #define AVOID_CCMODE_COPIES 1195*38fd1498Szrj 1196*38fd1498Szrj /* Specify the modes required to caller save a given hard regno. 1197*38fd1498Szrj We do this on i386 to prevent flags from being saved at all. 1198*38fd1498Szrj 1199*38fd1498Szrj Kill any attempts to combine saving of modes. */ 1200*38fd1498Szrj 1201*38fd1498Szrj #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1202*38fd1498Szrj (CC_REGNO_P (REGNO) ? VOIDmode \ 1203*38fd1498Szrj : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1204*38fd1498Szrj : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ 1205*38fd1498Szrj : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \ 1206*38fd1498Szrj && TARGET_PARTIAL_REG_STALL) \ 1207*38fd1498Szrj || MASK_REGNO_P (REGNO)) ? SImode \ 1208*38fd1498Szrj : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \ 1209*38fd1498Szrj || MASK_REGNO_P (REGNO)) ? SImode \ 1210*38fd1498Szrj : (MODE)) 1211*38fd1498Szrj 1212*38fd1498Szrj /* Specify the registers used for certain standard purposes. 1213*38fd1498Szrj The values of these macros are register numbers. */ 1214*38fd1498Szrj 1215*38fd1498Szrj /* on the 386 the pc register is %eip, and is not usable as a general 1216*38fd1498Szrj register. The ordinary mov instructions won't work */ 1217*38fd1498Szrj /* #define PC_REGNUM */ 1218*38fd1498Szrj 1219*38fd1498Szrj /* Base register for access to arguments of the function. */ 1220*38fd1498Szrj #define ARG_POINTER_REGNUM ARGP_REG 1221*38fd1498Szrj 1222*38fd1498Szrj /* Register to use for pushing function arguments. */ 1223*38fd1498Szrj #define STACK_POINTER_REGNUM SP_REG 1224*38fd1498Szrj 1225*38fd1498Szrj /* Base register for access to local variables of the function. */ 1226*38fd1498Szrj #define FRAME_POINTER_REGNUM FRAME_REG 1227*38fd1498Szrj #define HARD_FRAME_POINTER_REGNUM BP_REG 1228*38fd1498Szrj 1229*38fd1498Szrj #define FIRST_INT_REG AX_REG 1230*38fd1498Szrj #define LAST_INT_REG SP_REG 1231*38fd1498Szrj 1232*38fd1498Szrj #define FIRST_QI_REG AX_REG 1233*38fd1498Szrj #define LAST_QI_REG BX_REG 1234*38fd1498Szrj 1235*38fd1498Szrj /* First & last stack-like regs */ 1236*38fd1498Szrj #define FIRST_STACK_REG ST0_REG 1237*38fd1498Szrj #define LAST_STACK_REG ST7_REG 1238*38fd1498Szrj 1239*38fd1498Szrj #define FIRST_SSE_REG XMM0_REG 1240*38fd1498Szrj #define LAST_SSE_REG XMM7_REG 1241*38fd1498Szrj 1242*38fd1498Szrj #define FIRST_MMX_REG MM0_REG 1243*38fd1498Szrj #define LAST_MMX_REG MM7_REG 1244*38fd1498Szrj 1245*38fd1498Szrj #define FIRST_REX_INT_REG R8_REG 1246*38fd1498Szrj #define LAST_REX_INT_REG R15_REG 1247*38fd1498Szrj 1248*38fd1498Szrj #define FIRST_REX_SSE_REG XMM8_REG 1249*38fd1498Szrj #define LAST_REX_SSE_REG XMM15_REG 1250*38fd1498Szrj 1251*38fd1498Szrj #define FIRST_EXT_REX_SSE_REG XMM16_REG 1252*38fd1498Szrj #define LAST_EXT_REX_SSE_REG XMM31_REG 1253*38fd1498Szrj 1254*38fd1498Szrj #define FIRST_MASK_REG MASK0_REG 1255*38fd1498Szrj #define LAST_MASK_REG MASK7_REG 1256*38fd1498Szrj 1257*38fd1498Szrj #define FIRST_BND_REG BND0_REG 1258*38fd1498Szrj #define LAST_BND_REG BND3_REG 1259*38fd1498Szrj 1260*38fd1498Szrj /* Override this in other tm.h files to cope with various OS lossage 1261*38fd1498Szrj requiring a frame pointer. */ 1262*38fd1498Szrj #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1263*38fd1498Szrj #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1264*38fd1498Szrj #endif 1265*38fd1498Szrj 1266*38fd1498Szrj /* Make sure we can access arbitrary call frames. */ 1267*38fd1498Szrj #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1268*38fd1498Szrj 1269*38fd1498Szrj /* Register to hold the addressing base for position independent 1270*38fd1498Szrj code access to data items. We don't use PIC pointer for 64bit 1271*38fd1498Szrj mode. Define the regnum to dummy value to prevent gcc from 1272*38fd1498Szrj pessimizing code dealing with EBX. 1273*38fd1498Szrj 1274*38fd1498Szrj To avoid clobbering a call-saved register unnecessarily, we renumber 1275*38fd1498Szrj the pic register when possible. The change is visible after the 1276*38fd1498Szrj prologue has been emitted. */ 1277*38fd1498Szrj 1278*38fd1498Szrj #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) 1279*38fd1498Szrj 1280*38fd1498Szrj #define PIC_OFFSET_TABLE_REGNUM \ 1281*38fd1498Szrj (ix86_use_pseudo_pic_reg () \ 1282*38fd1498Szrj ? (pic_offset_table_rtx \ 1283*38fd1498Szrj ? INVALID_REGNUM \ 1284*38fd1498Szrj : REAL_PIC_OFFSET_TABLE_REGNUM) \ 1285*38fd1498Szrj : INVALID_REGNUM) 1286*38fd1498Szrj 1287*38fd1498Szrj #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1288*38fd1498Szrj 1289*38fd1498Szrj /* This is overridden by <cygwin.h>. */ 1290*38fd1498Szrj #define MS_AGGREGATE_RETURN 0 1291*38fd1498Szrj 1292*38fd1498Szrj #define KEEP_AGGREGATE_RETURN_POINTER 0 1293*38fd1498Szrj 1294*38fd1498Szrj /* Define the classes of registers for register constraints in the 1295*38fd1498Szrj machine description. Also define ranges of constants. 1296*38fd1498Szrj 1297*38fd1498Szrj One of the classes must always be named ALL_REGS and include all hard regs. 1298*38fd1498Szrj If there is more than one class, another class must be named NO_REGS 1299*38fd1498Szrj and contain no registers. 1300*38fd1498Szrj 1301*38fd1498Szrj The name GENERAL_REGS must be the name of a class (or an alias for 1302*38fd1498Szrj another name such as ALL_REGS). This is the class of registers 1303*38fd1498Szrj that is allowed by "g" or "r" in a register constraint. 1304*38fd1498Szrj Also, registers outside this class are allocated only when 1305*38fd1498Szrj instructions express preferences for them. 1306*38fd1498Szrj 1307*38fd1498Szrj The classes must be numbered in nondecreasing order; that is, 1308*38fd1498Szrj a larger-numbered class must never be contained completely 1309*38fd1498Szrj in a smaller-numbered class. This is why CLOBBERED_REGS class 1310*38fd1498Szrj is listed early, even though in 64-bit mode it contains more 1311*38fd1498Szrj registers than just %eax, %ecx, %edx. 1312*38fd1498Szrj 1313*38fd1498Szrj For any two classes, it is very desirable that there be another 1314*38fd1498Szrj class that represents their union. 1315*38fd1498Szrj 1316*38fd1498Szrj It might seem that class BREG is unnecessary, since no useful 386 1317*38fd1498Szrj opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1318*38fd1498Szrj and the "b" register constraint is useful in asms for syscalls. 1319*38fd1498Szrj 1320*38fd1498Szrj The flags, fpsr and fpcr registers are in no class. */ 1321*38fd1498Szrj 1322*38fd1498Szrj enum reg_class 1323*38fd1498Szrj { 1324*38fd1498Szrj NO_REGS, 1325*38fd1498Szrj AREG, DREG, CREG, BREG, SIREG, DIREG, 1326*38fd1498Szrj AD_REGS, /* %eax/%edx for DImode */ 1327*38fd1498Szrj CLOBBERED_REGS, /* call-clobbered integer registers */ 1328*38fd1498Szrj Q_REGS, /* %eax %ebx %ecx %edx */ 1329*38fd1498Szrj NON_Q_REGS, /* %esi %edi %ebp %esp */ 1330*38fd1498Szrj TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */ 1331*38fd1498Szrj INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1332*38fd1498Szrj LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1333*38fd1498Szrj GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp 1334*38fd1498Szrj %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ 1335*38fd1498Szrj FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1336*38fd1498Szrj FLOAT_REGS, 1337*38fd1498Szrj SSE_FIRST_REG, 1338*38fd1498Szrj NO_REX_SSE_REGS, 1339*38fd1498Szrj SSE_REGS, 1340*38fd1498Szrj EVEX_SSE_REGS, 1341*38fd1498Szrj BND_REGS, 1342*38fd1498Szrj ALL_SSE_REGS, 1343*38fd1498Szrj MMX_REGS, 1344*38fd1498Szrj FP_TOP_SSE_REGS, 1345*38fd1498Szrj FP_SECOND_SSE_REGS, 1346*38fd1498Szrj FLOAT_SSE_REGS, 1347*38fd1498Szrj FLOAT_INT_REGS, 1348*38fd1498Szrj INT_SSE_REGS, 1349*38fd1498Szrj FLOAT_INT_SSE_REGS, 1350*38fd1498Szrj MASK_EVEX_REGS, 1351*38fd1498Szrj MASK_REGS, 1352*38fd1498Szrj MOD4_SSE_REGS, 1353*38fd1498Szrj ALL_REGS, LIM_REG_CLASSES 1354*38fd1498Szrj }; 1355*38fd1498Szrj 1356*38fd1498Szrj #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1357*38fd1498Szrj 1358*38fd1498Szrj #define INTEGER_CLASS_P(CLASS) \ 1359*38fd1498Szrj reg_class_subset_p ((CLASS), GENERAL_REGS) 1360*38fd1498Szrj #define FLOAT_CLASS_P(CLASS) \ 1361*38fd1498Szrj reg_class_subset_p ((CLASS), FLOAT_REGS) 1362*38fd1498Szrj #define SSE_CLASS_P(CLASS) \ 1363*38fd1498Szrj reg_class_subset_p ((CLASS), ALL_SSE_REGS) 1364*38fd1498Szrj #define MMX_CLASS_P(CLASS) \ 1365*38fd1498Szrj ((CLASS) == MMX_REGS) 1366*38fd1498Szrj #define MASK_CLASS_P(CLASS) \ 1367*38fd1498Szrj reg_class_subset_p ((CLASS), MASK_REGS) 1368*38fd1498Szrj #define MAYBE_INTEGER_CLASS_P(CLASS) \ 1369*38fd1498Szrj reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1370*38fd1498Szrj #define MAYBE_FLOAT_CLASS_P(CLASS) \ 1371*38fd1498Szrj reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1372*38fd1498Szrj #define MAYBE_SSE_CLASS_P(CLASS) \ 1373*38fd1498Szrj reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) 1374*38fd1498Szrj #define MAYBE_MMX_CLASS_P(CLASS) \ 1375*38fd1498Szrj reg_classes_intersect_p ((CLASS), MMX_REGS) 1376*38fd1498Szrj #define MAYBE_MASK_CLASS_P(CLASS) \ 1377*38fd1498Szrj reg_classes_intersect_p ((CLASS), MASK_REGS) 1378*38fd1498Szrj 1379*38fd1498Szrj #define Q_CLASS_P(CLASS) \ 1380*38fd1498Szrj reg_class_subset_p ((CLASS), Q_REGS) 1381*38fd1498Szrj 1382*38fd1498Szrj #define MAYBE_NON_Q_CLASS_P(CLASS) \ 1383*38fd1498Szrj reg_classes_intersect_p ((CLASS), NON_Q_REGS) 1384*38fd1498Szrj 1385*38fd1498Szrj /* Give names of register classes as strings for dump file. */ 1386*38fd1498Szrj 1387*38fd1498Szrj #define REG_CLASS_NAMES \ 1388*38fd1498Szrj { "NO_REGS", \ 1389*38fd1498Szrj "AREG", "DREG", "CREG", "BREG", \ 1390*38fd1498Szrj "SIREG", "DIREG", \ 1391*38fd1498Szrj "AD_REGS", \ 1392*38fd1498Szrj "CLOBBERED_REGS", \ 1393*38fd1498Szrj "Q_REGS", "NON_Q_REGS", \ 1394*38fd1498Szrj "TLS_GOTBASE_REGS", \ 1395*38fd1498Szrj "INDEX_REGS", \ 1396*38fd1498Szrj "LEGACY_REGS", \ 1397*38fd1498Szrj "GENERAL_REGS", \ 1398*38fd1498Szrj "FP_TOP_REG", "FP_SECOND_REG", \ 1399*38fd1498Szrj "FLOAT_REGS", \ 1400*38fd1498Szrj "SSE_FIRST_REG", \ 1401*38fd1498Szrj "NO_REX_SSE_REGS", \ 1402*38fd1498Szrj "SSE_REGS", \ 1403*38fd1498Szrj "EVEX_SSE_REGS", \ 1404*38fd1498Szrj "BND_REGS", \ 1405*38fd1498Szrj "ALL_SSE_REGS", \ 1406*38fd1498Szrj "MMX_REGS", \ 1407*38fd1498Szrj "FP_TOP_SSE_REGS", \ 1408*38fd1498Szrj "FP_SECOND_SSE_REGS", \ 1409*38fd1498Szrj "FLOAT_SSE_REGS", \ 1410*38fd1498Szrj "FLOAT_INT_REGS", \ 1411*38fd1498Szrj "INT_SSE_REGS", \ 1412*38fd1498Szrj "FLOAT_INT_SSE_REGS", \ 1413*38fd1498Szrj "MASK_EVEX_REGS", \ 1414*38fd1498Szrj "MASK_REGS", \ 1415*38fd1498Szrj "MOD4_SSE_REGS", \ 1416*38fd1498Szrj "ALL_REGS" } 1417*38fd1498Szrj 1418*38fd1498Szrj /* Define which registers fit in which classes. This is an initializer 1419*38fd1498Szrj for a vector of HARD_REG_SET of length N_REG_CLASSES. 1420*38fd1498Szrj 1421*38fd1498Szrj Note that CLOBBERED_REGS are calculated by 1422*38fd1498Szrj TARGET_CONDITIONAL_REGISTER_USAGE. */ 1423*38fd1498Szrj 1424*38fd1498Szrj #define REG_CLASS_CONTENTS \ 1425*38fd1498Szrj { { 0x00, 0x0, 0x0 }, \ 1426*38fd1498Szrj { 0x01, 0x0, 0x0 }, /* AREG */ \ 1427*38fd1498Szrj { 0x02, 0x0, 0x0 }, /* DREG */ \ 1428*38fd1498Szrj { 0x04, 0x0, 0x0 }, /* CREG */ \ 1429*38fd1498Szrj { 0x08, 0x0, 0x0 }, /* BREG */ \ 1430*38fd1498Szrj { 0x10, 0x0, 0x0 }, /* SIREG */ \ 1431*38fd1498Szrj { 0x20, 0x0, 0x0 }, /* DIREG */ \ 1432*38fd1498Szrj { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ 1433*38fd1498Szrj { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ 1434*38fd1498Szrj { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ 1435*38fd1498Szrj { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \ 1436*38fd1498Szrj { 0x7e, 0x1fe0, 0x0 }, /* TLS_GOTBASE_REGS */ \ 1437*38fd1498Szrj { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \ 1438*38fd1498Szrj { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ 1439*38fd1498Szrj { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \ 1440*38fd1498Szrj { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ 1441*38fd1498Szrj { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ 1442*38fd1498Szrj { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ 1443*38fd1498Szrj { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ 1444*38fd1498Szrj { 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \ 1445*38fd1498Szrj { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ 1446*38fd1498Szrj { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \ 1447*38fd1498Szrj { 0x0, 0x0,0x1e000 }, /* BND_REGS */ \ 1448*38fd1498Szrj { 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ 1449*38fd1498Szrj { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ 1450*38fd1498Szrj { 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ 1451*38fd1498Szrj { 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ 1452*38fd1498Szrj { 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ 1453*38fd1498Szrj { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ 1454*38fd1498Szrj { 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ 1455*38fd1498Szrj { 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \ 1456*38fd1498Szrj { 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \ 1457*38fd1498Szrj { 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \ 1458*38fd1498Szrj { 0x1fe00000,0xffffe000, 0x1f }, /* MOD4_SSE_REGS */ \ 1459*38fd1498Szrj { 0xffffffff,0xffffffff,0x1ffff } \ 1460*38fd1498Szrj } 1461*38fd1498Szrj 1462*38fd1498Szrj /* The same information, inverted: 1463*38fd1498Szrj Return the class number of the smallest class containing 1464*38fd1498Szrj reg number REGNO. This could be a conditional expression 1465*38fd1498Szrj or could index an array. */ 1466*38fd1498Szrj 1467*38fd1498Szrj #define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)]) 1468*38fd1498Szrj 1469*38fd1498Szrj /* When this hook returns true for MODE, the compiler allows 1470*38fd1498Szrj registers explicitly used in the rtl to be used as spill registers 1471*38fd1498Szrj but prevents the compiler from extending the lifetime of these 1472*38fd1498Szrj registers. */ 1473*38fd1498Szrj #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 1474*38fd1498Szrj 1475*38fd1498Szrj #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) 1476*38fd1498Szrj #define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG) 1477*38fd1498Szrj 1478*38fd1498Szrj #define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X))) 1479*38fd1498Szrj #define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)) 1480*38fd1498Szrj 1481*38fd1498Szrj #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1482*38fd1498Szrj #define REX_INT_REGNO_P(N) \ 1483*38fd1498Szrj IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) 1484*38fd1498Szrj 1485*38fd1498Szrj #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1486*38fd1498Szrj #define GENERAL_REGNO_P(N) \ 1487*38fd1498Szrj (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N)) 1488*38fd1498Szrj 1489*38fd1498Szrj #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) 1490*38fd1498Szrj #define ANY_QI_REGNO_P(N) \ 1491*38fd1498Szrj (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) 1492*38fd1498Szrj 1493*38fd1498Szrj #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) 1494*38fd1498Szrj #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1495*38fd1498Szrj 1496*38fd1498Szrj #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) 1497*38fd1498Szrj #define SSE_REGNO_P(N) \ 1498*38fd1498Szrj (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ 1499*38fd1498Szrj || REX_SSE_REGNO_P (N) \ 1500*38fd1498Szrj || EXT_REX_SSE_REGNO_P (N)) 1501*38fd1498Szrj 1502*38fd1498Szrj #define REX_SSE_REGNO_P(N) \ 1503*38fd1498Szrj IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) 1504*38fd1498Szrj 1505*38fd1498Szrj #define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X))) 1506*38fd1498Szrj 1507*38fd1498Szrj #define EXT_REX_SSE_REGNO_P(N) \ 1508*38fd1498Szrj IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) 1509*38fd1498Szrj 1510*38fd1498Szrj #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1511*38fd1498Szrj #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) 1512*38fd1498Szrj 1513*38fd1498Szrj #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) 1514*38fd1498Szrj #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) 1515*38fd1498Szrj 1516*38fd1498Szrj #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) 1517*38fd1498Szrj #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 1518*38fd1498Szrj 1519*38fd1498Szrj #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1520*38fd1498Szrj #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1521*38fd1498Szrj 1522*38fd1498Szrj #define BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X))) 1523*38fd1498Szrj #define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG) 1524*38fd1498Szrj 1525*38fd1498Szrj #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X))) 1526*38fd1498Szrj #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \ 1527*38fd1498Szrj || (N) == XMM4_REG \ 1528*38fd1498Szrj || (N) == XMM8_REG \ 1529*38fd1498Szrj || (N) == XMM12_REG \ 1530*38fd1498Szrj || (N) == XMM16_REG \ 1531*38fd1498Szrj || (N) == XMM20_REG \ 1532*38fd1498Szrj || (N) == XMM24_REG \ 1533*38fd1498Szrj || (N) == XMM28_REG) 1534*38fd1498Szrj 1535*38fd1498Szrj /* First floating point reg */ 1536*38fd1498Szrj #define FIRST_FLOAT_REG FIRST_STACK_REG 1537*38fd1498Szrj #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) 1538*38fd1498Szrj 1539*38fd1498Szrj #define SSE_REGNO(N) \ 1540*38fd1498Szrj ((N) < 8 ? FIRST_SSE_REG + (N) \ 1541*38fd1498Szrj : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \ 1542*38fd1498Szrj : (FIRST_EXT_REX_SSE_REG + (N) - 16)) 1543*38fd1498Szrj 1544*38fd1498Szrj /* The class value for index registers, and the one for base regs. */ 1545*38fd1498Szrj 1546*38fd1498Szrj #define INDEX_REG_CLASS INDEX_REGS 1547*38fd1498Szrj #define BASE_REG_CLASS GENERAL_REGS 1548*38fd1498Szrj 1549*38fd1498Szrj /* Stack layout; function entry, exit and calling. */ 1550*38fd1498Szrj 1551*38fd1498Szrj /* Define this if pushing a word on the stack 1552*38fd1498Szrj makes the stack pointer a smaller address. */ 1553*38fd1498Szrj #define STACK_GROWS_DOWNWARD 1 1554*38fd1498Szrj 1555*38fd1498Szrj /* Define this to nonzero if the nominal address of the stack frame 1556*38fd1498Szrj is at the high-address end of the local variables; 1557*38fd1498Szrj that is, each additional local variable allocated 1558*38fd1498Szrj goes at a more negative offset in the frame. */ 1559*38fd1498Szrj #define FRAME_GROWS_DOWNWARD 1 1560*38fd1498Szrj 1561*38fd1498Szrj #define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES) 1562*38fd1498Szrj 1563*38fd1498Szrj /* If defined, the maximum amount of space required for outgoing arguments 1564*38fd1498Szrj will be computed and placed into the variable `crtl->outgoing_args_size'. 1565*38fd1498Szrj No space will be pushed onto the stack for each call; instead, the 1566*38fd1498Szrj function prologue should increase the stack frame size by this amount. 1567*38fd1498Szrj 1568*38fd1498Szrj In 32bit mode enabling argument accumulation results in about 5% code size 1569*38fd1498Szrj growth because move instructions are less compact than push. In 64bit 1570*38fd1498Szrj mode the difference is less drastic but visible. 1571*38fd1498Szrj 1572*38fd1498Szrj FIXME: Unlike earlier implementations, the size of unwind info seems to 1573*38fd1498Szrj actually grow with accumulation. Is that because accumulated args 1574*38fd1498Szrj unwind info became unnecesarily bloated? 1575*38fd1498Szrj 1576*38fd1498Szrj With the 64-bit MS ABI, we can generate correct code with or without 1577*38fd1498Szrj accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code 1578*38fd1498Szrj generated without accumulated args is terrible. 1579*38fd1498Szrj 1580*38fd1498Szrj If stack probes are required, the space used for large function 1581*38fd1498Szrj arguments on the stack must also be probed, so enable 1582*38fd1498Szrj -maccumulate-outgoing-args so this happens in the prologue. 1583*38fd1498Szrj 1584*38fd1498Szrj We must use argument accumulation in interrupt function if stack 1585*38fd1498Szrj may be realigned to avoid DRAP. */ 1586*38fd1498Szrj 1587*38fd1498Szrj #define ACCUMULATE_OUTGOING_ARGS \ 1588*38fd1498Szrj ((TARGET_ACCUMULATE_OUTGOING_ARGS \ 1589*38fd1498Szrj && optimize_function_for_speed_p (cfun)) \ 1590*38fd1498Szrj || (cfun->machine->func_type != TYPE_NORMAL \ 1591*38fd1498Szrj && crtl->stack_realign_needed) \ 1592*38fd1498Szrj || TARGET_STACK_PROBE \ 1593*38fd1498Szrj || TARGET_64BIT_MS_ABI \ 1594*38fd1498Szrj || (TARGET_MACHO && crtl->profile)) 1595*38fd1498Szrj 1596*38fd1498Szrj /* If defined, a C expression whose value is nonzero when we want to use PUSH 1597*38fd1498Szrj instructions to pass outgoing arguments. */ 1598*38fd1498Szrj 1599*38fd1498Szrj #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1600*38fd1498Szrj 1601*38fd1498Szrj /* We want the stack and args grow in opposite directions, even if 1602*38fd1498Szrj PUSH_ARGS is 0. */ 1603*38fd1498Szrj #define PUSH_ARGS_REVERSED 1 1604*38fd1498Szrj 1605*38fd1498Szrj /* Offset of first parameter from the argument pointer register value. */ 1606*38fd1498Szrj #define FIRST_PARM_OFFSET(FNDECL) 0 1607*38fd1498Szrj 1608*38fd1498Szrj /* Define this macro if functions should assume that stack space has been 1609*38fd1498Szrj allocated for arguments even when their values are passed in registers. 1610*38fd1498Szrj 1611*38fd1498Szrj The value of this macro is the size, in bytes, of the area reserved for 1612*38fd1498Szrj arguments passed in registers for the function represented by FNDECL. 1613*38fd1498Szrj 1614*38fd1498Szrj This space can be allocated by the caller, or be a part of the 1615*38fd1498Szrj machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1616*38fd1498Szrj which. */ 1617*38fd1498Szrj #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) 1618*38fd1498Szrj 1619*38fd1498Szrj #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ 1620*38fd1498Szrj (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) 1621*38fd1498Szrj 1622*38fd1498Szrj /* Define how to find the value returned by a library function 1623*38fd1498Szrj assuming the value has mode MODE. */ 1624*38fd1498Szrj 1625*38fd1498Szrj #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) 1626*38fd1498Szrj 1627*38fd1498Szrj /* Define the size of the result block used for communication between 1628*38fd1498Szrj untyped_call and untyped_return. The block contains a DImode value 1629*38fd1498Szrj followed by the block used by fnsave and frstor. */ 1630*38fd1498Szrj 1631*38fd1498Szrj #define APPLY_RESULT_SIZE (8+108) 1632*38fd1498Szrj 1633*38fd1498Szrj /* 1 if N is a possible register number for function argument passing. */ 1634*38fd1498Szrj #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1635*38fd1498Szrj 1636*38fd1498Szrj /* Define a data type for recording info about an argument list 1637*38fd1498Szrj during the scan of that argument list. This data type should 1638*38fd1498Szrj hold all necessary information about the function itself 1639*38fd1498Szrj and about the args processed so far, enough to enable macros 1640*38fd1498Szrj such as FUNCTION_ARG to determine where the next arg should go. */ 1641*38fd1498Szrj 1642*38fd1498Szrj typedef struct ix86_args { 1643*38fd1498Szrj int words; /* # words passed so far */ 1644*38fd1498Szrj int nregs; /* # registers available for passing */ 1645*38fd1498Szrj int regno; /* next available register number */ 1646*38fd1498Szrj int fastcall; /* fastcall or thiscall calling convention 1647*38fd1498Szrj is used */ 1648*38fd1498Szrj int sse_words; /* # sse words passed so far */ 1649*38fd1498Szrj int sse_nregs; /* # sse registers available for passing */ 1650*38fd1498Szrj int warn_avx512f; /* True when we want to warn 1651*38fd1498Szrj about AVX512F ABI. */ 1652*38fd1498Szrj int warn_avx; /* True when we want to warn about AVX ABI. */ 1653*38fd1498Szrj int warn_sse; /* True when we want to warn about SSE ABI. */ 1654*38fd1498Szrj int warn_mmx; /* True when we want to warn about MMX ABI. */ 1655*38fd1498Szrj int warn_empty; /* True when we want to warn about empty classes 1656*38fd1498Szrj passing ABI change. */ 1657*38fd1498Szrj int sse_regno; /* next available sse register number */ 1658*38fd1498Szrj int mmx_words; /* # mmx words passed so far */ 1659*38fd1498Szrj int mmx_nregs; /* # mmx registers available for passing */ 1660*38fd1498Szrj int mmx_regno; /* next available mmx register number */ 1661*38fd1498Szrj int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1662*38fd1498Szrj int caller; /* true if it is caller. */ 1663*38fd1498Szrj int float_in_sse; /* Set to 1 or 2 for 32bit targets if 1664*38fd1498Szrj SFmode/DFmode arguments should be passed 1665*38fd1498Szrj in SSE registers. Otherwise 0. */ 1666*38fd1498Szrj int bnd_regno; /* next available bnd register number */ 1667*38fd1498Szrj int bnds_in_bt; /* number of bounds expected in BT. */ 1668*38fd1498Szrj int force_bnd_pass; /* number of bounds expected for stdarg arg. */ 1669*38fd1498Szrj int stdarg; /* Set to 1 if function is stdarg. */ 1670*38fd1498Szrj enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 1671*38fd1498Szrj MS_ABI for ms abi. */ 1672*38fd1498Szrj tree decl; /* Callee decl. */ 1673*38fd1498Szrj } CUMULATIVE_ARGS; 1674*38fd1498Szrj 1675*38fd1498Szrj /* Initialize a variable CUM of type CUMULATIVE_ARGS 1676*38fd1498Szrj for a call to a function whose data type is FNTYPE. 1677*38fd1498Szrj For a library call, FNTYPE is 0. */ 1678*38fd1498Szrj 1679*38fd1498Szrj #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1680*38fd1498Szrj init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ 1681*38fd1498Szrj (N_NAMED_ARGS) != -1) 1682*38fd1498Szrj 1683*38fd1498Szrj /* Output assembler code to FILE to increment profiler label # LABELNO 1684*38fd1498Szrj for profiling a function entry. */ 1685*38fd1498Szrj 1686*38fd1498Szrj #define FUNCTION_PROFILER(FILE, LABELNO) \ 1687*38fd1498Szrj x86_function_profiler ((FILE), (LABELNO)) 1688*38fd1498Szrj 1689*38fd1498Szrj #define MCOUNT_NAME "_mcount" 1690*38fd1498Szrj 1691*38fd1498Szrj #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" 1692*38fd1498Szrj 1693*38fd1498Szrj #define PROFILE_COUNT_REGISTER "edx" 1694*38fd1498Szrj 1695*38fd1498Szrj /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1696*38fd1498Szrj the stack pointer does not matter. The value is tested only in 1697*38fd1498Szrj functions that have frame pointers. 1698*38fd1498Szrj No definition is equivalent to always zero. */ 1699*38fd1498Szrj /* Note on the 386 it might be more efficient not to define this since 1700*38fd1498Szrj we have to restore it ourselves from the frame pointer, in order to 1701*38fd1498Szrj use pop */ 1702*38fd1498Szrj 1703*38fd1498Szrj #define EXIT_IGNORE_STACK 1 1704*38fd1498Szrj 1705*38fd1498Szrj /* Define this macro as a C expression that is nonzero for registers 1706*38fd1498Szrj used by the epilogue or the `return' pattern. */ 1707*38fd1498Szrj 1708*38fd1498Szrj #define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO) 1709*38fd1498Szrj 1710*38fd1498Szrj /* Output assembler code for a block containing the constant parts 1711*38fd1498Szrj of a trampoline, leaving space for the variable parts. */ 1712*38fd1498Szrj 1713*38fd1498Szrj /* On the 386, the trampoline contains two instructions: 1714*38fd1498Szrj mov #STATIC,ecx 1715*38fd1498Szrj jmp FUNCTION 1716*38fd1498Szrj The trampoline is generated entirely at runtime. The operand of JMP 1717*38fd1498Szrj is the address of FUNCTION relative to the instruction following the 1718*38fd1498Szrj JMP (which is 5 bytes long). */ 1719*38fd1498Szrj 1720*38fd1498Szrj /* Length in units of the trampoline for entering a nested function. */ 1721*38fd1498Szrj 1722*38fd1498Szrj #define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14) 1723*38fd1498Szrj 1724*38fd1498Szrj /* Definitions for register eliminations. 1725*38fd1498Szrj 1726*38fd1498Szrj This is an array of structures. Each structure initializes one pair 1727*38fd1498Szrj of eliminable registers. The "from" register number is given first, 1728*38fd1498Szrj followed by "to". Eliminations of the same "from" register are listed 1729*38fd1498Szrj in order of preference. 1730*38fd1498Szrj 1731*38fd1498Szrj There are two registers that can always be eliminated on the i386. 1732*38fd1498Szrj The frame pointer and the arg pointer can be replaced by either the 1733*38fd1498Szrj hard frame pointer or to the stack pointer, depending upon the 1734*38fd1498Szrj circumstances. The hard frame pointer is not used before reload and 1735*38fd1498Szrj so it is not eligible for elimination. */ 1736*38fd1498Szrj 1737*38fd1498Szrj #define ELIMINABLE_REGS \ 1738*38fd1498Szrj {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1739*38fd1498Szrj { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1740*38fd1498Szrj { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1741*38fd1498Szrj { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1742*38fd1498Szrj 1743*38fd1498Szrj /* Define the offset between two registers, one to be eliminated, and the other 1744*38fd1498Szrj its replacement, at the start of a routine. */ 1745*38fd1498Szrj 1746*38fd1498Szrj #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1747*38fd1498Szrj ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1748*38fd1498Szrj 1749*38fd1498Szrj /* Addressing modes, and classification of registers for them. */ 1750*38fd1498Szrj 1751*38fd1498Szrj /* Macros to check register numbers against specific register classes. */ 1752*38fd1498Szrj 1753*38fd1498Szrj /* These assume that REGNO is a hard or pseudo reg number. 1754*38fd1498Szrj They give nonzero only if REGNO is a hard reg of the suitable class 1755*38fd1498Szrj or a pseudo reg currently allocated to a suitable hard reg. 1756*38fd1498Szrj Since they use reg_renumber, they are safe only once reg_renumber 1757*38fd1498Szrj has been allocated, which happens in reginfo.c during register 1758*38fd1498Szrj allocation. */ 1759*38fd1498Szrj 1760*38fd1498Szrj #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1761*38fd1498Szrj ((REGNO) < STACK_POINTER_REGNUM \ 1762*38fd1498Szrj || REX_INT_REGNO_P (REGNO) \ 1763*38fd1498Szrj || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ 1764*38fd1498Szrj || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1765*38fd1498Szrj 1766*38fd1498Szrj #define REGNO_OK_FOR_BASE_P(REGNO) \ 1767*38fd1498Szrj (GENERAL_REGNO_P (REGNO) \ 1768*38fd1498Szrj || (REGNO) == ARG_POINTER_REGNUM \ 1769*38fd1498Szrj || (REGNO) == FRAME_POINTER_REGNUM \ 1770*38fd1498Szrj || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1771*38fd1498Szrj 1772*38fd1498Szrj /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1773*38fd1498Szrj and check its validity for a certain class. 1774*38fd1498Szrj We have two alternate definitions for each of them. 1775*38fd1498Szrj The usual definition accepts all pseudo regs; the other rejects 1776*38fd1498Szrj them unless they have been allocated suitable hard regs. 1777*38fd1498Szrj The symbol REG_OK_STRICT causes the latter definition to be used. 1778*38fd1498Szrj 1779*38fd1498Szrj Most source files want to accept pseudo regs in the hope that 1780*38fd1498Szrj they will get allocated to the class that the insn wants them to be in. 1781*38fd1498Szrj Source files for reload pass need to be strict. 1782*38fd1498Szrj After reload, it makes no difference, since pseudo regs have 1783*38fd1498Szrj been eliminated by then. */ 1784*38fd1498Szrj 1785*38fd1498Szrj 1786*38fd1498Szrj /* Non strict versions, pseudos are ok. */ 1787*38fd1498Szrj #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1788*38fd1498Szrj (REGNO (X) < STACK_POINTER_REGNUM \ 1789*38fd1498Szrj || REX_INT_REGNO_P (REGNO (X)) \ 1790*38fd1498Szrj || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1791*38fd1498Szrj 1792*38fd1498Szrj #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1793*38fd1498Szrj (GENERAL_REGNO_P (REGNO (X)) \ 1794*38fd1498Szrj || REGNO (X) == ARG_POINTER_REGNUM \ 1795*38fd1498Szrj || REGNO (X) == FRAME_POINTER_REGNUM \ 1796*38fd1498Szrj || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1797*38fd1498Szrj 1798*38fd1498Szrj /* Strict versions, hard registers only */ 1799*38fd1498Szrj #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1800*38fd1498Szrj #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1801*38fd1498Szrj 1802*38fd1498Szrj #ifndef REG_OK_STRICT 1803*38fd1498Szrj #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1804*38fd1498Szrj #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1805*38fd1498Szrj 1806*38fd1498Szrj #else 1807*38fd1498Szrj #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1808*38fd1498Szrj #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1809*38fd1498Szrj #endif 1810*38fd1498Szrj 1811*38fd1498Szrj /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1812*38fd1498Szrj that is a valid memory address for an instruction. 1813*38fd1498Szrj The MODE argument is the machine mode for the MEM expression 1814*38fd1498Szrj that wants to use this address. 1815*38fd1498Szrj 1816*38fd1498Szrj The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, 1817*38fd1498Szrj except for CONSTANT_ADDRESS_P which is usually machine-independent. 1818*38fd1498Szrj 1819*38fd1498Szrj See legitimize_pic_address in i386.c for details as to what 1820*38fd1498Szrj constitutes a legitimate address when -fpic is used. */ 1821*38fd1498Szrj 1822*38fd1498Szrj #define MAX_REGS_PER_ADDRESS 2 1823*38fd1498Szrj 1824*38fd1498Szrj #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1825*38fd1498Szrj 1826*38fd1498Szrj /* If defined, a C expression to determine the base term of address X. 1827*38fd1498Szrj This macro is used in only one place: `find_base_term' in alias.c. 1828*38fd1498Szrj 1829*38fd1498Szrj It is always safe for this macro to not be defined. It exists so 1830*38fd1498Szrj that alias analysis can understand machine-dependent addresses. 1831*38fd1498Szrj 1832*38fd1498Szrj The typical use of this macro is to handle addresses containing 1833*38fd1498Szrj a label_ref or symbol_ref within an UNSPEC. */ 1834*38fd1498Szrj 1835*38fd1498Szrj #define FIND_BASE_TERM(X) ix86_find_base_term (X) 1836*38fd1498Szrj 1837*38fd1498Szrj /* Nonzero if the constant value X is a legitimate general operand 1838*38fd1498Szrj when generating PIC code. It is given that flag_pic is on and 1839*38fd1498Szrj that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1840*38fd1498Szrj 1841*38fd1498Szrj #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1842*38fd1498Szrj 1843*38fd1498Szrj #define SYMBOLIC_CONST(X) \ 1844*38fd1498Szrj (GET_CODE (X) == SYMBOL_REF \ 1845*38fd1498Szrj || GET_CODE (X) == LABEL_REF \ 1846*38fd1498Szrj || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1847*38fd1498Szrj 1848*38fd1498Szrj /* Max number of args passed in registers. If this is more than 3, we will 1849*38fd1498Szrj have problems with ebx (register #4), since it is a caller save register and 1850*38fd1498Szrj is also used as the pic register in ELF. So for now, don't allow more than 1851*38fd1498Szrj 3 registers to be passed in registers. */ 1852*38fd1498Szrj 1853*38fd1498Szrj /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ 1854*38fd1498Szrj #define X86_64_REGPARM_MAX 6 1855*38fd1498Szrj #define X86_64_MS_REGPARM_MAX 4 1856*38fd1498Szrj 1857*38fd1498Szrj #define X86_32_REGPARM_MAX 3 1858*38fd1498Szrj 1859*38fd1498Szrj #define REGPARM_MAX \ 1860*38fd1498Szrj (TARGET_64BIT \ 1861*38fd1498Szrj ? (TARGET_64BIT_MS_ABI \ 1862*38fd1498Szrj ? X86_64_MS_REGPARM_MAX \ 1863*38fd1498Szrj : X86_64_REGPARM_MAX) \ 1864*38fd1498Szrj : X86_32_REGPARM_MAX) 1865*38fd1498Szrj 1866*38fd1498Szrj #define X86_64_SSE_REGPARM_MAX 8 1867*38fd1498Szrj #define X86_64_MS_SSE_REGPARM_MAX 4 1868*38fd1498Szrj 1869*38fd1498Szrj #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) 1870*38fd1498Szrj 1871*38fd1498Szrj #define SSE_REGPARM_MAX \ 1872*38fd1498Szrj (TARGET_64BIT \ 1873*38fd1498Szrj ? (TARGET_64BIT_MS_ABI \ 1874*38fd1498Szrj ? X86_64_MS_SSE_REGPARM_MAX \ 1875*38fd1498Szrj : X86_64_SSE_REGPARM_MAX) \ 1876*38fd1498Szrj : X86_32_SSE_REGPARM_MAX) 1877*38fd1498Szrj 1878*38fd1498Szrj #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1879*38fd1498Szrj 1880*38fd1498Szrj /* Specify the machine mode that this machine uses 1881*38fd1498Szrj for the index in the tablejump instruction. */ 1882*38fd1498Szrj #define CASE_VECTOR_MODE \ 1883*38fd1498Szrj (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) 1884*38fd1498Szrj 1885*38fd1498Szrj /* Define this as 1 if `char' should by default be signed; else as 0. */ 1886*38fd1498Szrj #define DEFAULT_SIGNED_CHAR 1 1887*38fd1498Szrj 1888*38fd1498Szrj /* Max number of bytes we can move from memory to memory 1889*38fd1498Szrj in one reasonably fast instruction. */ 1890*38fd1498Szrj #define MOVE_MAX 16 1891*38fd1498Szrj 1892*38fd1498Szrj /* MOVE_MAX_PIECES is the number of bytes at a time which we can 1893*38fd1498Szrj move efficiently, as opposed to MOVE_MAX which is the maximum 1894*38fd1498Szrj number of bytes we can move with a single instruction. 1895*38fd1498Szrj 1896*38fd1498Szrj ??? We should use TImode in 32-bit mode and use OImode or XImode 1897*38fd1498Szrj if they are available. But since by_pieces_ninsns determines the 1898*38fd1498Szrj widest mode with MAX_FIXED_MODE_SIZE, we can only use TImode in 1899*38fd1498Szrj 64-bit mode. */ 1900*38fd1498Szrj #define MOVE_MAX_PIECES \ 1901*38fd1498Szrj ((TARGET_64BIT \ 1902*38fd1498Szrj && TARGET_SSE2 \ 1903*38fd1498Szrj && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 1904*38fd1498Szrj && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ 1905*38fd1498Szrj ? GET_MODE_SIZE (TImode) : UNITS_PER_WORD) 1906*38fd1498Szrj 1907*38fd1498Szrj /* If a memory-to-memory move would take MOVE_RATIO or more simple 1908*38fd1498Szrj move-instruction pairs, we will do a movmem or libcall instead. 1909*38fd1498Szrj Increasing the value will always make code faster, but eventually 1910*38fd1498Szrj incurs high cost in increased code size. 1911*38fd1498Szrj 1912*38fd1498Szrj If you don't define this, a reasonable default is used. */ 1913*38fd1498Szrj 1914*38fd1498Szrj #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) 1915*38fd1498Szrj 1916*38fd1498Szrj /* If a clear memory operation would take CLEAR_RATIO or more simple 1917*38fd1498Szrj move-instruction sequences, we will do a clrmem or libcall instead. */ 1918*38fd1498Szrj 1919*38fd1498Szrj #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) 1920*38fd1498Szrj 1921*38fd1498Szrj /* Define if shifts truncate the shift count which implies one can 1922*38fd1498Szrj omit a sign-extension or zero-extension of a shift count. 1923*38fd1498Szrj 1924*38fd1498Szrj On i386, shifts do truncate the count. But bit test instructions 1925*38fd1498Szrj take the modulo of the bit offset operand. */ 1926*38fd1498Szrj 1927*38fd1498Szrj /* #define SHIFT_COUNT_TRUNCATED */ 1928*38fd1498Szrj 1929*38fd1498Szrj /* A macro to update M and UNSIGNEDP when an object whose type is 1930*38fd1498Szrj TYPE and which has the specified mode and signedness is to be 1931*38fd1498Szrj stored in a register. This macro is only called when TYPE is a 1932*38fd1498Szrj scalar type. 1933*38fd1498Szrj 1934*38fd1498Szrj On i386 it is sometimes useful to promote HImode and QImode 1935*38fd1498Szrj quantities to SImode. The choice depends on target type. */ 1936*38fd1498Szrj 1937*38fd1498Szrj #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1938*38fd1498Szrj do { \ 1939*38fd1498Szrj if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1940*38fd1498Szrj || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1941*38fd1498Szrj (MODE) = SImode; \ 1942*38fd1498Szrj } while (0) 1943*38fd1498Szrj 1944*38fd1498Szrj /* Specify the machine mode that pointers have. 1945*38fd1498Szrj After generation of rtl, the compiler makes no further distinction 1946*38fd1498Szrj between pointers and any other objects of this machine mode. */ 1947*38fd1498Szrj #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) 1948*38fd1498Szrj 1949*38fd1498Szrj /* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save. 1950*38fd1498Szrj NONLOCAL needs space to save both shadow stack and stack pointers. 1951*38fd1498Szrj 1952*38fd1498Szrj FIXME: We only need to save and restore stack pointer in ptr_mode. 1953*38fd1498Szrj But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode 1954*38fd1498Szrj to save and restore stack pointer. See 1955*38fd1498Szrj https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150 1956*38fd1498Szrj */ 1957*38fd1498Szrj #define STACK_SAVEAREA_MODE(LEVEL) \ 1958*38fd1498Szrj ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) 1959*38fd1498Szrj 1960*38fd1498Szrj /* Specify the machine mode that bounds have. */ 1961*38fd1498Szrj #define BNDmode (ix86_pmode == PMODE_DI ? BND64mode : BND32mode) 1962*38fd1498Szrj 1963*38fd1498Szrj /* A C expression whose value is zero if pointers that need to be extended 1964*38fd1498Szrj from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1965*38fd1498Szrj greater then zero if they are zero-extended and less then zero if the 1966*38fd1498Szrj ptr_extend instruction should be used. */ 1967*38fd1498Szrj 1968*38fd1498Szrj #define POINTERS_EXTEND_UNSIGNED 1 1969*38fd1498Szrj 1970*38fd1498Szrj /* A function address in a call instruction 1971*38fd1498Szrj is a byte address (for indexing purposes) 1972*38fd1498Szrj so give the MEM rtx a byte's mode. */ 1973*38fd1498Szrj #define FUNCTION_MODE QImode 1974*38fd1498Szrj 1975*38fd1498Szrj 1976*38fd1498Szrj /* A C expression for the cost of a branch instruction. A value of 1 1977*38fd1498Szrj is the default; other values are interpreted relative to that. */ 1978*38fd1498Szrj 1979*38fd1498Szrj #define BRANCH_COST(speed_p, predictable_p) \ 1980*38fd1498Szrj (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) 1981*38fd1498Szrj 1982*38fd1498Szrj /* An integer expression for the size in bits of the largest integer machine 1983*38fd1498Szrj mode that should actually be used. We allow pairs of registers. */ 1984*38fd1498Szrj #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 1985*38fd1498Szrj 1986*38fd1498Szrj /* Define this macro as a C expression which is nonzero if accessing 1987*38fd1498Szrj less than a word of memory (i.e. a `char' or a `short') is no 1988*38fd1498Szrj faster than accessing a word of memory, i.e., if such access 1989*38fd1498Szrj require more than one instruction or if there is no difference in 1990*38fd1498Szrj cost between byte and (aligned) word loads. 1991*38fd1498Szrj 1992*38fd1498Szrj When this macro is not defined, the compiler will access a field by 1993*38fd1498Szrj finding the smallest containing object; when it is defined, a 1994*38fd1498Szrj fullword load will be used if alignment permits. Unless bytes 1995*38fd1498Szrj accesses are faster than word accesses, using word accesses is 1996*38fd1498Szrj preferable since it may eliminate subsequent memory access if 1997*38fd1498Szrj subsequent accesses occur to other fields in the same word of the 1998*38fd1498Szrj structure, but to different bytes. */ 1999*38fd1498Szrj 2000*38fd1498Szrj #define SLOW_BYTE_ACCESS 0 2001*38fd1498Szrj 2002*38fd1498Szrj /* Nonzero if access to memory by shorts is slow and undesirable. */ 2003*38fd1498Szrj #define SLOW_SHORT_ACCESS 0 2004*38fd1498Szrj 2005*38fd1498Szrj /* Define this macro if it is as good or better to call a constant 2006*38fd1498Szrj function address than to call an address kept in a register. 2007*38fd1498Szrj 2008*38fd1498Szrj Desirable on the 386 because a CALL with a constant address is 2009*38fd1498Szrj faster than one with a register address. */ 2010*38fd1498Szrj 2011*38fd1498Szrj #define NO_FUNCTION_CSE 1 2012*38fd1498Szrj 2013*38fd1498Szrj /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2014*38fd1498Szrj return the mode to be used for the comparison. 2015*38fd1498Szrj 2016*38fd1498Szrj For floating-point equality comparisons, CCFPEQmode should be used. 2017*38fd1498Szrj VOIDmode should be used in all other cases. 2018*38fd1498Szrj 2019*38fd1498Szrj For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2020*38fd1498Szrj possible, to allow for more combinations. */ 2021*38fd1498Szrj 2022*38fd1498Szrj #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2023*38fd1498Szrj 2024*38fd1498Szrj /* Return nonzero if MODE implies a floating point inequality can be 2025*38fd1498Szrj reversed. */ 2026*38fd1498Szrj 2027*38fd1498Szrj #define REVERSIBLE_CC_MODE(MODE) 1 2028*38fd1498Szrj 2029*38fd1498Szrj /* A C expression whose value is reversed condition code of the CODE for 2030*38fd1498Szrj comparison done in CC_MODE mode. */ 2031*38fd1498Szrj #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 2032*38fd1498Szrj 2033*38fd1498Szrj 2034*38fd1498Szrj /* Control the assembler format that we output, to the extent 2035*38fd1498Szrj this does not vary between assemblers. */ 2036*38fd1498Szrj 2037*38fd1498Szrj /* How to refer to registers in assembler output. 2038*38fd1498Szrj This sequence is indexed by compiler's hard-register-number (see above). */ 2039*38fd1498Szrj 2040*38fd1498Szrj /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". 2041*38fd1498Szrj For non floating point regs, the following are the HImode names. 2042*38fd1498Szrj 2043*38fd1498Szrj For float regs, the stack top is sometimes referred to as "%st(0)" 2044*38fd1498Szrj instead of just "%st". TARGET_PRINT_OPERAND handles this with the 2045*38fd1498Szrj "y" code. */ 2046*38fd1498Szrj 2047*38fd1498Szrj #define HI_REGISTER_NAMES \ 2048*38fd1498Szrj {"ax","dx","cx","bx","si","di","bp","sp", \ 2049*38fd1498Szrj "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 2050*38fd1498Szrj "argp", "flags", "fpsr", "fpcr", "frame", \ 2051*38fd1498Szrj "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2052*38fd1498Szrj "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 2053*38fd1498Szrj "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2054*38fd1498Szrj "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ 2055*38fd1498Szrj "xmm16", "xmm17", "xmm18", "xmm19", \ 2056*38fd1498Szrj "xmm20", "xmm21", "xmm22", "xmm23", \ 2057*38fd1498Szrj "xmm24", "xmm25", "xmm26", "xmm27", \ 2058*38fd1498Szrj "xmm28", "xmm29", "xmm30", "xmm31", \ 2059*38fd1498Szrj "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \ 2060*38fd1498Szrj "bnd0", "bnd1", "bnd2", "bnd3" } 2061*38fd1498Szrj 2062*38fd1498Szrj #define REGISTER_NAMES HI_REGISTER_NAMES 2063*38fd1498Szrj 2064*38fd1498Szrj /* Table of additional register names to use in user input. */ 2065*38fd1498Szrj 2066*38fd1498Szrj #define ADDITIONAL_REGISTER_NAMES \ 2067*38fd1498Szrj { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2068*38fd1498Szrj { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2069*38fd1498Szrj { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2070*38fd1498Szrj { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2071*38fd1498Szrj { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2072*38fd1498Szrj { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2073*38fd1498Szrj { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \ 2074*38fd1498Szrj { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \ 2075*38fd1498Szrj { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \ 2076*38fd1498Szrj { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \ 2077*38fd1498Szrj { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \ 2078*38fd1498Szrj { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \ 2079*38fd1498Szrj { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \ 2080*38fd1498Szrj { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \ 2081*38fd1498Szrj { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \ 2082*38fd1498Szrj { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \ 2083*38fd1498Szrj { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \ 2084*38fd1498Szrj { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \ 2085*38fd1498Szrj { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \ 2086*38fd1498Szrj { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \ 2087*38fd1498Szrj { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \ 2088*38fd1498Szrj { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} } 2089*38fd1498Szrj 2090*38fd1498Szrj /* Note we are omitting these since currently I don't know how 2091*38fd1498Szrj to get gcc to use these, since they want the same but different 2092*38fd1498Szrj number as al, and ax. 2093*38fd1498Szrj */ 2094*38fd1498Szrj 2095*38fd1498Szrj #define QI_REGISTER_NAMES \ 2096*38fd1498Szrj {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2097*38fd1498Szrj 2098*38fd1498Szrj /* These parallel the array above, and can be used to access bits 8:15 2099*38fd1498Szrj of regs 0 through 3. */ 2100*38fd1498Szrj 2101*38fd1498Szrj #define QI_HIGH_REGISTER_NAMES \ 2102*38fd1498Szrj {"ah", "dh", "ch", "bh", } 2103*38fd1498Szrj 2104*38fd1498Szrj /* How to renumber registers for dbx and gdb. */ 2105*38fd1498Szrj 2106*38fd1498Szrj #define DBX_REGISTER_NUMBER(N) \ 2107*38fd1498Szrj (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2108*38fd1498Szrj 2109*38fd1498Szrj extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2110*38fd1498Szrj extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2111*38fd1498Szrj extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2112*38fd1498Szrj 2113*38fd1498Szrj /* Before the prologue, RA is at 0(%esp). */ 2114*38fd1498Szrj #define INCOMING_RETURN_ADDR_RTX \ 2115*38fd1498Szrj gen_rtx_MEM (Pmode, stack_pointer_rtx) 2116*38fd1498Szrj 2117*38fd1498Szrj /* After the prologue, RA is at -4(AP) in the current frame. */ 2118*38fd1498Szrj #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2119*38fd1498Szrj ((COUNT) == 0 \ 2120*38fd1498Szrj ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ 2121*38fd1498Szrj -UNITS_PER_WORD)) \ 2122*38fd1498Szrj : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD))) 2123*38fd1498Szrj 2124*38fd1498Szrj /* PC is dbx register 8; let's use that column for RA. */ 2125*38fd1498Szrj #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2126*38fd1498Szrj 2127*38fd1498Szrj /* Before the prologue, there are return address and error code for 2128*38fd1498Szrj exception handler on the top of the frame. */ 2129*38fd1498Szrj #define INCOMING_FRAME_SP_OFFSET \ 2130*38fd1498Szrj (cfun->machine->func_type == TYPE_EXCEPTION \ 2131*38fd1498Szrj ? 2 * UNITS_PER_WORD : UNITS_PER_WORD) 2132*38fd1498Szrj 2133*38fd1498Szrj /* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in 2134*38fd1498Szrj .cfi_startproc. */ 2135*38fd1498Szrj #define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2136*38fd1498Szrj 2137*38fd1498Szrj /* Describe how we implement __builtin_eh_return. */ 2138*38fd1498Szrj #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) 2139*38fd1498Szrj #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) 2140*38fd1498Szrj 2141*38fd1498Szrj 2142*38fd1498Szrj /* Select a format to encode pointers in exception handling data. CODE 2143*38fd1498Szrj is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2144*38fd1498Szrj true if the symbol may be affected by dynamic relocations. 2145*38fd1498Szrj 2146*38fd1498Szrj ??? All x86 object file formats are capable of representing this. 2147*38fd1498Szrj After all, the relocation needed is the same as for the call insn. 2148*38fd1498Szrj Whether or not a particular assembler allows us to enter such, I 2149*38fd1498Szrj guess we'll have to see. */ 2150*38fd1498Szrj #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2151*38fd1498Szrj asm_preferred_eh_data_format ((CODE), (GLOBAL)) 2152*38fd1498Szrj 2153*38fd1498Szrj /* These are a couple of extensions to the formats accepted 2154*38fd1498Szrj by asm_fprintf: 2155*38fd1498Szrj %z prints out opcode suffix for word-mode instruction 2156*38fd1498Szrj %r prints out word-mode name for reg_names[arg] */ 2157*38fd1498Szrj #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 2158*38fd1498Szrj case 'z': \ 2159*38fd1498Szrj fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \ 2160*38fd1498Szrj break; \ 2161*38fd1498Szrj \ 2162*38fd1498Szrj case 'r': \ 2163*38fd1498Szrj { \ 2164*38fd1498Szrj unsigned int regno = va_arg ((ARGS), int); \ 2165*38fd1498Szrj if (LEGACY_INT_REGNO_P (regno)) \ 2166*38fd1498Szrj fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \ 2167*38fd1498Szrj fputs (reg_names[regno], (FILE)); \ 2168*38fd1498Szrj break; \ 2169*38fd1498Szrj } 2170*38fd1498Szrj 2171*38fd1498Szrj /* This is how to output an insn to push a register on the stack. */ 2172*38fd1498Szrj 2173*38fd1498Szrj #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2174*38fd1498Szrj asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO)) 2175*38fd1498Szrj 2176*38fd1498Szrj /* This is how to output an insn to pop a register from the stack. */ 2177*38fd1498Szrj 2178*38fd1498Szrj #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2179*38fd1498Szrj asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO)) 2180*38fd1498Szrj 2181*38fd1498Szrj /* This is how to output an element of a case-vector that is absolute. */ 2182*38fd1498Szrj 2183*38fd1498Szrj #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2184*38fd1498Szrj ix86_output_addr_vec_elt ((FILE), (VALUE)) 2185*38fd1498Szrj 2186*38fd1498Szrj /* This is how to output an element of a case-vector that is relative. */ 2187*38fd1498Szrj 2188*38fd1498Szrj #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2189*38fd1498Szrj ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2190*38fd1498Szrj 2191*38fd1498Szrj /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ 2192*38fd1498Szrj 2193*38fd1498Szrj #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ 2194*38fd1498Szrj { \ 2195*38fd1498Szrj if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ 2196*38fd1498Szrj (PTR) += TARGET_AVX ? 1 : 2; \ 2197*38fd1498Szrj } 2198*38fd1498Szrj 2199*38fd1498Szrj /* A C statement or statements which output an assembler instruction 2200*38fd1498Szrj opcode to the stdio stream STREAM. The macro-operand PTR is a 2201*38fd1498Szrj variable of type `char *' which points to the opcode name in 2202*38fd1498Szrj its "internal" form--the form that is written in the machine 2203*38fd1498Szrj description. */ 2204*38fd1498Szrj 2205*38fd1498Szrj #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 2206*38fd1498Szrj ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) 2207*38fd1498Szrj 2208*38fd1498Szrj /* A C statement to output to the stdio stream FILE an assembler 2209*38fd1498Szrj command to pad the location counter to a multiple of 1<<LOG 2210*38fd1498Szrj bytes if it is within MAX_SKIP bytes. */ 2211*38fd1498Szrj 2212*38fd1498Szrj #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2213*38fd1498Szrj #undef ASM_OUTPUT_MAX_SKIP_PAD 2214*38fd1498Szrj #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 2215*38fd1498Szrj if ((LOG) != 0) \ 2216*38fd1498Szrj { \ 2217*38fd1498Szrj if ((MAX_SKIP) == 0) \ 2218*38fd1498Szrj fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2219*38fd1498Szrj else \ 2220*38fd1498Szrj fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 2221*38fd1498Szrj } 2222*38fd1498Szrj #endif 2223*38fd1498Szrj 2224*38fd1498Szrj /* Write the extra assembler code needed to declare a function 2225*38fd1498Szrj properly. */ 2226*38fd1498Szrj 2227*38fd1498Szrj #undef ASM_OUTPUT_FUNCTION_LABEL 2228*38fd1498Szrj #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 2229*38fd1498Szrj ix86_asm_output_function_label ((FILE), (NAME), (DECL)) 2230*38fd1498Szrj 2231*38fd1498Szrj /* Under some conditions we need jump tables in the text section, 2232*38fd1498Szrj because the assembler cannot handle label differences between 2233*38fd1498Szrj sections. This is the case for x86_64 on Mach-O for example. */ 2234*38fd1498Szrj 2235*38fd1498Szrj #define JUMP_TABLES_IN_TEXT_SECTION \ 2236*38fd1498Szrj (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2237*38fd1498Szrj || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2238*38fd1498Szrj 2239*38fd1498Szrj /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2240*38fd1498Szrj and switch back. For x86 we do this only to save a few bytes that 2241*38fd1498Szrj would otherwise be unused in the text section. */ 2242*38fd1498Szrj #define CRT_MKSTR2(VAL) #VAL 2243*38fd1498Szrj #define CRT_MKSTR(x) CRT_MKSTR2(x) 2244*38fd1498Szrj 2245*38fd1498Szrj #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2246*38fd1498Szrj asm (SECTION_OP "\n\t" \ 2247*38fd1498Szrj "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ 2248*38fd1498Szrj TEXT_SECTION_ASM_OP); 2249*38fd1498Szrj 2250*38fd1498Szrj /* Default threshold for putting data in large sections 2251*38fd1498Szrj with x86-64 medium memory model */ 2252*38fd1498Szrj #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 2253*38fd1498Szrj 2254*38fd1498Szrj /* Adjust the length of the insn with the length of BND prefix. */ 2255*38fd1498Szrj 2256*38fd1498Szrj #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2257*38fd1498Szrj do { \ 2258*38fd1498Szrj if (NONDEBUG_INSN_P (INSN) && INSN_CODE (INSN) >= 0 \ 2259*38fd1498Szrj && get_attr_maybe_prefix_bnd (INSN)) \ 2260*38fd1498Szrj LENGTH += ix86_bnd_prefixed_insn_p (INSN); \ 2261*38fd1498Szrj } while (0) 2262*38fd1498Szrj 2263*38fd1498Szrj /* Which processor to tune code generation for. These must be in sync 2264*38fd1498Szrj with processor_target_table in i386.c. */ 2265*38fd1498Szrj 2266*38fd1498Szrj enum processor_type 2267*38fd1498Szrj { 2268*38fd1498Szrj PROCESSOR_GENERIC = 0, 2269*38fd1498Szrj PROCESSOR_I386, /* 80386 */ 2270*38fd1498Szrj PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2271*38fd1498Szrj PROCESSOR_PENTIUM, 2272*38fd1498Szrj PROCESSOR_LAKEMONT, 2273*38fd1498Szrj PROCESSOR_PENTIUMPRO, 2274*38fd1498Szrj PROCESSOR_PENTIUM4, 2275*38fd1498Szrj PROCESSOR_NOCONA, 2276*38fd1498Szrj PROCESSOR_CORE2, 2277*38fd1498Szrj PROCESSOR_NEHALEM, 2278*38fd1498Szrj PROCESSOR_SANDYBRIDGE, 2279*38fd1498Szrj PROCESSOR_HASWELL, 2280*38fd1498Szrj PROCESSOR_BONNELL, 2281*38fd1498Szrj PROCESSOR_SILVERMONT, 2282*38fd1498Szrj PROCESSOR_KNL, 2283*38fd1498Szrj PROCESSOR_KNM, 2284*38fd1498Szrj PROCESSOR_SKYLAKE, 2285*38fd1498Szrj PROCESSOR_SKYLAKE_AVX512, 2286*38fd1498Szrj PROCESSOR_CANNONLAKE, 2287*38fd1498Szrj PROCESSOR_ICELAKE_CLIENT, 2288*38fd1498Szrj PROCESSOR_ICELAKE_SERVER, 2289*38fd1498Szrj PROCESSOR_INTEL, 2290*38fd1498Szrj PROCESSOR_GEODE, 2291*38fd1498Szrj PROCESSOR_K6, 2292*38fd1498Szrj PROCESSOR_ATHLON, 2293*38fd1498Szrj PROCESSOR_K8, 2294*38fd1498Szrj PROCESSOR_AMDFAM10, 2295*38fd1498Szrj PROCESSOR_BDVER1, 2296*38fd1498Szrj PROCESSOR_BDVER2, 2297*38fd1498Szrj PROCESSOR_BDVER3, 2298*38fd1498Szrj PROCESSOR_BDVER4, 2299*38fd1498Szrj PROCESSOR_BTVER1, 2300*38fd1498Szrj PROCESSOR_BTVER2, 2301*38fd1498Szrj PROCESSOR_ZNVER1, 2302*38fd1498Szrj PROCESSOR_max 2303*38fd1498Szrj }; 2304*38fd1498Szrj 2305*38fd1498Szrj extern enum processor_type ix86_tune; 2306*38fd1498Szrj extern enum processor_type ix86_arch; 2307*38fd1498Szrj 2308*38fd1498Szrj /* Size of the RED_ZONE area. */ 2309*38fd1498Szrj #define RED_ZONE_SIZE 128 2310*38fd1498Szrj /* Reserved area of the red zone for temporaries. */ 2311*38fd1498Szrj #define RED_ZONE_RESERVE 8 2312*38fd1498Szrj 2313*38fd1498Szrj extern unsigned int ix86_preferred_stack_boundary; 2314*38fd1498Szrj extern unsigned int ix86_incoming_stack_boundary; 2315*38fd1498Szrj 2316*38fd1498Szrj /* Smallest class containing REGNO. */ 2317*38fd1498Szrj extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2318*38fd1498Szrj 2319*38fd1498Szrj enum ix86_fpcmp_strategy { 2320*38fd1498Szrj IX86_FPCMP_SAHF, 2321*38fd1498Szrj IX86_FPCMP_COMI, 2322*38fd1498Szrj IX86_FPCMP_ARITH 2323*38fd1498Szrj }; 2324*38fd1498Szrj 2325*38fd1498Szrj /* To properly truncate FP values into integers, we need to set i387 control 2326*38fd1498Szrj word. We can't emit proper mode switching code before reload, as spills 2327*38fd1498Szrj generated by reload may truncate values incorrectly, but we still can avoid 2328*38fd1498Szrj redundant computation of new control word by the mode switching pass. 2329*38fd1498Szrj The fldcw instructions are still emitted redundantly, but this is probably 2330*38fd1498Szrj not going to be noticeable problem, as most CPUs do have fast path for 2331*38fd1498Szrj the sequence. 2332*38fd1498Szrj 2333*38fd1498Szrj The machinery is to emit simple truncation instructions and split them 2334*38fd1498Szrj before reload to instructions having USEs of two memory locations that 2335*38fd1498Szrj are filled by this code to old and new control word. 2336*38fd1498Szrj 2337*38fd1498Szrj Post-reload pass may be later used to eliminate the redundant fildcw if 2338*38fd1498Szrj needed. */ 2339*38fd1498Szrj 2340*38fd1498Szrj enum ix86_stack_slot 2341*38fd1498Szrj { 2342*38fd1498Szrj SLOT_TEMP = 0, 2343*38fd1498Szrj SLOT_CW_STORED, 2344*38fd1498Szrj SLOT_CW_TRUNC, 2345*38fd1498Szrj SLOT_CW_FLOOR, 2346*38fd1498Szrj SLOT_CW_CEIL, 2347*38fd1498Szrj SLOT_CW_MASK_PM, 2348*38fd1498Szrj SLOT_STV_TEMP, 2349*38fd1498Szrj MAX_386_STACK_LOCALS 2350*38fd1498Szrj }; 2351*38fd1498Szrj 2352*38fd1498Szrj enum ix86_entity 2353*38fd1498Szrj { 2354*38fd1498Szrj X86_DIRFLAG = 0, 2355*38fd1498Szrj AVX_U128, 2356*38fd1498Szrj I387_TRUNC, 2357*38fd1498Szrj I387_FLOOR, 2358*38fd1498Szrj I387_CEIL, 2359*38fd1498Szrj I387_MASK_PM, 2360*38fd1498Szrj MAX_386_ENTITIES 2361*38fd1498Szrj }; 2362*38fd1498Szrj 2363*38fd1498Szrj enum x86_dirflag_state 2364*38fd1498Szrj { 2365*38fd1498Szrj X86_DIRFLAG_RESET, 2366*38fd1498Szrj X86_DIRFLAG_ANY 2367*38fd1498Szrj }; 2368*38fd1498Szrj 2369*38fd1498Szrj enum avx_u128_state 2370*38fd1498Szrj { 2371*38fd1498Szrj AVX_U128_CLEAN, 2372*38fd1498Szrj AVX_U128_DIRTY, 2373*38fd1498Szrj AVX_U128_ANY 2374*38fd1498Szrj }; 2375*38fd1498Szrj 2376*38fd1498Szrj /* Define this macro if the port needs extra instructions inserted 2377*38fd1498Szrj for mode switching in an optimizing compilation. */ 2378*38fd1498Szrj 2379*38fd1498Szrj #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2380*38fd1498Szrj ix86_optimize_mode_switching[(ENTITY)] 2381*38fd1498Szrj 2382*38fd1498Szrj /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2383*38fd1498Szrj initializer for an array of integers. Each initializer element N 2384*38fd1498Szrj refers to an entity that needs mode switching, and specifies the 2385*38fd1498Szrj number of different modes that might need to be set for this 2386*38fd1498Szrj entity. The position of the initializer in the initializer - 2387*38fd1498Szrj starting counting at zero - determines the integer that is used to 2388*38fd1498Szrj refer to the mode-switched entity in question. */ 2389*38fd1498Szrj 2390*38fd1498Szrj #define NUM_MODES_FOR_MODE_SWITCHING \ 2391*38fd1498Szrj { X86_DIRFLAG_ANY, AVX_U128_ANY, \ 2392*38fd1498Szrj I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2393*38fd1498Szrj 2394*38fd1498Szrj 2395*38fd1498Szrj /* Avoid renaming of stack registers, as doing so in combination with 2396*38fd1498Szrj scheduling just increases amount of live registers at time and in 2397*38fd1498Szrj the turn amount of fxch instructions needed. 2398*38fd1498Szrj 2399*38fd1498Szrj ??? Maybe Pentium chips benefits from renaming, someone can try.... 2400*38fd1498Szrj 2401*38fd1498Szrj Don't rename evex to non-evex sse registers. */ 2402*38fd1498Szrj 2403*38fd1498Szrj #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2404*38fd1498Szrj (!STACK_REGNO_P (SRC) \ 2405*38fd1498Szrj && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET)) 2406*38fd1498Szrj 2407*38fd1498Szrj 2408*38fd1498Szrj #define FASTCALL_PREFIX '@' 2409*38fd1498Szrj 2410*38fd1498Szrj #ifndef USED_FOR_TARGET 2411*38fd1498Szrj /* Structure describing stack frame layout. 2412*38fd1498Szrj Stack grows downward: 2413*38fd1498Szrj 2414*38fd1498Szrj [arguments] 2415*38fd1498Szrj <- ARG_POINTER 2416*38fd1498Szrj saved pc 2417*38fd1498Szrj 2418*38fd1498Szrj saved static chain if ix86_static_chain_on_stack 2419*38fd1498Szrj 2420*38fd1498Szrj saved frame pointer if frame_pointer_needed 2421*38fd1498Szrj <- HARD_FRAME_POINTER 2422*38fd1498Szrj [saved regs] 2423*38fd1498Szrj <- reg_save_offset 2424*38fd1498Szrj [padding0] 2425*38fd1498Szrj <- stack_realign_offset 2426*38fd1498Szrj [saved SSE regs] 2427*38fd1498Szrj OR 2428*38fd1498Szrj [stub-saved registers for ms x64 --> sysv clobbers 2429*38fd1498Szrj <- Start of out-of-line, stub-saved/restored regs 2430*38fd1498Szrj (see libgcc/config/i386/(sav|res)ms64*.S) 2431*38fd1498Szrj [XMM6-15] 2432*38fd1498Szrj [RSI] 2433*38fd1498Szrj [RDI] 2434*38fd1498Szrj [?RBX] only if RBX is clobbered 2435*38fd1498Szrj [?RBP] only if RBP and RBX are clobbered 2436*38fd1498Szrj [?R12] only if R12 and all previous regs are clobbered 2437*38fd1498Szrj [?R13] only if R13 and all previous regs are clobbered 2438*38fd1498Szrj [?R14] only if R14 and all previous regs are clobbered 2439*38fd1498Szrj [?R15] only if R15 and all previous regs are clobbered 2440*38fd1498Szrj <- end of stub-saved/restored regs 2441*38fd1498Szrj [padding1] 2442*38fd1498Szrj ] 2443*38fd1498Szrj <- sse_reg_save_offset 2444*38fd1498Szrj [padding2] 2445*38fd1498Szrj | <- FRAME_POINTER 2446*38fd1498Szrj [va_arg registers] | 2447*38fd1498Szrj | 2448*38fd1498Szrj [frame] | 2449*38fd1498Szrj | 2450*38fd1498Szrj [padding2] | = to_allocate 2451*38fd1498Szrj <- STACK_POINTER 2452*38fd1498Szrj */ 2453*38fd1498Szrj struct GTY(()) ix86_frame 2454*38fd1498Szrj { 2455*38fd1498Szrj int nsseregs; 2456*38fd1498Szrj int nregs; 2457*38fd1498Szrj int va_arg_size; 2458*38fd1498Szrj int red_zone_size; 2459*38fd1498Szrj int outgoing_arguments_size; 2460*38fd1498Szrj 2461*38fd1498Szrj /* The offsets relative to ARG_POINTER. */ 2462*38fd1498Szrj HOST_WIDE_INT frame_pointer_offset; 2463*38fd1498Szrj HOST_WIDE_INT hard_frame_pointer_offset; 2464*38fd1498Szrj HOST_WIDE_INT stack_pointer_offset; 2465*38fd1498Szrj HOST_WIDE_INT hfp_save_offset; 2466*38fd1498Szrj HOST_WIDE_INT reg_save_offset; 2467*38fd1498Szrj HOST_WIDE_INT stack_realign_allocate; 2468*38fd1498Szrj HOST_WIDE_INT stack_realign_offset; 2469*38fd1498Szrj HOST_WIDE_INT sse_reg_save_offset; 2470*38fd1498Szrj 2471*38fd1498Szrj /* When save_regs_using_mov is set, emit prologue using 2472*38fd1498Szrj move instead of push instructions. */ 2473*38fd1498Szrj bool save_regs_using_mov; 2474*38fd1498Szrj }; 2475*38fd1498Szrj 2476*38fd1498Szrj /* Machine specific frame tracking during prologue/epilogue generation. All 2477*38fd1498Szrj values are positive, but since the x86 stack grows downward, are subtratced 2478*38fd1498Szrj from the CFA to produce a valid address. */ 2479*38fd1498Szrj 2480*38fd1498Szrj struct GTY(()) machine_frame_state 2481*38fd1498Szrj { 2482*38fd1498Szrj /* This pair tracks the currently active CFA as reg+offset. When reg 2483*38fd1498Szrj is drap_reg, we don't bother trying to record here the real CFA when 2484*38fd1498Szrj it might really be a DW_CFA_def_cfa_expression. */ 2485*38fd1498Szrj rtx cfa_reg; 2486*38fd1498Szrj HOST_WIDE_INT cfa_offset; 2487*38fd1498Szrj 2488*38fd1498Szrj /* The current offset (canonically from the CFA) of ESP and EBP. 2489*38fd1498Szrj When stack frame re-alignment is active, these may not be relative 2490*38fd1498Szrj to the CFA. However, in all cases they are relative to the offsets 2491*38fd1498Szrj of the saved registers stored in ix86_frame. */ 2492*38fd1498Szrj HOST_WIDE_INT sp_offset; 2493*38fd1498Szrj HOST_WIDE_INT fp_offset; 2494*38fd1498Szrj 2495*38fd1498Szrj /* The size of the red-zone that may be assumed for the purposes of 2496*38fd1498Szrj eliding register restore notes in the epilogue. This may be zero 2497*38fd1498Szrj if no red-zone is in effect, or may be reduced from the real 2498*38fd1498Szrj red-zone value by a maximum runtime stack re-alignment value. */ 2499*38fd1498Szrj int red_zone_offset; 2500*38fd1498Szrj 2501*38fd1498Szrj /* Indicate whether each of ESP, EBP or DRAP currently holds a valid 2502*38fd1498Szrj value within the frame. If false then the offset above should be 2503*38fd1498Szrj ignored. Note that DRAP, if valid, *always* points to the CFA and 2504*38fd1498Szrj thus has an offset of zero. */ 2505*38fd1498Szrj BOOL_BITFIELD sp_valid : 1; 2506*38fd1498Szrj BOOL_BITFIELD fp_valid : 1; 2507*38fd1498Szrj BOOL_BITFIELD drap_valid : 1; 2508*38fd1498Szrj 2509*38fd1498Szrj /* Indicate whether the local stack frame has been re-aligned. When 2510*38fd1498Szrj set, the SP/FP offsets above are relative to the aligned frame 2511*38fd1498Szrj and not the CFA. */ 2512*38fd1498Szrj BOOL_BITFIELD realigned : 1; 2513*38fd1498Szrj 2514*38fd1498Szrj /* Indicates whether the stack pointer has been re-aligned. When set, 2515*38fd1498Szrj SP/FP continue to be relative to the CFA, but the stack pointer 2516*38fd1498Szrj should only be used for offsets > sp_realigned_offset, while 2517*38fd1498Szrj the frame pointer should be used for offsets <= sp_realigned_fp_last. 2518*38fd1498Szrj The flags realigned and sp_realigned are mutually exclusive. */ 2519*38fd1498Szrj BOOL_BITFIELD sp_realigned : 1; 2520*38fd1498Szrj 2521*38fd1498Szrj /* If sp_realigned is set, this is the last valid offset from the CFA 2522*38fd1498Szrj that can be used for access with the frame pointer. */ 2523*38fd1498Szrj HOST_WIDE_INT sp_realigned_fp_last; 2524*38fd1498Szrj 2525*38fd1498Szrj /* If sp_realigned is set, this is the offset from the CFA that the stack 2526*38fd1498Szrj pointer was realigned, and may or may not be equal to sp_realigned_fp_last. 2527*38fd1498Szrj Access via the stack pointer is only valid for offsets that are greater than 2528*38fd1498Szrj this value. */ 2529*38fd1498Szrj HOST_WIDE_INT sp_realigned_offset; 2530*38fd1498Szrj }; 2531*38fd1498Szrj 2532*38fd1498Szrj /* Private to winnt.c. */ 2533*38fd1498Szrj struct seh_frame_state; 2534*38fd1498Szrj 2535*38fd1498Szrj enum function_type 2536*38fd1498Szrj { 2537*38fd1498Szrj TYPE_UNKNOWN = 0, 2538*38fd1498Szrj TYPE_NORMAL, 2539*38fd1498Szrj /* The current function is an interrupt service routine with a 2540*38fd1498Szrj pointer argument as specified by the "interrupt" attribute. */ 2541*38fd1498Szrj TYPE_INTERRUPT, 2542*38fd1498Szrj /* The current function is an interrupt service routine with a 2543*38fd1498Szrj pointer argument and an integer argument as specified by the 2544*38fd1498Szrj "interrupt" attribute. */ 2545*38fd1498Szrj TYPE_EXCEPTION 2546*38fd1498Szrj }; 2547*38fd1498Szrj 2548*38fd1498Szrj struct GTY(()) machine_function { 2549*38fd1498Szrj struct stack_local_entry *stack_locals; 2550*38fd1498Szrj int varargs_gpr_size; 2551*38fd1498Szrj int varargs_fpr_size; 2552*38fd1498Szrj int optimize_mode_switching[MAX_386_ENTITIES]; 2553*38fd1498Szrj 2554*38fd1498Szrj /* Cached initial frame layout for the current function. */ 2555*38fd1498Szrj struct ix86_frame frame; 2556*38fd1498Szrj 2557*38fd1498Szrj /* For -fsplit-stack support: A stack local which holds a pointer to 2558*38fd1498Szrj the stack arguments for a function with a variable number of 2559*38fd1498Szrj arguments. This is set at the start of the function and is used 2560*38fd1498Szrj to initialize the overflow_arg_area field of the va_list 2561*38fd1498Szrj structure. */ 2562*38fd1498Szrj rtx split_stack_varargs_pointer; 2563*38fd1498Szrj 2564*38fd1498Szrj /* This value is used for amd64 targets and specifies the current abi 2565*38fd1498Szrj to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ 2566*38fd1498Szrj ENUM_BITFIELD(calling_abi) call_abi : 8; 2567*38fd1498Szrj 2568*38fd1498Szrj /* Nonzero if the function accesses a previous frame. */ 2569*38fd1498Szrj BOOL_BITFIELD accesses_prev_frame : 1; 2570*38fd1498Szrj 2571*38fd1498Szrj /* Set by ix86_compute_frame_layout and used by prologue/epilogue 2572*38fd1498Szrj expander to determine the style used. */ 2573*38fd1498Szrj BOOL_BITFIELD use_fast_prologue_epilogue : 1; 2574*38fd1498Szrj 2575*38fd1498Szrj /* Nonzero if the current function calls pc thunk and 2576*38fd1498Szrj must not use the red zone. */ 2577*38fd1498Szrj BOOL_BITFIELD pc_thunk_call_expanded : 1; 2578*38fd1498Szrj 2579*38fd1498Szrj /* If true, the current function needs the default PIC register, not 2580*38fd1498Szrj an alternate register (on x86) and must not use the red zone (on 2581*38fd1498Szrj x86_64), even if it's a leaf function. We don't want the 2582*38fd1498Szrj function to be regarded as non-leaf because TLS calls need not 2583*38fd1498Szrj affect register allocation. This flag is set when a TLS call 2584*38fd1498Szrj instruction is expanded within a function, and never reset, even 2585*38fd1498Szrj if all such instructions are optimized away. Use the 2586*38fd1498Szrj ix86_current_function_calls_tls_descriptor macro for a better 2587*38fd1498Szrj approximation. */ 2588*38fd1498Szrj BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; 2589*38fd1498Szrj 2590*38fd1498Szrj /* If true, the current function has a STATIC_CHAIN is placed on the 2591*38fd1498Szrj stack below the return address. */ 2592*38fd1498Szrj BOOL_BITFIELD static_chain_on_stack : 1; 2593*38fd1498Szrj 2594*38fd1498Szrj /* If true, it is safe to not save/restore DRAP register. */ 2595*38fd1498Szrj BOOL_BITFIELD no_drap_save_restore : 1; 2596*38fd1498Szrj 2597*38fd1498Szrj /* Function type. */ 2598*38fd1498Szrj ENUM_BITFIELD(function_type) func_type : 2; 2599*38fd1498Szrj 2600*38fd1498Szrj /* How to generate indirec branch. */ 2601*38fd1498Szrj ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3; 2602*38fd1498Szrj 2603*38fd1498Szrj /* If true, the current function has local indirect jumps, like 2604*38fd1498Szrj "indirect_jump" or "tablejump". */ 2605*38fd1498Szrj BOOL_BITFIELD has_local_indirect_jump : 1; 2606*38fd1498Szrj 2607*38fd1498Szrj /* How to generate function return. */ 2608*38fd1498Szrj ENUM_BITFIELD(indirect_branch) function_return_type : 3; 2609*38fd1498Szrj 2610*38fd1498Szrj /* If true, the current function is a function specified with 2611*38fd1498Szrj the "interrupt" or "no_caller_saved_registers" attribute. */ 2612*38fd1498Szrj BOOL_BITFIELD no_caller_saved_registers : 1; 2613*38fd1498Szrj 2614*38fd1498Szrj /* If true, there is register available for argument passing. This 2615*38fd1498Szrj is used only in ix86_function_ok_for_sibcall by 32-bit to determine 2616*38fd1498Szrj if there is scratch register available for indirect sibcall. In 2617*38fd1498Szrj 64-bit, rax, r10 and r11 are scratch registers which aren't used to 2618*38fd1498Szrj pass arguments and can be used for indirect sibcall. */ 2619*38fd1498Szrj BOOL_BITFIELD arg_reg_available : 1; 2620*38fd1498Szrj 2621*38fd1498Szrj /* If true, we're out-of-lining reg save/restore for regs clobbered 2622*38fd1498Szrj by 64-bit ms_abi functions calling a sysv_abi function. */ 2623*38fd1498Szrj BOOL_BITFIELD call_ms2sysv : 1; 2624*38fd1498Szrj 2625*38fd1498Szrj /* If true, the incoming 16-byte aligned stack has an offset (of 8) and 2626*38fd1498Szrj needs padding prior to out-of-line stub save/restore area. */ 2627*38fd1498Szrj BOOL_BITFIELD call_ms2sysv_pad_in : 1; 2628*38fd1498Szrj 2629*38fd1498Szrj /* This is the number of extra registers saved by stub (valid range is 2630*38fd1498Szrj 0-6). Each additional register is only saved/restored by the stubs 2631*38fd1498Szrj if all successive ones are. (Will always be zero when using a hard 2632*38fd1498Szrj frame pointer.) */ 2633*38fd1498Szrj unsigned int call_ms2sysv_extra_regs:3; 2634*38fd1498Szrj 2635*38fd1498Szrj /* Nonzero if the function places outgoing arguments on stack. */ 2636*38fd1498Szrj BOOL_BITFIELD outgoing_args_on_stack : 1; 2637*38fd1498Szrj 2638*38fd1498Szrj /* The largest alignment, in bytes, of stack slot actually used. */ 2639*38fd1498Szrj unsigned int max_used_stack_alignment; 2640*38fd1498Szrj 2641*38fd1498Szrj /* During prologue/epilogue generation, the current frame state. 2642*38fd1498Szrj Otherwise, the frame state at the end of the prologue. */ 2643*38fd1498Szrj struct machine_frame_state fs; 2644*38fd1498Szrj 2645*38fd1498Szrj /* During SEH output, this is non-null. */ 2646*38fd1498Szrj struct seh_frame_state * GTY((skip(""))) seh; 2647*38fd1498Szrj }; 2648*38fd1498Szrj #endif 2649*38fd1498Szrj 2650*38fd1498Szrj #define ix86_stack_locals (cfun->machine->stack_locals) 2651*38fd1498Szrj #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) 2652*38fd1498Szrj #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) 2653*38fd1498Szrj #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2654*38fd1498Szrj #define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded) 2655*38fd1498Szrj #define ix86_tls_descriptor_calls_expanded_in_cfun \ 2656*38fd1498Szrj (cfun->machine->tls_descriptor_call_expanded_p) 2657*38fd1498Szrj /* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2658*38fd1498Szrj calls are optimized away, we try to detect cases in which it was 2659*38fd1498Szrj optimized away. Since such instructions (use (reg REG_SP)), we can 2660*38fd1498Szrj verify whether there's any such instruction live by testing that 2661*38fd1498Szrj REG_SP is live. */ 2662*38fd1498Szrj #define ix86_current_function_calls_tls_descriptor \ 2663*38fd1498Szrj (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) 2664*38fd1498Szrj #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) 2665*38fd1498Szrj #define ix86_red_zone_size (cfun->machine->frame.red_zone_size) 2666*38fd1498Szrj 2667*38fd1498Szrj /* Control behavior of x86_file_start. */ 2668*38fd1498Szrj #define X86_FILE_START_VERSION_DIRECTIVE false 2669*38fd1498Szrj #define X86_FILE_START_FLTUSED false 2670*38fd1498Szrj 2671*38fd1498Szrj /* Flag to mark data that is in the large address area. */ 2672*38fd1498Szrj #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2673*38fd1498Szrj #define SYMBOL_REF_FAR_ADDR_P(X) \ 2674*38fd1498Szrj ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2675*38fd1498Szrj 2676*38fd1498Szrj /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to 2677*38fd1498Szrj have defined always, to avoid ifdefing. */ 2678*38fd1498Szrj #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) 2679*38fd1498Szrj #define SYMBOL_REF_DLLIMPORT_P(X) \ 2680*38fd1498Szrj ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) 2681*38fd1498Szrj 2682*38fd1498Szrj #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) 2683*38fd1498Szrj #define SYMBOL_REF_DLLEXPORT_P(X) \ 2684*38fd1498Szrj ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) 2685*38fd1498Szrj 2686*38fd1498Szrj #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) 2687*38fd1498Szrj #define SYMBOL_REF_STUBVAR_P(X) \ 2688*38fd1498Szrj ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) 2689*38fd1498Szrj 2690*38fd1498Szrj extern void debug_ready_dispatch (void); 2691*38fd1498Szrj extern void debug_dispatch_window (int); 2692*38fd1498Szrj 2693*38fd1498Szrj /* The value at zero is only defined for the BMI instructions 2694*38fd1498Szrj LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ 2695*38fd1498Szrj #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2696*38fd1498Szrj ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0) 2697*38fd1498Szrj #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2698*38fd1498Szrj ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0) 2699*38fd1498Szrj 2700*38fd1498Szrj 2701*38fd1498Szrj /* Flags returned by ix86_get_callcvt (). */ 2702*38fd1498Szrj #define IX86_CALLCVT_CDECL 0x1 2703*38fd1498Szrj #define IX86_CALLCVT_STDCALL 0x2 2704*38fd1498Szrj #define IX86_CALLCVT_FASTCALL 0x4 2705*38fd1498Szrj #define IX86_CALLCVT_THISCALL 0x8 2706*38fd1498Szrj #define IX86_CALLCVT_REGPARM 0x10 2707*38fd1498Szrj #define IX86_CALLCVT_SSEREGPARM 0x20 2708*38fd1498Szrj 2709*38fd1498Szrj #define IX86_BASE_CALLCVT(FLAGS) \ 2710*38fd1498Szrj ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ 2711*38fd1498Szrj | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) 2712*38fd1498Szrj 2713*38fd1498Szrj #define RECIP_MASK_NONE 0x00 2714*38fd1498Szrj #define RECIP_MASK_DIV 0x01 2715*38fd1498Szrj #define RECIP_MASK_SQRT 0x02 2716*38fd1498Szrj #define RECIP_MASK_VEC_DIV 0x04 2717*38fd1498Szrj #define RECIP_MASK_VEC_SQRT 0x08 2718*38fd1498Szrj #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ 2719*38fd1498Szrj | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2720*38fd1498Szrj #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2721*38fd1498Szrj 2722*38fd1498Szrj #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) 2723*38fd1498Szrj #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) 2724*38fd1498Szrj #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) 2725*38fd1498Szrj #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) 2726*38fd1498Szrj 2727*38fd1498Szrj /* Use 128-bit AVX instructions in the auto-vectorizer. */ 2728*38fd1498Szrj #define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128) 2729*38fd1498Szrj /* Use 256-bit AVX instructions in the auto-vectorizer. */ 2730*38fd1498Szrj #define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \ 2731*38fd1498Szrj || prefer_vector_width_type == PVW_AVX256) 2732*38fd1498Szrj 2733*38fd1498Szrj #define TARGET_INDIRECT_BRANCH_REGISTER \ 2734*38fd1498Szrj (ix86_indirect_branch_register \ 2735*38fd1498Szrj || cfun->machine->indirect_branch_type != indirect_branch_keep) 2736*38fd1498Szrj 2737*38fd1498Szrj #define IX86_HLE_ACQUIRE (1 << 16) 2738*38fd1498Szrj #define IX86_HLE_RELEASE (1 << 17) 2739*38fd1498Szrj 2740*38fd1498Szrj /* For switching between functions with different target attributes. */ 2741*38fd1498Szrj #define SWITCHABLE_TARGET 1 2742*38fd1498Szrj 2743*38fd1498Szrj #define TARGET_SUPPORTS_WIDE_INT 1 2744*38fd1498Szrj 2745*38fd1498Szrj /* 2746*38fd1498Szrj Local variables: 2747*38fd1498Szrj version-control: t 2748*38fd1498Szrj End: 2749*38fd1498Szrj */ 2750