1;; Slivermont(SLM) Scheduling 2;; Copyright (C) 2009-2018 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19;; 20;; Silvermont has 2 out-of-order IEC, 2 in-order FEC and 1 in-order MEC. 21 22 23(define_automaton "slm") 24 25;; EU: Execution Unit 26;; Silvermont EUs are connected by port 0 or port 1. 27 28;; SLM has two ports: port 0 and port 1 connecting to all execution units 29(define_cpu_unit "slm-port-0,slm-port-1" "slm") 30 31(define_cpu_unit "slm-ieu-0, slm-ieu-1, 32 slm-imul, slm-feu-0, slm-feu-1" 33 "slm") 34 35(define_reservation "slm-all-ieu" "(slm-ieu-0 + slm-ieu-1 + slm-imul)") 36(define_reservation "slm-all-feu" "(slm-feu-0 + slm-feu-1)") 37(define_reservation "slm-all-eu" "(slm-all-ieu + slm-all-feu)") 38(define_reservation "slm-fp-0" "(slm-port-0 + slm-feu-0)") 39 40;; Some EUs have duplicated copied and can be accessed via either 41;; port 0 or port 1 42;; (define_reservation "slm-port-either" "(slm-port-0 | slm-port-1)" 43(define_reservation "slm-port-dual" "(slm-port-0 + slm-port-1)") 44 45;;; fmul insn can have 4 or 5 cycles latency 46(define_reservation "slm-fmul-5c" 47 "(slm-port-0 + slm-feu-0), slm-feu-0, nothing*3") 48(define_reservation "slm-fmul-4c" "(slm-port-0 + slm-feu-0), nothing*3") 49 50;;; fadd can has 3 cycles latency depends on instruction forms 51(define_reservation "slm-fadd-3c" "(slm-port-1 + slm-feu-1), nothing*2") 52(define_reservation "slm-fadd-4c" 53 "(slm-port-1 + slm-feu-1), slm-feu-1, nothing*2") 54 55;;; imul insn has 3 cycles latency for SI operands 56(define_reservation "slm-imul-32" 57 "(slm-port-1 + slm-imul), nothing*2") 58(define_reservation "slm-imul-mem-32" 59 "(slm-port-1 + slm-imul + slm-port-0), nothing*2") 60;;; imul has 4 cycles latency for DI operands with 1/2 tput 61(define_reservation "slm-imul-64" 62 "(slm-port-1 + slm-imul), slm-imul, nothing*2") 63 64;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on 65;;; instruction forms 66(define_reservation "slm-dual-1c" "(slm-port-dual + slm-all-eu)") 67(define_reservation "slm-dual-2c" 68 "(slm-port-dual + slm-all-eu, nothing)") 69 70;;; Most of simple ALU instructions have 1 cycle latency. Some of them 71;;; issue in port 0, some in port 0 and some in either port. 72(define_reservation "slm-simple-0" "(slm-port-0 + slm-ieu-0)") 73(define_reservation "slm-simple-1" "(slm-port-1 + slm-ieu-1)") 74(define_reservation "slm-simple-either" "(slm-simple-0 | slm-simple-1)") 75 76;;; Complex macro-instruction has variants of latency, and uses both ports. 77(define_reservation "slm-complex" "(slm-port-dual + slm-all-eu)") 78 79(define_insn_reservation "slm_other" 9 80 (and (eq_attr "cpu" "slm") 81 (and (eq_attr "type" "other") 82 (eq_attr "atom_unit" "!jeu"))) 83 "slm-complex, slm-all-eu*8") 84 85;; return has type "other" with atom_unit "jeu" 86(define_insn_reservation "slm_other_2" 1 87 (and (eq_attr "cpu" "slm") 88 (and (eq_attr "type" "other") 89 (eq_attr "atom_unit" "jeu"))) 90 "slm-dual-1c") 91 92(define_insn_reservation "slm_multi" 9 93 (and (eq_attr "cpu" "slm") 94 (eq_attr "type" "multi")) 95 "slm-complex, slm-all-eu*8") 96 97;; Normal alu insns without carry 98(define_insn_reservation "slm_alu" 1 99 (and (eq_attr "cpu" "slm") 100 (and (eq_attr "type" "alu") 101 (and (eq_attr "memory" "none") 102 (eq_attr "use_carry" "0")))) 103 "slm-simple-either") 104 105;; Normal alu insns without carry, but use MEC. 106(define_insn_reservation "slm_alu_mem" 1 107 (and (eq_attr "cpu" "slm") 108 (and (eq_attr "type" "alu") 109 (and (eq_attr "memory" "!none") 110 (eq_attr "use_carry" "0")))) 111 "slm-simple-either") 112 113;; Alu insn consuming CF, such as add/sbb 114(define_insn_reservation "slm_alu_carry" 2 115 (and (eq_attr "cpu" "slm") 116 (and (eq_attr "type" "alu") 117 (and (eq_attr "memory" "none") 118 (eq_attr "use_carry" "1")))) 119 "slm-simple-either, nothing") 120 121;; Alu insn consuming CF, such as add/sbb 122(define_insn_reservation "slm_alu_carry_mem" 2 123 (and (eq_attr "cpu" "slm") 124 (and (eq_attr "type" "alu") 125 (and (eq_attr "memory" "!none") 126 (eq_attr "use_carry" "1")))) 127 "slm-simple-either, nothing") 128 129(define_insn_reservation "slm_alu1" 1 130 (and (eq_attr "cpu" "slm") 131 (and (eq_attr "type" "alu1") 132 (eq_attr "memory" "none") (eq_attr "prefix_0f" "0"))) 133 "slm-simple-either") 134 135;; bsf and bsf insn 136(define_insn_reservation "slm_alu1_1" 10 137 (and (eq_attr "cpu" "slm") 138 (and (eq_attr "type" "alu1") 139 (eq_attr "memory" "none") (eq_attr "prefix_0f" "1"))) 140 "slm-simple-1, slm-ieu-1*9") 141 142(define_insn_reservation "slm_alu1_mem" 1 143 (and (eq_attr "cpu" "slm") 144 (and (eq_attr "type" "alu1") 145 (eq_attr "memory" "!none"))) 146 "slm-simple-either") 147 148(define_insn_reservation "slm_negnot" 1 149 (and (eq_attr "cpu" "slm") 150 (and (eq_attr "type" "negnot") 151 (eq_attr "memory" "none"))) 152 "slm-simple-either") 153 154(define_insn_reservation "slm_negnot_mem" 1 155 (and (eq_attr "cpu" "slm") 156 (and (eq_attr "type" "negnot") 157 (eq_attr "memory" "!none"))) 158 "slm-simple-either") 159 160(define_insn_reservation "slm_imov" 1 161 (and (eq_attr "cpu" "slm") 162 (and (eq_attr "type" "imov") 163 (eq_attr "memory" "none"))) 164 "slm-simple-either") 165 166(define_insn_reservation "slm_imov_mem" 1 167 (and (eq_attr "cpu" "slm") 168 (and (eq_attr "type" "imov") 169 (eq_attr "memory" "!none"))) 170 "slm-simple-0") 171 172;; 16<-16, 32<-32 173(define_insn_reservation "slm_imovx" 1 174 (and (eq_attr "cpu" "slm") 175 (and (eq_attr "type" "imovx") 176 (and (eq_attr "memory" "none") 177 (ior (and (match_operand:HI 0 "register_operand") 178 (match_operand:HI 1 "general_operand")) 179 (and (match_operand:SI 0 "register_operand") 180 (match_operand:SI 1 "general_operand")))))) 181 "slm-simple-either") 182 183;; 16<-16, 32<-32, mem 184(define_insn_reservation "slm_imovx_mem" 1 185 (and (eq_attr "cpu" "slm") 186 (and (eq_attr "type" "imovx") 187 (and (eq_attr "memory" "!none") 188 (ior (and (match_operand:HI 0 "register_operand") 189 (match_operand:HI 1 "general_operand")) 190 (and (match_operand:SI 0 "register_operand") 191 (match_operand:SI 1 "general_operand")))))) 192 "slm-simple-either") 193 194;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8 195(define_insn_reservation "slm_imovx_2" 1 196 (and (eq_attr "cpu" "slm") 197 (and (eq_attr "type" "imovx") 198 (and (eq_attr "memory" "none") 199 (ior (match_operand:QI 0 "register_operand") 200 (ior (and (match_operand:SI 0 "register_operand") 201 (not (match_operand:SI 1 "general_operand"))) 202 (match_operand:DI 0 "register_operand")))))) 203 "slm-simple-either") 204 205;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem 206(define_insn_reservation "slm_imovx_2_mem" 1 207 (and (eq_attr "cpu" "slm") 208 (and (eq_attr "type" "imovx") 209 (and (eq_attr "memory" "!none") 210 (ior (match_operand:QI 0 "register_operand") 211 (ior (and (match_operand:SI 0 "register_operand") 212 (not (match_operand:SI 1 "general_operand"))) 213 (match_operand:DI 0 "register_operand")))))) 214 "slm-simple-0") 215 216;; 16<-8 217(define_insn_reservation "slm_imovx_3" 3 218 (and (eq_attr "cpu" "slm") 219 (and (eq_attr "type" "imovx") 220 (and (match_operand:HI 0 "register_operand") 221 (match_operand:QI 1 "general_operand")))) 222 "slm-simple-0, nothing*2") 223 224(define_insn_reservation "slm_lea" 1 225 (and (eq_attr "cpu" "slm") 226 (and (eq_attr "type" "lea") 227 (eq_attr "mode" "!HI"))) 228 "slm-simple-either") 229 230;; lea 16bit address is complex insn 231(define_insn_reservation "slm_lea_2" 2 232 (and (eq_attr "cpu" "slm") 233 (and (eq_attr "type" "lea") 234 (eq_attr "mode" "HI"))) 235 "slm-complex, slm-all-eu") 236 237(define_insn_reservation "slm_incdec" 1 238 (and (eq_attr "cpu" "slm") 239 (and (eq_attr "type" "incdec") 240 (eq_attr "memory" "none"))) 241 "slm-simple-0") 242 243(define_insn_reservation "slm_incdec_mem" 3 244 (and (eq_attr "cpu" "slm") 245 (and (eq_attr "type" "incdec") 246 (eq_attr "memory" "!none"))) 247 "slm-simple-0, nothing*2") 248 249;; simple shift instruction use SHIFT eu, none memory 250(define_insn_reservation "slm_ishift" 1 251 (and (eq_attr "cpu" "slm") 252 (and (eq_attr "type" "ishift") 253 (and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0")))) 254 "slm-simple-0") 255 256;; simple shift instruction use SHIFT eu, memory 257(define_insn_reservation "slm_ishift_mem" 1 258 (and (eq_attr "cpu" "slm") 259 (and (eq_attr "type" "ishift") 260 (and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0")))) 261 "slm-simple-0") 262 263;; DF shift (prefixed with 0f) is complex insn with latency of 4 cycles 264(define_insn_reservation "slm_ishift_3" 4 265 (and (eq_attr "cpu" "slm") 266 (and (eq_attr "type" "ishift") 267 (eq_attr "prefix_0f" "1"))) 268 "slm-complex, slm-all-eu*3") 269 270(define_insn_reservation "slm_ishift1" 1 271 (and (eq_attr "cpu" "slm") 272 (and (eq_attr "type" "ishift1") 273 (eq_attr "memory" "none"))) 274 "slm-simple-0") 275 276(define_insn_reservation "slm_ishift1_mem" 1 277 (and (eq_attr "cpu" "slm") 278 (and (eq_attr "type" "ishift1") 279 (eq_attr "memory" "!none"))) 280 "slm-simple-0") 281 282(define_insn_reservation "slm_rotate" 1 283 (and (eq_attr "cpu" "slm") 284 (and (eq_attr "type" "rotate") 285 (eq_attr "memory" "none"))) 286 "slm-simple-0") 287 288(define_insn_reservation "slm_rotate_mem" 1 289 (and (eq_attr "cpu" "slm") 290 (and (eq_attr "type" "rotate") 291 (eq_attr "memory" "!none"))) 292 "slm-simple-0") 293 294(define_insn_reservation "slm_rotate1" 1 295 (and (eq_attr "cpu" "slm") 296 (and (eq_attr "type" "rotate1") 297 (eq_attr "memory" "none"))) 298 "slm-simple-0") 299 300(define_insn_reservation "slm_rotate1_mem" 1 301 (and (eq_attr "cpu" "slm") 302 (and (eq_attr "type" "rotate1") 303 (eq_attr "memory" "!none"))) 304 "slm-simple-0") 305 306(define_insn_reservation "slm_imul" 3 307 (and (eq_attr "cpu" "slm") 308 (and (eq_attr "type" "imul") 309 (and (eq_attr "memory" "none") (eq_attr "mode" "SI")))) 310 "slm-imul-32") 311 312(define_insn_reservation "slm_imul_mem" 3 313 (and (eq_attr "cpu" "slm") 314 (and (eq_attr "type" "imul") 315 (and (eq_attr "memory" "!none") (eq_attr "mode" "SI")))) 316 "slm-imul-mem-32") 317 318;; latency set to 4 as common 64x64 imul with 1/2 tput 319(define_insn_reservation "slm_imul_3" 4 320 (and (eq_attr "cpu" "slm") 321 (and (eq_attr "type" "imul") 322 (eq_attr "mode" "!SI"))) 323 "slm-imul-64") 324 325(define_insn_reservation "slm_idiv" 33 326 (and (eq_attr "cpu" "slm") 327 (eq_attr "type" "idiv")) 328 "slm-complex, slm-all-eu*16, nothing*16") 329 330(define_insn_reservation "slm_icmp" 1 331 (and (eq_attr "cpu" "slm") 332 (and (eq_attr "type" "icmp") 333 (eq_attr "memory" "none"))) 334 "slm-simple-either") 335 336(define_insn_reservation "slm_icmp_mem" 1 337 (and (eq_attr "cpu" "slm") 338 (and (eq_attr "type" "icmp") 339 (eq_attr "memory" "!none"))) 340 "slm-simple-either") 341 342(define_insn_reservation "slm_test" 1 343 (and (eq_attr "cpu" "slm") 344 (and (eq_attr "type" "test") 345 (eq_attr "memory" "none"))) 346 "slm-simple-either") 347 348(define_insn_reservation "slm_test_mem" 1 349 (and (eq_attr "cpu" "slm") 350 (and (eq_attr "type" "test") 351 (eq_attr "memory" "!none"))) 352 "slm-simple-either") 353 354(define_insn_reservation "slm_ibr" 1 355 (and (eq_attr "cpu" "slm") 356 (and (eq_attr "type" "ibr") 357 (eq_attr "memory" "!load"))) 358 "slm-simple-1") 359 360;; complex if jump target is from address 361(define_insn_reservation "slm_ibr_2" 2 362 (and (eq_attr "cpu" "slm") 363 (and (eq_attr "type" "ibr") 364 (eq_attr "memory" "load"))) 365 "slm-complex, slm-all-eu") 366 367(define_insn_reservation "slm_setcc" 1 368 (and (eq_attr "cpu" "slm") 369 (and (eq_attr "type" "setcc") 370 (eq_attr "memory" "!store"))) 371 "slm-simple-either") 372 373;; 2 cycles complex if target is in memory 374(define_insn_reservation "slm_setcc_2" 2 375 (and (eq_attr "cpu" "slm") 376 (and (eq_attr "type" "setcc") 377 (eq_attr "memory" "store"))) 378 "slm-complex, slm-all-eu") 379 380(define_insn_reservation "slm_icmov" 2 381 (and (eq_attr "cpu" "slm") 382 (and (eq_attr "type" "icmov") 383 (eq_attr "memory" "none"))) 384 "slm-simple-either, nothing") 385 386(define_insn_reservation "slm_icmov_mem" 2 387 (and (eq_attr "cpu" "slm") 388 (and (eq_attr "type" "icmov") 389 (eq_attr "memory" "!none"))) 390 "slm-simple-0, nothing") 391 392;; UCODE if segreg, ignored 393(define_insn_reservation "slm_push" 2 394 (and (eq_attr "cpu" "slm") 395 (eq_attr "type" "push")) 396 "slm-dual-2c") 397 398;; pop r64 is 1 cycle. UCODE if segreg, ignored 399(define_insn_reservation "slm_pop" 1 400 (and (eq_attr "cpu" "slm") 401 (and (eq_attr "type" "pop") 402 (eq_attr "mode" "DI"))) 403 "slm-dual-1c") 404 405;; pop non-r64 is 2 cycles. UCODE if segreg, ignored 406(define_insn_reservation "slm_pop_2" 2 407 (and (eq_attr "cpu" "slm") 408 (and (eq_attr "type" "pop") 409 (eq_attr "mode" "!DI"))) 410 "slm-dual-2c") 411 412;; UCODE if segreg, ignored 413(define_insn_reservation "slm_call" 1 414 (and (eq_attr "cpu" "slm") 415 (eq_attr "type" "call")) 416 "slm-dual-1c") 417 418(define_insn_reservation "slm_callv" 1 419 (and (eq_attr "cpu" "slm") 420 (eq_attr "type" "callv")) 421 "slm-dual-1c") 422 423(define_insn_reservation "slm_leave" 3 424 (and (eq_attr "cpu" "slm") 425 (eq_attr "type" "leave")) 426 "slm-complex, slm-all-eu*2") 427 428(define_insn_reservation "slm_str" 3 429 (and (eq_attr "cpu" "slm") 430 (eq_attr "type" "str")) 431 "slm-complex, slm-all-eu*2") 432 433(define_insn_reservation "slm_sselog" 1 434 (and (eq_attr "cpu" "slm") 435 (and (eq_attr "type" "sselog") 436 (eq_attr "memory" "none"))) 437 "slm-simple-either") 438 439(define_insn_reservation "slm_sselog_mem" 1 440 (and (eq_attr "cpu" "slm") 441 (and (eq_attr "type" "sselog") 442 (eq_attr "memory" "!none"))) 443 "slm-simple-either") 444 445(define_insn_reservation "slm_sselog1" 1 446 (and (eq_attr "cpu" "slm") 447 (and (eq_attr "type" "sselog1") 448 (eq_attr "memory" "none"))) 449 "slm-simple-0") 450 451(define_insn_reservation "slm_sselog1_mem" 1 452 (and (eq_attr "cpu" "slm") 453 (and (eq_attr "type" "sselog1") 454 (eq_attr "memory" "!none"))) 455 "slm-simple-0") 456 457;; not pmad, not psad 458(define_insn_reservation "slm_sseiadd" 1 459 (and (eq_attr "cpu" "slm") 460 (and (eq_attr "type" "sseiadd") 461 (and (not (match_operand:V2DI 0 "register_operand")) 462 (and (eq_attr "atom_unit" "!simul") 463 (eq_attr "atom_unit" "!complex"))))) 464 "slm-simple-either") 465 466;; pmad, psad and 64 467(define_insn_reservation "slm_sseiadd_2" 4 468 (and (eq_attr "cpu" "slm") 469 (and (eq_attr "type" "sseiadd") 470 (and (not (match_operand:V2DI 0 "register_operand")) 471 (and (eq_attr "atom_unit" "simul" ) 472 (eq_attr "mode" "DI"))))) 473 "slm-fmul-4c") 474 475;; pmad, psad and 128 476(define_insn_reservation "slm_sseiadd_3" 5 477 (and (eq_attr "cpu" "slm") 478 (and (eq_attr "type" "sseiadd") 479 (and (not (match_operand:V2DI 0 "register_operand")) 480 (and (eq_attr "atom_unit" "simul" ) 481 (eq_attr "mode" "TI"))))) 482 "slm-fmul-5c") 483 484;; if paddq(64 bit op), phadd/phsub 485(define_insn_reservation "slm_sseiadd_4" 4 486 (and (eq_attr "cpu" "slm") 487 (and (eq_attr "type" "sseiadd") 488 (ior (match_operand:V2DI 0 "register_operand") 489 (eq_attr "atom_unit" "complex")))) 490 "slm-fadd-4c") 491 492;; if immediate op. 493(define_insn_reservation "slm_sseishft" 1 494 (and (eq_attr "cpu" "slm") 495 (and (eq_attr "type" "sseishft") 496 (and (eq_attr "atom_unit" "!sishuf") 497 (match_operand 2 "immediate_operand")))) 498 "slm-simple-either") 499 500;; if palignr or psrldq 501(define_insn_reservation "slm_sseishft_2" 1 502 (and (eq_attr "cpu" "slm") 503 (ior (eq_attr "type" "sseishft1") 504 (and (eq_attr "type" "sseishft") 505 (and (eq_attr "atom_unit" "sishuf") 506 (match_operand 2 "immediate_operand"))))) 507 "slm-simple-0") 508 509;; if reg/mem op 510(define_insn_reservation "slm_sseishft_3" 2 511 (and (eq_attr "cpu" "slm") 512 (and (eq_attr "type" "sseishft") 513 (not (match_operand 2 "immediate_operand")))) 514 "slm-complex, slm-all-eu") 515 516(define_insn_reservation "slm_sseimul" 5 517 (and (eq_attr "cpu" "slm") 518 (eq_attr "type" "sseimul")) 519 "slm-fmul-5c") 520 521;; rcpss or rsqrtss 522(define_insn_reservation "slm_sse" 4 523 (and (eq_attr "cpu" "slm") 524 (and (eq_attr "type" "sse") 525 (and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF")))) 526 "slm-fmul-4c") 527 528;; movshdup, movsldup. Suggest to type sseishft 529(define_insn_reservation "slm_sse_2" 1 530 (and (eq_attr "cpu" "slm") 531 (and (eq_attr "type" "sse") 532 (eq_attr "atom_sse_attr" "movdup"))) 533 "slm-simple-0") 534 535;; lfence 536(define_insn_reservation "slm_sse_3" 1 537 (and (eq_attr "cpu" "slm") 538 (and (eq_attr "type" "sse") 539 (eq_attr "atom_sse_attr" "lfence"))) 540 "slm-simple-either") 541 542;; sfence,clflush,mfence, prefetch 543(define_insn_reservation "slm_sse_4" 1 544 (and (eq_attr "cpu" "slm") 545 (and (eq_attr "type" "sse") 546 (ior (eq_attr "atom_sse_attr" "fence") 547 (eq_attr "atom_sse_attr" "prefetch")))) 548 "slm-simple-0") 549 550;; rcpps, rsqrtss, sqrt, ldmxcsr 551(define_insn_reservation "slm_sse_5" 9 552 (and (eq_attr "cpu" "slm") 553 (and (eq_attr "type" "sse") 554 (ior (ior (eq_attr "atom_sse_attr" "sqrt") 555 (eq_attr "atom_sse_attr" "mxcsr")) 556 (and (eq_attr "atom_sse_attr" "rcp") 557 (eq_attr "mode" "V4SF"))))) 558 "slm-complex, slm-all-eu*7, nothing") 559 560;; xmm->xmm 561(define_insn_reservation "slm_ssemov" 1 562 (and (eq_attr "cpu" "slm") 563 (and (eq_attr "type" "ssemov") 564 (and (match_operand 0 "register_operand" "xy") 565 (match_operand 1 "register_operand" "xy")))) 566 "slm-simple-either") 567 568;; reg->xmm 569(define_insn_reservation "slm_ssemov_2" 1 570 (and (eq_attr "cpu" "slm") 571 (and (eq_attr "type" "ssemov") 572 (and (match_operand 0 "register_operand" "xy") 573 (match_operand 1 "register_operand" "r")))) 574 "slm-simple-0") 575 576;; xmm->reg 577(define_insn_reservation "slm_ssemov_3" 3 578 (and (eq_attr "cpu" "slm") 579 (and (eq_attr "type" "ssemov") 580 (and (match_operand 0 "register_operand" "r") 581 (match_operand 1 "register_operand" "xy")))) 582 "slm-simple-0, nothing*2") 583 584;; mov mem 585(define_insn_reservation "slm_ssemov_4" 1 586 (and (eq_attr "cpu" "slm") 587 (and (eq_attr "type" "ssemov") 588 (and (eq_attr "movu" "0") (eq_attr "memory" "!none")))) 589 "slm-simple-0") 590 591;; movu mem 592(define_insn_reservation "slm_ssemov_5" 2 593 (and (eq_attr "cpu" "slm") 594 (and (eq_attr "type" "ssemov") 595 (ior (eq_attr "movu" "1") (eq_attr "memory" "!none")))) 596 "slm-simple-0, nothing") 597 598;; no memory simple 599(define_insn_reservation "slm_sseadd" 3 600 (and (eq_attr "cpu" "slm") 601 (and (eq_attr "type" "sseadd") 602 (and (eq_attr "memory" "none") 603 (and (eq_attr "mode" "!V2DF") 604 (eq_attr "atom_unit" "!complex"))))) 605 "slm-fadd-3c") 606 607;; memory simple 608(define_insn_reservation "slm_sseadd_mem" 3 609 (and (eq_attr "cpu" "slm") 610 (and (eq_attr "type" "sseadd") 611 (and (eq_attr "memory" "!none") 612 (and (eq_attr "mode" "!V2DF") 613 (eq_attr "atom_unit" "!complex"))))) 614 "slm-fadd-3c") 615 616;; maxps, minps, *pd, hadd, hsub 617(define_insn_reservation "slm_sseadd_3" 4 618 (and (eq_attr "cpu" "slm") 619 (and (eq_attr "type" "sseadd") 620 (ior (eq_attr "mode" "V2DF") (eq_attr "atom_unit" "complex")))) 621 "slm-fadd-4c") 622 623;; Except dppd/dpps 624(define_insn_reservation "slm_ssemul" 5 625 (and (eq_attr "cpu" "slm") 626 (and (eq_attr "type" "ssemul") 627 (eq_attr "mode" "!SF"))) 628 "slm-fmul-5c") 629 630;; Except dppd/dpps, 4 cycle if mulss 631(define_insn_reservation "slm_ssemul_2" 4 632 (and (eq_attr "cpu" "slm") 633 (and (eq_attr "type" "ssemul") 634 (eq_attr "mode" "SF"))) 635 "slm-fmul-4c") 636 637(define_insn_reservation "slm_ssecmp" 1 638 (and (eq_attr "cpu" "slm") 639 (eq_attr "type" "ssecmp")) 640 "slm-simple-either") 641 642(define_insn_reservation "slm_ssecomi" 1 643 (and (eq_attr "cpu" "slm") 644 (eq_attr "type" "ssecomi")) 645 "slm-simple-0") 646 647;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi 648(define_insn_reservation "slm_ssecvt" 5 649 (and (eq_attr "cpu" "slm") 650 (and (eq_attr "type" "ssecvt") 651 (ior (and (match_operand:V2SI 0 "register_operand") 652 (match_operand:V4SF 1 "register_operand")) 653 (and (match_operand:V4SF 0 "register_operand") 654 (match_operand:V2SI 1 "register_operand"))))) 655 "slm-fp-0, slm-feu-0, nothing*3") 656 657;; memory and cvtpi2ps, cvtps2pi, cvttps2pi 658(define_insn_reservation "slm_ssecvt_mem" 5 659 (and (eq_attr "cpu" "slm") 660 (and (eq_attr "type" "ssecvt") 661 (ior (and (match_operand:V2SI 0 "register_operand") 662 (match_operand:V4SF 1 "memory_operand")) 663 (and (match_operand:V4SF 0 "register_operand") 664 (match_operand:V2SI 1 "memory_operand"))))) 665"slm-fp-0, slm-feu-0, nothing*3") 666 667;; cvtpd2pi, cvtpi2pd 668(define_insn_reservation "slm_ssecvt_1" 2 669 (and (eq_attr "cpu" "slm") 670 (and (eq_attr "type" "ssecvt") 671 (ior (and (match_operand:V2DF 0 "register_operand") 672 (match_operand:V2SI 1 "register_operand")) 673 (and (match_operand:V2SI 0 "register_operand") 674 (match_operand:V2DF 1 "register_operand"))))) 675 "slm-fp-0, slm-feu-0") 676 677;; memory and cvtpd2pi, cvtpi2pd 678(define_insn_reservation "slm_ssecvt_1_mem" 2 679 (and (eq_attr "cpu" "slm") 680 (and (eq_attr "type" "ssecvt") 681 (ior (and (match_operand:V2DF 0 "register_operand") 682 (match_operand:V2SI 1 "memory_operand")) 683 (and (match_operand:V2SI 0 "register_operand") 684 (match_operand:V2DF 1 "memory_operand"))))) 685 "slm-fp-0, slm-feu-0") 686 687;; otherwise. 4 cycles average for cvtss2sd 688(define_insn_reservation "slm_ssecvt_3" 4 689 (and (eq_attr "cpu" "slm") 690 (and (eq_attr "type" "ssecvt") 691 (not (ior (and (match_operand:V2SI 0 "register_operand") 692 (match_operand:V4SF 1 "nonimmediate_operand")) 693 (and (match_operand:V4SF 0 "register_operand") 694 (match_operand:V2SI 1 "nonimmediate_operand")))))) 695 "slm-fp-0, nothing*3") 696 697;; memory and cvtsi2sd 698(define_insn_reservation "slm_sseicvt" 1 699 (and (eq_attr "cpu" "slm") 700 (and (eq_attr "type" "sseicvt") 701 (and (match_operand:V2DF 0 "register_operand") 702 (match_operand:SI 1 "nonimmediate_operand")))) 703 "slm-fp-0") 704 705;; otherwise. 8 cycles average for cvtsd2si 706(define_insn_reservation "slm_sseicvt_2" 4 707 (and (eq_attr "cpu" "slm") 708 (and (eq_attr "type" "sseicvt") 709 (not (and (match_operand:V2DF 0 "register_operand") 710 (match_operand:SI 1 "memory_operand"))))) 711 "slm-fp-0, nothing*3") 712 713(define_insn_reservation "slm_ssediv" 13 714 (and (eq_attr "cpu" "slm") 715 (eq_attr "type" "ssediv")) 716 "slm-fp-0, slm-feu-0*10, nothing*2") 717 718;; simple for fmov 719(define_insn_reservation "slm_fmov" 1 720 (and (eq_attr "cpu" "slm") 721 (and (eq_attr "type" "fmov") 722 (eq_attr "memory" "none"))) 723 "slm-simple-either") 724 725;; simple for fmov 726(define_insn_reservation "slm_fmov_mem" 1 727 (and (eq_attr "cpu" "slm") 728 (and (eq_attr "type" "fmov") 729 (eq_attr "memory" "!none"))) 730 "slm-simple-either") 731 732;; Define bypass here 733 734;; There will be 0 cycle stall from cmp/test to jcc 735 736;; There will be 1 cycle stall from flag producer to cmov and adc/sbb 737(define_bypass 2 "slm_icmp, slm_test, slm_alu, slm_alu_carry, 738 slm_alu1, slm_negnot, slm_incdec, slm_ishift, 739 slm_ishift1, slm_rotate, slm_rotate1" 740 "slm_icmov, slm_alu_carry") 741 742;; lea to shift source stall is 1 cycle 743(define_bypass 2 "slm_lea" 744 "slm_ishift, slm_ishift1, slm_rotate, slm_rotate1" 745 "!ix86_dep_by_shift_count") 746 747;; non-lea to shift count stall is 1 cycle 748(define_bypass 2 "slm_alu_carry, 749 slm_alu,slm_alu1,slm_negnot,slm_imov,slm_imovx, 750 slm_incdec,slm_ishift,slm_ishift1,slm_rotate, 751 slm_rotate1, slm_setcc, slm_icmov, slm_pop, 752 slm_alu_mem, slm_alu_carry_mem, slm_alu1_mem, 753 slm_imovx_mem, slm_imovx_2_mem, 754 slm_imov_mem, slm_icmov_mem, slm_fmov_mem" 755 "slm_ishift, slm_ishift1, slm_rotate, slm_rotate1, 756 slm_ishift_mem, slm_ishift1_mem, 757 slm_rotate_mem, slm_rotate1_mem" 758 "ix86_dep_by_shift_count") 759