1 /* Code for RTL transformations to satisfy insn constraints.
2    Copyright (C) 2010-2018 Free Software Foundation, Inc.
3    Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 
5    This file is part of GCC.
6 
7    GCC is free software; you can redistribute it and/or modify it under
8    the terms of the GNU General Public License as published by the Free
9    Software Foundation; either version 3, or (at your option) any later
10    version.
11 
12    GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13    WARRANTY; without even the implied warranty of MERCHANTABILITY or
14    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15    for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with GCC; see the file COPYING3.  If not see
19    <http://www.gnu.org/licenses/>.  */
20 
21 
22 /* This file contains code for 3 passes: constraint pass,
23    inheritance/split pass, and pass for undoing failed inheritance and
24    split.
25 
26    The major goal of constraint pass is to transform RTL to satisfy
27    insn and address constraints by:
28      o choosing insn alternatives;
29      o generating *reload insns* (or reloads in brief) and *reload
30        pseudos* which will get necessary hard registers later;
31      o substituting pseudos with equivalent values and removing the
32        instructions that initialized those pseudos.
33 
34    The constraint pass has biggest and most complicated code in LRA.
35    There are a lot of important details like:
36      o reuse of input reload pseudos to simplify reload pseudo
37        allocations;
38      o some heuristics to choose insn alternative to improve the
39        inheritance;
40      o early clobbers etc.
41 
42    The pass is mimicking former reload pass in alternative choosing
43    because the reload pass is oriented to current machine description
44    model.  It might be changed if the machine description model is
45    changed.
46 
47    There is special code for preventing all LRA and this pass cycling
48    in case of bugs.
49 
50    On the first iteration of the pass we process every instruction and
51    choose an alternative for each one.  On subsequent iterations we try
52    to avoid reprocessing instructions if we can be sure that the old
53    choice is still valid.
54 
55    The inheritance/spilt pass is to transform code to achieve
56    ineheritance and live range splitting.  It is done on backward
57    traversal of EBBs.
58 
59    The inheritance optimization goal is to reuse values in hard
60    registers. There is analogous optimization in old reload pass.  The
61    inheritance is achieved by following transformation:
62 
63        reload_p1 <- p	     reload_p1 <- p
64        ...		     new_p <- reload_p1
65        ...		=>   ...
66        reload_p2 <- p	     reload_p2 <- new_p
67 
68    where p is spilled and not changed between the insns.  Reload_p1 is
69    also called *original pseudo* and new_p is called *inheritance
70    pseudo*.
71 
72    The subsequent assignment pass will try to assign the same (or
73    another if it is not possible) hard register to new_p as to
74    reload_p1 or reload_p2.
75 
76    If the assignment pass fails to assign a hard register to new_p,
77    this file will undo the inheritance and restore the original code.
78    This is because implementing the above sequence with a spilled
79    new_p would make the code much worse.  The inheritance is done in
80    EBB scope.  The above is just a simplified example to get an idea
81    of the inheritance as the inheritance is also done for non-reload
82    insns.
83 
84    Splitting (transformation) is also done in EBB scope on the same
85    pass as the inheritance:
86 
87        r <- ... or ... <- r		 r <- ... or ... <- r
88        ...				 s <- r (new insn -- save)
89        ...			  =>
90        ...				 r <- s (new insn -- restore)
91        ... <- r				 ... <- r
92 
93     The *split pseudo* s is assigned to the hard register of the
94     original pseudo or hard register r.
95 
96     Splitting is done:
97       o In EBBs with high register pressure for global pseudos (living
98 	in at least 2 BBs) and assigned to hard registers when there
99 	are more one reloads needing the hard registers;
100       o for pseudos needing save/restore code around calls.
101 
102     If the split pseudo still has the same hard register as the
103     original pseudo after the subsequent assignment pass or the
104     original pseudo was split, the opposite transformation is done on
105     the same pass for undoing inheritance.  */
106 
107 #undef REG_OK_STRICT
108 
109 #include "config.h"
110 #include "system.h"
111 #include "coretypes.h"
112 #include "backend.h"
113 #include "target.h"
114 #include "rtl.h"
115 #include "tree.h"
116 #include "predict.h"
117 #include "df.h"
118 #include "memmodel.h"
119 #include "tm_p.h"
120 #include "expmed.h"
121 #include "optabs.h"
122 #include "regs.h"
123 #include "ira.h"
124 #include "recog.h"
125 #include "output.h"
126 #include "addresses.h"
127 #include "expr.h"
128 #include "cfgrtl.h"
129 #include "rtl-error.h"
130 #include "params.h"
131 #include "lra.h"
132 #include "lra-int.h"
133 #include "print-rtl.h"
134 
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136    insn.  Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137    reload insns.  */
138 static int bb_reload_num;
139 
140 /* The current insn being processed and corresponding its single set
141    (NULL otherwise), its data (basic block, the insn data, the insn
142    static data, and the mode of each operand).  */
143 static rtx_insn *curr_insn;
144 static rtx curr_insn_set;
145 static basic_block curr_bb;
146 static lra_insn_recog_data_t curr_id;
147 static struct lra_static_insn_data *curr_static_id;
148 static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150    (e.g. constant) and whose subreg is given operand of the current
151    insn.  VOIDmode in all other cases.  */
152 static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS];
153 
154 
155 
156 /* Start numbers for new registers and insns at the current constraints
157    pass start.	*/
158 static int new_regno_start;
159 static int new_insn_uid_start;
160 
161 /* If LOC is nonnull, strip any outer subreg from it.  */
162 static inline rtx *
163 strip_subreg (rtx *loc)
164 {
165   return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
166 }
167 
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169    register, use a hard register from its allocno class.  */
170 static int
171 get_try_hard_regno (int regno)
172 {
173   int hard_regno;
174   enum reg_class rclass;
175 
176   if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
177     hard_regno = lra_get_regno_hard_regno (regno);
178   if (hard_regno >= 0)
179     return hard_regno;
180   rclass = lra_get_allocno_class (regno);
181   if (rclass == NO_REGS)
182     return -1;
183   return ira_class_hard_regs[rclass][0];
184 }
185 
186 /* Return the hard regno of X after removing its subreg.  If X is not
187    a register or a subreg of a register, return -1.  If X is a pseudo,
188    use its assignment.  If FINAL_P return the final hard regno which will
189    be after elimination.  */
190 static int
191 get_hard_regno (rtx x, bool final_p)
192 {
193   rtx reg;
194   int hard_regno;
195 
196   reg = x;
197   if (SUBREG_P (x))
198     reg = SUBREG_REG (x);
199   if (! REG_P (reg))
200     return -1;
201   if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg)))
202     hard_regno = lra_get_regno_hard_regno (hard_regno);
203   if (hard_regno < 0)
204     return -1;
205   if (final_p)
206     hard_regno = lra_get_elimination_hard_regno (hard_regno);
207   if (SUBREG_P (x))
208     hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg),
209 				       SUBREG_BYTE (x),  GET_MODE (x));
210   return hard_regno;
211 }
212 
213 /* If REGNO is a hard register or has been allocated a hard register,
214    return the class of that register.  If REGNO is a reload pseudo
215    created by the current constraints pass, return its allocno class.
216    Return NO_REGS otherwise.  */
217 static enum reg_class
218 get_reg_class (int regno)
219 {
220   int hard_regno;
221 
222   if (! HARD_REGISTER_NUM_P (hard_regno = regno))
223     hard_regno = lra_get_regno_hard_regno (regno);
224   if (hard_regno >= 0)
225     {
226       hard_regno = lra_get_elimination_hard_regno (hard_regno);
227       return REGNO_REG_CLASS (hard_regno);
228     }
229   if (regno >= new_regno_start)
230     return lra_get_allocno_class (regno);
231   return NO_REGS;
232 }
233 
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235    CL.  Use elimination first if REG is a hard register.  If REG is a
236    reload pseudo created by this constraints pass, assume that it will
237    be allocated a hard register from its allocno class, but allow that
238    class to be narrowed to CL if it is currently a superset of CL.
239 
240    If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241    REGNO (reg), or NO_REGS if no change in its class was needed.  */
242 static bool
243 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
244 {
245   enum reg_class rclass, common_class;
246   machine_mode reg_mode;
247   int class_size, hard_regno, nregs, i, j;
248   int regno = REGNO (reg);
249 
250   if (new_class != NULL)
251     *new_class = NO_REGS;
252   if (regno < FIRST_PSEUDO_REGISTER)
253     {
254       rtx final_reg = reg;
255       rtx *final_loc = &final_reg;
256 
257       lra_eliminate_reg_if_possible (final_loc);
258       return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc));
259     }
260   reg_mode = GET_MODE (reg);
261   rclass = get_reg_class (regno);
262   if (regno < new_regno_start
263       /* Do not allow the constraints for reload instructions to
264 	 influence the classes of new pseudos.  These reloads are
265 	 typically moves that have many alternatives, and restricting
266 	 reload pseudos for one alternative may lead to situations
267 	 where other reload pseudos are no longer allocatable.  */
268       || (INSN_UID (curr_insn) >= new_insn_uid_start
269 	  && curr_insn_set != NULL
270 	  && ((OBJECT_P (SET_SRC (curr_insn_set))
271 	       && ! CONSTANT_P (SET_SRC (curr_insn_set)))
272 	      || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
273 		  && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
274 		  && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
275     /* When we don't know what class will be used finally for reload
276        pseudos, we use ALL_REGS.  */
277     return ((regno >= new_regno_start && rclass == ALL_REGS)
278 	    || (rclass != NO_REGS && ira_class_subset_p[rclass][cl]
279 		&& ! hard_reg_set_subset_p (reg_class_contents[cl],
280 					    lra_no_alloc_regs)));
281   else
282     {
283       common_class = ira_reg_class_subset[rclass][cl];
284       if (new_class != NULL)
285 	*new_class = common_class;
286       if (hard_reg_set_subset_p (reg_class_contents[common_class],
287 				 lra_no_alloc_regs))
288 	return false;
289       /* Check that there are enough allocatable regs.  */
290       class_size = ira_class_hard_regs_num[common_class];
291       for (i = 0; i < class_size; i++)
292 	{
293 	  hard_regno = ira_class_hard_regs[common_class][i];
294 	  nregs = hard_regno_nregs (hard_regno, reg_mode);
295 	  if (nregs == 1)
296 	    return true;
297 	  for (j = 0; j < nregs; j++)
298 	    if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
299 		|| ! TEST_HARD_REG_BIT (reg_class_contents[common_class],
300 					hard_regno + j))
301 	      break;
302 	  if (j >= nregs)
303 	    return true;
304 	}
305       return false;
306     }
307 }
308 
309 /* Return true if REGNO satisfies a memory constraint.	*/
310 static bool
311 in_mem_p (int regno)
312 {
313   return get_reg_class (regno) == NO_REGS;
314 }
315 
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317    space AS, and check that each pseudo has the proper kind of hard
318    reg.	 */
319 static int
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED,
321 		 rtx addr, addr_space_t as)
322 {
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324   lra_assert (ADDR_SPACE_GENERIC_P (as));
325   GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
326   return 0;
327 
328  win:
329   return 1;
330 #else
331   return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
332 #endif
333 }
334 
335 namespace {
336   /* Temporarily eliminates registers in an address (for the lifetime of
337      the object).  */
338   class address_eliminator {
339   public:
340     address_eliminator (struct address_info *ad);
341     ~address_eliminator ();
342 
343   private:
344     struct address_info *m_ad;
345     rtx *m_base_loc;
346     rtx m_base_reg;
347     rtx *m_index_loc;
348     rtx m_index_reg;
349   };
350 }
351 
352 address_eliminator::address_eliminator (struct address_info *ad)
353   : m_ad (ad),
354     m_base_loc (strip_subreg (ad->base_term)),
355     m_base_reg (NULL_RTX),
356     m_index_loc (strip_subreg (ad->index_term)),
357     m_index_reg (NULL_RTX)
358 {
359   if (m_base_loc != NULL)
360     {
361       m_base_reg = *m_base_loc;
362       lra_eliminate_reg_if_possible (m_base_loc);
363       if (m_ad->base_term2 != NULL)
364 	*m_ad->base_term2 = *m_ad->base_term;
365     }
366   if (m_index_loc != NULL)
367     {
368       m_index_reg = *m_index_loc;
369       lra_eliminate_reg_if_possible (m_index_loc);
370     }
371 }
372 
373 address_eliminator::~address_eliminator ()
374 {
375   if (m_base_loc && *m_base_loc != m_base_reg)
376     {
377       *m_base_loc = m_base_reg;
378       if (m_ad->base_term2 != NULL)
379 	*m_ad->base_term2 = *m_ad->base_term;
380     }
381   if (m_index_loc && *m_index_loc != m_index_reg)
382     *m_index_loc = m_index_reg;
383 }
384 
385 /* Return true if the eliminated form of AD is a legitimate target address.  */
386 static bool
387 valid_address_p (struct address_info *ad)
388 {
389   address_eliminator eliminator (ad);
390   return valid_address_p (ad->mode, *ad->outer, ad->as);
391 }
392 
393 /* Return true if the eliminated form of memory reference OP satisfies
394    extra (special) memory constraint CONSTRAINT.  */
395 static bool
396 satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
397 {
398   struct address_info ad;
399 
400   decompose_mem_address (&ad, op);
401   address_eliminator eliminator (&ad);
402   return constraint_satisfied_p (op, constraint);
403 }
404 
405 /* Return true if the eliminated form of address AD satisfies extra
406    address constraint CONSTRAINT.  */
407 static bool
408 satisfies_address_constraint_p (struct address_info *ad,
409 				enum constraint_num constraint)
410 {
411   address_eliminator eliminator (ad);
412   return constraint_satisfied_p (*ad->outer, constraint);
413 }
414 
415 /* Return true if the eliminated form of address OP satisfies extra
416    address constraint CONSTRAINT.  */
417 static bool
418 satisfies_address_constraint_p (rtx op, enum constraint_num constraint)
419 {
420   struct address_info ad;
421 
422   decompose_lea_address (&ad, &op);
423   return satisfies_address_constraint_p (&ad, constraint);
424 }
425 
426 /* Initiate equivalences for LRA.  As we keep original equivalences
427    before any elimination, we need to make copies otherwise any change
428    in insns might change the equivalences.  */
429 void
430 lra_init_equiv (void)
431 {
432   ira_expand_reg_equiv ();
433   for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
434     {
435       rtx res;
436 
437       if ((res = ira_reg_equiv[i].memory) != NULL_RTX)
438 	ira_reg_equiv[i].memory = copy_rtx (res);
439       if ((res = ira_reg_equiv[i].invariant) != NULL_RTX)
440 	ira_reg_equiv[i].invariant = copy_rtx (res);
441     }
442 }
443 
444 static rtx loc_equivalence_callback (rtx, const_rtx, void *);
445 
446 /* Update equivalence for REGNO.  We need to this as the equivalence
447    might contain other pseudos which are changed by their
448    equivalences.  */
449 static void
450 update_equiv (int regno)
451 {
452   rtx x;
453 
454   if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
455     ira_reg_equiv[regno].memory
456       = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
457 				 NULL_RTX);
458   if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX)
459     ira_reg_equiv[regno].invariant
460       = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
461 				 NULL_RTX);
462 }
463 
464 /* If we have decided to substitute X with another value, return that
465    value, otherwise return X.  */
466 static rtx
467 get_equiv (rtx x)
468 {
469   int regno;
470   rtx res;
471 
472   if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
473       || ! ira_reg_equiv[regno].defined_p
474       || ! ira_reg_equiv[regno].profitable_p
475       || lra_get_regno_hard_regno (regno) >= 0)
476     return x;
477   if ((res = ira_reg_equiv[regno].memory) != NULL_RTX)
478     {
479       if (targetm.cannot_substitute_mem_equiv_p (res))
480 	return x;
481       return res;
482     }
483   if ((res = ira_reg_equiv[regno].constant) != NULL_RTX)
484     return res;
485   if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX)
486     return res;
487   gcc_unreachable ();
488 }
489 
490 /* If we have decided to substitute X with the equivalent value,
491    return that value after elimination for INSN, otherwise return
492    X.  */
493 static rtx
494 get_equiv_with_elimination (rtx x, rtx_insn *insn)
495 {
496   rtx res = get_equiv (x);
497 
498   if (x == res || CONSTANT_P (res))
499     return res;
500   return lra_eliminate_regs_1 (insn, res, GET_MODE (res),
501 			       false, false, 0, true);
502 }
503 
504 /* Set up curr_operand_mode.  */
505 static void
506 init_curr_operand_mode (void)
507 {
508   int nop = curr_static_id->n_operands;
509   for (int i = 0; i < nop; i++)
510     {
511       machine_mode mode = GET_MODE (*curr_id->operand_loc[i]);
512       if (mode == VOIDmode)
513 	{
514 	  /* The .md mode for address operands is the mode of the
515 	     addressed value rather than the mode of the address itself.  */
516 	  if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
517 	    mode = Pmode;
518 	  else
519 	    mode = curr_static_id->operand[i].mode;
520 	}
521       curr_operand_mode[i] = mode;
522     }
523 }
524 
525 
526 
527 /* The page contains code to reuse input reloads.  */
528 
529 /* Structure describes input reload of the current insns.  */
530 struct input_reload
531 {
532   /* True for input reload of matched operands.  */
533   bool match_p;
534   /* Reloaded value.  */
535   rtx input;
536   /* Reload pseudo used.  */
537   rtx reg;
538 };
539 
540 /* The number of elements in the following array.  */
541 static int curr_insn_input_reloads_num;
542 /* Array containing info about input reloads.  It is used to find the
543    same input reload and reuse the reload pseudo in this case.	*/
544 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS];
545 
546 /* Initiate data concerning reuse of input reloads for the current
547    insn.  */
548 static void
549 init_curr_insn_input_reloads (void)
550 {
551   curr_insn_input_reloads_num = 0;
552 }
553 
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555    created input reload pseudo (only if TYPE is not OP_OUT).  Don't
556    reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557    wrapped up in SUBREG.  The result pseudo is returned through
558    RESULT_REG.  Return TRUE if we created a new pseudo, FALSE if we
559    reused the already created input reload pseudo.  Use TITLE to
560    describe new registers for debug purposes.  */
561 static bool
562 get_reload_reg (enum op_type type, machine_mode mode, rtx original,
563 		enum reg_class rclass, bool in_subreg_p,
564 		const char *title, rtx *result_reg)
565 {
566   int i, regno;
567   enum reg_class new_class;
568   bool unique_p = false;
569 
570   if (type == OP_OUT)
571     {
572       *result_reg
573 	= lra_create_new_reg_with_unique_value (mode, original, rclass, title);
574       return true;
575     }
576   /* Prevent reuse value of expression with side effects,
577      e.g. volatile memory.  */
578   if (! side_effects_p (original))
579     for (i = 0; i < curr_insn_input_reloads_num; i++)
580       {
581 	if (! curr_insn_input_reloads[i].match_p
582 	    && rtx_equal_p (curr_insn_input_reloads[i].input, original)
583 	    && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
584 	  {
585 	    rtx reg = curr_insn_input_reloads[i].reg;
586 	    regno = REGNO (reg);
587 	    /* If input is equal to original and both are VOIDmode,
588 	       GET_MODE (reg) might be still different from mode.
589 	       Ensure we don't return *result_reg with wrong mode.  */
590 	    if (GET_MODE (reg) != mode)
591 	      {
592 		if (in_subreg_p)
593 		  continue;
594 		if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)),
595 			      GET_MODE_SIZE (mode)))
596 		  continue;
597 		reg = lowpart_subreg (mode, reg, GET_MODE (reg));
598 		if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
599 		  continue;
600 	      }
601 	    *result_reg = reg;
602 	    if (lra_dump_file != NULL)
603 	      {
604 		fprintf (lra_dump_file, "	 Reuse r%d for reload ", regno);
605 		dump_value_slim (lra_dump_file, original, 1);
606 	      }
607 	    if (new_class != lra_get_allocno_class (regno))
608 	      lra_change_class (regno, new_class, ", change to", false);
609 	    if (lra_dump_file != NULL)
610 	      fprintf (lra_dump_file, "\n");
611 	    return false;
612 	  }
613 	/* If we have an input reload with a different mode, make sure it
614 	   will get a different hard reg.  */
615 	else if (REG_P (original)
616 		 && REG_P (curr_insn_input_reloads[i].input)
617 		 && REGNO (original) == REGNO (curr_insn_input_reloads[i].input)
618 		 && (GET_MODE (original)
619 		     != GET_MODE (curr_insn_input_reloads[i].input)))
620 	  unique_p = true;
621       }
622   *result_reg = (unique_p
623 		 ? lra_create_new_reg_with_unique_value
624 		 : lra_create_new_reg) (mode, original, rclass, title);
625   lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
626   curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
627   curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false;
628   curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
629   return true;
630 }
631 
632 
633 
634 /* The page contains code to extract memory address parts.  */
635 
636 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos.  */
637 static inline bool
638 ok_for_index_p_nonstrict (rtx reg)
639 {
640   unsigned regno = REGNO (reg);
641 
642   return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
643 }
644 
645 /* A version of regno_ok_for_base_p for use here, when all pseudos
646    should count as OK.	Arguments as for regno_ok_for_base_p.  */
647 static inline bool
648 ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as,
649 			 enum rtx_code outer_code, enum rtx_code index_code)
650 {
651   unsigned regno = REGNO (reg);
652 
653   if (regno >= FIRST_PSEUDO_REGISTER)
654     return true;
655   return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
656 }
657 
658 
659 
660 /* The page contains major code to choose the current insn alternative
661    and generate reloads for it.	 */
662 
663 /* Return the offset from REGNO of the least significant register
664    in (reg:MODE REGNO).
665 
666    This function is used to tell whether two registers satisfy
667    a matching constraint.  (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
668 
669          REGNO1 + lra_constraint_offset (REGNO1, MODE1)
670 	 == REGNO2 + lra_constraint_offset (REGNO2, MODE2)  */
671 int
672 lra_constraint_offset (int regno, machine_mode mode)
673 {
674   lra_assert (regno < FIRST_PSEUDO_REGISTER);
675 
676   scalar_int_mode int_mode;
677   if (WORDS_BIG_ENDIAN
678       && is_a <scalar_int_mode> (mode, &int_mode)
679       && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD)
680     return hard_regno_nregs (regno, mode) - 1;
681   return 0;
682 }
683 
684 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
685    if they are the same hard reg, and has special hacks for
686    auto-increment and auto-decrement.  This is specifically intended for
687    process_alt_operands to use in determining whether two operands
688    match.  X is the operand whose number is the lower of the two.
689 
690    It is supposed that X is the output operand and Y is the input
691    operand.  Y_HARD_REGNO is the final hard regno of register Y or
692    register in subreg Y as we know it now.  Otherwise, it is a
693    negative value.  */
694 static bool
695 operands_match_p (rtx x, rtx y, int y_hard_regno)
696 {
697   int i;
698   RTX_CODE code = GET_CODE (x);
699   const char *fmt;
700 
701   if (x == y)
702     return true;
703   if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
704       && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
705     {
706       int j;
707 
708       i = get_hard_regno (x, false);
709       if (i < 0)
710 	goto slow;
711 
712       if ((j = y_hard_regno) < 0)
713 	goto slow;
714 
715       i += lra_constraint_offset (i, GET_MODE (x));
716       j += lra_constraint_offset (j, GET_MODE (y));
717 
718       return i == j;
719     }
720 
721   /* If two operands must match, because they are really a single
722      operand of an assembler insn, then two post-increments are invalid
723      because the assembler insn would increment only once.  On the
724      other hand, a post-increment matches ordinary indexing if the
725      post-increment is the output operand.  */
726   if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
727     return operands_match_p (XEXP (x, 0), y, y_hard_regno);
728 
729   /* Two pre-increments are invalid because the assembler insn would
730      increment only once.  On the other hand, a pre-increment matches
731      ordinary indexing if the pre-increment is the input operand.  */
732   if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
733       || GET_CODE (y) == PRE_MODIFY)
734     return operands_match_p (x, XEXP (y, 0), -1);
735 
736  slow:
737 
738   if (code == REG && REG_P (y))
739     return REGNO (x) == REGNO (y);
740 
741   if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
742       && x == SUBREG_REG (y))
743     return true;
744   if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
745       && SUBREG_REG (x) == y)
746     return true;
747 
748   /* Now we have disposed of all the cases in which different rtx
749      codes can match.  */
750   if (code != GET_CODE (y))
751     return false;
752 
753   /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.  */
754   if (GET_MODE (x) != GET_MODE (y))
755     return false;
756 
757   switch (code)
758     {
759     CASE_CONST_UNIQUE:
760       return false;
761 
762     case LABEL_REF:
763       return label_ref_label (x) == label_ref_label (y);
764     case SYMBOL_REF:
765       return XSTR (x, 0) == XSTR (y, 0);
766 
767     default:
768       break;
769     }
770 
771   /* Compare the elements.  If any pair of corresponding elements fail
772      to match, return false for the whole things.  */
773 
774   fmt = GET_RTX_FORMAT (code);
775   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
776     {
777       int val, j;
778       switch (fmt[i])
779 	{
780 	case 'w':
781 	  if (XWINT (x, i) != XWINT (y, i))
782 	    return false;
783 	  break;
784 
785 	case 'i':
786 	  if (XINT (x, i) != XINT (y, i))
787 	    return false;
788 	  break;
789 
790 	case 'p':
791 	  if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y)))
792 	    return false;
793 	  break;
794 
795 	case 'e':
796 	  val = operands_match_p (XEXP (x, i), XEXP (y, i), -1);
797 	  if (val == 0)
798 	    return false;
799 	  break;
800 
801 	case '0':
802 	  break;
803 
804 	case 'E':
805 	  if (XVECLEN (x, i) != XVECLEN (y, i))
806 	    return false;
807 	  for (j = XVECLEN (x, i) - 1; j >= 0; --j)
808 	    {
809 	      val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1);
810 	      if (val == 0)
811 		return false;
812 	    }
813 	  break;
814 
815 	  /* It is believed that rtx's at this level will never
816 	     contain anything but integers and other rtx's, except for
817 	     within LABEL_REFs and SYMBOL_REFs.	 */
818 	default:
819 	  gcc_unreachable ();
820 	}
821     }
822   return true;
823 }
824 
825 /* True if X is a constant that can be forced into the constant pool.
826    MODE is the mode of the operand, or VOIDmode if not known.  */
827 #define CONST_POOL_OK_P(MODE, X)		\
828   ((MODE) != VOIDmode				\
829    && CONSTANT_P (X)				\
830    && GET_CODE (X) != HIGH			\
831    && GET_MODE_SIZE (MODE).is_constant ()	\
832    && !targetm.cannot_force_const_mem (MODE, X))
833 
834 /* True if C is a non-empty register class that has too few registers
835    to be safely used as a reload target class.	*/
836 #define SMALL_REGISTER_CLASS_P(C)		\
837   (ira_class_hard_regs_num [(C)] == 1		\
838    || (ira_class_hard_regs_num [(C)] >= 1	\
839        && targetm.class_likely_spilled_p (C)))
840 
841 /* If REG is a reload pseudo, try to make its class satisfying CL.  */
842 static void
843 narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
844 {
845   enum reg_class rclass;
846 
847   /* Do not make more accurate class from reloads generated.  They are
848      mostly moves with a lot of constraints.  Making more accurate
849      class may results in very narrow class and impossibility of find
850      registers for several reloads of one insn.	 */
851   if (INSN_UID (curr_insn) >= new_insn_uid_start)
852     return;
853   if (GET_CODE (reg) == SUBREG)
854     reg = SUBREG_REG (reg);
855   if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
856     return;
857   if (in_class_p (reg, cl, &rclass) && rclass != cl)
858     lra_change_class (REGNO (reg), rclass, "      Change to", true);
859 }
860 
861 /* Searches X for any reference to a reg with the same value as REGNO,
862    returning the rtx of the reference found if any.  Otherwise,
863    returns NULL_RTX.  */
864 static rtx
865 regno_val_use_in (unsigned int regno, rtx x)
866 {
867   const char *fmt;
868   int i, j;
869   rtx tem;
870 
871   if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val)
872     return x;
873 
874   fmt = GET_RTX_FORMAT (GET_CODE (x));
875   for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
876     {
877       if (fmt[i] == 'e')
878 	{
879 	  if ((tem = regno_val_use_in (regno, XEXP (x, i))))
880 	    return tem;
881 	}
882       else if (fmt[i] == 'E')
883 	for (j = XVECLEN (x, i) - 1; j >= 0; j--)
884 	  if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j))))
885 	    return tem;
886     }
887 
888   return NULL_RTX;
889 }
890 
891 /* Return true if all current insn non-output operands except INS (it
892    has a negaitve end marker) do not use pseudos with the same value
893    as REGNO.  */
894 static bool
895 check_conflict_input_operands (int regno, signed char *ins)
896 {
897   int in;
898   int n_operands = curr_static_id->n_operands;
899 
900   for (int nop = 0; nop < n_operands; nop++)
901     if (! curr_static_id->operand[nop].is_operator
902 	&& curr_static_id->operand[nop].type != OP_OUT)
903       {
904 	for (int i = 0; (in = ins[i]) >= 0; i++)
905 	  if (in == nop)
906 	    break;
907 	if (in < 0
908 	    && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX)
909 	  return false;
910       }
911   return true;
912 }
913 
914 /* Generate reloads for matching OUT and INS (array of input operand
915    numbers with end marker -1) with reg class GOAL_CLASS, considering
916    output operands OUTS (similar array to INS) needing to be in different
917    registers.  Add input and output reloads correspondingly to the lists
918    *BEFORE and *AFTER.  OUT might be negative.  In this case we generate
919    input reloads for matched input operands INS.  EARLY_CLOBBER_P is a flag
920    that the output operand is early clobbered for chosen alternative.  */
921 static void
922 match_reload (signed char out, signed char *ins, signed char *outs,
923 	      enum reg_class goal_class, rtx_insn **before,
924 	      rtx_insn **after, bool early_clobber_p)
925 {
926   bool out_conflict;
927   int i, in;
928   rtx new_in_reg, new_out_reg, reg;
929   machine_mode inmode, outmode;
930   rtx in_rtx = *curr_id->operand_loc[ins[0]];
931   rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
932 
933   inmode = curr_operand_mode[ins[0]];
934   outmode = out < 0 ? inmode : curr_operand_mode[out];
935   push_to_sequence (*before);
936   if (inmode != outmode)
937     {
938       /* process_alt_operands has already checked that the mode sizes
939 	 are ordered.  */
940       if (partial_subreg_p (outmode, inmode))
941 	{
942 	  reg = new_in_reg
943 	    = lra_create_new_reg_with_unique_value (inmode, in_rtx,
944 						    goal_class, "");
945 	  new_out_reg = gen_lowpart_SUBREG (outmode, reg);
946 	  LRA_SUBREG_P (new_out_reg) = 1;
947 	  /* If the input reg is dying here, we can use the same hard
948 	     register for REG and IN_RTX.  We do it only for original
949 	     pseudos as reload pseudos can die although original
950 	     pseudos still live where reload pseudos dies.  */
951 	  if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start
952 	      && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
953 	      && (!early_clobber_p
954 		  || check_conflict_input_operands(REGNO (in_rtx), ins)))
955 	    lra_assign_reg_val (REGNO (in_rtx), REGNO (reg));
956 	}
957       else
958 	{
959 	  reg = new_out_reg
960 	    = lra_create_new_reg_with_unique_value (outmode, out_rtx,
961 						    goal_class, "");
962 	  new_in_reg = gen_lowpart_SUBREG (inmode, reg);
963 	  /* NEW_IN_REG is non-paradoxical subreg.  We don't want
964 	     NEW_OUT_REG living above.  We add clobber clause for
965 	     this.  This is just a temporary clobber.  We can remove
966 	     it at the end of LRA work.  */
967 	  rtx_insn *clobber = emit_clobber (new_out_reg);
968 	  LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
969 	  LRA_SUBREG_P (new_in_reg) = 1;
970 	  if (GET_CODE (in_rtx) == SUBREG)
971 	    {
972 	      rtx subreg_reg = SUBREG_REG (in_rtx);
973 
974 	      /* If SUBREG_REG is dying here and sub-registers IN_RTX
975 		 and NEW_IN_REG are similar, we can use the same hard
976 		 register for REG and SUBREG_REG.  */
977 	      if (REG_P (subreg_reg)
978 		  && (int) REGNO (subreg_reg) < lra_new_regno_start
979 		  && GET_MODE (subreg_reg) == outmode
980 		  && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg))
981 		  && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))
982 		  && (! early_clobber_p
983 		      || check_conflict_input_operands (REGNO (subreg_reg),
984 							ins)))
985 		lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg));
986 	    }
987 	}
988     }
989   else
990     {
991       /* Pseudos have values -- see comments for lra_reg_info.
992 	 Different pseudos with the same value do not conflict even if
993 	 they live in the same place.  When we create a pseudo we
994 	 assign value of original pseudo (if any) from which we
995 	 created the new pseudo.  If we create the pseudo from the
996 	 input pseudo, the new pseudo will have no conflict with the
997 	 input pseudo which is wrong when the input pseudo lives after
998 	 the insn and as the new pseudo value is changed by the insn
999 	 output.  Therefore we create the new pseudo from the output
1000 	 except the case when we have single matched dying input
1001 	 pseudo.
1002 
1003 	 We cannot reuse the current output register because we might
1004 	 have a situation like "a <- a op b", where the constraints
1005 	 force the second input operand ("b") to match the output
1006 	 operand ("a").  "b" must then be copied into a new register
1007 	 so that it doesn't clobber the current value of "a".
1008 
1009 	 We can not use the same value if the output pseudo is
1010 	 early clobbered or the input pseudo is mentioned in the
1011 	 output, e.g. as an address part in memory, because
1012 	 output reload will actually extend the pseudo liveness.
1013 	 We don't care about eliminable hard regs here as we are
1014 	 interesting only in pseudos.  */
1015 
1016       /* Matching input's register value is the same as one of the other
1017 	 output operand.  Output operands in a parallel insn must be in
1018 	 different registers.  */
1019       out_conflict = false;
1020       if (REG_P (in_rtx))
1021 	{
1022 	  for (i = 0; outs[i] >= 0; i++)
1023 	    {
1024 	      rtx other_out_rtx = *curr_id->operand_loc[outs[i]];
1025 	      if (REG_P (other_out_rtx)
1026 		  && (regno_val_use_in (REGNO (in_rtx), other_out_rtx)
1027 		      != NULL_RTX))
1028 		{
1029 		  out_conflict = true;
1030 		  break;
1031 		}
1032 	    }
1033 	}
1034 
1035       new_in_reg = new_out_reg
1036 	= (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx)
1037 	   && (int) REGNO (in_rtx) < lra_new_regno_start
1038 	   && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
1039 	   && (! early_clobber_p
1040 	       || check_conflict_input_operands (REGNO (in_rtx), ins))
1041 	   && (out < 0
1042 	       || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX)
1043 	   && !out_conflict
1044 	   ? lra_create_new_reg (inmode, in_rtx, goal_class, "")
1045 	   : lra_create_new_reg_with_unique_value (outmode, out_rtx,
1046 						   goal_class, ""));
1047     }
1048   /* In operand can be got from transformations before processing insn
1049      constraints.  One example of such transformations is subreg
1050      reloading (see function simplify_operand_subreg).  The new
1051      pseudos created by the transformations might have inaccurate
1052      class (ALL_REGS) and we should make their classes more
1053      accurate.  */
1054   narrow_reload_pseudo_class (in_rtx, goal_class);
1055   lra_emit_move (copy_rtx (new_in_reg), in_rtx);
1056   *before = get_insns ();
1057   end_sequence ();
1058   /* Add the new pseudo to consider values of subsequent input reload
1059      pseudos.  */
1060   lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
1061   curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx;
1062   curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true;
1063   curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg;
1064   for (i = 0; (in = ins[i]) >= 0; i++)
1065     {
1066       lra_assert
1067 	(GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
1068 	 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]));
1069       *curr_id->operand_loc[in] = new_in_reg;
1070     }
1071   lra_update_dups (curr_id, ins);
1072   if (out < 0)
1073     return;
1074   /* See a comment for the input operand above.  */
1075   narrow_reload_pseudo_class (out_rtx, goal_class);
1076   if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX)
1077     {
1078       start_sequence ();
1079       lra_emit_move (out_rtx, copy_rtx (new_out_reg));
1080       emit_insn (*after);
1081       *after = get_insns ();
1082       end_sequence ();
1083     }
1084   *curr_id->operand_loc[out] = new_out_reg;
1085   lra_update_dup (curr_id, out);
1086 }
1087 
1088 /* Return register class which is union of all reg classes in insn
1089    constraint alternative string starting with P.  */
1090 static enum reg_class
1091 reg_class_from_constraints (const char *p)
1092 {
1093   int c, len;
1094   enum reg_class op_class = NO_REGS;
1095 
1096   do
1097     switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1098       {
1099       case '#':
1100       case ',':
1101 	return op_class;
1102 
1103       case 'g':
1104 	op_class = reg_class_subunion[op_class][GENERAL_REGS];
1105 	break;
1106 
1107       default:
1108 	enum constraint_num cn = lookup_constraint (p);
1109 	enum reg_class cl = reg_class_for_constraint (cn);
1110 	if (cl == NO_REGS)
1111 	  {
1112 	    if (insn_extra_address_constraint (cn))
1113 	      op_class
1114 		= (reg_class_subunion
1115 		   [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1116 					      ADDRESS, SCRATCH)]);
1117 	    break;
1118 	  }
1119 
1120 	op_class = reg_class_subunion[op_class][cl];
1121  	break;
1122       }
1123   while ((p += len), c);
1124   return op_class;
1125 }
1126 
1127 /* If OP is a register, return the class of the register as per
1128    get_reg_class, otherwise return NO_REGS.  */
1129 static inline enum reg_class
1130 get_op_class (rtx op)
1131 {
1132   return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS;
1133 }
1134 
1135 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1136    otherwise.  If modes of MEM_PSEUDO and VAL are different, use
1137    SUBREG for VAL to make them equal.  */
1138 static rtx_insn *
1139 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
1140 {
1141   if (GET_MODE (mem_pseudo) != GET_MODE (val))
1142     {
1143       /* Usually size of mem_pseudo is greater than val size but in
1144 	 rare cases it can be less as it can be defined by target
1145 	 dependent macro HARD_REGNO_CALLER_SAVE_MODE.  */
1146       if (! MEM_P (val))
1147 	{
1148 	  val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
1149 				    GET_CODE (val) == SUBREG
1150 				    ? SUBREG_REG (val) : val);
1151 	  LRA_SUBREG_P (val) = 1;
1152 	}
1153       else
1154 	{
1155 	  mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo);
1156 	  LRA_SUBREG_P (mem_pseudo) = 1;
1157 	}
1158     }
1159   return to_p ? gen_move_insn (mem_pseudo, val)
1160 	      : gen_move_insn (val, mem_pseudo);
1161 }
1162 
1163 /* Process a special case insn (register move), return true if we
1164    don't need to process it anymore.  INSN should be a single set
1165    insn.  Set up that RTL was changed through CHANGE_P and that hook
1166    TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1167    SEC_MEM_P.  */
1168 static bool
1169 check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
1170 {
1171   int sregno, dregno;
1172   rtx dest, src, dreg, sreg, new_reg, scratch_reg;
1173   rtx_insn *before;
1174   enum reg_class dclass, sclass, secondary_class;
1175   secondary_reload_info sri;
1176 
1177   lra_assert (curr_insn_set != NULL_RTX);
1178   dreg = dest = SET_DEST (curr_insn_set);
1179   sreg = src = SET_SRC (curr_insn_set);
1180   if (GET_CODE (dest) == SUBREG)
1181     dreg = SUBREG_REG (dest);
1182   if (GET_CODE (src) == SUBREG)
1183     sreg = SUBREG_REG (src);
1184   if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
1185     return false;
1186   sclass = dclass = NO_REGS;
1187   if (REG_P (dreg))
1188     dclass = get_reg_class (REGNO (dreg));
1189   gcc_assert (dclass < LIM_REG_CLASSES);
1190   if (dclass == ALL_REGS)
1191     /* ALL_REGS is used for new pseudos created by transformations
1192        like reload of SUBREG_REG (see function
1193        simplify_operand_subreg).  We don't know their class yet.  We
1194        should figure out the class from processing the insn
1195        constraints not in this fast path function.  Even if ALL_REGS
1196        were a right class for the pseudo, secondary_... hooks usually
1197        are not define for ALL_REGS.  */
1198     return false;
1199   if (REG_P (sreg))
1200     sclass = get_reg_class (REGNO (sreg));
1201   gcc_assert (sclass < LIM_REG_CLASSES);
1202   if (sclass == ALL_REGS)
1203     /* See comments above.  */
1204     return false;
1205   if (sclass == NO_REGS && dclass == NO_REGS)
1206     return false;
1207   if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass)
1208       && ((sclass != NO_REGS && dclass != NO_REGS)
1209 	  || (GET_MODE (src)
1210 	      != targetm.secondary_memory_needed_mode (GET_MODE (src)))))
1211     {
1212       *sec_mem_p = true;
1213       return false;
1214     }
1215   if (! REG_P (dreg) || ! REG_P (sreg))
1216     return false;
1217   sri.prev_sri = NULL;
1218   sri.icode = CODE_FOR_nothing;
1219   sri.extra_cost = 0;
1220   secondary_class = NO_REGS;
1221   /* Set up hard register for a reload pseudo for hook
1222      secondary_reload because some targets just ignore unassigned
1223      pseudos in the hook.  */
1224   if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0)
1225     {
1226       dregno = REGNO (dreg);
1227       reg_renumber[dregno] = ira_class_hard_regs[dclass][0];
1228     }
1229   else
1230     dregno = -1;
1231   if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0)
1232     {
1233       sregno = REGNO (sreg);
1234       reg_renumber[sregno] = ira_class_hard_regs[sclass][0];
1235     }
1236   else
1237     sregno = -1;
1238   if (sclass != NO_REGS)
1239     secondary_class
1240       = (enum reg_class) targetm.secondary_reload (false, dest,
1241 						   (reg_class_t) sclass,
1242 						   GET_MODE (src), &sri);
1243   if (sclass == NO_REGS
1244       || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1245 	  && dclass != NO_REGS))
1246     {
1247       enum reg_class old_sclass = secondary_class;
1248       secondary_reload_info old_sri = sri;
1249 
1250       sri.prev_sri = NULL;
1251       sri.icode = CODE_FOR_nothing;
1252       sri.extra_cost = 0;
1253       secondary_class
1254 	= (enum reg_class) targetm.secondary_reload (true, src,
1255 						     (reg_class_t) dclass,
1256 						     GET_MODE (src), &sri);
1257       /* Check the target hook consistency.  */
1258       lra_assert
1259 	((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1260 	 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)
1261 	 || (secondary_class == old_sclass && sri.icode == old_sri.icode));
1262     }
1263   if (sregno >= 0)
1264     reg_renumber [sregno] = -1;
1265   if (dregno >= 0)
1266     reg_renumber [dregno] = -1;
1267   if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1268     return false;
1269   *change_p = true;
1270   new_reg = NULL_RTX;
1271   if (secondary_class != NO_REGS)
1272     new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX,
1273 						    secondary_class,
1274 						    "secondary");
1275   start_sequence ();
1276   if (sri.icode == CODE_FOR_nothing)
1277     lra_emit_move (new_reg, src);
1278   else
1279     {
1280       enum reg_class scratch_class;
1281 
1282       scratch_class = (reg_class_from_constraints
1283 		       (insn_data[sri.icode].operand[2].constraint));
1284       scratch_reg = (lra_create_new_reg_with_unique_value
1285 		     (insn_data[sri.icode].operand[2].mode, NULL_RTX,
1286 		      scratch_class, "scratch"));
1287       emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
1288 				      src, scratch_reg));
1289     }
1290   before = get_insns ();
1291   end_sequence ();
1292   lra_process_new_insns (curr_insn, before, NULL, "Inserting the move");
1293   if (new_reg != NULL_RTX)
1294     SET_SRC (curr_insn_set) = new_reg;
1295   else
1296     {
1297       if (lra_dump_file != NULL)
1298 	{
1299 	  fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1300 	  dump_insn_slim (lra_dump_file, curr_insn);
1301 	}
1302       lra_set_insn_deleted (curr_insn);
1303       return true;
1304     }
1305   return false;
1306 }
1307 
1308 /* The following data describe the result of process_alt_operands.
1309    The data are used in curr_insn_transform to generate reloads.  */
1310 
1311 /* The chosen reg classes which should be used for the corresponding
1312    operands.  */
1313 static enum reg_class goal_alt[MAX_RECOG_OPERANDS];
1314 /* True if the operand should be the same as another operand and that
1315    other operand does not need a reload.  */
1316 static bool goal_alt_match_win[MAX_RECOG_OPERANDS];
1317 /* True if the operand does not need a reload.	*/
1318 static bool goal_alt_win[MAX_RECOG_OPERANDS];
1319 /* True if the operand can be offsetable memory.  */
1320 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS];
1321 /* The number of an operand to which given operand can be matched to.  */
1322 static int goal_alt_matches[MAX_RECOG_OPERANDS];
1323 /* The number of elements in the following array.  */
1324 static int goal_alt_dont_inherit_ops_num;
1325 /* Numbers of operands whose reload pseudos should not be inherited.  */
1326 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1327 /* True if the insn commutative operands should be swapped.  */
1328 static bool goal_alt_swapped;
1329 /* The chosen insn alternative.	 */
1330 static int goal_alt_number;
1331 
1332 /* True if the corresponding operand is the result of an equivalence
1333    substitution.  */
1334 static bool equiv_substition_p[MAX_RECOG_OPERANDS];
1335 
1336 /* The following five variables are used to choose the best insn
1337    alternative.	 They reflect final characteristics of the best
1338    alternative.	 */
1339 
1340 /* Number of necessary reloads and overall cost reflecting the
1341    previous value and other unpleasantness of the best alternative.  */
1342 static int best_losers, best_overall;
1343 /* Overall number hard registers used for reloads.  For example, on
1344    some targets we need 2 general registers to reload DFmode and only
1345    one floating point register.	 */
1346 static int best_reload_nregs;
1347 /* Overall number reflecting distances of previous reloading the same
1348    value.  The distances are counted from the current BB start.  It is
1349    used to improve inheritance chances.  */
1350 static int best_reload_sum;
1351 
1352 /* True if the current insn should have no correspondingly input or
1353    output reloads.  */
1354 static bool no_input_reloads_p, no_output_reloads_p;
1355 
1356 /* True if we swapped the commutative operands in the current
1357    insn.  */
1358 static int curr_swapped;
1359 
1360 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1361    register of class CL.  Add any input reloads to list BEFORE.  AFTER
1362    is nonnull if *LOC is an automodified value; handle that case by
1363    adding the required output reloads to list AFTER.  Return true if
1364    the RTL was changed.
1365 
1366    if CHECK_ONLY_P is true, check that the *LOC is a correct address
1367    register.  Return false if the address register is correct.  */
1368 static bool
1369 process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after,
1370 		  enum reg_class cl)
1371 {
1372   int regno;
1373   enum reg_class rclass, new_class;
1374   rtx reg;
1375   rtx new_reg;
1376   machine_mode mode;
1377   bool subreg_p, before_p = false;
1378 
1379   subreg_p = GET_CODE (*loc) == SUBREG;
1380   if (subreg_p)
1381     {
1382       reg = SUBREG_REG (*loc);
1383       mode = GET_MODE (reg);
1384 
1385       /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1386 	 between two registers with different classes, but there normally will
1387 	 be "mov" which transfers element of vector register into the general
1388 	 register, and this normally will be a subreg which should be reloaded
1389 	 as a whole.  This is particularly likely to be triggered when
1390 	 -fno-split-wide-types specified.  */
1391       if (!REG_P (reg)
1392 	  || in_class_p (reg, cl, &new_class)
1393 	  || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode)))
1394        loc = &SUBREG_REG (*loc);
1395     }
1396 
1397   reg = *loc;
1398   mode = GET_MODE (reg);
1399   if (! REG_P (reg))
1400     {
1401       if (check_only_p)
1402 	return true;
1403       /* Always reload memory in an address even if the target supports
1404 	 such addresses.  */
1405       new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address");
1406       before_p = true;
1407     }
1408   else
1409     {
1410       regno = REGNO (reg);
1411       rclass = get_reg_class (regno);
1412       if (! check_only_p
1413 	  && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1414 	{
1415 	  if (lra_dump_file != NULL)
1416 	    {
1417 	      fprintf (lra_dump_file,
1418 		       "Changing pseudo %d in address of insn %u on equiv ",
1419 		       REGNO (reg), INSN_UID (curr_insn));
1420 	      dump_value_slim (lra_dump_file, *loc, 1);
1421 	      fprintf (lra_dump_file, "\n");
1422 	    }
1423 	  *loc = copy_rtx (*loc);
1424 	}
1425       if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1426 	{
1427 	  if (check_only_p)
1428 	    return true;
1429 	  reg = *loc;
1430 	  if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT,
1431 			      mode, reg, cl, subreg_p, "address", &new_reg))
1432 	    before_p = true;
1433 	}
1434       else if (new_class != NO_REGS && rclass != new_class)
1435 	{
1436 	  if (check_only_p)
1437 	    return true;
1438 	  lra_change_class (regno, new_class, "	   Change to", true);
1439 	  return false;
1440 	}
1441       else
1442 	return false;
1443     }
1444   if (before_p)
1445     {
1446       push_to_sequence (*before);
1447       lra_emit_move (new_reg, reg);
1448       *before = get_insns ();
1449       end_sequence ();
1450     }
1451   *loc = new_reg;
1452   if (after != NULL)
1453     {
1454       start_sequence ();
1455       lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg);
1456       emit_insn (*after);
1457       *after = get_insns ();
1458       end_sequence ();
1459     }
1460   return true;
1461 }
1462 
1463 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1464    the insn to be inserted before curr insn. AFTER returns the
1465    the insn to be inserted after curr insn.  ORIGREG and NEWREG
1466    are the original reg and new reg for reload.  */
1467 static void
1468 insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg,
1469 			rtx newreg)
1470 {
1471   if (before)
1472     {
1473       push_to_sequence (*before);
1474       lra_emit_move (newreg, origreg);
1475       *before = get_insns ();
1476       end_sequence ();
1477     }
1478   if (after)
1479     {
1480       start_sequence ();
1481       lra_emit_move (origreg, newreg);
1482       emit_insn (*after);
1483       *after = get_insns ();
1484       end_sequence ();
1485     }
1486 }
1487 
1488 static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as);
1489 static bool process_address (int, bool, rtx_insn **, rtx_insn **);
1490 
1491 /* Make reloads for subreg in operand NOP with internal subreg mode
1492    REG_MODE, add new reloads for further processing.  Return true if
1493    any change was done.  */
1494 static bool
1495 simplify_operand_subreg (int nop, machine_mode reg_mode)
1496 {
1497   int hard_regno;
1498   rtx_insn *before, *after;
1499   machine_mode mode, innermode;
1500   rtx reg, new_reg;
1501   rtx operand = *curr_id->operand_loc[nop];
1502   enum reg_class regclass;
1503   enum op_type type;
1504 
1505   before = after = NULL;
1506 
1507   if (GET_CODE (operand) != SUBREG)
1508     return false;
1509 
1510   mode = GET_MODE (operand);
1511   reg = SUBREG_REG (operand);
1512   innermode = GET_MODE (reg);
1513   type = curr_static_id->operand[nop].type;
1514   if (MEM_P (reg))
1515     {
1516       const bool addr_was_valid
1517 	= valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg));
1518       alter_subreg (curr_id->operand_loc[nop], false);
1519       rtx subst = *curr_id->operand_loc[nop];
1520       lra_assert (MEM_P (subst));
1521 
1522       if (!addr_was_valid
1523 	  || valid_address_p (GET_MODE (subst), XEXP (subst, 0),
1524 			      MEM_ADDR_SPACE (subst))
1525 	  || ((get_constraint_type (lookup_constraint
1526 				    (curr_static_id->operand[nop].constraint))
1527 	       != CT_SPECIAL_MEMORY)
1528 	      /* We still can reload address and if the address is
1529 		 valid, we can remove subreg without reloading its
1530 		 inner memory.  */
1531 	      && valid_address_p (GET_MODE (subst),
1532 				  regno_reg_rtx
1533 				  [ira_class_hard_regs
1534 				   [base_reg_class (GET_MODE (subst),
1535 						    MEM_ADDR_SPACE (subst),
1536 						    ADDRESS, SCRATCH)][0]],
1537 				  MEM_ADDR_SPACE (subst))))
1538 	{
1539 	  /* If we change the address for a paradoxical subreg of memory, the
1540 	     new address might violate the necessary alignment or the access
1541 	     might be slow; take this into consideration.  We need not worry
1542 	     about accesses beyond allocated memory for paradoxical memory
1543 	     subregs as we don't substitute such equiv memory (see processing
1544 	     equivalences in function lra_constraints) and because for spilled
1545 	     pseudos we allocate stack memory enough for the biggest
1546 	     corresponding paradoxical subreg.
1547 
1548 	     However, do not blindly simplify a (subreg (mem ...)) for
1549 	     WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1550 	     data into a register when the inner is narrower than outer or
1551 	     missing important data from memory when the inner is wider than
1552 	     outer.  This rule only applies to modes that are no wider than
1553 	     a word.  */
1554 	  if (!(maybe_ne (GET_MODE_PRECISION (mode),
1555 			  GET_MODE_PRECISION (innermode))
1556 		&& known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD)
1557 		&& known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD)
1558 		&& WORD_REGISTER_OPERATIONS)
1559 	      && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode)
1560 		    && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst)))
1561 		  || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode)
1562 		      && targetm.slow_unaligned_access (innermode,
1563 							MEM_ALIGN (reg)))))
1564 	    return true;
1565 
1566 	  *curr_id->operand_loc[nop] = operand;
1567 
1568 	  /* But if the address was not valid, we cannot reload the MEM without
1569 	     reloading the address first.  */
1570 	  if (!addr_was_valid)
1571 	    process_address (nop, false, &before, &after);
1572 
1573 	  /* INNERMODE is fast, MODE slow.  Reload the mem in INNERMODE.  */
1574 	  enum reg_class rclass
1575 	    = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1576 	  if (get_reload_reg (curr_static_id->operand[nop].type, innermode,
1577 			      reg, rclass, TRUE, "slow mem", &new_reg))
1578 	    {
1579 	      bool insert_before, insert_after;
1580 	      bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1581 
1582 	      insert_before = (type != OP_OUT
1583 			       || partial_subreg_p (mode, innermode));
1584 	      insert_after = type != OP_IN;
1585 	      insert_move_for_subreg (insert_before ? &before : NULL,
1586 				      insert_after ? &after : NULL,
1587 				      reg, new_reg);
1588 	    }
1589 	  SUBREG_REG (operand) = new_reg;
1590 
1591 	  /* Convert to MODE.  */
1592 	  reg = operand;
1593 	  rclass
1594 	    = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1595 	  if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1596 			      rclass, TRUE, "slow mem", &new_reg))
1597 	    {
1598 	      bool insert_before, insert_after;
1599 	      bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1600 
1601 	      insert_before = type != OP_OUT;
1602 	      insert_after = type != OP_IN;
1603 	      insert_move_for_subreg (insert_before ? &before : NULL,
1604 				      insert_after ? &after : NULL,
1605 				      reg, new_reg);
1606 	    }
1607 	  *curr_id->operand_loc[nop] = new_reg;
1608 	  lra_process_new_insns (curr_insn, before, after,
1609 				 "Inserting slow mem reload");
1610 	  return true;
1611 	}
1612 
1613       /* If the address was valid and became invalid, prefer to reload
1614 	 the memory.  Typical case is when the index scale should
1615 	 correspond the memory.  */
1616       *curr_id->operand_loc[nop] = operand;
1617       /* Do not return false here as the MEM_P (reg) will be processed
1618 	 later in this function.  */
1619     }
1620   else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)
1621     {
1622       alter_subreg (curr_id->operand_loc[nop], false);
1623       return true;
1624     }
1625   else if (CONSTANT_P (reg))
1626     {
1627       /* Try to simplify subreg of constant.  It is usually result of
1628 	 equivalence substitution.  */
1629       if (innermode == VOIDmode
1630 	  && (innermode = original_subreg_reg_mode[nop]) == VOIDmode)
1631 	innermode = curr_static_id->operand[nop].mode;
1632       if ((new_reg = simplify_subreg (mode, reg, innermode,
1633 				      SUBREG_BYTE (operand))) != NULL_RTX)
1634 	{
1635 	  *curr_id->operand_loc[nop] = new_reg;
1636 	  return true;
1637 	}
1638     }
1639   /* Put constant into memory when we have mixed modes.  It generates
1640      a better code in most cases as it does not need a secondary
1641      reload memory.  It also prevents LRA looping when LRA is using
1642      secondary reload memory again and again.  */
1643   if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg)
1644       && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode))
1645     {
1646       SUBREG_REG (operand) = force_const_mem (reg_mode, reg);
1647       alter_subreg (curr_id->operand_loc[nop], false);
1648       return true;
1649     }
1650   /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1651      if there may be a problem accessing OPERAND in the outer
1652      mode.  */
1653   if ((REG_P (reg)
1654        && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1655        && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1656        /* Don't reload paradoxical subregs because we could be looping
1657 	  having repeatedly final regno out of hard regs range.  */
1658        && (hard_regno_nregs (hard_regno, innermode)
1659 	   >= hard_regno_nregs (hard_regno, mode))
1660        && simplify_subreg_regno (hard_regno, innermode,
1661 				 SUBREG_BYTE (operand), mode) < 0
1662        /* Don't reload subreg for matching reload.  It is actually
1663 	  valid subreg in LRA.  */
1664        && ! LRA_SUBREG_P (operand))
1665       || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
1666     {
1667       enum reg_class rclass;
1668 
1669       if (REG_P (reg))
1670 	/* There is a big probability that we will get the same class
1671 	   for the new pseudo and we will get the same insn which
1672 	   means infinite looping.  So spill the new pseudo.  */
1673 	rclass = NO_REGS;
1674       else
1675 	/* The class will be defined later in curr_insn_transform.  */
1676 	rclass
1677 	  = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1678 
1679       if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1680 			  rclass, TRUE, "subreg reg", &new_reg))
1681 	{
1682 	  bool insert_before, insert_after;
1683 	  bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1684 
1685 	  insert_before = (type != OP_OUT
1686 			   || read_modify_subreg_p (operand));
1687 	  insert_after = (type != OP_IN);
1688 	  insert_move_for_subreg (insert_before ? &before : NULL,
1689 				  insert_after ? &after : NULL,
1690 				  reg, new_reg);
1691 	}
1692       SUBREG_REG (operand) = new_reg;
1693       lra_process_new_insns (curr_insn, before, after,
1694 			     "Inserting subreg reload");
1695       return true;
1696     }
1697   /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1698      IRA allocates hardreg to the inner pseudo reg according to its mode
1699      instead of the outermode, so the size of the hardreg may not be enough
1700      to contain the outermode operand, in that case we may need to insert
1701      reload for the reg. For the following two types of paradoxical subreg,
1702      we need to insert reload:
1703      1. If the op_type is OP_IN, and the hardreg could not be paired with
1704         other hardreg to contain the outermode operand
1705         (checked by in_hard_reg_set_p), we need to insert the reload.
1706      2. If the op_type is OP_OUT or OP_INOUT.
1707 
1708      Here is a paradoxical subreg example showing how the reload is generated:
1709 
1710      (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1711         (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1712 
1713      In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1714      here, if reg107 is assigned to hardreg R15, because R15 is the last
1715      hardreg, compiler cannot find another hardreg to pair with R15 to
1716      contain TImode data. So we insert a TImode reload reg180 for it.
1717      After reload is inserted:
1718 
1719      (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1720         (reg:DI 107 [ __comp ])) -1
1721      (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1722         (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1723 
1724      Two reload hard registers will be allocated to reg180 to save TImode data
1725      in LRA_assign.  */
1726   else if (REG_P (reg)
1727 	   && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1728 	   && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1729 	   && (hard_regno_nregs (hard_regno, innermode)
1730 	       < hard_regno_nregs (hard_regno, mode))
1731 	   && (regclass = lra_get_allocno_class (REGNO (reg)))
1732 	   && (type != OP_IN
1733 	       || !in_hard_reg_set_p (reg_class_contents[regclass],
1734 				      mode, hard_regno)))
1735     {
1736       /* The class will be defined later in curr_insn_transform.  */
1737       enum reg_class rclass
1738 	= (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1739 
1740       if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1741                           rclass, TRUE, "paradoxical subreg", &new_reg))
1742         {
1743 	  rtx subreg;
1744 	  bool insert_before, insert_after;
1745 
1746 	  PUT_MODE (new_reg, mode);
1747           subreg = gen_lowpart_SUBREG (innermode, new_reg);
1748 	  bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1749 
1750 	  insert_before = (type != OP_OUT);
1751 	  insert_after = (type != OP_IN);
1752 	  insert_move_for_subreg (insert_before ? &before : NULL,
1753 				  insert_after ? &after : NULL,
1754 				  reg, subreg);
1755 	}
1756       SUBREG_REG (operand) = new_reg;
1757       lra_process_new_insns (curr_insn, before, after,
1758                              "Inserting paradoxical subreg reload");
1759       return true;
1760     }
1761   return false;
1762 }
1763 
1764 /* Return TRUE if X refers for a hard register from SET.  */
1765 static bool
1766 uses_hard_regs_p (rtx x, HARD_REG_SET set)
1767 {
1768   int i, j, x_hard_regno;
1769   machine_mode mode;
1770   const char *fmt;
1771   enum rtx_code code;
1772 
1773   if (x == NULL_RTX)
1774     return false;
1775   code = GET_CODE (x);
1776   mode = GET_MODE (x);
1777   if (code == SUBREG)
1778     {
1779       mode = wider_subreg_mode (x);
1780       x = SUBREG_REG (x);
1781       code = GET_CODE (x);
1782     }
1783 
1784   if (REG_P (x))
1785     {
1786       x_hard_regno = get_hard_regno (x, true);
1787       return (x_hard_regno >= 0
1788 	      && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1789     }
1790   if (MEM_P (x))
1791     {
1792       struct address_info ad;
1793 
1794       decompose_mem_address (&ad, x);
1795       if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set))
1796 	return true;
1797       if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set))
1798 	return true;
1799     }
1800   fmt = GET_RTX_FORMAT (code);
1801   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1802     {
1803       if (fmt[i] == 'e')
1804 	{
1805 	  if (uses_hard_regs_p (XEXP (x, i), set))
1806 	    return true;
1807 	}
1808       else if (fmt[i] == 'E')
1809 	{
1810 	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1811 	    if (uses_hard_regs_p (XVECEXP (x, i, j), set))
1812 	      return true;
1813 	}
1814     }
1815   return false;
1816 }
1817 
1818 /* Return true if OP is a spilled pseudo. */
1819 static inline bool
1820 spilled_pseudo_p (rtx op)
1821 {
1822   return (REG_P (op)
1823 	  && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op)));
1824 }
1825 
1826 /* Return true if X is a general constant.  */
1827 static inline bool
1828 general_constant_p (rtx x)
1829 {
1830   return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
1831 }
1832 
1833 static bool
1834 reg_in_class_p (rtx reg, enum reg_class cl)
1835 {
1836   if (cl == NO_REGS)
1837     return get_reg_class (REGNO (reg)) == NO_REGS;
1838   return in_class_p (reg, cl, NULL);
1839 }
1840 
1841 /* Return true if SET of RCLASS contains no hard regs which can be
1842    used in MODE.  */
1843 static bool
1844 prohibited_class_reg_set_mode_p (enum reg_class rclass,
1845 				 HARD_REG_SET &set,
1846 				 machine_mode mode)
1847 {
1848   HARD_REG_SET temp;
1849 
1850   lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
1851   COPY_HARD_REG_SET (temp, set);
1852   AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs);
1853   return (hard_reg_set_subset_p
1854 	  (temp, ira_prohibited_class_mode_regs[rclass][mode]));
1855 }
1856 
1857 
1858 /* Used to check validity info about small class input operands.  It
1859    should be incremented at start of processing an insn
1860    alternative.  */
1861 static unsigned int curr_small_class_check = 0;
1862 
1863 /* Update number of used inputs of class OP_CLASS for operand NOP.
1864    Return true if we have more such class operands than the number of
1865    available regs.  */
1866 static bool
1867 update_and_check_small_class_inputs (int nop, enum reg_class op_class)
1868 {
1869   static unsigned int small_class_check[LIM_REG_CLASSES];
1870   static int small_class_input_nums[LIM_REG_CLASSES];
1871 
1872   if (SMALL_REGISTER_CLASS_P (op_class)
1873       /* We are interesting in classes became small because of fixing
1874 	 some hard regs, e.g. by an user through GCC options.  */
1875       && hard_reg_set_intersect_p (reg_class_contents[op_class],
1876 				   ira_no_alloc_regs)
1877       && (curr_static_id->operand[nop].type != OP_OUT
1878 	  || curr_static_id->operand[nop].early_clobber))
1879     {
1880       if (small_class_check[op_class] == curr_small_class_check)
1881 	small_class_input_nums[op_class]++;
1882       else
1883 	{
1884 	  small_class_check[op_class] = curr_small_class_check;
1885 	  small_class_input_nums[op_class] = 1;
1886 	}
1887       if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class])
1888 	return true;
1889     }
1890   return false;
1891 }
1892 
1893 /* Major function to choose the current insn alternative and what
1894    operands should be reloaded and how.	 If ONLY_ALTERNATIVE is not
1895    negative we should consider only this alternative.  Return false if
1896    we can not choose the alternative or find how to reload the
1897    operands.  */
1898 static bool
1899 process_alt_operands (int only_alternative)
1900 {
1901   bool ok_p = false;
1902   int nop, overall, nalt;
1903   int n_alternatives = curr_static_id->n_alternatives;
1904   int n_operands = curr_static_id->n_operands;
1905   /* LOSERS counts the operands that don't fit this alternative and
1906      would require loading.  */
1907   int losers;
1908   int addr_losers;
1909   /* REJECT is a count of how undesirable this alternative says it is
1910      if any reloading is required.  If the alternative matches exactly
1911      then REJECT is ignored, but otherwise it gets this much counted
1912      against it in addition to the reloading needed.  */
1913   int reject;
1914   /* This is defined by '!' or '?' alternative constraint and added to
1915      reject.  But in some cases it can be ignored.  */
1916   int static_reject;
1917   int op_reject;
1918   /* The number of elements in the following array.  */
1919   int early_clobbered_regs_num;
1920   /* Numbers of operands which are early clobber registers.  */
1921   int early_clobbered_nops[MAX_RECOG_OPERANDS];
1922   enum reg_class curr_alt[MAX_RECOG_OPERANDS];
1923   HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
1924   bool curr_alt_match_win[MAX_RECOG_OPERANDS];
1925   bool curr_alt_win[MAX_RECOG_OPERANDS];
1926   bool curr_alt_offmemok[MAX_RECOG_OPERANDS];
1927   int curr_alt_matches[MAX_RECOG_OPERANDS];
1928   /* The number of elements in the following array.  */
1929   int curr_alt_dont_inherit_ops_num;
1930   /* Numbers of operands whose reload pseudos should not be inherited.	*/
1931   int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1932   rtx op;
1933   /* The register when the operand is a subreg of register, otherwise the
1934      operand itself.  */
1935   rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS];
1936   /* The register if the operand is a register or subreg of register,
1937      otherwise NULL.  */
1938   rtx operand_reg[MAX_RECOG_OPERANDS];
1939   int hard_regno[MAX_RECOG_OPERANDS];
1940   machine_mode biggest_mode[MAX_RECOG_OPERANDS];
1941   int reload_nregs, reload_sum;
1942   bool costly_p;
1943   enum reg_class cl;
1944 
1945   /* Calculate some data common for all alternatives to speed up the
1946      function.	*/
1947   for (nop = 0; nop < n_operands; nop++)
1948     {
1949       rtx reg;
1950 
1951       op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
1952       /* The real hard regno of the operand after the allocation.  */
1953       hard_regno[nop] = get_hard_regno (op, true);
1954 
1955       operand_reg[nop] = reg = op;
1956       biggest_mode[nop] = GET_MODE (op);
1957       if (GET_CODE (op) == SUBREG)
1958 	{
1959 	  biggest_mode[nop] = wider_subreg_mode (op);
1960 	  operand_reg[nop] = reg = SUBREG_REG (op);
1961 	}
1962       if (! REG_P (reg))
1963 	operand_reg[nop] = NULL_RTX;
1964       else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1965 	       || ((int) REGNO (reg)
1966 		   == lra_get_elimination_hard_regno (REGNO (reg))))
1967 	no_subreg_reg_operand[nop] = reg;
1968       else
1969 	operand_reg[nop] = no_subreg_reg_operand[nop]
1970 	  /* Just use natural mode for elimination result.  It should
1971 	     be enough for extra constraints hooks.  */
1972 	  = regno_reg_rtx[hard_regno[nop]];
1973     }
1974 
1975   /* The constraints are made of several alternatives.	Each operand's
1976      constraint looks like foo,bar,... with commas separating the
1977      alternatives.  The first alternatives for all operands go
1978      together, the second alternatives go together, etc.
1979 
1980      First loop over alternatives.  */
1981   alternative_mask preferred = curr_id->preferred_alternatives;
1982   if (only_alternative >= 0)
1983     preferred &= ALTERNATIVE_BIT (only_alternative);
1984 
1985   for (nalt = 0; nalt < n_alternatives; nalt++)
1986     {
1987       /* Loop over operands for one constraint alternative.  */
1988       if (!TEST_BIT (preferred, nalt))
1989 	continue;
1990 
1991       curr_small_class_check++;
1992       overall = losers = addr_losers = 0;
1993       static_reject = reject = reload_nregs = reload_sum = 0;
1994       for (nop = 0; nop < n_operands; nop++)
1995 	{
1996 	  int inc = (curr_static_id
1997 		     ->operand_alternative[nalt * n_operands + nop].reject);
1998 	  if (lra_dump_file != NULL && inc != 0)
1999 	    fprintf (lra_dump_file,
2000 		     "            Staticly defined alt reject+=%d\n", inc);
2001 	  static_reject += inc;
2002 	}
2003       reject += static_reject;
2004       early_clobbered_regs_num = 0;
2005 
2006       for (nop = 0; nop < n_operands; nop++)
2007 	{
2008 	  const char *p;
2009 	  char *end;
2010 	  int len, c, m, i, opalt_num, this_alternative_matches;
2011 	  bool win, did_match, offmemok, early_clobber_p;
2012 	  /* false => this operand can be reloaded somehow for this
2013 	     alternative.  */
2014 	  bool badop;
2015 	  /* true => this operand can be reloaded if the alternative
2016 	     allows regs.  */
2017 	  bool winreg;
2018 	  /* True if a constant forced into memory would be OK for
2019 	     this operand.  */
2020 	  bool constmemok;
2021 	  enum reg_class this_alternative, this_costly_alternative;
2022 	  HARD_REG_SET this_alternative_set, this_costly_alternative_set;
2023 	  bool this_alternative_match_win, this_alternative_win;
2024 	  bool this_alternative_offmemok;
2025 	  bool scratch_p;
2026 	  machine_mode mode;
2027 	  enum constraint_num cn;
2028 
2029 	  opalt_num = nalt * n_operands + nop;
2030 	  if (curr_static_id->operand_alternative[opalt_num].anything_ok)
2031 	    {
2032 	      /* Fast track for no constraints at all.	*/
2033 	      curr_alt[nop] = NO_REGS;
2034 	      CLEAR_HARD_REG_SET (curr_alt_set[nop]);
2035 	      curr_alt_win[nop] = true;
2036 	      curr_alt_match_win[nop] = false;
2037 	      curr_alt_offmemok[nop] = false;
2038 	      curr_alt_matches[nop] = -1;
2039 	      continue;
2040 	    }
2041 
2042 	  op = no_subreg_reg_operand[nop];
2043 	  mode = curr_operand_mode[nop];
2044 
2045 	  win = did_match = winreg = offmemok = constmemok = false;
2046 	  badop = true;
2047 
2048 	  early_clobber_p = false;
2049 	  p = curr_static_id->operand_alternative[opalt_num].constraint;
2050 
2051 	  this_costly_alternative = this_alternative = NO_REGS;
2052 	  /* We update set of possible hard regs besides its class
2053 	     because reg class might be inaccurate.  For example,
2054 	     union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2055 	     is translated in HI_REGS because classes are merged by
2056 	     pairs and there is no accurate intermediate class.	 */
2057 	  CLEAR_HARD_REG_SET (this_alternative_set);
2058 	  CLEAR_HARD_REG_SET (this_costly_alternative_set);
2059 	  this_alternative_win = false;
2060 	  this_alternative_match_win = false;
2061 	  this_alternative_offmemok = false;
2062 	  this_alternative_matches = -1;
2063 
2064 	  /* An empty constraint should be excluded by the fast
2065 	     track.  */
2066 	  lra_assert (*p != 0 && *p != ',');
2067 
2068 	  op_reject = 0;
2069 	  /* Scan this alternative's specs for this operand; set WIN
2070 	     if the operand fits any letter in this alternative.
2071 	     Otherwise, clear BADOP if this operand could fit some
2072 	     letter after reloads, or set WINREG if this operand could
2073 	     fit after reloads provided the constraint allows some
2074 	     registers.	 */
2075 	  costly_p = false;
2076 	  do
2077 	    {
2078 	      switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
2079 		{
2080 		case '\0':
2081 		  len = 0;
2082 		  break;
2083 		case ',':
2084 		  c = '\0';
2085 		  break;
2086 
2087 		case '&':
2088 		  early_clobber_p = true;
2089 		  break;
2090 
2091 		case '$':
2092 		  op_reject += LRA_MAX_REJECT;
2093 		  break;
2094 		case '^':
2095 		  op_reject += LRA_LOSER_COST_FACTOR;
2096 		  break;
2097 
2098 		case '#':
2099 		  /* Ignore rest of this alternative.  */
2100 		  c = '\0';
2101 		  break;
2102 
2103 		case '0':  case '1':  case '2':	 case '3':  case '4':
2104 		case '5':  case '6':  case '7':	 case '8':  case '9':
2105 		  {
2106 		    int m_hregno;
2107 		    bool match_p;
2108 
2109 		    m = strtoul (p, &end, 10);
2110 		    p = end;
2111 		    len = 0;
2112 		    lra_assert (nop > m);
2113 
2114 		    /* Reject matches if we don't know which operand is
2115 		       bigger.  This situation would arguably be a bug in
2116 		       an .md pattern, but could also occur in a user asm.  */
2117 		    if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]),
2118 				    GET_MODE_SIZE (biggest_mode[nop])))
2119 		      break;
2120 
2121 		    /* Don't match wrong asm insn operands for proper
2122 		       diagnostic later.  */
2123 		    if (INSN_CODE (curr_insn) < 0
2124 			&& (curr_operand_mode[m] == BLKmode
2125 			    || curr_operand_mode[nop] == BLKmode)
2126 			&& curr_operand_mode[m] != curr_operand_mode[nop])
2127 		      break;
2128 
2129 		    m_hregno = get_hard_regno (*curr_id->operand_loc[m], false);
2130 		    /* We are supposed to match a previous operand.
2131 		       If we do, we win if that one did.  If we do
2132 		       not, count both of the operands as losers.
2133 		       (This is too conservative, since most of the
2134 		       time only a single reload insn will be needed
2135 		       to make the two operands win.  As a result,
2136 		       this alternative may be rejected when it is
2137 		       actually desirable.)  */
2138 		    match_p = false;
2139 		    if (operands_match_p (*curr_id->operand_loc[nop],
2140 					  *curr_id->operand_loc[m], m_hregno))
2141 		      {
2142 			/* We should reject matching of an early
2143 			   clobber operand if the matching operand is
2144 			   not dying in the insn.  */
2145 			if (! curr_static_id->operand[m].early_clobber
2146 			    || operand_reg[nop] == NULL_RTX
2147 			    || (find_regno_note (curr_insn, REG_DEAD,
2148 						 REGNO (op))
2149 				|| REGNO (op) == REGNO (operand_reg[m])))
2150 			  match_p = true;
2151 		      }
2152 		    if (match_p)
2153 		      {
2154 			/* If we are matching a non-offsettable
2155 			   address where an offsettable address was
2156 			   expected, then we must reject this
2157 			   combination, because we can't reload
2158 			   it.	*/
2159 			if (curr_alt_offmemok[m]
2160 			    && MEM_P (*curr_id->operand_loc[m])
2161 			    && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
2162 			  continue;
2163 		      }
2164 		    else
2165 		      {
2166 			/* Operands don't match.  Both operands must
2167 			   allow a reload register, otherwise we
2168 			   cannot make them match.  */
2169 			if (curr_alt[m] == NO_REGS)
2170 			  break;
2171 			/* Retroactively mark the operand we had to
2172 			   match as a loser, if it wasn't already and
2173 			   it wasn't matched to a register constraint
2174 			   (e.g it might be matched by memory). */
2175 			if (curr_alt_win[m]
2176 			    && (operand_reg[m] == NULL_RTX
2177 				|| hard_regno[m] < 0))
2178 			  {
2179 			    losers++;
2180 			    reload_nregs
2181 			      += (ira_reg_class_max_nregs[curr_alt[m]]
2182 				  [GET_MODE (*curr_id->operand_loc[m])]);
2183 			  }
2184 
2185 			/* Prefer matching earlyclobber alternative as
2186 			   it results in less hard regs required for
2187 			   the insn than a non-matching earlyclobber
2188 			   alternative.  */
2189 			if (curr_static_id->operand[m].early_clobber)
2190 			  {
2191 			    if (lra_dump_file != NULL)
2192 			      fprintf
2193 				(lra_dump_file,
2194 				 "            %d Matching earlyclobber alt:"
2195 				 " reject--\n",
2196 				 nop);
2197 			    reject--;
2198 			  }
2199 			/* Otherwise we prefer no matching
2200 			   alternatives because it gives more freedom
2201 			   in RA.  */
2202 			else if (operand_reg[nop] == NULL_RTX
2203 				 || (find_regno_note (curr_insn, REG_DEAD,
2204 						      REGNO (operand_reg[nop]))
2205 				     == NULL_RTX))
2206 			  {
2207 			    if (lra_dump_file != NULL)
2208 			      fprintf
2209 				(lra_dump_file,
2210 				 "            %d Matching alt: reject+=2\n",
2211 				 nop);
2212 			    reject += 2;
2213 			  }
2214 		      }
2215 		    /* If we have to reload this operand and some
2216 		       previous operand also had to match the same
2217 		       thing as this operand, we don't know how to do
2218 		       that.  */
2219 		    if (!match_p || !curr_alt_win[m])
2220 		      {
2221 			for (i = 0; i < nop; i++)
2222 			  if (curr_alt_matches[i] == m)
2223 			    break;
2224 			if (i < nop)
2225 			  break;
2226 		      }
2227 		    else
2228 		      did_match = true;
2229 
2230 		    this_alternative_matches = m;
2231 		    /* This can be fixed with reloads if the operand
2232 		       we are supposed to match can be fixed with
2233 		       reloads. */
2234 		    badop = false;
2235 		    this_alternative = curr_alt[m];
2236 		    COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]);
2237 		    winreg = this_alternative != NO_REGS;
2238 		    break;
2239 		  }
2240 
2241 		case 'g':
2242 		  if (MEM_P (op)
2243 		      || general_constant_p (op)
2244 		      || spilled_pseudo_p (op))
2245 		    win = true;
2246 		  cl = GENERAL_REGS;
2247 		  goto reg;
2248 
2249 		default:
2250 		  cn = lookup_constraint (p);
2251 		  switch (get_constraint_type (cn))
2252 		    {
2253 		    case CT_REGISTER:
2254 		      cl = reg_class_for_constraint (cn);
2255 		      if (cl != NO_REGS)
2256 			goto reg;
2257 		      break;
2258 
2259 		    case CT_CONST_INT:
2260 		      if (CONST_INT_P (op)
2261 			  && insn_const_int_ok_for_constraint (INTVAL (op), cn))
2262 			win = true;
2263 		      break;
2264 
2265 		    case CT_MEMORY:
2266 		      if (MEM_P (op)
2267 			  && satisfies_memory_constraint_p (op, cn))
2268 			win = true;
2269 		      else if (spilled_pseudo_p (op))
2270 			win = true;
2271 
2272 		      /* If we didn't already win, we can reload constants
2273 			 via force_const_mem or put the pseudo value into
2274 			 memory, or make other memory by reloading the
2275 			 address like for 'o'.  */
2276 		      if (CONST_POOL_OK_P (mode, op)
2277 			  || MEM_P (op) || REG_P (op)
2278 			  /* We can restore the equiv insn by a
2279 			     reload.  */
2280 			  || equiv_substition_p[nop])
2281 			badop = false;
2282 		      constmemok = true;
2283 		      offmemok = true;
2284 		      break;
2285 
2286 		    case CT_ADDRESS:
2287 		      /* An asm operand with an address constraint
2288 			 that doesn't satisfy address_operand has
2289 			 is_address cleared, so that we don't try to
2290 			 make a non-address fit.  */
2291 		      if (!curr_static_id->operand[nop].is_address)
2292 			break;
2293 		      /* If we didn't already win, we can reload the address
2294 			 into a base register.  */
2295 		      if (satisfies_address_constraint_p (op, cn))
2296 			win = true;
2297 		      cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2298 					   ADDRESS, SCRATCH);
2299 		      badop = false;
2300 		      goto reg;
2301 
2302 		    case CT_FIXED_FORM:
2303 		      if (constraint_satisfied_p (op, cn))
2304 			win = true;
2305 		      break;
2306 
2307 		    case CT_SPECIAL_MEMORY:
2308 		      if (MEM_P (op)
2309 			  && satisfies_memory_constraint_p (op, cn))
2310 			win = true;
2311 		      else if (spilled_pseudo_p (op))
2312 			win = true;
2313 		      break;
2314 		    }
2315 		  break;
2316 
2317 		reg:
2318 		  this_alternative = reg_class_subunion[this_alternative][cl];
2319 		  IOR_HARD_REG_SET (this_alternative_set,
2320 				    reg_class_contents[cl]);
2321 		  if (costly_p)
2322 		    {
2323 		      this_costly_alternative
2324 			= reg_class_subunion[this_costly_alternative][cl];
2325 		      IOR_HARD_REG_SET (this_costly_alternative_set,
2326 					reg_class_contents[cl]);
2327 		    }
2328 		  if (mode == BLKmode)
2329 		    break;
2330 		  winreg = true;
2331 		  if (REG_P (op))
2332 		    {
2333 		      if (hard_regno[nop] >= 0
2334 			  && in_hard_reg_set_p (this_alternative_set,
2335 						mode, hard_regno[nop]))
2336 			win = true;
2337 		      else if (hard_regno[nop] < 0
2338 			       && in_class_p (op, this_alternative, NULL))
2339 			win = true;
2340 		    }
2341 		  break;
2342 		}
2343 	      if (c != ' ' && c != '\t')
2344 		costly_p = c == '*';
2345 	    }
2346 	  while ((p += len), c);
2347 
2348 	  scratch_p = (operand_reg[nop] != NULL_RTX
2349 		       && lra_former_scratch_p (REGNO (operand_reg[nop])));
2350 	  /* Record which operands fit this alternative.  */
2351 	  if (win)
2352 	    {
2353 	      this_alternative_win = true;
2354 	      if (operand_reg[nop] != NULL_RTX)
2355 		{
2356 		  if (hard_regno[nop] >= 0)
2357 		    {
2358 		      if (in_hard_reg_set_p (this_costly_alternative_set,
2359 					     mode, hard_regno[nop]))
2360 			{
2361 			  if (lra_dump_file != NULL)
2362 			    fprintf (lra_dump_file,
2363 				     "            %d Costly set: reject++\n",
2364 				     nop);
2365 			  reject++;
2366 			}
2367 		    }
2368 		  else
2369 		    {
2370 		      /* Prefer won reg to spilled pseudo under other
2371 			 equal conditions for possibe inheritance.  */
2372 		      if (! scratch_p)
2373 			{
2374 			  if (lra_dump_file != NULL)
2375 			    fprintf
2376 			      (lra_dump_file,
2377 			       "            %d Non pseudo reload: reject++\n",
2378 			       nop);
2379 			  reject++;
2380 			}
2381 		      if (in_class_p (operand_reg[nop],
2382 				      this_costly_alternative, NULL))
2383 			{
2384 			  if (lra_dump_file != NULL)
2385 			    fprintf
2386 			      (lra_dump_file,
2387 			       "            %d Non pseudo costly reload:"
2388 			       " reject++\n",
2389 			       nop);
2390 			  reject++;
2391 			}
2392 		    }
2393 		  /* We simulate the behavior of old reload here.
2394 		     Although scratches need hard registers and it
2395 		     might result in spilling other pseudos, no reload
2396 		     insns are generated for the scratches.  So it
2397 		     might cost something but probably less than old
2398 		     reload pass believes.  */
2399 		  if (scratch_p)
2400 		    {
2401 		      if (lra_dump_file != NULL)
2402 			fprintf (lra_dump_file,
2403 				 "            %d Scratch win: reject+=2\n",
2404 				 nop);
2405 		      reject += 2;
2406 		    }
2407 		}
2408 	    }
2409 	  else if (did_match)
2410 	    this_alternative_match_win = true;
2411 	  else
2412 	    {
2413 	      int const_to_mem = 0;
2414 	      bool no_regs_p;
2415 
2416 	      reject += op_reject;
2417 	      /* Never do output reload of stack pointer.  It makes
2418 		 impossible to do elimination when SP is changed in
2419 		 RTL.  */
2420 	      if (op == stack_pointer_rtx && ! frame_pointer_needed
2421 		  && curr_static_id->operand[nop].type != OP_IN)
2422 		goto fail;
2423 
2424 	      /* If this alternative asks for a specific reg class, see if there
2425 		 is at least one allocatable register in that class.  */
2426 	      no_regs_p
2427 		= (this_alternative == NO_REGS
2428 		   || (hard_reg_set_subset_p
2429 		       (reg_class_contents[this_alternative],
2430 			lra_no_alloc_regs)));
2431 
2432 	      /* For asms, verify that the class for this alternative is possible
2433 		 for the mode that is specified.  */
2434 	      if (!no_regs_p && INSN_CODE (curr_insn) < 0)
2435 		{
2436 		  int i;
2437 		  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2438 		    if (targetm.hard_regno_mode_ok (i, mode)
2439 			&& in_hard_reg_set_p (reg_class_contents[this_alternative],
2440 					      mode, i))
2441 		      break;
2442 		  if (i == FIRST_PSEUDO_REGISTER)
2443 		    winreg = false;
2444 		}
2445 
2446 	      /* If this operand accepts a register, and if the
2447 		 register class has at least one allocatable register,
2448 		 then this operand can be reloaded.  */
2449 	      if (winreg && !no_regs_p)
2450 		badop = false;
2451 
2452 	      if (badop)
2453 		{
2454 		  if (lra_dump_file != NULL)
2455 		    fprintf (lra_dump_file,
2456 			     "            alt=%d: Bad operand -- refuse\n",
2457 			     nalt);
2458 		  goto fail;
2459 		}
2460 
2461 	      if (this_alternative != NO_REGS)
2462 		{
2463 		  HARD_REG_SET available_regs;
2464 
2465 		  COPY_HARD_REG_SET (available_regs,
2466 				     reg_class_contents[this_alternative]);
2467 		  AND_COMPL_HARD_REG_SET
2468 		    (available_regs,
2469 		     ira_prohibited_class_mode_regs[this_alternative][mode]);
2470 		  AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs);
2471 		  if (hard_reg_set_empty_p (available_regs))
2472 		    {
2473 		      /* There are no hard regs holding a value of given
2474 			 mode.  */
2475 		      if (offmemok)
2476 			{
2477 			  this_alternative = NO_REGS;
2478 			  if (lra_dump_file != NULL)
2479 			    fprintf (lra_dump_file,
2480 				     "            %d Using memory because of"
2481 				     " a bad mode: reject+=2\n",
2482 				     nop);
2483 			  reject += 2;
2484 			}
2485 		      else
2486 			{
2487 			  if (lra_dump_file != NULL)
2488 			    fprintf (lra_dump_file,
2489 				     "            alt=%d: Wrong mode -- refuse\n",
2490 				     nalt);
2491 			  goto fail;
2492 			}
2493 		    }
2494 		}
2495 
2496 	      /* If not assigned pseudo has a class which a subset of
2497 		 required reg class, it is a less costly alternative
2498 		 as the pseudo still can get a hard reg of necessary
2499 		 class.  */
2500 	      if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0
2501 		  && (cl = get_reg_class (REGNO (op))) != NO_REGS
2502 		  && ira_class_subset_p[this_alternative][cl])
2503 		{
2504 		  if (lra_dump_file != NULL)
2505 		    fprintf
2506 		      (lra_dump_file,
2507 		       "            %d Super set class reg: reject-=3\n", nop);
2508 		  reject -= 3;
2509 		}
2510 
2511 	      this_alternative_offmemok = offmemok;
2512 	      if (this_costly_alternative != NO_REGS)
2513 		{
2514 		  if (lra_dump_file != NULL)
2515 		    fprintf (lra_dump_file,
2516 			     "            %d Costly loser: reject++\n", nop);
2517 		  reject++;
2518 		}
2519 	      /* If the operand is dying, has a matching constraint,
2520 		 and satisfies constraints of the matched operand
2521 		 which failed to satisfy the own constraints, most probably
2522 		 the reload for this operand will be gone.  */
2523 	      if (this_alternative_matches >= 0
2524 		  && !curr_alt_win[this_alternative_matches]
2525 		  && REG_P (op)
2526 		  && find_regno_note (curr_insn, REG_DEAD, REGNO (op))
2527 		  && (hard_regno[nop] >= 0
2528 		      ? in_hard_reg_set_p (this_alternative_set,
2529 					   mode, hard_regno[nop])
2530 		      : in_class_p (op, this_alternative, NULL)))
2531 		{
2532 		  if (lra_dump_file != NULL)
2533 		    fprintf
2534 		      (lra_dump_file,
2535 		       "            %d Dying matched operand reload: reject++\n",
2536 		       nop);
2537 		  reject++;
2538 		}
2539 	      else
2540 		{
2541 		  /* Strict_low_part requires to reload the register
2542 		     not the sub-register.  In this case we should
2543 		     check that a final reload hard reg can hold the
2544 		     value mode.  */
2545 		  if (curr_static_id->operand[nop].strict_low
2546 		      && REG_P (op)
2547 		      && hard_regno[nop] < 0
2548 		      && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
2549 		      && ira_class_hard_regs_num[this_alternative] > 0
2550 		      && (!targetm.hard_regno_mode_ok
2551 			  (ira_class_hard_regs[this_alternative][0],
2552 			   GET_MODE (*curr_id->operand_loc[nop]))))
2553 		    {
2554 		      if (lra_dump_file != NULL)
2555 			fprintf
2556 			  (lra_dump_file,
2557 			   "            alt=%d: Strict low subreg reload -- refuse\n",
2558 			   nalt);
2559 		      goto fail;
2560 		    }
2561 		  losers++;
2562 		}
2563 	      if (operand_reg[nop] != NULL_RTX
2564 		  /* Output operands and matched input operands are
2565 		     not inherited.  The following conditions do not
2566 		     exactly describe the previous statement but they
2567 		     are pretty close.  */
2568 		  && curr_static_id->operand[nop].type != OP_OUT
2569 		  && (this_alternative_matches < 0
2570 		      || curr_static_id->operand[nop].type != OP_IN))
2571 		{
2572 		  int last_reload = (lra_reg_info[ORIGINAL_REGNO
2573 						  (operand_reg[nop])]
2574 				     .last_reload);
2575 
2576 		  /* The value of reload_sum has sense only if we
2577 		     process insns in their order.  It happens only on
2578 		     the first constraints sub-pass when we do most of
2579 		     reload work.  */
2580 		  if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2581 		    reload_sum += last_reload - bb_reload_num;
2582 		}
2583 	      /* If this is a constant that is reloaded into the
2584 		 desired class by copying it to memory first, count
2585 		 that as another reload.  This is consistent with
2586 		 other code and is required to avoid choosing another
2587 		 alternative when the constant is moved into memory.
2588 		 Note that the test here is precisely the same as in
2589 		 the code below that calls force_const_mem.  */
2590 	      if (CONST_POOL_OK_P (mode, op)
2591 		  && ((targetm.preferred_reload_class
2592 		       (op, this_alternative) == NO_REGS)
2593 		      || no_input_reloads_p))
2594 		{
2595 		  const_to_mem = 1;
2596 		  if (! no_regs_p)
2597 		    losers++;
2598 		}
2599 
2600 	      /* Alternative loses if it requires a type of reload not
2601 		 permitted for this insn.  We can always reload
2602 		 objects with a REG_UNUSED note.  */
2603 	      if ((curr_static_id->operand[nop].type != OP_IN
2604 		   && no_output_reloads_p
2605 		   && ! find_reg_note (curr_insn, REG_UNUSED, op))
2606 		  || (curr_static_id->operand[nop].type != OP_OUT
2607 		      && no_input_reloads_p && ! const_to_mem)
2608 		  || (this_alternative_matches >= 0
2609 		      && (no_input_reloads_p
2610 			  || (no_output_reloads_p
2611 			      && (curr_static_id->operand
2612 				  [this_alternative_matches].type != OP_IN)
2613 			      && ! find_reg_note (curr_insn, REG_UNUSED,
2614 						  no_subreg_reg_operand
2615 						  [this_alternative_matches])))))
2616 		{
2617 		  if (lra_dump_file != NULL)
2618 		    fprintf
2619 		      (lra_dump_file,
2620 		       "            alt=%d: No input/otput reload -- refuse\n",
2621 		       nalt);
2622 		  goto fail;
2623 		}
2624 
2625 	      /* Alternative loses if it required class pseudo can not
2626 		 hold value of required mode.  Such insns can be
2627 		 described by insn definitions with mode iterators.  */
2628 	      if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
2629 		  && ! hard_reg_set_empty_p (this_alternative_set)
2630 		  /* It is common practice for constraints to use a
2631 		     class which does not have actually enough regs to
2632 		     hold the value (e.g. x86 AREG for mode requiring
2633 		     more one general reg).  Therefore we have 2
2634 		     conditions to check that the reload pseudo can
2635 		     not hold the mode value.  */
2636 		  && (!targetm.hard_regno_mode_ok
2637 		      (ira_class_hard_regs[this_alternative][0],
2638 		       GET_MODE (*curr_id->operand_loc[nop])))
2639 		  /* The above condition is not enough as the first
2640 		     reg in ira_class_hard_regs can be not aligned for
2641 		     multi-words mode values.  */
2642 		  && (prohibited_class_reg_set_mode_p
2643 		      (this_alternative, this_alternative_set,
2644 		       GET_MODE (*curr_id->operand_loc[nop]))))
2645 		{
2646 		  if (lra_dump_file != NULL)
2647 		    fprintf (lra_dump_file,
2648 			     "            alt=%d: reload pseudo for op %d "
2649 			     " can not hold the mode value -- refuse\n",
2650 			     nalt, nop);
2651 		  goto fail;
2652 		}
2653 
2654 	      /* Check strong discouragement of reload of non-constant
2655 		 into class THIS_ALTERNATIVE.  */
2656 	      if (! CONSTANT_P (op) && ! no_regs_p
2657 		  && (targetm.preferred_reload_class
2658 		      (op, this_alternative) == NO_REGS
2659 		      || (curr_static_id->operand[nop].type == OP_OUT
2660 			  && (targetm.preferred_output_reload_class
2661 			      (op, this_alternative) == NO_REGS))))
2662 		{
2663 		  if (lra_dump_file != NULL)
2664 		    fprintf (lra_dump_file,
2665 			     "            %d Non-prefered reload: reject+=%d\n",
2666 			     nop, LRA_MAX_REJECT);
2667 		  reject += LRA_MAX_REJECT;
2668 		}
2669 
2670 	      if (! (MEM_P (op) && offmemok)
2671 		  && ! (const_to_mem && constmemok))
2672 		{
2673 		  /* We prefer to reload pseudos over reloading other
2674 		     things, since such reloads may be able to be
2675 		     eliminated later.  So bump REJECT in other cases.
2676 		     Don't do this in the case where we are forcing a
2677 		     constant into memory and it will then win since
2678 		     we don't want to have a different alternative
2679 		     match then.  */
2680 		  if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2681 		    {
2682 		      if (lra_dump_file != NULL)
2683 			fprintf
2684 			  (lra_dump_file,
2685 			   "            %d Non-pseudo reload: reject+=2\n",
2686 			   nop);
2687 		      reject += 2;
2688 		    }
2689 
2690 		  if (! no_regs_p)
2691 		    reload_nregs
2692 		      += ira_reg_class_max_nregs[this_alternative][mode];
2693 
2694 		  if (SMALL_REGISTER_CLASS_P (this_alternative))
2695 		    {
2696 		      if (lra_dump_file != NULL)
2697 			fprintf
2698 			  (lra_dump_file,
2699 			   "            %d Small class reload: reject+=%d\n",
2700 			   nop, LRA_LOSER_COST_FACTOR / 2);
2701 		      reject += LRA_LOSER_COST_FACTOR / 2;
2702 		    }
2703 		}
2704 
2705 	      /* We are trying to spill pseudo into memory.  It is
2706 		 usually more costly than moving to a hard register
2707 		 although it might takes the same number of
2708 		 reloads.
2709 
2710 		 Non-pseudo spill may happen also.  Suppose a target allows both
2711 		 register and memory in the operand constraint alternatives,
2712 		 then it's typical that an eliminable register has a substition
2713 		 of "base + offset" which can either be reloaded by a simple
2714 		 "new_reg <= base + offset" which will match the register
2715 		 constraint, or a similar reg addition followed by further spill
2716 		 to and reload from memory which will match the memory
2717 		 constraint, but this memory spill will be much more costly
2718 		 usually.
2719 
2720 		 Code below increases the reject for both pseudo and non-pseudo
2721 		 spill.  */
2722 	      if (no_regs_p
2723 		  && !(MEM_P (op) && offmemok)
2724 		  && !(REG_P (op) && hard_regno[nop] < 0))
2725 		{
2726 		  if (lra_dump_file != NULL)
2727 		    fprintf
2728 		      (lra_dump_file,
2729 		       "            %d Spill %spseudo into memory: reject+=3\n",
2730 		       nop, REG_P (op) ? "" : "Non-");
2731 		  reject += 3;
2732 		  if (VECTOR_MODE_P (mode))
2733 		    {
2734 		      /* Spilling vectors into memory is usually more
2735 			 costly as they contain big values.  */
2736 		      if (lra_dump_file != NULL)
2737 			fprintf
2738 			  (lra_dump_file,
2739 			   "            %d Spill vector pseudo: reject+=2\n",
2740 			   nop);
2741 		      reject += 2;
2742 		    }
2743 		}
2744 
2745 	      /* When we use an operand requiring memory in given
2746 		 alternative, the insn should write *and* read the
2747 		 value to/from memory it is costly in comparison with
2748 		 an insn alternative which does not use memory
2749 		 (e.g. register or immediate operand).  We exclude
2750 		 memory operand for such case as we can satisfy the
2751 		 memory constraints by reloading address.  */
2752 	      if (no_regs_p && offmemok && !MEM_P (op))
2753 		{
2754 		  if (lra_dump_file != NULL)
2755 		    fprintf
2756 		      (lra_dump_file,
2757 		       "            Using memory insn operand %d: reject+=3\n",
2758 		       nop);
2759 		  reject += 3;
2760 		}
2761 
2762 	      /* If reload requires moving value through secondary
2763 		 memory, it will need one more insn at least.  */
2764 	      if (this_alternative != NO_REGS
2765 		  && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
2766 		  && ((curr_static_id->operand[nop].type != OP_OUT
2767 		       && targetm.secondary_memory_needed (GET_MODE (op), cl,
2768 							   this_alternative))
2769 		      || (curr_static_id->operand[nop].type != OP_IN
2770 			  && (targetm.secondary_memory_needed
2771 			      (GET_MODE (op), this_alternative, cl)))))
2772 		losers++;
2773 
2774 	      /* Input reloads can be inherited more often than output
2775 		 reloads can be removed, so penalize output
2776 		 reloads.  */
2777 	      if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
2778 		{
2779 		  if (lra_dump_file != NULL)
2780 		    fprintf
2781 		      (lra_dump_file,
2782 		       "            %d Non input pseudo reload: reject++\n",
2783 		       nop);
2784 		  reject++;
2785 		}
2786 
2787 	      if (MEM_P (op) && offmemok)
2788 		addr_losers++;
2789 	      else if (curr_static_id->operand[nop].type == OP_INOUT)
2790 		{
2791 		  if (lra_dump_file != NULL)
2792 		    fprintf
2793 		      (lra_dump_file,
2794 		       "            %d Input/Output reload: reject+=%d\n",
2795 		       nop, LRA_LOSER_COST_FACTOR);
2796 		  reject += LRA_LOSER_COST_FACTOR;
2797 		}
2798 	    }
2799 
2800 	  if (early_clobber_p && ! scratch_p)
2801 	    {
2802 	      if (lra_dump_file != NULL)
2803 		fprintf (lra_dump_file,
2804 			 "            %d Early clobber: reject++\n", nop);
2805 	      reject++;
2806 	    }
2807 	  /* ??? We check early clobbers after processing all operands
2808 	     (see loop below) and there we update the costs more.
2809 	     Should we update the cost (may be approximately) here
2810 	     because of early clobber register reloads or it is a rare
2811 	     or non-important thing to be worth to do it.  */
2812 	  overall = (losers * LRA_LOSER_COST_FACTOR + reject
2813 		     - (addr_losers == losers ? static_reject : 0));
2814 	  if ((best_losers == 0 || losers != 0) && best_overall < overall)
2815             {
2816               if (lra_dump_file != NULL)
2817 		fprintf (lra_dump_file,
2818 			 "            alt=%d,overall=%d,losers=%d -- refuse\n",
2819 			 nalt, overall, losers);
2820               goto fail;
2821             }
2822 
2823 	  if (update_and_check_small_class_inputs (nop, this_alternative))
2824 	    {
2825 	      if (lra_dump_file != NULL)
2826 		fprintf (lra_dump_file,
2827 			 "            alt=%d, not enough small class regs -- refuse\n",
2828 			 nalt);
2829 	      goto fail;
2830 	    }
2831 	  curr_alt[nop] = this_alternative;
2832 	  COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set);
2833 	  curr_alt_win[nop] = this_alternative_win;
2834 	  curr_alt_match_win[nop] = this_alternative_match_win;
2835 	  curr_alt_offmemok[nop] = this_alternative_offmemok;
2836 	  curr_alt_matches[nop] = this_alternative_matches;
2837 
2838 	  if (this_alternative_matches >= 0
2839 	      && !did_match && !this_alternative_win)
2840 	    curr_alt_win[this_alternative_matches] = false;
2841 
2842 	  if (early_clobber_p && operand_reg[nop] != NULL_RTX)
2843 	    early_clobbered_nops[early_clobbered_regs_num++] = nop;
2844 	}
2845 
2846       if (curr_insn_set != NULL_RTX && n_operands == 2
2847 	  /* Prevent processing non-move insns.  */
2848 	  && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
2849 	      || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
2850 	  && ((! curr_alt_win[0] && ! curr_alt_win[1]
2851 	       && REG_P (no_subreg_reg_operand[0])
2852 	       && REG_P (no_subreg_reg_operand[1])
2853 	       && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2854 		   || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
2855 	      || (! curr_alt_win[0] && curr_alt_win[1]
2856 		  && REG_P (no_subreg_reg_operand[1])
2857 		  /* Check that we reload memory not the memory
2858 		     address.  */
2859 		  && ! (curr_alt_offmemok[0]
2860 			&& MEM_P (no_subreg_reg_operand[0]))
2861 		  && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
2862 	      || (curr_alt_win[0] && ! curr_alt_win[1]
2863 		  && REG_P (no_subreg_reg_operand[0])
2864 		  /* Check that we reload memory not the memory
2865 		     address.  */
2866 		  && ! (curr_alt_offmemok[1]
2867 			&& MEM_P (no_subreg_reg_operand[1]))
2868 		  && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2869 		  && (! CONST_POOL_OK_P (curr_operand_mode[1],
2870 					 no_subreg_reg_operand[1])
2871 		      || (targetm.preferred_reload_class
2872 			  (no_subreg_reg_operand[1],
2873 			   (enum reg_class) curr_alt[1]) != NO_REGS))
2874 		  /* If it is a result of recent elimination in move
2875 		     insn we can transform it into an add still by
2876 		     using this alternative.  */
2877 		  && GET_CODE (no_subreg_reg_operand[1]) != PLUS
2878 		  /* Likewise if the source has been replaced with an
2879 		     equivalent value.  This only happens once -- the reload
2880 		     will use the equivalent value instead of the register it
2881 		     replaces -- so there should be no danger of cycling.  */
2882 		  && !equiv_substition_p[1])))
2883 	{
2884 	  /* We have a move insn and a new reload insn will be similar
2885 	     to the current insn.  We should avoid such situation as
2886 	     it results in LRA cycling.  */
2887 	  if (lra_dump_file != NULL)
2888 	    fprintf (lra_dump_file,
2889 		     "            Cycle danger: overall += LRA_MAX_REJECT\n");
2890 	  overall += LRA_MAX_REJECT;
2891 	}
2892       ok_p = true;
2893       curr_alt_dont_inherit_ops_num = 0;
2894       for (nop = 0; nop < early_clobbered_regs_num; nop++)
2895 	{
2896 	  int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
2897 	  HARD_REG_SET temp_set;
2898 
2899 	  i = early_clobbered_nops[nop];
2900 	  if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
2901 	      || hard_regno[i] < 0)
2902 	    continue;
2903 	  lra_assert (operand_reg[i] != NULL_RTX);
2904 	  clobbered_hard_regno = hard_regno[i];
2905 	  CLEAR_HARD_REG_SET (temp_set);
2906 	  add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno);
2907 	  first_conflict_j = last_conflict_j = -1;
2908 	  for (j = 0; j < n_operands; j++)
2909 	    if (j == i
2910 		/* We don't want process insides of match_operator and
2911 		   match_parallel because otherwise we would process
2912 		   their operands once again generating a wrong
2913 		   code.  */
2914 		|| curr_static_id->operand[j].is_operator)
2915 	      continue;
2916 	    else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
2917 		     || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
2918 	      continue;
2919 	    /* If we don't reload j-th operand, check conflicts.  */
2920 	    else if ((curr_alt_win[j] || curr_alt_match_win[j])
2921 		     && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
2922 	      {
2923 		if (first_conflict_j < 0)
2924 		  first_conflict_j = j;
2925 		last_conflict_j = j;
2926 	      }
2927 	  if (last_conflict_j < 0)
2928 	    continue;
2929 	  /* If earlyclobber operand conflicts with another
2930 	     non-matching operand which is actually the same register
2931 	     as the earlyclobber operand, it is better to reload the
2932 	     another operand as an operand matching the earlyclobber
2933 	     operand can be also the same.  */
2934 	  if (first_conflict_j == last_conflict_j
2935 	      && operand_reg[last_conflict_j] != NULL_RTX
2936 	      && ! curr_alt_match_win[last_conflict_j]
2937 	      && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j]))
2938 	    {
2939 	      curr_alt_win[last_conflict_j] = false;
2940 	      curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
2941 		= last_conflict_j;
2942 	      losers++;
2943 	      /* Early clobber was already reflected in REJECT. */
2944 	      lra_assert (reject > 0);
2945 	      if (lra_dump_file != NULL)
2946 		fprintf
2947 		  (lra_dump_file,
2948 		   "            %d Conflict early clobber reload: reject--\n",
2949 		   i);
2950 	      reject--;
2951 	      overall += LRA_LOSER_COST_FACTOR - 1;
2952 	    }
2953 	  else
2954 	    {
2955 	      /* We need to reload early clobbered register and the
2956 		 matched registers.  */
2957 	      for (j = 0; j < n_operands; j++)
2958 		if (curr_alt_matches[j] == i)
2959 		  {
2960 		    curr_alt_match_win[j] = false;
2961 		    losers++;
2962 		    overall += LRA_LOSER_COST_FACTOR;
2963 		  }
2964 	      if (! curr_alt_match_win[i])
2965 		curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
2966 	      else
2967 		{
2968 		  /* Remember pseudos used for match reloads are never
2969 		     inherited.  */
2970 		  lra_assert (curr_alt_matches[i] >= 0);
2971 		  curr_alt_win[curr_alt_matches[i]] = false;
2972 		}
2973 	      curr_alt_win[i] = curr_alt_match_win[i] = false;
2974 	      losers++;
2975 	      /* Early clobber was already reflected in REJECT. */
2976 	      lra_assert (reject > 0);
2977 	      if (lra_dump_file != NULL)
2978 		fprintf
2979 		  (lra_dump_file,
2980 		   "            %d Matched conflict early clobber reloads: "
2981 		   "reject--\n",
2982 		   i);
2983 	      reject--;
2984 	      overall += LRA_LOSER_COST_FACTOR - 1;
2985 	    }
2986 	}
2987       if (lra_dump_file != NULL)
2988 	fprintf (lra_dump_file, "          alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2989 		 nalt, overall, losers, reload_nregs);
2990 
2991       /* If this alternative can be made to work by reloading, and it
2992 	 needs less reloading than the others checked so far, record
2993 	 it as the chosen goal for reloading.  */
2994       if ((best_losers != 0 && losers == 0)
2995 	  || (((best_losers == 0 && losers == 0)
2996 	       || (best_losers != 0 && losers != 0))
2997 	      && (best_overall > overall
2998 		  || (best_overall == overall
2999 		      /* If the cost of the reloads is the same,
3000 			 prefer alternative which requires minimal
3001 			 number of reload regs.  */
3002 		      && (reload_nregs < best_reload_nregs
3003 			  || (reload_nregs == best_reload_nregs
3004 			      && (best_reload_sum < reload_sum
3005 				  || (best_reload_sum == reload_sum
3006 				      && nalt < goal_alt_number))))))))
3007 	{
3008 	  for (nop = 0; nop < n_operands; nop++)
3009 	    {
3010 	      goal_alt_win[nop] = curr_alt_win[nop];
3011 	      goal_alt_match_win[nop] = curr_alt_match_win[nop];
3012 	      goal_alt_matches[nop] = curr_alt_matches[nop];
3013 	      goal_alt[nop] = curr_alt[nop];
3014 	      goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
3015 	    }
3016 	  goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
3017 	  for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
3018 	    goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
3019 	  goal_alt_swapped = curr_swapped;
3020 	  best_overall = overall;
3021 	  best_losers = losers;
3022 	  best_reload_nregs = reload_nregs;
3023 	  best_reload_sum = reload_sum;
3024 	  goal_alt_number = nalt;
3025 	}
3026       if (losers == 0)
3027 	/* Everything is satisfied.  Do not process alternatives
3028 	   anymore.  */
3029 	break;
3030     fail:
3031       ;
3032     }
3033   return ok_p;
3034 }
3035 
3036 /* Make reload base reg from address AD.  */
3037 static rtx
3038 base_to_reg (struct address_info *ad)
3039 {
3040   enum reg_class cl;
3041   int code = -1;
3042   rtx new_inner = NULL_RTX;
3043   rtx new_reg = NULL_RTX;
3044   rtx_insn *insn;
3045   rtx_insn *last_insn = get_last_insn();
3046 
3047   lra_assert (ad->disp == ad->disp_term);
3048   cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3049                        get_index_code (ad));
3050   new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX,
3051                                 cl, "base");
3052   new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg,
3053                                    ad->disp_term == NULL
3054                                    ? const0_rtx
3055                                    : *ad->disp_term);
3056   if (!valid_address_p (ad->mode, new_inner, ad->as))
3057     return NULL_RTX;
3058   insn = emit_insn (gen_rtx_SET (new_reg, *ad->base));
3059   code = recog_memoized (insn);
3060   if (code < 0)
3061     {
3062       delete_insns_since (last_insn);
3063       return NULL_RTX;
3064     }
3065 
3066   return new_inner;
3067 }
3068 
3069 /* Make reload base reg + DISP from address AD.  Return the new pseudo.  */
3070 static rtx
3071 base_plus_disp_to_reg (struct address_info *ad, rtx disp)
3072 {
3073   enum reg_class cl;
3074   rtx new_reg;
3075 
3076   lra_assert (ad->base == ad->base_term);
3077   cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3078 		       get_index_code (ad));
3079   new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
3080 				cl, "base + disp");
3081   lra_emit_add (new_reg, *ad->base_term, disp);
3082   return new_reg;
3083 }
3084 
3085 /* Make reload of index part of address AD.  Return the new
3086    pseudo.  */
3087 static rtx
3088 index_part_to_reg (struct address_info *ad)
3089 {
3090   rtx new_reg;
3091 
3092   new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX,
3093 				INDEX_REG_CLASS, "index term");
3094   expand_mult (GET_MODE (*ad->index), *ad->index_term,
3095 	       GEN_INT (get_index_scale (ad)), new_reg, 1);
3096   return new_reg;
3097 }
3098 
3099 /* Return true if we can add a displacement to address AD, even if that
3100    makes the address invalid.  The fix-up code requires any new address
3101    to be the sum of the BASE_TERM, INDEX and DISP_TERM fields.  */
3102 static bool
3103 can_add_disp_p (struct address_info *ad)
3104 {
3105   return (!ad->autoinc_p
3106 	  && ad->segment == NULL
3107 	  && ad->base == ad->base_term
3108 	  && ad->disp == ad->disp_term);
3109 }
3110 
3111 /* Make equiv substitution in address AD.  Return true if a substitution
3112    was made.  */
3113 static bool
3114 equiv_address_substitution (struct address_info *ad)
3115 {
3116   rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
3117   poly_int64 disp;
3118   HOST_WIDE_INT scale;
3119   bool change_p;
3120 
3121   base_term = strip_subreg (ad->base_term);
3122   if (base_term == NULL)
3123     base_reg = new_base_reg = NULL_RTX;
3124   else
3125     {
3126       base_reg = *base_term;
3127       new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
3128     }
3129   index_term = strip_subreg (ad->index_term);
3130   if (index_term == NULL)
3131     index_reg = new_index_reg = NULL_RTX;
3132   else
3133     {
3134       index_reg = *index_term;
3135       new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
3136     }
3137   if (base_reg == new_base_reg && index_reg == new_index_reg)
3138     return false;
3139   disp = 0;
3140   change_p = false;
3141   if (lra_dump_file != NULL)
3142     {
3143       fprintf (lra_dump_file, "Changing address in insn %d ",
3144 	       INSN_UID (curr_insn));
3145       dump_value_slim (lra_dump_file, *ad->outer, 1);
3146     }
3147   if (base_reg != new_base_reg)
3148     {
3149       poly_int64 offset;
3150       if (REG_P (new_base_reg))
3151 	{
3152 	  *base_term = new_base_reg;
3153 	  change_p = true;
3154 	}
3155       else if (GET_CODE (new_base_reg) == PLUS
3156 	       && REG_P (XEXP (new_base_reg, 0))
3157 	       && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset)
3158 	       && can_add_disp_p (ad))
3159 	{
3160 	  disp += offset;
3161 	  *base_term = XEXP (new_base_reg, 0);
3162 	  change_p = true;
3163 	}
3164       if (ad->base_term2 != NULL)
3165 	*ad->base_term2 = *ad->base_term;
3166     }
3167   if (index_reg != new_index_reg)
3168     {
3169       poly_int64 offset;
3170       if (REG_P (new_index_reg))
3171 	{
3172 	  *index_term = new_index_reg;
3173 	  change_p = true;
3174 	}
3175       else if (GET_CODE (new_index_reg) == PLUS
3176 	       && REG_P (XEXP (new_index_reg, 0))
3177 	       && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset)
3178 	       && can_add_disp_p (ad)
3179 	       && (scale = get_index_scale (ad)))
3180 	{
3181 	  disp += offset * scale;
3182 	  *index_term = XEXP (new_index_reg, 0);
3183 	  change_p = true;
3184 	}
3185     }
3186   if (maybe_ne (disp, 0))
3187     {
3188       if (ad->disp != NULL)
3189 	*ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp);
3190       else
3191 	{
3192 	  *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp);
3193 	  update_address (ad);
3194 	}
3195       change_p = true;
3196     }
3197   if (lra_dump_file != NULL)
3198     {
3199       if (! change_p)
3200 	fprintf (lra_dump_file, " -- no change\n");
3201       else
3202 	{
3203 	  fprintf (lra_dump_file, " on equiv ");
3204 	  dump_value_slim (lra_dump_file, *ad->outer, 1);
3205 	  fprintf (lra_dump_file, "\n");
3206 	}
3207     }
3208   return change_p;
3209 }
3210 
3211 /* Major function to make reloads for an address in operand NOP or
3212    check its correctness (If CHECK_ONLY_P is true). The supported
3213    cases are:
3214 
3215    1) an address that existed before LRA started, at which point it
3216    must have been valid.  These addresses are subject to elimination
3217    and may have become invalid due to the elimination offset being out
3218    of range.
3219 
3220    2) an address created by forcing a constant to memory
3221    (force_const_to_mem).  The initial form of these addresses might
3222    not be valid, and it is this function's job to make them valid.
3223 
3224    3) a frame address formed from a register and a (possibly zero)
3225    constant offset.  As above, these addresses might not be valid and
3226    this function must make them so.
3227 
3228    Add reloads to the lists *BEFORE and *AFTER.  We might need to add
3229    reloads to *AFTER because of inc/dec, {pre, post} modify in the
3230    address.  Return true for any RTL change.
3231 
3232    The function is a helper function which does not produce all
3233    transformations (when CHECK_ONLY_P is false) which can be
3234    necessary.  It does just basic steps.  To do all necessary
3235    transformations use function process_address.  */
3236 static bool
3237 process_address_1 (int nop, bool check_only_p,
3238 		   rtx_insn **before, rtx_insn **after)
3239 {
3240   struct address_info ad;
3241   rtx new_reg;
3242   HOST_WIDE_INT scale;
3243   rtx op = *curr_id->operand_loc[nop];
3244   const char *constraint = curr_static_id->operand[nop].constraint;
3245   enum constraint_num cn = lookup_constraint (constraint);
3246   bool change_p = false;
3247 
3248   if (MEM_P (op)
3249       && GET_MODE (op) == BLKmode
3250       && GET_CODE (XEXP (op, 0)) == SCRATCH)
3251     return false;
3252 
3253   if (insn_extra_address_constraint (cn)
3254       /* When we find an asm operand with an address constraint that
3255 	 doesn't satisfy address_operand to begin with, we clear
3256 	 is_address, so that we don't try to make a non-address fit.
3257 	 If the asm statement got this far, it's because other
3258 	 constraints are available, and we'll use them, disregarding
3259 	 the unsatisfiable address ones.  */
3260       && curr_static_id->operand[nop].is_address)
3261     decompose_lea_address (&ad, curr_id->operand_loc[nop]);
3262   /* Do not attempt to decompose arbitrary addresses generated by combine
3263      for asm operands with loose constraints, e.g 'X'.  */
3264   else if (MEM_P (op)
3265 	   && !(INSN_CODE (curr_insn) < 0
3266 		&& get_constraint_type (cn) == CT_FIXED_FORM
3267 	        && constraint_satisfied_p (op, cn)))
3268     decompose_mem_address (&ad, op);
3269   else if (GET_CODE (op) == SUBREG
3270 	   && MEM_P (SUBREG_REG (op)))
3271     decompose_mem_address (&ad, SUBREG_REG (op));
3272   else
3273     return false;
3274   /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3275      index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3276      when INDEX_REG_CLASS is a single register class.  */
3277   if (ad.base_term != NULL
3278       && ad.index_term != NULL
3279       && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1
3280       && REG_P (*ad.base_term)
3281       && REG_P (*ad.index_term)
3282       && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL)
3283       && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL))
3284     {
3285       std::swap (ad.base, ad.index);
3286       std::swap (ad.base_term, ad.index_term);
3287     }
3288   if (! check_only_p)
3289     change_p = equiv_address_substitution (&ad);
3290   if (ad.base_term != NULL
3291       && (process_addr_reg
3292 	  (ad.base_term, check_only_p, before,
3293 	   (ad.autoinc_p
3294 	    && !(REG_P (*ad.base_term)
3295 		 && find_regno_note (curr_insn, REG_DEAD,
3296 				     REGNO (*ad.base_term)) != NULL_RTX)
3297 	    ? after : NULL),
3298 	   base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3299 			   get_index_code (&ad)))))
3300     {
3301       change_p = true;
3302       if (ad.base_term2 != NULL)
3303 	*ad.base_term2 = *ad.base_term;
3304     }
3305   if (ad.index_term != NULL
3306       && process_addr_reg (ad.index_term, check_only_p,
3307 			   before, NULL, INDEX_REG_CLASS))
3308     change_p = true;
3309 
3310   /* Target hooks sometimes don't treat extra-constraint addresses as
3311      legitimate address_operands, so handle them specially.  */
3312   if (insn_extra_address_constraint (cn)
3313       && satisfies_address_constraint_p (&ad, cn))
3314     return change_p;
3315 
3316   if (check_only_p)
3317     return change_p;
3318 
3319   /* There are three cases where the shape of *AD.INNER may now be invalid:
3320 
3321      1) the original address was valid, but either elimination or
3322      equiv_address_substitution was applied and that made
3323      the address invalid.
3324 
3325      2) the address is an invalid symbolic address created by
3326      force_const_to_mem.
3327 
3328      3) the address is a frame address with an invalid offset.
3329 
3330      4) the address is a frame address with an invalid base.
3331 
3332      All these cases involve a non-autoinc address, so there is no
3333      point revalidating other types.  */
3334   if (ad.autoinc_p || valid_address_p (&ad))
3335     return change_p;
3336 
3337   /* Any index existed before LRA started, so we can assume that the
3338      presence and shape of the index is valid.  */
3339   push_to_sequence (*before);
3340   lra_assert (ad.disp == ad.disp_term);
3341   if (ad.base == NULL)
3342     {
3343       if (ad.index == NULL)
3344 	{
3345 	  rtx_insn *insn;
3346 	  rtx_insn *last = get_last_insn ();
3347 	  int code = -1;
3348 	  enum reg_class cl = base_reg_class (ad.mode, ad.as,
3349 					      SCRATCH, SCRATCH);
3350 	  rtx addr = *ad.inner;
3351 
3352 	  new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3353 	  if (HAVE_lo_sum)
3354 	    {
3355 	      /* addr => lo_sum (new_base, addr), case (2) above.  */
3356 	      insn = emit_insn (gen_rtx_SET
3357 				(new_reg,
3358 				 gen_rtx_HIGH (Pmode, copy_rtx (addr))));
3359 	      code = recog_memoized (insn);
3360 	      if (code >= 0)
3361 		{
3362 		  *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
3363 		  if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3364 		    {
3365 		      /* Try to put lo_sum into register.  */
3366 		      insn = emit_insn (gen_rtx_SET
3367 					(new_reg,
3368 					 gen_rtx_LO_SUM (Pmode, new_reg, addr)));
3369 		      code = recog_memoized (insn);
3370 		      if (code >= 0)
3371 			{
3372 			  *ad.inner = new_reg;
3373 			  if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3374 			    {
3375 			      *ad.inner = addr;
3376 			      code = -1;
3377 			    }
3378 			}
3379 
3380 		    }
3381 		}
3382 	      if (code < 0)
3383 		delete_insns_since (last);
3384 	    }
3385 
3386 	  if (code < 0)
3387 	    {
3388 	      /* addr => new_base, case (2) above.  */
3389 	      lra_emit_move (new_reg, addr);
3390 
3391 	      for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last);
3392 		   insn != NULL_RTX;
3393 		   insn = NEXT_INSN (insn))
3394 		if (recog_memoized (insn) < 0)
3395 		  break;
3396 	      if (insn != NULL_RTX)
3397 		{
3398 		  /* Do nothing if we cannot generate right insns.
3399 		     This is analogous to reload pass behavior.  */
3400 		  delete_insns_since (last);
3401 		  end_sequence ();
3402 		  return false;
3403 		}
3404 	      *ad.inner = new_reg;
3405 	    }
3406 	}
3407       else
3408 	{
3409 	  /* index * scale + disp => new base + index * scale,
3410 	     case (1) above.  */
3411 	  enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
3412 					      GET_CODE (*ad.index));
3413 
3414 	  lra_assert (INDEX_REG_CLASS != NO_REGS);
3415 	  new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp");
3416 	  lra_emit_move (new_reg, *ad.disp);
3417 	  *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3418 					   new_reg, *ad.index);
3419 	}
3420     }
3421   else if (ad.index == NULL)
3422     {
3423       int regno;
3424       enum reg_class cl;
3425       rtx set;
3426       rtx_insn *insns, *last_insn;
3427       /* Try to reload base into register only if the base is invalid
3428          for the address but with valid offset, case (4) above.  */
3429       start_sequence ();
3430       new_reg = base_to_reg (&ad);
3431 
3432       /* base + disp => new base, cases (1) and (3) above.  */
3433       /* Another option would be to reload the displacement into an
3434 	 index register.  However, postreload has code to optimize
3435 	 address reloads that have the same base and different
3436 	 displacements, so reloading into an index register would
3437 	 not necessarily be a win.  */
3438       if (new_reg == NULL_RTX)
3439 	{
3440 	  /* See if the target can split the displacement into a
3441 	     legitimate new displacement from a local anchor.  */
3442 	  gcc_assert (ad.disp == ad.disp_term);
3443 	  poly_int64 orig_offset;
3444 	  rtx offset1, offset2;
3445 	  if (poly_int_rtx_p (*ad.disp, &orig_offset)
3446 	      && targetm.legitimize_address_displacement (&offset1, &offset2,
3447 							  orig_offset,
3448 							  ad.mode))
3449 	    {
3450 	      new_reg = base_plus_disp_to_reg (&ad, offset1);
3451 	      new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2);
3452 	    }
3453 	  else
3454 	    new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3455 	}
3456       insns = get_insns ();
3457       last_insn = get_last_insn ();
3458       /* If we generated at least two insns, try last insn source as
3459 	 an address.  If we succeed, we generate one less insn.  */
3460       if (REG_P (new_reg)
3461 	  && last_insn != insns
3462 	  && (set = single_set (last_insn)) != NULL_RTX
3463 	  && GET_CODE (SET_SRC (set)) == PLUS
3464 	  && REG_P (XEXP (SET_SRC (set), 0))
3465 	  && CONSTANT_P (XEXP (SET_SRC (set), 1)))
3466 	{
3467 	  *ad.inner = SET_SRC (set);
3468 	  if (valid_address_p (ad.mode, *ad.outer, ad.as))
3469 	    {
3470 	      *ad.base_term = XEXP (SET_SRC (set), 0);
3471 	      *ad.disp_term = XEXP (SET_SRC (set), 1);
3472 	      cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3473 				   get_index_code (&ad));
3474 	      regno = REGNO (*ad.base_term);
3475 	      if (regno >= FIRST_PSEUDO_REGISTER
3476 		  && cl != lra_get_allocno_class (regno))
3477 		lra_change_class (regno, cl, "      Change to", true);
3478 	      new_reg = SET_SRC (set);
3479 	      delete_insns_since (PREV_INSN (last_insn));
3480 	    }
3481 	}
3482       end_sequence ();
3483       emit_insn (insns);
3484       *ad.inner = new_reg;
3485     }
3486   else if (ad.disp_term != NULL)
3487     {
3488       /* base + scale * index + disp => new base + scale * index,
3489 	 case (1) above.  */
3490       gcc_assert (ad.disp == ad.disp_term);
3491       new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3492       *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3493 				       new_reg, *ad.index);
3494     }
3495   else if ((scale = get_index_scale (&ad)) == 1)
3496     {
3497       /* The last transformation to one reg will be made in
3498 	 curr_insn_transform function.  */
3499       end_sequence ();
3500       return false;
3501     }
3502   else if (scale != 0)
3503     {
3504       /* base + scale * index => base + new_reg,
3505 	 case (1) above.
3506       Index part of address may become invalid.  For example, we
3507       changed pseudo on the equivalent memory and a subreg of the
3508       pseudo onto the memory of different mode for which the scale is
3509       prohibitted.  */
3510       new_reg = index_part_to_reg (&ad);
3511       *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3512 				       *ad.base_term, new_reg);
3513     }
3514   else
3515     {
3516       enum reg_class cl = base_reg_class (ad.mode, ad.as,
3517 					  SCRATCH, SCRATCH);
3518       rtx addr = *ad.inner;
3519 
3520       new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3521       /* addr => new_base.  */
3522       lra_emit_move (new_reg, addr);
3523       *ad.inner = new_reg;
3524     }
3525   *before = get_insns ();
3526   end_sequence ();
3527   return true;
3528 }
3529 
3530 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3531    Use process_address_1 as a helper function.  Return true for any
3532    RTL changes.
3533 
3534    If CHECK_ONLY_P is true, just check address correctness.  Return
3535    false if the address correct.  */
3536 static bool
3537 process_address (int nop, bool check_only_p,
3538 		 rtx_insn **before, rtx_insn **after)
3539 {
3540   bool res = false;
3541 
3542   while (process_address_1 (nop, check_only_p, before, after))
3543     {
3544       if (check_only_p)
3545 	return true;
3546       res = true;
3547     }
3548   return res;
3549 }
3550 
3551 /* Emit insns to reload VALUE into a new register.  VALUE is an
3552    auto-increment or auto-decrement RTX whose operand is a register or
3553    memory location; so reloading involves incrementing that location.
3554    IN is either identical to VALUE, or some cheaper place to reload
3555    value being incremented/decremented from.
3556 
3557    INC_AMOUNT is the number to increment or decrement by (always
3558    positive and ignored for POST_MODIFY/PRE_MODIFY).
3559 
3560    Return pseudo containing the result.	 */
3561 static rtx
3562 emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount)
3563 {
3564   /* REG or MEM to be copied and incremented.  */
3565   rtx incloc = XEXP (value, 0);
3566   /* Nonzero if increment after copying.  */
3567   int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
3568 	      || GET_CODE (value) == POST_MODIFY);
3569   rtx_insn *last;
3570   rtx inc;
3571   rtx_insn *add_insn;
3572   int code;
3573   rtx real_in = in == value ? incloc : in;
3574   rtx result;
3575   bool plus_p = true;
3576 
3577   if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
3578     {
3579       lra_assert (GET_CODE (XEXP (value, 1)) == PLUS
3580 		  || GET_CODE (XEXP (value, 1)) == MINUS);
3581       lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0)));
3582       plus_p = GET_CODE (XEXP (value, 1)) == PLUS;
3583       inc = XEXP (XEXP (value, 1), 1);
3584     }
3585   else
3586     {
3587       if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
3588 	inc_amount = -inc_amount;
3589 
3590       inc = gen_int_mode (inc_amount, GET_MODE (value));
3591     }
3592 
3593   if (! post && REG_P (incloc))
3594     result = incloc;
3595   else
3596     result = lra_create_new_reg (GET_MODE (value), value, new_rclass,
3597 				 "INC/DEC result");
3598 
3599   if (real_in != result)
3600     {
3601       /* First copy the location to the result register.  */
3602       lra_assert (REG_P (result));
3603       emit_insn (gen_move_insn (result, real_in));
3604     }
3605 
3606   /* We suppose that there are insns to add/sub with the constant
3607      increment permitted in {PRE/POST)_{DEC/INC/MODIFY}.  At least the
3608      old reload worked with this assumption.  If the assumption
3609      becomes wrong, we should use approach in function
3610      base_plus_disp_to_reg.  */
3611   if (in == value)
3612     {
3613       /* See if we can directly increment INCLOC.  */
3614       last = get_last_insn ();
3615       add_insn = emit_insn (plus_p
3616 			    ? gen_add2_insn (incloc, inc)
3617 			    : gen_sub2_insn (incloc, inc));
3618 
3619       code = recog_memoized (add_insn);
3620       if (code >= 0)
3621 	{
3622 	  if (! post && result != incloc)
3623 	    emit_insn (gen_move_insn (result, incloc));
3624 	  return result;
3625 	}
3626       delete_insns_since (last);
3627     }
3628 
3629   /* If couldn't do the increment directly, must increment in RESULT.
3630      The way we do this depends on whether this is pre- or
3631      post-increment.  For pre-increment, copy INCLOC to the reload
3632      register, increment it there, then save back.  */
3633   if (! post)
3634     {
3635       if (real_in != result)
3636 	emit_insn (gen_move_insn (result, real_in));
3637       if (plus_p)
3638 	emit_insn (gen_add2_insn (result, inc));
3639       else
3640 	emit_insn (gen_sub2_insn (result, inc));
3641       if (result != incloc)
3642 	emit_insn (gen_move_insn (incloc, result));
3643     }
3644   else
3645     {
3646       /* Post-increment.
3647 
3648 	 Because this might be a jump insn or a compare, and because
3649 	 RESULT may not be available after the insn in an input
3650 	 reload, we must do the incrementing before the insn being
3651 	 reloaded for.
3652 
3653 	 We have already copied IN to RESULT.  Increment the copy in
3654 	 RESULT, save that back, then decrement RESULT so it has
3655 	 the original value.  */
3656       if (plus_p)
3657 	emit_insn (gen_add2_insn (result, inc));
3658       else
3659 	emit_insn (gen_sub2_insn (result, inc));
3660       emit_insn (gen_move_insn (incloc, result));
3661       /* Restore non-modified value for the result.  We prefer this
3662 	 way because it does not require an additional hard
3663 	 register.  */
3664       if (plus_p)
3665 	{
3666 	  poly_int64 offset;
3667 	  if (poly_int_rtx_p (inc, &offset))
3668 	    emit_insn (gen_add2_insn (result,
3669 				      gen_int_mode (-offset,
3670 						    GET_MODE (result))));
3671 	  else
3672 	    emit_insn (gen_sub2_insn (result, inc));
3673 	}
3674       else
3675 	emit_insn (gen_add2_insn (result, inc));
3676     }
3677   return result;
3678 }
3679 
3680 /* Return true if the current move insn does not need processing as we
3681    already know that it satisfies its constraints.  */
3682 static bool
3683 simple_move_p (void)
3684 {
3685   rtx dest, src;
3686   enum reg_class dclass, sclass;
3687 
3688   lra_assert (curr_insn_set != NULL_RTX);
3689   dest = SET_DEST (curr_insn_set);
3690   src = SET_SRC (curr_insn_set);
3691 
3692   /* If the instruction has multiple sets we need to process it even if it
3693      is single_set.  This can happen if one or more of the SETs are dead.
3694      See PR73650.  */
3695   if (multiple_sets (curr_insn))
3696     return false;
3697 
3698   return ((dclass = get_op_class (dest)) != NO_REGS
3699 	  && (sclass = get_op_class (src)) != NO_REGS
3700 	  /* The backend guarantees that register moves of cost 2
3701 	     never need reloads.  */
3702 	  && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2);
3703  }
3704 
3705 /* Swap operands NOP and NOP + 1. */
3706 static inline void
3707 swap_operands (int nop)
3708 {
3709   std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]);
3710   std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]);
3711   std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]);
3712   std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]);
3713   /* Swap the duplicates too.  */
3714   lra_update_dup (curr_id, nop);
3715   lra_update_dup (curr_id, nop + 1);
3716 }
3717 
3718 /* Main entry point of the constraint code: search the body of the
3719    current insn to choose the best alternative.  It is mimicking insn
3720    alternative cost calculation model of former reload pass.  That is
3721    because machine descriptions were written to use this model.  This
3722    model can be changed in future.  Make commutative operand exchange
3723    if it is chosen.
3724 
3725    if CHECK_ONLY_P is false, do RTL changes to satisfy the
3726    constraints.  Return true if any change happened during function
3727    call.
3728 
3729    If CHECK_ONLY_P is true then don't do any transformation.  Just
3730    check that the insn satisfies all constraints.  If the insn does
3731    not satisfy any constraint, return true.  */
3732 static bool
3733 curr_insn_transform (bool check_only_p)
3734 {
3735   int i, j, k;
3736   int n_operands;
3737   int n_alternatives;
3738   int n_outputs;
3739   int commutative;
3740   signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
3741   signed char match_inputs[MAX_RECOG_OPERANDS + 1];
3742   signed char outputs[MAX_RECOG_OPERANDS + 1];
3743   rtx_insn *before, *after;
3744   bool alt_p = false;
3745   /* Flag that the insn has been changed through a transformation.  */
3746   bool change_p;
3747   bool sec_mem_p;
3748   bool use_sec_mem_p;
3749   int max_regno_before;
3750   int reused_alternative_num;
3751 
3752   curr_insn_set = single_set (curr_insn);
3753   if (curr_insn_set != NULL_RTX && simple_move_p ())
3754     {
3755       /* We assume that the corresponding insn alternative has no
3756 	 earlier clobbers.  If it is not the case, don't define move
3757 	 cost equal to 2 for the corresponding register classes.  */
3758       lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT);
3759       return false;
3760     }
3761 
3762   no_input_reloads_p = no_output_reloads_p = false;
3763   goal_alt_number = -1;
3764   change_p = sec_mem_p = false;
3765   /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3766      reloads; neither are insns that SET cc0.  Insns that use CC0 are
3767      not allowed to have any input reloads.  */
3768   if (JUMP_P (curr_insn) || CALL_P (curr_insn))
3769     no_output_reloads_p = true;
3770 
3771   if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn)))
3772     no_input_reloads_p = true;
3773   if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn)))
3774     no_output_reloads_p = true;
3775 
3776   n_operands = curr_static_id->n_operands;
3777   n_alternatives = curr_static_id->n_alternatives;
3778 
3779   /* Just return "no reloads" if insn has no operands with
3780      constraints.  */
3781   if (n_operands == 0 || n_alternatives == 0)
3782     return false;
3783 
3784   max_regno_before = max_reg_num ();
3785 
3786   for (i = 0; i < n_operands; i++)
3787     {
3788       goal_alt_matched[i][0] = -1;
3789       goal_alt_matches[i] = -1;
3790     }
3791 
3792   commutative = curr_static_id->commutative;
3793 
3794   /* Now see what we need for pseudos that didn't get hard regs or got
3795      the wrong kind of hard reg.  For this, we must consider all the
3796      operands together against the register constraints.  */
3797 
3798   best_losers = best_overall = INT_MAX;
3799   best_reload_sum = 0;
3800 
3801   curr_swapped = false;
3802   goal_alt_swapped = false;
3803 
3804   if (! check_only_p)
3805     /* Make equivalence substitution and memory subreg elimination
3806        before address processing because an address legitimacy can
3807        depend on memory mode.  */
3808     for (i = 0; i < n_operands; i++)
3809       {
3810 	rtx op, subst, old;
3811 	bool op_change_p = false;
3812 
3813 	if (curr_static_id->operand[i].is_operator)
3814 	  continue;
3815 
3816 	old = op = *curr_id->operand_loc[i];
3817 	if (GET_CODE (old) == SUBREG)
3818 	  old = SUBREG_REG (old);
3819 	subst = get_equiv_with_elimination (old, curr_insn);
3820 	original_subreg_reg_mode[i] = VOIDmode;
3821 	equiv_substition_p[i] = false;
3822 	if (subst != old)
3823 	  {
3824 	    equiv_substition_p[i] = true;
3825 	    subst = copy_rtx (subst);
3826 	    lra_assert (REG_P (old));
3827 	    if (GET_CODE (op) != SUBREG)
3828 	      *curr_id->operand_loc[i] = subst;
3829 	    else
3830 	      {
3831 		SUBREG_REG (op) = subst;
3832 		if (GET_MODE (subst) == VOIDmode)
3833 		  original_subreg_reg_mode[i] = GET_MODE (old);
3834 	      }
3835 	    if (lra_dump_file != NULL)
3836 	      {
3837 		fprintf (lra_dump_file,
3838 			 "Changing pseudo %d in operand %i of insn %u on equiv ",
3839 			 REGNO (old), i, INSN_UID (curr_insn));
3840 		dump_value_slim (lra_dump_file, subst, 1);
3841 		fprintf (lra_dump_file, "\n");
3842 	      }
3843 	    op_change_p = change_p = true;
3844 	  }
3845 	if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p)
3846 	  {
3847 	    change_p = true;
3848 	    lra_update_dup (curr_id, i);
3849 	  }
3850       }
3851 
3852   /* Reload address registers and displacements.  We do it before
3853      finding an alternative because of memory constraints.  */
3854   before = after = NULL;
3855   for (i = 0; i < n_operands; i++)
3856     if (! curr_static_id->operand[i].is_operator
3857 	&& process_address (i, check_only_p, &before, &after))
3858       {
3859 	if (check_only_p)
3860 	  return true;
3861 	change_p = true;
3862 	lra_update_dup (curr_id, i);
3863       }
3864 
3865   if (change_p)
3866     /* If we've changed the instruction then any alternative that
3867        we chose previously may no longer be valid.  */
3868     lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT);
3869 
3870   if (! check_only_p && curr_insn_set != NULL_RTX
3871       && check_and_process_move (&change_p, &sec_mem_p))
3872     return change_p;
3873 
3874  try_swapped:
3875 
3876   reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative;
3877   if (lra_dump_file != NULL && reused_alternative_num >= 0)
3878     fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
3879 	     reused_alternative_num, INSN_UID (curr_insn));
3880 
3881   if (process_alt_operands (reused_alternative_num))
3882     alt_p = true;
3883 
3884   if (check_only_p)
3885     return ! alt_p || best_losers != 0;
3886 
3887   /* If insn is commutative (it's safe to exchange a certain pair of
3888      operands) then we need to try each alternative twice, the second
3889      time matching those two operands as if we had exchanged them.  To
3890      do this, really exchange them in operands.
3891 
3892      If we have just tried the alternatives the second time, return
3893      operands to normal and drop through.  */
3894 
3895   if (reused_alternative_num < 0 && commutative >= 0)
3896     {
3897       curr_swapped = !curr_swapped;
3898       if (curr_swapped)
3899 	{
3900 	  swap_operands (commutative);
3901 	  goto try_swapped;
3902 	}
3903       else
3904 	swap_operands (commutative);
3905     }
3906 
3907   if (! alt_p && ! sec_mem_p)
3908     {
3909       /* No alternative works with reloads??  */
3910       if (INSN_CODE (curr_insn) >= 0)
3911 	fatal_insn ("unable to generate reloads for:", curr_insn);
3912       error_for_asm (curr_insn,
3913 		     "inconsistent operand constraints in an %<asm%>");
3914       /* Avoid further trouble with this insn.  Don't generate use
3915 	 pattern here as we could use the insn SP offset.  */
3916       lra_set_insn_deleted (curr_insn);
3917       return true;
3918     }
3919 
3920   /* If the best alternative is with operands 1 and 2 swapped, swap
3921      them.  Update the operand numbers of any reloads already
3922      pushed.  */
3923 
3924   if (goal_alt_swapped)
3925     {
3926       if (lra_dump_file != NULL)
3927 	fprintf (lra_dump_file, "  Commutative operand exchange in insn %u\n",
3928 		 INSN_UID (curr_insn));
3929 
3930       /* Swap the duplicates too.  */
3931       swap_operands (commutative);
3932       change_p = true;
3933     }
3934 
3935   /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3936      too conservatively.  So we use the secondary memory only if there
3937      is no any alternative without reloads.  */
3938   use_sec_mem_p = false;
3939   if (! alt_p)
3940     use_sec_mem_p = true;
3941   else if (sec_mem_p)
3942     {
3943       for (i = 0; i < n_operands; i++)
3944 	if (! goal_alt_win[i] && ! goal_alt_match_win[i])
3945 	  break;
3946       use_sec_mem_p = i < n_operands;
3947     }
3948 
3949   if (use_sec_mem_p)
3950     {
3951       int in = -1, out = -1;
3952       rtx new_reg, src, dest, rld;
3953       machine_mode sec_mode, rld_mode;
3954 
3955       lra_assert (curr_insn_set != NULL_RTX && sec_mem_p);
3956       dest = SET_DEST (curr_insn_set);
3957       src = SET_SRC (curr_insn_set);
3958       for (i = 0; i < n_operands; i++)
3959 	if (*curr_id->operand_loc[i] == dest)
3960 	  out = i;
3961 	else if (*curr_id->operand_loc[i] == src)
3962 	  in = i;
3963       for (i = 0; i < curr_static_id->n_dups; i++)
3964 	if (out < 0 && *curr_id->dup_loc[i] == dest)
3965 	  out = curr_static_id->dup_num[i];
3966 	else if (in < 0 && *curr_id->dup_loc[i] == src)
3967 	  in = curr_static_id->dup_num[i];
3968       lra_assert (out >= 0 && in >= 0
3969 		  && curr_static_id->operand[out].type == OP_OUT
3970 		  && curr_static_id->operand[in].type == OP_IN);
3971       rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest;
3972       rld_mode = GET_MODE (rld);
3973       sec_mode = targetm.secondary_memory_needed_mode (rld_mode);
3974       new_reg = lra_create_new_reg (sec_mode, NULL_RTX,
3975 				    NO_REGS, "secondary");
3976       /* If the mode is changed, it should be wider.  */
3977       lra_assert (!partial_subreg_p (sec_mode, rld_mode));
3978       if (sec_mode != rld_mode)
3979         {
3980 	  /* If the target says specifically to use another mode for
3981 	     secondary memory moves we can not reuse the original
3982 	     insn.  */
3983 	  after = emit_spill_move (false, new_reg, dest);
3984 	  lra_process_new_insns (curr_insn, NULL, after,
3985 				 "Inserting the sec. move");
3986 	  /* We may have non null BEFORE here (e.g. after address
3987 	     processing.  */
3988 	  push_to_sequence (before);
3989 	  before = emit_spill_move (true, new_reg, src);
3990 	  emit_insn (before);
3991 	  before = get_insns ();
3992 	  end_sequence ();
3993 	  lra_process_new_insns (curr_insn, before, NULL, "Changing on");
3994 	  lra_set_insn_deleted (curr_insn);
3995 	}
3996       else if (dest == rld)
3997         {
3998 	  *curr_id->operand_loc[out] = new_reg;
3999 	  lra_update_dup (curr_id, out);
4000 	  after = emit_spill_move (false, new_reg, dest);
4001 	  lra_process_new_insns (curr_insn, NULL, after,
4002 				 "Inserting the sec. move");
4003 	}
4004       else
4005 	{
4006 	  *curr_id->operand_loc[in] = new_reg;
4007 	  lra_update_dup (curr_id, in);
4008 	  /* See comments above.  */
4009 	  push_to_sequence (before);
4010 	  before = emit_spill_move (true, new_reg, src);
4011 	  emit_insn (before);
4012 	  before = get_insns ();
4013 	  end_sequence ();
4014 	  lra_process_new_insns (curr_insn, before, NULL,
4015 				 "Inserting the sec. move");
4016 	}
4017       lra_update_insn_regno_info (curr_insn);
4018       return true;
4019     }
4020 
4021   lra_assert (goal_alt_number >= 0);
4022   lra_set_used_insn_alternative (curr_insn, goal_alt_number);
4023 
4024   if (lra_dump_file != NULL)
4025     {
4026       const char *p;
4027 
4028       fprintf (lra_dump_file, "	 Choosing alt %d in insn %u:",
4029 	       goal_alt_number, INSN_UID (curr_insn));
4030       for (i = 0; i < n_operands; i++)
4031 	{
4032 	  p = (curr_static_id->operand_alternative
4033 	       [goal_alt_number * n_operands + i].constraint);
4034 	  if (*p == '\0')
4035 	    continue;
4036 	  fprintf (lra_dump_file, "  (%d) ", i);
4037 	  for (; *p != '\0' && *p != ',' && *p != '#'; p++)
4038 	    fputc (*p, lra_dump_file);
4039 	}
4040       if (INSN_CODE (curr_insn) >= 0
4041           && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL)
4042         fprintf (lra_dump_file, " {%s}", p);
4043       if (maybe_ne (curr_id->sp_offset, 0))
4044 	{
4045 	  fprintf (lra_dump_file, " (sp_off=");
4046 	  print_dec (curr_id->sp_offset, lra_dump_file);
4047 	  fprintf (lra_dump_file, ")");
4048 	}
4049       fprintf (lra_dump_file, "\n");
4050     }
4051 
4052   /* Right now, for any pair of operands I and J that are required to
4053      match, with J < I, goal_alt_matches[I] is J.  Add I to
4054      goal_alt_matched[J].  */
4055 
4056   for (i = 0; i < n_operands; i++)
4057     if ((j = goal_alt_matches[i]) >= 0)
4058       {
4059 	for (k = 0; goal_alt_matched[j][k] >= 0; k++)
4060 	  ;
4061 	/* We allow matching one output operand and several input
4062 	   operands.  */
4063 	lra_assert (k == 0
4064 		    || (curr_static_id->operand[j].type == OP_OUT
4065 			&& curr_static_id->operand[i].type == OP_IN
4066 			&& (curr_static_id->operand
4067 			    [goal_alt_matched[j][0]].type == OP_IN)));
4068 	goal_alt_matched[j][k] = i;
4069 	goal_alt_matched[j][k + 1] = -1;
4070       }
4071 
4072   for (i = 0; i < n_operands; i++)
4073     goal_alt_win[i] |= goal_alt_match_win[i];
4074 
4075   /* Any constants that aren't allowed and can't be reloaded into
4076      registers are here changed into memory references.	 */
4077   for (i = 0; i < n_operands; i++)
4078     if (goal_alt_win[i])
4079       {
4080 	int regno;
4081 	enum reg_class new_class;
4082 	rtx reg = *curr_id->operand_loc[i];
4083 
4084 	if (GET_CODE (reg) == SUBREG)
4085 	  reg = SUBREG_REG (reg);
4086 
4087 	if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
4088 	  {
4089 	    bool ok_p = in_class_p (reg, goal_alt[i], &new_class);
4090 
4091 	    if (new_class != NO_REGS && get_reg_class (regno) != new_class)
4092 	      {
4093 		lra_assert (ok_p);
4094 		lra_change_class (regno, new_class, "      Change to", true);
4095 	      }
4096 	  }
4097       }
4098     else
4099       {
4100 	const char *constraint;
4101 	char c;
4102 	rtx op = *curr_id->operand_loc[i];
4103 	rtx subreg = NULL_RTX;
4104 	machine_mode mode = curr_operand_mode[i];
4105 
4106 	if (GET_CODE (op) == SUBREG)
4107 	  {
4108 	    subreg = op;
4109 	    op = SUBREG_REG (op);
4110 	    mode = GET_MODE (op);
4111 	  }
4112 
4113 	if (CONST_POOL_OK_P (mode, op)
4114 	    && ((targetm.preferred_reload_class
4115 		 (op, (enum reg_class) goal_alt[i]) == NO_REGS)
4116 		|| no_input_reloads_p))
4117 	  {
4118 	    rtx tem = force_const_mem (mode, op);
4119 
4120 	    change_p = true;
4121 	    if (subreg != NULL_RTX)
4122 	      tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg));
4123 
4124 	    *curr_id->operand_loc[i] = tem;
4125 	    lra_update_dup (curr_id, i);
4126 	    process_address (i, false, &before, &after);
4127 
4128 	    /* If the alternative accepts constant pool refs directly
4129 	       there will be no reload needed at all.  */
4130 	    if (subreg != NULL_RTX)
4131 	      continue;
4132 	    /* Skip alternatives before the one requested.  */
4133 	    constraint = (curr_static_id->operand_alternative
4134 			  [goal_alt_number * n_operands + i].constraint);
4135 	    for (;
4136 		 (c = *constraint) && c != ',' && c != '#';
4137 		 constraint += CONSTRAINT_LEN (c, constraint))
4138 	      {
4139 		enum constraint_num cn = lookup_constraint (constraint);
4140 		if ((insn_extra_memory_constraint (cn)
4141 		     || insn_extra_special_memory_constraint (cn))
4142 		    && satisfies_memory_constraint_p (tem, cn))
4143 		  break;
4144 	      }
4145 	    if (c == '\0' || c == ',' || c == '#')
4146 	      continue;
4147 
4148 	    goal_alt_win[i] = true;
4149 	  }
4150       }
4151 
4152   n_outputs = 0;
4153   outputs[0] = -1;
4154   for (i = 0; i < n_operands; i++)
4155     {
4156       int regno;
4157       bool optional_p = false;
4158       rtx old, new_reg;
4159       rtx op = *curr_id->operand_loc[i];
4160 
4161       if (goal_alt_win[i])
4162 	{
4163 	  if (goal_alt[i] == NO_REGS
4164 	      && REG_P (op)
4165 	      /* When we assign NO_REGS it means that we will not
4166 		 assign a hard register to the scratch pseudo by
4167 		 assigment pass and the scratch pseudo will be
4168 		 spilled.  Spilled scratch pseudos are transformed
4169 		 back to scratches at the LRA end.  */
4170 	      && lra_former_scratch_operand_p (curr_insn, i)
4171 	      && lra_former_scratch_p (REGNO (op)))
4172 	    {
4173 	      int regno = REGNO (op);
4174 	      lra_change_class (regno, NO_REGS, "      Change to", true);
4175 	      if (lra_get_regno_hard_regno (regno) >= 0)
4176 		/* We don't have to mark all insn affected by the
4177 		   spilled pseudo as there is only one such insn, the
4178 		   current one.  */
4179 		reg_renumber[regno] = -1;
4180 	      lra_assert (bitmap_single_bit_set_p
4181 			  (&lra_reg_info[REGNO (op)].insn_bitmap));
4182 	    }
4183 	  /* We can do an optional reload.  If the pseudo got a hard
4184 	     reg, we might improve the code through inheritance.  If
4185 	     it does not get a hard register we coalesce memory/memory
4186 	     moves later.  Ignore move insns to avoid cycling.  */
4187 	  if (! lra_simple_p
4188 	      && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES
4189 	      && goal_alt[i] != NO_REGS && REG_P (op)
4190 	      && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
4191 	      && regno < new_regno_start
4192 	      && ! lra_former_scratch_p (regno)
4193 	      && reg_renumber[regno] < 0
4194 	      /* Check that the optional reload pseudo will be able to
4195 		 hold given mode value.  */
4196 	      && ! (prohibited_class_reg_set_mode_p
4197 		    (goal_alt[i], reg_class_contents[goal_alt[i]],
4198 		     PSEUDO_REGNO_MODE (regno)))
4199 	      && (curr_insn_set == NULL_RTX
4200 		  || !((REG_P (SET_SRC (curr_insn_set))
4201 			|| MEM_P (SET_SRC (curr_insn_set))
4202 			|| GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
4203 		       && (REG_P (SET_DEST (curr_insn_set))
4204 			   || MEM_P (SET_DEST (curr_insn_set))
4205 			   || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
4206 	    optional_p = true;
4207 	  else
4208 	    continue;
4209 	}
4210 
4211       /* Operands that match previous ones have already been handled.  */
4212       if (goal_alt_matches[i] >= 0)
4213 	continue;
4214 
4215       /* We should not have an operand with a non-offsettable address
4216 	 appearing where an offsettable address will do.  It also may
4217 	 be a case when the address should be special in other words
4218 	 not a general one (e.g. it needs no index reg).  */
4219       if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op))
4220 	{
4221 	  enum reg_class rclass;
4222 	  rtx *loc = &XEXP (op, 0);
4223 	  enum rtx_code code = GET_CODE (*loc);
4224 
4225 	  push_to_sequence (before);
4226 	  rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op),
4227 				   MEM, SCRATCH);
4228 	  if (GET_RTX_CLASS (code) == RTX_AUTOINC)
4229 	    new_reg = emit_inc (rclass, *loc, *loc,
4230 				/* This value does not matter for MODIFY.  */
4231 				GET_MODE_SIZE (GET_MODE (op)));
4232 	  else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE,
4233 				   "offsetable address", &new_reg))
4234 	    {
4235 	      rtx addr = *loc;
4236 	      enum rtx_code code = GET_CODE (addr);
4237 
4238 	      if (code == AND && CONST_INT_P (XEXP (addr, 1)))
4239 		/* (and ... (const_int -X)) is used to align to X bytes.  */
4240 		addr = XEXP (*loc, 0);
4241 	      lra_emit_move (new_reg, addr);
4242 	      if (addr != *loc)
4243 		emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1)));
4244 	    }
4245 	  before = get_insns ();
4246 	  end_sequence ();
4247 	  *loc = new_reg;
4248 	  lra_update_dup (curr_id, i);
4249 	}
4250       else if (goal_alt_matched[i][0] == -1)
4251 	{
4252 	  machine_mode mode;
4253 	  rtx reg, *loc;
4254 	  int hard_regno;
4255 	  enum op_type type = curr_static_id->operand[i].type;
4256 
4257 	  loc = curr_id->operand_loc[i];
4258 	  mode = curr_operand_mode[i];
4259 	  if (GET_CODE (*loc) == SUBREG)
4260 	    {
4261 	      reg = SUBREG_REG (*loc);
4262 	      poly_int64 byte = SUBREG_BYTE (*loc);
4263 	      if (REG_P (reg)
4264 		  /* Strict_low_part requires reloading the register and not
4265 		     just the subreg.  Likewise for a strict subreg no wider
4266 		     than a word for WORD_REGISTER_OPERATIONS targets.  */
4267 		  && (curr_static_id->operand[i].strict_low
4268 		      || (!paradoxical_subreg_p (mode, GET_MODE (reg))
4269 			  && (hard_regno
4270 			      = get_try_hard_regno (REGNO (reg))) >= 0
4271 			  && (simplify_subreg_regno
4272 			      (hard_regno,
4273 			       GET_MODE (reg), byte, mode) < 0)
4274 			  && (goal_alt[i] == NO_REGS
4275 			      || (simplify_subreg_regno
4276 				  (ira_class_hard_regs[goal_alt[i]][0],
4277 				   GET_MODE (reg), byte, mode) >= 0)))
4278 		      || (partial_subreg_p (mode, GET_MODE (reg))
4279 			  && known_le (GET_MODE_SIZE (GET_MODE (reg)),
4280 				       UNITS_PER_WORD)
4281 			  && WORD_REGISTER_OPERATIONS)))
4282 		{
4283 		  /* An OP_INOUT is required when reloading a subreg of a
4284 		     mode wider than a word to ensure that data beyond the
4285 		     word being reloaded is preserved.  Also automatically
4286 		     ensure that strict_low_part reloads are made into
4287 		     OP_INOUT which should already be true from the backend
4288 		     constraints.  */
4289 		  if (type == OP_OUT
4290 		      && (curr_static_id->operand[i].strict_low
4291 			  || read_modify_subreg_p (*loc)))
4292 		    type = OP_INOUT;
4293 		  loc = &SUBREG_REG (*loc);
4294 		  mode = GET_MODE (*loc);
4295 		}
4296 	    }
4297 	  old = *loc;
4298 	  if (get_reload_reg (type, mode, old, goal_alt[i],
4299 			      loc != curr_id->operand_loc[i], "", &new_reg)
4300 	      && type != OP_OUT)
4301 	    {
4302 	      push_to_sequence (before);
4303 	      lra_emit_move (new_reg, old);
4304 	      before = get_insns ();
4305 	      end_sequence ();
4306 	    }
4307 	  *loc = new_reg;
4308 	  if (type != OP_IN
4309 	      && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX)
4310 	    {
4311 	      start_sequence ();
4312 	      lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
4313 	      emit_insn (after);
4314 	      after = get_insns ();
4315 	      end_sequence ();
4316 	      *loc = new_reg;
4317 	    }
4318 	  for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
4319 	    if (goal_alt_dont_inherit_ops[j] == i)
4320 	      {
4321 		lra_set_regno_unique_value (REGNO (new_reg));
4322 		break;
4323 	      }
4324 	  lra_update_dup (curr_id, i);
4325 	}
4326       else if (curr_static_id->operand[i].type == OP_IN
4327 	       && (curr_static_id->operand[goal_alt_matched[i][0]].type
4328 		   == OP_OUT
4329 		   || (curr_static_id->operand[goal_alt_matched[i][0]].type
4330 		       == OP_INOUT
4331 		       && (operands_match_p
4332 			   (*curr_id->operand_loc[i],
4333 			    *curr_id->operand_loc[goal_alt_matched[i][0]],
4334 			    -1)))))
4335 	{
4336 	  /* generate reloads for input and matched outputs.  */
4337 	  match_inputs[0] = i;
4338 	  match_inputs[1] = -1;
4339 	  match_reload (goal_alt_matched[i][0], match_inputs, outputs,
4340 			goal_alt[i], &before, &after,
4341 			curr_static_id->operand_alternative
4342 			[goal_alt_number * n_operands + goal_alt_matched[i][0]]
4343 			.earlyclobber);
4344 	}
4345       else if ((curr_static_id->operand[i].type == OP_OUT
4346 		|| (curr_static_id->operand[i].type == OP_INOUT
4347 		    && (operands_match_p
4348 			(*curr_id->operand_loc[i],
4349 			 *curr_id->operand_loc[goal_alt_matched[i][0]],
4350 			 -1))))
4351 	       && (curr_static_id->operand[goal_alt_matched[i][0]].type
4352 		    == OP_IN))
4353 	/* Generate reloads for output and matched inputs.  */
4354 	match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
4355 		      &after, curr_static_id->operand_alternative
4356 			      [goal_alt_number * n_operands + i].earlyclobber);
4357       else if (curr_static_id->operand[i].type == OP_IN
4358 	       && (curr_static_id->operand[goal_alt_matched[i][0]].type
4359 		   == OP_IN))
4360 	{
4361 	  /* Generate reloads for matched inputs.  */
4362 	  match_inputs[0] = i;
4363 	  for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
4364 	    match_inputs[j + 1] = k;
4365 	  match_inputs[j + 1] = -1;
4366 	  match_reload (-1, match_inputs, outputs, goal_alt[i], &before,
4367 			&after, false);
4368 	}
4369       else
4370 	/* We must generate code in any case when function
4371 	   process_alt_operands decides that it is possible.  */
4372 	gcc_unreachable ();
4373 
4374       /* Memorise processed outputs so that output remaining to be processed
4375 	 can avoid using the same register value (see match_reload).  */
4376       if (curr_static_id->operand[i].type == OP_OUT)
4377 	{
4378 	  outputs[n_outputs++] = i;
4379 	  outputs[n_outputs] = -1;
4380 	}
4381 
4382       if (optional_p)
4383 	{
4384 	  rtx reg = op;
4385 
4386 	  lra_assert (REG_P (reg));
4387 	  regno = REGNO (reg);
4388 	  op = *curr_id->operand_loc[i]; /* Substitution.  */
4389 	  if (GET_CODE (op) == SUBREG)
4390 	    op = SUBREG_REG (op);
4391 	  gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
4392 	  bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
4393 	  lra_reg_info[REGNO (op)].restore_rtx = reg;
4394 	  if (lra_dump_file != NULL)
4395 	    fprintf (lra_dump_file,
4396 		     "      Making reload reg %d for reg %d optional\n",
4397 		     REGNO (op), regno);
4398 	}
4399     }
4400   if (before != NULL_RTX || after != NULL_RTX
4401       || max_regno_before != max_reg_num ())
4402     change_p = true;
4403   if (change_p)
4404     {
4405       lra_update_operator_dups (curr_id);
4406       /* Something changes -- process the insn.	 */
4407       lra_update_insn_regno_info (curr_insn);
4408     }
4409   lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
4410   return change_p;
4411 }
4412 
4413 /* Return true if INSN satisfies all constraints.  In other words, no
4414    reload insns are needed.  */
4415 bool
4416 lra_constrain_insn (rtx_insn *insn)
4417 {
4418   int saved_new_regno_start = new_regno_start;
4419   int saved_new_insn_uid_start = new_insn_uid_start;
4420   bool change_p;
4421 
4422   curr_insn = insn;
4423   curr_id = lra_get_insn_recog_data (curr_insn);
4424   curr_static_id = curr_id->insn_static_data;
4425   new_insn_uid_start = get_max_uid ();
4426   new_regno_start = max_reg_num ();
4427   change_p = curr_insn_transform (true);
4428   new_regno_start = saved_new_regno_start;
4429   new_insn_uid_start = saved_new_insn_uid_start;
4430   return ! change_p;
4431 }
4432 
4433 /* Return true if X is in LIST.	 */
4434 static bool
4435 in_list_p (rtx x, rtx list)
4436 {
4437   for (; list != NULL_RTX; list = XEXP (list, 1))
4438     if (XEXP (list, 0) == x)
4439       return true;
4440   return false;
4441 }
4442 
4443 /* Return true if X contains an allocatable hard register (if
4444    HARD_REG_P) or a (spilled if SPILLED_P) pseudo.  */
4445 static bool
4446 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
4447 {
4448   int i, j;
4449   const char *fmt;
4450   enum rtx_code code;
4451 
4452   code = GET_CODE (x);
4453   if (REG_P (x))
4454     {
4455       int regno = REGNO (x);
4456       HARD_REG_SET alloc_regs;
4457 
4458       if (hard_reg_p)
4459 	{
4460 	  if (regno >= FIRST_PSEUDO_REGISTER)
4461 	    regno = lra_get_regno_hard_regno (regno);
4462 	  if (regno < 0)
4463 	    return false;
4464 	  COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs);
4465 	  return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
4466 	}
4467       else
4468 	{
4469 	  if (regno < FIRST_PSEUDO_REGISTER)
4470 	    return false;
4471 	  if (! spilled_p)
4472 	    return true;
4473 	  return lra_get_regno_hard_regno (regno) < 0;
4474 	}
4475     }
4476   fmt = GET_RTX_FORMAT (code);
4477   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4478     {
4479       if (fmt[i] == 'e')
4480 	{
4481 	  if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p))
4482 	    return true;
4483 	}
4484       else if (fmt[i] == 'E')
4485 	{
4486 	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4487 	    if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p))
4488 	      return true;
4489 	}
4490     }
4491   return false;
4492 }
4493 
4494 /* Process all regs in location *LOC and change them on equivalent
4495    substitution.  Return true if any change was done.  */
4496 static bool
4497 loc_equivalence_change_p (rtx *loc)
4498 {
4499   rtx subst, reg, x = *loc;
4500   bool result = false;
4501   enum rtx_code code = GET_CODE (x);
4502   const char *fmt;
4503   int i, j;
4504 
4505   if (code == SUBREG)
4506     {
4507       reg = SUBREG_REG (x);
4508       if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
4509 	  && GET_MODE (subst) == VOIDmode)
4510 	{
4511 	  /* We cannot reload debug location.  Simplify subreg here
4512 	     while we know the inner mode.  */
4513 	  *loc = simplify_gen_subreg (GET_MODE (x), subst,
4514 				      GET_MODE (reg), SUBREG_BYTE (x));
4515 	  return true;
4516 	}
4517     }
4518   if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x)
4519     {
4520       *loc = subst;
4521       return true;
4522     }
4523 
4524   /* Scan all the operand sub-expressions.  */
4525   fmt = GET_RTX_FORMAT (code);
4526   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4527     {
4528       if (fmt[i] == 'e')
4529 	result = loc_equivalence_change_p (&XEXP (x, i)) || result;
4530       else if (fmt[i] == 'E')
4531 	for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4532 	  result
4533 	    = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result;
4534     }
4535   return result;
4536 }
4537 
4538 /* Similar to loc_equivalence_change_p, but for use as
4539    simplify_replace_fn_rtx callback.  DATA is insn for which the
4540    elimination is done.  If it null we don't do the elimination.  */
4541 static rtx
4542 loc_equivalence_callback (rtx loc, const_rtx, void *data)
4543 {
4544   if (!REG_P (loc))
4545     return NULL_RTX;
4546 
4547   rtx subst = (data == NULL
4548 	       ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data));
4549   if (subst != loc)
4550     return subst;
4551 
4552   return NULL_RTX;
4553 }
4554 
4555 /* Maximum number of generated reload insns per an insn.  It is for
4556    preventing this pass cycling in a bug case.	*/
4557 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4558 
4559 /* The current iteration number of this LRA pass.  */
4560 int lra_constraint_iter;
4561 
4562 /* True if we substituted equiv which needs checking register
4563    allocation correctness because the equivalent value contains
4564    allocatable hard registers or when we restore multi-register
4565    pseudo.  */
4566 bool lra_risky_transformations_p;
4567 
4568 /* Return true if REGNO is referenced in more than one block.  */
4569 static bool
4570 multi_block_pseudo_p (int regno)
4571 {
4572   basic_block bb = NULL;
4573   unsigned int uid;
4574   bitmap_iterator bi;
4575 
4576   if (regno < FIRST_PSEUDO_REGISTER)
4577     return false;
4578 
4579     EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
4580       if (bb == NULL)
4581 	bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn);
4582       else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb)
4583 	return true;
4584     return false;
4585 }
4586 
4587 /* Return true if LIST contains a deleted insn.  */
4588 static bool
4589 contains_deleted_insn_p (rtx_insn_list *list)
4590 {
4591   for (; list != NULL_RTX; list = list->next ())
4592     if (NOTE_P (list->insn ())
4593 	&& NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED)
4594       return true;
4595   return false;
4596 }
4597 
4598 /* Return true if X contains a pseudo dying in INSN.  */
4599 static bool
4600 dead_pseudo_p (rtx x, rtx_insn *insn)
4601 {
4602   int i, j;
4603   const char *fmt;
4604   enum rtx_code code;
4605 
4606   if (REG_P (x))
4607     return (insn != NULL_RTX
4608 	    && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX);
4609   code = GET_CODE (x);
4610   fmt = GET_RTX_FORMAT (code);
4611   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4612     {
4613       if (fmt[i] == 'e')
4614 	{
4615 	  if (dead_pseudo_p (XEXP (x, i), insn))
4616 	    return true;
4617 	}
4618       else if (fmt[i] == 'E')
4619 	{
4620 	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4621 	    if (dead_pseudo_p (XVECEXP (x, i, j), insn))
4622 	      return true;
4623 	}
4624     }
4625   return false;
4626 }
4627 
4628 /* Return true if INSN contains a dying pseudo in INSN right hand
4629    side.  */
4630 static bool
4631 insn_rhs_dead_pseudo_p (rtx_insn *insn)
4632 {
4633   rtx set = single_set (insn);
4634 
4635   gcc_assert (set != NULL);
4636   return dead_pseudo_p (SET_SRC (set), insn);
4637 }
4638 
4639 /* Return true if any init insn of REGNO contains a dying pseudo in
4640    insn right hand side.  */
4641 static bool
4642 init_insn_rhs_dead_pseudo_p (int regno)
4643 {
4644   rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4645 
4646   if (insns == NULL)
4647     return false;
4648   for (; insns != NULL_RTX; insns = insns->next ())
4649     if (insn_rhs_dead_pseudo_p (insns->insn ()))
4650       return true;
4651   return false;
4652 }
4653 
4654 /* Return TRUE if REGNO has a reverse equivalence.  The equivalence is
4655    reverse only if we have one init insn with given REGNO as a
4656    source.  */
4657 static bool
4658 reverse_equiv_p (int regno)
4659 {
4660   rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4661   rtx set;
4662 
4663   if (insns == NULL)
4664     return false;
4665   if (! INSN_P (insns->insn ())
4666       || insns->next () != NULL)
4667     return false;
4668   if ((set = single_set (insns->insn ())) == NULL_RTX)
4669     return false;
4670   return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno;
4671 }
4672 
4673 /* Return TRUE if REGNO was reloaded in an equivalence init insn.  We
4674    call this function only for non-reverse equivalence.  */
4675 static bool
4676 contains_reloaded_insn_p (int regno)
4677 {
4678   rtx set;
4679   rtx_insn_list *list = ira_reg_equiv[regno].init_insns;
4680 
4681   for (; list != NULL; list = list->next ())
4682     if ((set = single_set (list->insn ())) == NULL_RTX
4683 	|| ! REG_P (SET_DEST (set))
4684 	|| (int) REGNO (SET_DEST (set)) != regno)
4685       return true;
4686   return false;
4687 }
4688 
4689 /* Entry function of LRA constraint pass.  Return true if the
4690    constraint pass did change the code.	 */
4691 bool
4692 lra_constraints (bool first_p)
4693 {
4694   bool changed_p;
4695   int i, hard_regno, new_insns_num;
4696   unsigned int min_len, new_min_len, uid;
4697   rtx set, x, reg, dest_reg;
4698   basic_block last_bb;
4699   bitmap_iterator bi;
4700 
4701   lra_constraint_iter++;
4702   if (lra_dump_file != NULL)
4703     fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
4704 	     lra_constraint_iter);
4705   changed_p = false;
4706   if (pic_offset_table_rtx
4707       && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
4708     lra_risky_transformations_p = true;
4709   else
4710     /* On the first iteration we should check IRA assignment
4711        correctness.  In rare cases, the assignments can be wrong as
4712        early clobbers operands are ignored in IRA.  */
4713     lra_risky_transformations_p = first_p;
4714   new_insn_uid_start = get_max_uid ();
4715   new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
4716   /* Mark used hard regs for target stack size calulations.  */
4717   for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4718     if (lra_reg_info[i].nrefs != 0
4719 	&& (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4720       {
4721 	int j, nregs;
4722 
4723 	nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode);
4724 	for (j = 0; j < nregs; j++)
4725 	  df_set_regs_ever_live (hard_regno + j, true);
4726       }
4727   /* Do elimination before the equivalence processing as we can spill
4728      some pseudos during elimination.  */
4729   lra_eliminate (false, first_p);
4730   auto_bitmap equiv_insn_bitmap (&reg_obstack);
4731   for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4732     if (lra_reg_info[i].nrefs != 0)
4733       {
4734 	ira_reg_equiv[i].profitable_p = true;
4735 	reg = regno_reg_rtx[i];
4736 	if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
4737 	  {
4738 	    bool pseudo_p = contains_reg_p (x, false, false);
4739 
4740 	    /* After RTL transformation, we can not guarantee that
4741 	       pseudo in the substitution was not reloaded which might
4742 	       make equivalence invalid.  For example, in reverse
4743 	       equiv of p0
4744 
4745 	       p0 <- ...
4746 	       ...
4747 	       equiv_mem <- p0
4748 
4749 	       the memory address register was reloaded before the 2nd
4750 	       insn.  */
4751 	    if ((! first_p && pseudo_p)
4752 		/* We don't use DF for compilation speed sake.  So it
4753 		   is problematic to update live info when we use an
4754 		   equivalence containing pseudos in more than one
4755 		   BB.  */
4756 		|| (pseudo_p && multi_block_pseudo_p (i))
4757 		/* If an init insn was deleted for some reason, cancel
4758 		   the equiv.  We could update the equiv insns after
4759 		   transformations including an equiv insn deletion
4760 		   but it is not worthy as such cases are extremely
4761 		   rare.  */
4762 		|| contains_deleted_insn_p (ira_reg_equiv[i].init_insns)
4763 		/* If it is not a reverse equivalence, we check that a
4764 		   pseudo in rhs of the init insn is not dying in the
4765 		   insn.  Otherwise, the live info at the beginning of
4766 		   the corresponding BB might be wrong after we
4767 		   removed the insn.  When the equiv can be a
4768 		   constant, the right hand side of the init insn can
4769 		   be a pseudo.  */
4770 		|| (! reverse_equiv_p (i)
4771 		    && (init_insn_rhs_dead_pseudo_p (i)
4772 			/* If we reloaded the pseudo in an equivalence
4773 			   init insn, we can not remove the equiv init
4774 			   insns and the init insns might write into
4775 			   const memory in this case.  */
4776 			|| contains_reloaded_insn_p (i)))
4777 		/* Prevent access beyond equivalent memory for
4778 		   paradoxical subregs.  */
4779 		|| (MEM_P (x)
4780 		    && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode),
4781 				 GET_MODE_SIZE (GET_MODE (x))))
4782 		|| (pic_offset_table_rtx
4783 		    && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x)
4784 			 && (targetm.preferred_reload_class
4785 			     (x, lra_get_allocno_class (i)) == NO_REGS))
4786 			|| contains_symbol_ref_p (x))))
4787 	      ira_reg_equiv[i].defined_p = false;
4788 	    if (contains_reg_p (x, false, true))
4789 	      ira_reg_equiv[i].profitable_p = false;
4790 	    if (get_equiv (reg) != reg)
4791 	      bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap);
4792 	  }
4793       }
4794   for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4795     update_equiv (i);
4796   /* We should add all insns containing pseudos which should be
4797      substituted by their equivalences.  */
4798   EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi)
4799     lra_push_insn_by_uid (uid);
4800   min_len = lra_insn_stack_length ();
4801   new_insns_num = 0;
4802   last_bb = NULL;
4803   changed_p = false;
4804   while ((new_min_len = lra_insn_stack_length ()) != 0)
4805     {
4806       curr_insn = lra_pop_insn ();
4807       --new_min_len;
4808       curr_bb = BLOCK_FOR_INSN (curr_insn);
4809       if (curr_bb != last_bb)
4810 	{
4811 	  last_bb = curr_bb;
4812 	  bb_reload_num = lra_curr_reload_num;
4813 	}
4814       if (min_len > new_min_len)
4815 	{
4816 	  min_len = new_min_len;
4817 	  new_insns_num = 0;
4818 	}
4819       if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
4820 	internal_error
4821 	  ("Max. number of generated reload insns per insn is achieved (%d)\n",
4822 	   MAX_RELOAD_INSNS_NUMBER);
4823       new_insns_num++;
4824       if (DEBUG_INSN_P (curr_insn))
4825 	{
4826 	  /* We need to check equivalence in debug insn and change
4827 	     pseudo to the equivalent value if necessary.  */
4828 	  curr_id = lra_get_insn_recog_data (curr_insn);
4829 	  if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)))
4830 	    {
4831 	      rtx old = *curr_id->operand_loc[0];
4832 	      *curr_id->operand_loc[0]
4833 		= simplify_replace_fn_rtx (old, NULL_RTX,
4834 					   loc_equivalence_callback, curr_insn);
4835 	      if (old != *curr_id->operand_loc[0])
4836 		{
4837 		  lra_update_insn_regno_info (curr_insn);
4838 		  changed_p = true;
4839 		}
4840 	    }
4841 	}
4842       else if (INSN_P (curr_insn))
4843 	{
4844 	  if ((set = single_set (curr_insn)) != NULL_RTX)
4845 	    {
4846 	      dest_reg = SET_DEST (set);
4847 	      /* The equivalence pseudo could be set up as SUBREG in a
4848 		 case when it is a call restore insn in a mode
4849 		 different from the pseudo mode.  */
4850 	      if (GET_CODE (dest_reg) == SUBREG)
4851 		dest_reg = SUBREG_REG (dest_reg);
4852 	      if ((REG_P (dest_reg)
4853 		   && (x = get_equiv (dest_reg)) != dest_reg
4854 		   /* Remove insns which set up a pseudo whose value
4855 		      can not be changed.  Such insns might be not in
4856 		      init_insns because we don't update equiv data
4857 		      during insn transformations.
4858 
4859 		      As an example, let suppose that a pseudo got
4860 		      hard register and on the 1st pass was not
4861 		      changed to equivalent constant.  We generate an
4862 		      additional insn setting up the pseudo because of
4863 		      secondary memory movement.  Then the pseudo is
4864 		      spilled and we use the equiv constant.  In this
4865 		      case we should remove the additional insn and
4866 		      this insn is not init_insns list.  */
4867 		   && (! MEM_P (x) || MEM_READONLY_P (x)
4868 		       /* Check that this is actually an insn setting
4869 			  up the equivalence.  */
4870 		       || in_list_p (curr_insn,
4871 				     ira_reg_equiv
4872 				     [REGNO (dest_reg)].init_insns)))
4873 		  || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set))
4874 		      && in_list_p (curr_insn,
4875 				    ira_reg_equiv
4876 				    [REGNO (SET_SRC (set))].init_insns)))
4877 		{
4878 		  /* This is equiv init insn of pseudo which did not get a
4879 		     hard register -- remove the insn.	*/
4880 		  if (lra_dump_file != NULL)
4881 		    {
4882 		      fprintf (lra_dump_file,
4883 			       "      Removing equiv init insn %i (freq=%d)\n",
4884 			       INSN_UID (curr_insn),
4885 			       REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn)));
4886 		      dump_insn_slim (lra_dump_file, curr_insn);
4887 		    }
4888 		  if (contains_reg_p (x, true, false))
4889 		    lra_risky_transformations_p = true;
4890 		  lra_set_insn_deleted (curr_insn);
4891 		  continue;
4892 		}
4893 	    }
4894 	  curr_id = lra_get_insn_recog_data (curr_insn);
4895 	  curr_static_id = curr_id->insn_static_data;
4896 	  init_curr_insn_input_reloads ();
4897 	  init_curr_operand_mode ();
4898 	  if (curr_insn_transform (false))
4899 	    changed_p = true;
4900 	  /* Check non-transformed insns too for equiv change as USE
4901 	     or CLOBBER don't need reloads but can contain pseudos
4902 	     being changed on their equivalences.  */
4903 	  else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))
4904 		   && loc_equivalence_change_p (&PATTERN (curr_insn)))
4905 	    {
4906 	      lra_update_insn_regno_info (curr_insn);
4907 	      changed_p = true;
4908 	    }
4909 	}
4910     }
4911 
4912   /* If we used a new hard regno, changed_p should be true because the
4913      hard reg is assigned to a new pseudo.  */
4914   if (flag_checking && !changed_p)
4915     {
4916       for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4917 	if (lra_reg_info[i].nrefs != 0
4918 	    && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4919 	  {
4920 	    int j, nregs = hard_regno_nregs (hard_regno,
4921 					     PSEUDO_REGNO_MODE (i));
4922 
4923 	    for (j = 0; j < nregs; j++)
4924 	      lra_assert (df_regs_ever_live_p (hard_regno + j));
4925 	  }
4926     }
4927   return changed_p;
4928 }
4929 
4930 static void initiate_invariants (void);
4931 static void finish_invariants (void);
4932 
4933 /* Initiate the LRA constraint pass.  It is done once per
4934    function.  */
4935 void
4936 lra_constraints_init (void)
4937 {
4938   initiate_invariants ();
4939 }
4940 
4941 /* Finalize the LRA constraint pass.  It is done once per
4942    function.  */
4943 void
4944 lra_constraints_finish (void)
4945 {
4946   finish_invariants ();
4947 }
4948 
4949 
4950 
4951 /* Structure describes invariants for ineheritance.  */
4952 struct lra_invariant
4953 {
4954   /* The order number of the invariant.  */
4955   int num;
4956   /* The invariant RTX.  */
4957   rtx invariant_rtx;
4958   /* The origin insn of the invariant.  */
4959   rtx_insn *insn;
4960 };
4961 
4962 typedef lra_invariant invariant_t;
4963 typedef invariant_t *invariant_ptr_t;
4964 typedef const invariant_t *const_invariant_ptr_t;
4965 
4966 /* Pointer to the inheritance invariants.  */
4967 static vec<invariant_ptr_t> invariants;
4968 
4969 /* Allocation pool for the invariants.  */
4970 static object_allocator<lra_invariant> *invariants_pool;
4971 
4972 /* Hash table for the invariants.  */
4973 static htab_t invariant_table;
4974 
4975 /* Hash function for INVARIANT.  */
4976 static hashval_t
4977 invariant_hash (const void *invariant)
4978 {
4979   rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx;
4980   return lra_rtx_hash (inv);
4981 }
4982 
4983 /* Equal function for invariants INVARIANT1 and INVARIANT2.  */
4984 static int
4985 invariant_eq_p (const void *invariant1, const void *invariant2)
4986 {
4987   rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx;
4988   rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx;
4989 
4990   return rtx_equal_p (inv1, inv2);
4991 }
4992 
4993 /* Insert INVARIANT_RTX into the table if it is not there yet.  Return
4994    invariant which is in the table.  */
4995 static invariant_ptr_t
4996 insert_invariant (rtx invariant_rtx)
4997 {
4998   void **entry_ptr;
4999   invariant_t invariant;
5000   invariant_ptr_t invariant_ptr;
5001 
5002   invariant.invariant_rtx = invariant_rtx;
5003   entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT);
5004   if (*entry_ptr == NULL)
5005     {
5006       invariant_ptr = invariants_pool->allocate ();
5007       invariant_ptr->invariant_rtx = invariant_rtx;
5008       invariant_ptr->insn = NULL;
5009       invariants.safe_push (invariant_ptr);
5010       *entry_ptr = (void *) invariant_ptr;
5011     }
5012   return (invariant_ptr_t) *entry_ptr;
5013 }
5014 
5015 /* Initiate the invariant table.  */
5016 static void
5017 initiate_invariants (void)
5018 {
5019   invariants.create (100);
5020   invariants_pool
5021     = new object_allocator<lra_invariant> ("Inheritance invariants");
5022   invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL);
5023 }
5024 
5025 /* Finish the invariant table.  */
5026 static void
5027 finish_invariants (void)
5028 {
5029   htab_delete (invariant_table);
5030   delete invariants_pool;
5031   invariants.release ();
5032 }
5033 
5034 /* Make the invariant table empty.  */
5035 static void
5036 clear_invariants (void)
5037 {
5038   htab_empty (invariant_table);
5039   invariants_pool->release ();
5040   invariants.truncate (0);
5041 }
5042 
5043 
5044 
5045 /* This page contains code to do inheritance/split
5046    transformations.  */
5047 
5048 /* Number of reloads passed so far in current EBB.  */
5049 static int reloads_num;
5050 
5051 /* Number of calls passed so far in current EBB.  */
5052 static int calls_num;
5053 
5054 /* Current reload pseudo check for validity of elements in
5055    USAGE_INSNS.	 */
5056 static int curr_usage_insns_check;
5057 
5058 /* Info about last usage of registers in EBB to do inheritance/split
5059    transformation.  Inheritance transformation is done from a spilled
5060    pseudo and split transformations from a hard register or a pseudo
5061    assigned to a hard register.	 */
5062 struct usage_insns
5063 {
5064   /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5065      value INSNS is valid.  The insns is chain of optional debug insns
5066      and a finishing non-debug insn using the corresponding reg.  The
5067      value is also used to mark the registers which are set up in the
5068      current insn.  The negated insn uid is used for this.  */
5069   int check;
5070   /* Value of global reloads_num at the last insn in INSNS.  */
5071   int reloads_num;
5072   /* Value of global reloads_nums at the last insn in INSNS.  */
5073   int calls_num;
5074   /* It can be true only for splitting.	 And it means that the restore
5075      insn should be put after insn given by the following member.  */
5076   bool after_p;
5077   /* Next insns in the current EBB which use the original reg and the
5078      original reg value is not changed between the current insn and
5079      the next insns.  In order words, e.g. for inheritance, if we need
5080      to use the original reg value again in the next insns we can try
5081      to use the value in a hard register from a reload insn of the
5082      current insn.  */
5083   rtx insns;
5084 };
5085 
5086 /* Map: regno -> corresponding pseudo usage insns.  */
5087 static struct usage_insns *usage_insns;
5088 
5089 static void
5090 setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p)
5091 {
5092   usage_insns[regno].check = curr_usage_insns_check;
5093   usage_insns[regno].insns = insn;
5094   usage_insns[regno].reloads_num = reloads_num;
5095   usage_insns[regno].calls_num = calls_num;
5096   usage_insns[regno].after_p = after_p;
5097 }
5098 
5099 /* The function is used to form list REGNO usages which consists of
5100    optional debug insns finished by a non-debug insn using REGNO.
5101    RELOADS_NUM is current number of reload insns processed so far.  */
5102 static void
5103 add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num)
5104 {
5105   rtx next_usage_insns;
5106 
5107   if (usage_insns[regno].check == curr_usage_insns_check
5108       && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX
5109       && DEBUG_INSN_P (insn))
5110     {
5111       /* Check that we did not add the debug insn yet.	*/
5112       if (next_usage_insns != insn
5113 	  && (GET_CODE (next_usage_insns) != INSN_LIST
5114 	      || XEXP (next_usage_insns, 0) != insn))
5115 	usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn,
5116 						      next_usage_insns);
5117     }
5118   else if (NONDEBUG_INSN_P (insn))
5119     setup_next_usage_insn (regno, insn, reloads_num, false);
5120   else
5121     usage_insns[regno].check = 0;
5122 }
5123 
5124 /* Return first non-debug insn in list USAGE_INSNS.  */
5125 static rtx_insn *
5126 skip_usage_debug_insns (rtx usage_insns)
5127 {
5128   rtx insn;
5129 
5130   /* Skip debug insns.  */
5131   for (insn = usage_insns;
5132        insn != NULL_RTX && GET_CODE (insn) == INSN_LIST;
5133        insn = XEXP (insn, 1))
5134     ;
5135   return safe_as_a <rtx_insn *> (insn);
5136 }
5137 
5138 /* Return true if we need secondary memory moves for insn in
5139    USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5140    into the insn.  */
5141 static bool
5142 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED,
5143 				 rtx usage_insns ATTRIBUTE_UNUSED)
5144 {
5145   rtx_insn *insn;
5146   rtx set, dest;
5147   enum reg_class cl;
5148 
5149   if (inher_cl == ALL_REGS
5150       || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX)
5151     return false;
5152   lra_assert (INSN_P (insn));
5153   if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set)))
5154     return false;
5155   dest = SET_DEST (set);
5156   if (! REG_P (dest))
5157     return false;
5158   lra_assert (inher_cl != NO_REGS);
5159   cl = get_reg_class (REGNO (dest));
5160   return (cl != NO_REGS && cl != ALL_REGS
5161 	  && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl));
5162 }
5163 
5164 /* Registers involved in inheritance/split in the current EBB
5165    (inheritance/split pseudos and original registers).	*/
5166 static bitmap_head check_only_regs;
5167 
5168 /* Reload pseudos can not be involded in invariant inheritance in the
5169    current EBB.  */
5170 static bitmap_head invalid_invariant_regs;
5171 
5172 /* Do inheritance transformations for insn INSN, which defines (if
5173    DEF_P) or uses ORIGINAL_REGNO.  NEXT_USAGE_INSNS specifies which
5174    instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5175    form as the "insns" field of usage_insns.  Return true if we
5176    succeed in such transformation.
5177 
5178    The transformations look like:
5179 
5180      p <- ...		  i <- ...
5181      ...		  p <- i    (new insn)
5182      ...	     =>
5183      <- ... p ...	  <- ... i ...
5184    or
5185      ...		  i <- p    (new insn)
5186      <- ... p ...	  <- ... i ...
5187      ...	     =>
5188      <- ... p ...	  <- ... i ...
5189    where p is a spilled original pseudo and i is a new inheritance pseudo.
5190 
5191 
5192    The inheritance pseudo has the smallest class of two classes CL and
5193    class of ORIGINAL REGNO.  */
5194 static bool
5195 inherit_reload_reg (bool def_p, int original_regno,
5196 		    enum reg_class cl, rtx_insn *insn, rtx next_usage_insns)
5197 {
5198   if (optimize_function_for_size_p (cfun))
5199     return false;
5200 
5201   enum reg_class rclass = lra_get_allocno_class (original_regno);
5202   rtx original_reg = regno_reg_rtx[original_regno];
5203   rtx new_reg, usage_insn;
5204   rtx_insn *new_insns;
5205 
5206   lra_assert (! usage_insns[original_regno].after_p);
5207   if (lra_dump_file != NULL)
5208     fprintf (lra_dump_file,
5209 	     "    <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5210   if (! ira_reg_classes_intersect_p[cl][rclass])
5211     {
5212       if (lra_dump_file != NULL)
5213 	{
5214 	  fprintf (lra_dump_file,
5215 		   "    Rejecting inheritance for %d "
5216 		   "because of disjoint classes %s and %s\n",
5217 		   original_regno, reg_class_names[cl],
5218 		   reg_class_names[rclass]);
5219 	  fprintf (lra_dump_file,
5220 		   "    >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5221 	}
5222       return false;
5223     }
5224   if ((ira_class_subset_p[cl][rclass] && cl != rclass)
5225       /* We don't use a subset of two classes because it can be
5226 	 NO_REGS.  This transformation is still profitable in most
5227 	 cases even if the classes are not intersected as register
5228 	 move is probably cheaper than a memory load.  */
5229       || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass])
5230     {
5231       if (lra_dump_file != NULL)
5232 	fprintf (lra_dump_file, "    Use smallest class of %s and %s\n",
5233 		 reg_class_names[cl], reg_class_names[rclass]);
5234 
5235       rclass = cl;
5236     }
5237   if (check_secondary_memory_needed_p (rclass, next_usage_insns))
5238     {
5239       /* Reject inheritance resulting in secondary memory moves.
5240 	 Otherwise, there is a danger in LRA cycling.  Also such
5241 	 transformation will be unprofitable.  */
5242       if (lra_dump_file != NULL)
5243 	{
5244 	  rtx_insn *insn = skip_usage_debug_insns (next_usage_insns);
5245 	  rtx set = single_set (insn);
5246 
5247 	  lra_assert (set != NULL_RTX);
5248 
5249 	  rtx dest = SET_DEST (set);
5250 
5251 	  lra_assert (REG_P (dest));
5252 	  fprintf (lra_dump_file,
5253 		   "    Rejecting inheritance for insn %d(%s)<-%d(%s) "
5254 		   "as secondary mem is needed\n",
5255 		   REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))],
5256 		   original_regno, reg_class_names[rclass]);
5257 	  fprintf (lra_dump_file,
5258 		   "    >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5259 	}
5260       return false;
5261     }
5262   new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
5263 				rclass, "inheritance");
5264   start_sequence ();
5265   if (def_p)
5266     lra_emit_move (original_reg, new_reg);
5267   else
5268     lra_emit_move (new_reg, original_reg);
5269   new_insns = get_insns ();
5270   end_sequence ();
5271   if (NEXT_INSN (new_insns) != NULL_RTX)
5272     {
5273       if (lra_dump_file != NULL)
5274 	{
5275 	  fprintf (lra_dump_file,
5276 		   "    Rejecting inheritance %d->%d "
5277 		   "as it results in 2 or more insns:\n",
5278 		   original_regno, REGNO (new_reg));
5279 	  dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0);
5280 	  fprintf (lra_dump_file,
5281 		   "	>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5282 	}
5283       return false;
5284     }
5285   lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false);
5286   lra_update_insn_regno_info (insn);
5287   if (! def_p)
5288     /* We now have a new usage insn for original regno.  */
5289     setup_next_usage_insn (original_regno, new_insns, reloads_num, false);
5290   if (lra_dump_file != NULL)
5291     fprintf (lra_dump_file, "    Original reg change %d->%d (bb%d):\n",
5292 	     original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
5293   lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno];
5294   bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5295   bitmap_set_bit (&check_only_regs, original_regno);
5296   bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
5297   if (def_p)
5298     lra_process_new_insns (insn, NULL, new_insns,
5299 			   "Add original<-inheritance");
5300   else
5301     lra_process_new_insns (insn, new_insns, NULL,
5302 			   "Add inheritance<-original");
5303   while (next_usage_insns != NULL_RTX)
5304     {
5305       if (GET_CODE (next_usage_insns) != INSN_LIST)
5306 	{
5307 	  usage_insn = next_usage_insns;
5308 	  lra_assert (NONDEBUG_INSN_P (usage_insn));
5309 	  next_usage_insns = NULL;
5310 	}
5311       else
5312 	{
5313 	  usage_insn = XEXP (next_usage_insns, 0);
5314 	  lra_assert (DEBUG_INSN_P (usage_insn));
5315 	  next_usage_insns = XEXP (next_usage_insns, 1);
5316 	}
5317       lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
5318 			     DEBUG_INSN_P (usage_insn));
5319       lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5320       if (lra_dump_file != NULL)
5321 	{
5322 	  basic_block bb = BLOCK_FOR_INSN (usage_insn);
5323 	  fprintf (lra_dump_file,
5324 		   "    Inheritance reuse change %d->%d (bb%d):\n",
5325 		   original_regno, REGNO (new_reg),
5326 		   bb ? bb->index : -1);
5327 	  dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5328 	}
5329     }
5330   if (lra_dump_file != NULL)
5331     fprintf (lra_dump_file,
5332 	     "	  >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5333   return true;
5334 }
5335 
5336 /* Return true if we need a caller save/restore for pseudo REGNO which
5337    was assigned to a hard register.  */
5338 static inline bool
5339 need_for_call_save_p (int regno)
5340 {
5341   lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0);
5342   return (usage_insns[regno].calls_num < calls_num
5343 	  && (overlaps_hard_reg_set_p
5344 	      ((flag_ipa_ra &&
5345 		! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set))
5346 	       ? lra_reg_info[regno].actual_call_used_reg_set
5347 	       : call_used_reg_set,
5348 	       PSEUDO_REGNO_MODE (regno), reg_renumber[regno])
5349 	      || (targetm.hard_regno_call_part_clobbered
5350 		  (reg_renumber[regno], PSEUDO_REGNO_MODE (regno)))));
5351 }
5352 
5353 /* Global registers occurring in the current EBB.  */
5354 static bitmap_head ebb_global_regs;
5355 
5356 /* Return true if we need a split for hard register REGNO or pseudo
5357    REGNO which was assigned to a hard register.
5358    POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5359    used for reloads since the EBB end.	It is an approximation of the
5360    used hard registers in the split range.  The exact value would
5361    require expensive calculations.  If we were aggressive with
5362    splitting because of the approximation, the split pseudo will save
5363    the same hard register assignment and will be removed in the undo
5364    pass.  We still need the approximation because too aggressive
5365    splitting would result in too inaccurate cost calculation in the
5366    assignment pass because of too many generated moves which will be
5367    probably removed in the undo pass.  */
5368 static inline bool
5369 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
5370 {
5371   int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno];
5372 
5373   lra_assert (hard_regno >= 0);
5374   return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno)
5375 	   /* Don't split eliminable hard registers, otherwise we can
5376 	      split hard registers like hard frame pointer, which
5377 	      lives on BB start/end according to DF-infrastructure,
5378 	      when there is a pseudo assigned to the register and
5379 	      living in the same BB.  */
5380 	   && (regno >= FIRST_PSEUDO_REGISTER
5381 	       || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
5382 	   && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
5383 	   /* Don't split call clobbered hard regs living through
5384 	      calls, otherwise we might have a check problem in the
5385 	      assign sub-pass as in the most cases (exception is a
5386 	      situation when lra_risky_transformations_p value is
5387 	      true) the assign pass assumes that all pseudos living
5388 	      through calls are assigned to call saved hard regs.  */
5389 	   && (regno >= FIRST_PSEUDO_REGISTER
5390 	       || ! TEST_HARD_REG_BIT (call_used_reg_set, regno)
5391 	       || usage_insns[regno].calls_num == calls_num)
5392 	   /* We need at least 2 reloads to make pseudo splitting
5393 	      profitable.  We should provide hard regno splitting in
5394 	      any case to solve 1st insn scheduling problem when
5395 	      moving hard register definition up might result in
5396 	      impossibility to find hard register for reload pseudo of
5397 	      small register class.  */
5398 	   && (usage_insns[regno].reloads_num
5399 	       + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num)
5400 	   && (regno < FIRST_PSEUDO_REGISTER
5401 	       /* For short living pseudos, spilling + inheritance can
5402 		  be considered a substitution for splitting.
5403 		  Therefore we do not splitting for local pseudos.  It
5404 		  decreases also aggressiveness of splitting.  The
5405 		  minimal number of references is chosen taking into
5406 		  account that for 2 references splitting has no sense
5407 		  as we can just spill the pseudo.  */
5408 	       || (regno >= FIRST_PSEUDO_REGISTER
5409 		   && lra_reg_info[regno].nrefs > 3
5410 		   && bitmap_bit_p (&ebb_global_regs, regno))))
5411 	  || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno)));
5412 }
5413 
5414 /* Return class for the split pseudo created from original pseudo with
5415    ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO.	 We
5416    choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5417    results in no secondary memory movements.  */
5418 static enum reg_class
5419 choose_split_class (enum reg_class allocno_class,
5420 		    int hard_regno ATTRIBUTE_UNUSED,
5421 		    machine_mode mode ATTRIBUTE_UNUSED)
5422 {
5423   int i;
5424   enum reg_class cl, best_cl = NO_REGS;
5425   enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5426     = REGNO_REG_CLASS (hard_regno);
5427 
5428   if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class)
5429       && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno))
5430     return allocno_class;
5431   for (i = 0;
5432        (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES;
5433        i++)
5434     if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class)
5435 	&& ! targetm.secondary_memory_needed (mode, hard_reg_class, cl)
5436 	&& TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno)
5437 	&& (best_cl == NO_REGS
5438 	    || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl]))
5439       best_cl = cl;
5440   return best_cl;
5441 }
5442 
5443 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5444    It only makes sense to call this function if NEW_REGNO is always
5445    equal to ORIGINAL_REGNO.  */
5446 
5447 static void
5448 lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno)
5449 {
5450   if (!ira_reg_equiv[original_regno].defined_p)
5451     return;
5452 
5453   ira_expand_reg_equiv ();
5454   ira_reg_equiv[new_regno].defined_p = true;
5455   if (ira_reg_equiv[original_regno].memory)
5456     ira_reg_equiv[new_regno].memory
5457       = copy_rtx (ira_reg_equiv[original_regno].memory);
5458   if (ira_reg_equiv[original_regno].constant)
5459     ira_reg_equiv[new_regno].constant
5460       = copy_rtx (ira_reg_equiv[original_regno].constant);
5461   if (ira_reg_equiv[original_regno].invariant)
5462     ira_reg_equiv[new_regno].invariant
5463       = copy_rtx (ira_reg_equiv[original_regno].invariant);
5464 }
5465 
5466 /* Do split transformations for insn INSN, which defines or uses
5467    ORIGINAL_REGNO.  NEXT_USAGE_INSNS specifies which instruction in
5468    the EBB next uses ORIGINAL_REGNO; it has the same form as the
5469    "insns" field of usage_insns.  If TO is not NULL, we don't use
5470    usage_insns, we put restore insns after TO insn.
5471 
5472    The transformations look like:
5473 
5474      p <- ...		  p <- ...
5475      ...		  s <- p    (new insn -- save)
5476      ...	     =>
5477      ...		  p <- s    (new insn -- restore)
5478      <- ... p ...	  <- ... p ...
5479    or
5480      <- ... p ...	  <- ... p ...
5481      ...		  s <- p    (new insn -- save)
5482      ...	     =>
5483      ...		  p <- s    (new insn -- restore)
5484      <- ... p ...	  <- ... p ...
5485 
5486    where p is an original pseudo got a hard register or a hard
5487    register and s is a new split pseudo.  The save is put before INSN
5488    if BEFORE_P is true.	 Return true if we succeed in such
5489    transformation.  */
5490 static bool
5491 split_reg (bool before_p, int original_regno, rtx_insn *insn,
5492 	   rtx next_usage_insns, rtx_insn *to)
5493 {
5494   enum reg_class rclass;
5495   rtx original_reg;
5496   int hard_regno, nregs;
5497   rtx new_reg, usage_insn;
5498   rtx_insn *restore, *save;
5499   bool after_p;
5500   bool call_save_p;
5501   machine_mode mode;
5502 
5503   if (original_regno < FIRST_PSEUDO_REGISTER)
5504     {
5505       rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)];
5506       hard_regno = original_regno;
5507       call_save_p = false;
5508       nregs = 1;
5509       mode = lra_reg_info[hard_regno].biggest_mode;
5510       machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]);
5511       /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5512 	 as part of a multi-word register.  In that case, or if the biggest
5513 	 mode was larger than a register, just use the reg_rtx.  Otherwise,
5514 	 limit the size to that of the biggest access in the function.  */
5515       if (mode == VOIDmode
5516 	  || paradoxical_subreg_p (mode, reg_rtx_mode))
5517 	{
5518 	  original_reg = regno_reg_rtx[hard_regno];
5519 	  mode = reg_rtx_mode;
5520 	}
5521       else
5522 	original_reg = gen_rtx_REG (mode, hard_regno);
5523     }
5524   else
5525     {
5526       mode = PSEUDO_REGNO_MODE (original_regno);
5527       hard_regno = reg_renumber[original_regno];
5528       nregs = hard_regno_nregs (hard_regno, mode);
5529       rclass = lra_get_allocno_class (original_regno);
5530       original_reg = regno_reg_rtx[original_regno];
5531       call_save_p = need_for_call_save_p (original_regno);
5532     }
5533   lra_assert (hard_regno >= 0);
5534   if (lra_dump_file != NULL)
5535     fprintf (lra_dump_file,
5536 	     "	  ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5537 
5538   if (call_save_p)
5539     {
5540       mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno,
5541 					  hard_regno_nregs (hard_regno, mode),
5542 					  mode);
5543       new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save");
5544     }
5545   else
5546     {
5547       rclass = choose_split_class (rclass, hard_regno, mode);
5548       if (rclass == NO_REGS)
5549 	{
5550 	  if (lra_dump_file != NULL)
5551 	    {
5552 	      fprintf (lra_dump_file,
5553 		       "    Rejecting split of %d(%s): "
5554 		       "no good reg class for %d(%s)\n",
5555 		       original_regno,
5556 		       reg_class_names[lra_get_allocno_class (original_regno)],
5557 		       hard_regno,
5558 		       reg_class_names[REGNO_REG_CLASS (hard_regno)]);
5559 	      fprintf
5560 		(lra_dump_file,
5561 		 "    ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5562 	    }
5563 	  return false;
5564 	}
5565       /* Split_if_necessary can split hard registers used as part of a
5566 	 multi-register mode but splits each register individually.  The
5567 	 mode used for each independent register may not be supported
5568 	 so reject the split.  Splitting the wider mode should theoretically
5569 	 be possible but is not implemented.  */
5570       if (!targetm.hard_regno_mode_ok (hard_regno, mode))
5571 	{
5572 	  if (lra_dump_file != NULL)
5573 	    {
5574 	      fprintf (lra_dump_file,
5575 		       "    Rejecting split of %d(%s): unsuitable mode %s\n",
5576 		       original_regno,
5577 		       reg_class_names[lra_get_allocno_class (original_regno)],
5578 		       GET_MODE_NAME (mode));
5579 	      fprintf
5580 		(lra_dump_file,
5581 		 "    ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5582 	    }
5583 	  return false;
5584 	}
5585       new_reg = lra_create_new_reg (mode, original_reg, rclass, "split");
5586       reg_renumber[REGNO (new_reg)] = hard_regno;
5587     }
5588   int new_regno = REGNO (new_reg);
5589   save = emit_spill_move (true, new_reg, original_reg);
5590   if (NEXT_INSN (save) != NULL_RTX && !call_save_p)
5591     {
5592       if (lra_dump_file != NULL)
5593 	{
5594 	  fprintf
5595 	    (lra_dump_file,
5596 	     "	  Rejecting split %d->%d resulting in > 2 save insns:\n",
5597 	     original_regno, new_regno);
5598 	  dump_rtl_slim (lra_dump_file, save, NULL, -1, 0);
5599 	  fprintf (lra_dump_file,
5600 		   "	))))))))))))))))))))))))))))))))))))))))))))))))\n");
5601 	}
5602       return false;
5603     }
5604   restore = emit_spill_move (false, new_reg, original_reg);
5605   if (NEXT_INSN (restore) != NULL_RTX && !call_save_p)
5606     {
5607       if (lra_dump_file != NULL)
5608 	{
5609 	  fprintf (lra_dump_file,
5610 		   "	Rejecting split %d->%d "
5611 		   "resulting in > 2 restore insns:\n",
5612 		   original_regno, new_regno);
5613 	  dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0);
5614 	  fprintf (lra_dump_file,
5615 		   "	))))))))))))))))))))))))))))))))))))))))))))))))\n");
5616 	}
5617       return false;
5618     }
5619   /* Transfer equivalence information to the spill register, so that
5620      if we fail to allocate the spill register, we have the option of
5621      rematerializing the original value instead of spilling to the stack.  */
5622   if (!HARD_REGISTER_NUM_P (original_regno)
5623       && mode == PSEUDO_REGNO_MODE (original_regno))
5624     lra_copy_reg_equiv (new_regno, original_regno);
5625   lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno];
5626   bitmap_set_bit (&check_only_regs, new_regno);
5627   bitmap_set_bit (&check_only_regs, original_regno);
5628   bitmap_set_bit (&lra_split_regs, new_regno);
5629   if (to != NULL)
5630     {
5631       usage_insn = to;
5632       after_p = TRUE;
5633     }
5634   else
5635     {
5636       after_p = usage_insns[original_regno].after_p;
5637       for (;;)
5638 	{
5639 	  if (GET_CODE (next_usage_insns) != INSN_LIST)
5640 	    {
5641 	      usage_insn = next_usage_insns;
5642 	      break;
5643 	    }
5644 	  usage_insn = XEXP (next_usage_insns, 0);
5645 	  lra_assert (DEBUG_INSN_P (usage_insn));
5646 	  next_usage_insns = XEXP (next_usage_insns, 1);
5647 	  lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
5648 				 true);
5649 	  lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5650 	  if (lra_dump_file != NULL)
5651 	    {
5652 	      fprintf (lra_dump_file, "    Split reuse change %d->%d:\n",
5653 		       original_regno, new_regno);
5654 	      dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5655 	    }
5656 	}
5657     }
5658   lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn));
5659   lra_assert (usage_insn != insn || (after_p && before_p));
5660   lra_process_new_insns (as_a <rtx_insn *> (usage_insn),
5661 			 after_p ? NULL : restore,
5662 			 after_p ? restore : NULL,
5663 			 call_save_p
5664 			 ?  "Add reg<-save" : "Add reg<-split");
5665   lra_process_new_insns (insn, before_p ? save : NULL,
5666 			 before_p ? NULL : save,
5667 			 call_save_p
5668 			 ?  "Add save<-reg" : "Add split<-reg");
5669   if (nregs > 1)
5670     /* If we are trying to split multi-register.  We should check
5671        conflicts on the next assignment sub-pass.  IRA can allocate on
5672        sub-register levels, LRA do this on pseudos level right now and
5673        this discrepancy may create allocation conflicts after
5674        splitting.  */
5675     lra_risky_transformations_p = true;
5676   if (lra_dump_file != NULL)
5677     fprintf (lra_dump_file,
5678 	     "	  ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5679   return true;
5680 }
5681 
5682 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
5683    in the range [FROM, TO].  Return true if did a split.  Otherwise,
5684    return false.  */
5685 bool
5686 spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to)
5687 {
5688   int i, hard_regno;
5689   int rclass_size;
5690   rtx_insn *insn;
5691   unsigned int uid;
5692   bitmap_iterator bi;
5693   HARD_REG_SET ignore;
5694 
5695   lra_assert (from != NULL && to != NULL);
5696   CLEAR_HARD_REG_SET (ignore);
5697   EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
5698     {
5699       lra_insn_recog_data_t id = lra_insn_recog_data[uid];
5700       struct lra_static_insn_data *static_id = id->insn_static_data;
5701       struct lra_insn_reg *reg;
5702 
5703       for (reg = id->regs; reg != NULL; reg = reg->next)
5704 	if (reg->regno <= FIRST_PSEUDO_REGISTER)
5705 	  SET_HARD_REG_BIT (ignore, reg->regno);
5706       for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
5707 	SET_HARD_REG_BIT (ignore, reg->regno);
5708     }
5709   rclass_size = ira_class_hard_regs_num[rclass];
5710   for (i = 0; i < rclass_size; i++)
5711     {
5712       hard_regno = ira_class_hard_regs[rclass][i];
5713       if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno)
5714 	  || TEST_HARD_REG_BIT (ignore, hard_regno))
5715 	continue;
5716       for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn))
5717 	if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap,
5718 			  INSN_UID (insn)))
5719 	  break;
5720       if (insn != NEXT_INSN (to))
5721 	continue;
5722       if (split_reg (TRUE, hard_regno, from, NULL, to))
5723 	return true;
5724     }
5725   return false;
5726 }
5727 
5728 /* Recognize that we need a split transformation for insn INSN, which
5729    defines or uses REGNO in its insn biggest MODE (we use it only if
5730    REGNO is a hard register).  POTENTIAL_RELOAD_HARD_REGS contains
5731    hard registers which might be used for reloads since the EBB end.
5732    Put the save before INSN if BEFORE_P is true.  MAX_UID is maximla
5733    uid before starting INSN processing.  Return true if we succeed in
5734    such transformation.  */
5735 static bool
5736 split_if_necessary (int regno, machine_mode mode,
5737 		    HARD_REG_SET potential_reload_hard_regs,
5738 		    bool before_p, rtx_insn *insn, int max_uid)
5739 {
5740   bool res = false;
5741   int i, nregs = 1;
5742   rtx next_usage_insns;
5743 
5744   if (regno < FIRST_PSEUDO_REGISTER)
5745     nregs = hard_regno_nregs (regno, mode);
5746   for (i = 0; i < nregs; i++)
5747     if (usage_insns[regno + i].check == curr_usage_insns_check
5748 	&& (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX
5749 	/* To avoid processing the register twice or more.  */
5750 	&& ((GET_CODE (next_usage_insns) != INSN_LIST
5751 	     && INSN_UID (next_usage_insns) < max_uid)
5752 	    || (GET_CODE (next_usage_insns) == INSN_LIST
5753 		&& (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid)))
5754 	&& need_for_split_p (potential_reload_hard_regs, regno + i)
5755 	&& split_reg (before_p, regno + i, insn, next_usage_insns, NULL))
5756     res = true;
5757   return res;
5758 }
5759 
5760 /* Return TRUE if rtx X is considered as an invariant for
5761    inheritance.  */
5762 static bool
5763 invariant_p (const_rtx x)
5764 {
5765   machine_mode mode;
5766   const char *fmt;
5767   enum rtx_code code;
5768   int i, j;
5769 
5770   code = GET_CODE (x);
5771   mode = GET_MODE (x);
5772   if (code == SUBREG)
5773     {
5774       x = SUBREG_REG (x);
5775       code = GET_CODE (x);
5776       mode = wider_subreg_mode (mode, GET_MODE (x));
5777     }
5778 
5779   if (MEM_P (x))
5780     return false;
5781 
5782   if (REG_P (x))
5783     {
5784       int i, nregs, regno = REGNO (x);
5785 
5786       if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM
5787 	  || TEST_HARD_REG_BIT (eliminable_regset, regno)
5788 	  || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
5789 	return false;
5790       nregs = hard_regno_nregs (regno, mode);
5791       for (i = 0; i < nregs; i++)
5792 	if (! fixed_regs[regno + i]
5793 	    /* A hard register may be clobbered in the current insn
5794 	       but we can ignore this case because if the hard
5795 	       register is used it should be set somewhere after the
5796 	       clobber.  */
5797 	    || bitmap_bit_p (&invalid_invariant_regs, regno + i))
5798 	  return false;
5799     }
5800   fmt = GET_RTX_FORMAT (code);
5801   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5802     {
5803       if (fmt[i] == 'e')
5804 	{
5805 	  if (! invariant_p (XEXP (x, i)))
5806 	    return false;
5807 	}
5808       else if (fmt[i] == 'E')
5809 	{
5810 	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5811 	    if (! invariant_p (XVECEXP (x, i, j)))
5812 	      return false;
5813 	}
5814     }
5815   return true;
5816 }
5817 
5818 /* We have 'dest_reg <- invariant'.  Let us try to make an invariant
5819    inheritance transformation (using dest_reg instead invariant in a
5820    subsequent insn).  */
5821 static bool
5822 process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx)
5823 {
5824   invariant_ptr_t invariant_ptr;
5825   rtx_insn *insn, *new_insns;
5826   rtx insn_set, insn_reg, new_reg;
5827   int insn_regno;
5828   bool succ_p = false;
5829   int dst_regno = REGNO (dst_reg);
5830   machine_mode dst_mode = GET_MODE (dst_reg);
5831   enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl;
5832 
5833   invariant_ptr = insert_invariant (invariant_rtx);
5834   if ((insn = invariant_ptr->insn) != NULL_RTX)
5835     {
5836       /* We have a subsequent insn using the invariant.  */
5837       insn_set = single_set (insn);
5838       lra_assert (insn_set != NULL);
5839       insn_reg = SET_DEST (insn_set);
5840       lra_assert (REG_P (insn_reg));
5841       insn_regno = REGNO (insn_reg);
5842       insn_reg_cl = lra_get_allocno_class (insn_regno);
5843 
5844       if (dst_mode == GET_MODE (insn_reg)
5845 	  /* We should consider only result move reg insns which are
5846 	     cheap.  */
5847 	  && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2
5848 	  && targetm.register_move_cost (dst_mode, cl, cl) == 2)
5849 	{
5850 	  if (lra_dump_file != NULL)
5851 	    fprintf (lra_dump_file,
5852 		     "    [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5853 	  new_reg = lra_create_new_reg (dst_mode, dst_reg,
5854 					cl, "invariant inheritance");
5855 	  bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
5856 	  bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5857 	  lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn);
5858 	  start_sequence ();
5859 	  lra_emit_move (new_reg, dst_reg);
5860 	  new_insns = get_insns ();
5861 	  end_sequence ();
5862 	  lra_process_new_insns (curr_insn, NULL, new_insns,
5863 				 "Add invariant inheritance<-original");
5864 	  start_sequence ();
5865 	  lra_emit_move (SET_DEST (insn_set), new_reg);
5866 	  new_insns = get_insns ();
5867 	  end_sequence ();
5868 	  lra_process_new_insns (insn, NULL, new_insns,
5869 				 "Changing reload<-inheritance");
5870 	  lra_set_insn_deleted (insn);
5871 	  succ_p = true;
5872 	  if (lra_dump_file != NULL)
5873 	    {
5874 	      fprintf (lra_dump_file,
5875 		       "    Invariant inheritance reuse change %d (bb%d):\n",
5876 		       REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
5877 	      dump_insn_slim (lra_dump_file, insn);
5878 	      fprintf (lra_dump_file,
5879 		       "	  ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5880 	    }
5881 	}
5882     }
5883   invariant_ptr->insn = curr_insn;
5884   return succ_p;
5885 }
5886 
5887 /* Check only registers living at the current program point in the
5888    current EBB.	 */
5889 static bitmap_head live_regs;
5890 
5891 /* Update live info in EBB given by its HEAD and TAIL insns after
5892    inheritance/split transformation.  The function removes dead moves
5893    too.	 */
5894 static void
5895 update_ebb_live_info (rtx_insn *head, rtx_insn *tail)
5896 {
5897   unsigned int j;
5898   int i, regno;
5899   bool live_p;
5900   rtx_insn *prev_insn;
5901   rtx set;
5902   bool remove_p;
5903   basic_block last_bb, prev_bb, curr_bb;
5904   bitmap_iterator bi;
5905   struct lra_insn_reg *reg;
5906   edge e;
5907   edge_iterator ei;
5908 
5909   last_bb = BLOCK_FOR_INSN (tail);
5910   prev_bb = NULL;
5911   for (curr_insn = tail;
5912        curr_insn != PREV_INSN (head);
5913        curr_insn = prev_insn)
5914     {
5915       prev_insn = PREV_INSN (curr_insn);
5916       /* We need to process empty blocks too.  They contain
5917 	 NOTE_INSN_BASIC_BLOCK referring for the basic block.  */
5918       if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK)
5919 	continue;
5920       curr_bb = BLOCK_FOR_INSN (curr_insn);
5921       if (curr_bb != prev_bb)
5922 	{
5923 	  if (prev_bb != NULL)
5924 	    {
5925 	      /* Update df_get_live_in (prev_bb):  */
5926 	      EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5927 		if (bitmap_bit_p (&live_regs, j))
5928 		  bitmap_set_bit (df_get_live_in (prev_bb), j);
5929 		else
5930 		  bitmap_clear_bit (df_get_live_in (prev_bb), j);
5931 	    }
5932 	  if (curr_bb != last_bb)
5933 	    {
5934 	      /* Update df_get_live_out (curr_bb):  */
5935 	      EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5936 		{
5937 		  live_p = bitmap_bit_p (&live_regs, j);
5938 		  if (! live_p)
5939 		    FOR_EACH_EDGE (e, ei, curr_bb->succs)
5940 		      if (bitmap_bit_p (df_get_live_in (e->dest), j))
5941 			{
5942 			  live_p = true;
5943 			  break;
5944 			}
5945 		  if (live_p)
5946 		    bitmap_set_bit (df_get_live_out (curr_bb), j);
5947 		  else
5948 		    bitmap_clear_bit (df_get_live_out (curr_bb), j);
5949 		}
5950 	    }
5951 	  prev_bb = curr_bb;
5952 	  bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb));
5953 	}
5954       if (! NONDEBUG_INSN_P (curr_insn))
5955 	continue;
5956       curr_id = lra_get_insn_recog_data (curr_insn);
5957       curr_static_id = curr_id->insn_static_data;
5958       remove_p = false;
5959       if ((set = single_set (curr_insn)) != NULL_RTX
5960 	  && REG_P (SET_DEST (set))
5961 	  && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER
5962 	  && SET_DEST (set) != pic_offset_table_rtx
5963 	  && bitmap_bit_p (&check_only_regs, regno)
5964 	  && ! bitmap_bit_p (&live_regs, regno))
5965 	remove_p = true;
5966       /* See which defined values die here.  */
5967       for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5968 	if (reg->type == OP_OUT && ! reg->subreg_p)
5969 	  bitmap_clear_bit (&live_regs, reg->regno);
5970       for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5971 	if (reg->type == OP_OUT && ! reg->subreg_p)
5972 	  bitmap_clear_bit (&live_regs, reg->regno);
5973       if (curr_id->arg_hard_regs != NULL)
5974 	/* Make clobbered argument hard registers die.  */
5975 	for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5976 	  if (regno >= FIRST_PSEUDO_REGISTER)
5977 	    bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER);
5978       /* Mark each used value as live.  */
5979       for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5980 	if (reg->type != OP_OUT
5981 	    && bitmap_bit_p (&check_only_regs, reg->regno))
5982 	  bitmap_set_bit (&live_regs, reg->regno);
5983       for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5984 	if (reg->type != OP_OUT
5985 	    && bitmap_bit_p (&check_only_regs, reg->regno))
5986 	  bitmap_set_bit (&live_regs, reg->regno);
5987       if (curr_id->arg_hard_regs != NULL)
5988 	/* Make used argument hard registers live.  */
5989 	for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5990 	  if (regno < FIRST_PSEUDO_REGISTER
5991 	      && bitmap_bit_p (&check_only_regs, regno))
5992 	    bitmap_set_bit (&live_regs, regno);
5993       /* It is quite important to remove dead move insns because it
5994 	 means removing dead store.  We don't need to process them for
5995 	 constraints.  */
5996       if (remove_p)
5997 	{
5998 	  if (lra_dump_file != NULL)
5999 	    {
6000 	      fprintf (lra_dump_file, "	    Removing dead insn:\n ");
6001 	      dump_insn_slim (lra_dump_file, curr_insn);
6002 	    }
6003 	  lra_set_insn_deleted (curr_insn);
6004 	}
6005     }
6006 }
6007 
6008 /* The structure describes info to do an inheritance for the current
6009    insn.  We need to collect such info first before doing the
6010    transformations because the transformations change the insn
6011    internal representation.  */
6012 struct to_inherit
6013 {
6014   /* Original regno.  */
6015   int regno;
6016   /* Subsequent insns which can inherit original reg value.  */
6017   rtx insns;
6018 };
6019 
6020 /* Array containing all info for doing inheritance from the current
6021    insn.  */
6022 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS];
6023 
6024 /* Number elements in the previous array.  */
6025 static int to_inherit_num;
6026 
6027 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6028    structure to_inherit.  */
6029 static void
6030 add_to_inherit (int regno, rtx insns)
6031 {
6032   int i;
6033 
6034   for (i = 0; i < to_inherit_num; i++)
6035     if (to_inherit[i].regno == regno)
6036       return;
6037   lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS);
6038   to_inherit[to_inherit_num].regno = regno;
6039   to_inherit[to_inherit_num++].insns = insns;
6040 }
6041 
6042 /* Return the last non-debug insn in basic block BB, or the block begin
6043    note if none.  */
6044 static rtx_insn *
6045 get_last_insertion_point (basic_block bb)
6046 {
6047   rtx_insn *insn;
6048 
6049   FOR_BB_INSNS_REVERSE (bb, insn)
6050     if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn))
6051       return insn;
6052   gcc_unreachable ();
6053 }
6054 
6055 /* Set up RES by registers living on edges FROM except the edge (FROM,
6056    TO) or by registers set up in a jump insn in BB FROM.  */
6057 static void
6058 get_live_on_other_edges (basic_block from, basic_block to, bitmap res)
6059 {
6060   rtx_insn *last;
6061   struct lra_insn_reg *reg;
6062   edge e;
6063   edge_iterator ei;
6064 
6065   lra_assert (to != NULL);
6066   bitmap_clear (res);
6067   FOR_EACH_EDGE (e, ei, from->succs)
6068     if (e->dest != to)
6069       bitmap_ior_into (res, df_get_live_in (e->dest));
6070   last = get_last_insertion_point (from);
6071   if (! JUMP_P (last))
6072     return;
6073   curr_id = lra_get_insn_recog_data (last);
6074   for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6075     if (reg->type != OP_IN)
6076       bitmap_set_bit (res, reg->regno);
6077 }
6078 
6079 /* Used as a temporary results of some bitmap calculations.  */
6080 static bitmap_head temp_bitmap;
6081 
6082 /* We split for reloads of small class of hard regs.  The following
6083    defines how many hard regs the class should have to be qualified as
6084    small.  The code is mostly oriented to x86/x86-64 architecture
6085    where some insns need to use only specific register or pair of
6086    registers and these register can live in RTL explicitly, e.g. for
6087    parameter passing.  */
6088 static const int max_small_class_regs_num = 2;
6089 
6090 /* Do inheritance/split transformations in EBB starting with HEAD and
6091    finishing on TAIL.  We process EBB insns in the reverse order.
6092    Return true if we did any inheritance/split transformation in the
6093    EBB.
6094 
6095    We should avoid excessive splitting which results in worse code
6096    because of inaccurate cost calculations for spilling new split
6097    pseudos in such case.  To achieve this we do splitting only if
6098    register pressure is high in given basic block and there are reload
6099    pseudos requiring hard registers.  We could do more register
6100    pressure calculations at any given program point to avoid necessary
6101    splitting even more but it is to expensive and the current approach
6102    works well enough.  */
6103 static bool
6104 inherit_in_ebb (rtx_insn *head, rtx_insn *tail)
6105 {
6106   int i, src_regno, dst_regno, nregs;
6107   bool change_p, succ_p, update_reloads_num_p;
6108   rtx_insn *prev_insn, *last_insn;
6109   rtx next_usage_insns, curr_set;
6110   enum reg_class cl;
6111   struct lra_insn_reg *reg;
6112   basic_block last_processed_bb, curr_bb = NULL;
6113   HARD_REG_SET potential_reload_hard_regs, live_hard_regs;
6114   bitmap to_process;
6115   unsigned int j;
6116   bitmap_iterator bi;
6117   bool head_p, after_p;
6118 
6119   change_p = false;
6120   curr_usage_insns_check++;
6121   clear_invariants ();
6122   reloads_num = calls_num = 0;
6123   bitmap_clear (&check_only_regs);
6124   bitmap_clear (&invalid_invariant_regs);
6125   last_processed_bb = NULL;
6126   CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6127   COPY_HARD_REG_SET (live_hard_regs, eliminable_regset);
6128   IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs);
6129   /* We don't process new insns generated in the loop.	*/
6130   for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
6131     {
6132       prev_insn = PREV_INSN (curr_insn);
6133       if (BLOCK_FOR_INSN (curr_insn) != NULL)
6134 	curr_bb = BLOCK_FOR_INSN (curr_insn);
6135       if (last_processed_bb != curr_bb)
6136 	{
6137 	  /* We are at the end of BB.  Add qualified living
6138 	     pseudos for potential splitting.  */
6139 	  to_process = df_get_live_out (curr_bb);
6140 	  if (last_processed_bb != NULL)
6141 	    {
6142 	      /* We are somewhere in the middle of EBB.	 */
6143 	      get_live_on_other_edges (curr_bb, last_processed_bb,
6144 				       &temp_bitmap);
6145 	      to_process = &temp_bitmap;
6146 	    }
6147 	  last_processed_bb = curr_bb;
6148 	  last_insn = get_last_insertion_point (curr_bb);
6149 	  after_p = (! JUMP_P (last_insn)
6150 		     && (! CALL_P (last_insn)
6151 			 || (find_reg_note (last_insn,
6152 					   REG_NORETURN, NULL_RTX) == NULL_RTX
6153 			     && ! SIBLING_CALL_P (last_insn))));
6154 	  CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6155 	  EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6156 	    {
6157 	      if ((int) j >= lra_constraint_new_regno_start)
6158 		break;
6159 	      if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6160 		{
6161 		  if (j < FIRST_PSEUDO_REGISTER)
6162 		    SET_HARD_REG_BIT (live_hard_regs, j);
6163 		  else
6164 		    add_to_hard_reg_set (&live_hard_regs,
6165 					 PSEUDO_REGNO_MODE (j),
6166 					 reg_renumber[j]);
6167 		  setup_next_usage_insn (j, last_insn, reloads_num, after_p);
6168 		}
6169 	    }
6170 	}
6171       src_regno = dst_regno = -1;
6172       curr_set = single_set (curr_insn);
6173       if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set)))
6174 	dst_regno = REGNO (SET_DEST (curr_set));
6175       if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set)))
6176 	src_regno = REGNO (SET_SRC (curr_set));
6177       update_reloads_num_p = true;
6178       if (src_regno < lra_constraint_new_regno_start
6179 	  && src_regno >= FIRST_PSEUDO_REGISTER
6180 	  && reg_renumber[src_regno] < 0
6181 	  && dst_regno >= lra_constraint_new_regno_start
6182 	  && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS)
6183 	{
6184 	  /* 'reload_pseudo <- original_pseudo'.  */
6185 	  if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6186 	    reloads_num++;
6187 	  update_reloads_num_p = false;
6188 	  succ_p = false;
6189 	  if (usage_insns[src_regno].check == curr_usage_insns_check
6190 	      && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX)
6191 	    succ_p = inherit_reload_reg (false, src_regno, cl,
6192 					 curr_insn, next_usage_insns);
6193 	  if (succ_p)
6194 	    change_p = true;
6195 	  else
6196 	    setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6197 	  if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6198 	    IOR_HARD_REG_SET (potential_reload_hard_regs,
6199 			      reg_class_contents[cl]);
6200 	}
6201       else if (src_regno < 0
6202 	       && dst_regno >= lra_constraint_new_regno_start
6203 	       && invariant_p (SET_SRC (curr_set))
6204 	       && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS
6205 	       && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno)
6206 	       && ! bitmap_bit_p (&invalid_invariant_regs,
6207 				  ORIGINAL_REGNO(regno_reg_rtx[dst_regno])))
6208 	{
6209 	  /* 'reload_pseudo <- invariant'.  */
6210 	  if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6211 	    reloads_num++;
6212 	  update_reloads_num_p = false;
6213 	  if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set)))
6214 	    change_p = true;
6215 	  if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6216 	    IOR_HARD_REG_SET (potential_reload_hard_regs,
6217 			      reg_class_contents[cl]);
6218 	}
6219       else if (src_regno >= lra_constraint_new_regno_start
6220 	       && dst_regno < lra_constraint_new_regno_start
6221 	       && dst_regno >= FIRST_PSEUDO_REGISTER
6222 	       && reg_renumber[dst_regno] < 0
6223 	       && (cl = lra_get_allocno_class (src_regno)) != NO_REGS
6224 	       && usage_insns[dst_regno].check == curr_usage_insns_check
6225 	       && (next_usage_insns
6226 		   = usage_insns[dst_regno].insns) != NULL_RTX)
6227 	{
6228 	  if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6229 	    reloads_num++;
6230 	  update_reloads_num_p = false;
6231 	  /* 'original_pseudo <- reload_pseudo'.  */
6232 	  if (! JUMP_P (curr_insn)
6233 	      && inherit_reload_reg (true, dst_regno, cl,
6234 				     curr_insn, next_usage_insns))
6235 	    change_p = true;
6236 	  /* Invalidate.  */
6237 	  usage_insns[dst_regno].check = 0;
6238 	  if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6239 	    IOR_HARD_REG_SET (potential_reload_hard_regs,
6240 			      reg_class_contents[cl]);
6241 	}
6242       else if (INSN_P (curr_insn))
6243 	{
6244 	  int iter;
6245 	  int max_uid = get_max_uid ();
6246 
6247 	  curr_id = lra_get_insn_recog_data (curr_insn);
6248 	  curr_static_id = curr_id->insn_static_data;
6249 	  to_inherit_num = 0;
6250 	  /* Process insn definitions.	*/
6251 	  for (iter = 0; iter < 2; iter++)
6252 	    for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6253 		 reg != NULL;
6254 		 reg = reg->next)
6255 	      if (reg->type != OP_IN
6256 		  && (dst_regno = reg->regno) < lra_constraint_new_regno_start)
6257 		{
6258 		  if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT
6259 		      && reg_renumber[dst_regno] < 0 && ! reg->subreg_p
6260 		      && usage_insns[dst_regno].check == curr_usage_insns_check
6261 		      && (next_usage_insns
6262 			  = usage_insns[dst_regno].insns) != NULL_RTX)
6263 		    {
6264 		      struct lra_insn_reg *r;
6265 
6266 		      for (r = curr_id->regs; r != NULL; r = r->next)
6267 			if (r->type != OP_OUT && r->regno == dst_regno)
6268 			  break;
6269 		      /* Don't do inheritance if the pseudo is also
6270 			 used in the insn.  */
6271 		      if (r == NULL)
6272 			/* We can not do inheritance right now
6273 			   because the current insn reg info (chain
6274 			   regs) can change after that.  */
6275 			add_to_inherit (dst_regno, next_usage_insns);
6276 		    }
6277 		  /* We can not process one reg twice here because of
6278 		     usage_insns invalidation.  */
6279 		  if ((dst_regno < FIRST_PSEUDO_REGISTER
6280 		       || reg_renumber[dst_regno] >= 0)
6281 		      && ! reg->subreg_p && reg->type != OP_IN)
6282 		    {
6283 		      HARD_REG_SET s;
6284 
6285 		      if (split_if_necessary (dst_regno, reg->biggest_mode,
6286 					      potential_reload_hard_regs,
6287 					      false, curr_insn, max_uid))
6288 			change_p = true;
6289 		      CLEAR_HARD_REG_SET (s);
6290 		      if (dst_regno < FIRST_PSEUDO_REGISTER)
6291 			add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno);
6292 		      else
6293 			add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
6294 					     reg_renumber[dst_regno]);
6295 		      AND_COMPL_HARD_REG_SET (live_hard_regs, s);
6296 		    }
6297 		  /* We should invalidate potential inheritance or
6298 		     splitting for the current insn usages to the next
6299 		     usage insns (see code below) as the output pseudo
6300 		     prevents this.  */
6301 		  if ((dst_regno >= FIRST_PSEUDO_REGISTER
6302 		       && reg_renumber[dst_regno] < 0)
6303 		      || (reg->type == OP_OUT && ! reg->subreg_p
6304 			  && (dst_regno < FIRST_PSEUDO_REGISTER
6305 			      || reg_renumber[dst_regno] >= 0)))
6306 		    {
6307 		      /* Invalidate and mark definitions.  */
6308 		      if (dst_regno >= FIRST_PSEUDO_REGISTER)
6309 			usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn);
6310 		      else
6311 			{
6312 			  nregs = hard_regno_nregs (dst_regno,
6313 						    reg->biggest_mode);
6314 			  for (i = 0; i < nregs; i++)
6315 			    usage_insns[dst_regno + i].check
6316 			      = -(int) INSN_UID (curr_insn);
6317 			}
6318 		    }
6319 		}
6320 	  /* Process clobbered call regs.  */
6321 	  if (curr_id->arg_hard_regs != NULL)
6322 	    for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6323 	      if (dst_regno >= FIRST_PSEUDO_REGISTER)
6324 		usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check
6325 		  = -(int) INSN_UID (curr_insn);
6326 	  if (! JUMP_P (curr_insn))
6327 	    for (i = 0; i < to_inherit_num; i++)
6328 	      if (inherit_reload_reg (true, to_inherit[i].regno,
6329 				      ALL_REGS, curr_insn,
6330 				      to_inherit[i].insns))
6331 	      change_p = true;
6332 	  if (CALL_P (curr_insn))
6333 	    {
6334 	      rtx cheap, pat, dest;
6335 	      rtx_insn *restore;
6336 	      int regno, hard_regno;
6337 
6338 	      calls_num++;
6339 	      if ((cheap = find_reg_note (curr_insn,
6340 					  REG_RETURNED, NULL_RTX)) != NULL_RTX
6341 		  && ((cheap = XEXP (cheap, 0)), true)
6342 		  && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER
6343 		  && (hard_regno = reg_renumber[regno]) >= 0
6344 		  && usage_insns[regno].check == curr_usage_insns_check
6345 		  /* If there are pending saves/restores, the
6346 		     optimization is not worth.	 */
6347 		  && usage_insns[regno].calls_num == calls_num - 1
6348 		  && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno))
6349 		{
6350 		  /* Restore the pseudo from the call result as
6351 		     REG_RETURNED note says that the pseudo value is
6352 		     in the call result and the pseudo is an argument
6353 		     of the call.  */
6354 		  pat = PATTERN (curr_insn);
6355 		  if (GET_CODE (pat) == PARALLEL)
6356 		    pat = XVECEXP (pat, 0, 0);
6357 		  dest = SET_DEST (pat);
6358 		  /* For multiple return values dest is PARALLEL.
6359 		     Currently we handle only single return value case.  */
6360 		  if (REG_P (dest))
6361 		    {
6362 		      start_sequence ();
6363 		      emit_move_insn (cheap, copy_rtx (dest));
6364 		      restore = get_insns ();
6365 		      end_sequence ();
6366 		      lra_process_new_insns (curr_insn, NULL, restore,
6367 					     "Inserting call parameter restore");
6368 		      /* We don't need to save/restore of the pseudo from
6369 			 this call.	 */
6370 		      usage_insns[regno].calls_num = calls_num;
6371 		      bitmap_set_bit (&check_only_regs, regno);
6372 		    }
6373 		}
6374 	    }
6375 	  to_inherit_num = 0;
6376 	  /* Process insn usages.  */
6377 	  for (iter = 0; iter < 2; iter++)
6378 	    for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6379 		 reg != NULL;
6380 		 reg = reg->next)
6381 	      if ((reg->type != OP_OUT
6382 		   || (reg->type == OP_OUT && reg->subreg_p))
6383 		  && (src_regno = reg->regno) < lra_constraint_new_regno_start)
6384 		{
6385 		  if (src_regno >= FIRST_PSEUDO_REGISTER
6386 		      && reg_renumber[src_regno] < 0 && reg->type == OP_IN)
6387 		    {
6388 		      if (usage_insns[src_regno].check == curr_usage_insns_check
6389 			  && (next_usage_insns
6390 			      = usage_insns[src_regno].insns) != NULL_RTX
6391 			  && NONDEBUG_INSN_P (curr_insn))
6392 			add_to_inherit (src_regno, next_usage_insns);
6393 		      else if (usage_insns[src_regno].check
6394 			       != -(int) INSN_UID (curr_insn))
6395 			/* Add usages but only if the reg is not set up
6396 			   in the same insn.  */
6397 			add_next_usage_insn (src_regno, curr_insn, reloads_num);
6398 		    }
6399 		  else if (src_regno < FIRST_PSEUDO_REGISTER
6400 			   || reg_renumber[src_regno] >= 0)
6401 		    {
6402 		      bool before_p;
6403 		      rtx_insn *use_insn = curr_insn;
6404 
6405 		      before_p = (JUMP_P (curr_insn)
6406 				  || (CALL_P (curr_insn) && reg->type == OP_IN));
6407 		      if (NONDEBUG_INSN_P (curr_insn)
6408 			  && (! JUMP_P (curr_insn) || reg->type == OP_IN)
6409 			  && split_if_necessary (src_regno, reg->biggest_mode,
6410 						 potential_reload_hard_regs,
6411 						 before_p, curr_insn, max_uid))
6412 			{
6413 			  if (reg->subreg_p)
6414 			    lra_risky_transformations_p = true;
6415 			  change_p = true;
6416 			  /* Invalidate. */
6417 			  usage_insns[src_regno].check = 0;
6418 			  if (before_p)
6419 			    use_insn = PREV_INSN (curr_insn);
6420 			}
6421 		      if (NONDEBUG_INSN_P (curr_insn))
6422 			{
6423 			  if (src_regno < FIRST_PSEUDO_REGISTER)
6424 			    add_to_hard_reg_set (&live_hard_regs,
6425 						 reg->biggest_mode, src_regno);
6426 			  else
6427 			    add_to_hard_reg_set (&live_hard_regs,
6428 						 PSEUDO_REGNO_MODE (src_regno),
6429 						 reg_renumber[src_regno]);
6430 			}
6431 		      if (src_regno >= FIRST_PSEUDO_REGISTER)
6432 			add_next_usage_insn (src_regno, use_insn, reloads_num);
6433 		      else
6434 			{
6435 			  for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++)
6436 			    add_next_usage_insn (src_regno + i, use_insn, reloads_num);
6437 			}
6438 		    }
6439 		}
6440 	  /* Process used call regs.  */
6441 	  if (curr_id->arg_hard_regs != NULL)
6442 	    for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6443 	      if (src_regno < FIRST_PSEUDO_REGISTER)
6444 		{
6445 	           SET_HARD_REG_BIT (live_hard_regs, src_regno);
6446 	           add_next_usage_insn (src_regno, curr_insn, reloads_num);
6447 		}
6448 	  for (i = 0; i < to_inherit_num; i++)
6449 	    {
6450 	      src_regno = to_inherit[i].regno;
6451 	      if (inherit_reload_reg (false, src_regno, ALL_REGS,
6452 				      curr_insn, to_inherit[i].insns))
6453 		change_p = true;
6454 	      else
6455 		setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6456 	    }
6457 	}
6458       if (update_reloads_num_p
6459 	  && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX)
6460 	{
6461 	  int regno = -1;
6462 	  if ((REG_P (SET_DEST (curr_set))
6463 	       && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start
6464 	       && reg_renumber[regno] < 0
6465 	       && (cl = lra_get_allocno_class (regno)) != NO_REGS)
6466 	      || (REG_P (SET_SRC (curr_set))
6467 	          && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start
6468 	          && reg_renumber[regno] < 0
6469 	          && (cl = lra_get_allocno_class (regno)) != NO_REGS))
6470 	    {
6471 	      if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6472 		reloads_num++;
6473 	      if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6474 		IOR_HARD_REG_SET (potential_reload_hard_regs,
6475 	                          reg_class_contents[cl]);
6476 	    }
6477 	}
6478       if (NONDEBUG_INSN_P (curr_insn))
6479 	{
6480 	  int regno;
6481 
6482 	  /* Invalidate invariants with changed regs.  */
6483 	  curr_id = lra_get_insn_recog_data (curr_insn);
6484 	  for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6485 	    if (reg->type != OP_IN)
6486 	      {
6487 		bitmap_set_bit (&invalid_invariant_regs, reg->regno);
6488 		bitmap_set_bit (&invalid_invariant_regs,
6489 				ORIGINAL_REGNO (regno_reg_rtx[reg->regno]));
6490 	      }
6491 	  curr_static_id = curr_id->insn_static_data;
6492 	  for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
6493 	    if (reg->type != OP_IN)
6494 	      bitmap_set_bit (&invalid_invariant_regs, reg->regno);
6495 	  if (curr_id->arg_hard_regs != NULL)
6496 	    for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6497 	      if (regno >= FIRST_PSEUDO_REGISTER)
6498 		bitmap_set_bit (&invalid_invariant_regs,
6499 				regno - FIRST_PSEUDO_REGISTER);
6500 	}
6501       /* We reached the start of the current basic block.  */
6502       if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head)
6503 	  || BLOCK_FOR_INSN (prev_insn) != curr_bb)
6504 	{
6505 	  /* We reached the beginning of the current block -- do
6506 	     rest of spliting in the current BB.  */
6507 	  to_process = df_get_live_in (curr_bb);
6508 	  if (BLOCK_FOR_INSN (head) != curr_bb)
6509 	    {
6510 	      /* We are somewhere in the middle of EBB.	 */
6511 	      get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src,
6512 				       curr_bb, &temp_bitmap);
6513 	      to_process = &temp_bitmap;
6514 	    }
6515 	  head_p = true;
6516 	  EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6517 	    {
6518 	      if ((int) j >= lra_constraint_new_regno_start)
6519 		break;
6520 	      if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6521 		  && usage_insns[j].check == curr_usage_insns_check
6522 		  && (next_usage_insns = usage_insns[j].insns) != NULL_RTX)
6523 		{
6524 		  if (need_for_split_p (potential_reload_hard_regs, j))
6525 		    {
6526 		      if (lra_dump_file != NULL && head_p)
6527 			{
6528 			  fprintf (lra_dump_file,
6529 				   "  ----------------------------------\n");
6530 			  head_p = false;
6531 			}
6532 		      if (split_reg (false, j, bb_note (curr_bb),
6533 				     next_usage_insns, NULL))
6534 			change_p = true;
6535 		    }
6536 		  usage_insns[j].check = 0;
6537 		}
6538 	    }
6539 	}
6540     }
6541   return change_p;
6542 }
6543 
6544 /* This value affects EBB forming.  If probability of edge from EBB to
6545    a BB is not greater than the following value, we don't add the BB
6546    to EBB.  */
6547 #define EBB_PROBABILITY_CUTOFF \
6548   ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6549 
6550 /* Current number of inheritance/split iteration.  */
6551 int lra_inheritance_iter;
6552 
6553 /* Entry function for inheritance/split pass.  */
6554 void
6555 lra_inheritance (void)
6556 {
6557   int i;
6558   basic_block bb, start_bb;
6559   edge e;
6560 
6561   lra_inheritance_iter++;
6562   if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
6563     return;
6564   timevar_push (TV_LRA_INHERITANCE);
6565   if (lra_dump_file != NULL)
6566     fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n",
6567 	     lra_inheritance_iter);
6568   curr_usage_insns_check = 0;
6569   usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start);
6570   for (i = 0; i < lra_constraint_new_regno_start; i++)
6571     usage_insns[i].check = 0;
6572   bitmap_initialize (&check_only_regs, &reg_obstack);
6573   bitmap_initialize (&invalid_invariant_regs, &reg_obstack);
6574   bitmap_initialize (&live_regs, &reg_obstack);
6575   bitmap_initialize (&temp_bitmap, &reg_obstack);
6576   bitmap_initialize (&ebb_global_regs, &reg_obstack);
6577   FOR_EACH_BB_FN (bb, cfun)
6578     {
6579       start_bb = bb;
6580       if (lra_dump_file != NULL)
6581 	fprintf (lra_dump_file, "EBB");
6582       /* Form a EBB starting with BB.  */
6583       bitmap_clear (&ebb_global_regs);
6584       bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb));
6585       for (;;)
6586 	{
6587 	  if (lra_dump_file != NULL)
6588 	    fprintf (lra_dump_file, " %d", bb->index);
6589 	  if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
6590 	      || LABEL_P (BB_HEAD (bb->next_bb)))
6591 	    break;
6592 	  e = find_fallthru_edge (bb->succs);
6593 	  if (! e)
6594 	    break;
6595 	  if (e->probability.initialized_p ()
6596 	      && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF)
6597 	    break;
6598 	  bb = bb->next_bb;
6599 	}
6600       bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb));
6601       if (lra_dump_file != NULL)
6602 	fprintf (lra_dump_file, "\n");
6603       if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb)))
6604 	/* Remember that the EBB head and tail can change in
6605 	   inherit_in_ebb.  */
6606 	update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb));
6607     }
6608   bitmap_clear (&ebb_global_regs);
6609   bitmap_clear (&temp_bitmap);
6610   bitmap_clear (&live_regs);
6611   bitmap_clear (&invalid_invariant_regs);
6612   bitmap_clear (&check_only_regs);
6613   free (usage_insns);
6614 
6615   timevar_pop (TV_LRA_INHERITANCE);
6616 }
6617 
6618 
6619 
6620 /* This page contains code to undo failed inheritance/split
6621    transformations.  */
6622 
6623 /* Current number of iteration undoing inheritance/split.  */
6624 int lra_undo_inheritance_iter;
6625 
6626 /* Fix BB live info LIVE after removing pseudos created on pass doing
6627    inheritance/split which are REMOVED_PSEUDOS.	 */
6628 static void
6629 fix_bb_live_info (bitmap live, bitmap removed_pseudos)
6630 {
6631   unsigned int regno;
6632   bitmap_iterator bi;
6633 
6634   EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi)
6635     if (bitmap_clear_bit (live, regno)
6636 	&& REG_P (lra_reg_info[regno].restore_rtx))
6637       bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx));
6638 }
6639 
6640 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6641    number.  */
6642 static int
6643 get_regno (rtx reg)
6644 {
6645   if (GET_CODE (reg) == SUBREG)
6646     reg = SUBREG_REG (reg);
6647   if (REG_P (reg))
6648     return REGNO (reg);
6649   return -1;
6650 }
6651 
6652 /* Delete a move INSN with destination reg DREGNO and a previous
6653    clobber insn with the same regno.  The inheritance/split code can
6654    generate moves with preceding clobber and when we delete such moves
6655    we should delete the clobber insn too to keep the correct life
6656    info.  */
6657 static void
6658 delete_move_and_clobber (rtx_insn *insn, int dregno)
6659 {
6660   rtx_insn *prev_insn = PREV_INSN (insn);
6661 
6662   lra_set_insn_deleted (insn);
6663   lra_assert (dregno >= 0);
6664   if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn)
6665       && GET_CODE (PATTERN (prev_insn)) == CLOBBER
6666       && dregno == get_regno (XEXP (PATTERN (prev_insn), 0)))
6667     lra_set_insn_deleted (prev_insn);
6668 }
6669 
6670 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6671    return true if we did any change.  The undo transformations for
6672    inheritance looks like
6673       i <- i2
6674       p <- i	  =>   p <- i2
6675    or removing
6676       p <- i, i <- p, and i <- i3
6677    where p is original pseudo from which inheritance pseudo i was
6678    created, i and i3 are removed inheritance pseudos, i2 is another
6679    not removed inheritance pseudo.  All split pseudos or other
6680    occurrences of removed inheritance pseudos are changed on the
6681    corresponding original pseudos.
6682 
6683    The function also schedules insns changed and created during
6684    inheritance/split pass for processing by the subsequent constraint
6685    pass.  */
6686 static bool
6687 remove_inheritance_pseudos (bitmap remove_pseudos)
6688 {
6689   basic_block bb;
6690   int regno, sregno, prev_sregno, dregno;
6691   rtx restore_rtx;
6692   rtx set, prev_set;
6693   rtx_insn *prev_insn;
6694   bool change_p, done_p;
6695 
6696   change_p = ! bitmap_empty_p (remove_pseudos);
6697   /* We can not finish the function right away if CHANGE_P is true
6698      because we need to marks insns affected by previous
6699      inheritance/split pass for processing by the subsequent
6700      constraint pass.  */
6701   FOR_EACH_BB_FN (bb, cfun)
6702     {
6703       fix_bb_live_info (df_get_live_in (bb), remove_pseudos);
6704       fix_bb_live_info (df_get_live_out (bb), remove_pseudos);
6705       FOR_BB_INSNS_REVERSE (bb, curr_insn)
6706 	{
6707 	  if (! INSN_P (curr_insn))
6708 	    continue;
6709 	  done_p = false;
6710 	  sregno = dregno = -1;
6711 	  if (change_p && NONDEBUG_INSN_P (curr_insn)
6712 	      && (set = single_set (curr_insn)) != NULL_RTX)
6713 	    {
6714 	      dregno = get_regno (SET_DEST (set));
6715 	      sregno = get_regno (SET_SRC (set));
6716 	    }
6717 
6718 	  if (sregno >= 0 && dregno >= 0)
6719 	    {
6720 	      if (bitmap_bit_p (remove_pseudos, dregno)
6721 		  && ! REG_P (lra_reg_info[dregno].restore_rtx))
6722 		{
6723 		  /* invariant inheritance pseudo <- original pseudo */
6724 		  if (lra_dump_file != NULL)
6725 		    {
6726 		      fprintf (lra_dump_file, "	   Removing invariant inheritance:\n");
6727 		      dump_insn_slim (lra_dump_file, curr_insn);
6728 		      fprintf (lra_dump_file, "\n");
6729 		    }
6730 		  delete_move_and_clobber (curr_insn, dregno);
6731 		  done_p = true;
6732 		}
6733 	      else if (bitmap_bit_p (remove_pseudos, sregno)
6734 		       && ! REG_P (lra_reg_info[sregno].restore_rtx))
6735 		{
6736 		  /* reload pseudo <- invariant inheritance pseudo */
6737 		  start_sequence ();
6738 		  /* We can not just change the source.  It might be
6739 		     an insn different from the move.  */
6740 		  emit_insn (lra_reg_info[sregno].restore_rtx);
6741 		  rtx_insn *new_insns = get_insns ();
6742 		  end_sequence ();
6743 		  lra_assert (single_set (new_insns) != NULL
6744 			      && SET_DEST (set) == SET_DEST (single_set (new_insns)));
6745 		  lra_process_new_insns (curr_insn, NULL, new_insns,
6746 					 "Changing reload<-invariant inheritance");
6747 		  delete_move_and_clobber (curr_insn, dregno);
6748 		  done_p = true;
6749 		}
6750 	      else if ((bitmap_bit_p (remove_pseudos, sregno)
6751 			&& (get_regno (lra_reg_info[sregno].restore_rtx) == dregno
6752 			    || (bitmap_bit_p (remove_pseudos, dregno)
6753 				&& get_regno (lra_reg_info[sregno].restore_rtx) >= 0
6754 				&& (get_regno (lra_reg_info[sregno].restore_rtx)
6755 				    == get_regno (lra_reg_info[dregno].restore_rtx)))))
6756 		       || (bitmap_bit_p (remove_pseudos, dregno)
6757 			   && get_regno (lra_reg_info[dregno].restore_rtx) == sregno))
6758 		/* One of the following cases:
6759 		     original <- removed inheritance pseudo
6760 		     removed inherit pseudo <- another removed inherit pseudo
6761 		     removed inherit pseudo <- original pseudo
6762 		   Or
6763 		     removed_split_pseudo <- original_reg
6764 		     original_reg <- removed_split_pseudo */
6765 		{
6766 		  if (lra_dump_file != NULL)
6767 		    {
6768 		      fprintf (lra_dump_file, "	   Removing %s:\n",
6769 			       bitmap_bit_p (&lra_split_regs, sregno)
6770 			       || bitmap_bit_p (&lra_split_regs, dregno)
6771 			       ? "split" : "inheritance");
6772 		      dump_insn_slim (lra_dump_file, curr_insn);
6773 		    }
6774 		  delete_move_and_clobber (curr_insn, dregno);
6775 		  done_p = true;
6776 		}
6777 	      else if (bitmap_bit_p (remove_pseudos, sregno)
6778 		       && bitmap_bit_p (&lra_inheritance_pseudos, sregno))
6779 		{
6780 		  /* Search the following pattern:
6781 		       inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6782 		       original_pseudo <- inherit_or_split_pseudo1
6783 		    where the 2nd insn is the current insn and
6784 		    inherit_or_split_pseudo2 is not removed.  If it is found,
6785 		    change the current insn onto:
6786 		       original_pseudo <- inherit_or_split_pseudo2.  */
6787 		  for (prev_insn = PREV_INSN (curr_insn);
6788 		       prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn);
6789 		       prev_insn = PREV_INSN (prev_insn))
6790 		    ;
6791 		  if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb
6792 		      && (prev_set = single_set (prev_insn)) != NULL_RTX
6793 		      /* There should be no subregs in insn we are
6794 			 searching because only the original reg might
6795 			 be in subreg when we changed the mode of
6796 			 load/store for splitting.  */
6797 		      && REG_P (SET_DEST (prev_set))
6798 		      && REG_P (SET_SRC (prev_set))
6799 		      && (int) REGNO (SET_DEST (prev_set)) == sregno
6800 		      && ((prev_sregno = REGNO (SET_SRC (prev_set)))
6801 			  >= FIRST_PSEUDO_REGISTER)
6802 		      && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX
6803 			  ||
6804 			  /* As we consider chain of inheritance or
6805 			     splitting described in above comment we should
6806 			     check that sregno and prev_sregno were
6807 			     inheritance/split pseudos created from the
6808 			     same original regno.  */
6809 			  (get_regno (lra_reg_info[sregno].restore_rtx) >= 0
6810 			   && (get_regno (lra_reg_info[sregno].restore_rtx)
6811 			       == get_regno (lra_reg_info[prev_sregno].restore_rtx))))
6812 		      && ! bitmap_bit_p (remove_pseudos, prev_sregno))
6813 		    {
6814 		      lra_assert (GET_MODE (SET_SRC (prev_set))
6815 				  == GET_MODE (regno_reg_rtx[sregno]));
6816 		      /* Although we have a single set, the insn can
6817 			 contain more one sregno register occurrence
6818 			 as a source.  Change all occurrences.  */
6819 		      lra_substitute_pseudo_within_insn (curr_insn, sregno,
6820 							 SET_SRC (prev_set),
6821 							 false);
6822 		      /* As we are finishing with processing the insn
6823 			 here, check the destination too as it might
6824 			 inheritance pseudo for another pseudo.  */
6825 		      if (bitmap_bit_p (remove_pseudos, dregno)
6826 			  && bitmap_bit_p (&lra_inheritance_pseudos, dregno)
6827 			  && (restore_rtx
6828 			      = lra_reg_info[dregno].restore_rtx) != NULL_RTX)
6829 			{
6830 			  if (GET_CODE (SET_DEST (set)) == SUBREG)
6831 			    SUBREG_REG (SET_DEST (set)) = restore_rtx;
6832 			  else
6833 			    SET_DEST (set) = restore_rtx;
6834 			}
6835 		      lra_push_insn_and_update_insn_regno_info (curr_insn);
6836 		      lra_set_used_insn_alternative_by_uid
6837 			(INSN_UID (curr_insn), LRA_UNKNOWN_ALT);
6838 		      done_p = true;
6839 		      if (lra_dump_file != NULL)
6840 			{
6841 			  fprintf (lra_dump_file, "    Change reload insn:\n");
6842 			  dump_insn_slim (lra_dump_file, curr_insn);
6843 			}
6844 		    }
6845 		}
6846 	    }
6847 	  if (! done_p)
6848 	    {
6849 	      struct lra_insn_reg *reg;
6850 	      bool restored_regs_p = false;
6851 	      bool kept_regs_p = false;
6852 
6853 	      curr_id = lra_get_insn_recog_data (curr_insn);
6854 	      for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6855 		{
6856 		  regno = reg->regno;
6857 		  restore_rtx = lra_reg_info[regno].restore_rtx;
6858 		  if (restore_rtx != NULL_RTX)
6859 		    {
6860 		      if (change_p && bitmap_bit_p (remove_pseudos, regno))
6861 			{
6862 			  lra_substitute_pseudo_within_insn
6863 			    (curr_insn, regno, restore_rtx, false);
6864 			  restored_regs_p = true;
6865 			}
6866 		      else
6867 			kept_regs_p = true;
6868 		    }
6869 		}
6870 	      if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p)
6871 		{
6872 		  /* The instruction has changed since the previous
6873 		     constraints pass.  */
6874 		  lra_push_insn_and_update_insn_regno_info (curr_insn);
6875 		  lra_set_used_insn_alternative_by_uid
6876 		    (INSN_UID (curr_insn), LRA_UNKNOWN_ALT);
6877 		}
6878 	      else if (restored_regs_p)
6879 		/* The instruction has been restored to the form that
6880 		   it had during the previous constraints pass.  */
6881 		lra_update_insn_regno_info (curr_insn);
6882 	      if (restored_regs_p && lra_dump_file != NULL)
6883 		{
6884 		  fprintf (lra_dump_file, "   Insn after restoring regs:\n");
6885 		  dump_insn_slim (lra_dump_file, curr_insn);
6886 		}
6887 	    }
6888 	}
6889     }
6890   return change_p;
6891 }
6892 
6893 /* If optional reload pseudos failed to get a hard register or was not
6894    inherited, it is better to remove optional reloads.  We do this
6895    transformation after undoing inheritance to figure out necessity to
6896    remove optional reloads easier.  Return true if we do any
6897    change.  */
6898 static bool
6899 undo_optional_reloads (void)
6900 {
6901   bool change_p, keep_p;
6902   unsigned int regno, uid;
6903   bitmap_iterator bi, bi2;
6904   rtx_insn *insn;
6905   rtx set, src, dest;
6906   auto_bitmap removed_optional_reload_pseudos (&reg_obstack);
6907 
6908   bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos);
6909   EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
6910     {
6911       keep_p = false;
6912       /* Keep optional reloads from previous subpasses.  */
6913       if (lra_reg_info[regno].restore_rtx == NULL_RTX
6914 	  /* If the original pseudo changed its allocation, just
6915 	     removing the optional pseudo is dangerous as the original
6916 	     pseudo will have longer live range.  */
6917 	  || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0)
6918 	keep_p = true;
6919       else if (reg_renumber[regno] >= 0)
6920 	EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2)
6921 	  {
6922 	    insn = lra_insn_recog_data[uid]->insn;
6923 	    if ((set = single_set (insn)) == NULL_RTX)
6924 	      continue;
6925 	    src = SET_SRC (set);
6926 	    dest = SET_DEST (set);
6927 	    if (! REG_P (src) || ! REG_P (dest))
6928 	      continue;
6929 	    if (REGNO (dest) == regno
6930 		/* Ignore insn for optional reloads itself.  */
6931 		&& REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src)
6932 		/* Check only inheritance on last inheritance pass.  */
6933 		&& (int) REGNO (src) >= new_regno_start
6934 		/* Check that the optional reload was inherited.  */
6935 		&& bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src)))
6936 	      {
6937 		keep_p = true;
6938 		break;
6939 	      }
6940 	  }
6941       if (keep_p)
6942 	{
6943 	  bitmap_clear_bit (removed_optional_reload_pseudos, regno);
6944 	  if (lra_dump_file != NULL)
6945 	    fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno);
6946 	}
6947     }
6948   change_p = ! bitmap_empty_p (removed_optional_reload_pseudos);
6949   auto_bitmap insn_bitmap (&reg_obstack);
6950   EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi)
6951     {
6952       if (lra_dump_file != NULL)
6953 	fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno);
6954       bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap);
6955       EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2)
6956 	{
6957 	  insn = lra_insn_recog_data[uid]->insn;
6958 	  if ((set = single_set (insn)) != NULL_RTX)
6959 	    {
6960 	      src = SET_SRC (set);
6961 	      dest = SET_DEST (set);
6962 	      if (REG_P (src) && REG_P (dest)
6963 		  && ((REGNO (src) == regno
6964 		       && (REGNO (lra_reg_info[regno].restore_rtx)
6965 			   == REGNO (dest)))
6966 		      || (REGNO (dest) == regno
6967 			  && (REGNO (lra_reg_info[regno].restore_rtx)
6968 			      == REGNO (src)))))
6969 		{
6970 		  if (lra_dump_file != NULL)
6971 		    {
6972 		      fprintf (lra_dump_file, "  Deleting move %u\n",
6973 			       INSN_UID (insn));
6974 		      dump_insn_slim (lra_dump_file, insn);
6975 		    }
6976 		  delete_move_and_clobber (insn, REGNO (dest));
6977 		  continue;
6978 		}
6979 	      /* We should not worry about generation memory-memory
6980 		 moves here as if the corresponding inheritance did
6981 		 not work (inheritance pseudo did not get a hard reg),
6982 		 we remove the inheritance pseudo and the optional
6983 		 reload.  */
6984 	    }
6985 	  lra_substitute_pseudo_within_insn
6986 	    (insn, regno, lra_reg_info[regno].restore_rtx, false);
6987 	  lra_update_insn_regno_info (insn);
6988 	  if (lra_dump_file != NULL)
6989 	    {
6990 	      fprintf (lra_dump_file,
6991 		       "  Restoring original insn:\n");
6992 	      dump_insn_slim (lra_dump_file, insn);
6993 	    }
6994 	}
6995     }
6996   /* Clear restore_regnos.  */
6997   EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
6998     lra_reg_info[regno].restore_rtx = NULL_RTX;
6999   return change_p;
7000 }
7001 
7002 /* Entry function for undoing inheritance/split transformation.	 Return true
7003    if we did any RTL change in this pass.  */
7004 bool
7005 lra_undo_inheritance (void)
7006 {
7007   unsigned int regno;
7008   int hard_regno;
7009   int n_all_inherit, n_inherit, n_all_split, n_split;
7010   rtx restore_rtx;
7011   bitmap_iterator bi;
7012   bool change_p;
7013 
7014   lra_undo_inheritance_iter++;
7015   if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
7016     return false;
7017   if (lra_dump_file != NULL)
7018     fprintf (lra_dump_file,
7019 	     "\n********** Undoing inheritance #%d: **********\n\n",
7020 	     lra_undo_inheritance_iter);
7021   auto_bitmap remove_pseudos (&reg_obstack);
7022   n_inherit = n_all_inherit = 0;
7023   EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
7024     if (lra_reg_info[regno].restore_rtx != NULL_RTX)
7025       {
7026 	n_all_inherit++;
7027 	if (reg_renumber[regno] < 0
7028 	    /* If the original pseudo changed its allocation, just
7029 	       removing inheritance is dangerous as for changing
7030 	       allocation we used shorter live-ranges.  */
7031 	    && (! REG_P (lra_reg_info[regno].restore_rtx)
7032 		|| reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0))
7033 	  bitmap_set_bit (remove_pseudos, regno);
7034 	else
7035 	  n_inherit++;
7036       }
7037   if (lra_dump_file != NULL && n_all_inherit != 0)
7038     fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n",
7039 	     n_inherit, n_all_inherit,
7040 	     (double) n_inherit / n_all_inherit * 100);
7041   n_split = n_all_split = 0;
7042   EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
7043     if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX)
7044       {
7045 	int restore_regno = REGNO (restore_rtx);
7046 
7047 	n_all_split++;
7048 	hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER
7049 		      ? reg_renumber[restore_regno] : restore_regno);
7050 	if (hard_regno < 0 || reg_renumber[regno] == hard_regno)
7051 	  bitmap_set_bit (remove_pseudos, regno);
7052 	else
7053 	  {
7054 	    n_split++;
7055 	    if (lra_dump_file != NULL)
7056 	      fprintf (lra_dump_file, "	     Keep split r%d (orig=r%d)\n",
7057 		       regno, restore_regno);
7058 	  }
7059       }
7060   if (lra_dump_file != NULL && n_all_split != 0)
7061     fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n",
7062 	     n_split, n_all_split,
7063 	     (double) n_split / n_all_split * 100);
7064   change_p = remove_inheritance_pseudos (remove_pseudos);
7065   /* Clear restore_regnos.  */
7066   EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
7067     lra_reg_info[regno].restore_rtx = NULL_RTX;
7068   EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
7069     lra_reg_info[regno].restore_rtx = NULL_RTX;
7070   change_p = undo_optional_reloads () || change_p;
7071   return change_p;
7072 }
7073