1*38fd1498Szrj /* This file contains definitions for the register renamer. 2*38fd1498Szrj Copyright (C) 2011-2018 Free Software Foundation, Inc. 3*38fd1498Szrj 4*38fd1498Szrj This file is part of GCC. 5*38fd1498Szrj 6*38fd1498Szrj GCC is free software; you can redistribute it and/or modify it under 7*38fd1498Szrj the terms of the GNU General Public License as published by the Free 8*38fd1498Szrj Software Foundation; either version 3, or (at your option) any later 9*38fd1498Szrj version. 10*38fd1498Szrj 11*38fd1498Szrj GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12*38fd1498Szrj WARRANTY; without even the implied warranty of MERCHANTABILITY or 13*38fd1498Szrj FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14*38fd1498Szrj for more details. 15*38fd1498Szrj 16*38fd1498Szrj You should have received a copy of the GNU General Public License 17*38fd1498Szrj along with GCC; see the file COPYING3. If not see 18*38fd1498Szrj <http://www.gnu.org/licenses/>. */ 19*38fd1498Szrj 20*38fd1498Szrj #ifndef GCC_REGRENAME_H 21*38fd1498Szrj #define GCC_REGRENAME_H 22*38fd1498Szrj 23*38fd1498Szrj /* We keep linked lists of DU_HEAD structures, each of which describes 24*38fd1498Szrj a chain of occurrences of a reg. */ 25*38fd1498Szrj struct du_head 26*38fd1498Szrj { 27*38fd1498Szrj /* The next chain. */ 28*38fd1498Szrj struct du_head *next_chain; 29*38fd1498Szrj /* The first and last elements of this chain. */ 30*38fd1498Szrj struct du_chain *first, *last; 31*38fd1498Szrj /* The chain that this chain is tied to. */ 32*38fd1498Szrj struct du_head *tied_chain; 33*38fd1498Szrj /* Describes the register being tracked. */ 34*38fd1498Szrj unsigned regno; 35*38fd1498Szrj int nregs; 36*38fd1498Szrj 37*38fd1498Szrj /* A unique id to be used as an index into the conflicts bitmaps. */ 38*38fd1498Szrj unsigned id; 39*38fd1498Szrj /* A bitmap to record conflicts with other chains. */ 40*38fd1498Szrj bitmap_head conflicts; 41*38fd1498Szrj /* Conflicts with untracked hard registers. */ 42*38fd1498Szrj HARD_REG_SET hard_conflicts; 43*38fd1498Szrj 44*38fd1498Szrj /* Nonzero if the chain crosses a call. */ 45*38fd1498Szrj unsigned int need_caller_save_reg:1; 46*38fd1498Szrj /* Nonzero if the register is used in a way that prevents renaming, 47*38fd1498Szrj such as the SET_DEST of a CALL_INSN or an asm operand that used 48*38fd1498Szrj to be a hard register. */ 49*38fd1498Szrj unsigned int cannot_rename:1; 50*38fd1498Szrj /* Nonzero if the chain has already been renamed. */ 51*38fd1498Szrj unsigned int renamed:1; 52*38fd1498Szrj 53*38fd1498Szrj /* Fields for use by target code. */ 54*38fd1498Szrj unsigned int target_data_1; 55*38fd1498Szrj unsigned int target_data_2; 56*38fd1498Szrj }; 57*38fd1498Szrj 58*38fd1498Szrj typedef struct du_head *du_head_p; 59*38fd1498Szrj 60*38fd1498Szrj /* This struct describes a single occurrence of a register. */ 61*38fd1498Szrj struct du_chain 62*38fd1498Szrj { 63*38fd1498Szrj /* Links to the next occurrence of the register. */ 64*38fd1498Szrj struct du_chain *next_use; 65*38fd1498Szrj 66*38fd1498Szrj /* The insn where the register appears. */ 67*38fd1498Szrj rtx_insn *insn; 68*38fd1498Szrj /* The location inside the insn. */ 69*38fd1498Szrj rtx *loc; 70*38fd1498Szrj /* The register class required by the insn at this location. */ 71*38fd1498Szrj ENUM_BITFIELD(reg_class) cl : 16; 72*38fd1498Szrj }; 73*38fd1498Szrj 74*38fd1498Szrj /* This struct describes data gathered during regrename_analyze about 75*38fd1498Szrj a single operand of an insn. */ 76*38fd1498Szrj struct operand_rr_info 77*38fd1498Szrj { 78*38fd1498Szrj /* The number of chains recorded for this operand. */ 79*38fd1498Szrj short n_chains; 80*38fd1498Szrj bool failed; 81*38fd1498Szrj /* Holds either the chain for the operand itself, or for the registers in 82*38fd1498Szrj a memory operand. */ 83*38fd1498Szrj struct du_chain *chains[MAX_REGS_PER_ADDRESS]; 84*38fd1498Szrj struct du_head *heads[MAX_REGS_PER_ADDRESS]; 85*38fd1498Szrj }; 86*38fd1498Szrj 87*38fd1498Szrj /* A struct to hold a vector of operand_rr_info structures describing the 88*38fd1498Szrj operands of an insn. */ 89*38fd1498Szrj struct insn_rr_info 90*38fd1498Szrj { 91*38fd1498Szrj operand_rr_info *op_info; 92*38fd1498Szrj }; 93*38fd1498Szrj 94*38fd1498Szrj 95*38fd1498Szrj extern vec<insn_rr_info> insn_rr; 96*38fd1498Szrj 97*38fd1498Szrj extern void regrename_init (bool); 98*38fd1498Szrj extern void regrename_finish (void); 99*38fd1498Szrj extern void regrename_analyze (bitmap); 100*38fd1498Szrj extern du_head_p regrename_chain_from_id (unsigned int); 101*38fd1498Szrj extern int find_rename_reg (du_head_p, enum reg_class, HARD_REG_SET *, int, 102*38fd1498Szrj bool); 103*38fd1498Szrj extern bool regrename_do_replace (du_head_p, int); 104*38fd1498Szrj extern reg_class regrename_find_superclass (du_head_p, int *, 105*38fd1498Szrj HARD_REG_SET *); 106*38fd1498Szrj 107*38fd1498Szrj #endif 108