xref: /dragonfly/contrib/gcc-8.0/gcc/regs.h (revision 38fd1498)
1*38fd1498Szrj /* Define per-register tables for data flow info and register allocation.
2*38fd1498Szrj    Copyright (C) 1987-2018 Free Software Foundation, Inc.
3*38fd1498Szrj 
4*38fd1498Szrj This file is part of GCC.
5*38fd1498Szrj 
6*38fd1498Szrj GCC is free software; you can redistribute it and/or modify it under
7*38fd1498Szrj the terms of the GNU General Public License as published by the Free
8*38fd1498Szrj Software Foundation; either version 3, or (at your option) any later
9*38fd1498Szrj version.
10*38fd1498Szrj 
11*38fd1498Szrj GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12*38fd1498Szrj WARRANTY; without even the implied warranty of MERCHANTABILITY or
13*38fd1498Szrj FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14*38fd1498Szrj for more details.
15*38fd1498Szrj 
16*38fd1498Szrj You should have received a copy of the GNU General Public License
17*38fd1498Szrj along with GCC; see the file COPYING3.  If not see
18*38fd1498Szrj <http://www.gnu.org/licenses/>.  */
19*38fd1498Szrj 
20*38fd1498Szrj #ifndef GCC_REGS_H
21*38fd1498Szrj #define GCC_REGS_H
22*38fd1498Szrj 
23*38fd1498Szrj #define REG_BYTES(R) mode_size[(int) GET_MODE (R)]
24*38fd1498Szrj 
25*38fd1498Szrj /* When you only have the mode of a pseudo register before it has a hard
26*38fd1498Szrj    register chosen for it, this reports the size of each hard register
27*38fd1498Szrj    a pseudo in such a mode would get allocated to.  A target may
28*38fd1498Szrj    override this.  */
29*38fd1498Szrj 
30*38fd1498Szrj #ifndef REGMODE_NATURAL_SIZE
31*38fd1498Szrj #define REGMODE_NATURAL_SIZE(MODE)	UNITS_PER_WORD
32*38fd1498Szrj #endif
33*38fd1498Szrj 
34*38fd1498Szrj /* Maximum register number used in this function, plus one.  */
35*38fd1498Szrj 
36*38fd1498Szrj extern int max_regno;
37*38fd1498Szrj 
38*38fd1498Szrj /* REG_N_REFS and REG_N_SETS are initialized by a call to
39*38fd1498Szrj    regstat_init_n_sets_and_refs from the current values of
40*38fd1498Szrj    DF_REG_DEF_COUNT and DF_REG_USE_COUNT.  REG_N_REFS and REG_N_SETS
41*38fd1498Szrj    should only be used if a pass need to change these values in some
42*38fd1498Szrj    magical way or the pass needs to have accurate values for these
43*38fd1498Szrj    and is not using incremental df scanning.
44*38fd1498Szrj 
45*38fd1498Szrj    At the end of a pass that uses REG_N_REFS and REG_N_SETS, a call
46*38fd1498Szrj    should be made to regstat_free_n_sets_and_refs.
47*38fd1498Szrj 
48*38fd1498Szrj    Local alloc seems to play pretty loose with these values.
49*38fd1498Szrj    REG_N_REFS is set to 0 if the register is used in an asm.
50*38fd1498Szrj    Furthermore, local_alloc calls regclass to hack both REG_N_REFS and
51*38fd1498Szrj    REG_N_SETS for three address insns.  Other passes seem to have
52*38fd1498Szrj    other special values.  */
53*38fd1498Szrj 
54*38fd1498Szrj 
55*38fd1498Szrj 
56*38fd1498Szrj /* Structure to hold values for REG_N_SETS (i) and REG_N_REFS (i). */
57*38fd1498Szrj 
58*38fd1498Szrj struct regstat_n_sets_and_refs_t
59*38fd1498Szrj {
60*38fd1498Szrj   int sets;			/* # of times (REG n) is set */
61*38fd1498Szrj   int refs;			/* # of times (REG n) is used or set */
62*38fd1498Szrj };
63*38fd1498Szrj 
64*38fd1498Szrj extern struct regstat_n_sets_and_refs_t *regstat_n_sets_and_refs;
65*38fd1498Szrj 
66*38fd1498Szrj /* Indexed by n, gives number of times (REG n) is used or set.  */
67*38fd1498Szrj static inline int
REG_N_REFS(int regno)68*38fd1498Szrj REG_N_REFS (int regno)
69*38fd1498Szrj {
70*38fd1498Szrj   return regstat_n_sets_and_refs[regno].refs;
71*38fd1498Szrj }
72*38fd1498Szrj 
73*38fd1498Szrj /* Indexed by n, gives number of times (REG n) is used or set.  */
74*38fd1498Szrj #define SET_REG_N_REFS(N,V) (regstat_n_sets_and_refs[N].refs = V)
75*38fd1498Szrj #define INC_REG_N_REFS(N,V) (regstat_n_sets_and_refs[N].refs += V)
76*38fd1498Szrj 
77*38fd1498Szrj /* Indexed by n, gives number of times (REG n) is set.  */
78*38fd1498Szrj static inline int
REG_N_SETS(int regno)79*38fd1498Szrj REG_N_SETS (int regno)
80*38fd1498Szrj {
81*38fd1498Szrj   return regstat_n_sets_and_refs[regno].sets;
82*38fd1498Szrj }
83*38fd1498Szrj 
84*38fd1498Szrj /* Indexed by n, gives number of times (REG n) is set.  */
85*38fd1498Szrj #define SET_REG_N_SETS(N,V) (regstat_n_sets_and_refs[N].sets = V)
86*38fd1498Szrj #define INC_REG_N_SETS(N,V) (regstat_n_sets_and_refs[N].sets += V)
87*38fd1498Szrj 
88*38fd1498Szrj /* Given a REG, return TRUE if the reg is a PARM_DECL, FALSE otherwise.  */
89*38fd1498Szrj extern bool reg_is_parm_p (rtx);
90*38fd1498Szrj 
91*38fd1498Szrj /* Functions defined in regstat.c.  */
92*38fd1498Szrj extern void regstat_init_n_sets_and_refs (void);
93*38fd1498Szrj extern void regstat_free_n_sets_and_refs (void);
94*38fd1498Szrj extern void regstat_compute_ri (void);
95*38fd1498Szrj extern void regstat_free_ri (void);
96*38fd1498Szrj extern bitmap regstat_get_setjmp_crosses (void);
97*38fd1498Szrj extern void regstat_compute_calls_crossed (void);
98*38fd1498Szrj extern void regstat_free_calls_crossed (void);
99*38fd1498Szrj extern void dump_reg_info (FILE *);
100*38fd1498Szrj 
101*38fd1498Szrj /* Register information indexed by register number.  This structure is
102*38fd1498Szrj    initialized by calling regstat_compute_ri and is destroyed by
103*38fd1498Szrj    calling regstat_free_ri.  */
104*38fd1498Szrj struct reg_info_t
105*38fd1498Szrj {
106*38fd1498Szrj   int freq;			/* # estimated frequency (REG n) is used or set */
107*38fd1498Szrj   int deaths;			/* # of times (REG n) dies */
108*38fd1498Szrj   int calls_crossed;		/* # of calls (REG n) is live across */
109*38fd1498Szrj   int basic_block;		/* # of basic blocks (REG n) is used in */
110*38fd1498Szrj };
111*38fd1498Szrj 
112*38fd1498Szrj extern struct reg_info_t *reg_info_p;
113*38fd1498Szrj 
114*38fd1498Szrj /* The number allocated elements of reg_info_p.  */
115*38fd1498Szrj extern size_t reg_info_p_size;
116*38fd1498Szrj 
117*38fd1498Szrj /* Estimate frequency of references to register N.  */
118*38fd1498Szrj 
119*38fd1498Szrj #define REG_FREQ(N) (reg_info_p[N].freq)
120*38fd1498Szrj 
121*38fd1498Szrj /* The weights for each insn varies from 0 to REG_FREQ_BASE.
122*38fd1498Szrj    This constant does not need to be high, as in infrequently executed
123*38fd1498Szrj    regions we want to count instructions equivalently to optimize for
124*38fd1498Szrj    size instead of speed.  */
125*38fd1498Szrj #define REG_FREQ_MAX 1000
126*38fd1498Szrj 
127*38fd1498Szrj /* Compute register frequency from the BB frequency.  When optimizing for size,
128*38fd1498Szrj    or profile driven feedback is available and the function is never executed,
129*38fd1498Szrj    frequency is always equivalent.  Otherwise rescale the basic block
130*38fd1498Szrj    frequency.  */
131*38fd1498Szrj #define REG_FREQ_FROM_BB(bb) (optimize_function_for_size_p (cfun)	      \
132*38fd1498Szrj 			      ? REG_FREQ_MAX				      \
133*38fd1498Szrj 			      : ((bb)->count.to_frequency (cfun)	      \
134*38fd1498Szrj 				* REG_FREQ_MAX / BB_FREQ_MAX)		      \
135*38fd1498Szrj 			      ? ((bb)->count.to_frequency (cfun)	      \
136*38fd1498Szrj 				 * REG_FREQ_MAX / BB_FREQ_MAX)		      \
137*38fd1498Szrj 			      : 1)
138*38fd1498Szrj 
139*38fd1498Szrj /* Indexed by N, gives number of insns in which register N dies.
140*38fd1498Szrj    Note that if register N is live around loops, it can die
141*38fd1498Szrj    in transitions between basic blocks, and that is not counted here.
142*38fd1498Szrj    So this is only a reliable indicator of how many regions of life there are
143*38fd1498Szrj    for registers that are contained in one basic block.  */
144*38fd1498Szrj 
145*38fd1498Szrj #define REG_N_DEATHS(N) (reg_info_p[N].deaths)
146*38fd1498Szrj 
147*38fd1498Szrj /* Get the number of consecutive words required to hold pseudo-reg N.  */
148*38fd1498Szrj 
149*38fd1498Szrj #define PSEUDO_REGNO_SIZE(N) \
150*38fd1498Szrj   ((GET_MODE_SIZE (PSEUDO_REGNO_MODE (N)) + UNITS_PER_WORD - 1)		\
151*38fd1498Szrj    / UNITS_PER_WORD)
152*38fd1498Szrj 
153*38fd1498Szrj /* Get the number of bytes required to hold pseudo-reg N.  */
154*38fd1498Szrj 
155*38fd1498Szrj #define PSEUDO_REGNO_BYTES(N) \
156*38fd1498Szrj   GET_MODE_SIZE (PSEUDO_REGNO_MODE (N))
157*38fd1498Szrj 
158*38fd1498Szrj /* Get the machine mode of pseudo-reg N.  */
159*38fd1498Szrj 
160*38fd1498Szrj #define PSEUDO_REGNO_MODE(N) GET_MODE (regno_reg_rtx[N])
161*38fd1498Szrj 
162*38fd1498Szrj /* Indexed by N, gives number of CALL_INSNS across which (REG n) is live.  */
163*38fd1498Szrj 
164*38fd1498Szrj #define REG_N_CALLS_CROSSED(N)  (reg_info_p[N].calls_crossed)
165*38fd1498Szrj 
166*38fd1498Szrj /* Indexed by n, gives number of basic block that  (REG n) is used in.
167*38fd1498Szrj    If the value is REG_BLOCK_GLOBAL (-1),
168*38fd1498Szrj    it means (REG n) is used in more than one basic block.
169*38fd1498Szrj    REG_BLOCK_UNKNOWN (0) means it hasn't been seen yet so we don't know.
170*38fd1498Szrj    This information remains valid for the rest of the compilation
171*38fd1498Szrj    of the current function; it is used to control register allocation.  */
172*38fd1498Szrj 
173*38fd1498Szrj #define REG_BLOCK_UNKNOWN 0
174*38fd1498Szrj #define REG_BLOCK_GLOBAL -1
175*38fd1498Szrj 
176*38fd1498Szrj #define REG_BASIC_BLOCK(N) (reg_info_p[N].basic_block)
177*38fd1498Szrj 
178*38fd1498Szrj /* Vector of substitutions of register numbers,
179*38fd1498Szrj    used to map pseudo regs into hardware regs.
180*38fd1498Szrj 
181*38fd1498Szrj    This can't be folded into reg_n_info without changing all of the
182*38fd1498Szrj    machine dependent directories, since the reload functions
183*38fd1498Szrj    in the machine dependent files access it.  */
184*38fd1498Szrj 
185*38fd1498Szrj extern short *reg_renumber;
186*38fd1498Szrj 
187*38fd1498Szrj /* Flag set by local-alloc or global-alloc if they decide to allocate
188*38fd1498Szrj    something in a call-clobbered register.  */
189*38fd1498Szrj 
190*38fd1498Szrj extern int caller_save_needed;
191*38fd1498Szrj 
192*38fd1498Szrj /* Select a register mode required for caller save of hard regno REGNO.  */
193*38fd1498Szrj #ifndef HARD_REGNO_CALLER_SAVE_MODE
194*38fd1498Szrj #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
195*38fd1498Szrj   choose_hard_reg_mode (REGNO, NREGS, false)
196*38fd1498Szrj #endif
197*38fd1498Szrj 
198*38fd1498Szrj /* Target-dependent globals.  */
199*38fd1498Szrj struct target_regs {
200*38fd1498Szrj   /* For each starting hard register, the number of consecutive hard
201*38fd1498Szrj      registers that a given machine mode occupies.  */
202*38fd1498Szrj   unsigned char x_hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE];
203*38fd1498Szrj 
204*38fd1498Szrj   /* For each hard register, the widest mode object that it can contain.
205*38fd1498Szrj      This will be a MODE_INT mode if the register can hold integers.  Otherwise
206*38fd1498Szrj      it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
207*38fd1498Szrj      register.  */
208*38fd1498Szrj   machine_mode x_reg_raw_mode[FIRST_PSEUDO_REGISTER];
209*38fd1498Szrj 
210*38fd1498Szrj   /* Vector indexed by machine mode saying whether there are regs of
211*38fd1498Szrj      that mode.  */
212*38fd1498Szrj   bool x_have_regs_of_mode[MAX_MACHINE_MODE];
213*38fd1498Szrj 
214*38fd1498Szrj   /* 1 if the corresponding class contains a register of the given mode.  */
215*38fd1498Szrj   char x_contains_reg_of_mode[N_REG_CLASSES][MAX_MACHINE_MODE];
216*38fd1498Szrj 
217*38fd1498Szrj   /* 1 if the corresponding class contains a register of the given mode
218*38fd1498Szrj      which is not global and can therefore be allocated.  */
219*38fd1498Szrj   char x_contains_allocatable_reg_of_mode[N_REG_CLASSES][MAX_MACHINE_MODE];
220*38fd1498Szrj 
221*38fd1498Szrj   /* Record for each mode whether we can move a register directly to or
222*38fd1498Szrj      from an object of that mode in memory.  If we can't, we won't try
223*38fd1498Szrj      to use that mode directly when accessing a field of that mode.  */
224*38fd1498Szrj   char x_direct_load[NUM_MACHINE_MODES];
225*38fd1498Szrj   char x_direct_store[NUM_MACHINE_MODES];
226*38fd1498Szrj 
227*38fd1498Szrj   /* Record for each mode whether we can float-extend from memory.  */
228*38fd1498Szrj   bool x_float_extend_from_mem[NUM_MACHINE_MODES][NUM_MACHINE_MODES];
229*38fd1498Szrj };
230*38fd1498Szrj 
231*38fd1498Szrj extern struct target_regs default_target_regs;
232*38fd1498Szrj #if SWITCHABLE_TARGET
233*38fd1498Szrj extern struct target_regs *this_target_regs;
234*38fd1498Szrj #else
235*38fd1498Szrj #define this_target_regs (&default_target_regs)
236*38fd1498Szrj #endif
237*38fd1498Szrj #define reg_raw_mode \
238*38fd1498Szrj   (this_target_regs->x_reg_raw_mode)
239*38fd1498Szrj #define have_regs_of_mode \
240*38fd1498Szrj   (this_target_regs->x_have_regs_of_mode)
241*38fd1498Szrj #define contains_reg_of_mode \
242*38fd1498Szrj   (this_target_regs->x_contains_reg_of_mode)
243*38fd1498Szrj #define contains_allocatable_reg_of_mode \
244*38fd1498Szrj   (this_target_regs->x_contains_allocatable_reg_of_mode)
245*38fd1498Szrj #define direct_load \
246*38fd1498Szrj   (this_target_regs->x_direct_load)
247*38fd1498Szrj #define direct_store \
248*38fd1498Szrj   (this_target_regs->x_direct_store)
249*38fd1498Szrj #define float_extend_from_mem \
250*38fd1498Szrj   (this_target_regs->x_float_extend_from_mem)
251*38fd1498Szrj 
252*38fd1498Szrj /* Return the number of hard registers in (reg:MODE REGNO).  */
253*38fd1498Szrj 
254*38fd1498Szrj ALWAYS_INLINE unsigned char
hard_regno_nregs(unsigned int regno,machine_mode mode)255*38fd1498Szrj hard_regno_nregs (unsigned int regno, machine_mode mode)
256*38fd1498Szrj {
257*38fd1498Szrj   return this_target_regs->x_hard_regno_nregs[regno][mode];
258*38fd1498Szrj }
259*38fd1498Szrj 
260*38fd1498Szrj /* Return an exclusive upper bound on the registers occupied by hard
261*38fd1498Szrj    register (reg:MODE REGNO).  */
262*38fd1498Szrj 
263*38fd1498Szrj static inline unsigned int
end_hard_regno(machine_mode mode,unsigned int regno)264*38fd1498Szrj end_hard_regno (machine_mode mode, unsigned int regno)
265*38fd1498Szrj {
266*38fd1498Szrj   return regno + hard_regno_nregs (regno, mode);
267*38fd1498Szrj }
268*38fd1498Szrj 
269*38fd1498Szrj /* Add to REGS all the registers required to store a value of mode MODE
270*38fd1498Szrj    in register REGNO.  */
271*38fd1498Szrj 
272*38fd1498Szrj static inline void
add_to_hard_reg_set(HARD_REG_SET * regs,machine_mode mode,unsigned int regno)273*38fd1498Szrj add_to_hard_reg_set (HARD_REG_SET *regs, machine_mode mode,
274*38fd1498Szrj 		     unsigned int regno)
275*38fd1498Szrj {
276*38fd1498Szrj   unsigned int end_regno;
277*38fd1498Szrj 
278*38fd1498Szrj   end_regno = end_hard_regno (mode, regno);
279*38fd1498Szrj   do
280*38fd1498Szrj     SET_HARD_REG_BIT (*regs, regno);
281*38fd1498Szrj   while (++regno < end_regno);
282*38fd1498Szrj }
283*38fd1498Szrj 
284*38fd1498Szrj /* Likewise, but remove the registers.  */
285*38fd1498Szrj 
286*38fd1498Szrj static inline void
remove_from_hard_reg_set(HARD_REG_SET * regs,machine_mode mode,unsigned int regno)287*38fd1498Szrj remove_from_hard_reg_set (HARD_REG_SET *regs, machine_mode mode,
288*38fd1498Szrj 			  unsigned int regno)
289*38fd1498Szrj {
290*38fd1498Szrj   unsigned int end_regno;
291*38fd1498Szrj 
292*38fd1498Szrj   end_regno = end_hard_regno (mode, regno);
293*38fd1498Szrj   do
294*38fd1498Szrj     CLEAR_HARD_REG_BIT (*regs, regno);
295*38fd1498Szrj   while (++regno < end_regno);
296*38fd1498Szrj }
297*38fd1498Szrj 
298*38fd1498Szrj /* Return true if REGS contains the whole of (reg:MODE REGNO).  */
299*38fd1498Szrj 
300*38fd1498Szrj static inline bool
in_hard_reg_set_p(const HARD_REG_SET regs,machine_mode mode,unsigned int regno)301*38fd1498Szrj in_hard_reg_set_p (const HARD_REG_SET regs, machine_mode mode,
302*38fd1498Szrj 		   unsigned int regno)
303*38fd1498Szrj {
304*38fd1498Szrj   unsigned int end_regno;
305*38fd1498Szrj 
306*38fd1498Szrj   gcc_assert (HARD_REGISTER_NUM_P (regno));
307*38fd1498Szrj 
308*38fd1498Szrj   if (!TEST_HARD_REG_BIT (regs, regno))
309*38fd1498Szrj     return false;
310*38fd1498Szrj 
311*38fd1498Szrj   end_regno = end_hard_regno (mode, regno);
312*38fd1498Szrj 
313*38fd1498Szrj   if (!HARD_REGISTER_NUM_P (end_regno - 1))
314*38fd1498Szrj     return false;
315*38fd1498Szrj 
316*38fd1498Szrj   while (++regno < end_regno)
317*38fd1498Szrj     if (!TEST_HARD_REG_BIT (regs, regno))
318*38fd1498Szrj       return false;
319*38fd1498Szrj 
320*38fd1498Szrj   return true;
321*38fd1498Szrj }
322*38fd1498Szrj 
323*38fd1498Szrj /* Return true if (reg:MODE REGNO) includes an element of REGS.  */
324*38fd1498Szrj 
325*38fd1498Szrj static inline bool
overlaps_hard_reg_set_p(const HARD_REG_SET regs,machine_mode mode,unsigned int regno)326*38fd1498Szrj overlaps_hard_reg_set_p (const HARD_REG_SET regs, machine_mode mode,
327*38fd1498Szrj 			 unsigned int regno)
328*38fd1498Szrj {
329*38fd1498Szrj   unsigned int end_regno;
330*38fd1498Szrj 
331*38fd1498Szrj   if (TEST_HARD_REG_BIT (regs, regno))
332*38fd1498Szrj     return true;
333*38fd1498Szrj 
334*38fd1498Szrj   end_regno = end_hard_regno (mode, regno);
335*38fd1498Szrj   while (++regno < end_regno)
336*38fd1498Szrj     if (TEST_HARD_REG_BIT (regs, regno))
337*38fd1498Szrj       return true;
338*38fd1498Szrj 
339*38fd1498Szrj   return false;
340*38fd1498Szrj }
341*38fd1498Szrj 
342*38fd1498Szrj /* Like add_to_hard_reg_set, but use a REGNO/NREGS range instead of
343*38fd1498Szrj    REGNO and MODE.  */
344*38fd1498Szrj 
345*38fd1498Szrj static inline void
add_range_to_hard_reg_set(HARD_REG_SET * regs,unsigned int regno,int nregs)346*38fd1498Szrj add_range_to_hard_reg_set (HARD_REG_SET *regs, unsigned int regno,
347*38fd1498Szrj 			   int nregs)
348*38fd1498Szrj {
349*38fd1498Szrj   while (nregs-- > 0)
350*38fd1498Szrj     SET_HARD_REG_BIT (*regs, regno + nregs);
351*38fd1498Szrj }
352*38fd1498Szrj 
353*38fd1498Szrj /* Likewise, but remove the registers.  */
354*38fd1498Szrj 
355*38fd1498Szrj static inline void
remove_range_from_hard_reg_set(HARD_REG_SET * regs,unsigned int regno,int nregs)356*38fd1498Szrj remove_range_from_hard_reg_set (HARD_REG_SET *regs, unsigned int regno,
357*38fd1498Szrj 				int nregs)
358*38fd1498Szrj {
359*38fd1498Szrj   while (nregs-- > 0)
360*38fd1498Szrj     CLEAR_HARD_REG_BIT (*regs, regno + nregs);
361*38fd1498Szrj }
362*38fd1498Szrj 
363*38fd1498Szrj /* Like overlaps_hard_reg_set_p, but use a REGNO/NREGS range instead of
364*38fd1498Szrj    REGNO and MODE.  */
365*38fd1498Szrj static inline bool
range_overlaps_hard_reg_set_p(const HARD_REG_SET set,unsigned regno,int nregs)366*38fd1498Szrj range_overlaps_hard_reg_set_p (const HARD_REG_SET set, unsigned regno,
367*38fd1498Szrj 			       int nregs)
368*38fd1498Szrj {
369*38fd1498Szrj   while (nregs-- > 0)
370*38fd1498Szrj     if (TEST_HARD_REG_BIT (set, regno + nregs))
371*38fd1498Szrj       return true;
372*38fd1498Szrj   return false;
373*38fd1498Szrj }
374*38fd1498Szrj 
375*38fd1498Szrj /* Like in_hard_reg_set_p, but use a REGNO/NREGS range instead of
376*38fd1498Szrj    REGNO and MODE.  */
377*38fd1498Szrj static inline bool
range_in_hard_reg_set_p(const HARD_REG_SET set,unsigned regno,int nregs)378*38fd1498Szrj range_in_hard_reg_set_p (const HARD_REG_SET set, unsigned regno, int nregs)
379*38fd1498Szrj {
380*38fd1498Szrj   while (nregs-- > 0)
381*38fd1498Szrj     if (!TEST_HARD_REG_BIT (set, regno + nregs))
382*38fd1498Szrj       return false;
383*38fd1498Szrj   return true;
384*38fd1498Szrj }
385*38fd1498Szrj 
386*38fd1498Szrj /* Get registers used by given function call instruction.  */
387*38fd1498Szrj extern bool get_call_reg_set_usage (rtx_insn *insn, HARD_REG_SET *reg_set,
388*38fd1498Szrj 				    HARD_REG_SET default_set);
389*38fd1498Szrj 
390*38fd1498Szrj #endif /* GCC_REGS_H */
391