1 /* Target-dependent code for AMD64. 2 3 Copyright (C) 2001-2012 Free Software Foundation, Inc. 4 5 Contributed by Jiri Smid, SuSE Labs. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "defs.h" 23 #include "opcode/i386.h" 24 #include "dis-asm.h" 25 #include "arch-utils.h" 26 #include "block.h" 27 #include "dummy-frame.h" 28 #include "frame.h" 29 #include "frame-base.h" 30 #include "frame-unwind.h" 31 #include "inferior.h" 32 #include "gdbcmd.h" 33 #include "gdbcore.h" 34 #include "objfiles.h" 35 #include "regcache.h" 36 #include "regset.h" 37 #include "symfile.h" 38 #include "disasm.h" 39 #include "gdb_assert.h" 40 #include "exceptions.h" 41 #include "amd64-tdep.h" 42 #include "i387-tdep.h" 43 44 #include "features/i386/amd64.c" 45 #include "features/i386/amd64-avx.c" 46 47 #include "ax.h" 48 #include "ax-gdb.h" 49 50 /* Note that the AMD64 architecture was previously known as x86-64. 51 The latter is (forever) engraved into the canonical system name as 52 returned by config.guess, and used as the name for the AMD64 port 53 of GNU/Linux. The BSD's have renamed their ports to amd64; they 54 don't like to shout. For GDB we prefer the amd64_-prefix over the 55 x86_64_-prefix since it's so much easier to type. */ 56 57 /* Register information. */ 58 59 static const char *amd64_register_names[] = 60 { 61 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", 62 63 /* %r8 is indeed register number 8. */ 64 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 65 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", 66 67 /* %st0 is register number 24. */ 68 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", 69 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", 70 71 /* %xmm0 is register number 40. */ 72 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 73 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 74 "mxcsr", 75 }; 76 77 static const char *amd64_ymm_names[] = 78 { 79 "ymm0", "ymm1", "ymm2", "ymm3", 80 "ymm4", "ymm5", "ymm6", "ymm7", 81 "ymm8", "ymm9", "ymm10", "ymm11", 82 "ymm12", "ymm13", "ymm14", "ymm15" 83 }; 84 85 static const char *amd64_ymmh_names[] = 86 { 87 "ymm0h", "ymm1h", "ymm2h", "ymm3h", 88 "ymm4h", "ymm5h", "ymm6h", "ymm7h", 89 "ymm8h", "ymm9h", "ymm10h", "ymm11h", 90 "ymm12h", "ymm13h", "ymm14h", "ymm15h" 91 }; 92 93 /* The registers used to pass integer arguments during a function call. */ 94 static int amd64_dummy_call_integer_regs[] = 95 { 96 AMD64_RDI_REGNUM, /* %rdi */ 97 AMD64_RSI_REGNUM, /* %rsi */ 98 AMD64_RDX_REGNUM, /* %rdx */ 99 AMD64_RCX_REGNUM, /* %rcx */ 100 8, /* %r8 */ 101 9 /* %r9 */ 102 }; 103 104 /* DWARF Register Number Mapping as defined in the System V psABI, 105 section 3.6. */ 106 107 static int amd64_dwarf_regmap[] = 108 { 109 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ 110 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, 111 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, 112 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 113 114 /* Frame Pointer Register RBP. */ 115 AMD64_RBP_REGNUM, 116 117 /* Stack Pointer Register RSP. */ 118 AMD64_RSP_REGNUM, 119 120 /* Extended Integer Registers 8 - 15. */ 121 8, 9, 10, 11, 12, 13, 14, 15, 122 123 /* Return Address RA. Mapped to RIP. */ 124 AMD64_RIP_REGNUM, 125 126 /* SSE Registers 0 - 7. */ 127 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 128 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 129 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 130 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 131 132 /* Extended SSE Registers 8 - 15. */ 133 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, 134 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, 135 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, 136 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, 137 138 /* Floating Point Registers 0-7. */ 139 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, 140 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, 141 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, 142 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, 143 144 /* Control and Status Flags Register. */ 145 AMD64_EFLAGS_REGNUM, 146 147 /* Selector Registers. */ 148 AMD64_ES_REGNUM, 149 AMD64_CS_REGNUM, 150 AMD64_SS_REGNUM, 151 AMD64_DS_REGNUM, 152 AMD64_FS_REGNUM, 153 AMD64_GS_REGNUM, 154 -1, 155 -1, 156 157 /* Segment Base Address Registers. */ 158 -1, 159 -1, 160 -1, 161 -1, 162 163 /* Special Selector Registers. */ 164 -1, 165 -1, 166 167 /* Floating Point Control Registers. */ 168 AMD64_MXCSR_REGNUM, 169 AMD64_FCTRL_REGNUM, 170 AMD64_FSTAT_REGNUM 171 }; 172 173 static const int amd64_dwarf_regmap_len = 174 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); 175 176 /* Convert DWARF register number REG to the appropriate register 177 number used by GDB. */ 178 179 static int 180 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) 181 { 182 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 183 int ymm0_regnum = tdep->ymm0_regnum; 184 int regnum = -1; 185 186 if (reg >= 0 && reg < amd64_dwarf_regmap_len) 187 regnum = amd64_dwarf_regmap[reg]; 188 189 if (regnum == -1) 190 warning (_("Unmapped DWARF Register #%d encountered."), reg); 191 else if (ymm0_regnum >= 0 192 && i386_xmm_regnum_p (gdbarch, regnum)) 193 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); 194 195 return regnum; 196 } 197 198 /* Map architectural register numbers to gdb register numbers. */ 199 200 static const int amd64_arch_regmap[16] = 201 { 202 AMD64_RAX_REGNUM, /* %rax */ 203 AMD64_RCX_REGNUM, /* %rcx */ 204 AMD64_RDX_REGNUM, /* %rdx */ 205 AMD64_RBX_REGNUM, /* %rbx */ 206 AMD64_RSP_REGNUM, /* %rsp */ 207 AMD64_RBP_REGNUM, /* %rbp */ 208 AMD64_RSI_REGNUM, /* %rsi */ 209 AMD64_RDI_REGNUM, /* %rdi */ 210 AMD64_R8_REGNUM, /* %r8 */ 211 AMD64_R9_REGNUM, /* %r9 */ 212 AMD64_R10_REGNUM, /* %r10 */ 213 AMD64_R11_REGNUM, /* %r11 */ 214 AMD64_R12_REGNUM, /* %r12 */ 215 AMD64_R13_REGNUM, /* %r13 */ 216 AMD64_R14_REGNUM, /* %r14 */ 217 AMD64_R15_REGNUM /* %r15 */ 218 }; 219 220 static const int amd64_arch_regmap_len = 221 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0])); 222 223 /* Convert architectural register number REG to the appropriate register 224 number used by GDB. */ 225 226 static int 227 amd64_arch_reg_to_regnum (int reg) 228 { 229 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len); 230 231 return amd64_arch_regmap[reg]; 232 } 233 234 /* Register names for byte pseudo-registers. */ 235 236 static const char *amd64_byte_names[] = 237 { 238 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", 239 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l", 240 "ah", "bh", "ch", "dh" 241 }; 242 243 /* Number of lower byte registers. */ 244 #define AMD64_NUM_LOWER_BYTE_REGS 16 245 246 /* Register names for word pseudo-registers. */ 247 248 static const char *amd64_word_names[] = 249 { 250 "ax", "bx", "cx", "dx", "si", "di", "bp", "", 251 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" 252 }; 253 254 /* Register names for dword pseudo-registers. */ 255 256 static const char *amd64_dword_names[] = 257 { 258 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", 259 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" 260 }; 261 262 /* Return the name of register REGNUM. */ 263 264 static const char * 265 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 266 { 267 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 268 if (i386_byte_regnum_p (gdbarch, regnum)) 269 return amd64_byte_names[regnum - tdep->al_regnum]; 270 else if (i386_ymm_regnum_p (gdbarch, regnum)) 271 return amd64_ymm_names[regnum - tdep->ymm0_regnum]; 272 else if (i386_word_regnum_p (gdbarch, regnum)) 273 return amd64_word_names[regnum - tdep->ax_regnum]; 274 else if (i386_dword_regnum_p (gdbarch, regnum)) 275 return amd64_dword_names[regnum - tdep->eax_regnum]; 276 else 277 return i386_pseudo_register_name (gdbarch, regnum); 278 } 279 280 static struct value * 281 amd64_pseudo_register_read_value (struct gdbarch *gdbarch, 282 struct regcache *regcache, 283 int regnum) 284 { 285 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 286 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 287 enum register_status status; 288 struct value *result_value; 289 gdb_byte *buf; 290 291 result_value = allocate_value (register_type (gdbarch, regnum)); 292 VALUE_LVAL (result_value) = lval_register; 293 VALUE_REGNUM (result_value) = regnum; 294 buf = value_contents_raw (result_value); 295 296 if (i386_byte_regnum_p (gdbarch, regnum)) 297 { 298 int gpnum = regnum - tdep->al_regnum; 299 300 /* Extract (always little endian). */ 301 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) 302 { 303 /* Special handling for AH, BH, CH, DH. */ 304 status = regcache_raw_read (regcache, 305 gpnum - AMD64_NUM_LOWER_BYTE_REGS, 306 raw_buf); 307 if (status == REG_VALID) 308 memcpy (buf, raw_buf + 1, 1); 309 else 310 mark_value_bytes_unavailable (result_value, 0, 311 TYPE_LENGTH (value_type (result_value))); 312 } 313 else 314 { 315 status = regcache_raw_read (regcache, gpnum, raw_buf); 316 if (status == REG_VALID) 317 memcpy (buf, raw_buf, 1); 318 else 319 mark_value_bytes_unavailable (result_value, 0, 320 TYPE_LENGTH (value_type (result_value))); 321 } 322 } 323 else if (i386_dword_regnum_p (gdbarch, regnum)) 324 { 325 int gpnum = regnum - tdep->eax_regnum; 326 /* Extract (always little endian). */ 327 status = regcache_raw_read (regcache, gpnum, raw_buf); 328 if (status == REG_VALID) 329 memcpy (buf, raw_buf, 4); 330 else 331 mark_value_bytes_unavailable (result_value, 0, 332 TYPE_LENGTH (value_type (result_value))); 333 } 334 else 335 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, 336 result_value); 337 338 return result_value; 339 } 340 341 static void 342 amd64_pseudo_register_write (struct gdbarch *gdbarch, 343 struct regcache *regcache, 344 int regnum, const gdb_byte *buf) 345 { 346 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 347 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 348 349 if (i386_byte_regnum_p (gdbarch, regnum)) 350 { 351 int gpnum = regnum - tdep->al_regnum; 352 353 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) 354 { 355 /* Read ... AH, BH, CH, DH. */ 356 regcache_raw_read (regcache, 357 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); 358 /* ... Modify ... (always little endian). */ 359 memcpy (raw_buf + 1, buf, 1); 360 /* ... Write. */ 361 regcache_raw_write (regcache, 362 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); 363 } 364 else 365 { 366 /* Read ... */ 367 regcache_raw_read (regcache, gpnum, raw_buf); 368 /* ... Modify ... (always little endian). */ 369 memcpy (raw_buf, buf, 1); 370 /* ... Write. */ 371 regcache_raw_write (regcache, gpnum, raw_buf); 372 } 373 } 374 else if (i386_dword_regnum_p (gdbarch, regnum)) 375 { 376 int gpnum = regnum - tdep->eax_regnum; 377 378 /* Read ... */ 379 regcache_raw_read (regcache, gpnum, raw_buf); 380 /* ... Modify ... (always little endian). */ 381 memcpy (raw_buf, buf, 4); 382 /* ... Write. */ 383 regcache_raw_write (regcache, gpnum, raw_buf); 384 } 385 else 386 i386_pseudo_register_write (gdbarch, regcache, regnum, buf); 387 } 388 389 390 391 /* Return the union class of CLASS1 and CLASS2. See the psABI for 392 details. */ 393 394 static enum amd64_reg_class 395 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) 396 { 397 /* Rule (a): If both classes are equal, this is the resulting class. */ 398 if (class1 == class2) 399 return class1; 400 401 /* Rule (b): If one of the classes is NO_CLASS, the resulting class 402 is the other class. */ 403 if (class1 == AMD64_NO_CLASS) 404 return class2; 405 if (class2 == AMD64_NO_CLASS) 406 return class1; 407 408 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ 409 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) 410 return AMD64_MEMORY; 411 412 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ 413 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) 414 return AMD64_INTEGER; 415 416 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, 417 MEMORY is used as class. */ 418 if (class1 == AMD64_X87 || class1 == AMD64_X87UP 419 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 420 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) 421 return AMD64_MEMORY; 422 423 /* Rule (f): Otherwise class SSE is used. */ 424 return AMD64_SSE; 425 } 426 427 /* Return non-zero if TYPE is a non-POD structure or union type. */ 428 429 static int 430 amd64_non_pod_p (struct type *type) 431 { 432 /* ??? A class with a base class certainly isn't POD, but does this 433 catch all non-POD structure types? */ 434 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) 435 return 1; 436 437 return 0; 438 } 439 440 /* Classify TYPE according to the rules for aggregate (structures and 441 arrays) and union types, and store the result in CLASS. */ 442 443 static void 444 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) 445 { 446 int len = TYPE_LENGTH (type); 447 448 /* 1. If the size of an object is larger than two eightbytes, or in 449 C++, is a non-POD structure or union type, or contains 450 unaligned fields, it has class memory. */ 451 if (len > 16 || amd64_non_pod_p (type)) 452 { 453 class[0] = class[1] = AMD64_MEMORY; 454 return; 455 } 456 457 /* 2. Both eightbytes get initialized to class NO_CLASS. */ 458 class[0] = class[1] = AMD64_NO_CLASS; 459 460 /* 3. Each field of an object is classified recursively so that 461 always two fields are considered. The resulting class is 462 calculated according to the classes of the fields in the 463 eightbyte: */ 464 465 if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 466 { 467 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); 468 469 /* All fields in an array have the same type. */ 470 amd64_classify (subtype, class); 471 if (len > 8 && class[1] == AMD64_NO_CLASS) 472 class[1] = class[0]; 473 } 474 else 475 { 476 int i; 477 478 /* Structure or union. */ 479 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT 480 || TYPE_CODE (type) == TYPE_CODE_UNION); 481 482 for (i = 0; i < TYPE_NFIELDS (type); i++) 483 { 484 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); 485 int pos = TYPE_FIELD_BITPOS (type, i) / 64; 486 enum amd64_reg_class subclass[2]; 487 int bitsize = TYPE_FIELD_BITSIZE (type, i); 488 int endpos; 489 490 if (bitsize == 0) 491 bitsize = TYPE_LENGTH (subtype) * 8; 492 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64; 493 494 /* Ignore static fields. */ 495 if (field_is_static (&TYPE_FIELD (type, i))) 496 continue; 497 498 gdb_assert (pos == 0 || pos == 1); 499 500 amd64_classify (subtype, subclass); 501 class[pos] = amd64_merge_classes (class[pos], subclass[0]); 502 if (bitsize <= 64 && pos == 0 && endpos == 1) 503 /* This is a bit of an odd case: We have a field that would 504 normally fit in one of the two eightbytes, except that 505 it is placed in a way that this field straddles them. 506 This has been seen with a structure containing an array. 507 508 The ABI is a bit unclear in this case, but we assume that 509 this field's class (stored in subclass[0]) must also be merged 510 into class[1]. In other words, our field has a piece stored 511 in the second eight-byte, and thus its class applies to 512 the second eight-byte as well. 513 514 In the case where the field length exceeds 8 bytes, 515 it should not be necessary to merge the field class 516 into class[1]. As LEN > 8, subclass[1] is necessarily 517 different from AMD64_NO_CLASS. If subclass[1] is equal 518 to subclass[0], then the normal class[1]/subclass[1] 519 merging will take care of everything. For subclass[1] 520 to be different from subclass[0], I can only see the case 521 where we have a SSE/SSEUP or X87/X87UP pair, which both 522 use up all 16 bytes of the aggregate, and are already 523 handled just fine (because each portion sits on its own 524 8-byte). */ 525 class[1] = amd64_merge_classes (class[1], subclass[0]); 526 if (pos == 0) 527 class[1] = amd64_merge_classes (class[1], subclass[1]); 528 } 529 } 530 531 /* 4. Then a post merger cleanup is done: */ 532 533 /* Rule (a): If one of the classes is MEMORY, the whole argument is 534 passed in memory. */ 535 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) 536 class[0] = class[1] = AMD64_MEMORY; 537 538 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to 539 SSE. */ 540 if (class[0] == AMD64_SSEUP) 541 class[0] = AMD64_SSE; 542 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) 543 class[1] = AMD64_SSE; 544 } 545 546 /* Classify TYPE, and store the result in CLASS. */ 547 548 void 549 amd64_classify (struct type *type, enum amd64_reg_class class[2]) 550 { 551 enum type_code code = TYPE_CODE (type); 552 int len = TYPE_LENGTH (type); 553 554 class[0] = class[1] = AMD64_NO_CLASS; 555 556 /* Arguments of types (signed and unsigned) _Bool, char, short, int, 557 long, long long, and pointers are in the INTEGER class. Similarly, 558 range types, used by languages such as Ada, are also in the INTEGER 559 class. */ 560 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM 561 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE 562 || code == TYPE_CODE_CHAR 563 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) 564 && (len == 1 || len == 2 || len == 4 || len == 8)) 565 class[0] = AMD64_INTEGER; 566 567 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 568 are in class SSE. */ 569 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) 570 && (len == 4 || len == 8)) 571 /* FIXME: __m64 . */ 572 class[0] = AMD64_SSE; 573 574 /* Arguments of types __float128, _Decimal128 and __m128 are split into 575 two halves. The least significant ones belong to class SSE, the most 576 significant one to class SSEUP. */ 577 else if (code == TYPE_CODE_DECFLOAT && len == 16) 578 /* FIXME: __float128, __m128. */ 579 class[0] = AMD64_SSE, class[1] = AMD64_SSEUP; 580 581 /* The 64-bit mantissa of arguments of type long double belongs to 582 class X87, the 16-bit exponent plus 6 bytes of padding belongs to 583 class X87UP. */ 584 else if (code == TYPE_CODE_FLT && len == 16) 585 /* Class X87 and X87UP. */ 586 class[0] = AMD64_X87, class[1] = AMD64_X87UP; 587 588 /* Aggregates. */ 589 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT 590 || code == TYPE_CODE_UNION) 591 amd64_classify_aggregate (type, class); 592 } 593 594 static enum return_value_convention 595 amd64_return_value (struct gdbarch *gdbarch, struct type *func_type, 596 struct type *type, struct regcache *regcache, 597 gdb_byte *readbuf, const gdb_byte *writebuf) 598 { 599 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 600 enum amd64_reg_class class[2]; 601 int len = TYPE_LENGTH (type); 602 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; 603 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; 604 int integer_reg = 0; 605 int sse_reg = 0; 606 int i; 607 608 gdb_assert (!(readbuf && writebuf)); 609 gdb_assert (tdep->classify); 610 611 /* 1. Classify the return type with the classification algorithm. */ 612 tdep->classify (type, class); 613 614 /* 2. If the type has class MEMORY, then the caller provides space 615 for the return value and passes the address of this storage in 616 %rdi as if it were the first argument to the function. In effect, 617 this address becomes a hidden first argument. 618 619 On return %rax will contain the address that has been passed in 620 by the caller in %rdi. */ 621 if (class[0] == AMD64_MEMORY) 622 { 623 /* As indicated by the comment above, the ABI guarantees that we 624 can always find the return value just after the function has 625 returned. */ 626 627 if (readbuf) 628 { 629 ULONGEST addr; 630 631 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); 632 read_memory (addr, readbuf, TYPE_LENGTH (type)); 633 } 634 635 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 636 } 637 638 gdb_assert (class[1] != AMD64_MEMORY); 639 gdb_assert (len <= 16); 640 641 for (i = 0; len > 0; i++, len -= 8) 642 { 643 int regnum = -1; 644 int offset = 0; 645 646 switch (class[i]) 647 { 648 case AMD64_INTEGER: 649 /* 3. If the class is INTEGER, the next available register 650 of the sequence %rax, %rdx is used. */ 651 regnum = integer_regnum[integer_reg++]; 652 break; 653 654 case AMD64_SSE: 655 /* 4. If the class is SSE, the next available SSE register 656 of the sequence %xmm0, %xmm1 is used. */ 657 regnum = sse_regnum[sse_reg++]; 658 break; 659 660 case AMD64_SSEUP: 661 /* 5. If the class is SSEUP, the eightbyte is passed in the 662 upper half of the last used SSE register. */ 663 gdb_assert (sse_reg > 0); 664 regnum = sse_regnum[sse_reg - 1]; 665 offset = 8; 666 break; 667 668 case AMD64_X87: 669 /* 6. If the class is X87, the value is returned on the X87 670 stack in %st0 as 80-bit x87 number. */ 671 regnum = AMD64_ST0_REGNUM; 672 if (writebuf) 673 i387_return_value (gdbarch, regcache); 674 break; 675 676 case AMD64_X87UP: 677 /* 7. If the class is X87UP, the value is returned together 678 with the previous X87 value in %st0. */ 679 gdb_assert (i > 0 && class[0] == AMD64_X87); 680 regnum = AMD64_ST0_REGNUM; 681 offset = 8; 682 len = 2; 683 break; 684 685 case AMD64_NO_CLASS: 686 continue; 687 688 default: 689 gdb_assert (!"Unexpected register class."); 690 } 691 692 gdb_assert (regnum != -1); 693 694 if (readbuf) 695 regcache_raw_read_part (regcache, regnum, offset, min (len, 8), 696 readbuf + i * 8); 697 if (writebuf) 698 regcache_raw_write_part (regcache, regnum, offset, min (len, 8), 699 writebuf + i * 8); 700 } 701 702 return RETURN_VALUE_REGISTER_CONVENTION; 703 } 704 705 706 static CORE_ADDR 707 amd64_push_arguments (struct regcache *regcache, int nargs, 708 struct value **args, CORE_ADDR sp, int struct_return) 709 { 710 struct gdbarch *gdbarch = get_regcache_arch (regcache); 711 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 712 int *integer_regs = tdep->call_dummy_integer_regs; 713 int num_integer_regs = tdep->call_dummy_num_integer_regs; 714 715 static int sse_regnum[] = 716 { 717 /* %xmm0 ... %xmm7 */ 718 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 719 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 720 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 721 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 722 }; 723 struct value **stack_args = alloca (nargs * sizeof (struct value *)); 724 /* An array that mirrors the stack_args array. For all arguments 725 that are passed by MEMORY, if that argument's address also needs 726 to be stored in a register, the ARG_ADDR_REGNO array will contain 727 that register number (or a negative value otherwise). */ 728 int *arg_addr_regno = alloca (nargs * sizeof (int)); 729 int num_stack_args = 0; 730 int num_elements = 0; 731 int element = 0; 732 int integer_reg = 0; 733 int sse_reg = 0; 734 int i; 735 736 gdb_assert (tdep->classify); 737 738 /* Reserve a register for the "hidden" argument. */ 739 if (struct_return) 740 integer_reg++; 741 742 for (i = 0; i < nargs; i++) 743 { 744 struct type *type = value_type (args[i]); 745 int len = TYPE_LENGTH (type); 746 enum amd64_reg_class class[2]; 747 int needed_integer_regs = 0; 748 int needed_sse_regs = 0; 749 int j; 750 751 /* Classify argument. */ 752 tdep->classify (type, class); 753 754 /* Calculate the number of integer and SSE registers needed for 755 this argument. */ 756 for (j = 0; j < 2; j++) 757 { 758 if (class[j] == AMD64_INTEGER) 759 needed_integer_regs++; 760 else if (class[j] == AMD64_SSE) 761 needed_sse_regs++; 762 } 763 764 /* Check whether enough registers are available, and if the 765 argument should be passed in registers at all. */ 766 if (integer_reg + needed_integer_regs > num_integer_regs 767 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) 768 || (needed_integer_regs == 0 && needed_sse_regs == 0)) 769 { 770 /* The argument will be passed on the stack. */ 771 num_elements += ((len + 7) / 8); 772 stack_args[num_stack_args] = args[i]; 773 /* If this is an AMD64_MEMORY argument whose address must also 774 be passed in one of the integer registers, reserve that 775 register and associate this value to that register so that 776 we can store the argument address as soon as we know it. */ 777 if (class[0] == AMD64_MEMORY 778 && tdep->memory_args_by_pointer 779 && integer_reg < tdep->call_dummy_num_integer_regs) 780 arg_addr_regno[num_stack_args] = 781 tdep->call_dummy_integer_regs[integer_reg++]; 782 else 783 arg_addr_regno[num_stack_args] = -1; 784 num_stack_args++; 785 } 786 else 787 { 788 /* The argument will be passed in registers. */ 789 const gdb_byte *valbuf = value_contents (args[i]); 790 gdb_byte buf[8]; 791 792 gdb_assert (len <= 16); 793 794 for (j = 0; len > 0; j++, len -= 8) 795 { 796 int regnum = -1; 797 int offset = 0; 798 799 switch (class[j]) 800 { 801 case AMD64_INTEGER: 802 regnum = integer_regs[integer_reg++]; 803 break; 804 805 case AMD64_SSE: 806 regnum = sse_regnum[sse_reg++]; 807 break; 808 809 case AMD64_SSEUP: 810 gdb_assert (sse_reg > 0); 811 regnum = sse_regnum[sse_reg - 1]; 812 offset = 8; 813 break; 814 815 default: 816 gdb_assert (!"Unexpected register class."); 817 } 818 819 gdb_assert (regnum != -1); 820 memset (buf, 0, sizeof buf); 821 memcpy (buf, valbuf + j * 8, min (len, 8)); 822 regcache_raw_write_part (regcache, regnum, offset, 8, buf); 823 } 824 } 825 } 826 827 /* Allocate space for the arguments on the stack. */ 828 sp -= num_elements * 8; 829 830 /* The psABI says that "The end of the input argument area shall be 831 aligned on a 16 byte boundary." */ 832 sp &= ~0xf; 833 834 /* Write out the arguments to the stack. */ 835 for (i = 0; i < num_stack_args; i++) 836 { 837 struct type *type = value_type (stack_args[i]); 838 const gdb_byte *valbuf = value_contents (stack_args[i]); 839 int len = TYPE_LENGTH (type); 840 CORE_ADDR arg_addr = sp + element * 8; 841 842 write_memory (arg_addr, valbuf, len); 843 if (arg_addr_regno[i] >= 0) 844 { 845 /* We also need to store the address of that argument in 846 the given register. */ 847 gdb_byte buf[8]; 848 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 849 850 store_unsigned_integer (buf, 8, byte_order, arg_addr); 851 regcache_cooked_write (regcache, arg_addr_regno[i], buf); 852 } 853 element += ((len + 7) / 8); 854 } 855 856 /* The psABI says that "For calls that may call functions that use 857 varargs or stdargs (prototype-less calls or calls to functions 858 containing ellipsis (...) in the declaration) %al is used as 859 hidden argument to specify the number of SSE registers used. */ 860 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); 861 return sp; 862 } 863 864 static CORE_ADDR 865 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 866 struct regcache *regcache, CORE_ADDR bp_addr, 867 int nargs, struct value **args, CORE_ADDR sp, 868 int struct_return, CORE_ADDR struct_addr) 869 { 870 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 871 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 872 gdb_byte buf[8]; 873 874 /* Pass arguments. */ 875 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); 876 877 /* Pass "hidden" argument". */ 878 if (struct_return) 879 { 880 /* The "hidden" argument is passed throught the first argument 881 register. */ 882 const int arg_regnum = tdep->call_dummy_integer_regs[0]; 883 884 store_unsigned_integer (buf, 8, byte_order, struct_addr); 885 regcache_cooked_write (regcache, arg_regnum, buf); 886 } 887 888 /* Reserve some memory on the stack for the integer-parameter registers, 889 if required by the ABI. */ 890 if (tdep->integer_param_regs_saved_in_caller_frame) 891 sp -= tdep->call_dummy_num_integer_regs * 8; 892 893 /* Store return address. */ 894 sp -= 8; 895 store_unsigned_integer (buf, 8, byte_order, bp_addr); 896 write_memory (sp, buf, 8); 897 898 /* Finally, update the stack pointer... */ 899 store_unsigned_integer (buf, 8, byte_order, sp); 900 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); 901 902 /* ...and fake a frame pointer. */ 903 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); 904 905 return sp + 16; 906 } 907 908 /* Displaced instruction handling. */ 909 910 /* A partially decoded instruction. 911 This contains enough details for displaced stepping purposes. */ 912 913 struct amd64_insn 914 { 915 /* The number of opcode bytes. */ 916 int opcode_len; 917 /* The offset of the rex prefix or -1 if not present. */ 918 int rex_offset; 919 /* The offset to the first opcode byte. */ 920 int opcode_offset; 921 /* The offset to the modrm byte or -1 if not present. */ 922 int modrm_offset; 923 924 /* The raw instruction. */ 925 gdb_byte *raw_insn; 926 }; 927 928 struct displaced_step_closure 929 { 930 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ 931 int tmp_used; 932 int tmp_regno; 933 ULONGEST tmp_save; 934 935 /* Details of the instruction. */ 936 struct amd64_insn insn_details; 937 938 /* Amount of space allocated to insn_buf. */ 939 int max_len; 940 941 /* The possibly modified insn. 942 This is a variable-length field. */ 943 gdb_byte insn_buf[1]; 944 }; 945 946 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with 947 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative, 948 at which point delete these in favor of libopcodes' versions). */ 949 950 static const unsigned char onebyte_has_modrm[256] = { 951 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 952 /* ------------------------------- */ 953 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ 954 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ 955 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ 956 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ 957 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ 958 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ 959 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ 960 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ 961 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ 962 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ 963 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ 964 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ 965 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ 966 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ 967 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ 968 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ 969 /* ------------------------------- */ 970 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 971 }; 972 973 static const unsigned char twobyte_has_modrm[256] = { 974 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 975 /* ------------------------------- */ 976 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ 977 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ 978 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ 979 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 980 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ 981 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 982 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 983 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ 984 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 985 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ 986 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ 987 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ 988 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ 989 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 990 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 991 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ 992 /* ------------------------------- */ 993 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 994 }; 995 996 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp); 997 998 static int 999 rex_prefix_p (gdb_byte pfx) 1000 { 1001 return REX_PREFIX_P (pfx); 1002 } 1003 1004 /* Skip the legacy instruction prefixes in INSN. 1005 We assume INSN is properly sentineled so we don't have to worry 1006 about falling off the end of the buffer. */ 1007 1008 static gdb_byte * 1009 amd64_skip_prefixes (gdb_byte *insn) 1010 { 1011 while (1) 1012 { 1013 switch (*insn) 1014 { 1015 case DATA_PREFIX_OPCODE: 1016 case ADDR_PREFIX_OPCODE: 1017 case CS_PREFIX_OPCODE: 1018 case DS_PREFIX_OPCODE: 1019 case ES_PREFIX_OPCODE: 1020 case FS_PREFIX_OPCODE: 1021 case GS_PREFIX_OPCODE: 1022 case SS_PREFIX_OPCODE: 1023 case LOCK_PREFIX_OPCODE: 1024 case REPE_PREFIX_OPCODE: 1025 case REPNE_PREFIX_OPCODE: 1026 ++insn; 1027 continue; 1028 default: 1029 break; 1030 } 1031 break; 1032 } 1033 1034 return insn; 1035 } 1036 1037 /* Return an integer register (other than RSP) that is unused as an input 1038 operand in INSN. 1039 In order to not require adding a rex prefix if the insn doesn't already 1040 have one, the result is restricted to RAX ... RDI, sans RSP. 1041 The register numbering of the result follows architecture ordering, 1042 e.g. RDI = 7. */ 1043 1044 static int 1045 amd64_get_unused_input_int_reg (const struct amd64_insn *details) 1046 { 1047 /* 1 bit for each reg */ 1048 int used_regs_mask = 0; 1049 1050 /* There can be at most 3 int regs used as inputs in an insn, and we have 1051 7 to choose from (RAX ... RDI, sans RSP). 1052 This allows us to take a conservative approach and keep things simple. 1053 E.g. By avoiding RAX, we don't have to specifically watch for opcodes 1054 that implicitly specify RAX. */ 1055 1056 /* Avoid RAX. */ 1057 used_regs_mask |= 1 << EAX_REG_NUM; 1058 /* Similarily avoid RDX, implicit operand in divides. */ 1059 used_regs_mask |= 1 << EDX_REG_NUM; 1060 /* Avoid RSP. */ 1061 used_regs_mask |= 1 << ESP_REG_NUM; 1062 1063 /* If the opcode is one byte long and there's no ModRM byte, 1064 assume the opcode specifies a register. */ 1065 if (details->opcode_len == 1 && details->modrm_offset == -1) 1066 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7); 1067 1068 /* Mark used regs in the modrm/sib bytes. */ 1069 if (details->modrm_offset != -1) 1070 { 1071 int modrm = details->raw_insn[details->modrm_offset]; 1072 int mod = MODRM_MOD_FIELD (modrm); 1073 int reg = MODRM_REG_FIELD (modrm); 1074 int rm = MODRM_RM_FIELD (modrm); 1075 int have_sib = mod != 3 && rm == 4; 1076 1077 /* Assume the reg field of the modrm byte specifies a register. */ 1078 used_regs_mask |= 1 << reg; 1079 1080 if (have_sib) 1081 { 1082 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]); 1083 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]); 1084 used_regs_mask |= 1 << base; 1085 used_regs_mask |= 1 << idx; 1086 } 1087 else 1088 { 1089 used_regs_mask |= 1 << rm; 1090 } 1091 } 1092 1093 gdb_assert (used_regs_mask < 256); 1094 gdb_assert (used_regs_mask != 255); 1095 1096 /* Finally, find a free reg. */ 1097 { 1098 int i; 1099 1100 for (i = 0; i < 8; ++i) 1101 { 1102 if (! (used_regs_mask & (1 << i))) 1103 return i; 1104 } 1105 1106 /* We shouldn't get here. */ 1107 internal_error (__FILE__, __LINE__, _("unable to find free reg")); 1108 } 1109 } 1110 1111 /* Extract the details of INSN that we need. */ 1112 1113 static void 1114 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) 1115 { 1116 gdb_byte *start = insn; 1117 int need_modrm; 1118 1119 details->raw_insn = insn; 1120 1121 details->opcode_len = -1; 1122 details->rex_offset = -1; 1123 details->opcode_offset = -1; 1124 details->modrm_offset = -1; 1125 1126 /* Skip legacy instruction prefixes. */ 1127 insn = amd64_skip_prefixes (insn); 1128 1129 /* Skip REX instruction prefix. */ 1130 if (rex_prefix_p (*insn)) 1131 { 1132 details->rex_offset = insn - start; 1133 ++insn; 1134 } 1135 1136 details->opcode_offset = insn - start; 1137 1138 if (*insn == TWO_BYTE_OPCODE_ESCAPE) 1139 { 1140 /* Two or three-byte opcode. */ 1141 ++insn; 1142 need_modrm = twobyte_has_modrm[*insn]; 1143 1144 /* Check for three-byte opcode. */ 1145 switch (*insn) 1146 { 1147 case 0x24: 1148 case 0x25: 1149 case 0x38: 1150 case 0x3a: 1151 case 0x7a: 1152 case 0x7b: 1153 ++insn; 1154 details->opcode_len = 3; 1155 break; 1156 default: 1157 details->opcode_len = 2; 1158 break; 1159 } 1160 } 1161 else 1162 { 1163 /* One-byte opcode. */ 1164 need_modrm = onebyte_has_modrm[*insn]; 1165 details->opcode_len = 1; 1166 } 1167 1168 if (need_modrm) 1169 { 1170 ++insn; 1171 details->modrm_offset = insn - start; 1172 } 1173 } 1174 1175 /* Update %rip-relative addressing in INSN. 1176 1177 %rip-relative addressing only uses a 32-bit displacement. 1178 32 bits is not enough to be guaranteed to cover the distance between where 1179 the real instruction is and where its copy is. 1180 Convert the insn to use base+disp addressing. 1181 We set base = pc + insn_length so we can leave disp unchanged. */ 1182 1183 static void 1184 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, 1185 CORE_ADDR from, CORE_ADDR to, struct regcache *regs) 1186 { 1187 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1188 const struct amd64_insn *insn_details = &dsc->insn_details; 1189 int modrm_offset = insn_details->modrm_offset; 1190 gdb_byte *insn = insn_details->raw_insn + modrm_offset; 1191 CORE_ADDR rip_base; 1192 int32_t disp; 1193 int insn_length; 1194 int arch_tmp_regno, tmp_regno; 1195 ULONGEST orig_value; 1196 1197 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */ 1198 ++insn; 1199 1200 /* Compute the rip-relative address. */ 1201 disp = extract_signed_integer (insn, sizeof (int32_t), byte_order); 1202 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf, 1203 dsc->max_len, from); 1204 rip_base = from + insn_length; 1205 1206 /* We need a register to hold the address. 1207 Pick one not used in the insn. 1208 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */ 1209 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details); 1210 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno); 1211 1212 /* REX.B should be unset as we were using rip-relative addressing, 1213 but ensure it's unset anyway, tmp_regno is not r8-r15. */ 1214 if (insn_details->rex_offset != -1) 1215 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B; 1216 1217 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value); 1218 dsc->tmp_regno = tmp_regno; 1219 dsc->tmp_save = orig_value; 1220 dsc->tmp_used = 1; 1221 1222 /* Convert the ModRM field to be base+disp. */ 1223 dsc->insn_buf[modrm_offset] &= ~0xc7; 1224 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno; 1225 1226 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base); 1227 1228 if (debug_displaced) 1229 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n" 1230 "displaced: using temp reg %d, old value %s, new value %s\n", 1231 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save), 1232 paddress (gdbarch, rip_base)); 1233 } 1234 1235 static void 1236 fixup_displaced_copy (struct gdbarch *gdbarch, 1237 struct displaced_step_closure *dsc, 1238 CORE_ADDR from, CORE_ADDR to, struct regcache *regs) 1239 { 1240 const struct amd64_insn *details = &dsc->insn_details; 1241 1242 if (details->modrm_offset != -1) 1243 { 1244 gdb_byte modrm = details->raw_insn[details->modrm_offset]; 1245 1246 if ((modrm & 0xc7) == 0x05) 1247 { 1248 /* The insn uses rip-relative addressing. 1249 Deal with it. */ 1250 fixup_riprel (gdbarch, dsc, from, to, regs); 1251 } 1252 } 1253 } 1254 1255 struct displaced_step_closure * 1256 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, 1257 CORE_ADDR from, CORE_ADDR to, 1258 struct regcache *regs) 1259 { 1260 int len = gdbarch_max_insn_length (gdbarch); 1261 /* Extra space for sentinels so fixup_{riprel,displaced_copy don't have to 1262 continually watch for running off the end of the buffer. */ 1263 int fixup_sentinel_space = len; 1264 struct displaced_step_closure *dsc = 1265 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space); 1266 gdb_byte *buf = &dsc->insn_buf[0]; 1267 struct amd64_insn *details = &dsc->insn_details; 1268 1269 dsc->tmp_used = 0; 1270 dsc->max_len = len + fixup_sentinel_space; 1271 1272 read_memory (from, buf, len); 1273 1274 /* Set up the sentinel space so we don't have to worry about running 1275 off the end of the buffer. An excessive number of leading prefixes 1276 could otherwise cause this. */ 1277 memset (buf + len, 0, fixup_sentinel_space); 1278 1279 amd64_get_insn_details (buf, details); 1280 1281 /* GDB may get control back after the insn after the syscall. 1282 Presumably this is a kernel bug. 1283 If this is a syscall, make sure there's a nop afterwards. */ 1284 { 1285 int syscall_length; 1286 1287 if (amd64_syscall_p (details, &syscall_length)) 1288 buf[details->opcode_offset + syscall_length] = NOP_OPCODE; 1289 } 1290 1291 /* Modify the insn to cope with the address where it will be executed from. 1292 In particular, handle any rip-relative addressing. */ 1293 fixup_displaced_copy (gdbarch, dsc, from, to, regs); 1294 1295 write_memory (to, buf, len); 1296 1297 if (debug_displaced) 1298 { 1299 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", 1300 paddress (gdbarch, from), paddress (gdbarch, to)); 1301 displaced_step_dump_bytes (gdb_stdlog, buf, len); 1302 } 1303 1304 return dsc; 1305 } 1306 1307 static int 1308 amd64_absolute_jmp_p (const struct amd64_insn *details) 1309 { 1310 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1311 1312 if (insn[0] == 0xff) 1313 { 1314 /* jump near, absolute indirect (/4) */ 1315 if ((insn[1] & 0x38) == 0x20) 1316 return 1; 1317 1318 /* jump far, absolute indirect (/5) */ 1319 if ((insn[1] & 0x38) == 0x28) 1320 return 1; 1321 } 1322 1323 return 0; 1324 } 1325 1326 static int 1327 amd64_absolute_call_p (const struct amd64_insn *details) 1328 { 1329 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1330 1331 if (insn[0] == 0xff) 1332 { 1333 /* Call near, absolute indirect (/2) */ 1334 if ((insn[1] & 0x38) == 0x10) 1335 return 1; 1336 1337 /* Call far, absolute indirect (/3) */ 1338 if ((insn[1] & 0x38) == 0x18) 1339 return 1; 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int 1346 amd64_ret_p (const struct amd64_insn *details) 1347 { 1348 /* NOTE: gcc can emit "repz ; ret". */ 1349 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1350 1351 switch (insn[0]) 1352 { 1353 case 0xc2: /* ret near, pop N bytes */ 1354 case 0xc3: /* ret near */ 1355 case 0xca: /* ret far, pop N bytes */ 1356 case 0xcb: /* ret far */ 1357 case 0xcf: /* iret */ 1358 return 1; 1359 1360 default: 1361 return 0; 1362 } 1363 } 1364 1365 static int 1366 amd64_call_p (const struct amd64_insn *details) 1367 { 1368 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1369 1370 if (amd64_absolute_call_p (details)) 1371 return 1; 1372 1373 /* call near, relative */ 1374 if (insn[0] == 0xe8) 1375 return 1; 1376 1377 return 0; 1378 } 1379 1380 /* Return non-zero if INSN is a system call, and set *LENGTHP to its 1381 length in bytes. Otherwise, return zero. */ 1382 1383 static int 1384 amd64_syscall_p (const struct amd64_insn *details, int *lengthp) 1385 { 1386 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1387 1388 if (insn[0] == 0x0f && insn[1] == 0x05) 1389 { 1390 *lengthp = 2; 1391 return 1; 1392 } 1393 1394 return 0; 1395 } 1396 1397 /* Fix up the state of registers and memory after having single-stepped 1398 a displaced instruction. */ 1399 1400 void 1401 amd64_displaced_step_fixup (struct gdbarch *gdbarch, 1402 struct displaced_step_closure *dsc, 1403 CORE_ADDR from, CORE_ADDR to, 1404 struct regcache *regs) 1405 { 1406 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1407 /* The offset we applied to the instruction's address. */ 1408 ULONGEST insn_offset = to - from; 1409 gdb_byte *insn = dsc->insn_buf; 1410 const struct amd64_insn *insn_details = &dsc->insn_details; 1411 1412 if (debug_displaced) 1413 fprintf_unfiltered (gdb_stdlog, 1414 "displaced: fixup (%s, %s), " 1415 "insn = 0x%02x 0x%02x ...\n", 1416 paddress (gdbarch, from), paddress (gdbarch, to), 1417 insn[0], insn[1]); 1418 1419 /* If we used a tmp reg, restore it. */ 1420 1421 if (dsc->tmp_used) 1422 { 1423 if (debug_displaced) 1424 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n", 1425 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); 1426 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save); 1427 } 1428 1429 /* The list of issues to contend with here is taken from 1430 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28. 1431 Yay for Free Software! */ 1432 1433 /* Relocate the %rip back to the program's instruction stream, 1434 if necessary. */ 1435 1436 /* Except in the case of absolute or indirect jump or call 1437 instructions, or a return instruction, the new rip is relative to 1438 the displaced instruction; make it relative to the original insn. 1439 Well, signal handler returns don't need relocation either, but we use the 1440 value of %rip to recognize those; see below. */ 1441 if (! amd64_absolute_jmp_p (insn_details) 1442 && ! amd64_absolute_call_p (insn_details) 1443 && ! amd64_ret_p (insn_details)) 1444 { 1445 ULONGEST orig_rip; 1446 int insn_len; 1447 1448 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip); 1449 1450 /* A signal trampoline system call changes the %rip, resuming 1451 execution of the main program after the signal handler has 1452 returned. That makes them like 'return' instructions; we 1453 shouldn't relocate %rip. 1454 1455 But most system calls don't, and we do need to relocate %rip. 1456 1457 Our heuristic for distinguishing these cases: if stepping 1458 over the system call instruction left control directly after 1459 the instruction, the we relocate --- control almost certainly 1460 doesn't belong in the displaced copy. Otherwise, we assume 1461 the instruction has put control where it belongs, and leave 1462 it unrelocated. Goodness help us if there are PC-relative 1463 system calls. */ 1464 if (amd64_syscall_p (insn_details, &insn_len) 1465 && orig_rip != to + insn_len 1466 /* GDB can get control back after the insn after the syscall. 1467 Presumably this is a kernel bug. 1468 Fixup ensures its a nop, we add one to the length for it. */ 1469 && orig_rip != to + insn_len + 1) 1470 { 1471 if (debug_displaced) 1472 fprintf_unfiltered (gdb_stdlog, 1473 "displaced: syscall changed %%rip; " 1474 "not relocating\n"); 1475 } 1476 else 1477 { 1478 ULONGEST rip = orig_rip - insn_offset; 1479 1480 /* If we just stepped over a breakpoint insn, we don't backup 1481 the pc on purpose; this is to match behaviour without 1482 stepping. */ 1483 1484 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip); 1485 1486 if (debug_displaced) 1487 fprintf_unfiltered (gdb_stdlog, 1488 "displaced: " 1489 "relocated %%rip from %s to %s\n", 1490 paddress (gdbarch, orig_rip), 1491 paddress (gdbarch, rip)); 1492 } 1493 } 1494 1495 /* If the instruction was PUSHFL, then the TF bit will be set in the 1496 pushed value, and should be cleared. We'll leave this for later, 1497 since GDB already messes up the TF flag when stepping over a 1498 pushfl. */ 1499 1500 /* If the instruction was a call, the return address now atop the 1501 stack is the address following the copied instruction. We need 1502 to make it the address following the original instruction. */ 1503 if (amd64_call_p (insn_details)) 1504 { 1505 ULONGEST rsp; 1506 ULONGEST retaddr; 1507 const ULONGEST retaddr_len = 8; 1508 1509 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp); 1510 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order); 1511 retaddr = (retaddr - insn_offset) & 0xffffffffUL; 1512 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr); 1513 1514 if (debug_displaced) 1515 fprintf_unfiltered (gdb_stdlog, 1516 "displaced: relocated return addr at %s " 1517 "to %s\n", 1518 paddress (gdbarch, rsp), 1519 paddress (gdbarch, retaddr)); 1520 } 1521 } 1522 1523 /* If the instruction INSN uses RIP-relative addressing, return the 1524 offset into the raw INSN where the displacement to be adjusted is 1525 found. Returns 0 if the instruction doesn't use RIP-relative 1526 addressing. */ 1527 1528 static int 1529 rip_relative_offset (struct amd64_insn *insn) 1530 { 1531 if (insn->modrm_offset != -1) 1532 { 1533 gdb_byte modrm = insn->raw_insn[insn->modrm_offset]; 1534 1535 if ((modrm & 0xc7) == 0x05) 1536 { 1537 /* The displacement is found right after the ModRM byte. */ 1538 return insn->modrm_offset + 1; 1539 } 1540 } 1541 1542 return 0; 1543 } 1544 1545 static void 1546 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) 1547 { 1548 target_write_memory (*to, buf, len); 1549 *to += len; 1550 } 1551 1552 static void 1553 amd64_relocate_instruction (struct gdbarch *gdbarch, 1554 CORE_ADDR *to, CORE_ADDR oldloc) 1555 { 1556 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1557 int len = gdbarch_max_insn_length (gdbarch); 1558 /* Extra space for sentinels. */ 1559 int fixup_sentinel_space = len; 1560 gdb_byte *buf = xmalloc (len + fixup_sentinel_space); 1561 struct amd64_insn insn_details; 1562 int offset = 0; 1563 LONGEST rel32, newrel; 1564 gdb_byte *insn; 1565 int insn_length; 1566 1567 read_memory (oldloc, buf, len); 1568 1569 /* Set up the sentinel space so we don't have to worry about running 1570 off the end of the buffer. An excessive number of leading prefixes 1571 could otherwise cause this. */ 1572 memset (buf + len, 0, fixup_sentinel_space); 1573 1574 insn = buf; 1575 amd64_get_insn_details (insn, &insn_details); 1576 1577 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc); 1578 1579 /* Skip legacy instruction prefixes. */ 1580 insn = amd64_skip_prefixes (insn); 1581 1582 /* Adjust calls with 32-bit relative addresses as push/jump, with 1583 the address pushed being the location where the original call in 1584 the user program would return to. */ 1585 if (insn[0] == 0xe8) 1586 { 1587 gdb_byte push_buf[16]; 1588 unsigned int ret_addr; 1589 1590 /* Where "ret" in the original code will return to. */ 1591 ret_addr = oldloc + insn_length; 1592 push_buf[0] = 0x68; /* pushq $... */ 1593 memcpy (&push_buf[1], &ret_addr, 4); 1594 /* Push the push. */ 1595 append_insns (to, 5, push_buf); 1596 1597 /* Convert the relative call to a relative jump. */ 1598 insn[0] = 0xe9; 1599 1600 /* Adjust the destination offset. */ 1601 rel32 = extract_signed_integer (insn + 1, 4, byte_order); 1602 newrel = (oldloc - *to) + rel32; 1603 store_signed_integer (insn + 1, 4, byte_order, newrel); 1604 1605 if (debug_displaced) 1606 fprintf_unfiltered (gdb_stdlog, 1607 "Adjusted insn rel32=%s at %s to" 1608 " rel32=%s at %s\n", 1609 hex_string (rel32), paddress (gdbarch, oldloc), 1610 hex_string (newrel), paddress (gdbarch, *to)); 1611 1612 /* Write the adjusted jump into its displaced location. */ 1613 append_insns (to, 5, insn); 1614 return; 1615 } 1616 1617 offset = rip_relative_offset (&insn_details); 1618 if (!offset) 1619 { 1620 /* Adjust jumps with 32-bit relative addresses. Calls are 1621 already handled above. */ 1622 if (insn[0] == 0xe9) 1623 offset = 1; 1624 /* Adjust conditional jumps. */ 1625 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) 1626 offset = 2; 1627 } 1628 1629 if (offset) 1630 { 1631 rel32 = extract_signed_integer (insn + offset, 4, byte_order); 1632 newrel = (oldloc - *to) + rel32; 1633 store_signed_integer (insn + offset, 4, byte_order, newrel); 1634 if (debug_displaced) 1635 fprintf_unfiltered (gdb_stdlog, 1636 "Adjusted insn rel32=%s at %s to" 1637 " rel32=%s at %s\n", 1638 hex_string (rel32), paddress (gdbarch, oldloc), 1639 hex_string (newrel), paddress (gdbarch, *to)); 1640 } 1641 1642 /* Write the adjusted instruction into its displaced location. */ 1643 append_insns (to, insn_length, buf); 1644 } 1645 1646 1647 /* The maximum number of saved registers. This should include %rip. */ 1648 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS 1649 1650 struct amd64_frame_cache 1651 { 1652 /* Base address. */ 1653 CORE_ADDR base; 1654 int base_p; 1655 CORE_ADDR sp_offset; 1656 CORE_ADDR pc; 1657 1658 /* Saved registers. */ 1659 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; 1660 CORE_ADDR saved_sp; 1661 int saved_sp_reg; 1662 1663 /* Do we have a frame? */ 1664 int frameless_p; 1665 }; 1666 1667 /* Initialize a frame cache. */ 1668 1669 static void 1670 amd64_init_frame_cache (struct amd64_frame_cache *cache) 1671 { 1672 int i; 1673 1674 /* Base address. */ 1675 cache->base = 0; 1676 cache->base_p = 0; 1677 cache->sp_offset = -8; 1678 cache->pc = 0; 1679 1680 /* Saved registers. We initialize these to -1 since zero is a valid 1681 offset (that's where %rbp is supposed to be stored). 1682 The values start out as being offsets, and are later converted to 1683 addresses (at which point -1 is interpreted as an address, still meaning 1684 "invalid"). */ 1685 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 1686 cache->saved_regs[i] = -1; 1687 cache->saved_sp = 0; 1688 cache->saved_sp_reg = -1; 1689 1690 /* Frameless until proven otherwise. */ 1691 cache->frameless_p = 1; 1692 } 1693 1694 /* Allocate and initialize a frame cache. */ 1695 1696 static struct amd64_frame_cache * 1697 amd64_alloc_frame_cache (void) 1698 { 1699 struct amd64_frame_cache *cache; 1700 1701 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); 1702 amd64_init_frame_cache (cache); 1703 return cache; 1704 } 1705 1706 /* GCC 4.4 and later, can put code in the prologue to realign the 1707 stack pointer. Check whether PC points to such code, and update 1708 CACHE accordingly. Return the first instruction after the code 1709 sequence or CURRENT_PC, whichever is smaller. If we don't 1710 recognize the code, return PC. */ 1711 1712 static CORE_ADDR 1713 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, 1714 struct amd64_frame_cache *cache) 1715 { 1716 /* There are 2 code sequences to re-align stack before the frame 1717 gets set up: 1718 1719 1. Use a caller-saved saved register: 1720 1721 leaq 8(%rsp), %reg 1722 andq $-XXX, %rsp 1723 pushq -8(%reg) 1724 1725 2. Use a callee-saved saved register: 1726 1727 pushq %reg 1728 leaq 16(%rsp), %reg 1729 andq $-XXX, %rsp 1730 pushq -8(%reg) 1731 1732 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: 1733 1734 0x48 0x83 0xe4 0xf0 andq $-16, %rsp 1735 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp 1736 */ 1737 1738 gdb_byte buf[18]; 1739 int reg, r; 1740 int offset, offset_and; 1741 1742 if (target_read_memory (pc, buf, sizeof buf)) 1743 return pc; 1744 1745 /* Check caller-saved saved register. The first instruction has 1746 to be "leaq 8(%rsp), %reg". */ 1747 if ((buf[0] & 0xfb) == 0x48 1748 && buf[1] == 0x8d 1749 && buf[3] == 0x24 1750 && buf[4] == 0x8) 1751 { 1752 /* MOD must be binary 10 and R/M must be binary 100. */ 1753 if ((buf[2] & 0xc7) != 0x44) 1754 return pc; 1755 1756 /* REG has register number. */ 1757 reg = (buf[2] >> 3) & 7; 1758 1759 /* Check the REX.R bit. */ 1760 if (buf[0] == 0x4c) 1761 reg += 8; 1762 1763 offset = 5; 1764 } 1765 else 1766 { 1767 /* Check callee-saved saved register. The first instruction 1768 has to be "pushq %reg". */ 1769 reg = 0; 1770 if ((buf[0] & 0xf8) == 0x50) 1771 offset = 0; 1772 else if ((buf[0] & 0xf6) == 0x40 1773 && (buf[1] & 0xf8) == 0x50) 1774 { 1775 /* Check the REX.B bit. */ 1776 if ((buf[0] & 1) != 0) 1777 reg = 8; 1778 1779 offset = 1; 1780 } 1781 else 1782 return pc; 1783 1784 /* Get register. */ 1785 reg += buf[offset] & 0x7; 1786 1787 offset++; 1788 1789 /* The next instruction has to be "leaq 16(%rsp), %reg". */ 1790 if ((buf[offset] & 0xfb) != 0x48 1791 || buf[offset + 1] != 0x8d 1792 || buf[offset + 3] != 0x24 1793 || buf[offset + 4] != 0x10) 1794 return pc; 1795 1796 /* MOD must be binary 10 and R/M must be binary 100. */ 1797 if ((buf[offset + 2] & 0xc7) != 0x44) 1798 return pc; 1799 1800 /* REG has register number. */ 1801 r = (buf[offset + 2] >> 3) & 7; 1802 1803 /* Check the REX.R bit. */ 1804 if (buf[offset] == 0x4c) 1805 r += 8; 1806 1807 /* Registers in pushq and leaq have to be the same. */ 1808 if (reg != r) 1809 return pc; 1810 1811 offset += 5; 1812 } 1813 1814 /* Rigister can't be %rsp nor %rbp. */ 1815 if (reg == 4 || reg == 5) 1816 return pc; 1817 1818 /* The next instruction has to be "andq $-XXX, %rsp". */ 1819 if (buf[offset] != 0x48 1820 || buf[offset + 2] != 0xe4 1821 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) 1822 return pc; 1823 1824 offset_and = offset; 1825 offset += buf[offset + 1] == 0x81 ? 7 : 4; 1826 1827 /* The next instruction has to be "pushq -8(%reg)". */ 1828 r = 0; 1829 if (buf[offset] == 0xff) 1830 offset++; 1831 else if ((buf[offset] & 0xf6) == 0x40 1832 && buf[offset + 1] == 0xff) 1833 { 1834 /* Check the REX.B bit. */ 1835 if ((buf[offset] & 0x1) != 0) 1836 r = 8; 1837 offset += 2; 1838 } 1839 else 1840 return pc; 1841 1842 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary 1843 01. */ 1844 if (buf[offset + 1] != 0xf8 1845 || (buf[offset] & 0xf8) != 0x70) 1846 return pc; 1847 1848 /* R/M has register. */ 1849 r += buf[offset] & 7; 1850 1851 /* Registers in leaq and pushq have to be the same. */ 1852 if (reg != r) 1853 return pc; 1854 1855 if (current_pc > pc + offset_and) 1856 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); 1857 1858 return min (pc + offset + 2, current_pc); 1859 } 1860 1861 /* Do a limited analysis of the prologue at PC and update CACHE 1862 accordingly. Bail out early if CURRENT_PC is reached. Return the 1863 address where the analysis stopped. 1864 1865 We will handle only functions beginning with: 1866 1867 pushq %rbp 0x55 1868 movq %rsp, %rbp 0x48 0x89 0xe5 1869 1870 Any function that doesn't start with this sequence will be assumed 1871 to have no prologue and thus no valid frame pointer in %rbp. */ 1872 1873 static CORE_ADDR 1874 amd64_analyze_prologue (struct gdbarch *gdbarch, 1875 CORE_ADDR pc, CORE_ADDR current_pc, 1876 struct amd64_frame_cache *cache) 1877 { 1878 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1879 static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */ 1880 gdb_byte buf[3]; 1881 gdb_byte op; 1882 1883 if (current_pc <= pc) 1884 return current_pc; 1885 1886 pc = amd64_analyze_stack_align (pc, current_pc, cache); 1887 1888 op = read_memory_unsigned_integer (pc, 1, byte_order); 1889 1890 if (op == 0x55) /* pushq %rbp */ 1891 { 1892 /* Take into account that we've executed the `pushq %rbp' that 1893 starts this instruction sequence. */ 1894 cache->saved_regs[AMD64_RBP_REGNUM] = 0; 1895 cache->sp_offset += 8; 1896 1897 /* If that's all, return now. */ 1898 if (current_pc <= pc + 1) 1899 return current_pc; 1900 1901 /* Check for `movq %rsp, %rbp'. */ 1902 read_memory (pc + 1, buf, 3); 1903 if (memcmp (buf, proto, 3) != 0) 1904 return pc + 1; 1905 1906 /* OK, we actually have a frame. */ 1907 cache->frameless_p = 0; 1908 return pc + 4; 1909 } 1910 1911 return pc; 1912 } 1913 1914 /* Work around false termination of prologue - GCC PR debug/48827. 1915 1916 START_PC is the first instruction of a function, PC is its minimal already 1917 determined advanced address. Function returns PC if it has nothing to do. 1918 1919 84 c0 test %al,%al 1920 74 23 je after 1921 <-- here is 0 lines advance - the false prologue end marker. 1922 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp) 1923 0f 29 4d 80 movaps %xmm1,-0x80(%rbp) 1924 0f 29 55 90 movaps %xmm2,-0x70(%rbp) 1925 0f 29 5d a0 movaps %xmm3,-0x60(%rbp) 1926 0f 29 65 b0 movaps %xmm4,-0x50(%rbp) 1927 0f 29 6d c0 movaps %xmm5,-0x40(%rbp) 1928 0f 29 75 d0 movaps %xmm6,-0x30(%rbp) 1929 0f 29 7d e0 movaps %xmm7,-0x20(%rbp) 1930 after: */ 1931 1932 static CORE_ADDR 1933 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) 1934 { 1935 struct symtab_and_line start_pc_sal, next_sal; 1936 gdb_byte buf[4 + 8 * 7]; 1937 int offset, xmmreg; 1938 1939 if (pc == start_pc) 1940 return pc; 1941 1942 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0); 1943 if (start_pc_sal.symtab == NULL 1944 || producer_is_gcc_ge_4 (start_pc_sal.symtab->producer) < 6 1945 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end) 1946 return pc; 1947 1948 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0); 1949 if (next_sal.line != start_pc_sal.line) 1950 return pc; 1951 1952 /* START_PC can be from overlayed memory, ignored here. */ 1953 if (target_read_memory (next_sal.pc - 4, buf, sizeof (buf)) != 0) 1954 return pc; 1955 1956 /* test %al,%al */ 1957 if (buf[0] != 0x84 || buf[1] != 0xc0) 1958 return pc; 1959 /* je AFTER */ 1960 if (buf[2] != 0x74) 1961 return pc; 1962 1963 offset = 4; 1964 for (xmmreg = 0; xmmreg < 8; xmmreg++) 1965 { 1966 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */ 1967 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29 1968 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5)) 1969 return pc; 1970 1971 /* 0b01?????? */ 1972 if ((buf[offset + 2] & 0xc0) == 0x40) 1973 { 1974 /* 8-bit displacement. */ 1975 offset += 4; 1976 } 1977 /* 0b10?????? */ 1978 else if ((buf[offset + 2] & 0xc0) == 0x80) 1979 { 1980 /* 32-bit displacement. */ 1981 offset += 7; 1982 } 1983 else 1984 return pc; 1985 } 1986 1987 /* je AFTER */ 1988 if (offset - 4 != buf[3]) 1989 return pc; 1990 1991 return next_sal.end; 1992 } 1993 1994 /* Return PC of first real instruction. */ 1995 1996 static CORE_ADDR 1997 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1998 { 1999 struct amd64_frame_cache cache; 2000 CORE_ADDR pc; 2001 2002 amd64_init_frame_cache (&cache); 2003 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL, 2004 &cache); 2005 if (cache.frameless_p) 2006 return start_pc; 2007 2008 return amd64_skip_xmm_prologue (pc, start_pc); 2009 } 2010 2011 2012 /* Normal frames. */ 2013 2014 static void 2015 amd64_frame_cache_1 (struct frame_info *this_frame, 2016 struct amd64_frame_cache *cache) 2017 { 2018 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2019 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2020 gdb_byte buf[8]; 2021 int i; 2022 2023 cache->pc = get_frame_func (this_frame); 2024 if (cache->pc != 0) 2025 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), 2026 cache); 2027 2028 if (cache->frameless_p) 2029 { 2030 /* We didn't find a valid frame. If we're at the start of a 2031 function, or somewhere half-way its prologue, the function's 2032 frame probably hasn't been fully setup yet. Try to 2033 reconstruct the base address for the stack frame by looking 2034 at the stack pointer. For truly "frameless" functions this 2035 might work too. */ 2036 2037 if (cache->saved_sp_reg != -1) 2038 { 2039 /* Stack pointer has been saved. */ 2040 get_frame_register (this_frame, cache->saved_sp_reg, buf); 2041 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order); 2042 2043 /* We're halfway aligning the stack. */ 2044 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8; 2045 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8; 2046 2047 /* This will be added back below. */ 2048 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base; 2049 } 2050 else 2051 { 2052 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2053 cache->base = extract_unsigned_integer (buf, 8, byte_order) 2054 + cache->sp_offset; 2055 } 2056 } 2057 else 2058 { 2059 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf); 2060 cache->base = extract_unsigned_integer (buf, 8, byte_order); 2061 } 2062 2063 /* Now that we have the base address for the stack frame we can 2064 calculate the value of %rsp in the calling frame. */ 2065 cache->saved_sp = cache->base + 16; 2066 2067 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a 2068 frame we find it at the same offset from the reconstructed base 2069 address. If we're halfway aligning the stack, %rip is handled 2070 differently (see above). */ 2071 if (!cache->frameless_p || cache->saved_sp_reg == -1) 2072 cache->saved_regs[AMD64_RIP_REGNUM] = 8; 2073 2074 /* Adjust all the saved registers such that they contain addresses 2075 instead of offsets. */ 2076 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 2077 if (cache->saved_regs[i] != -1) 2078 cache->saved_regs[i] += cache->base; 2079 2080 cache->base_p = 1; 2081 } 2082 2083 static struct amd64_frame_cache * 2084 amd64_frame_cache (struct frame_info *this_frame, void **this_cache) 2085 { 2086 volatile struct gdb_exception ex; 2087 struct amd64_frame_cache *cache; 2088 2089 if (*this_cache) 2090 return *this_cache; 2091 2092 cache = amd64_alloc_frame_cache (); 2093 *this_cache = cache; 2094 2095 TRY_CATCH (ex, RETURN_MASK_ERROR) 2096 { 2097 amd64_frame_cache_1 (this_frame, cache); 2098 } 2099 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) 2100 throw_exception (ex); 2101 2102 return cache; 2103 } 2104 2105 static enum unwind_stop_reason 2106 amd64_frame_unwind_stop_reason (struct frame_info *this_frame, 2107 void **this_cache) 2108 { 2109 struct amd64_frame_cache *cache = 2110 amd64_frame_cache (this_frame, this_cache); 2111 2112 if (!cache->base_p) 2113 return UNWIND_UNAVAILABLE; 2114 2115 /* This marks the outermost frame. */ 2116 if (cache->base == 0) 2117 return UNWIND_OUTERMOST; 2118 2119 return UNWIND_NO_REASON; 2120 } 2121 2122 static void 2123 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache, 2124 struct frame_id *this_id) 2125 { 2126 struct amd64_frame_cache *cache = 2127 amd64_frame_cache (this_frame, this_cache); 2128 2129 if (!cache->base_p) 2130 return; 2131 2132 /* This marks the outermost frame. */ 2133 if (cache->base == 0) 2134 return; 2135 2136 (*this_id) = frame_id_build (cache->base + 16, cache->pc); 2137 } 2138 2139 static struct value * 2140 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache, 2141 int regnum) 2142 { 2143 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2144 struct amd64_frame_cache *cache = 2145 amd64_frame_cache (this_frame, this_cache); 2146 2147 gdb_assert (regnum >= 0); 2148 2149 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) 2150 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); 2151 2152 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 2153 return frame_unwind_got_memory (this_frame, regnum, 2154 cache->saved_regs[regnum]); 2155 2156 return frame_unwind_got_register (this_frame, regnum, regnum); 2157 } 2158 2159 static const struct frame_unwind amd64_frame_unwind = 2160 { 2161 NORMAL_FRAME, 2162 amd64_frame_unwind_stop_reason, 2163 amd64_frame_this_id, 2164 amd64_frame_prev_register, 2165 NULL, 2166 default_frame_sniffer 2167 }; 2168 2169 /* Generate a bytecode expression to get the value of the saved PC. */ 2170 2171 static void 2172 amd64_gen_return_address (struct gdbarch *gdbarch, 2173 struct agent_expr *ax, struct axs_value *value, 2174 CORE_ADDR scope) 2175 { 2176 /* The following sequence assumes the traditional use of the base 2177 register. */ 2178 ax_reg (ax, AMD64_RBP_REGNUM); 2179 ax_const_l (ax, 8); 2180 ax_simple (ax, aop_add); 2181 value->type = register_type (gdbarch, AMD64_RIP_REGNUM); 2182 value->kind = axs_lvalue_memory; 2183 } 2184 2185 2186 /* Signal trampolines. */ 2187 2188 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and 2189 64-bit variants. This would require using identical frame caches 2190 on both platforms. */ 2191 2192 static struct amd64_frame_cache * 2193 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) 2194 { 2195 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2196 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2197 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2198 volatile struct gdb_exception ex; 2199 struct amd64_frame_cache *cache; 2200 CORE_ADDR addr; 2201 gdb_byte buf[8]; 2202 int i; 2203 2204 if (*this_cache) 2205 return *this_cache; 2206 2207 cache = amd64_alloc_frame_cache (); 2208 2209 TRY_CATCH (ex, RETURN_MASK_ERROR) 2210 { 2211 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2212 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8; 2213 2214 addr = tdep->sigcontext_addr (this_frame); 2215 gdb_assert (tdep->sc_reg_offset); 2216 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); 2217 for (i = 0; i < tdep->sc_num_regs; i++) 2218 if (tdep->sc_reg_offset[i] != -1) 2219 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 2220 2221 cache->base_p = 1; 2222 } 2223 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) 2224 throw_exception (ex); 2225 2226 *this_cache = cache; 2227 return cache; 2228 } 2229 2230 static enum unwind_stop_reason 2231 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, 2232 void **this_cache) 2233 { 2234 struct amd64_frame_cache *cache = 2235 amd64_sigtramp_frame_cache (this_frame, this_cache); 2236 2237 if (!cache->base_p) 2238 return UNWIND_UNAVAILABLE; 2239 2240 return UNWIND_NO_REASON; 2241 } 2242 2243 static void 2244 amd64_sigtramp_frame_this_id (struct frame_info *this_frame, 2245 void **this_cache, struct frame_id *this_id) 2246 { 2247 struct amd64_frame_cache *cache = 2248 amd64_sigtramp_frame_cache (this_frame, this_cache); 2249 2250 if (!cache->base_p) 2251 return; 2252 2253 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame)); 2254 } 2255 2256 static struct value * 2257 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame, 2258 void **this_cache, int regnum) 2259 { 2260 /* Make sure we've initialized the cache. */ 2261 amd64_sigtramp_frame_cache (this_frame, this_cache); 2262 2263 return amd64_frame_prev_register (this_frame, this_cache, regnum); 2264 } 2265 2266 static int 2267 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, 2268 struct frame_info *this_frame, 2269 void **this_cache) 2270 { 2271 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); 2272 2273 /* We shouldn't even bother if we don't have a sigcontext_addr 2274 handler. */ 2275 if (tdep->sigcontext_addr == NULL) 2276 return 0; 2277 2278 if (tdep->sigtramp_p != NULL) 2279 { 2280 if (tdep->sigtramp_p (this_frame)) 2281 return 1; 2282 } 2283 2284 if (tdep->sigtramp_start != 0) 2285 { 2286 CORE_ADDR pc = get_frame_pc (this_frame); 2287 2288 gdb_assert (tdep->sigtramp_end != 0); 2289 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) 2290 return 1; 2291 } 2292 2293 return 0; 2294 } 2295 2296 static const struct frame_unwind amd64_sigtramp_frame_unwind = 2297 { 2298 SIGTRAMP_FRAME, 2299 amd64_sigtramp_frame_unwind_stop_reason, 2300 amd64_sigtramp_frame_this_id, 2301 amd64_sigtramp_frame_prev_register, 2302 NULL, 2303 amd64_sigtramp_frame_sniffer 2304 }; 2305 2306 2307 static CORE_ADDR 2308 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache) 2309 { 2310 struct amd64_frame_cache *cache = 2311 amd64_frame_cache (this_frame, this_cache); 2312 2313 return cache->base; 2314 } 2315 2316 static const struct frame_base amd64_frame_base = 2317 { 2318 &amd64_frame_unwind, 2319 amd64_frame_base_address, 2320 amd64_frame_base_address, 2321 amd64_frame_base_address 2322 }; 2323 2324 /* Normal frames, but in a function epilogue. */ 2325 2326 /* The epilogue is defined here as the 'ret' instruction, which will 2327 follow any instruction such as 'leave' or 'pop %ebp' that destroys 2328 the function's stack frame. */ 2329 2330 static int 2331 amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2332 { 2333 gdb_byte insn; 2334 struct symtab *symtab; 2335 2336 symtab = find_pc_symtab (pc); 2337 if (symtab && symtab->epilogue_unwind_valid) 2338 return 0; 2339 2340 if (target_read_memory (pc, &insn, 1)) 2341 return 0; /* Can't read memory at pc. */ 2342 2343 if (insn != 0xc3) /* 'ret' instruction. */ 2344 return 0; 2345 2346 return 1; 2347 } 2348 2349 static int 2350 amd64_epilogue_frame_sniffer (const struct frame_unwind *self, 2351 struct frame_info *this_frame, 2352 void **this_prologue_cache) 2353 { 2354 if (frame_relative_level (this_frame) == 0) 2355 return amd64_in_function_epilogue_p (get_frame_arch (this_frame), 2356 get_frame_pc (this_frame)); 2357 else 2358 return 0; 2359 } 2360 2361 static struct amd64_frame_cache * 2362 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) 2363 { 2364 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2365 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2366 volatile struct gdb_exception ex; 2367 struct amd64_frame_cache *cache; 2368 gdb_byte buf[8]; 2369 2370 if (*this_cache) 2371 return *this_cache; 2372 2373 cache = amd64_alloc_frame_cache (); 2374 *this_cache = cache; 2375 2376 TRY_CATCH (ex, RETURN_MASK_ERROR) 2377 { 2378 /* Cache base will be %esp plus cache->sp_offset (-8). */ 2379 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2380 cache->base = extract_unsigned_integer (buf, 8, 2381 byte_order) + cache->sp_offset; 2382 2383 /* Cache pc will be the frame func. */ 2384 cache->pc = get_frame_pc (this_frame); 2385 2386 /* The saved %esp will be at cache->base plus 16. */ 2387 cache->saved_sp = cache->base + 16; 2388 2389 /* The saved %eip will be at cache->base plus 8. */ 2390 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8; 2391 2392 cache->base_p = 1; 2393 } 2394 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) 2395 throw_exception (ex); 2396 2397 return cache; 2398 } 2399 2400 static enum unwind_stop_reason 2401 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, 2402 void **this_cache) 2403 { 2404 struct amd64_frame_cache *cache 2405 = amd64_epilogue_frame_cache (this_frame, this_cache); 2406 2407 if (!cache->base_p) 2408 return UNWIND_UNAVAILABLE; 2409 2410 return UNWIND_NO_REASON; 2411 } 2412 2413 static void 2414 amd64_epilogue_frame_this_id (struct frame_info *this_frame, 2415 void **this_cache, 2416 struct frame_id *this_id) 2417 { 2418 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame, 2419 this_cache); 2420 2421 if (!cache->base_p) 2422 return; 2423 2424 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 2425 } 2426 2427 static const struct frame_unwind amd64_epilogue_frame_unwind = 2428 { 2429 NORMAL_FRAME, 2430 amd64_epilogue_frame_unwind_stop_reason, 2431 amd64_epilogue_frame_this_id, 2432 amd64_frame_prev_register, 2433 NULL, 2434 amd64_epilogue_frame_sniffer 2435 }; 2436 2437 static struct frame_id 2438 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2439 { 2440 CORE_ADDR fp; 2441 2442 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM); 2443 2444 return frame_id_build (fp + 16, get_frame_pc (this_frame)); 2445 } 2446 2447 /* 16 byte align the SP per frame requirements. */ 2448 2449 static CORE_ADDR 2450 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 2451 { 2452 return sp & -(CORE_ADDR)16; 2453 } 2454 2455 2456 /* Supply register REGNUM from the buffer specified by FPREGS and LEN 2457 in the floating-point register set REGSET to register cache 2458 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 2459 2460 static void 2461 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, 2462 int regnum, const void *fpregs, size_t len) 2463 { 2464 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 2465 2466 gdb_assert (len == tdep->sizeof_fpregset); 2467 amd64_supply_fxsave (regcache, regnum, fpregs); 2468 } 2469 2470 /* Collect register REGNUM from the register cache REGCACHE and store 2471 it in the buffer specified by FPREGS and LEN as described by the 2472 floating-point register set REGSET. If REGNUM is -1, do this for 2473 all registers in REGSET. */ 2474 2475 static void 2476 amd64_collect_fpregset (const struct regset *regset, 2477 const struct regcache *regcache, 2478 int regnum, void *fpregs, size_t len) 2479 { 2480 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 2481 2482 gdb_assert (len == tdep->sizeof_fpregset); 2483 amd64_collect_fxsave (regcache, regnum, fpregs); 2484 } 2485 2486 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */ 2487 2488 static void 2489 amd64_supply_xstateregset (const struct regset *regset, 2490 struct regcache *regcache, int regnum, 2491 const void *xstateregs, size_t len) 2492 { 2493 amd64_supply_xsave (regcache, regnum, xstateregs); 2494 } 2495 2496 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */ 2497 2498 static void 2499 amd64_collect_xstateregset (const struct regset *regset, 2500 const struct regcache *regcache, 2501 int regnum, void *xstateregs, size_t len) 2502 { 2503 amd64_collect_xsave (regcache, regnum, xstateregs, 1); 2504 } 2505 2506 /* Return the appropriate register set for the core section identified 2507 by SECT_NAME and SECT_SIZE. */ 2508 2509 static const struct regset * 2510 amd64_regset_from_core_section (struct gdbarch *gdbarch, 2511 const char *sect_name, size_t sect_size) 2512 { 2513 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2514 2515 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) 2516 { 2517 if (tdep->fpregset == NULL) 2518 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset, 2519 amd64_collect_fpregset); 2520 2521 return tdep->fpregset; 2522 } 2523 2524 if (strcmp (sect_name, ".reg-xstate") == 0) 2525 { 2526 if (tdep->xstateregset == NULL) 2527 tdep->xstateregset = regset_alloc (gdbarch, 2528 amd64_supply_xstateregset, 2529 amd64_collect_xstateregset); 2530 2531 return tdep->xstateregset; 2532 } 2533 2534 return i386_regset_from_core_section (gdbarch, sect_name, sect_size); 2535 } 2536 2537 2538 /* Figure out where the longjmp will land. Slurp the jmp_buf out of 2539 %rdi. We expect its value to be a pointer to the jmp_buf structure 2540 from which we extract the address that we will land at. This 2541 address is copied into PC. This routine returns non-zero on 2542 success. */ 2543 2544 static int 2545 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 2546 { 2547 gdb_byte buf[8]; 2548 CORE_ADDR jb_addr; 2549 struct gdbarch *gdbarch = get_frame_arch (frame); 2550 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; 2551 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr); 2552 2553 /* If JB_PC_OFFSET is -1, we have no way to find out where the 2554 longjmp will land. */ 2555 if (jb_pc_offset == -1) 2556 return 0; 2557 2558 get_frame_register (frame, AMD64_RDI_REGNUM, buf); 2559 jb_addr= extract_typed_address 2560 (buf, builtin_type (gdbarch)->builtin_data_ptr); 2561 if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) 2562 return 0; 2563 2564 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 2565 2566 return 1; 2567 } 2568 2569 static const int amd64_record_regmap[] = 2570 { 2571 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM, 2572 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 2573 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, 2574 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, 2575 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, 2576 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM 2577 }; 2578 2579 void 2580 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 2581 { 2582 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2583 const struct target_desc *tdesc = info.target_desc; 2584 2585 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its 2586 floating-point registers. */ 2587 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; 2588 2589 if (! tdesc_has_registers (tdesc)) 2590 tdesc = tdesc_amd64; 2591 tdep->tdesc = tdesc; 2592 2593 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS; 2594 tdep->register_names = amd64_register_names; 2595 2596 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL) 2597 { 2598 tdep->ymmh_register_names = amd64_ymmh_names; 2599 tdep->num_ymm_regs = 16; 2600 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM; 2601 } 2602 2603 tdep->num_byte_regs = 20; 2604 tdep->num_word_regs = 16; 2605 tdep->num_dword_regs = 16; 2606 /* Avoid wiring in the MMX registers for now. */ 2607 tdep->num_mmx_regs = 0; 2608 2609 set_gdbarch_pseudo_register_read_value (gdbarch, 2610 amd64_pseudo_register_read_value); 2611 set_gdbarch_pseudo_register_write (gdbarch, 2612 amd64_pseudo_register_write); 2613 2614 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name); 2615 2616 /* AMD64 has an FPU and 16 SSE registers. */ 2617 tdep->st0_regnum = AMD64_ST0_REGNUM; 2618 tdep->num_xmm_regs = 16; 2619 2620 /* This is what all the fuss is about. */ 2621 set_gdbarch_long_bit (gdbarch, 64); 2622 set_gdbarch_long_long_bit (gdbarch, 64); 2623 set_gdbarch_ptr_bit (gdbarch, 64); 2624 2625 /* In contrast to the i386, on AMD64 a `long double' actually takes 2626 up 128 bits, even though it's still based on the i387 extended 2627 floating-point format which has only 80 significant bits. */ 2628 set_gdbarch_long_double_bit (gdbarch, 128); 2629 2630 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); 2631 2632 /* Register numbers of various important registers. */ 2633 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ 2634 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ 2635 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ 2636 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ 2637 2638 /* The "default" register numbering scheme for AMD64 is referred to 2639 as the "DWARF Register Number Mapping" in the System V psABI. 2640 The preferred debugging format for all known AMD64 targets is 2641 actually DWARF2, and GCC doesn't seem to support DWARF (that is 2642 DWARF-1), but we provide the same mapping just in case. This 2643 mapping is also used for stabs, which GCC does support. */ 2644 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 2645 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 2646 2647 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to 2648 be in use on any of the supported AMD64 targets. */ 2649 2650 /* Call dummy code. */ 2651 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); 2652 set_gdbarch_frame_align (gdbarch, amd64_frame_align); 2653 set_gdbarch_frame_red_zone_size (gdbarch, 128); 2654 tdep->call_dummy_num_integer_regs = 2655 ARRAY_SIZE (amd64_dummy_call_integer_regs); 2656 tdep->call_dummy_integer_regs = amd64_dummy_call_integer_regs; 2657 tdep->classify = amd64_classify; 2658 2659 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p); 2660 set_gdbarch_register_to_value (gdbarch, i387_register_to_value); 2661 set_gdbarch_value_to_register (gdbarch, i387_value_to_register); 2662 2663 set_gdbarch_return_value (gdbarch, amd64_return_value); 2664 2665 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); 2666 2667 tdep->record_regmap = amd64_record_regmap; 2668 2669 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id); 2670 2671 /* Hook the function epilogue frame unwinder. This unwinder is 2672 appended to the list first, so that it supercedes the other 2673 unwinders in function epilogues. */ 2674 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind); 2675 2676 /* Hook the prologue-based frame unwinders. */ 2677 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind); 2678 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); 2679 frame_base_set_default (gdbarch, &amd64_frame_base); 2680 2681 /* If we have a register mapping, enable the generic core file support. */ 2682 if (tdep->gregset_reg_offset) 2683 set_gdbarch_regset_from_core_section (gdbarch, 2684 amd64_regset_from_core_section); 2685 2686 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); 2687 2688 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction); 2689 2690 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address); 2691 } 2692 2693 /* Provide a prototype to silence -Wmissing-prototypes. */ 2694 void _initialize_amd64_tdep (void); 2695 2696 void 2697 _initialize_amd64_tdep (void) 2698 { 2699 initialize_tdesc_amd64 (); 2700 initialize_tdesc_amd64_avx (); 2701 } 2702 2703 2704 /* The 64-bit FXSAVE format differs from the 32-bit format in the 2705 sense that the instruction pointer and data pointer are simply 2706 64-bit offsets into the code segment and the data segment instead 2707 of a selector offset pair. The functions below store the upper 32 2708 bits of these pointers (instead of just the 16-bits of the segment 2709 selector). */ 2710 2711 /* Fill register REGNUM in REGCACHE with the appropriate 2712 floating-point or SSE register value from *FXSAVE. If REGNUM is 2713 -1, do this for all registers. This function masks off any of the 2714 reserved bits in *FXSAVE. */ 2715 2716 void 2717 amd64_supply_fxsave (struct regcache *regcache, int regnum, 2718 const void *fxsave) 2719 { 2720 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2721 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2722 2723 i387_supply_fxsave (regcache, regnum, fxsave); 2724 2725 if (fxsave && gdbarch_ptr_bit (gdbarch) == 64) 2726 { 2727 const gdb_byte *regs = fxsave; 2728 2729 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 2730 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); 2731 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 2732 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); 2733 } 2734 } 2735 2736 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ 2737 2738 void 2739 amd64_supply_xsave (struct regcache *regcache, int regnum, 2740 const void *xsave) 2741 { 2742 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2743 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2744 2745 i387_supply_xsave (regcache, regnum, xsave); 2746 2747 if (xsave && gdbarch_ptr_bit (gdbarch) == 64) 2748 { 2749 const gdb_byte *regs = xsave; 2750 2751 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 2752 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), 2753 regs + 12); 2754 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 2755 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), 2756 regs + 20); 2757 } 2758 } 2759 2760 /* Fill register REGNUM (if it is a floating-point or SSE register) in 2761 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for 2762 all registers. This function doesn't touch any of the reserved 2763 bits in *FXSAVE. */ 2764 2765 void 2766 amd64_collect_fxsave (const struct regcache *regcache, int regnum, 2767 void *fxsave) 2768 { 2769 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2770 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2771 gdb_byte *regs = fxsave; 2772 2773 i387_collect_fxsave (regcache, regnum, fxsave); 2774 2775 if (gdbarch_ptr_bit (gdbarch) == 64) 2776 { 2777 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 2778 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); 2779 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 2780 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); 2781 } 2782 } 2783 2784 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */ 2785 2786 void 2787 amd64_collect_xsave (const struct regcache *regcache, int regnum, 2788 void *xsave, int gcore) 2789 { 2790 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2791 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2792 gdb_byte *regs = xsave; 2793 2794 i387_collect_xsave (regcache, regnum, xsave, gcore); 2795 2796 if (gdbarch_ptr_bit (gdbarch) == 64) 2797 { 2798 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 2799 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), 2800 regs + 12); 2801 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 2802 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), 2803 regs + 20); 2804 } 2805 } 2806