1 /* Native-dependent code for the i386. 2 3 Copyright (C) 2001, 2004-2005, 2007-2012 Free Software Foundation, 4 Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "i386-nat.h" 22 #include "defs.h" 23 #include "breakpoint.h" 24 #include "command.h" 25 #include "gdbcmd.h" 26 #include "target.h" 27 #include "gdb_assert.h" 28 29 /* Support for hardware watchpoints and breakpoints using the i386 30 debug registers. 31 32 This provides several functions for inserting and removing 33 hardware-assisted breakpoints and watchpoints, testing if one or 34 more of the watchpoints triggered and at what address, checking 35 whether a given region can be watched, etc. 36 37 The functions below implement debug registers sharing by reference 38 counts, and allow to watch regions up to 16 bytes long. */ 39 40 struct i386_dr_low_type i386_dr_low; 41 42 43 /* Support for 8-byte wide hw watchpoints. */ 44 #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8) 45 46 /* Debug registers' indices. */ 47 #define DR_NADDR 4 /* The number of debug address registers. */ 48 #define DR_STATUS 6 /* Index of debug status register (DR6). */ 49 #define DR_CONTROL 7 /* Index of debug control register (DR7). */ 50 51 /* DR7 Debug Control register fields. */ 52 53 /* How many bits to skip in DR7 to get to R/W and LEN fields. */ 54 #define DR_CONTROL_SHIFT 16 55 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ 56 #define DR_CONTROL_SIZE 4 57 58 /* Watchpoint/breakpoint read/write fields in DR7. */ 59 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ 60 #define DR_RW_WRITE (0x1) /* Break on data writes. */ 61 #define DR_RW_READ (0x3) /* Break on data reads or writes. */ 62 63 /* This is here for completeness. No platform supports this 64 functionality yet (as of March 2001). Note that the DE flag in the 65 CR4 register needs to be set to support this. */ 66 #ifndef DR_RW_IORW 67 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ 68 #endif 69 70 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift 71 is so we could OR this with the read/write field defined above. */ 72 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ 73 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ 74 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ 75 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ 76 77 /* Local and Global Enable flags in DR7. 78 79 When the Local Enable flag is set, the breakpoint/watchpoint is 80 enabled only for the current task; the processor automatically 81 clears this flag on every task switch. When the Global Enable flag 82 is set, the breakpoint/watchpoint is enabled for all tasks; the 83 processor never clears this flag. 84 85 Currently, all watchpoint are locally enabled. If you need to 86 enable them globally, read the comment which pertains to this in 87 i386_insert_aligned_watchpoint below. */ 88 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ 89 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ 90 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ 91 92 /* Local and global exact breakpoint enable flags (a.k.a. slowdown 93 flags). These are only required on i386, to allow detection of the 94 exact instruction which caused a watchpoint to break; i486 and 95 later processors do that automatically. We set these flags for 96 backwards compatibility. */ 97 #define DR_LOCAL_SLOWDOWN (0x100) 98 #define DR_GLOBAL_SLOWDOWN (0x200) 99 100 /* Fields reserved by Intel. This includes the GD (General Detect 101 Enable) flag, which causes a debug exception to be generated when a 102 MOV instruction accesses one of the debug registers. 103 104 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ 105 #define DR_CONTROL_RESERVED (0xFC00) 106 107 /* Auxiliary helper macros. */ 108 109 /* A value that masks all fields in DR7 that are reserved by Intel. */ 110 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) 111 112 /* The I'th debug register is vacant if its Local and Global Enable 113 bits are reset in the Debug Control register. */ 114 #define I386_DR_VACANT(state, i) \ 115 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) 116 117 /* Locally enable the break/watchpoint in the I'th debug register. */ 118 #define I386_DR_LOCAL_ENABLE(state, i) \ 119 do { \ 120 (state)->dr_control_mirror |= \ 121 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ 122 } while (0) 123 124 /* Globally enable the break/watchpoint in the I'th debug register. */ 125 #define I386_DR_GLOBAL_ENABLE(state, i) \ 126 do { \ 127 (state)->dr_control_mirror |= \ 128 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ 129 } while (0) 130 131 /* Disable the break/watchpoint in the I'th debug register. */ 132 #define I386_DR_DISABLE(state, i) \ 133 do { \ 134 (state)->dr_control_mirror &= \ 135 ~(3 << (DR_ENABLE_SIZE * (i))); \ 136 } while (0) 137 138 /* Set in DR7 the RW and LEN fields for the I'th debug register. */ 139 #define I386_DR_SET_RW_LEN(state, i, rwlen) \ 140 do { \ 141 (state)->dr_control_mirror &= \ 142 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ 143 (state)->dr_control_mirror |= \ 144 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ 145 } while (0) 146 147 /* Get from DR7 the RW and LEN fields for the I'th debug register. */ 148 #define I386_DR_GET_RW_LEN(dr7, i) \ 149 (((dr7) \ 150 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) 151 152 /* Mask that this I'th watchpoint has triggered. */ 153 #define I386_DR_WATCH_MASK(i) (1 << (i)) 154 155 /* Did the watchpoint whose address is in the I'th register break? */ 156 #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) 157 158 /* A macro to loop over all debug registers. */ 159 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) 160 161 162 /* Global state needed to track h/w watchpoints. */ 163 164 struct i386_debug_reg_state 165 { 166 /* Mirror the inferior's DRi registers. We keep the status and 167 control registers separated because they don't hold addresses. 168 Note that since we can change these mirrors while threads are 169 running, we never trust them to explain a cause of a trap. 170 For that, we need to peek directly in the inferior registers. */ 171 CORE_ADDR dr_mirror[DR_NADDR]; 172 unsigned dr_status_mirror, dr_control_mirror; 173 174 /* Reference counts for each debug register. */ 175 int dr_ref_count[DR_NADDR]; 176 }; 177 178 /* Clear the reference counts and forget everything we knew about the 179 debug registers. */ 180 181 static void 182 i386_init_dregs (struct i386_debug_reg_state *state) 183 { 184 int i; 185 186 ALL_DEBUG_REGISTERS (i) 187 { 188 state->dr_mirror[i] = 0; 189 state->dr_ref_count[i] = 0; 190 } 191 state->dr_control_mirror = 0; 192 state->dr_status_mirror = 0; 193 } 194 195 static struct i386_debug_reg_state dr_mirror; 196 197 /* Whether or not to print the mirrored debug registers. */ 198 static int maint_show_dr; 199 200 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ 201 typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; 202 203 /* Internal functions. */ 204 205 /* Return the value of a 4-bit field for DR7 suitable for watching a 206 region of LEN bytes for accesses of type TYPE. LEN is assumed to 207 have the value of 1, 2, or 4. */ 208 static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); 209 210 /* Insert a watchpoint at address ADDR, which is assumed to be aligned 211 according to the length of the region to watch. LEN_RW_BITS is the 212 value of the bit-field from DR7 which describes the length and 213 access type of the region to be watched by this watchpoint. Return 214 0 on success, -1 on failure. */ 215 static int i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, 216 CORE_ADDR addr, 217 unsigned len_rw_bits); 218 219 /* Remove a watchpoint at address ADDR, which is assumed to be aligned 220 according to the length of the region to watch. LEN_RW_BITS is the 221 value of the bits from DR7 which describes the length and access 222 type of the region watched by this watchpoint. Return 0 on 223 success, -1 on failure. */ 224 static int i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, 225 CORE_ADDR addr, 226 unsigned len_rw_bits); 227 228 /* Insert or remove a (possibly non-aligned) watchpoint, or count the 229 number of debug registers required to watch a region at address 230 ADDR whose length is LEN for accesses of type TYPE. Return 0 on 231 successful insertion or removal, a positive number when queried 232 about the number of registers, or -1 on failure. If WHAT is not a 233 valid value, bombs through internal_error. */ 234 static int i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, 235 i386_wp_op_t what, 236 CORE_ADDR addr, int len, 237 enum target_hw_bp_type type); 238 239 /* Implementation. */ 240 241 /* Clear the reference counts and forget everything we knew about the 242 debug registers. */ 243 244 void 245 i386_cleanup_dregs (void) 246 { 247 i386_init_dregs (&dr_mirror); 248 } 249 250 /* Print the values of the mirrored debug registers. This is called 251 when maint_show_dr is non-zero. To set that up, type "maint 252 show-debug-regs" at GDB's prompt. */ 253 254 static void 255 i386_show_dr (struct i386_debug_reg_state *state, 256 const char *func, CORE_ADDR addr, 257 int len, enum target_hw_bp_type type) 258 { 259 int addr_size = gdbarch_addr_bit (target_gdbarch) / 8; 260 int i; 261 262 puts_unfiltered (func); 263 if (addr || len) 264 printf_unfiltered (" (addr=%lx, len=%d, type=%s)", 265 /* This code is for ia32, so casting CORE_ADDR 266 to unsigned long should be okay. */ 267 (unsigned long)addr, len, 268 type == hw_write ? "data-write" 269 : (type == hw_read ? "data-read" 270 : (type == hw_access ? "data-read/write" 271 : (type == hw_execute ? "instruction-execute" 272 /* FIXME: if/when I/O read/write 273 watchpoints are supported, add them 274 here. */ 275 : "??unknown??")))); 276 puts_unfiltered (":\n"); 277 printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", 278 phex (state->dr_control_mirror, 8), 279 phex (state->dr_status_mirror, 8)); 280 ALL_DEBUG_REGISTERS(i) 281 { 282 printf_unfiltered ("\ 283 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", 284 i, phex (state->dr_mirror[i], addr_size), 285 state->dr_ref_count[i], 286 i + 1, phex (state->dr_mirror[i + 1], addr_size), 287 state->dr_ref_count[i+1]); 288 i++; 289 } 290 } 291 292 /* Return the value of a 4-bit field for DR7 suitable for watching a 293 region of LEN bytes for accesses of type TYPE. LEN is assumed to 294 have the value of 1, 2, or 4. */ 295 296 static unsigned 297 i386_length_and_rw_bits (int len, enum target_hw_bp_type type) 298 { 299 unsigned rw; 300 301 switch (type) 302 { 303 case hw_execute: 304 rw = DR_RW_EXECUTE; 305 break; 306 case hw_write: 307 rw = DR_RW_WRITE; 308 break; 309 case hw_read: 310 internal_error (__FILE__, __LINE__, 311 _("The i386 doesn't support " 312 "data-read watchpoints.\n")); 313 case hw_access: 314 rw = DR_RW_READ; 315 break; 316 #if 0 317 /* Not yet supported. */ 318 case hw_io_access: 319 rw = DR_RW_IORW; 320 break; 321 #endif 322 default: 323 internal_error (__FILE__, __LINE__, _("\ 324 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), 325 (int) type); 326 } 327 328 switch (len) 329 { 330 case 1: 331 return (DR_LEN_1 | rw); 332 case 2: 333 return (DR_LEN_2 | rw); 334 case 4: 335 return (DR_LEN_4 | rw); 336 case 8: 337 if (TARGET_HAS_DR_LEN_8) 338 return (DR_LEN_8 | rw); 339 /* ELSE FALL THROUGH */ 340 default: 341 internal_error (__FILE__, __LINE__, _("\ 342 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); 343 } 344 } 345 346 /* Insert a watchpoint at address ADDR, which is assumed to be aligned 347 according to the length of the region to watch. LEN_RW_BITS is the 348 value of the bits from DR7 which describes the length and access 349 type of the region to be watched by this watchpoint. Return 0 on 350 success, -1 on failure. */ 351 352 static int 353 i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, 354 CORE_ADDR addr, unsigned len_rw_bits) 355 { 356 int i; 357 358 if (!i386_dr_low.set_addr || !i386_dr_low.set_control) 359 return -1; 360 361 /* First, look for an occupied debug register with the same address 362 and the same RW and LEN definitions. If we find one, we can 363 reuse it for this watchpoint as well (and save a register). */ 364 ALL_DEBUG_REGISTERS(i) 365 { 366 if (!I386_DR_VACANT (state, i) 367 && state->dr_mirror[i] == addr 368 && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) 369 { 370 state->dr_ref_count[i]++; 371 return 0; 372 } 373 } 374 375 /* Next, look for a vacant debug register. */ 376 ALL_DEBUG_REGISTERS(i) 377 { 378 if (I386_DR_VACANT (state, i)) 379 break; 380 } 381 382 /* No more debug registers! */ 383 if (i >= DR_NADDR) 384 return -1; 385 386 /* Now set up the register I to watch our region. */ 387 388 /* Record the info in our local mirrored array. */ 389 state->dr_mirror[i] = addr; 390 state->dr_ref_count[i] = 1; 391 I386_DR_SET_RW_LEN (state, i, len_rw_bits); 392 /* Note: we only enable the watchpoint locally, i.e. in the current 393 task. Currently, no i386 target allows or supports global 394 watchpoints; however, if any target would want that in the 395 future, GDB should probably provide a command to control whether 396 to enable watchpoints globally or locally, and the code below 397 should use global or local enable and slow-down flags as 398 appropriate. */ 399 I386_DR_LOCAL_ENABLE (state, i); 400 state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; 401 state->dr_control_mirror &= I386_DR_CONTROL_MASK; 402 403 return 0; 404 } 405 406 /* Remove a watchpoint at address ADDR, which is assumed to be aligned 407 according to the length of the region to watch. LEN_RW_BITS is the 408 value of the bits from DR7 which describes the length and access 409 type of the region watched by this watchpoint. Return 0 on 410 success, -1 on failure. */ 411 412 static int 413 i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, 414 CORE_ADDR addr, unsigned len_rw_bits) 415 { 416 int i, retval = -1; 417 418 ALL_DEBUG_REGISTERS(i) 419 { 420 if (!I386_DR_VACANT (state, i) 421 && state->dr_mirror[i] == addr 422 && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) 423 { 424 if (--state->dr_ref_count[i] == 0) /* no longer in use? */ 425 { 426 /* Reset our mirror. */ 427 state->dr_mirror[i] = 0; 428 I386_DR_DISABLE (state, i); 429 } 430 retval = 0; 431 } 432 } 433 434 return retval; 435 } 436 437 /* Insert or remove a (possibly non-aligned) watchpoint, or count the 438 number of debug registers required to watch a region at address 439 ADDR whose length is LEN for accesses of type TYPE. Return 0 on 440 successful insertion or removal, a positive number when queried 441 about the number of registers, or -1 on failure. If WHAT is not a 442 valid value, bombs through internal_error. */ 443 444 static int 445 i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, 446 i386_wp_op_t what, CORE_ADDR addr, int len, 447 enum target_hw_bp_type type) 448 { 449 int retval = 0; 450 int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; 451 452 static int size_try_array[8][8] = 453 { 454 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ 455 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ 456 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ 457 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ 458 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ 459 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ 460 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ 461 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ 462 }; 463 464 while (len > 0) 465 { 466 int align = addr % max_wp_len; 467 /* Four (eight on AMD64) is the maximum length a debug register 468 can watch. */ 469 int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); 470 int size = size_try_array[try][align]; 471 472 if (what == WP_COUNT) 473 { 474 /* size_try_array[] is defined such that each iteration 475 through the loop is guaranteed to produce an address and a 476 size that can be watched with a single debug register. 477 Thus, for counting the registers required to watch a 478 region, we simply need to increment the count on each 479 iteration. */ 480 retval++; 481 } 482 else 483 { 484 unsigned len_rw = i386_length_and_rw_bits (size, type); 485 486 if (what == WP_INSERT) 487 retval = i386_insert_aligned_watchpoint (state, addr, len_rw); 488 else if (what == WP_REMOVE) 489 retval = i386_remove_aligned_watchpoint (state, addr, len_rw); 490 else 491 internal_error (__FILE__, __LINE__, _("\ 492 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), 493 (int)what); 494 if (retval) 495 break; 496 } 497 498 addr += size; 499 len -= size; 500 } 501 502 return retval; 503 } 504 505 /* Update the inferior's debug registers with the new debug registers 506 state, in NEW_STATE, and then update our local mirror to match. */ 507 508 static void 509 i386_update_inferior_debug_regs (struct i386_debug_reg_state *new_state) 510 { 511 int i; 512 513 ALL_DEBUG_REGISTERS (i) 514 { 515 if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (&dr_mirror, i)) 516 { 517 if (!I386_DR_VACANT (new_state, i)) 518 { 519 i386_dr_low.set_addr (i, new_state->dr_mirror[i]); 520 521 /* Only a sanity check for leftover bits (set possibly only 522 by inferior). */ 523 if (i386_dr_low.unset_status) 524 i386_dr_low.unset_status (I386_DR_WATCH_MASK (i)); 525 } 526 else 527 { 528 if (i386_dr_low.reset_addr) 529 i386_dr_low.reset_addr (i); 530 } 531 } 532 else 533 gdb_assert (new_state->dr_mirror[i] == dr_mirror.dr_mirror[i]); 534 } 535 536 if (new_state->dr_control_mirror != dr_mirror.dr_control_mirror) 537 i386_dr_low.set_control (new_state->dr_control_mirror); 538 539 dr_mirror = *new_state; 540 } 541 542 /* Insert a watchpoint to watch a memory region which starts at 543 address ADDR and whose length is LEN bytes. Watch memory accesses 544 of the type TYPE. Return 0 on success, -1 on failure. */ 545 546 static int 547 i386_insert_watchpoint (CORE_ADDR addr, int len, int type, 548 struct expression *cond) 549 { 550 int retval; 551 /* Work on a local copy of the debug registers, and on success, 552 commit the change back to the inferior. */ 553 struct i386_debug_reg_state local_state = dr_mirror; 554 555 if (type == hw_read) 556 return 1; /* unsupported */ 557 558 if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) 559 || addr % len != 0) 560 retval = i386_handle_nonaligned_watchpoint (&local_state, 561 WP_INSERT, addr, len, type); 562 else 563 { 564 unsigned len_rw = i386_length_and_rw_bits (len, type); 565 566 retval = i386_insert_aligned_watchpoint (&local_state, 567 addr, len_rw); 568 } 569 570 if (retval == 0) 571 i386_update_inferior_debug_regs (&local_state); 572 573 if (maint_show_dr) 574 i386_show_dr (&dr_mirror, "insert_watchpoint", addr, len, type); 575 576 return retval; 577 } 578 579 /* Remove a watchpoint that watched the memory region which starts at 580 address ADDR, whose length is LEN bytes, and for accesses of the 581 type TYPE. Return 0 on success, -1 on failure. */ 582 static int 583 i386_remove_watchpoint (CORE_ADDR addr, int len, int type, 584 struct expression *cond) 585 { 586 int retval; 587 /* Work on a local copy of the debug registers, and on success, 588 commit the change back to the inferior. */ 589 struct i386_debug_reg_state local_state = dr_mirror; 590 591 if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) 592 || addr % len != 0) 593 retval = i386_handle_nonaligned_watchpoint (&local_state, 594 WP_REMOVE, addr, len, type); 595 else 596 { 597 unsigned len_rw = i386_length_and_rw_bits (len, type); 598 599 retval = i386_remove_aligned_watchpoint (&local_state, 600 addr, len_rw); 601 } 602 603 if (retval == 0) 604 i386_update_inferior_debug_regs (&local_state); 605 606 if (maint_show_dr) 607 i386_show_dr (&dr_mirror, "remove_watchpoint", addr, len, type); 608 609 return retval; 610 } 611 612 /* Return non-zero if we can watch a memory region that starts at 613 address ADDR and whose length is LEN bytes. */ 614 615 static int 616 i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) 617 { 618 int nregs; 619 620 /* Compute how many aligned watchpoints we would need to cover this 621 region. */ 622 nregs = i386_handle_nonaligned_watchpoint (&dr_mirror, 623 WP_COUNT, addr, len, hw_write); 624 return nregs <= DR_NADDR ? 1 : 0; 625 } 626 627 /* If the inferior has some watchpoint that triggered, set the 628 address associated with that watchpoint and return non-zero. 629 Otherwise, return zero. */ 630 631 static int 632 i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) 633 { 634 CORE_ADDR addr = 0; 635 int i; 636 int rc = 0; 637 unsigned status; 638 unsigned control; 639 struct i386_debug_reg_state *state = &dr_mirror; 640 641 dr_mirror.dr_status_mirror = i386_dr_low.get_status (); 642 status = dr_mirror.dr_status_mirror; 643 control = dr_mirror.dr_control_mirror; 644 645 ALL_DEBUG_REGISTERS(i) 646 { 647 if (I386_DR_WATCH_HIT (status, i) 648 /* This second condition makes sure DRi is set up for a data 649 watchpoint, not a hardware breakpoint. The reason is 650 that GDB doesn't call the target_stopped_data_address 651 method except for data watchpoints. In other words, I'm 652 being paranoiac. */ 653 && I386_DR_GET_RW_LEN (control, i) != 0 654 /* This third condition makes sure DRi is not vacant, this 655 avoids false positives in windows-nat.c. */ 656 && !I386_DR_VACANT (state, i)) 657 { 658 addr = state->dr_mirror[i]; 659 rc = 1; 660 if (maint_show_dr) 661 i386_show_dr (&dr_mirror, "watchpoint_hit", addr, -1, hw_write); 662 } 663 } 664 if (maint_show_dr && addr == 0) 665 i386_show_dr (&dr_mirror, "stopped_data_addr", 0, 0, hw_write); 666 667 if (rc) 668 *addr_p = addr; 669 return rc; 670 } 671 672 static int 673 i386_stopped_by_watchpoint (void) 674 { 675 CORE_ADDR addr = 0; 676 return i386_stopped_data_address (¤t_target, &addr); 677 } 678 679 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. 680 Return 0 on success, EBUSY on failure. */ 681 static int 682 i386_insert_hw_breakpoint (struct gdbarch *gdbarch, 683 struct bp_target_info *bp_tgt) 684 { 685 unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); 686 CORE_ADDR addr = bp_tgt->placed_address; 687 /* Work on a local copy of the debug registers, and on success, 688 commit the change back to the inferior. */ 689 struct i386_debug_reg_state local_state = dr_mirror; 690 int retval = i386_insert_aligned_watchpoint (&local_state, 691 addr, len_rw) ? EBUSY : 0; 692 693 if (retval == 0) 694 i386_update_inferior_debug_regs (&local_state); 695 696 if (maint_show_dr) 697 i386_show_dr (&dr_mirror, "insert_hwbp", addr, 1, hw_execute); 698 699 return retval; 700 } 701 702 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. 703 Return 0 on success, -1 on failure. */ 704 705 static int 706 i386_remove_hw_breakpoint (struct gdbarch *gdbarch, 707 struct bp_target_info *bp_tgt) 708 { 709 unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); 710 CORE_ADDR addr = bp_tgt->placed_address; 711 /* Work on a local copy of the debug registers, and on success, 712 commit the change back to the inferior. */ 713 struct i386_debug_reg_state local_state = dr_mirror; 714 int retval = i386_remove_aligned_watchpoint (&local_state, 715 addr, len_rw); 716 717 if (retval == 0) 718 i386_update_inferior_debug_regs (&local_state); 719 720 if (maint_show_dr) 721 i386_show_dr (&dr_mirror, "remove_hwbp", addr, 1, hw_execute); 722 723 return retval; 724 } 725 726 /* Returns the number of hardware watchpoints of type TYPE that we can 727 set. Value is positive if we can set CNT watchpoints, zero if 728 setting watchpoints of type TYPE is not supported, and negative if 729 CNT is more than the maximum number of watchpoints of type TYPE 730 that we can support. TYPE is one of bp_hardware_watchpoint, 731 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. 732 CNT is the number of such watchpoints used so far (including this 733 one). OTHERTYPE is non-zero if other types of watchpoints are 734 currently enabled. 735 736 We always return 1 here because we don't have enough information 737 about possible overlap of addresses that they want to watch. As an 738 extreme example, consider the case where all the watchpoints watch 739 the same address and the same region length: then we can handle a 740 virtually unlimited number of watchpoints, due to debug register 741 sharing implemented via reference counts in i386-nat.c. */ 742 743 static int 744 i386_can_use_hw_breakpoint (int type, int cnt, int othertype) 745 { 746 return 1; 747 } 748 749 static void 750 add_show_debug_regs_command (void) 751 { 752 /* A maintenance command to enable printing the internal DRi mirror 753 variables. */ 754 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, 755 &maint_show_dr, _("\ 756 Set whether to show variables that mirror the x86 debug registers."), _("\ 757 Show whether to show variables that mirror the x86 debug registers."), _("\ 758 Use \"on\" to enable, \"off\" to disable.\n\ 759 If enabled, the debug registers values are shown when GDB inserts\n\ 760 or removes a hardware breakpoint or watchpoint, and when the inferior\n\ 761 triggers a breakpoint or watchpoint."), 762 NULL, 763 NULL, 764 &maintenance_set_cmdlist, 765 &maintenance_show_cmdlist); 766 } 767 768 /* There are only two global functions left. */ 769 770 void 771 i386_use_watchpoints (struct target_ops *t) 772 { 773 /* After a watchpoint trap, the PC points to the instruction after the 774 one that caused the trap. Therefore we don't need to step over it. 775 But we do need to reset the status register to avoid another trap. */ 776 t->to_have_continuable_watchpoint = 1; 777 778 t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; 779 t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; 780 t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; 781 t->to_stopped_data_address = i386_stopped_data_address; 782 t->to_insert_watchpoint = i386_insert_watchpoint; 783 t->to_remove_watchpoint = i386_remove_watchpoint; 784 t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; 785 t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; 786 } 787 788 void 789 i386_set_debug_register_length (int len) 790 { 791 /* This function should be called only once for each native target. */ 792 gdb_assert (i386_dr_low.debug_register_length == 0); 793 gdb_assert (len == 4 || len == 8); 794 i386_dr_low.debug_register_length = len; 795 add_show_debug_regs_command (); 796 } 797