1 /* Native-dependent code for the i386. 2 3 Copyright (C) 2001, 2004, 2005, 2007, 2008, 2009, 2010 4 Free Software Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "i386-nat.h" 22 #include "defs.h" 23 #include "breakpoint.h" 24 #include "command.h" 25 #include "gdbcmd.h" 26 #include "target.h" 27 #include "gdb_assert.h" 28 29 /* Support for hardware watchpoints and breakpoints using the i386 30 debug registers. 31 32 This provides several functions for inserting and removing 33 hardware-assisted breakpoints and watchpoints, testing if one or 34 more of the watchpoints triggered and at what address, checking 35 whether a given region can be watched, etc. 36 37 The functions below implement debug registers sharing by reference 38 counts, and allow to watch regions up to 16 bytes long. */ 39 40 struct i386_dr_low_type i386_dr_low; 41 42 43 /* Support for 8-byte wide hw watchpoints. */ 44 #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8) 45 46 /* Debug registers' indices. */ 47 #define DR_NADDR 4 /* The number of debug address registers. */ 48 #define DR_STATUS 6 /* Index of debug status register (DR6). */ 49 #define DR_CONTROL 7 /* Index of debug control register (DR7). */ 50 51 /* DR7 Debug Control register fields. */ 52 53 /* How many bits to skip in DR7 to get to R/W and LEN fields. */ 54 #define DR_CONTROL_SHIFT 16 55 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ 56 #define DR_CONTROL_SIZE 4 57 58 /* Watchpoint/breakpoint read/write fields in DR7. */ 59 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ 60 #define DR_RW_WRITE (0x1) /* Break on data writes. */ 61 #define DR_RW_READ (0x3) /* Break on data reads or writes. */ 62 63 /* This is here for completeness. No platform supports this 64 functionality yet (as of March 2001). Note that the DE flag in the 65 CR4 register needs to be set to support this. */ 66 #ifndef DR_RW_IORW 67 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ 68 #endif 69 70 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift 71 is so we could OR this with the read/write field defined above. */ 72 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ 73 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ 74 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ 75 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ 76 77 /* Local and Global Enable flags in DR7. 78 79 When the Local Enable flag is set, the breakpoint/watchpoint is 80 enabled only for the current task; the processor automatically 81 clears this flag on every task switch. When the Global Enable flag 82 is set, the breakpoint/watchpoint is enabled for all tasks; the 83 processor never clears this flag. 84 85 Currently, all watchpoint are locally enabled. If you need to 86 enable them globally, read the comment which pertains to this in 87 i386_insert_aligned_watchpoint below. */ 88 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ 89 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ 90 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ 91 92 /* Local and global exact breakpoint enable flags (a.k.a. slowdown 93 flags). These are only required on i386, to allow detection of the 94 exact instruction which caused a watchpoint to break; i486 and 95 later processors do that automatically. We set these flags for 96 backwards compatibility. */ 97 #define DR_LOCAL_SLOWDOWN (0x100) 98 #define DR_GLOBAL_SLOWDOWN (0x200) 99 100 /* Fields reserved by Intel. This includes the GD (General Detect 101 Enable) flag, which causes a debug exception to be generated when a 102 MOV instruction accesses one of the debug registers. 103 104 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ 105 #define DR_CONTROL_RESERVED (0xFC00) 106 107 /* Auxiliary helper macros. */ 108 109 /* A value that masks all fields in DR7 that are reserved by Intel. */ 110 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) 111 112 /* The I'th debug register is vacant if its Local and Global Enable 113 bits are reset in the Debug Control register. */ 114 #define I386_DR_VACANT(i) \ 115 ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) 116 117 /* Locally enable the break/watchpoint in the I'th debug register. */ 118 #define I386_DR_LOCAL_ENABLE(i) \ 119 dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))) 120 121 /* Globally enable the break/watchpoint in the I'th debug register. */ 122 #define I386_DR_GLOBAL_ENABLE(i) \ 123 dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))) 124 125 /* Disable the break/watchpoint in the I'th debug register. */ 126 #define I386_DR_DISABLE(i) \ 127 dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i))) 128 129 /* Set in DR7 the RW and LEN fields for the I'th debug register. */ 130 #define I386_DR_SET_RW_LEN(i,rwlen) \ 131 do { \ 132 dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \ 133 dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \ 134 } while (0) 135 136 /* Get from DR7 the RW and LEN fields for the I'th debug register. */ 137 #define I386_DR_GET_RW_LEN(i) \ 138 ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) 139 140 /* Mask that this I'th watchpoint has triggered. */ 141 #define I386_DR_WATCH_MASK(i) (1 << (i)) 142 143 /* Did the watchpoint whose address is in the I'th register break? */ 144 #define I386_DR_WATCH_HIT(i) (dr_status_mirror & I386_DR_WATCH_MASK (i)) 145 146 /* A macro to loop over all debug registers. */ 147 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) 148 149 /* Mirror the inferior's DRi registers. We keep the status and 150 control registers separated because they don't hold addresses. */ 151 static CORE_ADDR dr_mirror[DR_NADDR]; 152 static unsigned long dr_status_mirror, dr_control_mirror; 153 154 /* Reference counts for each debug register. */ 155 static int dr_ref_count[DR_NADDR]; 156 157 /* Whether or not to print the mirrored debug registers. */ 158 static int maint_show_dr; 159 160 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ 161 typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; 162 163 /* Internal functions. */ 164 165 /* Return the value of a 4-bit field for DR7 suitable for watching a 166 region of LEN bytes for accesses of type TYPE. LEN is assumed to 167 have the value of 1, 2, or 4. */ 168 static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); 169 170 /* Insert a watchpoint at address ADDR, which is assumed to be aligned 171 according to the length of the region to watch. LEN_RW_BITS is the 172 value of the bit-field from DR7 which describes the length and 173 access type of the region to be watched by this watchpoint. Return 174 0 on success, -1 on failure. */ 175 static int i386_insert_aligned_watchpoint (CORE_ADDR addr, 176 unsigned len_rw_bits); 177 178 /* Remove a watchpoint at address ADDR, which is assumed to be aligned 179 according to the length of the region to watch. LEN_RW_BITS is the 180 value of the bits from DR7 which describes the length and access 181 type of the region watched by this watchpoint. Return 0 on 182 success, -1 on failure. */ 183 static int i386_remove_aligned_watchpoint (CORE_ADDR addr, 184 unsigned len_rw_bits); 185 186 /* Insert or remove a (possibly non-aligned) watchpoint, or count the 187 number of debug registers required to watch a region at address 188 ADDR whose length is LEN for accesses of type TYPE. Return 0 on 189 successful insertion or removal, a positive number when queried 190 about the number of registers, or -1 on failure. If WHAT is not a 191 valid value, bombs through internal_error. */ 192 static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what, 193 CORE_ADDR addr, int len, 194 enum target_hw_bp_type type); 195 196 /* Implementation. */ 197 198 /* Clear the reference counts and forget everything we knew about the 199 debug registers. */ 200 201 void 202 i386_cleanup_dregs (void) 203 { 204 int i; 205 206 ALL_DEBUG_REGISTERS(i) 207 { 208 dr_mirror[i] = 0; 209 dr_ref_count[i] = 0; 210 } 211 dr_control_mirror = 0; 212 dr_status_mirror = 0; 213 } 214 215 /* Print the values of the mirrored debug registers. This is called 216 when maint_show_dr is non-zero. To set that up, type "maint 217 show-debug-regs" at GDB's prompt. */ 218 219 static void 220 i386_show_dr (const char *func, CORE_ADDR addr, 221 int len, enum target_hw_bp_type type) 222 { 223 int addr_size = gdbarch_addr_bit (target_gdbarch) / 8; 224 int i; 225 226 puts_unfiltered (func); 227 if (addr || len) 228 printf_unfiltered (" (addr=%lx, len=%d, type=%s)", 229 /* This code is for ia32, so casting CORE_ADDR 230 to unsigned long should be okay. */ 231 (unsigned long)addr, len, 232 type == hw_write ? "data-write" 233 : (type == hw_read ? "data-read" 234 : (type == hw_access ? "data-read/write" 235 : (type == hw_execute ? "instruction-execute" 236 /* FIXME: if/when I/O read/write 237 watchpoints are supported, add them 238 here. */ 239 : "??unknown??")))); 240 puts_unfiltered (":\n"); 241 printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", 242 phex (dr_control_mirror, 8), phex (dr_status_mirror, 8)); 243 ALL_DEBUG_REGISTERS(i) 244 { 245 printf_unfiltered ("\ 246 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", 247 i, phex (dr_mirror[i], addr_size), dr_ref_count[i], 248 i+1, phex (dr_mirror[i+1], addr_size), dr_ref_count[i+1]); 249 i++; 250 } 251 } 252 253 /* Return the value of a 4-bit field for DR7 suitable for watching a 254 region of LEN bytes for accesses of type TYPE. LEN is assumed to 255 have the value of 1, 2, or 4. */ 256 257 static unsigned 258 i386_length_and_rw_bits (int len, enum target_hw_bp_type type) 259 { 260 unsigned rw; 261 262 switch (type) 263 { 264 case hw_execute: 265 rw = DR_RW_EXECUTE; 266 break; 267 case hw_write: 268 rw = DR_RW_WRITE; 269 break; 270 case hw_read: 271 internal_error (__FILE__, __LINE__, 272 _("The i386 doesn't support data-read watchpoints.\n")); 273 case hw_access: 274 rw = DR_RW_READ; 275 break; 276 #if 0 277 /* Not yet supported. */ 278 case hw_io_access: 279 rw = DR_RW_IORW; 280 break; 281 #endif 282 default: 283 internal_error (__FILE__, __LINE__, _("\ 284 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), 285 (int) type); 286 } 287 288 switch (len) 289 { 290 case 1: 291 return (DR_LEN_1 | rw); 292 case 2: 293 return (DR_LEN_2 | rw); 294 case 4: 295 return (DR_LEN_4 | rw); 296 case 8: 297 if (TARGET_HAS_DR_LEN_8) 298 return (DR_LEN_8 | rw); 299 default: 300 internal_error (__FILE__, __LINE__, _("\ 301 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); 302 } 303 } 304 305 /* Insert a watchpoint at address ADDR, which is assumed to be aligned 306 according to the length of the region to watch. LEN_RW_BITS is the 307 value of the bits from DR7 which describes the length and access 308 type of the region to be watched by this watchpoint. Return 0 on 309 success, -1 on failure. */ 310 311 static int 312 i386_insert_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits) 313 { 314 int i; 315 316 if (!i386_dr_low.set_addr || !i386_dr_low.set_control) 317 return -1; 318 319 /* First, look for an occupied debug register with the same address 320 and the same RW and LEN definitions. If we find one, we can 321 reuse it for this watchpoint as well (and save a register). */ 322 ALL_DEBUG_REGISTERS(i) 323 { 324 if (!I386_DR_VACANT (i) 325 && dr_mirror[i] == addr 326 && I386_DR_GET_RW_LEN (i) == len_rw_bits) 327 { 328 dr_ref_count[i]++; 329 return 0; 330 } 331 } 332 333 /* Next, look for a vacant debug register. */ 334 ALL_DEBUG_REGISTERS(i) 335 { 336 if (I386_DR_VACANT (i)) 337 break; 338 } 339 340 /* No more debug registers! */ 341 if (i >= DR_NADDR) 342 return -1; 343 344 /* Now set up the register I to watch our region. */ 345 346 /* Record the info in our local mirrored array. */ 347 dr_mirror[i] = addr; 348 dr_ref_count[i] = 1; 349 I386_DR_SET_RW_LEN (i, len_rw_bits); 350 /* Note: we only enable the watchpoint locally, i.e. in the current 351 task. Currently, no i386 target allows or supports global 352 watchpoints; however, if any target would want that in the 353 future, GDB should probably provide a command to control whether 354 to enable watchpoints globally or locally, and the code below 355 should use global or local enable and slow-down flags as 356 appropriate. */ 357 I386_DR_LOCAL_ENABLE (i); 358 dr_control_mirror |= DR_LOCAL_SLOWDOWN; 359 dr_control_mirror &= I386_DR_CONTROL_MASK; 360 361 /* Finally, actually pass the info to the inferior. */ 362 i386_dr_low.set_addr (i, addr); 363 i386_dr_low.set_control (dr_control_mirror); 364 365 /* Only a sanity check for leftover bits (set possibly only by inferior). */ 366 if (i386_dr_low.unset_status) 367 i386_dr_low.unset_status (I386_DR_WATCH_MASK (i)); 368 369 return 0; 370 } 371 372 /* Remove a watchpoint at address ADDR, which is assumed to be aligned 373 according to the length of the region to watch. LEN_RW_BITS is the 374 value of the bits from DR7 which describes the length and access 375 type of the region watched by this watchpoint. Return 0 on 376 success, -1 on failure. */ 377 378 static int 379 i386_remove_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits) 380 { 381 int i, retval = -1; 382 383 ALL_DEBUG_REGISTERS(i) 384 { 385 if (!I386_DR_VACANT (i) 386 && dr_mirror[i] == addr 387 && I386_DR_GET_RW_LEN (i) == len_rw_bits) 388 { 389 if (--dr_ref_count[i] == 0) /* no longer in use? */ 390 { 391 /* Reset our mirror. */ 392 dr_mirror[i] = 0; 393 I386_DR_DISABLE (i); 394 /* Reset it in the inferior. */ 395 i386_dr_low.set_control (dr_control_mirror); 396 if (i386_dr_low.reset_addr) 397 i386_dr_low.reset_addr (i); 398 } 399 retval = 0; 400 } 401 } 402 403 return retval; 404 } 405 406 /* Insert or remove a (possibly non-aligned) watchpoint, or count the 407 number of debug registers required to watch a region at address 408 ADDR whose length is LEN for accesses of type TYPE. Return 0 on 409 successful insertion or removal, a positive number when queried 410 about the number of registers, or -1 on failure. If WHAT is not a 411 valid value, bombs through internal_error. */ 412 413 static int 414 i386_handle_nonaligned_watchpoint (i386_wp_op_t what, CORE_ADDR addr, int len, 415 enum target_hw_bp_type type) 416 { 417 int retval = 0, status = 0; 418 int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; 419 420 static int size_try_array[8][8] = 421 { 422 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ 423 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ 424 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ 425 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ 426 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ 427 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ 428 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ 429 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ 430 }; 431 432 while (len > 0) 433 { 434 int align = addr % max_wp_len; 435 /* Four (eight on AMD64) is the maximum length a debug register 436 can watch. */ 437 int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); 438 int size = size_try_array[try][align]; 439 440 if (what == WP_COUNT) 441 { 442 /* size_try_array[] is defined such that each iteration 443 through the loop is guaranteed to produce an address and a 444 size that can be watched with a single debug register. 445 Thus, for counting the registers required to watch a 446 region, we simply need to increment the count on each 447 iteration. */ 448 retval++; 449 } 450 else 451 { 452 unsigned len_rw = i386_length_and_rw_bits (size, type); 453 454 if (what == WP_INSERT) 455 status = i386_insert_aligned_watchpoint (addr, len_rw); 456 else if (what == WP_REMOVE) 457 status = i386_remove_aligned_watchpoint (addr, len_rw); 458 else 459 internal_error (__FILE__, __LINE__, _("\ 460 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), 461 (int)what); 462 /* We keep the loop going even after a failure, because some 463 of the other aligned watchpoints might still succeed 464 (e.g. if they watch addresses that are already watched, 465 in which case we just increment the reference counts of 466 occupied debug registers). If we break out of the loop 467 too early, we could cause those addresses watched by 468 other watchpoints to be disabled when breakpoint.c reacts 469 to our failure to insert this watchpoint and tries to 470 remove it. */ 471 if (status) 472 retval = status; 473 } 474 475 addr += size; 476 len -= size; 477 } 478 479 return retval; 480 } 481 482 /* Insert a watchpoint to watch a memory region which starts at 483 address ADDR and whose length is LEN bytes. Watch memory accesses 484 of the type TYPE. Return 0 on success, -1 on failure. */ 485 486 static int 487 i386_insert_watchpoint (CORE_ADDR addr, int len, int type, 488 struct expression *cond) 489 { 490 int retval; 491 492 if (type == hw_read) 493 return 1; /* unsupported */ 494 495 if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) 496 || addr % len != 0) 497 retval = i386_handle_nonaligned_watchpoint (WP_INSERT, addr, len, type); 498 else 499 { 500 unsigned len_rw = i386_length_and_rw_bits (len, type); 501 502 retval = i386_insert_aligned_watchpoint (addr, len_rw); 503 } 504 505 if (maint_show_dr) 506 i386_show_dr ("insert_watchpoint", addr, len, type); 507 508 return retval; 509 } 510 511 /* Remove a watchpoint that watched the memory region which starts at 512 address ADDR, whose length is LEN bytes, and for accesses of the 513 type TYPE. Return 0 on success, -1 on failure. */ 514 static int 515 i386_remove_watchpoint (CORE_ADDR addr, int len, int type, 516 struct expression *cond) 517 { 518 int retval; 519 520 if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) 521 || addr % len != 0) 522 retval = i386_handle_nonaligned_watchpoint (WP_REMOVE, addr, len, type); 523 else 524 { 525 unsigned len_rw = i386_length_and_rw_bits (len, type); 526 527 retval = i386_remove_aligned_watchpoint (addr, len_rw); 528 } 529 530 if (maint_show_dr) 531 i386_show_dr ("remove_watchpoint", addr, len, type); 532 533 return retval; 534 } 535 536 /* Return non-zero if we can watch a memory region that starts at 537 address ADDR and whose length is LEN bytes. */ 538 539 static int 540 i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) 541 { 542 int nregs; 543 544 /* Compute how many aligned watchpoints we would need to cover this 545 region. */ 546 nregs = i386_handle_nonaligned_watchpoint (WP_COUNT, addr, len, hw_write); 547 return nregs <= DR_NADDR ? 1 : 0; 548 } 549 550 /* If the inferior has some watchpoint that triggered, set the 551 address associated with that watchpoint and return non-zero. 552 Otherwise, return zero. */ 553 554 static int 555 i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) 556 { 557 CORE_ADDR addr = 0; 558 int i; 559 int rc = 0; 560 561 dr_status_mirror = i386_dr_low.get_status (); 562 563 ALL_DEBUG_REGISTERS(i) 564 { 565 if (I386_DR_WATCH_HIT (i) 566 /* This second condition makes sure DRi is set up for a data 567 watchpoint, not a hardware breakpoint. The reason is 568 that GDB doesn't call the target_stopped_data_address 569 method except for data watchpoints. In other words, I'm 570 being paranoiac. */ 571 && I386_DR_GET_RW_LEN (i) != 0 572 /* This third condition makes sure DRi is not vacant, this 573 avoids false positives in windows-nat.c. */ 574 && !I386_DR_VACANT (i)) 575 { 576 addr = dr_mirror[i]; 577 rc = 1; 578 if (maint_show_dr) 579 i386_show_dr ("watchpoint_hit", addr, -1, hw_write); 580 } 581 } 582 if (maint_show_dr && addr == 0) 583 i386_show_dr ("stopped_data_addr", 0, 0, hw_write); 584 585 if (rc) 586 *addr_p = addr; 587 return rc; 588 } 589 590 static int 591 i386_stopped_by_watchpoint (void) 592 { 593 CORE_ADDR addr = 0; 594 return i386_stopped_data_address (¤t_target, &addr); 595 } 596 597 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. 598 Return 0 on success, EBUSY on failure. */ 599 static int 600 i386_insert_hw_breakpoint (struct gdbarch *gdbarch, 601 struct bp_target_info *bp_tgt) 602 { 603 unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); 604 CORE_ADDR addr = bp_tgt->placed_address; 605 int retval = i386_insert_aligned_watchpoint (addr, len_rw) ? EBUSY : 0; 606 607 if (maint_show_dr) 608 i386_show_dr ("insert_hwbp", addr, 1, hw_execute); 609 610 return retval; 611 } 612 613 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. 614 Return 0 on success, -1 on failure. */ 615 616 static int 617 i386_remove_hw_breakpoint (struct gdbarch *gdbarch, 618 struct bp_target_info *bp_tgt) 619 { 620 unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); 621 CORE_ADDR addr = bp_tgt->placed_address; 622 int retval = i386_remove_aligned_watchpoint (addr, len_rw); 623 624 if (maint_show_dr) 625 i386_show_dr ("remove_hwbp", addr, 1, hw_execute); 626 627 return retval; 628 } 629 630 /* Returns the number of hardware watchpoints of type TYPE that we can 631 set. Value is positive if we can set CNT watchpoints, zero if 632 setting watchpoints of type TYPE is not supported, and negative if 633 CNT is more than the maximum number of watchpoints of type TYPE 634 that we can support. TYPE is one of bp_hardware_watchpoint, 635 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. 636 CNT is the number of such watchpoints used so far (including this 637 one). OTHERTYPE is non-zero if other types of watchpoints are 638 currently enabled. 639 640 We always return 1 here because we don't have enough information 641 about possible overlap of addresses that they want to watch. As an 642 extreme example, consider the case where all the watchpoints watch 643 the same address and the same region length: then we can handle a 644 virtually unlimited number of watchpoints, due to debug register 645 sharing implemented via reference counts in i386-nat.c. */ 646 647 static int 648 i386_can_use_hw_breakpoint (int type, int cnt, int othertype) 649 { 650 return 1; 651 } 652 653 static void 654 add_show_debug_regs_command (void) 655 { 656 /* A maintenance command to enable printing the internal DRi mirror 657 variables. */ 658 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, 659 &maint_show_dr, _("\ 660 Set whether to show variables that mirror the x86 debug registers."), _("\ 661 Show whether to show variables that mirror the x86 debug registers."), _("\ 662 Use \"on\" to enable, \"off\" to disable.\n\ 663 If enabled, the debug registers values are shown when GDB inserts\n\ 664 or removes a hardware breakpoint or watchpoint, and when the inferior\n\ 665 triggers a breakpoint or watchpoint."), 666 NULL, 667 NULL, 668 &maintenance_set_cmdlist, 669 &maintenance_show_cmdlist); 670 } 671 672 /* There are only two global functions left. */ 673 674 void 675 i386_use_watchpoints (struct target_ops *t) 676 { 677 /* After a watchpoint trap, the PC points to the instruction after the 678 one that caused the trap. Therefore we don't need to step over it. 679 But we do need to reset the status register to avoid another trap. */ 680 t->to_have_continuable_watchpoint = 1; 681 682 t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; 683 t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; 684 t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; 685 t->to_stopped_data_address = i386_stopped_data_address; 686 t->to_insert_watchpoint = i386_insert_watchpoint; 687 t->to_remove_watchpoint = i386_remove_watchpoint; 688 t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; 689 t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; 690 } 691 692 void 693 i386_set_debug_register_length (int len) 694 { 695 /* This function should be called only once for each native target. */ 696 gdb_assert (i386_dr_low.debug_register_length == 0); 697 gdb_assert (len == 4 || len == 8); 698 i386_dr_low.debug_register_length = len; 699 add_show_debug_regs_command (); 700 } 701