1 /* opcode/i386.h -- Intel 80386 opcode macros 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived 24 ix86 Unix assemblers, generate floating point instructions with 25 reversed source and destination registers in certain cases. 26 Unfortunately, gcc and possibly many other programs use this 27 reversed syntax, so we're stuck with it. 28 29 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but 30 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than 31 the expected st(3) = st(3) - st 32 33 This happens with all the non-commutative arithmetic floating point 34 operations with two register operands, where the source register is 35 %st, and destination register is %st(i). 36 37 The affected opcode map is dceX, dcfX, deeX, defX. */ 38 39 #ifndef OPCODE_I386_H 40 #define OPCODE_I386_H 41 42 #ifndef SYSV386_COMPAT 43 /* Set non-zero for broken, compatible instructions. Set to zero for 44 non-broken opcodes at your peril. gcc generates SystemV/386 45 compatible instructions. */ 46 #define SYSV386_COMPAT 1 47 #endif 48 #ifndef OLDGCC_COMPAT 49 /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could 50 generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands 51 reversed. */ 52 #define OLDGCC_COMPAT SYSV386_COMPAT 53 #endif 54 55 #define MOV_AX_DISP32 0xa0 56 #define POP_SEG_SHORT 0x07 57 #define JUMP_PC_RELATIVE 0xeb 58 #define INT_OPCODE 0xcd 59 #define INT3_OPCODE 0xcc 60 /* The opcode for the fwait instruction, which disassembler treats as a 61 prefix when it can. */ 62 #define FWAIT_OPCODE 0x9b 63 64 /* Instruction prefixes. 65 NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as 66 part of the opcode. Other prefixes may still appear between them 67 and the 0x0f part of the opcode. */ 68 #define ADDR_PREFIX_OPCODE 0x67 69 #define DATA_PREFIX_OPCODE 0x66 70 #define LOCK_PREFIX_OPCODE 0xf0 71 #define CS_PREFIX_OPCODE 0x2e 72 #define DS_PREFIX_OPCODE 0x3e 73 #define ES_PREFIX_OPCODE 0x26 74 #define FS_PREFIX_OPCODE 0x64 75 #define GS_PREFIX_OPCODE 0x65 76 #define SS_PREFIX_OPCODE 0x36 77 #define REPNE_PREFIX_OPCODE 0xf2 78 #define REPE_PREFIX_OPCODE 0xf3 79 #define XACQUIRE_PREFIX_OPCODE 0xf2 80 #define XRELEASE_PREFIX_OPCODE 0xf3 81 82 #define TWO_BYTE_OPCODE_ESCAPE 0x0f 83 #define NOP_OPCODE (char) 0x90 84 85 /* register numbers */ 86 #define EAX_REG_NUM 0 87 #define ECX_REG_NUM 1 88 #define EDX_REG_NUM 2 89 #define EBX_REG_NUM 3 90 #define ESP_REG_NUM 4 91 #define EBP_REG_NUM 5 92 #define ESI_REG_NUM 6 93 #define EDI_REG_NUM 7 94 95 /* modrm_byte.regmem for twobyte escape */ 96 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM 97 /* index_base_byte.index for no index register addressing */ 98 #define NO_INDEX_REGISTER ESP_REG_NUM 99 /* index_base_byte.base for no base register addressing */ 100 #define NO_BASE_REGISTER EBP_REG_NUM 101 #define NO_BASE_REGISTER_16 6 102 103 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ 104 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ 105 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) 106 107 /* Extract fields from the mod/rm byte. */ 108 #define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3) 109 #define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7) 110 #define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7) 111 112 /* Extract fields from the sib byte. */ 113 #define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3) 114 #define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7) 115 #define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7) 116 117 /* x86-64 extension prefix. */ 118 #define REX_OPCODE 0x40 119 120 /* Non-zero if OPCODE is the rex prefix. */ 121 #define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE) 122 123 /* Indicates 64 bit operand size. */ 124 #define REX_W 8 125 /* High extension to reg field of modrm byte. */ 126 #define REX_R 4 127 /* High extension to SIB index field. */ 128 #define REX_X 2 129 /* High extension to base field of modrm or SIB, or reg field of opcode. */ 130 #define REX_B 1 131 132 /* max operands per insn */ 133 #define MAX_OPERANDS 5 134 135 /* max immediates per insn (lcall, ljmp, insertq, extrq) */ 136 #define MAX_IMMEDIATE_OPERANDS 2 137 138 /* max memory refs per insn (string ops) */ 139 #define MAX_MEMORY_OPERANDS 2 140 141 /* max size of insn mnemonics. */ 142 #define MAX_MNEM_SIZE 20 143 144 /* max size of register name in insn mnemonics. */ 145 #define MAX_REG_NAME_SIZE 8 146 147 #endif /* OPCODE_I386_H */ 148