1 /* Print i386 instructions for GDB, the GNU debugger. 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 4 Free Software Foundation, Inc. 5 6 This file is part of the GNU opcodes library. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) 25 July 1988 26 modified by John Hassey (hassey@dg-rtp.dg.com) 27 x86-64 support added by Jan Hubicka (jh@suse.cz) 28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ 29 30 /* The main tables describing the instructions is essentially a copy 31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386 32 Programmers Manual. Usually, there is a capital letter, followed 33 by a small letter. The capital letter tell the addressing mode, 34 and the small letter tells about the operand size. Refer to 35 the Intel manual for details. */ 36 37 #include "sysdep.h" 38 #include "dis-asm.h" 39 #include "opintl.h" 40 #include "opcode/i386.h" 41 #include "libiberty.h" 42 43 #include <setjmp.h> 44 45 static int fetch_data (struct disassemble_info *, bfd_byte *); 46 static void ckprefix (void); 47 static const char *prefix_name (int, int); 48 static int print_insn (bfd_vma, disassemble_info *); 49 static void dofloat (int); 50 static void OP_ST (int, int); 51 static void OP_STi (int, int); 52 static int putop (const char *, int); 53 static void oappend (const char *); 54 static void append_seg (void); 55 static void OP_indirE (int, int); 56 static void print_operand_value (char *, int, bfd_vma); 57 static void OP_E_register (int, int); 58 static void OP_E_memory (int, int); 59 static void OP_E_extended (int, int); 60 static void print_displacement (char *, bfd_vma); 61 static void OP_E (int, int); 62 static void OP_G (int, int); 63 static bfd_vma get64 (void); 64 static bfd_signed_vma get32 (void); 65 static bfd_signed_vma get32s (void); 66 static int get16 (void); 67 static void set_op (bfd_vma, int); 68 static void OP_Skip_MODRM (int, int); 69 static void OP_REG (int, int); 70 static void OP_IMREG (int, int); 71 static void OP_I (int, int); 72 static void OP_I64 (int, int); 73 static void OP_sI (int, int); 74 static void OP_J (int, int); 75 static void OP_SEG (int, int); 76 static void OP_DIR (int, int); 77 static void OP_OFF (int, int); 78 static void OP_OFF64 (int, int); 79 static void ptr_reg (int, int); 80 static void OP_ESreg (int, int); 81 static void OP_DSreg (int, int); 82 static void OP_C (int, int); 83 static void OP_D (int, int); 84 static void OP_T (int, int); 85 static void OP_R (int, int); 86 static void OP_MMX (int, int); 87 static void OP_XMM (int, int); 88 static void OP_EM (int, int); 89 static void OP_EX (int, int); 90 static void OP_EMC (int,int); 91 static void OP_MXC (int,int); 92 static void OP_MS (int, int); 93 static void OP_XS (int, int); 94 static void OP_M (int, int); 95 static void OP_VEX (int, int); 96 static void OP_VEX_FMA (int, int); 97 static void OP_EX_Vex (int, int); 98 static void OP_EX_VexW (int, int); 99 static void OP_XMM_Vex (int, int); 100 static void OP_XMM_VexW (int, int); 101 static void OP_REG_VexI4 (int, int); 102 static void PCLMUL_Fixup (int, int); 103 static void VEXI4_Fixup (int, int); 104 static void VZERO_Fixup (int, int); 105 static void VCMP_Fixup (int, int); 106 static void OP_0f07 (int, int); 107 static void OP_Monitor (int, int); 108 static void OP_Mwait (int, int); 109 static void NOP_Fixup1 (int, int); 110 static void NOP_Fixup2 (int, int); 111 static void OP_3DNowSuffix (int, int); 112 static void CMP_Fixup (int, int); 113 static void BadOp (void); 114 static void REP_Fixup (int, int); 115 static void CMPXCHG8B_Fixup (int, int); 116 static void XMM_Fixup (int, int); 117 static void CRC32_Fixup (int, int); 118 119 static void MOVBE_Fixup (int, int); 120 121 struct dis_private { 122 /* Points to first byte not fetched. */ 123 bfd_byte *max_fetched; 124 bfd_byte the_buffer[MAX_MNEM_SIZE]; 125 bfd_vma insn_start; 126 int orig_sizeflag; 127 jmp_buf bailout; 128 }; 129 130 enum address_mode 131 { 132 mode_16bit, 133 mode_32bit, 134 mode_64bit 135 }; 136 137 enum address_mode address_mode; 138 139 /* Flags for the prefixes for the current instruction. See below. */ 140 static int prefixes; 141 142 /* REX prefix the current instruction. See below. */ 143 static int rex; 144 /* Bits of REX we've already used. */ 145 static int rex_used; 146 /* Original REX prefix. */ 147 static int rex_original; 148 /* REX bits in original REX prefix ignored. It may not be the same 149 as rex_original since some bits may not be ignored. */ 150 static int rex_ignored; 151 /* Mark parts used in the REX prefix. When we are testing for 152 empty prefix (for 8bit register REX extension), just mask it 153 out. Otherwise test for REX bit is excuse for existence of REX 154 only in case value is nonzero. */ 155 #define USED_REX(value) \ 156 { \ 157 if (value) \ 158 { \ 159 if ((rex & value)) \ 160 rex_used |= (value) | REX_OPCODE; \ 161 } \ 162 else \ 163 rex_used |= REX_OPCODE; \ 164 } 165 166 /* Flags for prefixes which we somehow handled when printing the 167 current instruction. */ 168 static int used_prefixes; 169 170 /* Flags stored in PREFIXES. */ 171 #define PREFIX_REPZ 1 172 #define PREFIX_REPNZ 2 173 #define PREFIX_LOCK 4 174 #define PREFIX_CS 8 175 #define PREFIX_SS 0x10 176 #define PREFIX_DS 0x20 177 #define PREFIX_ES 0x40 178 #define PREFIX_FS 0x80 179 #define PREFIX_GS 0x100 180 #define PREFIX_DATA 0x200 181 #define PREFIX_ADDR 0x400 182 #define PREFIX_FWAIT 0x800 183 184 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) 185 to ADDR (exclusive) are valid. Returns 1 for success, longjmps 186 on error. */ 187 #define FETCH_DATA(info, addr) \ 188 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ 189 ? 1 : fetch_data ((info), (addr))) 190 191 static int 192 fetch_data (struct disassemble_info *info, bfd_byte *addr) 193 { 194 int status; 195 struct dis_private *priv = (struct dis_private *) info->private_data; 196 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); 197 198 if (addr <= priv->the_buffer + MAX_MNEM_SIZE) 199 status = (*info->read_memory_func) (start, 200 priv->max_fetched, 201 addr - priv->max_fetched, 202 info); 203 else 204 status = -1; 205 if (status != 0) 206 { 207 /* If we did manage to read at least one byte, then 208 print_insn_i386 will do something sensible. Otherwise, print 209 an error. We do that here because this is where we know 210 STATUS. */ 211 if (priv->max_fetched == priv->the_buffer) 212 (*info->memory_error_func) (status, start, info); 213 longjmp (priv->bailout, 1); 214 } 215 else 216 priv->max_fetched = addr; 217 return 1; 218 } 219 220 #define XX { NULL, 0 } 221 222 #define Eb { OP_E, b_mode } 223 #define EbS { OP_E, b_swap_mode } 224 #define Ev { OP_E, v_mode } 225 #define EvS { OP_E, v_swap_mode } 226 #define Ed { OP_E, d_mode } 227 #define Edq { OP_E, dq_mode } 228 #define Edqw { OP_E, dqw_mode } 229 #define Edqb { OP_E, dqb_mode } 230 #define Edqd { OP_E, dqd_mode } 231 #define Eq { OP_E, q_mode } 232 #define indirEv { OP_indirE, stack_v_mode } 233 #define indirEp { OP_indirE, f_mode } 234 #define stackEv { OP_E, stack_v_mode } 235 #define Em { OP_E, m_mode } 236 #define Ew { OP_E, w_mode } 237 #define M { OP_M, 0 } /* lea, lgdt, etc. */ 238 #define Ma { OP_M, a_mode } 239 #define Mb { OP_M, b_mode } 240 #define Md { OP_M, d_mode } 241 #define Mo { OP_M, o_mode } 242 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ 243 #define Mq { OP_M, q_mode } 244 #define Mx { OP_M, x_mode } 245 #define Mxmm { OP_M, xmm_mode } 246 #define Gb { OP_G, b_mode } 247 #define Gv { OP_G, v_mode } 248 #define Gd { OP_G, d_mode } 249 #define Gdq { OP_G, dq_mode } 250 #define Gm { OP_G, m_mode } 251 #define Gw { OP_G, w_mode } 252 #define Rd { OP_R, d_mode } 253 #define Rm { OP_R, m_mode } 254 #define Ib { OP_I, b_mode } 255 #define sIb { OP_sI, b_mode } /* sign extened byte */ 256 #define Iv { OP_I, v_mode } 257 #define Iq { OP_I, q_mode } 258 #define Iv64 { OP_I64, v_mode } 259 #define Iw { OP_I, w_mode } 260 #define I1 { OP_I, const_1_mode } 261 #define Jb { OP_J, b_mode } 262 #define Jv { OP_J, v_mode } 263 #define Cm { OP_C, m_mode } 264 #define Dm { OP_D, m_mode } 265 #define Td { OP_T, d_mode } 266 #define Skip_MODRM { OP_Skip_MODRM, 0 } 267 268 #define RMeAX { OP_REG, eAX_reg } 269 #define RMeBX { OP_REG, eBX_reg } 270 #define RMeCX { OP_REG, eCX_reg } 271 #define RMeDX { OP_REG, eDX_reg } 272 #define RMeSP { OP_REG, eSP_reg } 273 #define RMeBP { OP_REG, eBP_reg } 274 #define RMeSI { OP_REG, eSI_reg } 275 #define RMeDI { OP_REG, eDI_reg } 276 #define RMrAX { OP_REG, rAX_reg } 277 #define RMrBX { OP_REG, rBX_reg } 278 #define RMrCX { OP_REG, rCX_reg } 279 #define RMrDX { OP_REG, rDX_reg } 280 #define RMrSP { OP_REG, rSP_reg } 281 #define RMrBP { OP_REG, rBP_reg } 282 #define RMrSI { OP_REG, rSI_reg } 283 #define RMrDI { OP_REG, rDI_reg } 284 #define RMAL { OP_REG, al_reg } 285 #define RMAL { OP_REG, al_reg } 286 #define RMCL { OP_REG, cl_reg } 287 #define RMDL { OP_REG, dl_reg } 288 #define RMBL { OP_REG, bl_reg } 289 #define RMAH { OP_REG, ah_reg } 290 #define RMCH { OP_REG, ch_reg } 291 #define RMDH { OP_REG, dh_reg } 292 #define RMBH { OP_REG, bh_reg } 293 #define RMAX { OP_REG, ax_reg } 294 #define RMDX { OP_REG, dx_reg } 295 296 #define eAX { OP_IMREG, eAX_reg } 297 #define eBX { OP_IMREG, eBX_reg } 298 #define eCX { OP_IMREG, eCX_reg } 299 #define eDX { OP_IMREG, eDX_reg } 300 #define eSP { OP_IMREG, eSP_reg } 301 #define eBP { OP_IMREG, eBP_reg } 302 #define eSI { OP_IMREG, eSI_reg } 303 #define eDI { OP_IMREG, eDI_reg } 304 #define AL { OP_IMREG, al_reg } 305 #define CL { OP_IMREG, cl_reg } 306 #define DL { OP_IMREG, dl_reg } 307 #define BL { OP_IMREG, bl_reg } 308 #define AH { OP_IMREG, ah_reg } 309 #define CH { OP_IMREG, ch_reg } 310 #define DH { OP_IMREG, dh_reg } 311 #define BH { OP_IMREG, bh_reg } 312 #define AX { OP_IMREG, ax_reg } 313 #define DX { OP_IMREG, dx_reg } 314 #define zAX { OP_IMREG, z_mode_ax_reg } 315 #define indirDX { OP_IMREG, indir_dx_reg } 316 317 #define Sw { OP_SEG, w_mode } 318 #define Sv { OP_SEG, v_mode } 319 #define Ap { OP_DIR, 0 } 320 #define Ob { OP_OFF64, b_mode } 321 #define Ov { OP_OFF64, v_mode } 322 #define Xb { OP_DSreg, eSI_reg } 323 #define Xv { OP_DSreg, eSI_reg } 324 #define Xz { OP_DSreg, eSI_reg } 325 #define Yb { OP_ESreg, eDI_reg } 326 #define Yv { OP_ESreg, eDI_reg } 327 #define DSBX { OP_DSreg, eBX_reg } 328 329 #define es { OP_REG, es_reg } 330 #define ss { OP_REG, ss_reg } 331 #define cs { OP_REG, cs_reg } 332 #define ds { OP_REG, ds_reg } 333 #define fs { OP_REG, fs_reg } 334 #define gs { OP_REG, gs_reg } 335 336 #define MX { OP_MMX, 0 } 337 #define XM { OP_XMM, 0 } 338 #define XMM { OP_XMM, xmm_mode } 339 #define EM { OP_EM, v_mode } 340 #define EMS { OP_EM, v_swap_mode } 341 #define EMd { OP_EM, d_mode } 342 #define EMx { OP_EM, x_mode } 343 #define EXw { OP_EX, w_mode } 344 #define EXd { OP_EX, d_mode } 345 #define EXdS { OP_EX, d_swap_mode } 346 #define EXq { OP_EX, q_mode } 347 #define EXqS { OP_EX, q_swap_mode } 348 #define EXx { OP_EX, x_mode } 349 #define EXxS { OP_EX, x_swap_mode } 350 #define EXxmm { OP_EX, xmm_mode } 351 #define EXxmmq { OP_EX, xmmq_mode } 352 #define EXymmq { OP_EX, ymmq_mode } 353 #define EXVexWdq { OP_EX, vex_w_dq_mode } 354 #define MS { OP_MS, v_mode } 355 #define XS { OP_XS, v_mode } 356 #define EMCq { OP_EMC, q_mode } 357 #define MXC { OP_MXC, 0 } 358 #define OPSUF { OP_3DNowSuffix, 0 } 359 #define CMP { CMP_Fixup, 0 } 360 #define XMM0 { XMM_Fixup, 0 } 361 362 #define Vex { OP_VEX, vex_mode } 363 #define Vex128 { OP_VEX, vex128_mode } 364 #define Vex256 { OP_VEX, vex256_mode } 365 #define VexI4 { VEXI4_Fixup, 0} 366 #define VexFMA { OP_VEX_FMA, vex_mode } 367 #define Vex128FMA { OP_VEX_FMA, vex128_mode } 368 #define EXdVex { OP_EX_Vex, d_mode } 369 #define EXdVexS { OP_EX_Vex, d_swap_mode } 370 #define EXqVex { OP_EX_Vex, q_mode } 371 #define EXqVexS { OP_EX_Vex, q_swap_mode } 372 #define EXVexW { OP_EX_VexW, x_mode } 373 #define EXdVexW { OP_EX_VexW, d_mode } 374 #define EXqVexW { OP_EX_VexW, q_mode } 375 #define XMVex { OP_XMM_Vex, 0 } 376 #define XMVexW { OP_XMM_VexW, 0 } 377 #define XMVexI4 { OP_REG_VexI4, x_mode } 378 #define PCLMUL { PCLMUL_Fixup, 0 } 379 #define VZERO { VZERO_Fixup, 0 } 380 #define VCMP { VCMP_Fixup, 0 } 381 382 /* Used handle "rep" prefix for string instructions. */ 383 #define Xbr { REP_Fixup, eSI_reg } 384 #define Xvr { REP_Fixup, eSI_reg } 385 #define Ybr { REP_Fixup, eDI_reg } 386 #define Yvr { REP_Fixup, eDI_reg } 387 #define Yzr { REP_Fixup, eDI_reg } 388 #define indirDXr { REP_Fixup, indir_dx_reg } 389 #define ALr { REP_Fixup, al_reg } 390 #define eAXr { REP_Fixup, eAX_reg } 391 392 #define cond_jump_flag { NULL, cond_jump_mode } 393 #define loop_jcxz_flag { NULL, loop_jcxz_mode } 394 395 /* bits in sizeflag */ 396 #define SUFFIX_ALWAYS 4 397 #define AFLAG 2 398 #define DFLAG 1 399 400 /* byte operand */ 401 #define b_mode 1 402 /* byte operand with operand swapped */ 403 #define b_swap_mode (b_mode + 1) 404 /* operand size depends on prefixes */ 405 #define v_mode (b_swap_mode + 1) 406 /* operand size depends on prefixes with operand swapped */ 407 #define v_swap_mode (v_mode + 1) 408 /* word operand */ 409 #define w_mode (v_swap_mode + 1) 410 /* double word operand */ 411 #define d_mode (w_mode + 1) 412 /* double word operand with operand swapped */ 413 #define d_swap_mode (d_mode + 1) 414 /* quad word operand */ 415 #define q_mode (d_swap_mode + 1) 416 /* quad word operand with operand swapped */ 417 #define q_swap_mode (q_mode + 1) 418 /* ten-byte operand */ 419 #define t_mode (q_swap_mode + 1) 420 /* 16-byte XMM or 32-byte YMM operand */ 421 #define x_mode (t_mode + 1) 422 /* 16-byte XMM or 32-byte YMM operand with operand swapped */ 423 #define x_swap_mode (x_mode + 1) 424 /* 16-byte XMM operand */ 425 #define xmm_mode (x_swap_mode + 1) 426 /* 16-byte XMM or quad word operand */ 427 #define xmmq_mode (xmm_mode + 1) 428 /* 32-byte YMM or quad word operand */ 429 #define ymmq_mode (xmmq_mode + 1) 430 /* d_mode in 32bit, q_mode in 64bit mode. */ 431 #define m_mode (ymmq_mode + 1) 432 /* pair of v_mode operands */ 433 #define a_mode (m_mode + 1) 434 #define cond_jump_mode (a_mode + 1) 435 #define loop_jcxz_mode (cond_jump_mode + 1) 436 /* operand size depends on REX prefixes. */ 437 #define dq_mode (loop_jcxz_mode + 1) 438 /* registers like dq_mode, memory like w_mode. */ 439 #define dqw_mode (dq_mode + 1) 440 /* 4- or 6-byte pointer operand */ 441 #define f_mode (dqw_mode + 1) 442 #define const_1_mode (f_mode + 1) 443 /* v_mode for stack-related opcodes. */ 444 #define stack_v_mode (const_1_mode + 1) 445 /* non-quad operand size depends on prefixes */ 446 #define z_mode (stack_v_mode + 1) 447 /* 16-byte operand */ 448 #define o_mode (z_mode + 1) 449 /* registers like dq_mode, memory like b_mode. */ 450 #define dqb_mode (o_mode + 1) 451 /* registers like dq_mode, memory like d_mode. */ 452 #define dqd_mode (dqb_mode + 1) 453 /* normal vex mode */ 454 #define vex_mode (dqd_mode + 1) 455 /* 128bit vex mode */ 456 #define vex128_mode (vex_mode + 1) 457 /* 256bit vex mode */ 458 #define vex256_mode (vex128_mode + 1) 459 /* operand size depends on the VEX.W bit. */ 460 #define vex_w_dq_mode (vex256_mode + 1) 461 462 #define es_reg (vex_w_dq_mode + 1) 463 #define cs_reg (es_reg + 1) 464 #define ss_reg (cs_reg + 1) 465 #define ds_reg (ss_reg + 1) 466 #define fs_reg (ds_reg + 1) 467 #define gs_reg (fs_reg + 1) 468 469 #define eAX_reg (gs_reg + 1) 470 #define eCX_reg (eAX_reg + 1) 471 #define eDX_reg (eCX_reg + 1) 472 #define eBX_reg (eDX_reg + 1) 473 #define eSP_reg (eBX_reg + 1) 474 #define eBP_reg (eSP_reg + 1) 475 #define eSI_reg (eBP_reg + 1) 476 #define eDI_reg (eSI_reg + 1) 477 478 #define al_reg (eDI_reg + 1) 479 #define cl_reg (al_reg + 1) 480 #define dl_reg (cl_reg + 1) 481 #define bl_reg (dl_reg + 1) 482 #define ah_reg (bl_reg + 1) 483 #define ch_reg (ah_reg + 1) 484 #define dh_reg (ch_reg + 1) 485 #define bh_reg (dh_reg + 1) 486 487 #define ax_reg (bh_reg + 1) 488 #define cx_reg (ax_reg + 1) 489 #define dx_reg (cx_reg + 1) 490 #define bx_reg (dx_reg + 1) 491 #define sp_reg (bx_reg + 1) 492 #define bp_reg (sp_reg + 1) 493 #define si_reg (bp_reg + 1) 494 #define di_reg (si_reg + 1) 495 496 #define rAX_reg (di_reg + 1) 497 #define rCX_reg (rAX_reg + 1) 498 #define rDX_reg (rCX_reg + 1) 499 #define rBX_reg (rDX_reg + 1) 500 #define rSP_reg (rBX_reg + 1) 501 #define rBP_reg (rSP_reg + 1) 502 #define rSI_reg (rBP_reg + 1) 503 #define rDI_reg (rSI_reg + 1) 504 505 #define z_mode_ax_reg (rDI_reg + 1) 506 #define indir_dx_reg (z_mode_ax_reg + 1) 507 508 #define MAX_BYTEMODE indir_dx_reg 509 510 511 #define FLOATCODE 1 512 #define USE_REG_TABLE (FLOATCODE + 1) 513 #define USE_MOD_TABLE (USE_REG_TABLE + 1) 514 #define USE_RM_TABLE (USE_MOD_TABLE + 1) 515 #define USE_PREFIX_TABLE (USE_RM_TABLE + 1) 516 #define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1) 517 #define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1) 518 #define USE_VEX_C4_TABLE (USE_3BYTE_TABLE + 1) 519 #define USE_VEX_C5_TABLE (USE_VEX_C4_TABLE + 1) 520 #define USE_VEX_LEN_TABLE (USE_VEX_C5_TABLE + 1) 521 522 #define FLOAT NULL, { { NULL, FLOATCODE } } 523 524 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } 525 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) 526 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) 527 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) 528 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) 529 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) 530 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) 531 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) 532 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) 533 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) 534 535 #define REG_80 0 536 #define REG_81 (REG_80 + 1) 537 #define REG_82 (REG_81 + 1) 538 #define REG_8F (REG_82 + 1) 539 #define REG_C0 (REG_8F + 1) 540 #define REG_C1 (REG_C0 + 1) 541 #define REG_C6 (REG_C1 + 1) 542 #define REG_C7 (REG_C6 + 1) 543 #define REG_D0 (REG_C7 + 1) 544 #define REG_D1 (REG_D0 + 1) 545 #define REG_D2 (REG_D1 + 1) 546 #define REG_D3 (REG_D2 + 1) 547 #define REG_F6 (REG_D3 + 1) 548 #define REG_F7 (REG_F6 + 1) 549 #define REG_FE (REG_F7 + 1) 550 #define REG_FF (REG_FE + 1) 551 #define REG_0F00 (REG_FF + 1) 552 #define REG_0F01 (REG_0F00 + 1) 553 #define REG_0F0D (REG_0F01 + 1) 554 #define REG_0F18 (REG_0F0D + 1) 555 #define REG_0F71 (REG_0F18 + 1) 556 #define REG_0F72 (REG_0F71 + 1) 557 #define REG_0F73 (REG_0F72 + 1) 558 #define REG_0FA6 (REG_0F73 + 1) 559 #define REG_0FA7 (REG_0FA6 + 1) 560 #define REG_0FAE (REG_0FA7 + 1) 561 #define REG_0FBA (REG_0FAE + 1) 562 #define REG_0FC7 (REG_0FBA + 1) 563 #define REG_VEX_71 (REG_0FC7 + 1) 564 #define REG_VEX_72 (REG_VEX_71 + 1) 565 #define REG_VEX_73 (REG_VEX_72 + 1) 566 #define REG_VEX_AE (REG_VEX_73 + 1) 567 568 #define MOD_8D 0 569 #define MOD_0F01_REG_0 (MOD_8D + 1) 570 #define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1) 571 #define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1) 572 #define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1) 573 #define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1) 574 #define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1) 575 #define MOD_0F13 (MOD_0F12_PREFIX_0 + 1) 576 #define MOD_0F16_PREFIX_0 (MOD_0F13 + 1) 577 #define MOD_0F17 (MOD_0F16_PREFIX_0 + 1) 578 #define MOD_0F18_REG_0 (MOD_0F17 + 1) 579 #define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1) 580 #define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1) 581 #define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1) 582 #define MOD_0F20 (MOD_0F18_REG_3 + 1) 583 #define MOD_0F21 (MOD_0F20 + 1) 584 #define MOD_0F22 (MOD_0F21 + 1) 585 #define MOD_0F23 (MOD_0F22 + 1) 586 #define MOD_0F24 (MOD_0F23 + 1) 587 #define MOD_0F26 (MOD_0F24 + 1) 588 #define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1) 589 #define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1) 590 #define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1) 591 #define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1) 592 #define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1) 593 #define MOD_0F71_REG_2 (MOD_0F51 + 1) 594 #define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1) 595 #define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1) 596 #define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1) 597 #define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1) 598 #define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1) 599 #define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1) 600 #define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1) 601 #define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1) 602 #define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1) 603 #define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1) 604 #define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1) 605 #define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1) 606 #define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1) 607 #define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1) 608 #define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1) 609 #define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1) 610 #define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1) 611 #define MOD_0FB2 (MOD_0FAE_REG_7 + 1) 612 #define MOD_0FB4 (MOD_0FB2 + 1) 613 #define MOD_0FB5 (MOD_0FB4 + 1) 614 #define MOD_0FC7_REG_6 (MOD_0FB5 + 1) 615 #define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1) 616 #define MOD_0FD7 (MOD_0FC7_REG_7 + 1) 617 #define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1) 618 #define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1) 619 #define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1) 620 #define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1) 621 #define MOD_C4_32BIT (MOD_62_32BIT + 1) 622 #define MOD_C5_32BIT (MOD_C4_32BIT + 1) 623 #define MOD_VEX_12_PREFIX_0 (MOD_C5_32BIT + 1) 624 #define MOD_VEX_13 (MOD_VEX_12_PREFIX_0 + 1) 625 #define MOD_VEX_16_PREFIX_0 (MOD_VEX_13 + 1) 626 #define MOD_VEX_17 (MOD_VEX_16_PREFIX_0 + 1) 627 #define MOD_VEX_2B (MOD_VEX_17 + 1) 628 #define MOD_VEX_51 (MOD_VEX_2B + 1) 629 #define MOD_VEX_71_REG_2 (MOD_VEX_51 + 1) 630 #define MOD_VEX_71_REG_4 (MOD_VEX_71_REG_2 + 1) 631 #define MOD_VEX_71_REG_6 (MOD_VEX_71_REG_4 + 1) 632 #define MOD_VEX_72_REG_2 (MOD_VEX_71_REG_6 + 1) 633 #define MOD_VEX_72_REG_4 (MOD_VEX_72_REG_2 + 1) 634 #define MOD_VEX_72_REG_6 (MOD_VEX_72_REG_4 + 1) 635 #define MOD_VEX_73_REG_2 (MOD_VEX_72_REG_6 + 1) 636 #define MOD_VEX_73_REG_3 (MOD_VEX_73_REG_2 + 1) 637 #define MOD_VEX_73_REG_6 (MOD_VEX_73_REG_3 + 1) 638 #define MOD_VEX_73_REG_7 (MOD_VEX_73_REG_6 + 1) 639 #define MOD_VEX_AE_REG_2 (MOD_VEX_73_REG_7 + 1) 640 #define MOD_VEX_AE_REG_3 (MOD_VEX_AE_REG_2 + 1) 641 #define MOD_VEX_D7_PREFIX_2 (MOD_VEX_AE_REG_3 + 1) 642 #define MOD_VEX_E7_PREFIX_2 (MOD_VEX_D7_PREFIX_2 + 1) 643 #define MOD_VEX_F0_PREFIX_3 (MOD_VEX_E7_PREFIX_2 + 1) 644 #define MOD_VEX_3818_PREFIX_2 (MOD_VEX_F0_PREFIX_3 + 1) 645 #define MOD_VEX_3819_PREFIX_2 (MOD_VEX_3818_PREFIX_2 + 1) 646 #define MOD_VEX_381A_PREFIX_2 (MOD_VEX_3819_PREFIX_2 + 1) 647 #define MOD_VEX_382A_PREFIX_2 (MOD_VEX_381A_PREFIX_2 + 1) 648 #define MOD_VEX_382C_PREFIX_2 (MOD_VEX_382A_PREFIX_2 + 1) 649 #define MOD_VEX_382D_PREFIX_2 (MOD_VEX_382C_PREFIX_2 + 1) 650 #define MOD_VEX_382E_PREFIX_2 (MOD_VEX_382D_PREFIX_2 + 1) 651 #define MOD_VEX_382F_PREFIX_2 (MOD_VEX_382E_PREFIX_2 + 1) 652 653 #define RM_0F01_REG_0 0 654 #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1) 655 #define RM_0F01_REG_2 (RM_0F01_REG_1 + 1) 656 #define RM_0F01_REG_3 (RM_0F01_REG_2 + 1) 657 #define RM_0F01_REG_7 (RM_0F01_REG_3 + 1) 658 #define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1) 659 #define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1) 660 #define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1) 661 662 #define PREFIX_90 0 663 #define PREFIX_0F10 (PREFIX_90 + 1) 664 #define PREFIX_0F11 (PREFIX_0F10 + 1) 665 #define PREFIX_0F12 (PREFIX_0F11 + 1) 666 #define PREFIX_0F16 (PREFIX_0F12 + 1) 667 #define PREFIX_0F2A (PREFIX_0F16 + 1) 668 #define PREFIX_0F2B (PREFIX_0F2A + 1) 669 #define PREFIX_0F2C (PREFIX_0F2B + 1) 670 #define PREFIX_0F2D (PREFIX_0F2C + 1) 671 #define PREFIX_0F2E (PREFIX_0F2D + 1) 672 #define PREFIX_0F2F (PREFIX_0F2E + 1) 673 #define PREFIX_0F51 (PREFIX_0F2F + 1) 674 #define PREFIX_0F52 (PREFIX_0F51 + 1) 675 #define PREFIX_0F53 (PREFIX_0F52 + 1) 676 #define PREFIX_0F58 (PREFIX_0F53 + 1) 677 #define PREFIX_0F59 (PREFIX_0F58 + 1) 678 #define PREFIX_0F5A (PREFIX_0F59 + 1) 679 #define PREFIX_0F5B (PREFIX_0F5A + 1) 680 #define PREFIX_0F5C (PREFIX_0F5B + 1) 681 #define PREFIX_0F5D (PREFIX_0F5C + 1) 682 #define PREFIX_0F5E (PREFIX_0F5D + 1) 683 #define PREFIX_0F5F (PREFIX_0F5E + 1) 684 #define PREFIX_0F60 (PREFIX_0F5F + 1) 685 #define PREFIX_0F61 (PREFIX_0F60 + 1) 686 #define PREFIX_0F62 (PREFIX_0F61 + 1) 687 #define PREFIX_0F6C (PREFIX_0F62 + 1) 688 #define PREFIX_0F6D (PREFIX_0F6C + 1) 689 #define PREFIX_0F6F (PREFIX_0F6D + 1) 690 #define PREFIX_0F70 (PREFIX_0F6F + 1) 691 #define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1) 692 #define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1) 693 #define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1) 694 #define PREFIX_0F79 (PREFIX_0F78 + 1) 695 #define PREFIX_0F7C (PREFIX_0F79 + 1) 696 #define PREFIX_0F7D (PREFIX_0F7C + 1) 697 #define PREFIX_0F7E (PREFIX_0F7D + 1) 698 #define PREFIX_0F7F (PREFIX_0F7E + 1) 699 #define PREFIX_0FB8 (PREFIX_0F7F + 1) 700 #define PREFIX_0FBD (PREFIX_0FB8 + 1) 701 #define PREFIX_0FC2 (PREFIX_0FBD + 1) 702 #define PREFIX_0FC3 (PREFIX_0FC2 + 1) 703 #define PREFIX_0FC7_REG_6 (PREFIX_0FC3 + 1) 704 #define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1) 705 #define PREFIX_0FD6 (PREFIX_0FD0 + 1) 706 #define PREFIX_0FE6 (PREFIX_0FD6 + 1) 707 #define PREFIX_0FE7 (PREFIX_0FE6 + 1) 708 #define PREFIX_0FF0 (PREFIX_0FE7 + 1) 709 #define PREFIX_0FF7 (PREFIX_0FF0 + 1) 710 #define PREFIX_0F3810 (PREFIX_0FF7 + 1) 711 #define PREFIX_0F3814 (PREFIX_0F3810 + 1) 712 #define PREFIX_0F3815 (PREFIX_0F3814 + 1) 713 #define PREFIX_0F3817 (PREFIX_0F3815 + 1) 714 #define PREFIX_0F3820 (PREFIX_0F3817 + 1) 715 #define PREFIX_0F3821 (PREFIX_0F3820 + 1) 716 #define PREFIX_0F3822 (PREFIX_0F3821 + 1) 717 #define PREFIX_0F3823 (PREFIX_0F3822 + 1) 718 #define PREFIX_0F3824 (PREFIX_0F3823 + 1) 719 #define PREFIX_0F3825 (PREFIX_0F3824 + 1) 720 #define PREFIX_0F3828 (PREFIX_0F3825 + 1) 721 #define PREFIX_0F3829 (PREFIX_0F3828 + 1) 722 #define PREFIX_0F382A (PREFIX_0F3829 + 1) 723 #define PREFIX_0F382B (PREFIX_0F382A + 1) 724 #define PREFIX_0F3830 (PREFIX_0F382B + 1) 725 #define PREFIX_0F3831 (PREFIX_0F3830 + 1) 726 #define PREFIX_0F3832 (PREFIX_0F3831 + 1) 727 #define PREFIX_0F3833 (PREFIX_0F3832 + 1) 728 #define PREFIX_0F3834 (PREFIX_0F3833 + 1) 729 #define PREFIX_0F3835 (PREFIX_0F3834 + 1) 730 #define PREFIX_0F3837 (PREFIX_0F3835 + 1) 731 #define PREFIX_0F3838 (PREFIX_0F3837 + 1) 732 #define PREFIX_0F3839 (PREFIX_0F3838 + 1) 733 #define PREFIX_0F383A (PREFIX_0F3839 + 1) 734 #define PREFIX_0F383B (PREFIX_0F383A + 1) 735 #define PREFIX_0F383C (PREFIX_0F383B + 1) 736 #define PREFIX_0F383D (PREFIX_0F383C + 1) 737 #define PREFIX_0F383E (PREFIX_0F383D + 1) 738 #define PREFIX_0F383F (PREFIX_0F383E + 1) 739 #define PREFIX_0F3840 (PREFIX_0F383F + 1) 740 #define PREFIX_0F3841 (PREFIX_0F3840 + 1) 741 #define PREFIX_0F3880 (PREFIX_0F3841 + 1) 742 #define PREFIX_0F3881 (PREFIX_0F3880 + 1) 743 #define PREFIX_0F38DB (PREFIX_0F3881 + 1) 744 #define PREFIX_0F38DC (PREFIX_0F38DB + 1) 745 #define PREFIX_0F38DD (PREFIX_0F38DC + 1) 746 #define PREFIX_0F38DE (PREFIX_0F38DD + 1) 747 #define PREFIX_0F38DF (PREFIX_0F38DE + 1) 748 #define PREFIX_0F38F0 (PREFIX_0F38DF + 1) 749 #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1) 750 #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1) 751 #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1) 752 #define PREFIX_0F3A0A (PREFIX_0F3A09 + 1) 753 #define PREFIX_0F3A0B (PREFIX_0F3A0A + 1) 754 #define PREFIX_0F3A0C (PREFIX_0F3A0B + 1) 755 #define PREFIX_0F3A0D (PREFIX_0F3A0C + 1) 756 #define PREFIX_0F3A0E (PREFIX_0F3A0D + 1) 757 #define PREFIX_0F3A14 (PREFIX_0F3A0E + 1) 758 #define PREFIX_0F3A15 (PREFIX_0F3A14 + 1) 759 #define PREFIX_0F3A16 (PREFIX_0F3A15 + 1) 760 #define PREFIX_0F3A17 (PREFIX_0F3A16 + 1) 761 #define PREFIX_0F3A20 (PREFIX_0F3A17 + 1) 762 #define PREFIX_0F3A21 (PREFIX_0F3A20 + 1) 763 #define PREFIX_0F3A22 (PREFIX_0F3A21 + 1) 764 #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1) 765 #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1) 766 #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1) 767 #define PREFIX_0F3A44 (PREFIX_0F3A42 + 1) 768 #define PREFIX_0F3A60 (PREFIX_0F3A44 + 1) 769 #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1) 770 #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1) 771 #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1) 772 #define PREFIX_0F3ADF (PREFIX_0F3A63 + 1) 773 #define PREFIX_VEX_10 (PREFIX_0F3ADF + 1) 774 #define PREFIX_VEX_11 (PREFIX_VEX_10 + 1) 775 #define PREFIX_VEX_12 (PREFIX_VEX_11 + 1) 776 #define PREFIX_VEX_16 (PREFIX_VEX_12 + 1) 777 #define PREFIX_VEX_2A (PREFIX_VEX_16 + 1) 778 #define PREFIX_VEX_2C (PREFIX_VEX_2A + 1) 779 #define PREFIX_VEX_2D (PREFIX_VEX_2C + 1) 780 #define PREFIX_VEX_2E (PREFIX_VEX_2D + 1) 781 #define PREFIX_VEX_2F (PREFIX_VEX_2E + 1) 782 #define PREFIX_VEX_51 (PREFIX_VEX_2F + 1) 783 #define PREFIX_VEX_52 (PREFIX_VEX_51 + 1) 784 #define PREFIX_VEX_53 (PREFIX_VEX_52 + 1) 785 #define PREFIX_VEX_58 (PREFIX_VEX_53 + 1) 786 #define PREFIX_VEX_59 (PREFIX_VEX_58 + 1) 787 #define PREFIX_VEX_5A (PREFIX_VEX_59 + 1) 788 #define PREFIX_VEX_5B (PREFIX_VEX_5A + 1) 789 #define PREFIX_VEX_5C (PREFIX_VEX_5B + 1) 790 #define PREFIX_VEX_5D (PREFIX_VEX_5C + 1) 791 #define PREFIX_VEX_5E (PREFIX_VEX_5D + 1) 792 #define PREFIX_VEX_5F (PREFIX_VEX_5E + 1) 793 #define PREFIX_VEX_60 (PREFIX_VEX_5F + 1) 794 #define PREFIX_VEX_61 (PREFIX_VEX_60 + 1) 795 #define PREFIX_VEX_62 (PREFIX_VEX_61 + 1) 796 #define PREFIX_VEX_63 (PREFIX_VEX_62 + 1) 797 #define PREFIX_VEX_64 (PREFIX_VEX_63 + 1) 798 #define PREFIX_VEX_65 (PREFIX_VEX_64 + 1) 799 #define PREFIX_VEX_66 (PREFIX_VEX_65 + 1) 800 #define PREFIX_VEX_67 (PREFIX_VEX_66 + 1) 801 #define PREFIX_VEX_68 (PREFIX_VEX_67 + 1) 802 #define PREFIX_VEX_69 (PREFIX_VEX_68 + 1) 803 #define PREFIX_VEX_6A (PREFIX_VEX_69 + 1) 804 #define PREFIX_VEX_6B (PREFIX_VEX_6A + 1) 805 #define PREFIX_VEX_6C (PREFIX_VEX_6B + 1) 806 #define PREFIX_VEX_6D (PREFIX_VEX_6C + 1) 807 #define PREFIX_VEX_6E (PREFIX_VEX_6D + 1) 808 #define PREFIX_VEX_6F (PREFIX_VEX_6E + 1) 809 #define PREFIX_VEX_70 (PREFIX_VEX_6F + 1) 810 #define PREFIX_VEX_71_REG_2 (PREFIX_VEX_70 + 1) 811 #define PREFIX_VEX_71_REG_4 (PREFIX_VEX_71_REG_2 + 1) 812 #define PREFIX_VEX_71_REG_6 (PREFIX_VEX_71_REG_4 + 1) 813 #define PREFIX_VEX_72_REG_2 (PREFIX_VEX_71_REG_6 + 1) 814 #define PREFIX_VEX_72_REG_4 (PREFIX_VEX_72_REG_2 + 1) 815 #define PREFIX_VEX_72_REG_6 (PREFIX_VEX_72_REG_4 + 1) 816 #define PREFIX_VEX_73_REG_2 (PREFIX_VEX_72_REG_6 + 1) 817 #define PREFIX_VEX_73_REG_3 (PREFIX_VEX_73_REG_2 + 1) 818 #define PREFIX_VEX_73_REG_6 (PREFIX_VEX_73_REG_3 + 1) 819 #define PREFIX_VEX_73_REG_7 (PREFIX_VEX_73_REG_6 + 1) 820 #define PREFIX_VEX_74 (PREFIX_VEX_73_REG_7 + 1) 821 #define PREFIX_VEX_75 (PREFIX_VEX_74 + 1) 822 #define PREFIX_VEX_76 (PREFIX_VEX_75 + 1) 823 #define PREFIX_VEX_77 (PREFIX_VEX_76 + 1) 824 #define PREFIX_VEX_7C (PREFIX_VEX_77 + 1) 825 #define PREFIX_VEX_7D (PREFIX_VEX_7C + 1) 826 #define PREFIX_VEX_7E (PREFIX_VEX_7D + 1) 827 #define PREFIX_VEX_7F (PREFIX_VEX_7E + 1) 828 #define PREFIX_VEX_C2 (PREFIX_VEX_7F + 1) 829 #define PREFIX_VEX_C4 (PREFIX_VEX_C2 + 1) 830 #define PREFIX_VEX_C5 (PREFIX_VEX_C4 + 1) 831 #define PREFIX_VEX_D0 (PREFIX_VEX_C5 + 1) 832 #define PREFIX_VEX_D1 (PREFIX_VEX_D0 + 1) 833 #define PREFIX_VEX_D2 (PREFIX_VEX_D1 + 1) 834 #define PREFIX_VEX_D3 (PREFIX_VEX_D2 + 1) 835 #define PREFIX_VEX_D4 (PREFIX_VEX_D3 + 1) 836 #define PREFIX_VEX_D5 (PREFIX_VEX_D4 + 1) 837 #define PREFIX_VEX_D6 (PREFIX_VEX_D5 + 1) 838 #define PREFIX_VEX_D7 (PREFIX_VEX_D6 + 1) 839 #define PREFIX_VEX_D8 (PREFIX_VEX_D7 + 1) 840 #define PREFIX_VEX_D9 (PREFIX_VEX_D8 + 1) 841 #define PREFIX_VEX_DA (PREFIX_VEX_D9 + 1) 842 #define PREFIX_VEX_DB (PREFIX_VEX_DA + 1) 843 #define PREFIX_VEX_DC (PREFIX_VEX_DB + 1) 844 #define PREFIX_VEX_DD (PREFIX_VEX_DC + 1) 845 #define PREFIX_VEX_DE (PREFIX_VEX_DD + 1) 846 #define PREFIX_VEX_DF (PREFIX_VEX_DE + 1) 847 #define PREFIX_VEX_E0 (PREFIX_VEX_DF + 1) 848 #define PREFIX_VEX_E1 (PREFIX_VEX_E0 + 1) 849 #define PREFIX_VEX_E2 (PREFIX_VEX_E1 + 1) 850 #define PREFIX_VEX_E3 (PREFIX_VEX_E2 + 1) 851 #define PREFIX_VEX_E4 (PREFIX_VEX_E3 + 1) 852 #define PREFIX_VEX_E5 (PREFIX_VEX_E4 + 1) 853 #define PREFIX_VEX_E6 (PREFIX_VEX_E5 + 1) 854 #define PREFIX_VEX_E7 (PREFIX_VEX_E6 + 1) 855 #define PREFIX_VEX_E8 (PREFIX_VEX_E7 + 1) 856 #define PREFIX_VEX_E9 (PREFIX_VEX_E8 + 1) 857 #define PREFIX_VEX_EA (PREFIX_VEX_E9 + 1) 858 #define PREFIX_VEX_EB (PREFIX_VEX_EA + 1) 859 #define PREFIX_VEX_EC (PREFIX_VEX_EB + 1) 860 #define PREFIX_VEX_ED (PREFIX_VEX_EC + 1) 861 #define PREFIX_VEX_EE (PREFIX_VEX_ED + 1) 862 #define PREFIX_VEX_EF (PREFIX_VEX_EE + 1) 863 #define PREFIX_VEX_F0 (PREFIX_VEX_EF + 1) 864 #define PREFIX_VEX_F1 (PREFIX_VEX_F0 + 1) 865 #define PREFIX_VEX_F2 (PREFIX_VEX_F1 + 1) 866 #define PREFIX_VEX_F3 (PREFIX_VEX_F2 + 1) 867 #define PREFIX_VEX_F4 (PREFIX_VEX_F3 + 1) 868 #define PREFIX_VEX_F5 (PREFIX_VEX_F4 + 1) 869 #define PREFIX_VEX_F6 (PREFIX_VEX_F5 + 1) 870 #define PREFIX_VEX_F7 (PREFIX_VEX_F6 + 1) 871 #define PREFIX_VEX_F8 (PREFIX_VEX_F7 + 1) 872 #define PREFIX_VEX_F9 (PREFIX_VEX_F8 + 1) 873 #define PREFIX_VEX_FA (PREFIX_VEX_F9 + 1) 874 #define PREFIX_VEX_FB (PREFIX_VEX_FA + 1) 875 #define PREFIX_VEX_FC (PREFIX_VEX_FB + 1) 876 #define PREFIX_VEX_FD (PREFIX_VEX_FC + 1) 877 #define PREFIX_VEX_FE (PREFIX_VEX_FD + 1) 878 #define PREFIX_VEX_3800 (PREFIX_VEX_FE + 1) 879 #define PREFIX_VEX_3801 (PREFIX_VEX_3800 + 1) 880 #define PREFIX_VEX_3802 (PREFIX_VEX_3801 + 1) 881 #define PREFIX_VEX_3803 (PREFIX_VEX_3802 + 1) 882 #define PREFIX_VEX_3804 (PREFIX_VEX_3803 + 1) 883 #define PREFIX_VEX_3805 (PREFIX_VEX_3804 + 1) 884 #define PREFIX_VEX_3806 (PREFIX_VEX_3805 + 1) 885 #define PREFIX_VEX_3807 (PREFIX_VEX_3806 + 1) 886 #define PREFIX_VEX_3808 (PREFIX_VEX_3807 + 1) 887 #define PREFIX_VEX_3809 (PREFIX_VEX_3808 + 1) 888 #define PREFIX_VEX_380A (PREFIX_VEX_3809 + 1) 889 #define PREFIX_VEX_380B (PREFIX_VEX_380A + 1) 890 #define PREFIX_VEX_380C (PREFIX_VEX_380B + 1) 891 #define PREFIX_VEX_380D (PREFIX_VEX_380C + 1) 892 #define PREFIX_VEX_380E (PREFIX_VEX_380D + 1) 893 #define PREFIX_VEX_380F (PREFIX_VEX_380E + 1) 894 #define PREFIX_VEX_3817 (PREFIX_VEX_380F + 1) 895 #define PREFIX_VEX_3818 (PREFIX_VEX_3817 + 1) 896 #define PREFIX_VEX_3819 (PREFIX_VEX_3818 + 1) 897 #define PREFIX_VEX_381A (PREFIX_VEX_3819 + 1) 898 #define PREFIX_VEX_381C (PREFIX_VEX_381A + 1) 899 #define PREFIX_VEX_381D (PREFIX_VEX_381C + 1) 900 #define PREFIX_VEX_381E (PREFIX_VEX_381D + 1) 901 #define PREFIX_VEX_3820 (PREFIX_VEX_381E + 1) 902 #define PREFIX_VEX_3821 (PREFIX_VEX_3820 + 1) 903 #define PREFIX_VEX_3822 (PREFIX_VEX_3821 + 1) 904 #define PREFIX_VEX_3823 (PREFIX_VEX_3822 + 1) 905 #define PREFIX_VEX_3824 (PREFIX_VEX_3823 + 1) 906 #define PREFIX_VEX_3825 (PREFIX_VEX_3824 + 1) 907 #define PREFIX_VEX_3828 (PREFIX_VEX_3825 + 1) 908 #define PREFIX_VEX_3829 (PREFIX_VEX_3828 + 1) 909 #define PREFIX_VEX_382A (PREFIX_VEX_3829 + 1) 910 #define PREFIX_VEX_382B (PREFIX_VEX_382A + 1) 911 #define PREFIX_VEX_382C (PREFIX_VEX_382B + 1) 912 #define PREFIX_VEX_382D (PREFIX_VEX_382C + 1) 913 #define PREFIX_VEX_382E (PREFIX_VEX_382D + 1) 914 #define PREFIX_VEX_382F (PREFIX_VEX_382E + 1) 915 #define PREFIX_VEX_3830 (PREFIX_VEX_382F + 1) 916 #define PREFIX_VEX_3831 (PREFIX_VEX_3830 + 1) 917 #define PREFIX_VEX_3832 (PREFIX_VEX_3831 + 1) 918 #define PREFIX_VEX_3833 (PREFIX_VEX_3832 + 1) 919 #define PREFIX_VEX_3834 (PREFIX_VEX_3833 + 1) 920 #define PREFIX_VEX_3835 (PREFIX_VEX_3834 + 1) 921 #define PREFIX_VEX_3837 (PREFIX_VEX_3835 + 1) 922 #define PREFIX_VEX_3838 (PREFIX_VEX_3837 + 1) 923 #define PREFIX_VEX_3839 (PREFIX_VEX_3838 + 1) 924 #define PREFIX_VEX_383A (PREFIX_VEX_3839 + 1) 925 #define PREFIX_VEX_383B (PREFIX_VEX_383A + 1) 926 #define PREFIX_VEX_383C (PREFIX_VEX_383B + 1) 927 #define PREFIX_VEX_383D (PREFIX_VEX_383C + 1) 928 #define PREFIX_VEX_383E (PREFIX_VEX_383D + 1) 929 #define PREFIX_VEX_383F (PREFIX_VEX_383E + 1) 930 #define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1) 931 #define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1) 932 #define PREFIX_VEX_3896 (PREFIX_VEX_3841 + 1) 933 #define PREFIX_VEX_3897 (PREFIX_VEX_3896 + 1) 934 #define PREFIX_VEX_3898 (PREFIX_VEX_3897 + 1) 935 #define PREFIX_VEX_3899 (PREFIX_VEX_3898 + 1) 936 #define PREFIX_VEX_389A (PREFIX_VEX_3899 + 1) 937 #define PREFIX_VEX_389B (PREFIX_VEX_389A + 1) 938 #define PREFIX_VEX_389C (PREFIX_VEX_389B + 1) 939 #define PREFIX_VEX_389D (PREFIX_VEX_389C + 1) 940 #define PREFIX_VEX_389E (PREFIX_VEX_389D + 1) 941 #define PREFIX_VEX_389F (PREFIX_VEX_389E + 1) 942 #define PREFIX_VEX_38A6 (PREFIX_VEX_389F + 1) 943 #define PREFIX_VEX_38A7 (PREFIX_VEX_38A6 + 1) 944 #define PREFIX_VEX_38A8 (PREFIX_VEX_38A7 + 1) 945 #define PREFIX_VEX_38A9 (PREFIX_VEX_38A8 + 1) 946 #define PREFIX_VEX_38AA (PREFIX_VEX_38A9 + 1) 947 #define PREFIX_VEX_38AB (PREFIX_VEX_38AA + 1) 948 #define PREFIX_VEX_38AC (PREFIX_VEX_38AB + 1) 949 #define PREFIX_VEX_38AD (PREFIX_VEX_38AC + 1) 950 #define PREFIX_VEX_38AE (PREFIX_VEX_38AD + 1) 951 #define PREFIX_VEX_38AF (PREFIX_VEX_38AE + 1) 952 #define PREFIX_VEX_38B6 (PREFIX_VEX_38AF + 1) 953 #define PREFIX_VEX_38B7 (PREFIX_VEX_38B6 + 1) 954 #define PREFIX_VEX_38B8 (PREFIX_VEX_38B7 + 1) 955 #define PREFIX_VEX_38B9 (PREFIX_VEX_38B8 + 1) 956 #define PREFIX_VEX_38BA (PREFIX_VEX_38B9 + 1) 957 #define PREFIX_VEX_38BB (PREFIX_VEX_38BA + 1) 958 #define PREFIX_VEX_38BC (PREFIX_VEX_38BB + 1) 959 #define PREFIX_VEX_38BD (PREFIX_VEX_38BC + 1) 960 #define PREFIX_VEX_38BE (PREFIX_VEX_38BD + 1) 961 #define PREFIX_VEX_38BF (PREFIX_VEX_38BE + 1) 962 #define PREFIX_VEX_38DB (PREFIX_VEX_38BF + 1) 963 #define PREFIX_VEX_38DC (PREFIX_VEX_38DB + 1) 964 #define PREFIX_VEX_38DD (PREFIX_VEX_38DC + 1) 965 #define PREFIX_VEX_38DE (PREFIX_VEX_38DD + 1) 966 #define PREFIX_VEX_38DF (PREFIX_VEX_38DE + 1) 967 #define PREFIX_VEX_3A04 (PREFIX_VEX_38DF + 1) 968 #define PREFIX_VEX_3A05 (PREFIX_VEX_3A04 + 1) 969 #define PREFIX_VEX_3A06 (PREFIX_VEX_3A05 + 1) 970 #define PREFIX_VEX_3A08 (PREFIX_VEX_3A06 + 1) 971 #define PREFIX_VEX_3A09 (PREFIX_VEX_3A08 + 1) 972 #define PREFIX_VEX_3A0A (PREFIX_VEX_3A09 + 1) 973 #define PREFIX_VEX_3A0B (PREFIX_VEX_3A0A + 1) 974 #define PREFIX_VEX_3A0C (PREFIX_VEX_3A0B + 1) 975 #define PREFIX_VEX_3A0D (PREFIX_VEX_3A0C + 1) 976 #define PREFIX_VEX_3A0E (PREFIX_VEX_3A0D + 1) 977 #define PREFIX_VEX_3A0F (PREFIX_VEX_3A0E + 1) 978 #define PREFIX_VEX_3A14 (PREFIX_VEX_3A0F + 1) 979 #define PREFIX_VEX_3A15 (PREFIX_VEX_3A14 + 1) 980 #define PREFIX_VEX_3A16 (PREFIX_VEX_3A15 + 1) 981 #define PREFIX_VEX_3A17 (PREFIX_VEX_3A16 + 1) 982 #define PREFIX_VEX_3A18 (PREFIX_VEX_3A17 + 1) 983 #define PREFIX_VEX_3A19 (PREFIX_VEX_3A18 + 1) 984 #define PREFIX_VEX_3A20 (PREFIX_VEX_3A19 + 1) 985 #define PREFIX_VEX_3A21 (PREFIX_VEX_3A20 + 1) 986 #define PREFIX_VEX_3A22 (PREFIX_VEX_3A21 + 1) 987 #define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1) 988 #define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1) 989 #define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1) 990 #define PREFIX_VEX_3A44 (PREFIX_VEX_3A42 + 1) 991 #define PREFIX_VEX_3A4A (PREFIX_VEX_3A44 + 1) 992 #define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1) 993 #define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1) 994 #define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1) 995 #define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1) 996 #define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1) 997 #define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1) 998 #define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1) 999 #define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1) 1000 #define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1) 1001 #define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1) 1002 #define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1) 1003 #define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1) 1004 #define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1) 1005 #define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1) 1006 #define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1) 1007 #define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1) 1008 #define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1) 1009 #define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1) 1010 #define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1) 1011 #define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1) 1012 #define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1) 1013 #define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1) 1014 #define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1) 1015 #define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1) 1016 #define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1) 1017 #define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1) 1018 #define PREFIX_VEX_3ADF (PREFIX_VEX_3A7F + 1) 1019 1020 #define X86_64_06 0 1021 #define X86_64_07 (X86_64_06 + 1) 1022 #define X86_64_0D (X86_64_07 + 1) 1023 #define X86_64_16 (X86_64_0D + 1) 1024 #define X86_64_17 (X86_64_16 + 1) 1025 #define X86_64_1E (X86_64_17 + 1) 1026 #define X86_64_1F (X86_64_1E + 1) 1027 #define X86_64_27 (X86_64_1F + 1) 1028 #define X86_64_2F (X86_64_27 + 1) 1029 #define X86_64_37 (X86_64_2F + 1) 1030 #define X86_64_3F (X86_64_37 + 1) 1031 #define X86_64_60 (X86_64_3F + 1) 1032 #define X86_64_61 (X86_64_60 + 1) 1033 #define X86_64_62 (X86_64_61 + 1) 1034 #define X86_64_63 (X86_64_62 + 1) 1035 #define X86_64_6D (X86_64_63 + 1) 1036 #define X86_64_6F (X86_64_6D + 1) 1037 #define X86_64_9A (X86_64_6F + 1) 1038 #define X86_64_C4 (X86_64_9A + 1) 1039 #define X86_64_C5 (X86_64_C4 + 1) 1040 #define X86_64_CE (X86_64_C5 + 1) 1041 #define X86_64_D4 (X86_64_CE + 1) 1042 #define X86_64_D5 (X86_64_D4 + 1) 1043 #define X86_64_EA (X86_64_D5 + 1) 1044 #define X86_64_0F01_REG_0 (X86_64_EA + 1) 1045 #define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1) 1046 #define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1) 1047 #define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1) 1048 1049 #define THREE_BYTE_0F38 0 1050 #define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1) 1051 #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1) 1052 1053 #define VEX_0F 0 1054 #define VEX_0F38 (VEX_0F + 1) 1055 #define VEX_0F3A (VEX_0F38 + 1) 1056 1057 #define VEX_LEN_10_P_1 0 1058 #define VEX_LEN_10_P_3 (VEX_LEN_10_P_1 + 1) 1059 #define VEX_LEN_11_P_1 (VEX_LEN_10_P_3 + 1) 1060 #define VEX_LEN_11_P_3 (VEX_LEN_11_P_1 + 1) 1061 #define VEX_LEN_12_P_0_M_0 (VEX_LEN_11_P_3 + 1) 1062 #define VEX_LEN_12_P_0_M_1 (VEX_LEN_12_P_0_M_0 + 1) 1063 #define VEX_LEN_12_P_2 (VEX_LEN_12_P_0_M_1 + 1) 1064 #define VEX_LEN_13_M_0 (VEX_LEN_12_P_2 + 1) 1065 #define VEX_LEN_16_P_0_M_0 (VEX_LEN_13_M_0 + 1) 1066 #define VEX_LEN_16_P_0_M_1 (VEX_LEN_16_P_0_M_0 + 1) 1067 #define VEX_LEN_16_P_2 (VEX_LEN_16_P_0_M_1 + 1) 1068 #define VEX_LEN_17_M_0 (VEX_LEN_16_P_2 + 1) 1069 #define VEX_LEN_2A_P_1 (VEX_LEN_17_M_0 + 1) 1070 #define VEX_LEN_2A_P_3 (VEX_LEN_2A_P_1 + 1) 1071 #define VEX_LEN_2C_P_1 (VEX_LEN_2A_P_3 + 1) 1072 #define VEX_LEN_2C_P_3 (VEX_LEN_2C_P_1 + 1) 1073 #define VEX_LEN_2D_P_1 (VEX_LEN_2C_P_3 + 1) 1074 #define VEX_LEN_2D_P_3 (VEX_LEN_2D_P_1 + 1) 1075 #define VEX_LEN_2E_P_0 (VEX_LEN_2D_P_3 + 1) 1076 #define VEX_LEN_2E_P_2 (VEX_LEN_2E_P_0 + 1) 1077 #define VEX_LEN_2F_P_0 (VEX_LEN_2E_P_2 + 1) 1078 #define VEX_LEN_2F_P_2 (VEX_LEN_2F_P_0 + 1) 1079 #define VEX_LEN_51_P_1 (VEX_LEN_2F_P_2 + 1) 1080 #define VEX_LEN_51_P_3 (VEX_LEN_51_P_1 + 1) 1081 #define VEX_LEN_52_P_1 (VEX_LEN_51_P_3 + 1) 1082 #define VEX_LEN_53_P_1 (VEX_LEN_52_P_1 + 1) 1083 #define VEX_LEN_58_P_1 (VEX_LEN_53_P_1 + 1) 1084 #define VEX_LEN_58_P_3 (VEX_LEN_58_P_1 + 1) 1085 #define VEX_LEN_59_P_1 (VEX_LEN_58_P_3 + 1) 1086 #define VEX_LEN_59_P_3 (VEX_LEN_59_P_1 + 1) 1087 #define VEX_LEN_5A_P_1 (VEX_LEN_59_P_3 + 1) 1088 #define VEX_LEN_5A_P_3 (VEX_LEN_5A_P_1 + 1) 1089 #define VEX_LEN_5C_P_1 (VEX_LEN_5A_P_3 + 1) 1090 #define VEX_LEN_5C_P_3 (VEX_LEN_5C_P_1 + 1) 1091 #define VEX_LEN_5D_P_1 (VEX_LEN_5C_P_3 + 1) 1092 #define VEX_LEN_5D_P_3 (VEX_LEN_5D_P_1 + 1) 1093 #define VEX_LEN_5E_P_1 (VEX_LEN_5D_P_3 + 1) 1094 #define VEX_LEN_5E_P_3 (VEX_LEN_5E_P_1 + 1) 1095 #define VEX_LEN_5F_P_1 (VEX_LEN_5E_P_3 + 1) 1096 #define VEX_LEN_5F_P_3 (VEX_LEN_5F_P_1 + 1) 1097 #define VEX_LEN_60_P_2 (VEX_LEN_5F_P_3 + 1) 1098 #define VEX_LEN_61_P_2 (VEX_LEN_60_P_2 + 1) 1099 #define VEX_LEN_62_P_2 (VEX_LEN_61_P_2 + 1) 1100 #define VEX_LEN_63_P_2 (VEX_LEN_62_P_2 + 1) 1101 #define VEX_LEN_64_P_2 (VEX_LEN_63_P_2 + 1) 1102 #define VEX_LEN_65_P_2 (VEX_LEN_64_P_2 + 1) 1103 #define VEX_LEN_66_P_2 (VEX_LEN_65_P_2 + 1) 1104 #define VEX_LEN_67_P_2 (VEX_LEN_66_P_2 + 1) 1105 #define VEX_LEN_68_P_2 (VEX_LEN_67_P_2 + 1) 1106 #define VEX_LEN_69_P_2 (VEX_LEN_68_P_2 + 1) 1107 #define VEX_LEN_6A_P_2 (VEX_LEN_69_P_2 + 1) 1108 #define VEX_LEN_6B_P_2 (VEX_LEN_6A_P_2 + 1) 1109 #define VEX_LEN_6C_P_2 (VEX_LEN_6B_P_2 + 1) 1110 #define VEX_LEN_6D_P_2 (VEX_LEN_6C_P_2 + 1) 1111 #define VEX_LEN_6E_P_2 (VEX_LEN_6D_P_2 + 1) 1112 #define VEX_LEN_70_P_1 (VEX_LEN_6E_P_2 + 1) 1113 #define VEX_LEN_70_P_2 (VEX_LEN_70_P_1 + 1) 1114 #define VEX_LEN_70_P_3 (VEX_LEN_70_P_2 + 1) 1115 #define VEX_LEN_71_R_2_P_2 (VEX_LEN_70_P_3 + 1) 1116 #define VEX_LEN_71_R_4_P_2 (VEX_LEN_71_R_2_P_2 + 1) 1117 #define VEX_LEN_71_R_6_P_2 (VEX_LEN_71_R_4_P_2 + 1) 1118 #define VEX_LEN_72_R_2_P_2 (VEX_LEN_71_R_6_P_2 + 1) 1119 #define VEX_LEN_72_R_4_P_2 (VEX_LEN_72_R_2_P_2 + 1) 1120 #define VEX_LEN_72_R_6_P_2 (VEX_LEN_72_R_4_P_2 + 1) 1121 #define VEX_LEN_73_R_2_P_2 (VEX_LEN_72_R_6_P_2 + 1) 1122 #define VEX_LEN_73_R_3_P_2 (VEX_LEN_73_R_2_P_2 + 1) 1123 #define VEX_LEN_73_R_6_P_2 (VEX_LEN_73_R_3_P_2 + 1) 1124 #define VEX_LEN_73_R_7_P_2 (VEX_LEN_73_R_6_P_2 + 1) 1125 #define VEX_LEN_74_P_2 (VEX_LEN_73_R_7_P_2 + 1) 1126 #define VEX_LEN_75_P_2 (VEX_LEN_74_P_2 + 1) 1127 #define VEX_LEN_76_P_2 (VEX_LEN_75_P_2 + 1) 1128 #define VEX_LEN_7E_P_1 (VEX_LEN_76_P_2 + 1) 1129 #define VEX_LEN_7E_P_2 (VEX_LEN_7E_P_1 + 1) 1130 #define VEX_LEN_AE_R_2_M_0 (VEX_LEN_7E_P_2 + 1) 1131 #define VEX_LEN_AE_R_3_M_0 (VEX_LEN_AE_R_2_M_0 + 1) 1132 #define VEX_LEN_C2_P_1 (VEX_LEN_AE_R_3_M_0 + 1) 1133 #define VEX_LEN_C2_P_3 (VEX_LEN_C2_P_1 + 1) 1134 #define VEX_LEN_C4_P_2 (VEX_LEN_C2_P_3 + 1) 1135 #define VEX_LEN_C5_P_2 (VEX_LEN_C4_P_2 + 1) 1136 #define VEX_LEN_D1_P_2 (VEX_LEN_C5_P_2 + 1) 1137 #define VEX_LEN_D2_P_2 (VEX_LEN_D1_P_2 + 1) 1138 #define VEX_LEN_D3_P_2 (VEX_LEN_D2_P_2 + 1) 1139 #define VEX_LEN_D4_P_2 (VEX_LEN_D3_P_2 + 1) 1140 #define VEX_LEN_D5_P_2 (VEX_LEN_D4_P_2 + 1) 1141 #define VEX_LEN_D6_P_2 (VEX_LEN_D5_P_2 + 1) 1142 #define VEX_LEN_D7_P_2_M_1 (VEX_LEN_D6_P_2 + 1) 1143 #define VEX_LEN_D8_P_2 (VEX_LEN_D7_P_2_M_1 + 1) 1144 #define VEX_LEN_D9_P_2 (VEX_LEN_D8_P_2 + 1) 1145 #define VEX_LEN_DA_P_2 (VEX_LEN_D9_P_2 + 1) 1146 #define VEX_LEN_DB_P_2 (VEX_LEN_DA_P_2 + 1) 1147 #define VEX_LEN_DC_P_2 (VEX_LEN_DB_P_2 + 1) 1148 #define VEX_LEN_DD_P_2 (VEX_LEN_DC_P_2 + 1) 1149 #define VEX_LEN_DE_P_2 (VEX_LEN_DD_P_2 + 1) 1150 #define VEX_LEN_DF_P_2 (VEX_LEN_DE_P_2 + 1) 1151 #define VEX_LEN_E0_P_2 (VEX_LEN_DF_P_2 + 1) 1152 #define VEX_LEN_E1_P_2 (VEX_LEN_E0_P_2 + 1) 1153 #define VEX_LEN_E2_P_2 (VEX_LEN_E1_P_2 + 1) 1154 #define VEX_LEN_E3_P_2 (VEX_LEN_E2_P_2 + 1) 1155 #define VEX_LEN_E4_P_2 (VEX_LEN_E3_P_2 + 1) 1156 #define VEX_LEN_E5_P_2 (VEX_LEN_E4_P_2 + 1) 1157 #define VEX_LEN_E8_P_2 (VEX_LEN_E5_P_2 + 1) 1158 #define VEX_LEN_E9_P_2 (VEX_LEN_E8_P_2 + 1) 1159 #define VEX_LEN_EA_P_2 (VEX_LEN_E9_P_2 + 1) 1160 #define VEX_LEN_EB_P_2 (VEX_LEN_EA_P_2 + 1) 1161 #define VEX_LEN_EC_P_2 (VEX_LEN_EB_P_2 + 1) 1162 #define VEX_LEN_ED_P_2 (VEX_LEN_EC_P_2 + 1) 1163 #define VEX_LEN_EE_P_2 (VEX_LEN_ED_P_2 + 1) 1164 #define VEX_LEN_EF_P_2 (VEX_LEN_EE_P_2 + 1) 1165 #define VEX_LEN_F1_P_2 (VEX_LEN_EF_P_2 + 1) 1166 #define VEX_LEN_F2_P_2 (VEX_LEN_F1_P_2 + 1) 1167 #define VEX_LEN_F3_P_2 (VEX_LEN_F2_P_2 + 1) 1168 #define VEX_LEN_F4_P_2 (VEX_LEN_F3_P_2 + 1) 1169 #define VEX_LEN_F5_P_2 (VEX_LEN_F4_P_2 + 1) 1170 #define VEX_LEN_F6_P_2 (VEX_LEN_F5_P_2 + 1) 1171 #define VEX_LEN_F7_P_2 (VEX_LEN_F6_P_2 + 1) 1172 #define VEX_LEN_F8_P_2 (VEX_LEN_F7_P_2 + 1) 1173 #define VEX_LEN_F9_P_2 (VEX_LEN_F8_P_2 + 1) 1174 #define VEX_LEN_FA_P_2 (VEX_LEN_F9_P_2 + 1) 1175 #define VEX_LEN_FB_P_2 (VEX_LEN_FA_P_2 + 1) 1176 #define VEX_LEN_FC_P_2 (VEX_LEN_FB_P_2 + 1) 1177 #define VEX_LEN_FD_P_2 (VEX_LEN_FC_P_2 + 1) 1178 #define VEX_LEN_FE_P_2 (VEX_LEN_FD_P_2 + 1) 1179 #define VEX_LEN_3800_P_2 (VEX_LEN_FE_P_2 + 1) 1180 #define VEX_LEN_3801_P_2 (VEX_LEN_3800_P_2 + 1) 1181 #define VEX_LEN_3802_P_2 (VEX_LEN_3801_P_2 + 1) 1182 #define VEX_LEN_3803_P_2 (VEX_LEN_3802_P_2 + 1) 1183 #define VEX_LEN_3804_P_2 (VEX_LEN_3803_P_2 + 1) 1184 #define VEX_LEN_3805_P_2 (VEX_LEN_3804_P_2 + 1) 1185 #define VEX_LEN_3806_P_2 (VEX_LEN_3805_P_2 + 1) 1186 #define VEX_LEN_3807_P_2 (VEX_LEN_3806_P_2 + 1) 1187 #define VEX_LEN_3808_P_2 (VEX_LEN_3807_P_2 + 1) 1188 #define VEX_LEN_3809_P_2 (VEX_LEN_3808_P_2 + 1) 1189 #define VEX_LEN_380A_P_2 (VEX_LEN_3809_P_2 + 1) 1190 #define VEX_LEN_380B_P_2 (VEX_LEN_380A_P_2 + 1) 1191 #define VEX_LEN_3819_P_2_M_0 (VEX_LEN_380B_P_2 + 1) 1192 #define VEX_LEN_381A_P_2_M_0 (VEX_LEN_3819_P_2_M_0 + 1) 1193 #define VEX_LEN_381C_P_2 (VEX_LEN_381A_P_2_M_0 + 1) 1194 #define VEX_LEN_381D_P_2 (VEX_LEN_381C_P_2 + 1) 1195 #define VEX_LEN_381E_P_2 (VEX_LEN_381D_P_2 + 1) 1196 #define VEX_LEN_3820_P_2 (VEX_LEN_381E_P_2 + 1) 1197 #define VEX_LEN_3821_P_2 (VEX_LEN_3820_P_2 + 1) 1198 #define VEX_LEN_3822_P_2 (VEX_LEN_3821_P_2 + 1) 1199 #define VEX_LEN_3823_P_2 (VEX_LEN_3822_P_2 + 1) 1200 #define VEX_LEN_3824_P_2 (VEX_LEN_3823_P_2 + 1) 1201 #define VEX_LEN_3825_P_2 (VEX_LEN_3824_P_2 + 1) 1202 #define VEX_LEN_3828_P_2 (VEX_LEN_3825_P_2 + 1) 1203 #define VEX_LEN_3829_P_2 (VEX_LEN_3828_P_2 + 1) 1204 #define VEX_LEN_382A_P_2_M_0 (VEX_LEN_3829_P_2 + 1) 1205 #define VEX_LEN_382B_P_2 (VEX_LEN_382A_P_2_M_0 + 1) 1206 #define VEX_LEN_3830_P_2 (VEX_LEN_382B_P_2 + 1) 1207 #define VEX_LEN_3831_P_2 (VEX_LEN_3830_P_2 + 1) 1208 #define VEX_LEN_3832_P_2 (VEX_LEN_3831_P_2 + 1) 1209 #define VEX_LEN_3833_P_2 (VEX_LEN_3832_P_2 + 1) 1210 #define VEX_LEN_3834_P_2 (VEX_LEN_3833_P_2 + 1) 1211 #define VEX_LEN_3835_P_2 (VEX_LEN_3834_P_2 + 1) 1212 #define VEX_LEN_3837_P_2 (VEX_LEN_3835_P_2 + 1) 1213 #define VEX_LEN_3838_P_2 (VEX_LEN_3837_P_2 + 1) 1214 #define VEX_LEN_3839_P_2 (VEX_LEN_3838_P_2 + 1) 1215 #define VEX_LEN_383A_P_2 (VEX_LEN_3839_P_2 + 1) 1216 #define VEX_LEN_383B_P_2 (VEX_LEN_383A_P_2 + 1) 1217 #define VEX_LEN_383C_P_2 (VEX_LEN_383B_P_2 + 1) 1218 #define VEX_LEN_383D_P_2 (VEX_LEN_383C_P_2 + 1) 1219 #define VEX_LEN_383E_P_2 (VEX_LEN_383D_P_2 + 1) 1220 #define VEX_LEN_383F_P_2 (VEX_LEN_383E_P_2 + 1) 1221 #define VEX_LEN_3840_P_2 (VEX_LEN_383F_P_2 + 1) 1222 #define VEX_LEN_3841_P_2 (VEX_LEN_3840_P_2 + 1) 1223 #define VEX_LEN_38DB_P_2 (VEX_LEN_3841_P_2 + 1) 1224 #define VEX_LEN_38DC_P_2 (VEX_LEN_38DB_P_2 + 1) 1225 #define VEX_LEN_38DD_P_2 (VEX_LEN_38DC_P_2 + 1) 1226 #define VEX_LEN_38DE_P_2 (VEX_LEN_38DD_P_2 + 1) 1227 #define VEX_LEN_38DF_P_2 (VEX_LEN_38DE_P_2 + 1) 1228 #define VEX_LEN_3A06_P_2 (VEX_LEN_38DF_P_2 + 1) 1229 #define VEX_LEN_3A0A_P_2 (VEX_LEN_3A06_P_2 + 1) 1230 #define VEX_LEN_3A0B_P_2 (VEX_LEN_3A0A_P_2 + 1) 1231 #define VEX_LEN_3A0E_P_2 (VEX_LEN_3A0B_P_2 + 1) 1232 #define VEX_LEN_3A0F_P_2 (VEX_LEN_3A0E_P_2 + 1) 1233 #define VEX_LEN_3A14_P_2 (VEX_LEN_3A0F_P_2 + 1) 1234 #define VEX_LEN_3A15_P_2 (VEX_LEN_3A14_P_2 + 1) 1235 #define VEX_LEN_3A16_P_2 (VEX_LEN_3A15_P_2 + 1) 1236 #define VEX_LEN_3A17_P_2 (VEX_LEN_3A16_P_2 + 1) 1237 #define VEX_LEN_3A18_P_2 (VEX_LEN_3A17_P_2 + 1) 1238 #define VEX_LEN_3A19_P_2 (VEX_LEN_3A18_P_2 + 1) 1239 #define VEX_LEN_3A20_P_2 (VEX_LEN_3A19_P_2 + 1) 1240 #define VEX_LEN_3A21_P_2 (VEX_LEN_3A20_P_2 + 1) 1241 #define VEX_LEN_3A22_P_2 (VEX_LEN_3A21_P_2 + 1) 1242 #define VEX_LEN_3A41_P_2 (VEX_LEN_3A22_P_2 + 1) 1243 #define VEX_LEN_3A42_P_2 (VEX_LEN_3A41_P_2 + 1) 1244 #define VEX_LEN_3A44_P_2 (VEX_LEN_3A42_P_2 + 1) 1245 #define VEX_LEN_3A4C_P_2 (VEX_LEN_3A44_P_2 + 1) 1246 #define VEX_LEN_3A60_P_2 (VEX_LEN_3A4C_P_2 + 1) 1247 #define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1) 1248 #define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1) 1249 #define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1) 1250 #define VEX_LEN_3A6A_P_2 (VEX_LEN_3A63_P_2 + 1) 1251 #define VEX_LEN_3A6B_P_2 (VEX_LEN_3A6A_P_2 + 1) 1252 #define VEX_LEN_3A6E_P_2 (VEX_LEN_3A6B_P_2 + 1) 1253 #define VEX_LEN_3A6F_P_2 (VEX_LEN_3A6E_P_2 + 1) 1254 #define VEX_LEN_3A7A_P_2 (VEX_LEN_3A6F_P_2 + 1) 1255 #define VEX_LEN_3A7B_P_2 (VEX_LEN_3A7A_P_2 + 1) 1256 #define VEX_LEN_3A7E_P_2 (VEX_LEN_3A7B_P_2 + 1) 1257 #define VEX_LEN_3A7F_P_2 (VEX_LEN_3A7E_P_2 + 1) 1258 #define VEX_LEN_3ADF_P_2 (VEX_LEN_3A7F_P_2 + 1) 1259 1260 typedef void (*op_rtn) (int bytemode, int sizeflag); 1261 1262 struct dis386 { 1263 const char *name; 1264 struct 1265 { 1266 op_rtn rtn; 1267 int bytemode; 1268 } op[MAX_OPERANDS]; 1269 }; 1270 1271 /* Upper case letters in the instruction names here are macros. 1272 'A' => print 'b' if no register operands or suffix_always is true 1273 'B' => print 'b' if suffix_always is true 1274 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand 1275 size prefix 1276 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if 1277 suffix_always is true 1278 'E' => print 'e' if 32-bit form of jcxz 1279 'F' => print 'w' or 'l' depending on address size prefix (loop insns) 1280 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) 1281 'H' => print ",pt" or ",pn" branch hint 1282 'I' => honor following macro letter even in Intel mode (implemented only 1283 for some of the macro letters) 1284 'J' => print 'l' 1285 'K' => print 'd' or 'q' if rex prefix is present. 1286 'L' => print 'l' if suffix_always is true 1287 'M' => print 'r' if intel_mnemonic is false. 1288 'N' => print 'n' if instruction has no wait "prefix" 1289 'O' => print 'd' or 'o' (or 'q' in Intel mode) 1290 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, 1291 or suffix_always is true. print 'q' if rex prefix is present. 1292 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always 1293 is true 1294 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) 1295 'S' => print 'w', 'l' or 'q' if suffix_always is true 1296 'T' => print 'q' in 64bit mode and behave as 'P' otherwise 1297 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise 1298 'V' => print 'q' in 64bit mode and behave as 'S' otherwise 1299 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 1300 'X' => print 's', 'd' depending on data16 prefix (for XMM) 1301 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and 1302 suffix_always is true. 1303 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise 1304 '!' => change condition from true to false or from false to true. 1305 '%' => add 1 upper case letter to the macro. 1306 1307 2 upper case letter macros: 1308 "XY" => print 'x' or 'y' if no register operands or suffix_always 1309 is true. 1310 'XW' => print 's', 'd' depending on the VEX.W bit (for FMA) 1311 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand 1312 or suffix_always is true 1313 1314 Many of the above letters print nothing in Intel mode. See "putop" 1315 for the details. 1316 1317 Braces '{' and '}', and vertical bars '|', indicate alternative 1318 mnemonic strings for AT&T and Intel. */ 1319 1320 static const struct dis386 dis386[] = { 1321 /* 00 */ 1322 { "addB", { Eb, Gb } }, 1323 { "addS", { Ev, Gv } }, 1324 { "addB", { Gb, EbS } }, 1325 { "addS", { Gv, EvS } }, 1326 { "addB", { AL, Ib } }, 1327 { "addS", { eAX, Iv } }, 1328 { X86_64_TABLE (X86_64_06) }, 1329 { X86_64_TABLE (X86_64_07) }, 1330 /* 08 */ 1331 { "orB", { Eb, Gb } }, 1332 { "orS", { Ev, Gv } }, 1333 { "orB", { Gb, EbS } }, 1334 { "orS", { Gv, EvS } }, 1335 { "orB", { AL, Ib } }, 1336 { "orS", { eAX, Iv } }, 1337 { X86_64_TABLE (X86_64_0D) }, 1338 { "(bad)", { XX } }, /* 0x0f extended opcode escape */ 1339 /* 10 */ 1340 { "adcB", { Eb, Gb } }, 1341 { "adcS", { Ev, Gv } }, 1342 { "adcB", { Gb, EbS } }, 1343 { "adcS", { Gv, EvS } }, 1344 { "adcB", { AL, Ib } }, 1345 { "adcS", { eAX, Iv } }, 1346 { X86_64_TABLE (X86_64_16) }, 1347 { X86_64_TABLE (X86_64_17) }, 1348 /* 18 */ 1349 { "sbbB", { Eb, Gb } }, 1350 { "sbbS", { Ev, Gv } }, 1351 { "sbbB", { Gb, EbS } }, 1352 { "sbbS", { Gv, EvS } }, 1353 { "sbbB", { AL, Ib } }, 1354 { "sbbS", { eAX, Iv } }, 1355 { X86_64_TABLE (X86_64_1E) }, 1356 { X86_64_TABLE (X86_64_1F) }, 1357 /* 20 */ 1358 { "andB", { Eb, Gb } }, 1359 { "andS", { Ev, Gv } }, 1360 { "andB", { Gb, EbS } }, 1361 { "andS", { Gv, EvS } }, 1362 { "andB", { AL, Ib } }, 1363 { "andS", { eAX, Iv } }, 1364 { "(bad)", { XX } }, /* SEG ES prefix */ 1365 { X86_64_TABLE (X86_64_27) }, 1366 /* 28 */ 1367 { "subB", { Eb, Gb } }, 1368 { "subS", { Ev, Gv } }, 1369 { "subB", { Gb, EbS } }, 1370 { "subS", { Gv, EvS } }, 1371 { "subB", { AL, Ib } }, 1372 { "subS", { eAX, Iv } }, 1373 { "(bad)", { XX } }, /* SEG CS prefix */ 1374 { X86_64_TABLE (X86_64_2F) }, 1375 /* 30 */ 1376 { "xorB", { Eb, Gb } }, 1377 { "xorS", { Ev, Gv } }, 1378 { "xorB", { Gb, EbS } }, 1379 { "xorS", { Gv, EvS } }, 1380 { "xorB", { AL, Ib } }, 1381 { "xorS", { eAX, Iv } }, 1382 { "(bad)", { XX } }, /* SEG SS prefix */ 1383 { X86_64_TABLE (X86_64_37) }, 1384 /* 38 */ 1385 { "cmpB", { Eb, Gb } }, 1386 { "cmpS", { Ev, Gv } }, 1387 { "cmpB", { Gb, EbS } }, 1388 { "cmpS", { Gv, EvS } }, 1389 { "cmpB", { AL, Ib } }, 1390 { "cmpS", { eAX, Iv } }, 1391 { "(bad)", { XX } }, /* SEG DS prefix */ 1392 { X86_64_TABLE (X86_64_3F) }, 1393 /* 40 */ 1394 { "inc{S|}", { RMeAX } }, 1395 { "inc{S|}", { RMeCX } }, 1396 { "inc{S|}", { RMeDX } }, 1397 { "inc{S|}", { RMeBX } }, 1398 { "inc{S|}", { RMeSP } }, 1399 { "inc{S|}", { RMeBP } }, 1400 { "inc{S|}", { RMeSI } }, 1401 { "inc{S|}", { RMeDI } }, 1402 /* 48 */ 1403 { "dec{S|}", { RMeAX } }, 1404 { "dec{S|}", { RMeCX } }, 1405 { "dec{S|}", { RMeDX } }, 1406 { "dec{S|}", { RMeBX } }, 1407 { "dec{S|}", { RMeSP } }, 1408 { "dec{S|}", { RMeBP } }, 1409 { "dec{S|}", { RMeSI } }, 1410 { "dec{S|}", { RMeDI } }, 1411 /* 50 */ 1412 { "pushV", { RMrAX } }, 1413 { "pushV", { RMrCX } }, 1414 { "pushV", { RMrDX } }, 1415 { "pushV", { RMrBX } }, 1416 { "pushV", { RMrSP } }, 1417 { "pushV", { RMrBP } }, 1418 { "pushV", { RMrSI } }, 1419 { "pushV", { RMrDI } }, 1420 /* 58 */ 1421 { "popV", { RMrAX } }, 1422 { "popV", { RMrCX } }, 1423 { "popV", { RMrDX } }, 1424 { "popV", { RMrBX } }, 1425 { "popV", { RMrSP } }, 1426 { "popV", { RMrBP } }, 1427 { "popV", { RMrSI } }, 1428 { "popV", { RMrDI } }, 1429 /* 60 */ 1430 { X86_64_TABLE (X86_64_60) }, 1431 { X86_64_TABLE (X86_64_61) }, 1432 { X86_64_TABLE (X86_64_62) }, 1433 { X86_64_TABLE (X86_64_63) }, 1434 { "(bad)", { XX } }, /* seg fs */ 1435 { "(bad)", { XX } }, /* seg gs */ 1436 { "(bad)", { XX } }, /* op size prefix */ 1437 { "(bad)", { XX } }, /* adr size prefix */ 1438 /* 68 */ 1439 { "pushT", { Iq } }, 1440 { "imulS", { Gv, Ev, Iv } }, 1441 { "pushT", { sIb } }, 1442 { "imulS", { Gv, Ev, sIb } }, 1443 { "ins{b|}", { Ybr, indirDX } }, 1444 { X86_64_TABLE (X86_64_6D) }, 1445 { "outs{b|}", { indirDXr, Xb } }, 1446 { X86_64_TABLE (X86_64_6F) }, 1447 /* 70 */ 1448 { "joH", { Jb, XX, cond_jump_flag } }, 1449 { "jnoH", { Jb, XX, cond_jump_flag } }, 1450 { "jbH", { Jb, XX, cond_jump_flag } }, 1451 { "jaeH", { Jb, XX, cond_jump_flag } }, 1452 { "jeH", { Jb, XX, cond_jump_flag } }, 1453 { "jneH", { Jb, XX, cond_jump_flag } }, 1454 { "jbeH", { Jb, XX, cond_jump_flag } }, 1455 { "jaH", { Jb, XX, cond_jump_flag } }, 1456 /* 78 */ 1457 { "jsH", { Jb, XX, cond_jump_flag } }, 1458 { "jnsH", { Jb, XX, cond_jump_flag } }, 1459 { "jpH", { Jb, XX, cond_jump_flag } }, 1460 { "jnpH", { Jb, XX, cond_jump_flag } }, 1461 { "jlH", { Jb, XX, cond_jump_flag } }, 1462 { "jgeH", { Jb, XX, cond_jump_flag } }, 1463 { "jleH", { Jb, XX, cond_jump_flag } }, 1464 { "jgH", { Jb, XX, cond_jump_flag } }, 1465 /* 80 */ 1466 { REG_TABLE (REG_80) }, 1467 { REG_TABLE (REG_81) }, 1468 { "(bad)", { XX } }, 1469 { REG_TABLE (REG_82) }, 1470 { "testB", { Eb, Gb } }, 1471 { "testS", { Ev, Gv } }, 1472 { "xchgB", { Eb, Gb } }, 1473 { "xchgS", { Ev, Gv } }, 1474 /* 88 */ 1475 { "movB", { Eb, Gb } }, 1476 { "movS", { Ev, Gv } }, 1477 { "movB", { Gb, EbS } }, 1478 { "movS", { Gv, EvS } }, 1479 { "movD", { Sv, Sw } }, 1480 { MOD_TABLE (MOD_8D) }, 1481 { "movD", { Sw, Sv } }, 1482 { REG_TABLE (REG_8F) }, 1483 /* 90 */ 1484 { PREFIX_TABLE (PREFIX_90) }, 1485 { "xchgS", { RMeCX, eAX } }, 1486 { "xchgS", { RMeDX, eAX } }, 1487 { "xchgS", { RMeBX, eAX } }, 1488 { "xchgS", { RMeSP, eAX } }, 1489 { "xchgS", { RMeBP, eAX } }, 1490 { "xchgS", { RMeSI, eAX } }, 1491 { "xchgS", { RMeDI, eAX } }, 1492 /* 98 */ 1493 { "cW{t|}R", { XX } }, 1494 { "cR{t|}O", { XX } }, 1495 { X86_64_TABLE (X86_64_9A) }, 1496 { "(bad)", { XX } }, /* fwait */ 1497 { "pushfT", { XX } }, 1498 { "popfT", { XX } }, 1499 { "sahf", { XX } }, 1500 { "lahf", { XX } }, 1501 /* a0 */ 1502 { "movB", { AL, Ob } }, 1503 { "movS", { eAX, Ov } }, 1504 { "movB", { Ob, AL } }, 1505 { "movS", { Ov, eAX } }, 1506 { "movs{b|}", { Ybr, Xb } }, 1507 { "movs{R|}", { Yvr, Xv } }, 1508 { "cmps{b|}", { Xb, Yb } }, 1509 { "cmps{R|}", { Xv, Yv } }, 1510 /* a8 */ 1511 { "testB", { AL, Ib } }, 1512 { "testS", { eAX, Iv } }, 1513 { "stosB", { Ybr, AL } }, 1514 { "stosS", { Yvr, eAX } }, 1515 { "lodsB", { ALr, Xb } }, 1516 { "lodsS", { eAXr, Xv } }, 1517 { "scasB", { AL, Yb } }, 1518 { "scasS", { eAX, Yv } }, 1519 /* b0 */ 1520 { "movB", { RMAL, Ib } }, 1521 { "movB", { RMCL, Ib } }, 1522 { "movB", { RMDL, Ib } }, 1523 { "movB", { RMBL, Ib } }, 1524 { "movB", { RMAH, Ib } }, 1525 { "movB", { RMCH, Ib } }, 1526 { "movB", { RMDH, Ib } }, 1527 { "movB", { RMBH, Ib } }, 1528 /* b8 */ 1529 { "movS", { RMeAX, Iv64 } }, 1530 { "movS", { RMeCX, Iv64 } }, 1531 { "movS", { RMeDX, Iv64 } }, 1532 { "movS", { RMeBX, Iv64 } }, 1533 { "movS", { RMeSP, Iv64 } }, 1534 { "movS", { RMeBP, Iv64 } }, 1535 { "movS", { RMeSI, Iv64 } }, 1536 { "movS", { RMeDI, Iv64 } }, 1537 /* c0 */ 1538 { REG_TABLE (REG_C0) }, 1539 { REG_TABLE (REG_C1) }, 1540 { "retT", { Iw } }, 1541 { "retT", { XX } }, 1542 { X86_64_TABLE (X86_64_C4) }, 1543 { X86_64_TABLE (X86_64_C5) }, 1544 { REG_TABLE (REG_C6) }, 1545 { REG_TABLE (REG_C7) }, 1546 /* c8 */ 1547 { "enterT", { Iw, Ib } }, 1548 { "leaveT", { XX } }, 1549 { "Jret{|f}P", { Iw } }, 1550 { "Jret{|f}P", { XX } }, 1551 { "int3", { XX } }, 1552 { "int", { Ib } }, 1553 { X86_64_TABLE (X86_64_CE) }, 1554 { "iretP", { XX } }, 1555 /* d0 */ 1556 { REG_TABLE (REG_D0) }, 1557 { REG_TABLE (REG_D1) }, 1558 { REG_TABLE (REG_D2) }, 1559 { REG_TABLE (REG_D3) }, 1560 { X86_64_TABLE (X86_64_D4) }, 1561 { X86_64_TABLE (X86_64_D5) }, 1562 { "(bad)", { XX } }, 1563 { "xlat", { DSBX } }, 1564 /* d8 */ 1565 { FLOAT }, 1566 { FLOAT }, 1567 { FLOAT }, 1568 { FLOAT }, 1569 { FLOAT }, 1570 { FLOAT }, 1571 { FLOAT }, 1572 { FLOAT }, 1573 /* e0 */ 1574 { "loopneFH", { Jb, XX, loop_jcxz_flag } }, 1575 { "loopeFH", { Jb, XX, loop_jcxz_flag } }, 1576 { "loopFH", { Jb, XX, loop_jcxz_flag } }, 1577 { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, 1578 { "inB", { AL, Ib } }, 1579 { "inG", { zAX, Ib } }, 1580 { "outB", { Ib, AL } }, 1581 { "outG", { Ib, zAX } }, 1582 /* e8 */ 1583 { "callT", { Jv } }, 1584 { "jmpT", { Jv } }, 1585 { X86_64_TABLE (X86_64_EA) }, 1586 { "jmp", { Jb } }, 1587 { "inB", { AL, indirDX } }, 1588 { "inG", { zAX, indirDX } }, 1589 { "outB", { indirDX, AL } }, 1590 { "outG", { indirDX, zAX } }, 1591 /* f0 */ 1592 { "(bad)", { XX } }, /* lock prefix */ 1593 { "icebp", { XX } }, 1594 { "(bad)", { XX } }, /* repne */ 1595 { "(bad)", { XX } }, /* repz */ 1596 { "hlt", { XX } }, 1597 { "cmc", { XX } }, 1598 { REG_TABLE (REG_F6) }, 1599 { REG_TABLE (REG_F7) }, 1600 /* f8 */ 1601 { "clc", { XX } }, 1602 { "stc", { XX } }, 1603 { "cli", { XX } }, 1604 { "sti", { XX } }, 1605 { "cld", { XX } }, 1606 { "std", { XX } }, 1607 { REG_TABLE (REG_FE) }, 1608 { REG_TABLE (REG_FF) }, 1609 }; 1610 1611 static const struct dis386 dis386_twobyte[] = { 1612 /* 00 */ 1613 { REG_TABLE (REG_0F00 ) }, 1614 { REG_TABLE (REG_0F01 ) }, 1615 { "larS", { Gv, Ew } }, 1616 { "lslS", { Gv, Ew } }, 1617 { "(bad)", { XX } }, 1618 { "syscall", { XX } }, 1619 { "clts", { XX } }, 1620 { "sysretP", { XX } }, 1621 /* 08 */ 1622 { "invd", { XX } }, 1623 { "wbinvd", { XX } }, 1624 { "(bad)", { XX } }, 1625 { "ud2a", { XX } }, 1626 { "(bad)", { XX } }, 1627 { REG_TABLE (REG_0F0D) }, 1628 { "femms", { XX } }, 1629 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ 1630 /* 10 */ 1631 { PREFIX_TABLE (PREFIX_0F10) }, 1632 { PREFIX_TABLE (PREFIX_0F11) }, 1633 { PREFIX_TABLE (PREFIX_0F12) }, 1634 { MOD_TABLE (MOD_0F13) }, 1635 { "unpcklpX", { XM, EXx } }, 1636 { "unpckhpX", { XM, EXx } }, 1637 { PREFIX_TABLE (PREFIX_0F16) }, 1638 { MOD_TABLE (MOD_0F17) }, 1639 /* 18 */ 1640 { REG_TABLE (REG_0F18) }, 1641 { "nopQ", { Ev } }, 1642 { "nopQ", { Ev } }, 1643 { "nopQ", { Ev } }, 1644 { "nopQ", { Ev } }, 1645 { "nopQ", { Ev } }, 1646 { "nopQ", { Ev } }, 1647 { "nopQ", { Ev } }, 1648 /* 20 */ 1649 { MOD_TABLE (MOD_0F20) }, 1650 { MOD_TABLE (MOD_0F21) }, 1651 { MOD_TABLE (MOD_0F22) }, 1652 { MOD_TABLE (MOD_0F23) }, 1653 { MOD_TABLE (MOD_0F24) }, 1654 { "(bad)", { XX } }, 1655 { MOD_TABLE (MOD_0F26) }, 1656 { "(bad)", { XX } }, 1657 /* 28 */ 1658 { "movapX", { XM, EXx } }, 1659 { "movapX", { EXxS, XM } }, 1660 { PREFIX_TABLE (PREFIX_0F2A) }, 1661 { PREFIX_TABLE (PREFIX_0F2B) }, 1662 { PREFIX_TABLE (PREFIX_0F2C) }, 1663 { PREFIX_TABLE (PREFIX_0F2D) }, 1664 { PREFIX_TABLE (PREFIX_0F2E) }, 1665 { PREFIX_TABLE (PREFIX_0F2F) }, 1666 /* 30 */ 1667 { "wrmsr", { XX } }, 1668 { "rdtsc", { XX } }, 1669 { "rdmsr", { XX } }, 1670 { "rdpmc", { XX } }, 1671 { "sysenter", { XX } }, 1672 { "sysexit", { XX } }, 1673 { "(bad)", { XX } }, 1674 { "getsec", { XX } }, 1675 /* 38 */ 1676 { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, 1677 { "(bad)", { XX } }, 1678 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, 1679 { "(bad)", { XX } }, 1680 { "(bad)", { XX } }, 1681 { "(bad)", { XX } }, 1682 { "(bad)", { XX } }, 1683 { "(bad)", { XX } }, 1684 /* 40 */ 1685 { "cmovoS", { Gv, Ev } }, 1686 { "cmovnoS", { Gv, Ev } }, 1687 { "cmovbS", { Gv, Ev } }, 1688 { "cmovaeS", { Gv, Ev } }, 1689 { "cmoveS", { Gv, Ev } }, 1690 { "cmovneS", { Gv, Ev } }, 1691 { "cmovbeS", { Gv, Ev } }, 1692 { "cmovaS", { Gv, Ev } }, 1693 /* 48 */ 1694 { "cmovsS", { Gv, Ev } }, 1695 { "cmovnsS", { Gv, Ev } }, 1696 { "cmovpS", { Gv, Ev } }, 1697 { "cmovnpS", { Gv, Ev } }, 1698 { "cmovlS", { Gv, Ev } }, 1699 { "cmovgeS", { Gv, Ev } }, 1700 { "cmovleS", { Gv, Ev } }, 1701 { "cmovgS", { Gv, Ev } }, 1702 /* 50 */ 1703 { MOD_TABLE (MOD_0F51) }, 1704 { PREFIX_TABLE (PREFIX_0F51) }, 1705 { PREFIX_TABLE (PREFIX_0F52) }, 1706 { PREFIX_TABLE (PREFIX_0F53) }, 1707 { "andpX", { XM, EXx } }, 1708 { "andnpX", { XM, EXx } }, 1709 { "orpX", { XM, EXx } }, 1710 { "xorpX", { XM, EXx } }, 1711 /* 58 */ 1712 { PREFIX_TABLE (PREFIX_0F58) }, 1713 { PREFIX_TABLE (PREFIX_0F59) }, 1714 { PREFIX_TABLE (PREFIX_0F5A) }, 1715 { PREFIX_TABLE (PREFIX_0F5B) }, 1716 { PREFIX_TABLE (PREFIX_0F5C) }, 1717 { PREFIX_TABLE (PREFIX_0F5D) }, 1718 { PREFIX_TABLE (PREFIX_0F5E) }, 1719 { PREFIX_TABLE (PREFIX_0F5F) }, 1720 /* 60 */ 1721 { PREFIX_TABLE (PREFIX_0F60) }, 1722 { PREFIX_TABLE (PREFIX_0F61) }, 1723 { PREFIX_TABLE (PREFIX_0F62) }, 1724 { "packsswb", { MX, EM } }, 1725 { "pcmpgtb", { MX, EM } }, 1726 { "pcmpgtw", { MX, EM } }, 1727 { "pcmpgtd", { MX, EM } }, 1728 { "packuswb", { MX, EM } }, 1729 /* 68 */ 1730 { "punpckhbw", { MX, EM } }, 1731 { "punpckhwd", { MX, EM } }, 1732 { "punpckhdq", { MX, EM } }, 1733 { "packssdw", { MX, EM } }, 1734 { PREFIX_TABLE (PREFIX_0F6C) }, 1735 { PREFIX_TABLE (PREFIX_0F6D) }, 1736 { "movK", { MX, Edq } }, 1737 { PREFIX_TABLE (PREFIX_0F6F) }, 1738 /* 70 */ 1739 { PREFIX_TABLE (PREFIX_0F70) }, 1740 { REG_TABLE (REG_0F71) }, 1741 { REG_TABLE (REG_0F72) }, 1742 { REG_TABLE (REG_0F73) }, 1743 { "pcmpeqb", { MX, EM } }, 1744 { "pcmpeqw", { MX, EM } }, 1745 { "pcmpeqd", { MX, EM } }, 1746 { "emms", { XX } }, 1747 /* 78 */ 1748 { PREFIX_TABLE (PREFIX_0F78) }, 1749 { PREFIX_TABLE (PREFIX_0F79) }, 1750 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, 1751 { "(bad)", { XX } }, 1752 { PREFIX_TABLE (PREFIX_0F7C) }, 1753 { PREFIX_TABLE (PREFIX_0F7D) }, 1754 { PREFIX_TABLE (PREFIX_0F7E) }, 1755 { PREFIX_TABLE (PREFIX_0F7F) }, 1756 /* 80 */ 1757 { "joH", { Jv, XX, cond_jump_flag } }, 1758 { "jnoH", { Jv, XX, cond_jump_flag } }, 1759 { "jbH", { Jv, XX, cond_jump_flag } }, 1760 { "jaeH", { Jv, XX, cond_jump_flag } }, 1761 { "jeH", { Jv, XX, cond_jump_flag } }, 1762 { "jneH", { Jv, XX, cond_jump_flag } }, 1763 { "jbeH", { Jv, XX, cond_jump_flag } }, 1764 { "jaH", { Jv, XX, cond_jump_flag } }, 1765 /* 88 */ 1766 { "jsH", { Jv, XX, cond_jump_flag } }, 1767 { "jnsH", { Jv, XX, cond_jump_flag } }, 1768 { "jpH", { Jv, XX, cond_jump_flag } }, 1769 { "jnpH", { Jv, XX, cond_jump_flag } }, 1770 { "jlH", { Jv, XX, cond_jump_flag } }, 1771 { "jgeH", { Jv, XX, cond_jump_flag } }, 1772 { "jleH", { Jv, XX, cond_jump_flag } }, 1773 { "jgH", { Jv, XX, cond_jump_flag } }, 1774 /* 90 */ 1775 { "seto", { Eb } }, 1776 { "setno", { Eb } }, 1777 { "setb", { Eb } }, 1778 { "setae", { Eb } }, 1779 { "sete", { Eb } }, 1780 { "setne", { Eb } }, 1781 { "setbe", { Eb } }, 1782 { "seta", { Eb } }, 1783 /* 98 */ 1784 { "sets", { Eb } }, 1785 { "setns", { Eb } }, 1786 { "setp", { Eb } }, 1787 { "setnp", { Eb } }, 1788 { "setl", { Eb } }, 1789 { "setge", { Eb } }, 1790 { "setle", { Eb } }, 1791 { "setg", { Eb } }, 1792 /* a0 */ 1793 { "pushT", { fs } }, 1794 { "popT", { fs } }, 1795 { "cpuid", { XX } }, 1796 { "btS", { Ev, Gv } }, 1797 { "shldS", { Ev, Gv, Ib } }, 1798 { "shldS", { Ev, Gv, CL } }, 1799 { REG_TABLE (REG_0FA6) }, 1800 { REG_TABLE (REG_0FA7) }, 1801 /* a8 */ 1802 { "pushT", { gs } }, 1803 { "popT", { gs } }, 1804 { "rsm", { XX } }, 1805 { "btsS", { Ev, Gv } }, 1806 { "shrdS", { Ev, Gv, Ib } }, 1807 { "shrdS", { Ev, Gv, CL } }, 1808 { REG_TABLE (REG_0FAE) }, 1809 { "imulS", { Gv, Ev } }, 1810 /* b0 */ 1811 { "cmpxchgB", { Eb, Gb } }, 1812 { "cmpxchgS", { Ev, Gv } }, 1813 { MOD_TABLE (MOD_0FB2) }, 1814 { "btrS", { Ev, Gv } }, 1815 { MOD_TABLE (MOD_0FB4) }, 1816 { MOD_TABLE (MOD_0FB5) }, 1817 { "movz{bR|x}", { Gv, Eb } }, 1818 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ 1819 /* b8 */ 1820 { PREFIX_TABLE (PREFIX_0FB8) }, 1821 { "ud2b", { XX } }, 1822 { REG_TABLE (REG_0FBA) }, 1823 { "btcS", { Ev, Gv } }, 1824 { "bsfS", { Gv, Ev } }, 1825 { PREFIX_TABLE (PREFIX_0FBD) }, 1826 { "movs{bR|x}", { Gv, Eb } }, 1827 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ 1828 /* c0 */ 1829 { "xaddB", { Eb, Gb } }, 1830 { "xaddS", { Ev, Gv } }, 1831 { PREFIX_TABLE (PREFIX_0FC2) }, 1832 { PREFIX_TABLE (PREFIX_0FC3) }, 1833 { "pinsrw", { MX, Edqw, Ib } }, 1834 { "pextrw", { Gdq, MS, Ib } }, 1835 { "shufpX", { XM, EXx, Ib } }, 1836 { REG_TABLE (REG_0FC7) }, 1837 /* c8 */ 1838 { "bswap", { RMeAX } }, 1839 { "bswap", { RMeCX } }, 1840 { "bswap", { RMeDX } }, 1841 { "bswap", { RMeBX } }, 1842 { "bswap", { RMeSP } }, 1843 { "bswap", { RMeBP } }, 1844 { "bswap", { RMeSI } }, 1845 { "bswap", { RMeDI } }, 1846 /* d0 */ 1847 { PREFIX_TABLE (PREFIX_0FD0) }, 1848 { "psrlw", { MX, EM } }, 1849 { "psrld", { MX, EM } }, 1850 { "psrlq", { MX, EM } }, 1851 { "paddq", { MX, EM } }, 1852 { "pmullw", { MX, EM } }, 1853 { PREFIX_TABLE (PREFIX_0FD6) }, 1854 { MOD_TABLE (MOD_0FD7) }, 1855 /* d8 */ 1856 { "psubusb", { MX, EM } }, 1857 { "psubusw", { MX, EM } }, 1858 { "pminub", { MX, EM } }, 1859 { "pand", { MX, EM } }, 1860 { "paddusb", { MX, EM } }, 1861 { "paddusw", { MX, EM } }, 1862 { "pmaxub", { MX, EM } }, 1863 { "pandn", { MX, EM } }, 1864 /* e0 */ 1865 { "pavgb", { MX, EM } }, 1866 { "psraw", { MX, EM } }, 1867 { "psrad", { MX, EM } }, 1868 { "pavgw", { MX, EM } }, 1869 { "pmulhuw", { MX, EM } }, 1870 { "pmulhw", { MX, EM } }, 1871 { PREFIX_TABLE (PREFIX_0FE6) }, 1872 { PREFIX_TABLE (PREFIX_0FE7) }, 1873 /* e8 */ 1874 { "psubsb", { MX, EM } }, 1875 { "psubsw", { MX, EM } }, 1876 { "pminsw", { MX, EM } }, 1877 { "por", { MX, EM } }, 1878 { "paddsb", { MX, EM } }, 1879 { "paddsw", { MX, EM } }, 1880 { "pmaxsw", { MX, EM } }, 1881 { "pxor", { MX, EM } }, 1882 /* f0 */ 1883 { PREFIX_TABLE (PREFIX_0FF0) }, 1884 { "psllw", { MX, EM } }, 1885 { "pslld", { MX, EM } }, 1886 { "psllq", { MX, EM } }, 1887 { "pmuludq", { MX, EM } }, 1888 { "pmaddwd", { MX, EM } }, 1889 { "psadbw", { MX, EM } }, 1890 { PREFIX_TABLE (PREFIX_0FF7) }, 1891 /* f8 */ 1892 { "psubb", { MX, EM } }, 1893 { "psubw", { MX, EM } }, 1894 { "psubd", { MX, EM } }, 1895 { "psubq", { MX, EM } }, 1896 { "paddb", { MX, EM } }, 1897 { "paddw", { MX, EM } }, 1898 { "paddd", { MX, EM } }, 1899 { "(bad)", { XX } }, 1900 }; 1901 1902 static const unsigned char onebyte_has_modrm[256] = { 1903 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1904 /* ------------------------------- */ 1905 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ 1906 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ 1907 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ 1908 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ 1909 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ 1910 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ 1911 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ 1912 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ 1913 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ 1914 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ 1915 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ 1916 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ 1917 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ 1918 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ 1919 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ 1920 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ 1921 /* ------------------------------- */ 1922 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1923 }; 1924 1925 static const unsigned char twobyte_has_modrm[256] = { 1926 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1927 /* ------------------------------- */ 1928 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ 1929 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ 1930 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ 1931 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 1932 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ 1933 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 1934 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 1935 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ 1936 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 1937 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ 1938 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ 1939 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ 1940 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ 1941 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 1942 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 1943 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ 1944 /* ------------------------------- */ 1945 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1946 }; 1947 1948 static char obuf[100]; 1949 static char *obufp; 1950 static char *mnemonicendp; 1951 static char scratchbuf[100]; 1952 static unsigned char *start_codep; 1953 static unsigned char *insn_codep; 1954 static unsigned char *codep; 1955 static const char *lock_prefix; 1956 static const char *data_prefix; 1957 static const char *addr_prefix; 1958 static const char *repz_prefix; 1959 static const char *repnz_prefix; 1960 static disassemble_info *the_info; 1961 static struct 1962 { 1963 int mod; 1964 int reg; 1965 int rm; 1966 } 1967 modrm; 1968 static unsigned char need_modrm; 1969 static struct 1970 { 1971 int register_specifier; 1972 int length; 1973 int prefix; 1974 int w; 1975 } 1976 vex; 1977 static unsigned char need_vex; 1978 static unsigned char need_vex_reg; 1979 static unsigned char vex_w_done; 1980 1981 struct op 1982 { 1983 const char *name; 1984 unsigned int len; 1985 }; 1986 1987 /* If we are accessing mod/rm/reg without need_modrm set, then the 1988 values are stale. Hitting this abort likely indicates that you 1989 need to update onebyte_has_modrm or twobyte_has_modrm. */ 1990 #define MODRM_CHECK if (!need_modrm) abort () 1991 1992 static const char **names64; 1993 static const char **names32; 1994 static const char **names16; 1995 static const char **names8; 1996 static const char **names8rex; 1997 static const char **names_seg; 1998 static const char *index64; 1999 static const char *index32; 2000 static const char **index16; 2001 2002 static const char *intel_names64[] = { 2003 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 2004 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 2005 }; 2006 static const char *intel_names32[] = { 2007 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", 2008 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" 2009 }; 2010 static const char *intel_names16[] = { 2011 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", 2012 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" 2013 }; 2014 static const char *intel_names8[] = { 2015 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", 2016 }; 2017 static const char *intel_names8rex[] = { 2018 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", 2019 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" 2020 }; 2021 static const char *intel_names_seg[] = { 2022 "es", "cs", "ss", "ds", "fs", "gs", "?", "?", 2023 }; 2024 static const char *intel_index64 = "riz"; 2025 static const char *intel_index32 = "eiz"; 2026 static const char *intel_index16[] = { 2027 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" 2028 }; 2029 2030 static const char *att_names64[] = { 2031 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 2032 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 2033 }; 2034 static const char *att_names32[] = { 2035 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 2036 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 2037 }; 2038 static const char *att_names16[] = { 2039 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 2040 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 2041 }; 2042 static const char *att_names8[] = { 2043 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 2044 }; 2045 static const char *att_names8rex[] = { 2046 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 2047 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 2048 }; 2049 static const char *att_names_seg[] = { 2050 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", 2051 }; 2052 static const char *att_index64 = "%riz"; 2053 static const char *att_index32 = "%eiz"; 2054 static const char *att_index16[] = { 2055 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" 2056 }; 2057 2058 static const struct dis386 reg_table[][8] = { 2059 /* REG_80 */ 2060 { 2061 { "addA", { Eb, Ib } }, 2062 { "orA", { Eb, Ib } }, 2063 { "adcA", { Eb, Ib } }, 2064 { "sbbA", { Eb, Ib } }, 2065 { "andA", { Eb, Ib } }, 2066 { "subA", { Eb, Ib } }, 2067 { "xorA", { Eb, Ib } }, 2068 { "cmpA", { Eb, Ib } }, 2069 }, 2070 /* REG_81 */ 2071 { 2072 { "addQ", { Ev, Iv } }, 2073 { "orQ", { Ev, Iv } }, 2074 { "adcQ", { Ev, Iv } }, 2075 { "sbbQ", { Ev, Iv } }, 2076 { "andQ", { Ev, Iv } }, 2077 { "subQ", { Ev, Iv } }, 2078 { "xorQ", { Ev, Iv } }, 2079 { "cmpQ", { Ev, Iv } }, 2080 }, 2081 /* REG_82 */ 2082 { 2083 { "addQ", { Ev, sIb } }, 2084 { "orQ", { Ev, sIb } }, 2085 { "adcQ", { Ev, sIb } }, 2086 { "sbbQ", { Ev, sIb } }, 2087 { "andQ", { Ev, sIb } }, 2088 { "subQ", { Ev, sIb } }, 2089 { "xorQ", { Ev, sIb } }, 2090 { "cmpQ", { Ev, sIb } }, 2091 }, 2092 /* REG_8F */ 2093 { 2094 { "popU", { stackEv } }, 2095 { "(bad)", { XX } }, 2096 { "(bad)", { XX } }, 2097 { "(bad)", { XX } }, 2098 { "(bad)", { XX } }, 2099 { "(bad)", { XX } }, 2100 { "(bad)", { XX } }, 2101 { "(bad)", { XX } }, 2102 }, 2103 /* REG_C0 */ 2104 { 2105 { "rolA", { Eb, Ib } }, 2106 { "rorA", { Eb, Ib } }, 2107 { "rclA", { Eb, Ib } }, 2108 { "rcrA", { Eb, Ib } }, 2109 { "shlA", { Eb, Ib } }, 2110 { "shrA", { Eb, Ib } }, 2111 { "(bad)", { XX } }, 2112 { "sarA", { Eb, Ib } }, 2113 }, 2114 /* REG_C1 */ 2115 { 2116 { "rolQ", { Ev, Ib } }, 2117 { "rorQ", { Ev, Ib } }, 2118 { "rclQ", { Ev, Ib } }, 2119 { "rcrQ", { Ev, Ib } }, 2120 { "shlQ", { Ev, Ib } }, 2121 { "shrQ", { Ev, Ib } }, 2122 { "(bad)", { XX } }, 2123 { "sarQ", { Ev, Ib } }, 2124 }, 2125 /* REG_C6 */ 2126 { 2127 { "movA", { Eb, Ib } }, 2128 { "(bad)", { XX } }, 2129 { "(bad)", { XX } }, 2130 { "(bad)", { XX } }, 2131 { "(bad)", { XX } }, 2132 { "(bad)", { XX } }, 2133 { "(bad)", { XX } }, 2134 { "(bad)", { XX } }, 2135 }, 2136 /* REG_C7 */ 2137 { 2138 { "movQ", { Ev, Iv } }, 2139 { "(bad)", { XX } }, 2140 { "(bad)", { XX } }, 2141 { "(bad)", { XX } }, 2142 { "(bad)", { XX } }, 2143 { "(bad)", { XX } }, 2144 { "(bad)", { XX } }, 2145 { "(bad)", { XX } }, 2146 }, 2147 /* REG_D0 */ 2148 { 2149 { "rolA", { Eb, I1 } }, 2150 { "rorA", { Eb, I1 } }, 2151 { "rclA", { Eb, I1 } }, 2152 { "rcrA", { Eb, I1 } }, 2153 { "shlA", { Eb, I1 } }, 2154 { "shrA", { Eb, I1 } }, 2155 { "(bad)", { XX } }, 2156 { "sarA", { Eb, I1 } }, 2157 }, 2158 /* REG_D1 */ 2159 { 2160 { "rolQ", { Ev, I1 } }, 2161 { "rorQ", { Ev, I1 } }, 2162 { "rclQ", { Ev, I1 } }, 2163 { "rcrQ", { Ev, I1 } }, 2164 { "shlQ", { Ev, I1 } }, 2165 { "shrQ", { Ev, I1 } }, 2166 { "(bad)", { XX } }, 2167 { "sarQ", { Ev, I1 } }, 2168 }, 2169 /* REG_D2 */ 2170 { 2171 { "rolA", { Eb, CL } }, 2172 { "rorA", { Eb, CL } }, 2173 { "rclA", { Eb, CL } }, 2174 { "rcrA", { Eb, CL } }, 2175 { "shlA", { Eb, CL } }, 2176 { "shrA", { Eb, CL } }, 2177 { "(bad)", { XX } }, 2178 { "sarA", { Eb, CL } }, 2179 }, 2180 /* REG_D3 */ 2181 { 2182 { "rolQ", { Ev, CL } }, 2183 { "rorQ", { Ev, CL } }, 2184 { "rclQ", { Ev, CL } }, 2185 { "rcrQ", { Ev, CL } }, 2186 { "shlQ", { Ev, CL } }, 2187 { "shrQ", { Ev, CL } }, 2188 { "(bad)", { XX } }, 2189 { "sarQ", { Ev, CL } }, 2190 }, 2191 /* REG_F6 */ 2192 { 2193 { "testA", { Eb, Ib } }, 2194 { "(bad)", { XX } }, 2195 { "notA", { Eb } }, 2196 { "negA", { Eb } }, 2197 { "mulA", { Eb } }, /* Don't print the implicit %al register, */ 2198 { "imulA", { Eb } }, /* to distinguish these opcodes from other */ 2199 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ 2200 { "idivA", { Eb } }, /* and idiv for consistency. */ 2201 }, 2202 /* REG_F7 */ 2203 { 2204 { "testQ", { Ev, Iv } }, 2205 { "(bad)", { XX } }, 2206 { "notQ", { Ev } }, 2207 { "negQ", { Ev } }, 2208 { "mulQ", { Ev } }, /* Don't print the implicit register. */ 2209 { "imulQ", { Ev } }, 2210 { "divQ", { Ev } }, 2211 { "idivQ", { Ev } }, 2212 }, 2213 /* REG_FE */ 2214 { 2215 { "incA", { Eb } }, 2216 { "decA", { Eb } }, 2217 { "(bad)", { XX } }, 2218 { "(bad)", { XX } }, 2219 { "(bad)", { XX } }, 2220 { "(bad)", { XX } }, 2221 { "(bad)", { XX } }, 2222 { "(bad)", { XX } }, 2223 }, 2224 /* REG_FF */ 2225 { 2226 { "incQ", { Ev } }, 2227 { "decQ", { Ev } }, 2228 { "callT", { indirEv } }, 2229 { "JcallT", { indirEp } }, 2230 { "jmpT", { indirEv } }, 2231 { "JjmpT", { indirEp } }, 2232 { "pushU", { stackEv } }, 2233 { "(bad)", { XX } }, 2234 }, 2235 /* REG_0F00 */ 2236 { 2237 { "sldtD", { Sv } }, 2238 { "strD", { Sv } }, 2239 { "lldt", { Ew } }, 2240 { "ltr", { Ew } }, 2241 { "verr", { Ew } }, 2242 { "verw", { Ew } }, 2243 { "(bad)", { XX } }, 2244 { "(bad)", { XX } }, 2245 }, 2246 /* REG_0F01 */ 2247 { 2248 { MOD_TABLE (MOD_0F01_REG_0) }, 2249 { MOD_TABLE (MOD_0F01_REG_1) }, 2250 { MOD_TABLE (MOD_0F01_REG_2) }, 2251 { MOD_TABLE (MOD_0F01_REG_3) }, 2252 { "smswD", { Sv } }, 2253 { "(bad)", { XX } }, 2254 { "lmsw", { Ew } }, 2255 { MOD_TABLE (MOD_0F01_REG_7) }, 2256 }, 2257 /* REG_0F0D */ 2258 { 2259 { "prefetch", { Eb } }, 2260 { "prefetchw", { Eb } }, 2261 { "(bad)", { XX } }, 2262 { "(bad)", { XX } }, 2263 { "(bad)", { XX } }, 2264 { "(bad)", { XX } }, 2265 { "(bad)", { XX } }, 2266 { "(bad)", { XX } }, 2267 }, 2268 /* REG_0F18 */ 2269 { 2270 { MOD_TABLE (MOD_0F18_REG_0) }, 2271 { MOD_TABLE (MOD_0F18_REG_1) }, 2272 { MOD_TABLE (MOD_0F18_REG_2) }, 2273 { MOD_TABLE (MOD_0F18_REG_3) }, 2274 { "(bad)", { XX } }, 2275 { "(bad)", { XX } }, 2276 { "(bad)", { XX } }, 2277 { "(bad)", { XX } }, 2278 }, 2279 /* REG_0F71 */ 2280 { 2281 { "(bad)", { XX } }, 2282 { "(bad)", { XX } }, 2283 { MOD_TABLE (MOD_0F71_REG_2) }, 2284 { "(bad)", { XX } }, 2285 { MOD_TABLE (MOD_0F71_REG_4) }, 2286 { "(bad)", { XX } }, 2287 { MOD_TABLE (MOD_0F71_REG_6) }, 2288 { "(bad)", { XX } }, 2289 }, 2290 /* REG_0F72 */ 2291 { 2292 { "(bad)", { XX } }, 2293 { "(bad)", { XX } }, 2294 { MOD_TABLE (MOD_0F72_REG_2) }, 2295 { "(bad)", { XX } }, 2296 { MOD_TABLE (MOD_0F72_REG_4) }, 2297 { "(bad)", { XX } }, 2298 { MOD_TABLE (MOD_0F72_REG_6) }, 2299 { "(bad)", { XX } }, 2300 }, 2301 /* REG_0F73 */ 2302 { 2303 { "(bad)", { XX } }, 2304 { "(bad)", { XX } }, 2305 { MOD_TABLE (MOD_0F73_REG_2) }, 2306 { MOD_TABLE (MOD_0F73_REG_3) }, 2307 { "(bad)", { XX } }, 2308 { "(bad)", { XX } }, 2309 { MOD_TABLE (MOD_0F73_REG_6) }, 2310 { MOD_TABLE (MOD_0F73_REG_7) }, 2311 }, 2312 /* REG_0FA6 */ 2313 { 2314 { "montmul", { { OP_0f07, 0 } } }, 2315 { "xsha1", { { OP_0f07, 0 } } }, 2316 { "xsha256", { { OP_0f07, 0 } } }, 2317 { "(bad)", { { OP_0f07, 0 } } }, 2318 { "(bad)", { { OP_0f07, 0 } } }, 2319 { "(bad)", { { OP_0f07, 0 } } }, 2320 { "(bad)", { { OP_0f07, 0 } } }, 2321 { "(bad)", { { OP_0f07, 0 } } }, 2322 }, 2323 /* REG_0FA7 */ 2324 { 2325 { "xstore-rng", { { OP_0f07, 0 } } }, 2326 { "xcrypt-ecb", { { OP_0f07, 0 } } }, 2327 { "xcrypt-cbc", { { OP_0f07, 0 } } }, 2328 { "xcrypt-ctr", { { OP_0f07, 0 } } }, 2329 { "xcrypt-cfb", { { OP_0f07, 0 } } }, 2330 { "xcrypt-ofb", { { OP_0f07, 0 } } }, 2331 { "(bad)", { { OP_0f07, 0 } } }, 2332 { "(bad)", { { OP_0f07, 0 } } }, 2333 }, 2334 /* REG_0FAE */ 2335 { 2336 { MOD_TABLE (MOD_0FAE_REG_0) }, 2337 { MOD_TABLE (MOD_0FAE_REG_1) }, 2338 { MOD_TABLE (MOD_0FAE_REG_2) }, 2339 { MOD_TABLE (MOD_0FAE_REG_3) }, 2340 { MOD_TABLE (MOD_0FAE_REG_4) }, 2341 { MOD_TABLE (MOD_0FAE_REG_5) }, 2342 { MOD_TABLE (MOD_0FAE_REG_6) }, 2343 { MOD_TABLE (MOD_0FAE_REG_7) }, 2344 }, 2345 /* REG_0FBA */ 2346 { 2347 { "(bad)", { XX } }, 2348 { "(bad)", { XX } }, 2349 { "(bad)", { XX } }, 2350 { "(bad)", { XX } }, 2351 { "btQ", { Ev, Ib } }, 2352 { "btsQ", { Ev, Ib } }, 2353 { "btrQ", { Ev, Ib } }, 2354 { "btcQ", { Ev, Ib } }, 2355 }, 2356 /* REG_0FC7 */ 2357 { 2358 { "(bad)", { XX } }, 2359 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, 2360 { "(bad)", { XX } }, 2361 { "(bad)", { XX } }, 2362 { "(bad)", { XX } }, 2363 { "(bad)", { XX } }, 2364 { MOD_TABLE (MOD_0FC7_REG_6) }, 2365 { MOD_TABLE (MOD_0FC7_REG_7) }, 2366 }, 2367 /* REG_VEX_71 */ 2368 { 2369 { "(bad)", { XX } }, 2370 { "(bad)", { XX } }, 2371 { MOD_TABLE (MOD_VEX_71_REG_2) }, 2372 { "(bad)", { XX } }, 2373 { MOD_TABLE (MOD_VEX_71_REG_4) }, 2374 { "(bad)", { XX } }, 2375 { MOD_TABLE (MOD_VEX_71_REG_6) }, 2376 { "(bad)", { XX } }, 2377 }, 2378 /* REG_VEX_72 */ 2379 { 2380 { "(bad)", { XX } }, 2381 { "(bad)", { XX } }, 2382 { MOD_TABLE (MOD_VEX_72_REG_2) }, 2383 { "(bad)", { XX } }, 2384 { MOD_TABLE (MOD_VEX_72_REG_4) }, 2385 { "(bad)", { XX } }, 2386 { MOD_TABLE (MOD_VEX_72_REG_6) }, 2387 { "(bad)", { XX } }, 2388 }, 2389 /* REG_VEX_73 */ 2390 { 2391 { "(bad)", { XX } }, 2392 { "(bad)", { XX } }, 2393 { MOD_TABLE (MOD_VEX_73_REG_2) }, 2394 { MOD_TABLE (MOD_VEX_73_REG_3) }, 2395 { "(bad)", { XX } }, 2396 { "(bad)", { XX } }, 2397 { MOD_TABLE (MOD_VEX_73_REG_6) }, 2398 { MOD_TABLE (MOD_VEX_73_REG_7) }, 2399 }, 2400 /* REG_VEX_AE */ 2401 { 2402 { "(bad)", { XX } }, 2403 { "(bad)", { XX } }, 2404 { MOD_TABLE (MOD_VEX_AE_REG_2) }, 2405 { MOD_TABLE (MOD_VEX_AE_REG_3) }, 2406 { "(bad)", { XX } }, 2407 { "(bad)", { XX } }, 2408 { "(bad)", { XX } }, 2409 { "(bad)", { XX } }, 2410 }, 2411 }; 2412 2413 static const struct dis386 prefix_table[][4] = { 2414 /* PREFIX_90 */ 2415 { 2416 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, 2417 { "pause", { XX } }, 2418 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, 2419 { "(bad)", { XX } }, 2420 }, 2421 2422 /* PREFIX_0F10 */ 2423 { 2424 { "movups", { XM, EXx } }, 2425 { "movss", { XM, EXd } }, 2426 { "movupd", { XM, EXx } }, 2427 { "movsd", { XM, EXq } }, 2428 }, 2429 2430 /* PREFIX_0F11 */ 2431 { 2432 { "movups", { EXxS, XM } }, 2433 { "movss", { EXdS, XM } }, 2434 { "movupd", { EXxS, XM } }, 2435 { "movsd", { EXqS, XM } }, 2436 }, 2437 2438 /* PREFIX_0F12 */ 2439 { 2440 { MOD_TABLE (MOD_0F12_PREFIX_0) }, 2441 { "movsldup", { XM, EXx } }, 2442 { "movlpd", { XM, EXq } }, 2443 { "movddup", { XM, EXq } }, 2444 }, 2445 2446 /* PREFIX_0F16 */ 2447 { 2448 { MOD_TABLE (MOD_0F16_PREFIX_0) }, 2449 { "movshdup", { XM, EXx } }, 2450 { "movhpd", { XM, EXq } }, 2451 { "(bad)", { XX } }, 2452 }, 2453 2454 /* PREFIX_0F2A */ 2455 { 2456 { "cvtpi2ps", { XM, EMCq } }, 2457 { "cvtsi2ss%LQ", { XM, Ev } }, 2458 { "cvtpi2pd", { XM, EMCq } }, 2459 { "cvtsi2sd%LQ", { XM, Ev } }, 2460 }, 2461 2462 /* PREFIX_0F2B */ 2463 { 2464 { MOD_TABLE (MOD_0F2B_PREFIX_0) }, 2465 { MOD_TABLE (MOD_0F2B_PREFIX_1) }, 2466 { MOD_TABLE (MOD_0F2B_PREFIX_2) }, 2467 { MOD_TABLE (MOD_0F2B_PREFIX_3) }, 2468 }, 2469 2470 /* PREFIX_0F2C */ 2471 { 2472 { "cvttps2pi", { MXC, EXq } }, 2473 { "cvttss2siY", { Gv, EXd } }, 2474 { "cvttpd2pi", { MXC, EXx } }, 2475 { "cvttsd2siY", { Gv, EXq } }, 2476 }, 2477 2478 /* PREFIX_0F2D */ 2479 { 2480 { "cvtps2pi", { MXC, EXq } }, 2481 { "cvtss2siY", { Gv, EXd } }, 2482 { "cvtpd2pi", { MXC, EXx } }, 2483 { "cvtsd2siY", { Gv, EXq } }, 2484 }, 2485 2486 /* PREFIX_0F2E */ 2487 { 2488 { "ucomiss",{ XM, EXd } }, 2489 { "(bad)", { XX } }, 2490 { "ucomisd",{ XM, EXq } }, 2491 { "(bad)", { XX } }, 2492 }, 2493 2494 /* PREFIX_0F2F */ 2495 { 2496 { "comiss", { XM, EXd } }, 2497 { "(bad)", { XX } }, 2498 { "comisd", { XM, EXq } }, 2499 { "(bad)", { XX } }, 2500 }, 2501 2502 /* PREFIX_0F51 */ 2503 { 2504 { "sqrtps", { XM, EXx } }, 2505 { "sqrtss", { XM, EXd } }, 2506 { "sqrtpd", { XM, EXx } }, 2507 { "sqrtsd", { XM, EXq } }, 2508 }, 2509 2510 /* PREFIX_0F52 */ 2511 { 2512 { "rsqrtps",{ XM, EXx } }, 2513 { "rsqrtss",{ XM, EXd } }, 2514 { "(bad)", { XX } }, 2515 { "(bad)", { XX } }, 2516 }, 2517 2518 /* PREFIX_0F53 */ 2519 { 2520 { "rcpps", { XM, EXx } }, 2521 { "rcpss", { XM, EXd } }, 2522 { "(bad)", { XX } }, 2523 { "(bad)", { XX } }, 2524 }, 2525 2526 /* PREFIX_0F58 */ 2527 { 2528 { "addps", { XM, EXx } }, 2529 { "addss", { XM, EXd } }, 2530 { "addpd", { XM, EXx } }, 2531 { "addsd", { XM, EXq } }, 2532 }, 2533 2534 /* PREFIX_0F59 */ 2535 { 2536 { "mulps", { XM, EXx } }, 2537 { "mulss", { XM, EXd } }, 2538 { "mulpd", { XM, EXx } }, 2539 { "mulsd", { XM, EXq } }, 2540 }, 2541 2542 /* PREFIX_0F5A */ 2543 { 2544 { "cvtps2pd", { XM, EXq } }, 2545 { "cvtss2sd", { XM, EXd } }, 2546 { "cvtpd2ps", { XM, EXx } }, 2547 { "cvtsd2ss", { XM, EXq } }, 2548 }, 2549 2550 /* PREFIX_0F5B */ 2551 { 2552 { "cvtdq2ps", { XM, EXx } }, 2553 { "cvttps2dq", { XM, EXx } }, 2554 { "cvtps2dq", { XM, EXx } }, 2555 { "(bad)", { XX } }, 2556 }, 2557 2558 /* PREFIX_0F5C */ 2559 { 2560 { "subps", { XM, EXx } }, 2561 { "subss", { XM, EXd } }, 2562 { "subpd", { XM, EXx } }, 2563 { "subsd", { XM, EXq } }, 2564 }, 2565 2566 /* PREFIX_0F5D */ 2567 { 2568 { "minps", { XM, EXx } }, 2569 { "minss", { XM, EXd } }, 2570 { "minpd", { XM, EXx } }, 2571 { "minsd", { XM, EXq } }, 2572 }, 2573 2574 /* PREFIX_0F5E */ 2575 { 2576 { "divps", { XM, EXx } }, 2577 { "divss", { XM, EXd } }, 2578 { "divpd", { XM, EXx } }, 2579 { "divsd", { XM, EXq } }, 2580 }, 2581 2582 /* PREFIX_0F5F */ 2583 { 2584 { "maxps", { XM, EXx } }, 2585 { "maxss", { XM, EXd } }, 2586 { "maxpd", { XM, EXx } }, 2587 { "maxsd", { XM, EXq } }, 2588 }, 2589 2590 /* PREFIX_0F60 */ 2591 { 2592 { "punpcklbw",{ MX, EMd } }, 2593 { "(bad)", { XX } }, 2594 { "punpcklbw",{ MX, EMx } }, 2595 { "(bad)", { XX } }, 2596 }, 2597 2598 /* PREFIX_0F61 */ 2599 { 2600 { "punpcklwd",{ MX, EMd } }, 2601 { "(bad)", { XX } }, 2602 { "punpcklwd",{ MX, EMx } }, 2603 { "(bad)", { XX } }, 2604 }, 2605 2606 /* PREFIX_0F62 */ 2607 { 2608 { "punpckldq",{ MX, EMd } }, 2609 { "(bad)", { XX } }, 2610 { "punpckldq",{ MX, EMx } }, 2611 { "(bad)", { XX } }, 2612 }, 2613 2614 /* PREFIX_0F6C */ 2615 { 2616 { "(bad)", { XX } }, 2617 { "(bad)", { XX } }, 2618 { "punpcklqdq", { XM, EXx } }, 2619 { "(bad)", { XX } }, 2620 }, 2621 2622 /* PREFIX_0F6D */ 2623 { 2624 { "(bad)", { XX } }, 2625 { "(bad)", { XX } }, 2626 { "punpckhqdq", { XM, EXx } }, 2627 { "(bad)", { XX } }, 2628 }, 2629 2630 /* PREFIX_0F6F */ 2631 { 2632 { "movq", { MX, EM } }, 2633 { "movdqu", { XM, EXx } }, 2634 { "movdqa", { XM, EXx } }, 2635 { "(bad)", { XX } }, 2636 }, 2637 2638 /* PREFIX_0F70 */ 2639 { 2640 { "pshufw", { MX, EM, Ib } }, 2641 { "pshufhw",{ XM, EXx, Ib } }, 2642 { "pshufd", { XM, EXx, Ib } }, 2643 { "pshuflw",{ XM, EXx, Ib } }, 2644 }, 2645 2646 /* PREFIX_0F73_REG_3 */ 2647 { 2648 { "(bad)", { XX } }, 2649 { "(bad)", { XX } }, 2650 { "psrldq", { XS, Ib } }, 2651 { "(bad)", { XX } }, 2652 }, 2653 2654 /* PREFIX_0F73_REG_7 */ 2655 { 2656 { "(bad)", { XX } }, 2657 { "(bad)", { XX } }, 2658 { "pslldq", { XS, Ib } }, 2659 { "(bad)", { XX } }, 2660 }, 2661 2662 /* PREFIX_0F78 */ 2663 { 2664 {"vmread", { Em, Gm } }, 2665 {"(bad)", { XX } }, 2666 {"extrq", { XS, Ib, Ib } }, 2667 {"insertq", { XM, XS, Ib, Ib } }, 2668 }, 2669 2670 /* PREFIX_0F79 */ 2671 { 2672 {"vmwrite", { Gm, Em } }, 2673 {"(bad)", { XX } }, 2674 {"extrq", { XM, XS } }, 2675 {"insertq", { XM, XS } }, 2676 }, 2677 2678 /* PREFIX_0F7C */ 2679 { 2680 { "(bad)", { XX } }, 2681 { "(bad)", { XX } }, 2682 { "haddpd", { XM, EXx } }, 2683 { "haddps", { XM, EXx } }, 2684 }, 2685 2686 /* PREFIX_0F7D */ 2687 { 2688 { "(bad)", { XX } }, 2689 { "(bad)", { XX } }, 2690 { "hsubpd", { XM, EXx } }, 2691 { "hsubps", { XM, EXx } }, 2692 }, 2693 2694 /* PREFIX_0F7E */ 2695 { 2696 { "movK", { Edq, MX } }, 2697 { "movq", { XM, EXq } }, 2698 { "movK", { Edq, XM } }, 2699 { "(bad)", { XX } }, 2700 }, 2701 2702 /* PREFIX_0F7F */ 2703 { 2704 { "movq", { EMS, MX } }, 2705 { "movdqu", { EXxS, XM } }, 2706 { "movdqa", { EXxS, XM } }, 2707 { "(bad)", { XX } }, 2708 }, 2709 2710 /* PREFIX_0FB8 */ 2711 { 2712 { "(bad)", { XX } }, 2713 { "popcntS", { Gv, Ev } }, 2714 { "(bad)", { XX } }, 2715 { "(bad)", { XX } }, 2716 }, 2717 2718 /* PREFIX_0FBD */ 2719 { 2720 { "bsrS", { Gv, Ev } }, 2721 { "lzcntS", { Gv, Ev } }, 2722 { "bsrS", { Gv, Ev } }, 2723 { "(bad)", { XX } }, 2724 }, 2725 2726 /* PREFIX_0FC2 */ 2727 { 2728 { "cmpps", { XM, EXx, CMP } }, 2729 { "cmpss", { XM, EXd, CMP } }, 2730 { "cmppd", { XM, EXx, CMP } }, 2731 { "cmpsd", { XM, EXq, CMP } }, 2732 }, 2733 2734 /* PREFIX_0FC3 */ 2735 { 2736 { "movntiS", { Ma, Gv } }, 2737 { "(bad)", { XX } }, 2738 { "(bad)", { XX } }, 2739 { "(bad)", { XX } }, 2740 }, 2741 2742 /* PREFIX_0FC7_REG_6 */ 2743 { 2744 { "vmptrld",{ Mq } }, 2745 { "vmxon", { Mq } }, 2746 { "vmclear",{ Mq } }, 2747 { "(bad)", { XX } }, 2748 }, 2749 2750 /* PREFIX_0FD0 */ 2751 { 2752 { "(bad)", { XX } }, 2753 { "(bad)", { XX } }, 2754 { "addsubpd", { XM, EXx } }, 2755 { "addsubps", { XM, EXx } }, 2756 }, 2757 2758 /* PREFIX_0FD6 */ 2759 { 2760 { "(bad)", { XX } }, 2761 { "movq2dq",{ XM, MS } }, 2762 { "movq", { EXqS, XM } }, 2763 { "movdq2q",{ MX, XS } }, 2764 }, 2765 2766 /* PREFIX_0FE6 */ 2767 { 2768 { "(bad)", { XX } }, 2769 { "cvtdq2pd", { XM, EXq } }, 2770 { "cvttpd2dq", { XM, EXx } }, 2771 { "cvtpd2dq", { XM, EXx } }, 2772 }, 2773 2774 /* PREFIX_0FE7 */ 2775 { 2776 { "movntq", { Mq, MX } }, 2777 { "(bad)", { XX } }, 2778 { MOD_TABLE (MOD_0FE7_PREFIX_2) }, 2779 { "(bad)", { XX } }, 2780 }, 2781 2782 /* PREFIX_0FF0 */ 2783 { 2784 { "(bad)", { XX } }, 2785 { "(bad)", { XX } }, 2786 { "(bad)", { XX } }, 2787 { MOD_TABLE (MOD_0FF0_PREFIX_3) }, 2788 }, 2789 2790 /* PREFIX_0FF7 */ 2791 { 2792 { "maskmovq", { MX, MS } }, 2793 { "(bad)", { XX } }, 2794 { "maskmovdqu", { XM, XS } }, 2795 { "(bad)", { XX } }, 2796 }, 2797 2798 /* PREFIX_0F3810 */ 2799 { 2800 { "(bad)", { XX } }, 2801 { "(bad)", { XX } }, 2802 { "pblendvb", { XM, EXx, XMM0 } }, 2803 { "(bad)", { XX } }, 2804 }, 2805 2806 /* PREFIX_0F3814 */ 2807 { 2808 { "(bad)", { XX } }, 2809 { "(bad)", { XX } }, 2810 { "blendvps", { XM, EXx, XMM0 } }, 2811 { "(bad)", { XX } }, 2812 }, 2813 2814 /* PREFIX_0F3815 */ 2815 { 2816 { "(bad)", { XX } }, 2817 { "(bad)", { XX } }, 2818 { "blendvpd", { XM, EXx, XMM0 } }, 2819 { "(bad)", { XX } }, 2820 }, 2821 2822 /* PREFIX_0F3817 */ 2823 { 2824 { "(bad)", { XX } }, 2825 { "(bad)", { XX } }, 2826 { "ptest", { XM, EXx } }, 2827 { "(bad)", { XX } }, 2828 }, 2829 2830 /* PREFIX_0F3820 */ 2831 { 2832 { "(bad)", { XX } }, 2833 { "(bad)", { XX } }, 2834 { "pmovsxbw", { XM, EXq } }, 2835 { "(bad)", { XX } }, 2836 }, 2837 2838 /* PREFIX_0F3821 */ 2839 { 2840 { "(bad)", { XX } }, 2841 { "(bad)", { XX } }, 2842 { "pmovsxbd", { XM, EXd } }, 2843 { "(bad)", { XX } }, 2844 }, 2845 2846 /* PREFIX_0F3822 */ 2847 { 2848 { "(bad)", { XX } }, 2849 { "(bad)", { XX } }, 2850 { "pmovsxbq", { XM, EXw } }, 2851 { "(bad)", { XX } }, 2852 }, 2853 2854 /* PREFIX_0F3823 */ 2855 { 2856 { "(bad)", { XX } }, 2857 { "(bad)", { XX } }, 2858 { "pmovsxwd", { XM, EXq } }, 2859 { "(bad)", { XX } }, 2860 }, 2861 2862 /* PREFIX_0F3824 */ 2863 { 2864 { "(bad)", { XX } }, 2865 { "(bad)", { XX } }, 2866 { "pmovsxwq", { XM, EXd } }, 2867 { "(bad)", { XX } }, 2868 }, 2869 2870 /* PREFIX_0F3825 */ 2871 { 2872 { "(bad)", { XX } }, 2873 { "(bad)", { XX } }, 2874 { "pmovsxdq", { XM, EXq } }, 2875 { "(bad)", { XX } }, 2876 }, 2877 2878 /* PREFIX_0F3828 */ 2879 { 2880 { "(bad)", { XX } }, 2881 { "(bad)", { XX } }, 2882 { "pmuldq", { XM, EXx } }, 2883 { "(bad)", { XX } }, 2884 }, 2885 2886 /* PREFIX_0F3829 */ 2887 { 2888 { "(bad)", { XX } }, 2889 { "(bad)", { XX } }, 2890 { "pcmpeqq", { XM, EXx } }, 2891 { "(bad)", { XX } }, 2892 }, 2893 2894 /* PREFIX_0F382A */ 2895 { 2896 { "(bad)", { XX } }, 2897 { "(bad)", { XX } }, 2898 { MOD_TABLE (MOD_0F382A_PREFIX_2) }, 2899 { "(bad)", { XX } }, 2900 }, 2901 2902 /* PREFIX_0F382B */ 2903 { 2904 { "(bad)", { XX } }, 2905 { "(bad)", { XX } }, 2906 { "packusdw", { XM, EXx } }, 2907 { "(bad)", { XX } }, 2908 }, 2909 2910 /* PREFIX_0F3830 */ 2911 { 2912 { "(bad)", { XX } }, 2913 { "(bad)", { XX } }, 2914 { "pmovzxbw", { XM, EXq } }, 2915 { "(bad)", { XX } }, 2916 }, 2917 2918 /* PREFIX_0F3831 */ 2919 { 2920 { "(bad)", { XX } }, 2921 { "(bad)", { XX } }, 2922 { "pmovzxbd", { XM, EXd } }, 2923 { "(bad)", { XX } }, 2924 }, 2925 2926 /* PREFIX_0F3832 */ 2927 { 2928 { "(bad)", { XX } }, 2929 { "(bad)", { XX } }, 2930 { "pmovzxbq", { XM, EXw } }, 2931 { "(bad)", { XX } }, 2932 }, 2933 2934 /* PREFIX_0F3833 */ 2935 { 2936 { "(bad)", { XX } }, 2937 { "(bad)", { XX } }, 2938 { "pmovzxwd", { XM, EXq } }, 2939 { "(bad)", { XX } }, 2940 }, 2941 2942 /* PREFIX_0F3834 */ 2943 { 2944 { "(bad)", { XX } }, 2945 { "(bad)", { XX } }, 2946 { "pmovzxwq", { XM, EXd } }, 2947 { "(bad)", { XX } }, 2948 }, 2949 2950 /* PREFIX_0F3835 */ 2951 { 2952 { "(bad)", { XX } }, 2953 { "(bad)", { XX } }, 2954 { "pmovzxdq", { XM, EXq } }, 2955 { "(bad)", { XX } }, 2956 }, 2957 2958 /* PREFIX_0F3837 */ 2959 { 2960 { "(bad)", { XX } }, 2961 { "(bad)", { XX } }, 2962 { "pcmpgtq", { XM, EXx } }, 2963 { "(bad)", { XX } }, 2964 }, 2965 2966 /* PREFIX_0F3838 */ 2967 { 2968 { "(bad)", { XX } }, 2969 { "(bad)", { XX } }, 2970 { "pminsb", { XM, EXx } }, 2971 { "(bad)", { XX } }, 2972 }, 2973 2974 /* PREFIX_0F3839 */ 2975 { 2976 { "(bad)", { XX } }, 2977 { "(bad)", { XX } }, 2978 { "pminsd", { XM, EXx } }, 2979 { "(bad)", { XX } }, 2980 }, 2981 2982 /* PREFIX_0F383A */ 2983 { 2984 { "(bad)", { XX } }, 2985 { "(bad)", { XX } }, 2986 { "pminuw", { XM, EXx } }, 2987 { "(bad)", { XX } }, 2988 }, 2989 2990 /* PREFIX_0F383B */ 2991 { 2992 { "(bad)", { XX } }, 2993 { "(bad)", { XX } }, 2994 { "pminud", { XM, EXx } }, 2995 { "(bad)", { XX } }, 2996 }, 2997 2998 /* PREFIX_0F383C */ 2999 { 3000 { "(bad)", { XX } }, 3001 { "(bad)", { XX } }, 3002 { "pmaxsb", { XM, EXx } }, 3003 { "(bad)", { XX } }, 3004 }, 3005 3006 /* PREFIX_0F383D */ 3007 { 3008 { "(bad)", { XX } }, 3009 { "(bad)", { XX } }, 3010 { "pmaxsd", { XM, EXx } }, 3011 { "(bad)", { XX } }, 3012 }, 3013 3014 /* PREFIX_0F383E */ 3015 { 3016 { "(bad)", { XX } }, 3017 { "(bad)", { XX } }, 3018 { "pmaxuw", { XM, EXx } }, 3019 { "(bad)", { XX } }, 3020 }, 3021 3022 /* PREFIX_0F383F */ 3023 { 3024 { "(bad)", { XX } }, 3025 { "(bad)", { XX } }, 3026 { "pmaxud", { XM, EXx } }, 3027 { "(bad)", { XX } }, 3028 }, 3029 3030 /* PREFIX_0F3840 */ 3031 { 3032 { "(bad)", { XX } }, 3033 { "(bad)", { XX } }, 3034 { "pmulld", { XM, EXx } }, 3035 { "(bad)", { XX } }, 3036 }, 3037 3038 /* PREFIX_0F3841 */ 3039 { 3040 { "(bad)", { XX } }, 3041 { "(bad)", { XX } }, 3042 { "phminposuw", { XM, EXx } }, 3043 { "(bad)", { XX } }, 3044 }, 3045 3046 /* PREFIX_0F3880 */ 3047 { 3048 { "(bad)", { XX } }, 3049 { "(bad)", { XX } }, 3050 { "invept", { Gm, Mo } }, 3051 { "(bad)", { XX } }, 3052 }, 3053 3054 /* PREFIX_0F3881 */ 3055 { 3056 { "(bad)", { XX } }, 3057 { "(bad)", { XX } }, 3058 { "invvpid", { Gm, Mo } }, 3059 { "(bad)", { XX } }, 3060 }, 3061 3062 /* PREFIX_0F38DB */ 3063 { 3064 { "(bad)", { XX } }, 3065 { "(bad)", { XX } }, 3066 { "aesimc", { XM, EXx } }, 3067 { "(bad)", { XX } }, 3068 }, 3069 3070 /* PREFIX_0F38DC */ 3071 { 3072 { "(bad)", { XX } }, 3073 { "(bad)", { XX } }, 3074 { "aesenc", { XM, EXx } }, 3075 { "(bad)", { XX } }, 3076 }, 3077 3078 /* PREFIX_0F38DD */ 3079 { 3080 { "(bad)", { XX } }, 3081 { "(bad)", { XX } }, 3082 { "aesenclast", { XM, EXx } }, 3083 { "(bad)", { XX } }, 3084 }, 3085 3086 /* PREFIX_0F38DE */ 3087 { 3088 { "(bad)", { XX } }, 3089 { "(bad)", { XX } }, 3090 { "aesdec", { XM, EXx } }, 3091 { "(bad)", { XX } }, 3092 }, 3093 3094 /* PREFIX_0F38DF */ 3095 { 3096 { "(bad)", { XX } }, 3097 { "(bad)", { XX } }, 3098 { "aesdeclast", { XM, EXx } }, 3099 { "(bad)", { XX } }, 3100 }, 3101 3102 /* PREFIX_0F38F0 */ 3103 { 3104 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, 3105 { "(bad)", { XX } }, 3106 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, 3107 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, 3108 }, 3109 3110 /* PREFIX_0F38F1 */ 3111 { 3112 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, 3113 { "(bad)", { XX } }, 3114 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, 3115 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, 3116 }, 3117 3118 /* PREFIX_0F3A08 */ 3119 { 3120 { "(bad)", { XX } }, 3121 { "(bad)", { XX } }, 3122 { "roundps", { XM, EXx, Ib } }, 3123 { "(bad)", { XX } }, 3124 }, 3125 3126 /* PREFIX_0F3A09 */ 3127 { 3128 { "(bad)", { XX } }, 3129 { "(bad)", { XX } }, 3130 { "roundpd", { XM, EXx, Ib } }, 3131 { "(bad)", { XX } }, 3132 }, 3133 3134 /* PREFIX_0F3A0A */ 3135 { 3136 { "(bad)", { XX } }, 3137 { "(bad)", { XX } }, 3138 { "roundss", { XM, EXd, Ib } }, 3139 { "(bad)", { XX } }, 3140 }, 3141 3142 /* PREFIX_0F3A0B */ 3143 { 3144 { "(bad)", { XX } }, 3145 { "(bad)", { XX } }, 3146 { "roundsd", { XM, EXq, Ib } }, 3147 { "(bad)", { XX } }, 3148 }, 3149 3150 /* PREFIX_0F3A0C */ 3151 { 3152 { "(bad)", { XX } }, 3153 { "(bad)", { XX } }, 3154 { "blendps", { XM, EXx, Ib } }, 3155 { "(bad)", { XX } }, 3156 }, 3157 3158 /* PREFIX_0F3A0D */ 3159 { 3160 { "(bad)", { XX } }, 3161 { "(bad)", { XX } }, 3162 { "blendpd", { XM, EXx, Ib } }, 3163 { "(bad)", { XX } }, 3164 }, 3165 3166 /* PREFIX_0F3A0E */ 3167 { 3168 { "(bad)", { XX } }, 3169 { "(bad)", { XX } }, 3170 { "pblendw", { XM, EXx, Ib } }, 3171 { "(bad)", { XX } }, 3172 }, 3173 3174 /* PREFIX_0F3A14 */ 3175 { 3176 { "(bad)", { XX } }, 3177 { "(bad)", { XX } }, 3178 { "pextrb", { Edqb, XM, Ib } }, 3179 { "(bad)", { XX } }, 3180 }, 3181 3182 /* PREFIX_0F3A15 */ 3183 { 3184 { "(bad)", { XX } }, 3185 { "(bad)", { XX } }, 3186 { "pextrw", { Edqw, XM, Ib } }, 3187 { "(bad)", { XX } }, 3188 }, 3189 3190 /* PREFIX_0F3A16 */ 3191 { 3192 { "(bad)", { XX } }, 3193 { "(bad)", { XX } }, 3194 { "pextrK", { Edq, XM, Ib } }, 3195 { "(bad)", { XX } }, 3196 }, 3197 3198 /* PREFIX_0F3A17 */ 3199 { 3200 { "(bad)", { XX } }, 3201 { "(bad)", { XX } }, 3202 { "extractps", { Edqd, XM, Ib } }, 3203 { "(bad)", { XX } }, 3204 }, 3205 3206 /* PREFIX_0F3A20 */ 3207 { 3208 { "(bad)", { XX } }, 3209 { "(bad)", { XX } }, 3210 { "pinsrb", { XM, Edqb, Ib } }, 3211 { "(bad)", { XX } }, 3212 }, 3213 3214 /* PREFIX_0F3A21 */ 3215 { 3216 { "(bad)", { XX } }, 3217 { "(bad)", { XX } }, 3218 { "insertps", { XM, EXd, Ib } }, 3219 { "(bad)", { XX } }, 3220 }, 3221 3222 /* PREFIX_0F3A22 */ 3223 { 3224 { "(bad)", { XX } }, 3225 { "(bad)", { XX } }, 3226 { "pinsrK", { XM, Edq, Ib } }, 3227 { "(bad)", { XX } }, 3228 }, 3229 3230 /* PREFIX_0F3A40 */ 3231 { 3232 { "(bad)", { XX } }, 3233 { "(bad)", { XX } }, 3234 { "dpps", { XM, EXx, Ib } }, 3235 { "(bad)", { XX } }, 3236 }, 3237 3238 /* PREFIX_0F3A41 */ 3239 { 3240 { "(bad)", { XX } }, 3241 { "(bad)", { XX } }, 3242 { "dppd", { XM, EXx, Ib } }, 3243 { "(bad)", { XX } }, 3244 }, 3245 3246 /* PREFIX_0F3A42 */ 3247 { 3248 { "(bad)", { XX } }, 3249 { "(bad)", { XX } }, 3250 { "mpsadbw", { XM, EXx, Ib } }, 3251 { "(bad)", { XX } }, 3252 }, 3253 3254 /* PREFIX_0F3A44 */ 3255 { 3256 { "(bad)", { XX } }, 3257 { "(bad)", { XX } }, 3258 { "pclmulqdq", { XM, EXx, PCLMUL } }, 3259 { "(bad)", { XX } }, 3260 }, 3261 3262 /* PREFIX_0F3A60 */ 3263 { 3264 { "(bad)", { XX } }, 3265 { "(bad)", { XX } }, 3266 { "pcmpestrm", { XM, EXx, Ib } }, 3267 { "(bad)", { XX } }, 3268 }, 3269 3270 /* PREFIX_0F3A61 */ 3271 { 3272 { "(bad)", { XX } }, 3273 { "(bad)", { XX } }, 3274 { "pcmpestri", { XM, EXx, Ib } }, 3275 { "(bad)", { XX } }, 3276 }, 3277 3278 /* PREFIX_0F3A62 */ 3279 { 3280 { "(bad)", { XX } }, 3281 { "(bad)", { XX } }, 3282 { "pcmpistrm", { XM, EXx, Ib } }, 3283 { "(bad)", { XX } }, 3284 }, 3285 3286 /* PREFIX_0F3A63 */ 3287 { 3288 { "(bad)", { XX } }, 3289 { "(bad)", { XX } }, 3290 { "pcmpistri", { XM, EXx, Ib } }, 3291 { "(bad)", { XX } }, 3292 }, 3293 3294 /* PREFIX_0F3ADF */ 3295 { 3296 { "(bad)", { XX } }, 3297 { "(bad)", { XX } }, 3298 { "aeskeygenassist", { XM, EXx, Ib } }, 3299 { "(bad)", { XX } }, 3300 }, 3301 3302 /* PREFIX_VEX_10 */ 3303 { 3304 { "vmovups", { XM, EXx } }, 3305 { VEX_LEN_TABLE (VEX_LEN_10_P_1) }, 3306 { "vmovupd", { XM, EXx } }, 3307 { VEX_LEN_TABLE (VEX_LEN_10_P_3) }, 3308 }, 3309 3310 /* PREFIX_VEX_11 */ 3311 { 3312 { "vmovups", { EXxS, XM } }, 3313 { VEX_LEN_TABLE (VEX_LEN_11_P_1) }, 3314 { "vmovupd", { EXxS, XM } }, 3315 { VEX_LEN_TABLE (VEX_LEN_11_P_3) }, 3316 }, 3317 3318 /* PREFIX_VEX_12 */ 3319 { 3320 { MOD_TABLE (MOD_VEX_12_PREFIX_0) }, 3321 { "vmovsldup", { XM, EXx } }, 3322 { VEX_LEN_TABLE (VEX_LEN_12_P_2) }, 3323 { "vmovddup", { XM, EXymmq } }, 3324 }, 3325 3326 /* PREFIX_VEX_16 */ 3327 { 3328 { MOD_TABLE (MOD_VEX_16_PREFIX_0) }, 3329 { "vmovshdup", { XM, EXx } }, 3330 { VEX_LEN_TABLE (VEX_LEN_16_P_2) }, 3331 { "(bad)", { XX } }, 3332 }, 3333 3334 /* PREFIX_VEX_2A */ 3335 { 3336 { "(bad)", { XX } }, 3337 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) }, 3338 { "(bad)", { XX } }, 3339 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) }, 3340 }, 3341 3342 /* PREFIX_VEX_2C */ 3343 { 3344 { "(bad)", { XX } }, 3345 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) }, 3346 { "(bad)", { XX } }, 3347 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) }, 3348 }, 3349 3350 /* PREFIX_VEX_2D */ 3351 { 3352 { "(bad)", { XX } }, 3353 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) }, 3354 { "(bad)", { XX } }, 3355 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) }, 3356 }, 3357 3358 /* PREFIX_VEX_2E */ 3359 { 3360 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) }, 3361 { "(bad)", { XX } }, 3362 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) }, 3363 { "(bad)", { XX } }, 3364 }, 3365 3366 /* PREFIX_VEX_2F */ 3367 { 3368 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) }, 3369 { "(bad)", { XX } }, 3370 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) }, 3371 { "(bad)", { XX } }, 3372 }, 3373 3374 /* PREFIX_VEX_51 */ 3375 { 3376 { "vsqrtps", { XM, EXx } }, 3377 { VEX_LEN_TABLE (VEX_LEN_51_P_1) }, 3378 { "vsqrtpd", { XM, EXx } }, 3379 { VEX_LEN_TABLE (VEX_LEN_51_P_3) }, 3380 }, 3381 3382 /* PREFIX_VEX_52 */ 3383 { 3384 { "vrsqrtps", { XM, EXx } }, 3385 { VEX_LEN_TABLE (VEX_LEN_52_P_1) }, 3386 { "(bad)", { XX } }, 3387 { "(bad)", { XX } }, 3388 }, 3389 3390 /* PREFIX_VEX_53 */ 3391 { 3392 { "vrcpps", { XM, EXx } }, 3393 { VEX_LEN_TABLE (VEX_LEN_53_P_1) }, 3394 { "(bad)", { XX } }, 3395 { "(bad)", { XX } }, 3396 }, 3397 3398 /* PREFIX_VEX_58 */ 3399 { 3400 { "vaddps", { XM, Vex, EXx } }, 3401 { VEX_LEN_TABLE (VEX_LEN_58_P_1) }, 3402 { "vaddpd", { XM, Vex, EXx } }, 3403 { VEX_LEN_TABLE (VEX_LEN_58_P_3) }, 3404 }, 3405 3406 /* PREFIX_VEX_59 */ 3407 { 3408 { "vmulps", { XM, Vex, EXx } }, 3409 { VEX_LEN_TABLE (VEX_LEN_59_P_1) }, 3410 { "vmulpd", { XM, Vex, EXx } }, 3411 { VEX_LEN_TABLE (VEX_LEN_59_P_3) }, 3412 }, 3413 3414 /* PREFIX_VEX_5A */ 3415 { 3416 { "vcvtps2pd", { XM, EXxmmq } }, 3417 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) }, 3418 { "vcvtpd2ps%XY", { XMM, EXx } }, 3419 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) }, 3420 }, 3421 3422 /* PREFIX_VEX_5B */ 3423 { 3424 { "vcvtdq2ps", { XM, EXx } }, 3425 { "vcvttps2dq", { XM, EXx } }, 3426 { "vcvtps2dq", { XM, EXx } }, 3427 { "(bad)", { XX } }, 3428 }, 3429 3430 /* PREFIX_VEX_5C */ 3431 { 3432 { "vsubps", { XM, Vex, EXx } }, 3433 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) }, 3434 { "vsubpd", { XM, Vex, EXx } }, 3435 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) }, 3436 }, 3437 3438 /* PREFIX_VEX_5D */ 3439 { 3440 { "vminps", { XM, Vex, EXx } }, 3441 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) }, 3442 { "vminpd", { XM, Vex, EXx } }, 3443 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) }, 3444 }, 3445 3446 /* PREFIX_VEX_5E */ 3447 { 3448 { "vdivps", { XM, Vex, EXx } }, 3449 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) }, 3450 { "vdivpd", { XM, Vex, EXx } }, 3451 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) }, 3452 }, 3453 3454 /* PREFIX_VEX_5F */ 3455 { 3456 { "vmaxps", { XM, Vex, EXx } }, 3457 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) }, 3458 { "vmaxpd", { XM, Vex, EXx } }, 3459 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) }, 3460 }, 3461 3462 /* PREFIX_VEX_60 */ 3463 { 3464 { "(bad)", { XX } }, 3465 { "(bad)", { XX } }, 3466 { VEX_LEN_TABLE (VEX_LEN_60_P_2) }, 3467 { "(bad)", { XX } }, 3468 }, 3469 3470 /* PREFIX_VEX_61 */ 3471 { 3472 { "(bad)", { XX } }, 3473 { "(bad)", { XX } }, 3474 { VEX_LEN_TABLE (VEX_LEN_61_P_2) }, 3475 { "(bad)", { XX } }, 3476 }, 3477 3478 /* PREFIX_VEX_62 */ 3479 { 3480 { "(bad)", { XX } }, 3481 { "(bad)", { XX } }, 3482 { VEX_LEN_TABLE (VEX_LEN_62_P_2) }, 3483 { "(bad)", { XX } }, 3484 }, 3485 3486 /* PREFIX_VEX_63 */ 3487 { 3488 { "(bad)", { XX } }, 3489 { "(bad)", { XX } }, 3490 { VEX_LEN_TABLE (VEX_LEN_63_P_2) }, 3491 { "(bad)", { XX } }, 3492 }, 3493 3494 /* PREFIX_VEX_64 */ 3495 { 3496 { "(bad)", { XX } }, 3497 { "(bad)", { XX } }, 3498 { VEX_LEN_TABLE (VEX_LEN_64_P_2) }, 3499 { "(bad)", { XX } }, 3500 }, 3501 3502 /* PREFIX_VEX_65 */ 3503 { 3504 { "(bad)", { XX } }, 3505 { "(bad)", { XX } }, 3506 { VEX_LEN_TABLE (VEX_LEN_65_P_2) }, 3507 { "(bad)", { XX } }, 3508 }, 3509 3510 /* PREFIX_VEX_66 */ 3511 { 3512 { "(bad)", { XX } }, 3513 { "(bad)", { XX } }, 3514 { VEX_LEN_TABLE (VEX_LEN_66_P_2) }, 3515 { "(bad)", { XX } }, 3516 }, 3517 3518 /* PREFIX_VEX_67 */ 3519 { 3520 { "(bad)", { XX } }, 3521 { "(bad)", { XX } }, 3522 { VEX_LEN_TABLE (VEX_LEN_67_P_2) }, 3523 { "(bad)", { XX } }, 3524 }, 3525 3526 /* PREFIX_VEX_68 */ 3527 { 3528 { "(bad)", { XX } }, 3529 { "(bad)", { XX } }, 3530 { VEX_LEN_TABLE (VEX_LEN_68_P_2) }, 3531 { "(bad)", { XX } }, 3532 }, 3533 3534 /* PREFIX_VEX_69 */ 3535 { 3536 { "(bad)", { XX } }, 3537 { "(bad)", { XX } }, 3538 { VEX_LEN_TABLE (VEX_LEN_69_P_2) }, 3539 { "(bad)", { XX } }, 3540 }, 3541 3542 /* PREFIX_VEX_6A */ 3543 { 3544 { "(bad)", { XX } }, 3545 { "(bad)", { XX } }, 3546 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) }, 3547 { "(bad)", { XX } }, 3548 }, 3549 3550 /* PREFIX_VEX_6B */ 3551 { 3552 { "(bad)", { XX } }, 3553 { "(bad)", { XX } }, 3554 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) }, 3555 { "(bad)", { XX } }, 3556 }, 3557 3558 /* PREFIX_VEX_6C */ 3559 { 3560 { "(bad)", { XX } }, 3561 { "(bad)", { XX } }, 3562 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) }, 3563 { "(bad)", { XX } }, 3564 }, 3565 3566 /* PREFIX_VEX_6D */ 3567 { 3568 { "(bad)", { XX } }, 3569 { "(bad)", { XX } }, 3570 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) }, 3571 { "(bad)", { XX } }, 3572 }, 3573 3574 /* PREFIX_VEX_6E */ 3575 { 3576 { "(bad)", { XX } }, 3577 { "(bad)", { XX } }, 3578 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) }, 3579 { "(bad)", { XX } }, 3580 }, 3581 3582 /* PREFIX_VEX_6F */ 3583 { 3584 { "(bad)", { XX } }, 3585 { "vmovdqu", { XM, EXx } }, 3586 { "vmovdqa", { XM, EXx } }, 3587 { "(bad)", { XX } }, 3588 }, 3589 3590 /* PREFIX_VEX_70 */ 3591 { 3592 { "(bad)", { XX } }, 3593 { VEX_LEN_TABLE (VEX_LEN_70_P_1) }, 3594 { VEX_LEN_TABLE (VEX_LEN_70_P_2) }, 3595 { VEX_LEN_TABLE (VEX_LEN_70_P_3) }, 3596 }, 3597 3598 /* PREFIX_VEX_71_REG_2 */ 3599 { 3600 { "(bad)", { XX } }, 3601 { "(bad)", { XX } }, 3602 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) }, 3603 { "(bad)", { XX } }, 3604 }, 3605 3606 /* PREFIX_VEX_71_REG_4 */ 3607 { 3608 { "(bad)", { XX } }, 3609 { "(bad)", { XX } }, 3610 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) }, 3611 { "(bad)", { XX } }, 3612 }, 3613 3614 /* PREFIX_VEX_71_REG_6 */ 3615 { 3616 { "(bad)", { XX } }, 3617 { "(bad)", { XX } }, 3618 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) }, 3619 { "(bad)", { XX } }, 3620 }, 3621 3622 /* PREFIX_VEX_72_REG_2 */ 3623 { 3624 { "(bad)", { XX } }, 3625 { "(bad)", { XX } }, 3626 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) }, 3627 { "(bad)", { XX } }, 3628 }, 3629 3630 /* PREFIX_VEX_72_REG_4 */ 3631 { 3632 { "(bad)", { XX } }, 3633 { "(bad)", { XX } }, 3634 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) }, 3635 { "(bad)", { XX } }, 3636 }, 3637 3638 /* PREFIX_VEX_72_REG_6 */ 3639 { 3640 { "(bad)", { XX } }, 3641 { "(bad)", { XX } }, 3642 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) }, 3643 { "(bad)", { XX } }, 3644 }, 3645 3646 /* PREFIX_VEX_73_REG_2 */ 3647 { 3648 { "(bad)", { XX } }, 3649 { "(bad)", { XX } }, 3650 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) }, 3651 { "(bad)", { XX } }, 3652 }, 3653 3654 /* PREFIX_VEX_73_REG_3 */ 3655 { 3656 { "(bad)", { XX } }, 3657 { "(bad)", { XX } }, 3658 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) }, 3659 { "(bad)", { XX } }, 3660 }, 3661 3662 /* PREFIX_VEX_73_REG_6 */ 3663 { 3664 { "(bad)", { XX } }, 3665 { "(bad)", { XX } }, 3666 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) }, 3667 { "(bad)", { XX } }, 3668 }, 3669 3670 /* PREFIX_VEX_73_REG_7 */ 3671 { 3672 { "(bad)", { XX } }, 3673 { "(bad)", { XX } }, 3674 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) }, 3675 { "(bad)", { XX } }, 3676 }, 3677 3678 /* PREFIX_VEX_74 */ 3679 { 3680 { "(bad)", { XX } }, 3681 { "(bad)", { XX } }, 3682 { VEX_LEN_TABLE (VEX_LEN_74_P_2) }, 3683 { "(bad)", { XX } }, 3684 }, 3685 3686 /* PREFIX_VEX_75 */ 3687 { 3688 { "(bad)", { XX } }, 3689 { "(bad)", { XX } }, 3690 { VEX_LEN_TABLE (VEX_LEN_75_P_2) }, 3691 { "(bad)", { XX } }, 3692 }, 3693 3694 /* PREFIX_VEX_76 */ 3695 { 3696 { "(bad)", { XX } }, 3697 { "(bad)", { XX } }, 3698 { VEX_LEN_TABLE (VEX_LEN_76_P_2) }, 3699 { "(bad)", { XX } }, 3700 }, 3701 3702 /* PREFIX_VEX_77 */ 3703 { 3704 { "", { VZERO } }, 3705 { "(bad)", { XX } }, 3706 { "(bad)", { XX } }, 3707 { "(bad)", { XX } }, 3708 }, 3709 3710 /* PREFIX_VEX_7C */ 3711 { 3712 { "(bad)", { XX } }, 3713 { "(bad)", { XX } }, 3714 { "vhaddpd", { XM, Vex, EXx } }, 3715 { "vhaddps", { XM, Vex, EXx } }, 3716 }, 3717 3718 /* PREFIX_VEX_7D */ 3719 { 3720 { "(bad)", { XX } }, 3721 { "(bad)", { XX } }, 3722 { "vhsubpd", { XM, Vex, EXx } }, 3723 { "vhsubps", { XM, Vex, EXx } }, 3724 }, 3725 3726 /* PREFIX_VEX_7E */ 3727 { 3728 { "(bad)", { XX } }, 3729 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) }, 3730 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) }, 3731 { "(bad)", { XX } }, 3732 }, 3733 3734 /* PREFIX_VEX_7F */ 3735 { 3736 { "(bad)", { XX } }, 3737 { "vmovdqu", { EXxS, XM } }, 3738 { "vmovdqa", { EXxS, XM } }, 3739 { "(bad)", { XX } }, 3740 }, 3741 3742 /* PREFIX_VEX_C2 */ 3743 { 3744 { "vcmpps", { XM, Vex, EXx, VCMP } }, 3745 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) }, 3746 { "vcmppd", { XM, Vex, EXx, VCMP } }, 3747 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) }, 3748 }, 3749 3750 /* PREFIX_VEX_C4 */ 3751 { 3752 { "(bad)", { XX } }, 3753 { "(bad)", { XX } }, 3754 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) }, 3755 { "(bad)", { XX } }, 3756 }, 3757 3758 /* PREFIX_VEX_C5 */ 3759 { 3760 { "(bad)", { XX } }, 3761 { "(bad)", { XX } }, 3762 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) }, 3763 { "(bad)", { XX } }, 3764 }, 3765 3766 /* PREFIX_VEX_D0 */ 3767 { 3768 { "(bad)", { XX } }, 3769 { "(bad)", { XX } }, 3770 { "vaddsubpd", { XM, Vex, EXx } }, 3771 { "vaddsubps", { XM, Vex, EXx } }, 3772 }, 3773 3774 /* PREFIX_VEX_D1 */ 3775 { 3776 { "(bad)", { XX } }, 3777 { "(bad)", { XX } }, 3778 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) }, 3779 { "(bad)", { XX } }, 3780 }, 3781 3782 /* PREFIX_VEX_D2 */ 3783 { 3784 { "(bad)", { XX } }, 3785 { "(bad)", { XX } }, 3786 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) }, 3787 { "(bad)", { XX } }, 3788 }, 3789 3790 /* PREFIX_VEX_D3 */ 3791 { 3792 { "(bad)", { XX } }, 3793 { "(bad)", { XX } }, 3794 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) }, 3795 { "(bad)", { XX } }, 3796 }, 3797 3798 /* PREFIX_VEX_D4 */ 3799 { 3800 { "(bad)", { XX } }, 3801 { "(bad)", { XX } }, 3802 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) }, 3803 { "(bad)", { XX } }, 3804 }, 3805 3806 /* PREFIX_VEX_D5 */ 3807 { 3808 { "(bad)", { XX } }, 3809 { "(bad)", { XX } }, 3810 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) }, 3811 { "(bad)", { XX } }, 3812 }, 3813 3814 /* PREFIX_VEX_D6 */ 3815 { 3816 { "(bad)", { XX } }, 3817 { "(bad)", { XX } }, 3818 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) }, 3819 { "(bad)", { XX } }, 3820 }, 3821 3822 /* PREFIX_VEX_D7 */ 3823 { 3824 { "(bad)", { XX } }, 3825 { "(bad)", { XX } }, 3826 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) }, 3827 { "(bad)", { XX } }, 3828 }, 3829 3830 /* PREFIX_VEX_D8 */ 3831 { 3832 { "(bad)", { XX } }, 3833 { "(bad)", { XX } }, 3834 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) }, 3835 { "(bad)", { XX } }, 3836 }, 3837 3838 /* PREFIX_VEX_D9 */ 3839 { 3840 { "(bad)", { XX } }, 3841 { "(bad)", { XX } }, 3842 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) }, 3843 { "(bad)", { XX } }, 3844 }, 3845 3846 /* PREFIX_VEX_DA */ 3847 { 3848 { "(bad)", { XX } }, 3849 { "(bad)", { XX } }, 3850 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) }, 3851 { "(bad)", { XX } }, 3852 }, 3853 3854 /* PREFIX_VEX_DB */ 3855 { 3856 { "(bad)", { XX } }, 3857 { "(bad)", { XX } }, 3858 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) }, 3859 { "(bad)", { XX } }, 3860 }, 3861 3862 /* PREFIX_VEX_DC */ 3863 { 3864 { "(bad)", { XX } }, 3865 { "(bad)", { XX } }, 3866 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) }, 3867 { "(bad)", { XX } }, 3868 }, 3869 3870 /* PREFIX_VEX_DD */ 3871 { 3872 { "(bad)", { XX } }, 3873 { "(bad)", { XX } }, 3874 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) }, 3875 { "(bad)", { XX } }, 3876 }, 3877 3878 /* PREFIX_VEX_DE */ 3879 { 3880 { "(bad)", { XX } }, 3881 { "(bad)", { XX } }, 3882 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) }, 3883 { "(bad)", { XX } }, 3884 }, 3885 3886 /* PREFIX_VEX_DF */ 3887 { 3888 { "(bad)", { XX } }, 3889 { "(bad)", { XX } }, 3890 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) }, 3891 { "(bad)", { XX } }, 3892 }, 3893 3894 /* PREFIX_VEX_E0 */ 3895 { 3896 { "(bad)", { XX } }, 3897 { "(bad)", { XX } }, 3898 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) }, 3899 { "(bad)", { XX } }, 3900 }, 3901 3902 /* PREFIX_VEX_E1 */ 3903 { 3904 { "(bad)", { XX } }, 3905 { "(bad)", { XX } }, 3906 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) }, 3907 { "(bad)", { XX } }, 3908 }, 3909 3910 /* PREFIX_VEX_E2 */ 3911 { 3912 { "(bad)", { XX } }, 3913 { "(bad)", { XX } }, 3914 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) }, 3915 { "(bad)", { XX } }, 3916 }, 3917 3918 /* PREFIX_VEX_E3 */ 3919 { 3920 { "(bad)", { XX } }, 3921 { "(bad)", { XX } }, 3922 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) }, 3923 { "(bad)", { XX } }, 3924 }, 3925 3926 /* PREFIX_VEX_E4 */ 3927 { 3928 { "(bad)", { XX } }, 3929 { "(bad)", { XX } }, 3930 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) }, 3931 { "(bad)", { XX } }, 3932 }, 3933 3934 /* PREFIX_VEX_E5 */ 3935 { 3936 { "(bad)", { XX } }, 3937 { "(bad)", { XX } }, 3938 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) }, 3939 { "(bad)", { XX } }, 3940 }, 3941 3942 /* PREFIX_VEX_E6 */ 3943 { 3944 { "(bad)", { XX } }, 3945 { "vcvtdq2pd", { XM, EXxmmq } }, 3946 { "vcvttpd2dq%XY", { XMM, EXx } }, 3947 { "vcvtpd2dq%XY", { XMM, EXx } }, 3948 }, 3949 3950 /* PREFIX_VEX_E7 */ 3951 { 3952 { "(bad)", { XX } }, 3953 { "(bad)", { XX } }, 3954 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) }, 3955 { "(bad)", { XX } }, 3956 }, 3957 3958 /* PREFIX_VEX_E8 */ 3959 { 3960 { "(bad)", { XX } }, 3961 { "(bad)", { XX } }, 3962 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) }, 3963 { "(bad)", { XX } }, 3964 }, 3965 3966 /* PREFIX_VEX_E9 */ 3967 { 3968 { "(bad)", { XX } }, 3969 { "(bad)", { XX } }, 3970 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) }, 3971 { "(bad)", { XX } }, 3972 }, 3973 3974 /* PREFIX_VEX_EA */ 3975 { 3976 { "(bad)", { XX } }, 3977 { "(bad)", { XX } }, 3978 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) }, 3979 { "(bad)", { XX } }, 3980 }, 3981 3982 /* PREFIX_VEX_EB */ 3983 { 3984 { "(bad)", { XX } }, 3985 { "(bad)", { XX } }, 3986 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) }, 3987 { "(bad)", { XX } }, 3988 }, 3989 3990 /* PREFIX_VEX_EC */ 3991 { 3992 { "(bad)", { XX } }, 3993 { "(bad)", { XX } }, 3994 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) }, 3995 { "(bad)", { XX } }, 3996 }, 3997 3998 /* PREFIX_VEX_ED */ 3999 { 4000 { "(bad)", { XX } }, 4001 { "(bad)", { XX } }, 4002 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) }, 4003 { "(bad)", { XX } }, 4004 }, 4005 4006 /* PREFIX_VEX_EE */ 4007 { 4008 { "(bad)", { XX } }, 4009 { "(bad)", { XX } }, 4010 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) }, 4011 { "(bad)", { XX } }, 4012 }, 4013 4014 /* PREFIX_VEX_EF */ 4015 { 4016 { "(bad)", { XX } }, 4017 { "(bad)", { XX } }, 4018 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) }, 4019 { "(bad)", { XX } }, 4020 }, 4021 4022 /* PREFIX_VEX_F0 */ 4023 { 4024 { "(bad)", { XX } }, 4025 { "(bad)", { XX } }, 4026 { "(bad)", { XX } }, 4027 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) }, 4028 }, 4029 4030 /* PREFIX_VEX_F1 */ 4031 { 4032 { "(bad)", { XX } }, 4033 { "(bad)", { XX } }, 4034 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) }, 4035 { "(bad)", { XX } }, 4036 }, 4037 4038 /* PREFIX_VEX_F2 */ 4039 { 4040 { "(bad)", { XX } }, 4041 { "(bad)", { XX } }, 4042 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) }, 4043 { "(bad)", { XX } }, 4044 }, 4045 4046 /* PREFIX_VEX_F3 */ 4047 { 4048 { "(bad)", { XX } }, 4049 { "(bad)", { XX } }, 4050 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) }, 4051 { "(bad)", { XX } }, 4052 }, 4053 4054 /* PREFIX_VEX_F4 */ 4055 { 4056 { "(bad)", { XX } }, 4057 { "(bad)", { XX } }, 4058 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) }, 4059 { "(bad)", { XX } }, 4060 }, 4061 4062 /* PREFIX_VEX_F5 */ 4063 { 4064 { "(bad)", { XX } }, 4065 { "(bad)", { XX } }, 4066 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) }, 4067 { "(bad)", { XX } }, 4068 }, 4069 4070 /* PREFIX_VEX_F6 */ 4071 { 4072 { "(bad)", { XX } }, 4073 { "(bad)", { XX } }, 4074 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) }, 4075 { "(bad)", { XX } }, 4076 }, 4077 4078 /* PREFIX_VEX_F7 */ 4079 { 4080 { "(bad)", { XX } }, 4081 { "(bad)", { XX } }, 4082 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) }, 4083 { "(bad)", { XX } }, 4084 }, 4085 4086 /* PREFIX_VEX_F8 */ 4087 { 4088 { "(bad)", { XX } }, 4089 { "(bad)", { XX } }, 4090 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) }, 4091 { "(bad)", { XX } }, 4092 }, 4093 4094 /* PREFIX_VEX_F9 */ 4095 { 4096 { "(bad)", { XX } }, 4097 { "(bad)", { XX } }, 4098 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) }, 4099 { "(bad)", { XX } }, 4100 }, 4101 4102 /* PREFIX_VEX_FA */ 4103 { 4104 { "(bad)", { XX } }, 4105 { "(bad)", { XX } }, 4106 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) }, 4107 { "(bad)", { XX } }, 4108 }, 4109 4110 /* PREFIX_VEX_FB */ 4111 { 4112 { "(bad)", { XX } }, 4113 { "(bad)", { XX } }, 4114 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) }, 4115 { "(bad)", { XX } }, 4116 }, 4117 4118 /* PREFIX_VEX_FC */ 4119 { 4120 { "(bad)", { XX } }, 4121 { "(bad)", { XX } }, 4122 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) }, 4123 { "(bad)", { XX } }, 4124 }, 4125 4126 /* PREFIX_VEX_FD */ 4127 { 4128 { "(bad)", { XX } }, 4129 { "(bad)", { XX } }, 4130 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) }, 4131 { "(bad)", { XX } }, 4132 }, 4133 4134 /* PREFIX_VEX_FE */ 4135 { 4136 { "(bad)", { XX } }, 4137 { "(bad)", { XX } }, 4138 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) }, 4139 { "(bad)", { XX } }, 4140 }, 4141 4142 /* PREFIX_VEX_3800 */ 4143 { 4144 { "(bad)", { XX } }, 4145 { "(bad)", { XX } }, 4146 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) }, 4147 { "(bad)", { XX } }, 4148 }, 4149 4150 /* PREFIX_VEX_3801 */ 4151 { 4152 { "(bad)", { XX } }, 4153 { "(bad)", { XX } }, 4154 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) }, 4155 { "(bad)", { XX } }, 4156 }, 4157 4158 /* PREFIX_VEX_3802 */ 4159 { 4160 { "(bad)", { XX } }, 4161 { "(bad)", { XX } }, 4162 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) }, 4163 { "(bad)", { XX } }, 4164 }, 4165 4166 /* PREFIX_VEX_3803 */ 4167 { 4168 { "(bad)", { XX } }, 4169 { "(bad)", { XX } }, 4170 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) }, 4171 { "(bad)", { XX } }, 4172 }, 4173 4174 /* PREFIX_VEX_3804 */ 4175 { 4176 { "(bad)", { XX } }, 4177 { "(bad)", { XX } }, 4178 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) }, 4179 { "(bad)", { XX } }, 4180 }, 4181 4182 /* PREFIX_VEX_3805 */ 4183 { 4184 { "(bad)", { XX } }, 4185 { "(bad)", { XX } }, 4186 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) }, 4187 { "(bad)", { XX } }, 4188 }, 4189 4190 /* PREFIX_VEX_3806 */ 4191 { 4192 { "(bad)", { XX } }, 4193 { "(bad)", { XX } }, 4194 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) }, 4195 { "(bad)", { XX } }, 4196 }, 4197 4198 /* PREFIX_VEX_3807 */ 4199 { 4200 { "(bad)", { XX } }, 4201 { "(bad)", { XX } }, 4202 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) }, 4203 { "(bad)", { XX } }, 4204 }, 4205 4206 /* PREFIX_VEX_3808 */ 4207 { 4208 { "(bad)", { XX } }, 4209 { "(bad)", { XX } }, 4210 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) }, 4211 { "(bad)", { XX } }, 4212 }, 4213 4214 /* PREFIX_VEX_3809 */ 4215 { 4216 { "(bad)", { XX } }, 4217 { "(bad)", { XX } }, 4218 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) }, 4219 { "(bad)", { XX } }, 4220 }, 4221 4222 /* PREFIX_VEX_380A */ 4223 { 4224 { "(bad)", { XX } }, 4225 { "(bad)", { XX } }, 4226 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) }, 4227 { "(bad)", { XX } }, 4228 }, 4229 4230 /* PREFIX_VEX_380B */ 4231 { 4232 { "(bad)", { XX } }, 4233 { "(bad)", { XX } }, 4234 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) }, 4235 { "(bad)", { XX } }, 4236 }, 4237 4238 /* PREFIX_VEX_380C */ 4239 { 4240 { "(bad)", { XX } }, 4241 { "(bad)", { XX } }, 4242 { "vpermilps", { XM, Vex, EXx } }, 4243 { "(bad)", { XX } }, 4244 }, 4245 4246 /* PREFIX_VEX_380D */ 4247 { 4248 { "(bad)", { XX } }, 4249 { "(bad)", { XX } }, 4250 { "vpermilpd", { XM, Vex, EXx } }, 4251 { "(bad)", { XX } }, 4252 }, 4253 4254 /* PREFIX_VEX_380E */ 4255 { 4256 { "(bad)", { XX } }, 4257 { "(bad)", { XX } }, 4258 { "vtestps", { XM, EXx } }, 4259 { "(bad)", { XX } }, 4260 }, 4261 4262 /* PREFIX_VEX_380F */ 4263 { 4264 { "(bad)", { XX } }, 4265 { "(bad)", { XX } }, 4266 { "vtestpd", { XM, EXx } }, 4267 { "(bad)", { XX } }, 4268 }, 4269 4270 /* PREFIX_VEX_3817 */ 4271 { 4272 { "(bad)", { XX } }, 4273 { "(bad)", { XX } }, 4274 { "vptest", { XM, EXx } }, 4275 { "(bad)", { XX } }, 4276 }, 4277 4278 /* PREFIX_VEX_3818 */ 4279 { 4280 { "(bad)", { XX } }, 4281 { "(bad)", { XX } }, 4282 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) }, 4283 { "(bad)", { XX } }, 4284 }, 4285 4286 /* PREFIX_VEX_3819 */ 4287 { 4288 { "(bad)", { XX } }, 4289 { "(bad)", { XX } }, 4290 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) }, 4291 { "(bad)", { XX } }, 4292 }, 4293 4294 /* PREFIX_VEX_381A */ 4295 { 4296 { "(bad)", { XX } }, 4297 { "(bad)", { XX } }, 4298 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) }, 4299 { "(bad)", { XX } }, 4300 }, 4301 4302 /* PREFIX_VEX_381C */ 4303 { 4304 { "(bad)", { XX } }, 4305 { "(bad)", { XX } }, 4306 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) }, 4307 { "(bad)", { XX } }, 4308 }, 4309 4310 /* PREFIX_VEX_381D */ 4311 { 4312 { "(bad)", { XX } }, 4313 { "(bad)", { XX } }, 4314 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) }, 4315 { "(bad)", { XX } }, 4316 }, 4317 4318 /* PREFIX_VEX_381E */ 4319 { 4320 { "(bad)", { XX } }, 4321 { "(bad)", { XX } }, 4322 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) }, 4323 { "(bad)", { XX } }, 4324 }, 4325 4326 /* PREFIX_VEX_3820 */ 4327 { 4328 { "(bad)", { XX } }, 4329 { "(bad)", { XX } }, 4330 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) }, 4331 { "(bad)", { XX } }, 4332 }, 4333 4334 /* PREFIX_VEX_3821 */ 4335 { 4336 { "(bad)", { XX } }, 4337 { "(bad)", { XX } }, 4338 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) }, 4339 { "(bad)", { XX } }, 4340 }, 4341 4342 /* PREFIX_VEX_3822 */ 4343 { 4344 { "(bad)", { XX } }, 4345 { "(bad)", { XX } }, 4346 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) }, 4347 { "(bad)", { XX } }, 4348 }, 4349 4350 /* PREFIX_VEX_3823 */ 4351 { 4352 { "(bad)", { XX } }, 4353 { "(bad)", { XX } }, 4354 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) }, 4355 { "(bad)", { XX } }, 4356 }, 4357 4358 /* PREFIX_VEX_3824 */ 4359 { 4360 { "(bad)", { XX } }, 4361 { "(bad)", { XX } }, 4362 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) }, 4363 { "(bad)", { XX } }, 4364 }, 4365 4366 /* PREFIX_VEX_3825 */ 4367 { 4368 { "(bad)", { XX } }, 4369 { "(bad)", { XX } }, 4370 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) }, 4371 { "(bad)", { XX } }, 4372 }, 4373 4374 /* PREFIX_VEX_3828 */ 4375 { 4376 { "(bad)", { XX } }, 4377 { "(bad)", { XX } }, 4378 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) }, 4379 { "(bad)", { XX } }, 4380 }, 4381 4382 /* PREFIX_VEX_3829 */ 4383 { 4384 { "(bad)", { XX } }, 4385 { "(bad)", { XX } }, 4386 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) }, 4387 { "(bad)", { XX } }, 4388 }, 4389 4390 /* PREFIX_VEX_382A */ 4391 { 4392 { "(bad)", { XX } }, 4393 { "(bad)", { XX } }, 4394 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) }, 4395 { "(bad)", { XX } }, 4396 }, 4397 4398 /* PREFIX_VEX_382B */ 4399 { 4400 { "(bad)", { XX } }, 4401 { "(bad)", { XX } }, 4402 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) }, 4403 { "(bad)", { XX } }, 4404 }, 4405 4406 /* PREFIX_VEX_382C */ 4407 { 4408 { "(bad)", { XX } }, 4409 { "(bad)", { XX } }, 4410 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) }, 4411 { "(bad)", { XX } }, 4412 }, 4413 4414 /* PREFIX_VEX_382D */ 4415 { 4416 { "(bad)", { XX } }, 4417 { "(bad)", { XX } }, 4418 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) }, 4419 { "(bad)", { XX } }, 4420 }, 4421 4422 /* PREFIX_VEX_382E */ 4423 { 4424 { "(bad)", { XX } }, 4425 { "(bad)", { XX } }, 4426 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) }, 4427 { "(bad)", { XX } }, 4428 }, 4429 4430 /* PREFIX_VEX_382F */ 4431 { 4432 { "(bad)", { XX } }, 4433 { "(bad)", { XX } }, 4434 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) }, 4435 { "(bad)", { XX } }, 4436 }, 4437 4438 /* PREFIX_VEX_3830 */ 4439 { 4440 { "(bad)", { XX } }, 4441 { "(bad)", { XX } }, 4442 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) }, 4443 { "(bad)", { XX } }, 4444 }, 4445 4446 /* PREFIX_VEX_3831 */ 4447 { 4448 { "(bad)", { XX } }, 4449 { "(bad)", { XX } }, 4450 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) }, 4451 { "(bad)", { XX } }, 4452 }, 4453 4454 /* PREFIX_VEX_3832 */ 4455 { 4456 { "(bad)", { XX } }, 4457 { "(bad)", { XX } }, 4458 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) }, 4459 { "(bad)", { XX } }, 4460 }, 4461 4462 /* PREFIX_VEX_3833 */ 4463 { 4464 { "(bad)", { XX } }, 4465 { "(bad)", { XX } }, 4466 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) }, 4467 { "(bad)", { XX } }, 4468 }, 4469 4470 /* PREFIX_VEX_3834 */ 4471 { 4472 { "(bad)", { XX } }, 4473 { "(bad)", { XX } }, 4474 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) }, 4475 { "(bad)", { XX } }, 4476 }, 4477 4478 /* PREFIX_VEX_3835 */ 4479 { 4480 { "(bad)", { XX } }, 4481 { "(bad)", { XX } }, 4482 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) }, 4483 { "(bad)", { XX } }, 4484 }, 4485 4486 /* PREFIX_VEX_3837 */ 4487 { 4488 { "(bad)", { XX } }, 4489 { "(bad)", { XX } }, 4490 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) }, 4491 { "(bad)", { XX } }, 4492 }, 4493 4494 /* PREFIX_VEX_3838 */ 4495 { 4496 { "(bad)", { XX } }, 4497 { "(bad)", { XX } }, 4498 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) }, 4499 { "(bad)", { XX } }, 4500 }, 4501 4502 /* PREFIX_VEX_3839 */ 4503 { 4504 { "(bad)", { XX } }, 4505 { "(bad)", { XX } }, 4506 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) }, 4507 { "(bad)", { XX } }, 4508 }, 4509 4510 /* PREFIX_VEX_383A */ 4511 { 4512 { "(bad)", { XX } }, 4513 { "(bad)", { XX } }, 4514 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) }, 4515 { "(bad)", { XX } }, 4516 }, 4517 4518 /* PREFIX_VEX_383B */ 4519 { 4520 { "(bad)", { XX } }, 4521 { "(bad)", { XX } }, 4522 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) }, 4523 { "(bad)", { XX } }, 4524 }, 4525 4526 /* PREFIX_VEX_383C */ 4527 { 4528 { "(bad)", { XX } }, 4529 { "(bad)", { XX } }, 4530 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) }, 4531 { "(bad)", { XX } }, 4532 }, 4533 4534 /* PREFIX_VEX_383D */ 4535 { 4536 { "(bad)", { XX } }, 4537 { "(bad)", { XX } }, 4538 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) }, 4539 { "(bad)", { XX } }, 4540 }, 4541 4542 /* PREFIX_VEX_383E */ 4543 { 4544 { "(bad)", { XX } }, 4545 { "(bad)", { XX } }, 4546 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) }, 4547 { "(bad)", { XX } }, 4548 }, 4549 4550 /* PREFIX_VEX_383F */ 4551 { 4552 { "(bad)", { XX } }, 4553 { "(bad)", { XX } }, 4554 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) }, 4555 { "(bad)", { XX } }, 4556 }, 4557 4558 /* PREFIX_VEX_3840 */ 4559 { 4560 { "(bad)", { XX } }, 4561 { "(bad)", { XX } }, 4562 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) }, 4563 { "(bad)", { XX } }, 4564 }, 4565 4566 /* PREFIX_VEX_3841 */ 4567 { 4568 { "(bad)", { XX } }, 4569 { "(bad)", { XX } }, 4570 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) }, 4571 { "(bad)", { XX } }, 4572 }, 4573 4574 /* PREFIX_VEX_3896 */ 4575 { 4576 { "(bad)", { XX } }, 4577 { "(bad)", { XX } }, 4578 { "vfmaddsub132p%XW", { XM, Vex, EXx } }, 4579 { "(bad)", { XX } }, 4580 }, 4581 4582 /* PREFIX_VEX_3897 */ 4583 { 4584 { "(bad)", { XX } }, 4585 { "(bad)", { XX } }, 4586 { "vfmsubadd132p%XW", { XM, Vex, EXx } }, 4587 { "(bad)", { XX } }, 4588 }, 4589 4590 /* PREFIX_VEX_3898 */ 4591 { 4592 { "(bad)", { XX } }, 4593 { "(bad)", { XX } }, 4594 { "vfmadd132p%XW", { XM, Vex, EXx } }, 4595 { "(bad)", { XX } }, 4596 }, 4597 4598 /* PREFIX_VEX_3899 */ 4599 { 4600 { "(bad)", { XX } }, 4601 { "(bad)", { XX } }, 4602 { "vfmadd132s%XW", { XM, Vex, EXVexWdq } }, 4603 { "(bad)", { XX } }, 4604 }, 4605 4606 /* PREFIX_VEX_389A */ 4607 { 4608 { "(bad)", { XX } }, 4609 { "(bad)", { XX } }, 4610 { "vfmsub132p%XW", { XM, Vex, EXx } }, 4611 { "(bad)", { XX } }, 4612 }, 4613 4614 /* PREFIX_VEX_389B */ 4615 { 4616 { "(bad)", { XX } }, 4617 { "(bad)", { XX } }, 4618 { "vfmsub132s%XW", { XM, Vex, EXVexWdq } }, 4619 { "(bad)", { XX } }, 4620 }, 4621 4622 /* PREFIX_VEX_389C */ 4623 { 4624 { "(bad)", { XX } }, 4625 { "(bad)", { XX } }, 4626 { "vfnmadd132p%XW", { XM, Vex, EXx } }, 4627 { "(bad)", { XX } }, 4628 }, 4629 4630 /* PREFIX_VEX_389D */ 4631 { 4632 { "(bad)", { XX } }, 4633 { "(bad)", { XX } }, 4634 { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } }, 4635 { "(bad)", { XX } }, 4636 }, 4637 4638 /* PREFIX_VEX_389E */ 4639 { 4640 { "(bad)", { XX } }, 4641 { "(bad)", { XX } }, 4642 { "vfnmsub132p%XW", { XM, Vex, EXx } }, 4643 { "(bad)", { XX } }, 4644 }, 4645 4646 /* PREFIX_VEX_389F */ 4647 { 4648 { "(bad)", { XX } }, 4649 { "(bad)", { XX } }, 4650 { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } }, 4651 { "(bad)", { XX } }, 4652 }, 4653 4654 /* PREFIX_VEX_38A6 */ 4655 { 4656 { "(bad)", { XX } }, 4657 { "(bad)", { XX } }, 4658 { "vfmaddsub213p%XW", { XM, Vex, EXx } }, 4659 { "(bad)", { XX } }, 4660 }, 4661 4662 /* PREFIX_VEX_38A7 */ 4663 { 4664 { "(bad)", { XX } }, 4665 { "(bad)", { XX } }, 4666 { "vfmsubadd213p%XW", { XM, Vex, EXx } }, 4667 { "(bad)", { XX } }, 4668 }, 4669 4670 /* PREFIX_VEX_38A8 */ 4671 { 4672 { "(bad)", { XX } }, 4673 { "(bad)", { XX } }, 4674 { "vfmadd213p%XW", { XM, Vex, EXx } }, 4675 { "(bad)", { XX } }, 4676 }, 4677 4678 /* PREFIX_VEX_38A9 */ 4679 { 4680 { "(bad)", { XX } }, 4681 { "(bad)", { XX } }, 4682 { "vfmadd213s%XW", { XM, Vex, EXVexWdq } }, 4683 { "(bad)", { XX } }, 4684 }, 4685 4686 /* PREFIX_VEX_38AA */ 4687 { 4688 { "(bad)", { XX } }, 4689 { "(bad)", { XX } }, 4690 { "vfmsub213p%XW", { XM, Vex, EXx } }, 4691 { "(bad)", { XX } }, 4692 }, 4693 4694 /* PREFIX_VEX_38AB */ 4695 { 4696 { "(bad)", { XX } }, 4697 { "(bad)", { XX } }, 4698 { "vfmsub213s%XW", { XM, Vex, EXVexWdq } }, 4699 { "(bad)", { XX } }, 4700 }, 4701 4702 /* PREFIX_VEX_38AC */ 4703 { 4704 { "(bad)", { XX } }, 4705 { "(bad)", { XX } }, 4706 { "vfnmadd213p%XW", { XM, Vex, EXx } }, 4707 { "(bad)", { XX } }, 4708 }, 4709 4710 /* PREFIX_VEX_38AD */ 4711 { 4712 { "(bad)", { XX } }, 4713 { "(bad)", { XX } }, 4714 { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } }, 4715 { "(bad)", { XX } }, 4716 }, 4717 4718 /* PREFIX_VEX_38AE */ 4719 { 4720 { "(bad)", { XX } }, 4721 { "(bad)", { XX } }, 4722 { "vfnmsub213p%XW", { XM, Vex, EXx } }, 4723 { "(bad)", { XX } }, 4724 }, 4725 4726 /* PREFIX_VEX_38AF */ 4727 { 4728 { "(bad)", { XX } }, 4729 { "(bad)", { XX } }, 4730 { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } }, 4731 { "(bad)", { XX } }, 4732 }, 4733 4734 /* PREFIX_VEX_38B6 */ 4735 { 4736 { "(bad)", { XX } }, 4737 { "(bad)", { XX } }, 4738 { "vfmaddsub231p%XW", { XM, Vex, EXx } }, 4739 { "(bad)", { XX } }, 4740 }, 4741 4742 /* PREFIX_VEX_38B7 */ 4743 { 4744 { "(bad)", { XX } }, 4745 { "(bad)", { XX } }, 4746 { "vfmsubadd231p%XW", { XM, Vex, EXx } }, 4747 { "(bad)", { XX } }, 4748 }, 4749 4750 /* PREFIX_VEX_38B8 */ 4751 { 4752 { "(bad)", { XX } }, 4753 { "(bad)", { XX } }, 4754 { "vfmadd231p%XW", { XM, Vex, EXx } }, 4755 { "(bad)", { XX } }, 4756 }, 4757 4758 /* PREFIX_VEX_38B9 */ 4759 { 4760 { "(bad)", { XX } }, 4761 { "(bad)", { XX } }, 4762 { "vfmadd231s%XW", { XM, Vex, EXVexWdq } }, 4763 { "(bad)", { XX } }, 4764 }, 4765 4766 /* PREFIX_VEX_38BA */ 4767 { 4768 { "(bad)", { XX } }, 4769 { "(bad)", { XX } }, 4770 { "vfmsub231p%XW", { XM, Vex, EXx } }, 4771 { "(bad)", { XX } }, 4772 }, 4773 4774 /* PREFIX_VEX_38BB */ 4775 { 4776 { "(bad)", { XX } }, 4777 { "(bad)", { XX } }, 4778 { "vfmsub231s%XW", { XM, Vex, EXVexWdq } }, 4779 { "(bad)", { XX } }, 4780 }, 4781 4782 /* PREFIX_VEX_38BC */ 4783 { 4784 { "(bad)", { XX } }, 4785 { "(bad)", { XX } }, 4786 { "vfnmadd231p%XW", { XM, Vex, EXx } }, 4787 { "(bad)", { XX } }, 4788 }, 4789 4790 /* PREFIX_VEX_38BD */ 4791 { 4792 { "(bad)", { XX } }, 4793 { "(bad)", { XX } }, 4794 { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } }, 4795 { "(bad)", { XX } }, 4796 }, 4797 4798 /* PREFIX_VEX_38BE */ 4799 { 4800 { "(bad)", { XX } }, 4801 { "(bad)", { XX } }, 4802 { "vfnmsub231p%XW", { XM, Vex, EXx } }, 4803 { "(bad)", { XX } }, 4804 }, 4805 4806 /* PREFIX_VEX_38BF */ 4807 { 4808 { "(bad)", { XX } }, 4809 { "(bad)", { XX } }, 4810 { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } }, 4811 { "(bad)", { XX } }, 4812 }, 4813 4814 /* PREFIX_VEX_38DB */ 4815 { 4816 { "(bad)", { XX } }, 4817 { "(bad)", { XX } }, 4818 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) }, 4819 { "(bad)", { XX } }, 4820 }, 4821 4822 /* PREFIX_VEX_38DC */ 4823 { 4824 { "(bad)", { XX } }, 4825 { "(bad)", { XX } }, 4826 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) }, 4827 { "(bad)", { XX } }, 4828 }, 4829 4830 /* PREFIX_VEX_38DD */ 4831 { 4832 { "(bad)", { XX } }, 4833 { "(bad)", { XX } }, 4834 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) }, 4835 { "(bad)", { XX } }, 4836 }, 4837 4838 /* PREFIX_VEX_38DE */ 4839 { 4840 { "(bad)", { XX } }, 4841 { "(bad)", { XX } }, 4842 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) }, 4843 { "(bad)", { XX } }, 4844 }, 4845 4846 /* PREFIX_VEX_38DF */ 4847 { 4848 { "(bad)", { XX } }, 4849 { "(bad)", { XX } }, 4850 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) }, 4851 { "(bad)", { XX } }, 4852 }, 4853 4854 /* PREFIX_VEX_3A04 */ 4855 { 4856 { "(bad)", { XX } }, 4857 { "(bad)", { XX } }, 4858 { "vpermilps", { XM, EXx, Ib } }, 4859 { "(bad)", { XX } }, 4860 }, 4861 4862 /* PREFIX_VEX_3A05 */ 4863 { 4864 { "(bad)", { XX } }, 4865 { "(bad)", { XX } }, 4866 { "vpermilpd", { XM, EXx, Ib } }, 4867 { "(bad)", { XX } }, 4868 }, 4869 4870 /* PREFIX_VEX_3A06 */ 4871 { 4872 { "(bad)", { XX } }, 4873 { "(bad)", { XX } }, 4874 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) }, 4875 { "(bad)", { XX } }, 4876 }, 4877 4878 /* PREFIX_VEX_3A08 */ 4879 { 4880 { "(bad)", { XX } }, 4881 { "(bad)", { XX } }, 4882 { "vroundps", { XM, EXx, Ib } }, 4883 { "(bad)", { XX } }, 4884 }, 4885 4886 /* PREFIX_VEX_3A09 */ 4887 { 4888 { "(bad)", { XX } }, 4889 { "(bad)", { XX } }, 4890 { "vroundpd", { XM, EXx, Ib } }, 4891 { "(bad)", { XX } }, 4892 }, 4893 4894 /* PREFIX_VEX_3A0A */ 4895 { 4896 { "(bad)", { XX } }, 4897 { "(bad)", { XX } }, 4898 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) }, 4899 { "(bad)", { XX } }, 4900 }, 4901 4902 /* PREFIX_VEX_3A0B */ 4903 { 4904 { "(bad)", { XX } }, 4905 { "(bad)", { XX } }, 4906 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) }, 4907 { "(bad)", { XX } }, 4908 }, 4909 4910 /* PREFIX_VEX_3A0C */ 4911 { 4912 { "(bad)", { XX } }, 4913 { "(bad)", { XX } }, 4914 { "vblendps", { XM, Vex, EXx, Ib } }, 4915 { "(bad)", { XX } }, 4916 }, 4917 4918 /* PREFIX_VEX_3A0D */ 4919 { 4920 { "(bad)", { XX } }, 4921 { "(bad)", { XX } }, 4922 { "vblendpd", { XM, Vex, EXx, Ib } }, 4923 { "(bad)", { XX } }, 4924 }, 4925 4926 /* PREFIX_VEX_3A0E */ 4927 { 4928 { "(bad)", { XX } }, 4929 { "(bad)", { XX } }, 4930 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) }, 4931 { "(bad)", { XX } }, 4932 }, 4933 4934 /* PREFIX_VEX_3A0F */ 4935 { 4936 { "(bad)", { XX } }, 4937 { "(bad)", { XX } }, 4938 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) }, 4939 { "(bad)", { XX } }, 4940 }, 4941 4942 /* PREFIX_VEX_3A14 */ 4943 { 4944 { "(bad)", { XX } }, 4945 { "(bad)", { XX } }, 4946 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) }, 4947 { "(bad)", { XX } }, 4948 }, 4949 4950 /* PREFIX_VEX_3A15 */ 4951 { 4952 { "(bad)", { XX } }, 4953 { "(bad)", { XX } }, 4954 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) }, 4955 { "(bad)", { XX } }, 4956 }, 4957 4958 /* PREFIX_VEX_3A16 */ 4959 { 4960 { "(bad)", { XX } }, 4961 { "(bad)", { XX } }, 4962 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) }, 4963 { "(bad)", { XX } }, 4964 }, 4965 4966 /* PREFIX_VEX_3A17 */ 4967 { 4968 { "(bad)", { XX } }, 4969 { "(bad)", { XX } }, 4970 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) }, 4971 { "(bad)", { XX } }, 4972 }, 4973 4974 /* PREFIX_VEX_3A18 */ 4975 { 4976 { "(bad)", { XX } }, 4977 { "(bad)", { XX } }, 4978 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) }, 4979 { "(bad)", { XX } }, 4980 }, 4981 4982 /* PREFIX_VEX_3A19 */ 4983 { 4984 { "(bad)", { XX } }, 4985 { "(bad)", { XX } }, 4986 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) }, 4987 { "(bad)", { XX } }, 4988 }, 4989 4990 /* PREFIX_VEX_3A20 */ 4991 { 4992 { "(bad)", { XX } }, 4993 { "(bad)", { XX } }, 4994 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) }, 4995 { "(bad)", { XX } }, 4996 }, 4997 4998 /* PREFIX_VEX_3A21 */ 4999 { 5000 { "(bad)", { XX } }, 5001 { "(bad)", { XX } }, 5002 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) }, 5003 { "(bad)", { XX } }, 5004 }, 5005 5006 /* PREFIX_VEX_3A22 */ 5007 { 5008 { "(bad)", { XX } }, 5009 { "(bad)", { XX } }, 5010 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) }, 5011 { "(bad)", { XX } }, 5012 }, 5013 5014 /* PREFIX_VEX_3A40 */ 5015 { 5016 { "(bad)", { XX } }, 5017 { "(bad)", { XX } }, 5018 { "vdpps", { XM, Vex, EXx, Ib } }, 5019 { "(bad)", { XX } }, 5020 }, 5021 5022 /* PREFIX_VEX_3A41 */ 5023 { 5024 { "(bad)", { XX } }, 5025 { "(bad)", { XX } }, 5026 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) }, 5027 { "(bad)", { XX } }, 5028 }, 5029 5030 /* PREFIX_VEX_3A42 */ 5031 { 5032 { "(bad)", { XX } }, 5033 { "(bad)", { XX } }, 5034 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) }, 5035 { "(bad)", { XX } }, 5036 }, 5037 5038 /* PREFIX_VEX_3A44 */ 5039 { 5040 { "(bad)", { XX } }, 5041 { "(bad)", { XX } }, 5042 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) }, 5043 { "(bad)", { XX } }, 5044 }, 5045 5046 /* PREFIX_VEX_3A4A */ 5047 { 5048 { "(bad)", { XX } }, 5049 { "(bad)", { XX } }, 5050 { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, 5051 { "(bad)", { XX } }, 5052 }, 5053 5054 /* PREFIX_VEX_3A4B */ 5055 { 5056 { "(bad)", { XX } }, 5057 { "(bad)", { XX } }, 5058 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, 5059 { "(bad)", { XX } }, 5060 }, 5061 5062 /* PREFIX_VEX_3A4C */ 5063 { 5064 { "(bad)", { XX } }, 5065 { "(bad)", { XX } }, 5066 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) }, 5067 { "(bad)", { XX } }, 5068 }, 5069 5070 /* PREFIX_VEX_3A5C */ 5071 { 5072 { "(bad)", { XX } }, 5073 { "(bad)", { XX } }, 5074 { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5075 { "(bad)", { XX } }, 5076 }, 5077 5078 /* PREFIX_VEX_3A5D */ 5079 { 5080 { "(bad)", { XX } }, 5081 { "(bad)", { XX } }, 5082 { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5083 { "(bad)", { XX } }, 5084 }, 5085 5086 /* PREFIX_VEX_3A5E */ 5087 { 5088 { "(bad)", { XX } }, 5089 { "(bad)", { XX } }, 5090 { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5091 { "(bad)", { XX } }, 5092 }, 5093 5094 /* PREFIX_VEX_3A5F */ 5095 { 5096 { "(bad)", { XX } }, 5097 { "(bad)", { XX } }, 5098 { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5099 { "(bad)", { XX } }, 5100 }, 5101 5102 /* PREFIX_VEX_3A60 */ 5103 { 5104 { "(bad)", { XX } }, 5105 { "(bad)", { XX } }, 5106 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) }, 5107 { "(bad)", { XX } }, 5108 }, 5109 5110 /* PREFIX_VEX_3A61 */ 5111 { 5112 { "(bad)", { XX } }, 5113 { "(bad)", { XX } }, 5114 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) }, 5115 { "(bad)", { XX } }, 5116 }, 5117 5118 /* PREFIX_VEX_3A62 */ 5119 { 5120 { "(bad)", { XX } }, 5121 { "(bad)", { XX } }, 5122 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) }, 5123 { "(bad)", { XX } }, 5124 }, 5125 5126 /* PREFIX_VEX_3A63 */ 5127 { 5128 { "(bad)", { XX } }, 5129 { "(bad)", { XX } }, 5130 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) }, 5131 { "(bad)", { XX } }, 5132 }, 5133 5134 /* PREFIX_VEX_3A68 */ 5135 { 5136 { "(bad)", { XX } }, 5137 { "(bad)", { XX } }, 5138 { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5139 { "(bad)", { XX } }, 5140 }, 5141 5142 /* PREFIX_VEX_3A69 */ 5143 { 5144 { "(bad)", { XX } }, 5145 { "(bad)", { XX } }, 5146 { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5147 { "(bad)", { XX } }, 5148 }, 5149 5150 /* PREFIX_VEX_3A6A */ 5151 { 5152 { "(bad)", { XX } }, 5153 { "(bad)", { XX } }, 5154 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) }, 5155 { "(bad)", { XX } }, 5156 }, 5157 5158 /* PREFIX_VEX_3A6B */ 5159 { 5160 { "(bad)", { XX } }, 5161 { "(bad)", { XX } }, 5162 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) }, 5163 { "(bad)", { XX } }, 5164 }, 5165 5166 /* PREFIX_VEX_3A6C */ 5167 { 5168 { "(bad)", { XX } }, 5169 { "(bad)", { XX } }, 5170 { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5171 { "(bad)", { XX } }, 5172 }, 5173 5174 /* PREFIX_VEX_3A6D */ 5175 { 5176 { "(bad)", { XX } }, 5177 { "(bad)", { XX } }, 5178 { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5179 { "(bad)", { XX } }, 5180 }, 5181 5182 /* PREFIX_VEX_3A6E */ 5183 { 5184 { "(bad)", { XX } }, 5185 { "(bad)", { XX } }, 5186 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) }, 5187 { "(bad)", { XX } }, 5188 }, 5189 5190 /* PREFIX_VEX_3A6F */ 5191 { 5192 { "(bad)", { XX } }, 5193 { "(bad)", { XX } }, 5194 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) }, 5195 { "(bad)", { XX } }, 5196 }, 5197 5198 /* PREFIX_VEX_3A78 */ 5199 { 5200 { "(bad)", { XX } }, 5201 { "(bad)", { XX } }, 5202 { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5203 { "(bad)", { XX } }, 5204 }, 5205 5206 /* PREFIX_VEX_3A79 */ 5207 { 5208 { "(bad)", { XX } }, 5209 { "(bad)", { XX } }, 5210 { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5211 { "(bad)", { XX } }, 5212 }, 5213 5214 /* PREFIX_VEX_3A7A */ 5215 { 5216 { "(bad)", { XX } }, 5217 { "(bad)", { XX } }, 5218 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) }, 5219 { "(bad)", { XX } }, 5220 }, 5221 5222 /* PREFIX_VEX_3A7B */ 5223 { 5224 { "(bad)", { XX } }, 5225 { "(bad)", { XX } }, 5226 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) }, 5227 { "(bad)", { XX } }, 5228 }, 5229 5230 /* PREFIX_VEX_3A7C */ 5231 { 5232 { "(bad)", { XX } }, 5233 { "(bad)", { XX } }, 5234 { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5235 { "(bad)", { XX } }, 5236 }, 5237 5238 /* PREFIX_VEX_3A7D */ 5239 { 5240 { "(bad)", { XX } }, 5241 { "(bad)", { XX } }, 5242 { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } }, 5243 { "(bad)", { XX } }, 5244 }, 5245 5246 /* PREFIX_VEX_3A7E */ 5247 { 5248 { "(bad)", { XX } }, 5249 { "(bad)", { XX } }, 5250 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) }, 5251 { "(bad)", { XX } }, 5252 }, 5253 5254 /* PREFIX_VEX_3A7F */ 5255 { 5256 { "(bad)", { XX } }, 5257 { "(bad)", { XX } }, 5258 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) }, 5259 { "(bad)", { XX } }, 5260 }, 5261 5262 /* PREFIX_VEX_3ADF */ 5263 { 5264 { "(bad)", { XX } }, 5265 { "(bad)", { XX } }, 5266 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) }, 5267 { "(bad)", { XX } }, 5268 }, 5269 }; 5270 5271 static const struct dis386 x86_64_table[][2] = { 5272 /* X86_64_06 */ 5273 { 5274 { "push{T|}", { es } }, 5275 { "(bad)", { XX } }, 5276 }, 5277 5278 /* X86_64_07 */ 5279 { 5280 { "pop{T|}", { es } }, 5281 { "(bad)", { XX } }, 5282 }, 5283 5284 /* X86_64_0D */ 5285 { 5286 { "push{T|}", { cs } }, 5287 { "(bad)", { XX } }, 5288 }, 5289 5290 /* X86_64_16 */ 5291 { 5292 { "push{T|}", { ss } }, 5293 { "(bad)", { XX } }, 5294 }, 5295 5296 /* X86_64_17 */ 5297 { 5298 { "pop{T|}", { ss } }, 5299 { "(bad)", { XX } }, 5300 }, 5301 5302 /* X86_64_1E */ 5303 { 5304 { "push{T|}", { ds } }, 5305 { "(bad)", { XX } }, 5306 }, 5307 5308 /* X86_64_1F */ 5309 { 5310 { "pop{T|}", { ds } }, 5311 { "(bad)", { XX } }, 5312 }, 5313 5314 /* X86_64_27 */ 5315 { 5316 { "daa", { XX } }, 5317 { "(bad)", { XX } }, 5318 }, 5319 5320 /* X86_64_2F */ 5321 { 5322 { "das", { XX } }, 5323 { "(bad)", { XX } }, 5324 }, 5325 5326 /* X86_64_37 */ 5327 { 5328 { "aaa", { XX } }, 5329 { "(bad)", { XX } }, 5330 }, 5331 5332 /* X86_64_3F */ 5333 { 5334 { "aas", { XX } }, 5335 { "(bad)", { XX } }, 5336 }, 5337 5338 /* X86_64_60 */ 5339 { 5340 { "pusha{P|}", { XX } }, 5341 { "(bad)", { XX } }, 5342 }, 5343 5344 /* X86_64_61 */ 5345 { 5346 { "popa{P|}", { XX } }, 5347 { "(bad)", { XX } }, 5348 }, 5349 5350 /* X86_64_62 */ 5351 { 5352 { MOD_TABLE (MOD_62_32BIT) }, 5353 { "(bad)", { XX } }, 5354 }, 5355 5356 /* X86_64_63 */ 5357 { 5358 { "arpl", { Ew, Gw } }, 5359 { "movs{lq|xd}", { Gv, Ed } }, 5360 }, 5361 5362 /* X86_64_6D */ 5363 { 5364 { "ins{R|}", { Yzr, indirDX } }, 5365 { "ins{G|}", { Yzr, indirDX } }, 5366 }, 5367 5368 /* X86_64_6F */ 5369 { 5370 { "outs{R|}", { indirDXr, Xz } }, 5371 { "outs{G|}", { indirDXr, Xz } }, 5372 }, 5373 5374 /* X86_64_9A */ 5375 { 5376 { "Jcall{T|}", { Ap } }, 5377 { "(bad)", { XX } }, 5378 }, 5379 5380 /* X86_64_C4 */ 5381 { 5382 { MOD_TABLE (MOD_C4_32BIT) }, 5383 { VEX_C4_TABLE (VEX_0F) }, 5384 }, 5385 5386 /* X86_64_C5 */ 5387 { 5388 { MOD_TABLE (MOD_C5_32BIT) }, 5389 { VEX_C5_TABLE (VEX_0F) }, 5390 }, 5391 5392 /* X86_64_CE */ 5393 { 5394 { "into", { XX } }, 5395 { "(bad)", { XX } }, 5396 }, 5397 5398 /* X86_64_D4 */ 5399 { 5400 { "aam", { sIb } }, 5401 { "(bad)", { XX } }, 5402 }, 5403 5404 /* X86_64_D5 */ 5405 { 5406 { "aad", { sIb } }, 5407 { "(bad)", { XX } }, 5408 }, 5409 5410 /* X86_64_EA */ 5411 { 5412 { "Jjmp{T|}", { Ap } }, 5413 { "(bad)", { XX } }, 5414 }, 5415 5416 /* X86_64_0F01_REG_0 */ 5417 { 5418 { "sgdt{Q|IQ}", { M } }, 5419 { "sgdt", { M } }, 5420 }, 5421 5422 /* X86_64_0F01_REG_1 */ 5423 { 5424 { "sidt{Q|IQ}", { M } }, 5425 { "sidt", { M } }, 5426 }, 5427 5428 /* X86_64_0F01_REG_2 */ 5429 { 5430 { "lgdt{Q|Q}", { M } }, 5431 { "lgdt", { M } }, 5432 }, 5433 5434 /* X86_64_0F01_REG_3 */ 5435 { 5436 { "lidt{Q|Q}", { M } }, 5437 { "lidt", { M } }, 5438 }, 5439 }; 5440 5441 static const struct dis386 three_byte_table[][256] = { 5442 5443 /* THREE_BYTE_0F38 */ 5444 { 5445 /* 00 */ 5446 { "pshufb", { MX, EM } }, 5447 { "phaddw", { MX, EM } }, 5448 { "phaddd", { MX, EM } }, 5449 { "phaddsw", { MX, EM } }, 5450 { "pmaddubsw", { MX, EM } }, 5451 { "phsubw", { MX, EM } }, 5452 { "phsubd", { MX, EM } }, 5453 { "phsubsw", { MX, EM } }, 5454 /* 08 */ 5455 { "psignb", { MX, EM } }, 5456 { "psignw", { MX, EM } }, 5457 { "psignd", { MX, EM } }, 5458 { "pmulhrsw", { MX, EM } }, 5459 { "(bad)", { XX } }, 5460 { "(bad)", { XX } }, 5461 { "(bad)", { XX } }, 5462 { "(bad)", { XX } }, 5463 /* 10 */ 5464 { PREFIX_TABLE (PREFIX_0F3810) }, 5465 { "(bad)", { XX } }, 5466 { "(bad)", { XX } }, 5467 { "(bad)", { XX } }, 5468 { PREFIX_TABLE (PREFIX_0F3814) }, 5469 { PREFIX_TABLE (PREFIX_0F3815) }, 5470 { "(bad)", { XX } }, 5471 { PREFIX_TABLE (PREFIX_0F3817) }, 5472 /* 18 */ 5473 { "(bad)", { XX } }, 5474 { "(bad)", { XX } }, 5475 { "(bad)", { XX } }, 5476 { "(bad)", { XX } }, 5477 { "pabsb", { MX, EM } }, 5478 { "pabsw", { MX, EM } }, 5479 { "pabsd", { MX, EM } }, 5480 { "(bad)", { XX } }, 5481 /* 20 */ 5482 { PREFIX_TABLE (PREFIX_0F3820) }, 5483 { PREFIX_TABLE (PREFIX_0F3821) }, 5484 { PREFIX_TABLE (PREFIX_0F3822) }, 5485 { PREFIX_TABLE (PREFIX_0F3823) }, 5486 { PREFIX_TABLE (PREFIX_0F3824) }, 5487 { PREFIX_TABLE (PREFIX_0F3825) }, 5488 { "(bad)", { XX } }, 5489 { "(bad)", { XX } }, 5490 /* 28 */ 5491 { PREFIX_TABLE (PREFIX_0F3828) }, 5492 { PREFIX_TABLE (PREFIX_0F3829) }, 5493 { PREFIX_TABLE (PREFIX_0F382A) }, 5494 { PREFIX_TABLE (PREFIX_0F382B) }, 5495 { "(bad)", { XX } }, 5496 { "(bad)", { XX } }, 5497 { "(bad)", { XX } }, 5498 { "(bad)", { XX } }, 5499 /* 30 */ 5500 { PREFIX_TABLE (PREFIX_0F3830) }, 5501 { PREFIX_TABLE (PREFIX_0F3831) }, 5502 { PREFIX_TABLE (PREFIX_0F3832) }, 5503 { PREFIX_TABLE (PREFIX_0F3833) }, 5504 { PREFIX_TABLE (PREFIX_0F3834) }, 5505 { PREFIX_TABLE (PREFIX_0F3835) }, 5506 { "(bad)", { XX } }, 5507 { PREFIX_TABLE (PREFIX_0F3837) }, 5508 /* 38 */ 5509 { PREFIX_TABLE (PREFIX_0F3838) }, 5510 { PREFIX_TABLE (PREFIX_0F3839) }, 5511 { PREFIX_TABLE (PREFIX_0F383A) }, 5512 { PREFIX_TABLE (PREFIX_0F383B) }, 5513 { PREFIX_TABLE (PREFIX_0F383C) }, 5514 { PREFIX_TABLE (PREFIX_0F383D) }, 5515 { PREFIX_TABLE (PREFIX_0F383E) }, 5516 { PREFIX_TABLE (PREFIX_0F383F) }, 5517 /* 40 */ 5518 { PREFIX_TABLE (PREFIX_0F3840) }, 5519 { PREFIX_TABLE (PREFIX_0F3841) }, 5520 { "(bad)", { XX } }, 5521 { "(bad)", { XX } }, 5522 { "(bad)", { XX } }, 5523 { "(bad)", { XX } }, 5524 { "(bad)", { XX } }, 5525 { "(bad)", { XX } }, 5526 /* 48 */ 5527 { "(bad)", { XX } }, 5528 { "(bad)", { XX } }, 5529 { "(bad)", { XX } }, 5530 { "(bad)", { XX } }, 5531 { "(bad)", { XX } }, 5532 { "(bad)", { XX } }, 5533 { "(bad)", { XX } }, 5534 { "(bad)", { XX } }, 5535 /* 50 */ 5536 { "(bad)", { XX } }, 5537 { "(bad)", { XX } }, 5538 { "(bad)", { XX } }, 5539 { "(bad)", { XX } }, 5540 { "(bad)", { XX } }, 5541 { "(bad)", { XX } }, 5542 { "(bad)", { XX } }, 5543 { "(bad)", { XX } }, 5544 /* 58 */ 5545 { "(bad)", { XX } }, 5546 { "(bad)", { XX } }, 5547 { "(bad)", { XX } }, 5548 { "(bad)", { XX } }, 5549 { "(bad)", { XX } }, 5550 { "(bad)", { XX } }, 5551 { "(bad)", { XX } }, 5552 { "(bad)", { XX } }, 5553 /* 60 */ 5554 { "(bad)", { XX } }, 5555 { "(bad)", { XX } }, 5556 { "(bad)", { XX } }, 5557 { "(bad)", { XX } }, 5558 { "(bad)", { XX } }, 5559 { "(bad)", { XX } }, 5560 { "(bad)", { XX } }, 5561 { "(bad)", { XX } }, 5562 /* 68 */ 5563 { "(bad)", { XX } }, 5564 { "(bad)", { XX } }, 5565 { "(bad)", { XX } }, 5566 { "(bad)", { XX } }, 5567 { "(bad)", { XX } }, 5568 { "(bad)", { XX } }, 5569 { "(bad)", { XX } }, 5570 { "(bad)", { XX } }, 5571 /* 70 */ 5572 { "(bad)", { XX } }, 5573 { "(bad)", { XX } }, 5574 { "(bad)", { XX } }, 5575 { "(bad)", { XX } }, 5576 { "(bad)", { XX } }, 5577 { "(bad)", { XX } }, 5578 { "(bad)", { XX } }, 5579 { "(bad)", { XX } }, 5580 /* 78 */ 5581 { "(bad)", { XX } }, 5582 { "(bad)", { XX } }, 5583 { "(bad)", { XX } }, 5584 { "(bad)", { XX } }, 5585 { "(bad)", { XX } }, 5586 { "(bad)", { XX } }, 5587 { "(bad)", { XX } }, 5588 { "(bad)", { XX } }, 5589 /* 80 */ 5590 { PREFIX_TABLE (PREFIX_0F3880) }, 5591 { PREFIX_TABLE (PREFIX_0F3881) }, 5592 { "(bad)", { XX } }, 5593 { "(bad)", { XX } }, 5594 { "(bad)", { XX } }, 5595 { "(bad)", { XX } }, 5596 { "(bad)", { XX } }, 5597 { "(bad)", { XX } }, 5598 /* 88 */ 5599 { "(bad)", { XX } }, 5600 { "(bad)", { XX } }, 5601 { "(bad)", { XX } }, 5602 { "(bad)", { XX } }, 5603 { "(bad)", { XX } }, 5604 { "(bad)", { XX } }, 5605 { "(bad)", { XX } }, 5606 { "(bad)", { XX } }, 5607 /* 90 */ 5608 { "(bad)", { XX } }, 5609 { "(bad)", { XX } }, 5610 { "(bad)", { XX } }, 5611 { "(bad)", { XX } }, 5612 { "(bad)", { XX } }, 5613 { "(bad)", { XX } }, 5614 { "(bad)", { XX } }, 5615 { "(bad)", { XX } }, 5616 /* 98 */ 5617 { "(bad)", { XX } }, 5618 { "(bad)", { XX } }, 5619 { "(bad)", { XX } }, 5620 { "(bad)", { XX } }, 5621 { "(bad)", { XX } }, 5622 { "(bad)", { XX } }, 5623 { "(bad)", { XX } }, 5624 { "(bad)", { XX } }, 5625 /* a0 */ 5626 { "(bad)", { XX } }, 5627 { "(bad)", { XX } }, 5628 { "(bad)", { XX } }, 5629 { "(bad)", { XX } }, 5630 { "(bad)", { XX } }, 5631 { "(bad)", { XX } }, 5632 { "(bad)", { XX } }, 5633 { "(bad)", { XX } }, 5634 /* a8 */ 5635 { "(bad)", { XX } }, 5636 { "(bad)", { XX } }, 5637 { "(bad)", { XX } }, 5638 { "(bad)", { XX } }, 5639 { "(bad)", { XX } }, 5640 { "(bad)", { XX } }, 5641 { "(bad)", { XX } }, 5642 { "(bad)", { XX } }, 5643 /* b0 */ 5644 { "(bad)", { XX } }, 5645 { "(bad)", { XX } }, 5646 { "(bad)", { XX } }, 5647 { "(bad)", { XX } }, 5648 { "(bad)", { XX } }, 5649 { "(bad)", { XX } }, 5650 { "(bad)", { XX } }, 5651 { "(bad)", { XX } }, 5652 /* b8 */ 5653 { "(bad)", { XX } }, 5654 { "(bad)", { XX } }, 5655 { "(bad)", { XX } }, 5656 { "(bad)", { XX } }, 5657 { "(bad)", { XX } }, 5658 { "(bad)", { XX } }, 5659 { "(bad)", { XX } }, 5660 { "(bad)", { XX } }, 5661 /* c0 */ 5662 { "(bad)", { XX } }, 5663 { "(bad)", { XX } }, 5664 { "(bad)", { XX } }, 5665 { "(bad)", { XX } }, 5666 { "(bad)", { XX } }, 5667 { "(bad)", { XX } }, 5668 { "(bad)", { XX } }, 5669 { "(bad)", { XX } }, 5670 /* c8 */ 5671 { "(bad)", { XX } }, 5672 { "(bad)", { XX } }, 5673 { "(bad)", { XX } }, 5674 { "(bad)", { XX } }, 5675 { "(bad)", { XX } }, 5676 { "(bad)", { XX } }, 5677 { "(bad)", { XX } }, 5678 { "(bad)", { XX } }, 5679 /* d0 */ 5680 { "(bad)", { XX } }, 5681 { "(bad)", { XX } }, 5682 { "(bad)", { XX } }, 5683 { "(bad)", { XX } }, 5684 { "(bad)", { XX } }, 5685 { "(bad)", { XX } }, 5686 { "(bad)", { XX } }, 5687 { "(bad)", { XX } }, 5688 /* d8 */ 5689 { "(bad)", { XX } }, 5690 { "(bad)", { XX } }, 5691 { "(bad)", { XX } }, 5692 { PREFIX_TABLE (PREFIX_0F38DB) }, 5693 { PREFIX_TABLE (PREFIX_0F38DC) }, 5694 { PREFIX_TABLE (PREFIX_0F38DD) }, 5695 { PREFIX_TABLE (PREFIX_0F38DE) }, 5696 { PREFIX_TABLE (PREFIX_0F38DF) }, 5697 /* e0 */ 5698 { "(bad)", { XX } }, 5699 { "(bad)", { XX } }, 5700 { "(bad)", { XX } }, 5701 { "(bad)", { XX } }, 5702 { "(bad)", { XX } }, 5703 { "(bad)", { XX } }, 5704 { "(bad)", { XX } }, 5705 { "(bad)", { XX } }, 5706 /* e8 */ 5707 { "(bad)", { XX } }, 5708 { "(bad)", { XX } }, 5709 { "(bad)", { XX } }, 5710 { "(bad)", { XX } }, 5711 { "(bad)", { XX } }, 5712 { "(bad)", { XX } }, 5713 { "(bad)", { XX } }, 5714 { "(bad)", { XX } }, 5715 /* f0 */ 5716 { PREFIX_TABLE (PREFIX_0F38F0) }, 5717 { PREFIX_TABLE (PREFIX_0F38F1) }, 5718 { "(bad)", { XX } }, 5719 { "(bad)", { XX } }, 5720 { "(bad)", { XX } }, 5721 { "(bad)", { XX } }, 5722 { "(bad)", { XX } }, 5723 { "(bad)", { XX } }, 5724 /* f8 */ 5725 { "(bad)", { XX } }, 5726 { "(bad)", { XX } }, 5727 { "(bad)", { XX } }, 5728 { "(bad)", { XX } }, 5729 { "(bad)", { XX } }, 5730 { "(bad)", { XX } }, 5731 { "(bad)", { XX } }, 5732 { "(bad)", { XX } }, 5733 }, 5734 /* THREE_BYTE_0F3A */ 5735 { 5736 /* 00 */ 5737 { "(bad)", { XX } }, 5738 { "(bad)", { XX } }, 5739 { "(bad)", { XX } }, 5740 { "(bad)", { XX } }, 5741 { "(bad)", { XX } }, 5742 { "(bad)", { XX } }, 5743 { "(bad)", { XX } }, 5744 { "(bad)", { XX } }, 5745 /* 08 */ 5746 { PREFIX_TABLE (PREFIX_0F3A08) }, 5747 { PREFIX_TABLE (PREFIX_0F3A09) }, 5748 { PREFIX_TABLE (PREFIX_0F3A0A) }, 5749 { PREFIX_TABLE (PREFIX_0F3A0B) }, 5750 { PREFIX_TABLE (PREFIX_0F3A0C) }, 5751 { PREFIX_TABLE (PREFIX_0F3A0D) }, 5752 { PREFIX_TABLE (PREFIX_0F3A0E) }, 5753 { "palignr", { MX, EM, Ib } }, 5754 /* 10 */ 5755 { "(bad)", { XX } }, 5756 { "(bad)", { XX } }, 5757 { "(bad)", { XX } }, 5758 { "(bad)", { XX } }, 5759 { PREFIX_TABLE (PREFIX_0F3A14) }, 5760 { PREFIX_TABLE (PREFIX_0F3A15) }, 5761 { PREFIX_TABLE (PREFIX_0F3A16) }, 5762 { PREFIX_TABLE (PREFIX_0F3A17) }, 5763 /* 18 */ 5764 { "(bad)", { XX } }, 5765 { "(bad)", { XX } }, 5766 { "(bad)", { XX } }, 5767 { "(bad)", { XX } }, 5768 { "(bad)", { XX } }, 5769 { "(bad)", { XX } }, 5770 { "(bad)", { XX } }, 5771 { "(bad)", { XX } }, 5772 /* 20 */ 5773 { PREFIX_TABLE (PREFIX_0F3A20) }, 5774 { PREFIX_TABLE (PREFIX_0F3A21) }, 5775 { PREFIX_TABLE (PREFIX_0F3A22) }, 5776 { "(bad)", { XX } }, 5777 { "(bad)", { XX } }, 5778 { "(bad)", { XX } }, 5779 { "(bad)", { XX } }, 5780 { "(bad)", { XX } }, 5781 /* 28 */ 5782 { "(bad)", { XX } }, 5783 { "(bad)", { XX } }, 5784 { "(bad)", { XX } }, 5785 { "(bad)", { XX } }, 5786 { "(bad)", { XX } }, 5787 { "(bad)", { XX } }, 5788 { "(bad)", { XX } }, 5789 { "(bad)", { XX } }, 5790 /* 30 */ 5791 { "(bad)", { XX } }, 5792 { "(bad)", { XX } }, 5793 { "(bad)", { XX } }, 5794 { "(bad)", { XX } }, 5795 { "(bad)", { XX } }, 5796 { "(bad)", { XX } }, 5797 { "(bad)", { XX } }, 5798 { "(bad)", { XX } }, 5799 /* 38 */ 5800 { "(bad)", { XX } }, 5801 { "(bad)", { XX } }, 5802 { "(bad)", { XX } }, 5803 { "(bad)", { XX } }, 5804 { "(bad)", { XX } }, 5805 { "(bad)", { XX } }, 5806 { "(bad)", { XX } }, 5807 { "(bad)", { XX } }, 5808 /* 40 */ 5809 { PREFIX_TABLE (PREFIX_0F3A40) }, 5810 { PREFIX_TABLE (PREFIX_0F3A41) }, 5811 { PREFIX_TABLE (PREFIX_0F3A42) }, 5812 { "(bad)", { XX } }, 5813 { PREFIX_TABLE (PREFIX_0F3A44) }, 5814 { "(bad)", { XX } }, 5815 { "(bad)", { XX } }, 5816 { "(bad)", { XX } }, 5817 /* 48 */ 5818 { "(bad)", { XX } }, 5819 { "(bad)", { XX } }, 5820 { "(bad)", { XX } }, 5821 { "(bad)", { XX } }, 5822 { "(bad)", { XX } }, 5823 { "(bad)", { XX } }, 5824 { "(bad)", { XX } }, 5825 { "(bad)", { XX } }, 5826 /* 50 */ 5827 { "(bad)", { XX } }, 5828 { "(bad)", { XX } }, 5829 { "(bad)", { XX } }, 5830 { "(bad)", { XX } }, 5831 { "(bad)", { XX } }, 5832 { "(bad)", { XX } }, 5833 { "(bad)", { XX } }, 5834 { "(bad)", { XX } }, 5835 /* 58 */ 5836 { "(bad)", { XX } }, 5837 { "(bad)", { XX } }, 5838 { "(bad)", { XX } }, 5839 { "(bad)", { XX } }, 5840 { "(bad)", { XX } }, 5841 { "(bad)", { XX } }, 5842 { "(bad)", { XX } }, 5843 { "(bad)", { XX } }, 5844 /* 60 */ 5845 { PREFIX_TABLE (PREFIX_0F3A60) }, 5846 { PREFIX_TABLE (PREFIX_0F3A61) }, 5847 { PREFIX_TABLE (PREFIX_0F3A62) }, 5848 { PREFIX_TABLE (PREFIX_0F3A63) }, 5849 { "(bad)", { XX } }, 5850 { "(bad)", { XX } }, 5851 { "(bad)", { XX } }, 5852 { "(bad)", { XX } }, 5853 /* 68 */ 5854 { "(bad)", { XX } }, 5855 { "(bad)", { XX } }, 5856 { "(bad)", { XX } }, 5857 { "(bad)", { XX } }, 5858 { "(bad)", { XX } }, 5859 { "(bad)", { XX } }, 5860 { "(bad)", { XX } }, 5861 { "(bad)", { XX } }, 5862 /* 70 */ 5863 { "(bad)", { XX } }, 5864 { "(bad)", { XX } }, 5865 { "(bad)", { XX } }, 5866 { "(bad)", { XX } }, 5867 { "(bad)", { XX } }, 5868 { "(bad)", { XX } }, 5869 { "(bad)", { XX } }, 5870 { "(bad)", { XX } }, 5871 /* 78 */ 5872 { "(bad)", { XX } }, 5873 { "(bad)", { XX } }, 5874 { "(bad)", { XX } }, 5875 { "(bad)", { XX } }, 5876 { "(bad)", { XX } }, 5877 { "(bad)", { XX } }, 5878 { "(bad)", { XX } }, 5879 { "(bad)", { XX } }, 5880 /* 80 */ 5881 { "(bad)", { XX } }, 5882 { "(bad)", { XX } }, 5883 { "(bad)", { XX } }, 5884 { "(bad)", { XX } }, 5885 { "(bad)", { XX } }, 5886 { "(bad)", { XX } }, 5887 { "(bad)", { XX } }, 5888 { "(bad)", { XX } }, 5889 /* 88 */ 5890 { "(bad)", { XX } }, 5891 { "(bad)", { XX } }, 5892 { "(bad)", { XX } }, 5893 { "(bad)", { XX } }, 5894 { "(bad)", { XX } }, 5895 { "(bad)", { XX } }, 5896 { "(bad)", { XX } }, 5897 { "(bad)", { XX } }, 5898 /* 90 */ 5899 { "(bad)", { XX } }, 5900 { "(bad)", { XX } }, 5901 { "(bad)", { XX } }, 5902 { "(bad)", { XX } }, 5903 { "(bad)", { XX } }, 5904 { "(bad)", { XX } }, 5905 { "(bad)", { XX } }, 5906 { "(bad)", { XX } }, 5907 /* 98 */ 5908 { "(bad)", { XX } }, 5909 { "(bad)", { XX } }, 5910 { "(bad)", { XX } }, 5911 { "(bad)", { XX } }, 5912 { "(bad)", { XX } }, 5913 { "(bad)", { XX } }, 5914 { "(bad)", { XX } }, 5915 { "(bad)", { XX } }, 5916 /* a0 */ 5917 { "(bad)", { XX } }, 5918 { "(bad)", { XX } }, 5919 { "(bad)", { XX } }, 5920 { "(bad)", { XX } }, 5921 { "(bad)", { XX } }, 5922 { "(bad)", { XX } }, 5923 { "(bad)", { XX } }, 5924 { "(bad)", { XX } }, 5925 /* a8 */ 5926 { "(bad)", { XX } }, 5927 { "(bad)", { XX } }, 5928 { "(bad)", { XX } }, 5929 { "(bad)", { XX } }, 5930 { "(bad)", { XX } }, 5931 { "(bad)", { XX } }, 5932 { "(bad)", { XX } }, 5933 { "(bad)", { XX } }, 5934 /* b0 */ 5935 { "(bad)", { XX } }, 5936 { "(bad)", { XX } }, 5937 { "(bad)", { XX } }, 5938 { "(bad)", { XX } }, 5939 { "(bad)", { XX } }, 5940 { "(bad)", { XX } }, 5941 { "(bad)", { XX } }, 5942 { "(bad)", { XX } }, 5943 /* b8 */ 5944 { "(bad)", { XX } }, 5945 { "(bad)", { XX } }, 5946 { "(bad)", { XX } }, 5947 { "(bad)", { XX } }, 5948 { "(bad)", { XX } }, 5949 { "(bad)", { XX } }, 5950 { "(bad)", { XX } }, 5951 { "(bad)", { XX } }, 5952 /* c0 */ 5953 { "(bad)", { XX } }, 5954 { "(bad)", { XX } }, 5955 { "(bad)", { XX } }, 5956 { "(bad)", { XX } }, 5957 { "(bad)", { XX } }, 5958 { "(bad)", { XX } }, 5959 { "(bad)", { XX } }, 5960 { "(bad)", { XX } }, 5961 /* c8 */ 5962 { "(bad)", { XX } }, 5963 { "(bad)", { XX } }, 5964 { "(bad)", { XX } }, 5965 { "(bad)", { XX } }, 5966 { "(bad)", { XX } }, 5967 { "(bad)", { XX } }, 5968 { "(bad)", { XX } }, 5969 { "(bad)", { XX } }, 5970 /* d0 */ 5971 { "(bad)", { XX } }, 5972 { "(bad)", { XX } }, 5973 { "(bad)", { XX } }, 5974 { "(bad)", { XX } }, 5975 { "(bad)", { XX } }, 5976 { "(bad)", { XX } }, 5977 { "(bad)", { XX } }, 5978 { "(bad)", { XX } }, 5979 /* d8 */ 5980 { "(bad)", { XX } }, 5981 { "(bad)", { XX } }, 5982 { "(bad)", { XX } }, 5983 { "(bad)", { XX } }, 5984 { "(bad)", { XX } }, 5985 { "(bad)", { XX } }, 5986 { "(bad)", { XX } }, 5987 { PREFIX_TABLE (PREFIX_0F3ADF) }, 5988 /* e0 */ 5989 { "(bad)", { XX } }, 5990 { "(bad)", { XX } }, 5991 { "(bad)", { XX } }, 5992 { "(bad)", { XX } }, 5993 { "(bad)", { XX } }, 5994 { "(bad)", { XX } }, 5995 { "(bad)", { XX } }, 5996 { "(bad)", { XX } }, 5997 /* e8 */ 5998 { "(bad)", { XX } }, 5999 { "(bad)", { XX } }, 6000 { "(bad)", { XX } }, 6001 { "(bad)", { XX } }, 6002 { "(bad)", { XX } }, 6003 { "(bad)", { XX } }, 6004 { "(bad)", { XX } }, 6005 { "(bad)", { XX } }, 6006 /* f0 */ 6007 { "(bad)", { XX } }, 6008 { "(bad)", { XX } }, 6009 { "(bad)", { XX } }, 6010 { "(bad)", { XX } }, 6011 { "(bad)", { XX } }, 6012 { "(bad)", { XX } }, 6013 { "(bad)", { XX } }, 6014 { "(bad)", { XX } }, 6015 /* f8 */ 6016 { "(bad)", { XX } }, 6017 { "(bad)", { XX } }, 6018 { "(bad)", { XX } }, 6019 { "(bad)", { XX } }, 6020 { "(bad)", { XX } }, 6021 { "(bad)", { XX } }, 6022 { "(bad)", { XX } }, 6023 { "(bad)", { XX } }, 6024 }, 6025 6026 /* THREE_BYTE_0F7A */ 6027 { 6028 /* 00 */ 6029 { "(bad)", { XX } }, 6030 { "(bad)", { XX } }, 6031 { "(bad)", { XX } }, 6032 { "(bad)", { XX } }, 6033 { "(bad)", { XX } }, 6034 { "(bad)", { XX } }, 6035 { "(bad)", { XX } }, 6036 { "(bad)", { XX } }, 6037 /* 08 */ 6038 { "(bad)", { XX } }, 6039 { "(bad)", { XX } }, 6040 { "(bad)", { XX } }, 6041 { "(bad)", { XX } }, 6042 { "(bad)", { XX } }, 6043 { "(bad)", { XX } }, 6044 { "(bad)", { XX } }, 6045 { "(bad)", { XX } }, 6046 /* 10 */ 6047 { "(bad)", { XX } }, 6048 { "(bad)", { XX } }, 6049 { "(bad)", { XX } }, 6050 { "(bad)", { XX } }, 6051 { "(bad)", { XX } }, 6052 { "(bad)", { XX } }, 6053 { "(bad)", { XX } }, 6054 { "(bad)", { XX } }, 6055 /* 18 */ 6056 { "(bad)", { XX } }, 6057 { "(bad)", { XX } }, 6058 { "(bad)", { XX } }, 6059 { "(bad)", { XX } }, 6060 { "(bad)", { XX } }, 6061 { "(bad)", { XX } }, 6062 { "(bad)", { XX } }, 6063 { "(bad)", { XX } }, 6064 /* 20 */ 6065 { "ptest", { XX } }, 6066 { "(bad)", { XX } }, 6067 { "(bad)", { XX } }, 6068 { "(bad)", { XX } }, 6069 { "(bad)", { XX } }, 6070 { "(bad)", { XX } }, 6071 { "(bad)", { XX } }, 6072 { "(bad)", { XX } }, 6073 /* 28 */ 6074 { "(bad)", { XX } }, 6075 { "(bad)", { XX } }, 6076 { "(bad)", { XX } }, 6077 { "(bad)", { XX } }, 6078 { "(bad)", { XX } }, 6079 { "(bad)", { XX } }, 6080 { "(bad)", { XX } }, 6081 { "(bad)", { XX } }, 6082 /* 30 */ 6083 { "(bad)", { XX } }, 6084 { "(bad)", { XX } }, 6085 { "(bad)", { XX } }, 6086 { "(bad)", { XX } }, 6087 { "(bad)", { XX } }, 6088 { "(bad)", { XX } }, 6089 { "(bad)", { XX } }, 6090 { "(bad)", { XX } }, 6091 /* 38 */ 6092 { "(bad)", { XX } }, 6093 { "(bad)", { XX } }, 6094 { "(bad)", { XX } }, 6095 { "(bad)", { XX } }, 6096 { "(bad)", { XX } }, 6097 { "(bad)", { XX } }, 6098 { "(bad)", { XX } }, 6099 { "(bad)", { XX } }, 6100 /* 40 */ 6101 { "(bad)", { XX } }, 6102 { "phaddbw", { XM, EXq } }, 6103 { "phaddbd", { XM, EXq } }, 6104 { "phaddbq", { XM, EXq } }, 6105 { "(bad)", { XX } }, 6106 { "(bad)", { XX } }, 6107 { "phaddwd", { XM, EXq } }, 6108 { "phaddwq", { XM, EXq } }, 6109 /* 48 */ 6110 { "(bad)", { XX } }, 6111 { "(bad)", { XX } }, 6112 { "(bad)", { XX } }, 6113 { "phadddq", { XM, EXq } }, 6114 { "(bad)", { XX } }, 6115 { "(bad)", { XX } }, 6116 { "(bad)", { XX } }, 6117 { "(bad)", { XX } }, 6118 /* 50 */ 6119 { "(bad)", { XX } }, 6120 { "phaddubw", { XM, EXq } }, 6121 { "phaddubd", { XM, EXq } }, 6122 { "phaddubq", { XM, EXq } }, 6123 { "(bad)", { XX } }, 6124 { "(bad)", { XX } }, 6125 { "phadduwd", { XM, EXq } }, 6126 { "phadduwq", { XM, EXq } }, 6127 /* 58 */ 6128 { "(bad)", { XX } }, 6129 { "(bad)", { XX } }, 6130 { "(bad)", { XX } }, 6131 { "phaddudq", { XM, EXq } }, 6132 { "(bad)", { XX } }, 6133 { "(bad)", { XX } }, 6134 { "(bad)", { XX } }, 6135 { "(bad)", { XX } }, 6136 /* 60 */ 6137 { "(bad)", { XX } }, 6138 { "phsubbw", { XM, EXq } }, 6139 { "phsubbd", { XM, EXq } }, 6140 { "phsubbq", { XM, EXq } }, 6141 { "(bad)", { XX } }, 6142 { "(bad)", { XX } }, 6143 { "(bad)", { XX } }, 6144 { "(bad)", { XX } }, 6145 /* 68 */ 6146 { "(bad)", { XX } }, 6147 { "(bad)", { XX } }, 6148 { "(bad)", { XX } }, 6149 { "(bad)", { XX } }, 6150 { "(bad)", { XX } }, 6151 { "(bad)", { XX } }, 6152 { "(bad)", { XX } }, 6153 { "(bad)", { XX } }, 6154 /* 70 */ 6155 { "(bad)", { XX } }, 6156 { "(bad)", { XX } }, 6157 { "(bad)", { XX } }, 6158 { "(bad)", { XX } }, 6159 { "(bad)", { XX } }, 6160 { "(bad)", { XX } }, 6161 { "(bad)", { XX } }, 6162 { "(bad)", { XX } }, 6163 /* 78 */ 6164 { "(bad)", { XX } }, 6165 { "(bad)", { XX } }, 6166 { "(bad)", { XX } }, 6167 { "(bad)", { XX } }, 6168 { "(bad)", { XX } }, 6169 { "(bad)", { XX } }, 6170 { "(bad)", { XX } }, 6171 { "(bad)", { XX } }, 6172 /* 80 */ 6173 { "(bad)", { XX } }, 6174 { "(bad)", { XX } }, 6175 { "(bad)", { XX } }, 6176 { "(bad)", { XX } }, 6177 { "(bad)", { XX } }, 6178 { "(bad)", { XX } }, 6179 { "(bad)", { XX } }, 6180 { "(bad)", { XX } }, 6181 /* 88 */ 6182 { "(bad)", { XX } }, 6183 { "(bad)", { XX } }, 6184 { "(bad)", { XX } }, 6185 { "(bad)", { XX } }, 6186 { "(bad)", { XX } }, 6187 { "(bad)", { XX } }, 6188 { "(bad)", { XX } }, 6189 { "(bad)", { XX } }, 6190 /* 90 */ 6191 { "(bad)", { XX } }, 6192 { "(bad)", { XX } }, 6193 { "(bad)", { XX } }, 6194 { "(bad)", { XX } }, 6195 { "(bad)", { XX } }, 6196 { "(bad)", { XX } }, 6197 { "(bad)", { XX } }, 6198 { "(bad)", { XX } }, 6199 /* 98 */ 6200 { "(bad)", { XX } }, 6201 { "(bad)", { XX } }, 6202 { "(bad)", { XX } }, 6203 { "(bad)", { XX } }, 6204 { "(bad)", { XX } }, 6205 { "(bad)", { XX } }, 6206 { "(bad)", { XX } }, 6207 { "(bad)", { XX } }, 6208 /* a0 */ 6209 { "(bad)", { XX } }, 6210 { "(bad)", { XX } }, 6211 { "(bad)", { XX } }, 6212 { "(bad)", { XX } }, 6213 { "(bad)", { XX } }, 6214 { "(bad)", { XX } }, 6215 { "(bad)", { XX } }, 6216 { "(bad)", { XX } }, 6217 /* a8 */ 6218 { "(bad)", { XX } }, 6219 { "(bad)", { XX } }, 6220 { "(bad)", { XX } }, 6221 { "(bad)", { XX } }, 6222 { "(bad)", { XX } }, 6223 { "(bad)", { XX } }, 6224 { "(bad)", { XX } }, 6225 { "(bad)", { XX } }, 6226 /* b0 */ 6227 { "(bad)", { XX } }, 6228 { "(bad)", { XX } }, 6229 { "(bad)", { XX } }, 6230 { "(bad)", { XX } }, 6231 { "(bad)", { XX } }, 6232 { "(bad)", { XX } }, 6233 { "(bad)", { XX } }, 6234 { "(bad)", { XX } }, 6235 /* b8 */ 6236 { "(bad)", { XX } }, 6237 { "(bad)", { XX } }, 6238 { "(bad)", { XX } }, 6239 { "(bad)", { XX } }, 6240 { "(bad)", { XX } }, 6241 { "(bad)", { XX } }, 6242 { "(bad)", { XX } }, 6243 { "(bad)", { XX } }, 6244 /* c0 */ 6245 { "(bad)", { XX } }, 6246 { "(bad)", { XX } }, 6247 { "(bad)", { XX } }, 6248 { "(bad)", { XX } }, 6249 { "(bad)", { XX } }, 6250 { "(bad)", { XX } }, 6251 { "(bad)", { XX } }, 6252 { "(bad)", { XX } }, 6253 /* c8 */ 6254 { "(bad)", { XX } }, 6255 { "(bad)", { XX } }, 6256 { "(bad)", { XX } }, 6257 { "(bad)", { XX } }, 6258 { "(bad)", { XX } }, 6259 { "(bad)", { XX } }, 6260 { "(bad)", { XX } }, 6261 { "(bad)", { XX } }, 6262 /* d0 */ 6263 { "(bad)", { XX } }, 6264 { "(bad)", { XX } }, 6265 { "(bad)", { XX } }, 6266 { "(bad)", { XX } }, 6267 { "(bad)", { XX } }, 6268 { "(bad)", { XX } }, 6269 { "(bad)", { XX } }, 6270 { "(bad)", { XX } }, 6271 /* d8 */ 6272 { "(bad)", { XX } }, 6273 { "(bad)", { XX } }, 6274 { "(bad)", { XX } }, 6275 { "(bad)", { XX } }, 6276 { "(bad)", { XX } }, 6277 { "(bad)", { XX } }, 6278 { "(bad)", { XX } }, 6279 { "(bad)", { XX } }, 6280 /* e0 */ 6281 { "(bad)", { XX } }, 6282 { "(bad)", { XX } }, 6283 { "(bad)", { XX } }, 6284 { "(bad)", { XX } }, 6285 { "(bad)", { XX } }, 6286 { "(bad)", { XX } }, 6287 { "(bad)", { XX } }, 6288 { "(bad)", { XX } }, 6289 /* e8 */ 6290 { "(bad)", { XX } }, 6291 { "(bad)", { XX } }, 6292 { "(bad)", { XX } }, 6293 { "(bad)", { XX } }, 6294 { "(bad)", { XX } }, 6295 { "(bad)", { XX } }, 6296 { "(bad)", { XX } }, 6297 { "(bad)", { XX } }, 6298 /* f0 */ 6299 { "(bad)", { XX } }, 6300 { "(bad)", { XX } }, 6301 { "(bad)", { XX } }, 6302 { "(bad)", { XX } }, 6303 { "(bad)", { XX } }, 6304 { "(bad)", { XX } }, 6305 { "(bad)", { XX } }, 6306 { "(bad)", { XX } }, 6307 /* f8 */ 6308 { "(bad)", { XX } }, 6309 { "(bad)", { XX } }, 6310 { "(bad)", { XX } }, 6311 { "(bad)", { XX } }, 6312 { "(bad)", { XX } }, 6313 { "(bad)", { XX } }, 6314 { "(bad)", { XX } }, 6315 { "(bad)", { XX } }, 6316 }, 6317 }; 6318 6319 6320 static const struct dis386 vex_table[][256] = { 6321 /* VEX_0F */ 6322 { 6323 /* 00 */ 6324 { "(bad)", { XX } }, 6325 { "(bad)", { XX } }, 6326 { "(bad)", { XX } }, 6327 { "(bad)", { XX } }, 6328 { "(bad)", { XX } }, 6329 { "(bad)", { XX } }, 6330 { "(bad)", { XX } }, 6331 { "(bad)", { XX } }, 6332 /* 08 */ 6333 { "(bad)", { XX } }, 6334 { "(bad)", { XX } }, 6335 { "(bad)", { XX } }, 6336 { "(bad)", { XX } }, 6337 { "(bad)", { XX } }, 6338 { "(bad)", { XX } }, 6339 { "(bad)", { XX } }, 6340 { "(bad)", { XX } }, 6341 /* 10 */ 6342 { PREFIX_TABLE (PREFIX_VEX_10) }, 6343 { PREFIX_TABLE (PREFIX_VEX_11) }, 6344 { PREFIX_TABLE (PREFIX_VEX_12) }, 6345 { MOD_TABLE (MOD_VEX_13) }, 6346 { "vunpcklpX", { XM, Vex, EXx } }, 6347 { "vunpckhpX", { XM, Vex, EXx } }, 6348 { PREFIX_TABLE (PREFIX_VEX_16) }, 6349 { MOD_TABLE (MOD_VEX_17) }, 6350 /* 18 */ 6351 { "(bad)", { XX } }, 6352 { "(bad)", { XX } }, 6353 { "(bad)", { XX } }, 6354 { "(bad)", { XX } }, 6355 { "(bad)", { XX } }, 6356 { "(bad)", { XX } }, 6357 { "(bad)", { XX } }, 6358 { "(bad)", { XX } }, 6359 /* 20 */ 6360 { "(bad)", { XX } }, 6361 { "(bad)", { XX } }, 6362 { "(bad)", { XX } }, 6363 { "(bad)", { XX } }, 6364 { "(bad)", { XX } }, 6365 { "(bad)", { XX } }, 6366 { "(bad)", { XX } }, 6367 { "(bad)", { XX } }, 6368 /* 28 */ 6369 { "vmovapX", { XM, EXx } }, 6370 { "vmovapX", { EXxS, XM } }, 6371 { PREFIX_TABLE (PREFIX_VEX_2A) }, 6372 { MOD_TABLE (MOD_VEX_2B) }, 6373 { PREFIX_TABLE (PREFIX_VEX_2C) }, 6374 { PREFIX_TABLE (PREFIX_VEX_2D) }, 6375 { PREFIX_TABLE (PREFIX_VEX_2E) }, 6376 { PREFIX_TABLE (PREFIX_VEX_2F) }, 6377 /* 30 */ 6378 { "(bad)", { XX } }, 6379 { "(bad)", { XX } }, 6380 { "(bad)", { XX } }, 6381 { "(bad)", { XX } }, 6382 { "(bad)", { XX } }, 6383 { "(bad)", { XX } }, 6384 { "(bad)", { XX } }, 6385 { "(bad)", { XX } }, 6386 /* 38 */ 6387 { "(bad)", { XX } }, 6388 { "(bad)", { XX } }, 6389 { "(bad)", { XX } }, 6390 { "(bad)", { XX } }, 6391 { "(bad)", { XX } }, 6392 { "(bad)", { XX } }, 6393 { "(bad)", { XX } }, 6394 { "(bad)", { XX } }, 6395 /* 40 */ 6396 { "(bad)", { XX } }, 6397 { "(bad)", { XX } }, 6398 { "(bad)", { XX } }, 6399 { "(bad)", { XX } }, 6400 { "(bad)", { XX } }, 6401 { "(bad)", { XX } }, 6402 { "(bad)", { XX } }, 6403 { "(bad)", { XX } }, 6404 /* 48 */ 6405 { "(bad)", { XX } }, 6406 { "(bad)", { XX } }, 6407 { "(bad)", { XX } }, 6408 { "(bad)", { XX } }, 6409 { "(bad)", { XX } }, 6410 { "(bad)", { XX } }, 6411 { "(bad)", { XX } }, 6412 { "(bad)", { XX } }, 6413 /* 50 */ 6414 { MOD_TABLE (MOD_VEX_51) }, 6415 { PREFIX_TABLE (PREFIX_VEX_51) }, 6416 { PREFIX_TABLE (PREFIX_VEX_52) }, 6417 { PREFIX_TABLE (PREFIX_VEX_53) }, 6418 { "vandpX", { XM, Vex, EXx } }, 6419 { "vandnpX", { XM, Vex, EXx } }, 6420 { "vorpX", { XM, Vex, EXx } }, 6421 { "vxorpX", { XM, Vex, EXx } }, 6422 /* 58 */ 6423 { PREFIX_TABLE (PREFIX_VEX_58) }, 6424 { PREFIX_TABLE (PREFIX_VEX_59) }, 6425 { PREFIX_TABLE (PREFIX_VEX_5A) }, 6426 { PREFIX_TABLE (PREFIX_VEX_5B) }, 6427 { PREFIX_TABLE (PREFIX_VEX_5C) }, 6428 { PREFIX_TABLE (PREFIX_VEX_5D) }, 6429 { PREFIX_TABLE (PREFIX_VEX_5E) }, 6430 { PREFIX_TABLE (PREFIX_VEX_5F) }, 6431 /* 60 */ 6432 { PREFIX_TABLE (PREFIX_VEX_60) }, 6433 { PREFIX_TABLE (PREFIX_VEX_61) }, 6434 { PREFIX_TABLE (PREFIX_VEX_62) }, 6435 { PREFIX_TABLE (PREFIX_VEX_63) }, 6436 { PREFIX_TABLE (PREFIX_VEX_64) }, 6437 { PREFIX_TABLE (PREFIX_VEX_65) }, 6438 { PREFIX_TABLE (PREFIX_VEX_66) }, 6439 { PREFIX_TABLE (PREFIX_VEX_67) }, 6440 /* 68 */ 6441 { PREFIX_TABLE (PREFIX_VEX_68) }, 6442 { PREFIX_TABLE (PREFIX_VEX_69) }, 6443 { PREFIX_TABLE (PREFIX_VEX_6A) }, 6444 { PREFIX_TABLE (PREFIX_VEX_6B) }, 6445 { PREFIX_TABLE (PREFIX_VEX_6C) }, 6446 { PREFIX_TABLE (PREFIX_VEX_6D) }, 6447 { PREFIX_TABLE (PREFIX_VEX_6E) }, 6448 { PREFIX_TABLE (PREFIX_VEX_6F) }, 6449 /* 70 */ 6450 { PREFIX_TABLE (PREFIX_VEX_70) }, 6451 { REG_TABLE (REG_VEX_71) }, 6452 { REG_TABLE (REG_VEX_72) }, 6453 { REG_TABLE (REG_VEX_73) }, 6454 { PREFIX_TABLE (PREFIX_VEX_74) }, 6455 { PREFIX_TABLE (PREFIX_VEX_75) }, 6456 { PREFIX_TABLE (PREFIX_VEX_76) }, 6457 { PREFIX_TABLE (PREFIX_VEX_77) }, 6458 /* 78 */ 6459 { "(bad)", { XX } }, 6460 { "(bad)", { XX } }, 6461 { "(bad)", { XX } }, 6462 { "(bad)", { XX } }, 6463 { PREFIX_TABLE (PREFIX_VEX_7C) }, 6464 { PREFIX_TABLE (PREFIX_VEX_7D) }, 6465 { PREFIX_TABLE (PREFIX_VEX_7E) }, 6466 { PREFIX_TABLE (PREFIX_VEX_7F) }, 6467 /* 80 */ 6468 { "(bad)", { XX } }, 6469 { "(bad)", { XX } }, 6470 { "(bad)", { XX } }, 6471 { "(bad)", { XX } }, 6472 { "(bad)", { XX } }, 6473 { "(bad)", { XX } }, 6474 { "(bad)", { XX } }, 6475 { "(bad)", { XX } }, 6476 /* 88 */ 6477 { "(bad)", { XX } }, 6478 { "(bad)", { XX } }, 6479 { "(bad)", { XX } }, 6480 { "(bad)", { XX } }, 6481 { "(bad)", { XX } }, 6482 { "(bad)", { XX } }, 6483 { "(bad)", { XX } }, 6484 { "(bad)", { XX } }, 6485 /* 90 */ 6486 { "(bad)", { XX } }, 6487 { "(bad)", { XX } }, 6488 { "(bad)", { XX } }, 6489 { "(bad)", { XX } }, 6490 { "(bad)", { XX } }, 6491 { "(bad)", { XX } }, 6492 { "(bad)", { XX } }, 6493 { "(bad)", { XX } }, 6494 /* 98 */ 6495 { "(bad)", { XX } }, 6496 { "(bad)", { XX } }, 6497 { "(bad)", { XX } }, 6498 { "(bad)", { XX } }, 6499 { "(bad)", { XX } }, 6500 { "(bad)", { XX } }, 6501 { "(bad)", { XX } }, 6502 { "(bad)", { XX } }, 6503 /* a0 */ 6504 { "(bad)", { XX } }, 6505 { "(bad)", { XX } }, 6506 { "(bad)", { XX } }, 6507 { "(bad)", { XX } }, 6508 { "(bad)", { XX } }, 6509 { "(bad)", { XX } }, 6510 { "(bad)", { XX } }, 6511 { "(bad)", { XX } }, 6512 /* a8 */ 6513 { "(bad)", { XX } }, 6514 { "(bad)", { XX } }, 6515 { "(bad)", { XX } }, 6516 { "(bad)", { XX } }, 6517 { "(bad)", { XX } }, 6518 { "(bad)", { XX } }, 6519 { REG_TABLE (REG_VEX_AE) }, 6520 { "(bad)", { XX } }, 6521 /* b0 */ 6522 { "(bad)", { XX } }, 6523 { "(bad)", { XX } }, 6524 { "(bad)", { XX } }, 6525 { "(bad)", { XX } }, 6526 { "(bad)", { XX } }, 6527 { "(bad)", { XX } }, 6528 { "(bad)", { XX } }, 6529 { "(bad)", { XX } }, 6530 /* b8 */ 6531 { "(bad)", { XX } }, 6532 { "(bad)", { XX } }, 6533 { "(bad)", { XX } }, 6534 { "(bad)", { XX } }, 6535 { "(bad)", { XX } }, 6536 { "(bad)", { XX } }, 6537 { "(bad)", { XX } }, 6538 { "(bad)", { XX } }, 6539 /* c0 */ 6540 { "(bad)", { XX } }, 6541 { "(bad)", { XX } }, 6542 { PREFIX_TABLE (PREFIX_VEX_C2) }, 6543 { "(bad)", { XX } }, 6544 { PREFIX_TABLE (PREFIX_VEX_C4) }, 6545 { PREFIX_TABLE (PREFIX_VEX_C5) }, 6546 { "vshufpX", { XM, Vex, EXx, Ib } }, 6547 { "(bad)", { XX } }, 6548 /* c8 */ 6549 { "(bad)", { XX } }, 6550 { "(bad)", { XX } }, 6551 { "(bad)", { XX } }, 6552 { "(bad)", { XX } }, 6553 { "(bad)", { XX } }, 6554 { "(bad)", { XX } }, 6555 { "(bad)", { XX } }, 6556 { "(bad)", { XX } }, 6557 /* d0 */ 6558 { PREFIX_TABLE (PREFIX_VEX_D0) }, 6559 { PREFIX_TABLE (PREFIX_VEX_D1) }, 6560 { PREFIX_TABLE (PREFIX_VEX_D2) }, 6561 { PREFIX_TABLE (PREFIX_VEX_D3) }, 6562 { PREFIX_TABLE (PREFIX_VEX_D4) }, 6563 { PREFIX_TABLE (PREFIX_VEX_D5) }, 6564 { PREFIX_TABLE (PREFIX_VEX_D6) }, 6565 { PREFIX_TABLE (PREFIX_VEX_D7) }, 6566 /* d8 */ 6567 { PREFIX_TABLE (PREFIX_VEX_D8) }, 6568 { PREFIX_TABLE (PREFIX_VEX_D9) }, 6569 { PREFIX_TABLE (PREFIX_VEX_DA) }, 6570 { PREFIX_TABLE (PREFIX_VEX_DB) }, 6571 { PREFIX_TABLE (PREFIX_VEX_DC) }, 6572 { PREFIX_TABLE (PREFIX_VEX_DD) }, 6573 { PREFIX_TABLE (PREFIX_VEX_DE) }, 6574 { PREFIX_TABLE (PREFIX_VEX_DF) }, 6575 /* e0 */ 6576 { PREFIX_TABLE (PREFIX_VEX_E0) }, 6577 { PREFIX_TABLE (PREFIX_VEX_E1) }, 6578 { PREFIX_TABLE (PREFIX_VEX_E2) }, 6579 { PREFIX_TABLE (PREFIX_VEX_E3) }, 6580 { PREFIX_TABLE (PREFIX_VEX_E4) }, 6581 { PREFIX_TABLE (PREFIX_VEX_E5) }, 6582 { PREFIX_TABLE (PREFIX_VEX_E6) }, 6583 { PREFIX_TABLE (PREFIX_VEX_E7) }, 6584 /* e8 */ 6585 { PREFIX_TABLE (PREFIX_VEX_E8) }, 6586 { PREFIX_TABLE (PREFIX_VEX_E9) }, 6587 { PREFIX_TABLE (PREFIX_VEX_EA) }, 6588 { PREFIX_TABLE (PREFIX_VEX_EB) }, 6589 { PREFIX_TABLE (PREFIX_VEX_EC) }, 6590 { PREFIX_TABLE (PREFIX_VEX_ED) }, 6591 { PREFIX_TABLE (PREFIX_VEX_EE) }, 6592 { PREFIX_TABLE (PREFIX_VEX_EF) }, 6593 /* f0 */ 6594 { PREFIX_TABLE (PREFIX_VEX_F0) }, 6595 { PREFIX_TABLE (PREFIX_VEX_F1) }, 6596 { PREFIX_TABLE (PREFIX_VEX_F2) }, 6597 { PREFIX_TABLE (PREFIX_VEX_F3) }, 6598 { PREFIX_TABLE (PREFIX_VEX_F4) }, 6599 { PREFIX_TABLE (PREFIX_VEX_F5) }, 6600 { PREFIX_TABLE (PREFIX_VEX_F6) }, 6601 { PREFIX_TABLE (PREFIX_VEX_F7) }, 6602 /* f8 */ 6603 { PREFIX_TABLE (PREFIX_VEX_F8) }, 6604 { PREFIX_TABLE (PREFIX_VEX_F9) }, 6605 { PREFIX_TABLE (PREFIX_VEX_FA) }, 6606 { PREFIX_TABLE (PREFIX_VEX_FB) }, 6607 { PREFIX_TABLE (PREFIX_VEX_FC) }, 6608 { PREFIX_TABLE (PREFIX_VEX_FD) }, 6609 { PREFIX_TABLE (PREFIX_VEX_FE) }, 6610 { "(bad)", { XX } }, 6611 }, 6612 /* VEX_0F38 */ 6613 { 6614 /* 00 */ 6615 { PREFIX_TABLE (PREFIX_VEX_3800) }, 6616 { PREFIX_TABLE (PREFIX_VEX_3801) }, 6617 { PREFIX_TABLE (PREFIX_VEX_3802) }, 6618 { PREFIX_TABLE (PREFIX_VEX_3803) }, 6619 { PREFIX_TABLE (PREFIX_VEX_3804) }, 6620 { PREFIX_TABLE (PREFIX_VEX_3805) }, 6621 { PREFIX_TABLE (PREFIX_VEX_3806) }, 6622 { PREFIX_TABLE (PREFIX_VEX_3807) }, 6623 /* 08 */ 6624 { PREFIX_TABLE (PREFIX_VEX_3808) }, 6625 { PREFIX_TABLE (PREFIX_VEX_3809) }, 6626 { PREFIX_TABLE (PREFIX_VEX_380A) }, 6627 { PREFIX_TABLE (PREFIX_VEX_380B) }, 6628 { PREFIX_TABLE (PREFIX_VEX_380C) }, 6629 { PREFIX_TABLE (PREFIX_VEX_380D) }, 6630 { PREFIX_TABLE (PREFIX_VEX_380E) }, 6631 { PREFIX_TABLE (PREFIX_VEX_380F) }, 6632 /* 10 */ 6633 { "(bad)", { XX } }, 6634 { "(bad)", { XX } }, 6635 { "(bad)", { XX } }, 6636 { "(bad)", { XX } }, 6637 { "(bad)", { XX } }, 6638 { "(bad)", { XX } }, 6639 { "(bad)", { XX } }, 6640 { PREFIX_TABLE (PREFIX_VEX_3817) }, 6641 /* 18 */ 6642 { PREFIX_TABLE (PREFIX_VEX_3818) }, 6643 { PREFIX_TABLE (PREFIX_VEX_3819) }, 6644 { PREFIX_TABLE (PREFIX_VEX_381A) }, 6645 { "(bad)", { XX } }, 6646 { PREFIX_TABLE (PREFIX_VEX_381C) }, 6647 { PREFIX_TABLE (PREFIX_VEX_381D) }, 6648 { PREFIX_TABLE (PREFIX_VEX_381E) }, 6649 { "(bad)", { XX } }, 6650 /* 20 */ 6651 { PREFIX_TABLE (PREFIX_VEX_3820) }, 6652 { PREFIX_TABLE (PREFIX_VEX_3821) }, 6653 { PREFIX_TABLE (PREFIX_VEX_3822) }, 6654 { PREFIX_TABLE (PREFIX_VEX_3823) }, 6655 { PREFIX_TABLE (PREFIX_VEX_3824) }, 6656 { PREFIX_TABLE (PREFIX_VEX_3825) }, 6657 { "(bad)", { XX } }, 6658 { "(bad)", { XX } }, 6659 /* 28 */ 6660 { PREFIX_TABLE (PREFIX_VEX_3828) }, 6661 { PREFIX_TABLE (PREFIX_VEX_3829) }, 6662 { PREFIX_TABLE (PREFIX_VEX_382A) }, 6663 { PREFIX_TABLE (PREFIX_VEX_382B) }, 6664 { PREFIX_TABLE (PREFIX_VEX_382C) }, 6665 { PREFIX_TABLE (PREFIX_VEX_382D) }, 6666 { PREFIX_TABLE (PREFIX_VEX_382E) }, 6667 { PREFIX_TABLE (PREFIX_VEX_382F) }, 6668 /* 30 */ 6669 { PREFIX_TABLE (PREFIX_VEX_3830) }, 6670 { PREFIX_TABLE (PREFIX_VEX_3831) }, 6671 { PREFIX_TABLE (PREFIX_VEX_3832) }, 6672 { PREFIX_TABLE (PREFIX_VEX_3833) }, 6673 { PREFIX_TABLE (PREFIX_VEX_3834) }, 6674 { PREFIX_TABLE (PREFIX_VEX_3835) }, 6675 { "(bad)", { XX } }, 6676 { PREFIX_TABLE (PREFIX_VEX_3837) }, 6677 /* 38 */ 6678 { PREFIX_TABLE (PREFIX_VEX_3838) }, 6679 { PREFIX_TABLE (PREFIX_VEX_3839) }, 6680 { PREFIX_TABLE (PREFIX_VEX_383A) }, 6681 { PREFIX_TABLE (PREFIX_VEX_383B) }, 6682 { PREFIX_TABLE (PREFIX_VEX_383C) }, 6683 { PREFIX_TABLE (PREFIX_VEX_383D) }, 6684 { PREFIX_TABLE (PREFIX_VEX_383E) }, 6685 { PREFIX_TABLE (PREFIX_VEX_383F) }, 6686 /* 40 */ 6687 { PREFIX_TABLE (PREFIX_VEX_3840) }, 6688 { PREFIX_TABLE (PREFIX_VEX_3841) }, 6689 { "(bad)", { XX } }, 6690 { "(bad)", { XX } }, 6691 { "(bad)", { XX } }, 6692 { "(bad)", { XX } }, 6693 { "(bad)", { XX } }, 6694 { "(bad)", { XX } }, 6695 /* 48 */ 6696 { "(bad)", { XX } }, 6697 { "(bad)", { XX } }, 6698 { "(bad)", { XX } }, 6699 { "(bad)", { XX } }, 6700 { "(bad)", { XX } }, 6701 { "(bad)", { XX } }, 6702 { "(bad)", { XX } }, 6703 { "(bad)", { XX } }, 6704 /* 50 */ 6705 { "(bad)", { XX } }, 6706 { "(bad)", { XX } }, 6707 { "(bad)", { XX } }, 6708 { "(bad)", { XX } }, 6709 { "(bad)", { XX } }, 6710 { "(bad)", { XX } }, 6711 { "(bad)", { XX } }, 6712 { "(bad)", { XX } }, 6713 /* 58 */ 6714 { "(bad)", { XX } }, 6715 { "(bad)", { XX } }, 6716 { "(bad)", { XX } }, 6717 { "(bad)", { XX } }, 6718 { "(bad)", { XX } }, 6719 { "(bad)", { XX } }, 6720 { "(bad)", { XX } }, 6721 { "(bad)", { XX } }, 6722 /* 60 */ 6723 { "(bad)", { XX } }, 6724 { "(bad)", { XX } }, 6725 { "(bad)", { XX } }, 6726 { "(bad)", { XX } }, 6727 { "(bad)", { XX } }, 6728 { "(bad)", { XX } }, 6729 { "(bad)", { XX } }, 6730 { "(bad)", { XX } }, 6731 /* 68 */ 6732 { "(bad)", { XX } }, 6733 { "(bad)", { XX } }, 6734 { "(bad)", { XX } }, 6735 { "(bad)", { XX } }, 6736 { "(bad)", { XX } }, 6737 { "(bad)", { XX } }, 6738 { "(bad)", { XX } }, 6739 { "(bad)", { XX } }, 6740 /* 70 */ 6741 { "(bad)", { XX } }, 6742 { "(bad)", { XX } }, 6743 { "(bad)", { XX } }, 6744 { "(bad)", { XX } }, 6745 { "(bad)", { XX } }, 6746 { "(bad)", { XX } }, 6747 { "(bad)", { XX } }, 6748 { "(bad)", { XX } }, 6749 /* 78 */ 6750 { "(bad)", { XX } }, 6751 { "(bad)", { XX } }, 6752 { "(bad)", { XX } }, 6753 { "(bad)", { XX } }, 6754 { "(bad)", { XX } }, 6755 { "(bad)", { XX } }, 6756 { "(bad)", { XX } }, 6757 { "(bad)", { XX } }, 6758 /* 80 */ 6759 { "(bad)", { XX } }, 6760 { "(bad)", { XX } }, 6761 { "(bad)", { XX } }, 6762 { "(bad)", { XX } }, 6763 { "(bad)", { XX } }, 6764 { "(bad)", { XX } }, 6765 { "(bad)", { XX } }, 6766 { "(bad)", { XX } }, 6767 /* 88 */ 6768 { "(bad)", { XX } }, 6769 { "(bad)", { XX } }, 6770 { "(bad)", { XX } }, 6771 { "(bad)", { XX } }, 6772 { "(bad)", { XX } }, 6773 { "(bad)", { XX } }, 6774 { "(bad)", { XX } }, 6775 { "(bad)", { XX } }, 6776 /* 90 */ 6777 { "(bad)", { XX } }, 6778 { "(bad)", { XX } }, 6779 { "(bad)", { XX } }, 6780 { "(bad)", { XX } }, 6781 { "(bad)", { XX } }, 6782 { "(bad)", { XX } }, 6783 { PREFIX_TABLE (PREFIX_VEX_3896) }, 6784 { PREFIX_TABLE (PREFIX_VEX_3897) }, 6785 /* 98 */ 6786 { PREFIX_TABLE (PREFIX_VEX_3898) }, 6787 { PREFIX_TABLE (PREFIX_VEX_3899) }, 6788 { PREFIX_TABLE (PREFIX_VEX_389A) }, 6789 { PREFIX_TABLE (PREFIX_VEX_389B) }, 6790 { PREFIX_TABLE (PREFIX_VEX_389C) }, 6791 { PREFIX_TABLE (PREFIX_VEX_389D) }, 6792 { PREFIX_TABLE (PREFIX_VEX_389E) }, 6793 { PREFIX_TABLE (PREFIX_VEX_389F) }, 6794 /* a0 */ 6795 { "(bad)", { XX } }, 6796 { "(bad)", { XX } }, 6797 { "(bad)", { XX } }, 6798 { "(bad)", { XX } }, 6799 { "(bad)", { XX } }, 6800 { "(bad)", { XX } }, 6801 { PREFIX_TABLE (PREFIX_VEX_38A6) }, 6802 { PREFIX_TABLE (PREFIX_VEX_38A7) }, 6803 /* a8 */ 6804 { PREFIX_TABLE (PREFIX_VEX_38A8) }, 6805 { PREFIX_TABLE (PREFIX_VEX_38A9) }, 6806 { PREFIX_TABLE (PREFIX_VEX_38AA) }, 6807 { PREFIX_TABLE (PREFIX_VEX_38AB) }, 6808 { PREFIX_TABLE (PREFIX_VEX_38AC) }, 6809 { PREFIX_TABLE (PREFIX_VEX_38AD) }, 6810 { PREFIX_TABLE (PREFIX_VEX_38AE) }, 6811 { PREFIX_TABLE (PREFIX_VEX_38AF) }, 6812 /* b0 */ 6813 { "(bad)", { XX } }, 6814 { "(bad)", { XX } }, 6815 { "(bad)", { XX } }, 6816 { "(bad)", { XX } }, 6817 { "(bad)", { XX } }, 6818 { "(bad)", { XX } }, 6819 { PREFIX_TABLE (PREFIX_VEX_38B6) }, 6820 { PREFIX_TABLE (PREFIX_VEX_38B7) }, 6821 /* b8 */ 6822 { PREFIX_TABLE (PREFIX_VEX_38B8) }, 6823 { PREFIX_TABLE (PREFIX_VEX_38B9) }, 6824 { PREFIX_TABLE (PREFIX_VEX_38BA) }, 6825 { PREFIX_TABLE (PREFIX_VEX_38BB) }, 6826 { PREFIX_TABLE (PREFIX_VEX_38BC) }, 6827 { PREFIX_TABLE (PREFIX_VEX_38BD) }, 6828 { PREFIX_TABLE (PREFIX_VEX_38BE) }, 6829 { PREFIX_TABLE (PREFIX_VEX_38BF) }, 6830 /* c0 */ 6831 { "(bad)", { XX } }, 6832 { "(bad)", { XX } }, 6833 { "(bad)", { XX } }, 6834 { "(bad)", { XX } }, 6835 { "(bad)", { XX } }, 6836 { "(bad)", { XX } }, 6837 { "(bad)", { XX } }, 6838 { "(bad)", { XX } }, 6839 /* c8 */ 6840 { "(bad)", { XX } }, 6841 { "(bad)", { XX } }, 6842 { "(bad)", { XX } }, 6843 { "(bad)", { XX } }, 6844 { "(bad)", { XX } }, 6845 { "(bad)", { XX } }, 6846 { "(bad)", { XX } }, 6847 { "(bad)", { XX } }, 6848 /* d0 */ 6849 { "(bad)", { XX } }, 6850 { "(bad)", { XX } }, 6851 { "(bad)", { XX } }, 6852 { "(bad)", { XX } }, 6853 { "(bad)", { XX } }, 6854 { "(bad)", { XX } }, 6855 { "(bad)", { XX } }, 6856 { "(bad)", { XX } }, 6857 /* d8 */ 6858 { "(bad)", { XX } }, 6859 { "(bad)", { XX } }, 6860 { "(bad)", { XX } }, 6861 { PREFIX_TABLE (PREFIX_VEX_38DB) }, 6862 { PREFIX_TABLE (PREFIX_VEX_38DC) }, 6863 { PREFIX_TABLE (PREFIX_VEX_38DD) }, 6864 { PREFIX_TABLE (PREFIX_VEX_38DE) }, 6865 { PREFIX_TABLE (PREFIX_VEX_38DF) }, 6866 /* e0 */ 6867 { "(bad)", { XX } }, 6868 { "(bad)", { XX } }, 6869 { "(bad)", { XX } }, 6870 { "(bad)", { XX } }, 6871 { "(bad)", { XX } }, 6872 { "(bad)", { XX } }, 6873 { "(bad)", { XX } }, 6874 { "(bad)", { XX } }, 6875 /* e8 */ 6876 { "(bad)", { XX } }, 6877 { "(bad)", { XX } }, 6878 { "(bad)", { XX } }, 6879 { "(bad)", { XX } }, 6880 { "(bad)", { XX } }, 6881 { "(bad)", { XX } }, 6882 { "(bad)", { XX } }, 6883 { "(bad)", { XX } }, 6884 /* f0 */ 6885 { "(bad)", { XX } }, 6886 { "(bad)", { XX } }, 6887 { "(bad)", { XX } }, 6888 { "(bad)", { XX } }, 6889 { "(bad)", { XX } }, 6890 { "(bad)", { XX } }, 6891 { "(bad)", { XX } }, 6892 { "(bad)", { XX } }, 6893 /* f8 */ 6894 { "(bad)", { XX } }, 6895 { "(bad)", { XX } }, 6896 { "(bad)", { XX } }, 6897 { "(bad)", { XX } }, 6898 { "(bad)", { XX } }, 6899 { "(bad)", { XX } }, 6900 { "(bad)", { XX } }, 6901 { "(bad)", { XX } }, 6902 }, 6903 /* VEX_0F3A */ 6904 { 6905 /* 00 */ 6906 { "(bad)", { XX } }, 6907 { "(bad)", { XX } }, 6908 { "(bad)", { XX } }, 6909 { "(bad)", { XX } }, 6910 { PREFIX_TABLE (PREFIX_VEX_3A04) }, 6911 { PREFIX_TABLE (PREFIX_VEX_3A05) }, 6912 { PREFIX_TABLE (PREFIX_VEX_3A06) }, 6913 { "(bad)", { XX } }, 6914 /* 08 */ 6915 { PREFIX_TABLE (PREFIX_VEX_3A08) }, 6916 { PREFIX_TABLE (PREFIX_VEX_3A09) }, 6917 { PREFIX_TABLE (PREFIX_VEX_3A0A) }, 6918 { PREFIX_TABLE (PREFIX_VEX_3A0B) }, 6919 { PREFIX_TABLE (PREFIX_VEX_3A0C) }, 6920 { PREFIX_TABLE (PREFIX_VEX_3A0D) }, 6921 { PREFIX_TABLE (PREFIX_VEX_3A0E) }, 6922 { PREFIX_TABLE (PREFIX_VEX_3A0F) }, 6923 /* 10 */ 6924 { "(bad)", { XX } }, 6925 { "(bad)", { XX } }, 6926 { "(bad)", { XX } }, 6927 { "(bad)", { XX } }, 6928 { PREFIX_TABLE (PREFIX_VEX_3A14) }, 6929 { PREFIX_TABLE (PREFIX_VEX_3A15) }, 6930 { PREFIX_TABLE (PREFIX_VEX_3A16) }, 6931 { PREFIX_TABLE (PREFIX_VEX_3A17) }, 6932 /* 18 */ 6933 { PREFIX_TABLE (PREFIX_VEX_3A18) }, 6934 { PREFIX_TABLE (PREFIX_VEX_3A19) }, 6935 { "(bad)", { XX } }, 6936 { "(bad)", { XX } }, 6937 { "(bad)", { XX } }, 6938 { "(bad)", { XX } }, 6939 { "(bad)", { XX } }, 6940 { "(bad)", { XX } }, 6941 /* 20 */ 6942 { PREFIX_TABLE (PREFIX_VEX_3A20) }, 6943 { PREFIX_TABLE (PREFIX_VEX_3A21) }, 6944 { PREFIX_TABLE (PREFIX_VEX_3A22) }, 6945 { "(bad)", { XX } }, 6946 { "(bad)", { XX } }, 6947 { "(bad)", { XX } }, 6948 { "(bad)", { XX } }, 6949 { "(bad)", { XX } }, 6950 /* 28 */ 6951 { "(bad)", { XX } }, 6952 { "(bad)", { XX } }, 6953 { "(bad)", { XX } }, 6954 { "(bad)", { XX } }, 6955 { "(bad)", { XX } }, 6956 { "(bad)", { XX } }, 6957 { "(bad)", { XX } }, 6958 { "(bad)", { XX } }, 6959 /* 30 */ 6960 { "(bad)", { XX } }, 6961 { "(bad)", { XX } }, 6962 { "(bad)", { XX } }, 6963 { "(bad)", { XX } }, 6964 { "(bad)", { XX } }, 6965 { "(bad)", { XX } }, 6966 { "(bad)", { XX } }, 6967 { "(bad)", { XX } }, 6968 /* 38 */ 6969 { "(bad)", { XX } }, 6970 { "(bad)", { XX } }, 6971 { "(bad)", { XX } }, 6972 { "(bad)", { XX } }, 6973 { "(bad)", { XX } }, 6974 { "(bad)", { XX } }, 6975 { "(bad)", { XX } }, 6976 { "(bad)", { XX } }, 6977 /* 40 */ 6978 { PREFIX_TABLE (PREFIX_VEX_3A40) }, 6979 { PREFIX_TABLE (PREFIX_VEX_3A41) }, 6980 { PREFIX_TABLE (PREFIX_VEX_3A42) }, 6981 { "(bad)", { XX } }, 6982 { PREFIX_TABLE (PREFIX_VEX_3A44) }, 6983 { "(bad)", { XX } }, 6984 { "(bad)", { XX } }, 6985 { "(bad)", { XX } }, 6986 /* 48 */ 6987 { "(bad)", { XX } }, 6988 { "(bad)", { XX } }, 6989 { PREFIX_TABLE (PREFIX_VEX_3A4A) }, 6990 { PREFIX_TABLE (PREFIX_VEX_3A4B) }, 6991 { PREFIX_TABLE (PREFIX_VEX_3A4C) }, 6992 { "(bad)", { XX } }, 6993 { "(bad)", { XX } }, 6994 { "(bad)", { XX } }, 6995 /* 50 */ 6996 { "(bad)", { XX } }, 6997 { "(bad)", { XX } }, 6998 { "(bad)", { XX } }, 6999 { "(bad)", { XX } }, 7000 { "(bad)", { XX } }, 7001 { "(bad)", { XX } }, 7002 { "(bad)", { XX } }, 7003 { "(bad)", { XX } }, 7004 /* 58 */ 7005 { "(bad)", { XX } }, 7006 { "(bad)", { XX } }, 7007 { "(bad)", { XX } }, 7008 { "(bad)", { XX } }, 7009 { PREFIX_TABLE (PREFIX_VEX_3A5C) }, 7010 { PREFIX_TABLE (PREFIX_VEX_3A5D) }, 7011 { PREFIX_TABLE (PREFIX_VEX_3A5E) }, 7012 { PREFIX_TABLE (PREFIX_VEX_3A5F) }, 7013 /* 60 */ 7014 { PREFIX_TABLE (PREFIX_VEX_3A60) }, 7015 { PREFIX_TABLE (PREFIX_VEX_3A61) }, 7016 { PREFIX_TABLE (PREFIX_VEX_3A62) }, 7017 { PREFIX_TABLE (PREFIX_VEX_3A63) }, 7018 { "(bad)", { XX } }, 7019 { "(bad)", { XX } }, 7020 { "(bad)", { XX } }, 7021 { "(bad)", { XX } }, 7022 /* 68 */ 7023 { PREFIX_TABLE (PREFIX_VEX_3A68) }, 7024 { PREFIX_TABLE (PREFIX_VEX_3A69) }, 7025 { PREFIX_TABLE (PREFIX_VEX_3A6A) }, 7026 { PREFIX_TABLE (PREFIX_VEX_3A6B) }, 7027 { PREFIX_TABLE (PREFIX_VEX_3A6C) }, 7028 { PREFIX_TABLE (PREFIX_VEX_3A6D) }, 7029 { PREFIX_TABLE (PREFIX_VEX_3A6E) }, 7030 { PREFIX_TABLE (PREFIX_VEX_3A6F) }, 7031 /* 70 */ 7032 { "(bad)", { XX } }, 7033 { "(bad)", { XX } }, 7034 { "(bad)", { XX } }, 7035 { "(bad)", { XX } }, 7036 { "(bad)", { XX } }, 7037 { "(bad)", { XX } }, 7038 { "(bad)", { XX } }, 7039 { "(bad)", { XX } }, 7040 /* 78 */ 7041 { PREFIX_TABLE (PREFIX_VEX_3A78) }, 7042 { PREFIX_TABLE (PREFIX_VEX_3A79) }, 7043 { PREFIX_TABLE (PREFIX_VEX_3A7A) }, 7044 { PREFIX_TABLE (PREFIX_VEX_3A7B) }, 7045 { PREFIX_TABLE (PREFIX_VEX_3A7C) }, 7046 { PREFIX_TABLE (PREFIX_VEX_3A7D) }, 7047 { PREFIX_TABLE (PREFIX_VEX_3A7E) }, 7048 { PREFIX_TABLE (PREFIX_VEX_3A7F) }, 7049 /* 80 */ 7050 { "(bad)", { XX } }, 7051 { "(bad)", { XX } }, 7052 { "(bad)", { XX } }, 7053 { "(bad)", { XX } }, 7054 { "(bad)", { XX } }, 7055 { "(bad)", { XX } }, 7056 { "(bad)", { XX } }, 7057 { "(bad)", { XX } }, 7058 /* 88 */ 7059 { "(bad)", { XX } }, 7060 { "(bad)", { XX } }, 7061 { "(bad)", { XX } }, 7062 { "(bad)", { XX } }, 7063 { "(bad)", { XX } }, 7064 { "(bad)", { XX } }, 7065 { "(bad)", { XX } }, 7066 { "(bad)", { XX } }, 7067 /* 90 */ 7068 { "(bad)", { XX } }, 7069 { "(bad)", { XX } }, 7070 { "(bad)", { XX } }, 7071 { "(bad)", { XX } }, 7072 { "(bad)", { XX } }, 7073 { "(bad)", { XX } }, 7074 { "(bad)", { XX } }, 7075 { "(bad)", { XX } }, 7076 /* 98 */ 7077 { "(bad)", { XX } }, 7078 { "(bad)", { XX } }, 7079 { "(bad)", { XX } }, 7080 { "(bad)", { XX } }, 7081 { "(bad)", { XX } }, 7082 { "(bad)", { XX } }, 7083 { "(bad)", { XX } }, 7084 { "(bad)", { XX } }, 7085 /* a0 */ 7086 { "(bad)", { XX } }, 7087 { "(bad)", { XX } }, 7088 { "(bad)", { XX } }, 7089 { "(bad)", { XX } }, 7090 { "(bad)", { XX } }, 7091 { "(bad)", { XX } }, 7092 { "(bad)", { XX } }, 7093 { "(bad)", { XX } }, 7094 /* a8 */ 7095 { "(bad)", { XX } }, 7096 { "(bad)", { XX } }, 7097 { "(bad)", { XX } }, 7098 { "(bad)", { XX } }, 7099 { "(bad)", { XX } }, 7100 { "(bad)", { XX } }, 7101 { "(bad)", { XX } }, 7102 { "(bad)", { XX } }, 7103 /* b0 */ 7104 { "(bad)", { XX } }, 7105 { "(bad)", { XX } }, 7106 { "(bad)", { XX } }, 7107 { "(bad)", { XX } }, 7108 { "(bad)", { XX } }, 7109 { "(bad)", { XX } }, 7110 { "(bad)", { XX } }, 7111 { "(bad)", { XX } }, 7112 /* b8 */ 7113 { "(bad)", { XX } }, 7114 { "(bad)", { XX } }, 7115 { "(bad)", { XX } }, 7116 { "(bad)", { XX } }, 7117 { "(bad)", { XX } }, 7118 { "(bad)", { XX } }, 7119 { "(bad)", { XX } }, 7120 { "(bad)", { XX } }, 7121 /* c0 */ 7122 { "(bad)", { XX } }, 7123 { "(bad)", { XX } }, 7124 { "(bad)", { XX } }, 7125 { "(bad)", { XX } }, 7126 { "(bad)", { XX } }, 7127 { "(bad)", { XX } }, 7128 { "(bad)", { XX } }, 7129 { "(bad)", { XX } }, 7130 /* c8 */ 7131 { "(bad)", { XX } }, 7132 { "(bad)", { XX } }, 7133 { "(bad)", { XX } }, 7134 { "(bad)", { XX } }, 7135 { "(bad)", { XX } }, 7136 { "(bad)", { XX } }, 7137 { "(bad)", { XX } }, 7138 { "(bad)", { XX } }, 7139 /* d0 */ 7140 { "(bad)", { XX } }, 7141 { "(bad)", { XX } }, 7142 { "(bad)", { XX } }, 7143 { "(bad)", { XX } }, 7144 { "(bad)", { XX } }, 7145 { "(bad)", { XX } }, 7146 { "(bad)", { XX } }, 7147 { "(bad)", { XX } }, 7148 /* d8 */ 7149 { "(bad)", { XX } }, 7150 { "(bad)", { XX } }, 7151 { "(bad)", { XX } }, 7152 { "(bad)", { XX } }, 7153 { "(bad)", { XX } }, 7154 { "(bad)", { XX } }, 7155 { "(bad)", { XX } }, 7156 { PREFIX_TABLE (PREFIX_VEX_3ADF) }, 7157 /* e0 */ 7158 { "(bad)", { XX } }, 7159 { "(bad)", { XX } }, 7160 { "(bad)", { XX } }, 7161 { "(bad)", { XX } }, 7162 { "(bad)", { XX } }, 7163 { "(bad)", { XX } }, 7164 { "(bad)", { XX } }, 7165 { "(bad)", { XX } }, 7166 /* e8 */ 7167 { "(bad)", { XX } }, 7168 { "(bad)", { XX } }, 7169 { "(bad)", { XX } }, 7170 { "(bad)", { XX } }, 7171 { "(bad)", { XX } }, 7172 { "(bad)", { XX } }, 7173 { "(bad)", { XX } }, 7174 { "(bad)", { XX } }, 7175 /* f0 */ 7176 { "(bad)", { XX } }, 7177 { "(bad)", { XX } }, 7178 { "(bad)", { XX } }, 7179 { "(bad)", { XX } }, 7180 { "(bad)", { XX } }, 7181 { "(bad)", { XX } }, 7182 { "(bad)", { XX } }, 7183 { "(bad)", { XX } }, 7184 /* f8 */ 7185 { "(bad)", { XX } }, 7186 { "(bad)", { XX } }, 7187 { "(bad)", { XX } }, 7188 { "(bad)", { XX } }, 7189 { "(bad)", { XX } }, 7190 { "(bad)", { XX } }, 7191 { "(bad)", { XX } }, 7192 { "(bad)", { XX } }, 7193 }, 7194 }; 7195 7196 static const struct dis386 vex_len_table[][2] = { 7197 /* VEX_LEN_10_P_1 */ 7198 { 7199 { "vmovss", { XMVex, Vex128, EXd } }, 7200 { "(bad)", { XX } }, 7201 }, 7202 7203 /* VEX_LEN_10_P_3 */ 7204 { 7205 { "vmovsd", { XMVex, Vex128, EXq } }, 7206 { "(bad)", { XX } }, 7207 }, 7208 7209 /* VEX_LEN_11_P_1 */ 7210 { 7211 { "vmovss", { EXdVexS, Vex128, XM } }, 7212 { "(bad)", { XX } }, 7213 }, 7214 7215 /* VEX_LEN_11_P_3 */ 7216 { 7217 { "vmovsd", { EXqVexS, Vex128, XM } }, 7218 { "(bad)", { XX } }, 7219 }, 7220 7221 /* VEX_LEN_12_P_0_M_0 */ 7222 { 7223 { "vmovlps", { XM, Vex128, EXq } }, 7224 { "(bad)", { XX } }, 7225 }, 7226 7227 /* VEX_LEN_12_P_0_M_1 */ 7228 { 7229 { "vmovhlps", { XM, Vex128, EXq } }, 7230 { "(bad)", { XX } }, 7231 }, 7232 7233 /* VEX_LEN_12_P_2 */ 7234 { 7235 { "vmovlpd", { XM, Vex128, EXq } }, 7236 { "(bad)", { XX } }, 7237 }, 7238 7239 /* VEX_LEN_13_M_0 */ 7240 { 7241 { "vmovlpX", { EXq, XM } }, 7242 { "(bad)", { XX } }, 7243 }, 7244 7245 /* VEX_LEN_16_P_0_M_0 */ 7246 { 7247 { "vmovhps", { XM, Vex128, EXq } }, 7248 { "(bad)", { XX } }, 7249 }, 7250 7251 /* VEX_LEN_16_P_0_M_1 */ 7252 { 7253 { "vmovlhps", { XM, Vex128, EXq } }, 7254 { "(bad)", { XX } }, 7255 }, 7256 7257 /* VEX_LEN_16_P_2 */ 7258 { 7259 { "vmovhpd", { XM, Vex128, EXq } }, 7260 { "(bad)", { XX } }, 7261 }, 7262 7263 /* VEX_LEN_17_M_0 */ 7264 { 7265 { "vmovhpX", { EXq, XM } }, 7266 { "(bad)", { XX } }, 7267 }, 7268 7269 /* VEX_LEN_2A_P_1 */ 7270 { 7271 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } }, 7272 { "(bad)", { XX } }, 7273 }, 7274 7275 /* VEX_LEN_2A_P_3 */ 7276 { 7277 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } }, 7278 { "(bad)", { XX } }, 7279 }, 7280 7281 /* VEX_LEN_2C_P_1 */ 7282 { 7283 { "vcvttss2siY", { Gv, EXd } }, 7284 { "(bad)", { XX } }, 7285 }, 7286 7287 /* VEX_LEN_2C_P_3 */ 7288 { 7289 { "vcvttsd2siY", { Gv, EXq } }, 7290 { "(bad)", { XX } }, 7291 }, 7292 7293 /* VEX_LEN_2D_P_1 */ 7294 { 7295 { "vcvtss2siY", { Gv, EXd } }, 7296 { "(bad)", { XX } }, 7297 }, 7298 7299 /* VEX_LEN_2D_P_3 */ 7300 { 7301 { "vcvtsd2siY", { Gv, EXq } }, 7302 { "(bad)", { XX } }, 7303 }, 7304 7305 /* VEX_LEN_2E_P_0 */ 7306 { 7307 { "vucomiss", { XM, EXd } }, 7308 { "(bad)", { XX } }, 7309 }, 7310 7311 /* VEX_LEN_2E_P_2 */ 7312 { 7313 { "vucomisd", { XM, EXq } }, 7314 { "(bad)", { XX } }, 7315 }, 7316 7317 /* VEX_LEN_2F_P_0 */ 7318 { 7319 { "vcomiss", { XM, EXd } }, 7320 { "(bad)", { XX } }, 7321 }, 7322 7323 /* VEX_LEN_2F_P_2 */ 7324 { 7325 { "vcomisd", { XM, EXq } }, 7326 { "(bad)", { XX } }, 7327 }, 7328 7329 /* VEX_LEN_51_P_1 */ 7330 { 7331 { "vsqrtss", { XM, Vex128, EXd } }, 7332 { "(bad)", { XX } }, 7333 }, 7334 7335 /* VEX_LEN_51_P_3 */ 7336 { 7337 { "vsqrtsd", { XM, Vex128, EXq } }, 7338 { "(bad)", { XX } }, 7339 }, 7340 7341 /* VEX_LEN_52_P_1 */ 7342 { 7343 { "vrsqrtss", { XM, Vex128, EXd } }, 7344 { "(bad)", { XX } }, 7345 }, 7346 7347 /* VEX_LEN_53_P_1 */ 7348 { 7349 { "vrcpss", { XM, Vex128, EXd } }, 7350 { "(bad)", { XX } }, 7351 }, 7352 7353 /* VEX_LEN_58_P_1 */ 7354 { 7355 { "vaddss", { XM, Vex128, EXd } }, 7356 { "(bad)", { XX } }, 7357 }, 7358 7359 /* VEX_LEN_58_P_3 */ 7360 { 7361 { "vaddsd", { XM, Vex128, EXq } }, 7362 { "(bad)", { XX } }, 7363 }, 7364 7365 /* VEX_LEN_59_P_1 */ 7366 { 7367 { "vmulss", { XM, Vex128, EXd } }, 7368 { "(bad)", { XX } }, 7369 }, 7370 7371 /* VEX_LEN_59_P_3 */ 7372 { 7373 { "vmulsd", { XM, Vex128, EXq } }, 7374 { "(bad)", { XX } }, 7375 }, 7376 7377 /* VEX_LEN_5A_P_1 */ 7378 { 7379 { "vcvtss2sd", { XM, Vex128, EXd } }, 7380 { "(bad)", { XX } }, 7381 }, 7382 7383 /* VEX_LEN_5A_P_3 */ 7384 { 7385 { "vcvtsd2ss", { XM, Vex128, EXq } }, 7386 { "(bad)", { XX } }, 7387 }, 7388 7389 /* VEX_LEN_5C_P_1 */ 7390 { 7391 { "vsubss", { XM, Vex128, EXd } }, 7392 { "(bad)", { XX } }, 7393 }, 7394 7395 /* VEX_LEN_5C_P_3 */ 7396 { 7397 { "vsubsd", { XM, Vex128, EXq } }, 7398 { "(bad)", { XX } }, 7399 }, 7400 7401 /* VEX_LEN_5D_P_1 */ 7402 { 7403 { "vminss", { XM, Vex128, EXd } }, 7404 { "(bad)", { XX } }, 7405 }, 7406 7407 /* VEX_LEN_5D_P_3 */ 7408 { 7409 { "vminsd", { XM, Vex128, EXq } }, 7410 { "(bad)", { XX } }, 7411 }, 7412 7413 /* VEX_LEN_5E_P_1 */ 7414 { 7415 { "vdivss", { XM, Vex128, EXd } }, 7416 { "(bad)", { XX } }, 7417 }, 7418 7419 /* VEX_LEN_5E_P_3 */ 7420 { 7421 { "vdivsd", { XM, Vex128, EXq } }, 7422 { "(bad)", { XX } }, 7423 }, 7424 7425 /* VEX_LEN_5F_P_1 */ 7426 { 7427 { "vmaxss", { XM, Vex128, EXd } }, 7428 { "(bad)", { XX } }, 7429 }, 7430 7431 /* VEX_LEN_5F_P_3 */ 7432 { 7433 { "vmaxsd", { XM, Vex128, EXq } }, 7434 { "(bad)", { XX } }, 7435 }, 7436 7437 /* VEX_LEN_60_P_2 */ 7438 { 7439 { "vpunpcklbw", { XM, Vex128, EXx } }, 7440 { "(bad)", { XX } }, 7441 }, 7442 7443 /* VEX_LEN_61_P_2 */ 7444 { 7445 { "vpunpcklwd", { XM, Vex128, EXx } }, 7446 { "(bad)", { XX } }, 7447 }, 7448 7449 /* VEX_LEN_62_P_2 */ 7450 { 7451 { "vpunpckldq", { XM, Vex128, EXx } }, 7452 { "(bad)", { XX } }, 7453 }, 7454 7455 /* VEX_LEN_63_P_2 */ 7456 { 7457 { "vpacksswb", { XM, Vex128, EXx } }, 7458 { "(bad)", { XX } }, 7459 }, 7460 7461 /* VEX_LEN_64_P_2 */ 7462 { 7463 { "vpcmpgtb", { XM, Vex128, EXx } }, 7464 { "(bad)", { XX } }, 7465 }, 7466 7467 /* VEX_LEN_65_P_2 */ 7468 { 7469 { "vpcmpgtw", { XM, Vex128, EXx } }, 7470 { "(bad)", { XX } }, 7471 }, 7472 7473 /* VEX_LEN_66_P_2 */ 7474 { 7475 { "vpcmpgtd", { XM, Vex128, EXx } }, 7476 { "(bad)", { XX } }, 7477 }, 7478 7479 /* VEX_LEN_67_P_2 */ 7480 { 7481 { "vpackuswb", { XM, Vex128, EXx } }, 7482 { "(bad)", { XX } }, 7483 }, 7484 7485 /* VEX_LEN_68_P_2 */ 7486 { 7487 { "vpunpckhbw", { XM, Vex128, EXx } }, 7488 { "(bad)", { XX } }, 7489 }, 7490 7491 /* VEX_LEN_69_P_2 */ 7492 { 7493 { "vpunpckhwd", { XM, Vex128, EXx } }, 7494 { "(bad)", { XX } }, 7495 }, 7496 7497 /* VEX_LEN_6A_P_2 */ 7498 { 7499 { "vpunpckhdq", { XM, Vex128, EXx } }, 7500 { "(bad)", { XX } }, 7501 }, 7502 7503 /* VEX_LEN_6B_P_2 */ 7504 { 7505 { "vpackssdw", { XM, Vex128, EXx } }, 7506 { "(bad)", { XX } }, 7507 }, 7508 7509 /* VEX_LEN_6C_P_2 */ 7510 { 7511 { "vpunpcklqdq", { XM, Vex128, EXx } }, 7512 { "(bad)", { XX } }, 7513 }, 7514 7515 /* VEX_LEN_6D_P_2 */ 7516 { 7517 { "vpunpckhqdq", { XM, Vex128, EXx } }, 7518 { "(bad)", { XX } }, 7519 }, 7520 7521 /* VEX_LEN_6E_P_2 */ 7522 { 7523 { "vmovK", { XM, Edq } }, 7524 { "(bad)", { XX } }, 7525 }, 7526 7527 /* VEX_LEN_70_P_1 */ 7528 { 7529 { "vpshufhw", { XM, EXx, Ib } }, 7530 { "(bad)", { XX } }, 7531 }, 7532 7533 /* VEX_LEN_70_P_2 */ 7534 { 7535 { "vpshufd", { XM, EXx, Ib } }, 7536 { "(bad)", { XX } }, 7537 }, 7538 7539 /* VEX_LEN_70_P_3 */ 7540 { 7541 { "vpshuflw", { XM, EXx, Ib } }, 7542 { "(bad)", { XX } }, 7543 }, 7544 7545 /* VEX_LEN_71_R_2_P_2 */ 7546 { 7547 { "vpsrlw", { Vex128, XS, Ib } }, 7548 { "(bad)", { XX } }, 7549 }, 7550 7551 /* VEX_LEN_71_R_4_P_2 */ 7552 { 7553 { "vpsraw", { Vex128, XS, Ib } }, 7554 { "(bad)", { XX } }, 7555 }, 7556 7557 /* VEX_LEN_71_R_6_P_2 */ 7558 { 7559 { "vpsllw", { Vex128, XS, Ib } }, 7560 { "(bad)", { XX } }, 7561 }, 7562 7563 /* VEX_LEN_72_R_2_P_2 */ 7564 { 7565 { "vpsrld", { Vex128, XS, Ib } }, 7566 { "(bad)", { XX } }, 7567 }, 7568 7569 /* VEX_LEN_72_R_4_P_2 */ 7570 { 7571 { "vpsrad", { Vex128, XS, Ib } }, 7572 { "(bad)", { XX } }, 7573 }, 7574 7575 /* VEX_LEN_72_R_6_P_2 */ 7576 { 7577 { "vpslld", { Vex128, XS, Ib } }, 7578 { "(bad)", { XX } }, 7579 }, 7580 7581 /* VEX_LEN_73_R_2_P_2 */ 7582 { 7583 { "vpsrlq", { Vex128, XS, Ib } }, 7584 { "(bad)", { XX } }, 7585 }, 7586 7587 /* VEX_LEN_73_R_3_P_2 */ 7588 { 7589 { "vpsrldq", { Vex128, XS, Ib } }, 7590 { "(bad)", { XX } }, 7591 }, 7592 7593 /* VEX_LEN_73_R_6_P_2 */ 7594 { 7595 { "vpsllq", { Vex128, XS, Ib } }, 7596 { "(bad)", { XX } }, 7597 }, 7598 7599 /* VEX_LEN_73_R_7_P_2 */ 7600 { 7601 { "vpslldq", { Vex128, XS, Ib } }, 7602 { "(bad)", { XX } }, 7603 }, 7604 7605 /* VEX_LEN_74_P_2 */ 7606 { 7607 { "vpcmpeqb", { XM, Vex128, EXx } }, 7608 { "(bad)", { XX } }, 7609 }, 7610 7611 /* VEX_LEN_75_P_2 */ 7612 { 7613 { "vpcmpeqw", { XM, Vex128, EXx } }, 7614 { "(bad)", { XX } }, 7615 }, 7616 7617 /* VEX_LEN_76_P_2 */ 7618 { 7619 { "vpcmpeqd", { XM, Vex128, EXx } }, 7620 { "(bad)", { XX } }, 7621 }, 7622 7623 /* VEX_LEN_7E_P_1 */ 7624 { 7625 { "vmovq", { XM, EXq } }, 7626 { "(bad)", { XX } }, 7627 }, 7628 7629 /* VEX_LEN_7E_P_2 */ 7630 { 7631 { "vmovK", { Edq, XM } }, 7632 { "(bad)", { XX } }, 7633 }, 7634 7635 /* VEX_LEN_AE_R_2_M_0 */ 7636 { 7637 { "vldmxcsr", { Md } }, 7638 { "(bad)", { XX } }, 7639 }, 7640 7641 /* VEX_LEN_AE_R_3_M_0 */ 7642 { 7643 { "vstmxcsr", { Md } }, 7644 { "(bad)", { XX } }, 7645 }, 7646 7647 /* VEX_LEN_C2_P_1 */ 7648 { 7649 { "vcmpss", { XM, Vex128, EXd, VCMP } }, 7650 { "(bad)", { XX } }, 7651 }, 7652 7653 /* VEX_LEN_C2_P_3 */ 7654 { 7655 { "vcmpsd", { XM, Vex128, EXq, VCMP } }, 7656 { "(bad)", { XX } }, 7657 }, 7658 7659 /* VEX_LEN_C4_P_2 */ 7660 { 7661 { "vpinsrw", { XM, Vex128, Edqw, Ib } }, 7662 { "(bad)", { XX } }, 7663 }, 7664 7665 /* VEX_LEN_C5_P_2 */ 7666 { 7667 { "vpextrw", { Gdq, XS, Ib } }, 7668 { "(bad)", { XX } }, 7669 }, 7670 7671 /* VEX_LEN_D1_P_2 */ 7672 { 7673 { "vpsrlw", { XM, Vex128, EXx } }, 7674 { "(bad)", { XX } }, 7675 }, 7676 7677 /* VEX_LEN_D2_P_2 */ 7678 { 7679 { "vpsrld", { XM, Vex128, EXx } }, 7680 { "(bad)", { XX } }, 7681 }, 7682 7683 /* VEX_LEN_D3_P_2 */ 7684 { 7685 { "vpsrlq", { XM, Vex128, EXx } }, 7686 { "(bad)", { XX } }, 7687 }, 7688 7689 /* VEX_LEN_D4_P_2 */ 7690 { 7691 { "vpaddq", { XM, Vex128, EXx } }, 7692 { "(bad)", { XX } }, 7693 }, 7694 7695 /* VEX_LEN_D5_P_2 */ 7696 { 7697 { "vpmullw", { XM, Vex128, EXx } }, 7698 { "(bad)", { XX } }, 7699 }, 7700 7701 /* VEX_LEN_D6_P_2 */ 7702 { 7703 { "vmovq", { EXqS, XM } }, 7704 { "(bad)", { XX } }, 7705 }, 7706 7707 /* VEX_LEN_D7_P_2_M_1 */ 7708 { 7709 { "vpmovmskb", { Gdq, XS } }, 7710 { "(bad)", { XX } }, 7711 }, 7712 7713 /* VEX_LEN_D8_P_2 */ 7714 { 7715 { "vpsubusb", { XM, Vex128, EXx } }, 7716 { "(bad)", { XX } }, 7717 }, 7718 7719 /* VEX_LEN_D9_P_2 */ 7720 { 7721 { "vpsubusw", { XM, Vex128, EXx } }, 7722 { "(bad)", { XX } }, 7723 }, 7724 7725 /* VEX_LEN_DA_P_2 */ 7726 { 7727 { "vpminub", { XM, Vex128, EXx } }, 7728 { "(bad)", { XX } }, 7729 }, 7730 7731 /* VEX_LEN_DB_P_2 */ 7732 { 7733 { "vpand", { XM, Vex128, EXx } }, 7734 { "(bad)", { XX } }, 7735 }, 7736 7737 /* VEX_LEN_DC_P_2 */ 7738 { 7739 { "vpaddusb", { XM, Vex128, EXx } }, 7740 { "(bad)", { XX } }, 7741 }, 7742 7743 /* VEX_LEN_DD_P_2 */ 7744 { 7745 { "vpaddusw", { XM, Vex128, EXx } }, 7746 { "(bad)", { XX } }, 7747 }, 7748 7749 /* VEX_LEN_DE_P_2 */ 7750 { 7751 { "vpmaxub", { XM, Vex128, EXx } }, 7752 { "(bad)", { XX } }, 7753 }, 7754 7755 /* VEX_LEN_DF_P_2 */ 7756 { 7757 { "vpandn", { XM, Vex128, EXx } }, 7758 { "(bad)", { XX } }, 7759 }, 7760 7761 /* VEX_LEN_E0_P_2 */ 7762 { 7763 { "vpavgb", { XM, Vex128, EXx } }, 7764 { "(bad)", { XX } }, 7765 }, 7766 7767 /* VEX_LEN_E1_P_2 */ 7768 { 7769 { "vpsraw", { XM, Vex128, EXx } }, 7770 { "(bad)", { XX } }, 7771 }, 7772 7773 /* VEX_LEN_E2_P_2 */ 7774 { 7775 { "vpsrad", { XM, Vex128, EXx } }, 7776 { "(bad)", { XX } }, 7777 }, 7778 7779 /* VEX_LEN_E3_P_2 */ 7780 { 7781 { "vpavgw", { XM, Vex128, EXx } }, 7782 { "(bad)", { XX } }, 7783 }, 7784 7785 /* VEX_LEN_E4_P_2 */ 7786 { 7787 { "vpmulhuw", { XM, Vex128, EXx } }, 7788 { "(bad)", { XX } }, 7789 }, 7790 7791 /* VEX_LEN_E5_P_2 */ 7792 { 7793 { "vpmulhw", { XM, Vex128, EXx } }, 7794 { "(bad)", { XX } }, 7795 }, 7796 7797 /* VEX_LEN_E8_P_2 */ 7798 { 7799 { "vpsubsb", { XM, Vex128, EXx } }, 7800 { "(bad)", { XX } }, 7801 }, 7802 7803 /* VEX_LEN_E9_P_2 */ 7804 { 7805 { "vpsubsw", { XM, Vex128, EXx } }, 7806 { "(bad)", { XX } }, 7807 }, 7808 7809 /* VEX_LEN_EA_P_2 */ 7810 { 7811 { "vpminsw", { XM, Vex128, EXx } }, 7812 { "(bad)", { XX } }, 7813 }, 7814 7815 /* VEX_LEN_EB_P_2 */ 7816 { 7817 { "vpor", { XM, Vex128, EXx } }, 7818 { "(bad)", { XX } }, 7819 }, 7820 7821 /* VEX_LEN_EC_P_2 */ 7822 { 7823 { "vpaddsb", { XM, Vex128, EXx } }, 7824 { "(bad)", { XX } }, 7825 }, 7826 7827 /* VEX_LEN_ED_P_2 */ 7828 { 7829 { "vpaddsw", { XM, Vex128, EXx } }, 7830 { "(bad)", { XX } }, 7831 }, 7832 7833 /* VEX_LEN_EE_P_2 */ 7834 { 7835 { "vpmaxsw", { XM, Vex128, EXx } }, 7836 { "(bad)", { XX } }, 7837 }, 7838 7839 /* VEX_LEN_EF_P_2 */ 7840 { 7841 { "vpxor", { XM, Vex128, EXx } }, 7842 { "(bad)", { XX } }, 7843 }, 7844 7845 /* VEX_LEN_F1_P_2 */ 7846 { 7847 { "vpsllw", { XM, Vex128, EXx } }, 7848 { "(bad)", { XX } }, 7849 }, 7850 7851 /* VEX_LEN_F2_P_2 */ 7852 { 7853 { "vpslld", { XM, Vex128, EXx } }, 7854 { "(bad)", { XX } }, 7855 }, 7856 7857 /* VEX_LEN_F3_P_2 */ 7858 { 7859 { "vpsllq", { XM, Vex128, EXx } }, 7860 { "(bad)", { XX } }, 7861 }, 7862 7863 /* VEX_LEN_F4_P_2 */ 7864 { 7865 { "vpmuludq", { XM, Vex128, EXx } }, 7866 { "(bad)", { XX } }, 7867 }, 7868 7869 /* VEX_LEN_F5_P_2 */ 7870 { 7871 { "vpmaddwd", { XM, Vex128, EXx } }, 7872 { "(bad)", { XX } }, 7873 }, 7874 7875 /* VEX_LEN_F6_P_2 */ 7876 { 7877 { "vpsadbw", { XM, Vex128, EXx } }, 7878 { "(bad)", { XX } }, 7879 }, 7880 7881 /* VEX_LEN_F7_P_2 */ 7882 { 7883 { "vmaskmovdqu", { XM, XS } }, 7884 { "(bad)", { XX } }, 7885 }, 7886 7887 /* VEX_LEN_F8_P_2 */ 7888 { 7889 { "vpsubb", { XM, Vex128, EXx } }, 7890 { "(bad)", { XX } }, 7891 }, 7892 7893 /* VEX_LEN_F9_P_2 */ 7894 { 7895 { "vpsubw", { XM, Vex128, EXx } }, 7896 { "(bad)", { XX } }, 7897 }, 7898 7899 /* VEX_LEN_FA_P_2 */ 7900 { 7901 { "vpsubd", { XM, Vex128, EXx } }, 7902 { "(bad)", { XX } }, 7903 }, 7904 7905 /* VEX_LEN_FB_P_2 */ 7906 { 7907 { "vpsubq", { XM, Vex128, EXx } }, 7908 { "(bad)", { XX } }, 7909 }, 7910 7911 /* VEX_LEN_FC_P_2 */ 7912 { 7913 { "vpaddb", { XM, Vex128, EXx } }, 7914 { "(bad)", { XX } }, 7915 }, 7916 7917 /* VEX_LEN_FD_P_2 */ 7918 { 7919 { "vpaddw", { XM, Vex128, EXx } }, 7920 { "(bad)", { XX } }, 7921 }, 7922 7923 /* VEX_LEN_FE_P_2 */ 7924 { 7925 { "vpaddd", { XM, Vex128, EXx } }, 7926 { "(bad)", { XX } }, 7927 }, 7928 7929 /* VEX_LEN_3800_P_2 */ 7930 { 7931 { "vpshufb", { XM, Vex128, EXx } }, 7932 { "(bad)", { XX } }, 7933 }, 7934 7935 /* VEX_LEN_3801_P_2 */ 7936 { 7937 { "vphaddw", { XM, Vex128, EXx } }, 7938 { "(bad)", { XX } }, 7939 }, 7940 7941 /* VEX_LEN_3802_P_2 */ 7942 { 7943 { "vphaddd", { XM, Vex128, EXx } }, 7944 { "(bad)", { XX } }, 7945 }, 7946 7947 /* VEX_LEN_3803_P_2 */ 7948 { 7949 { "vphaddsw", { XM, Vex128, EXx } }, 7950 { "(bad)", { XX } }, 7951 }, 7952 7953 /* VEX_LEN_3804_P_2 */ 7954 { 7955 { "vpmaddubsw", { XM, Vex128, EXx } }, 7956 { "(bad)", { XX } }, 7957 }, 7958 7959 /* VEX_LEN_3805_P_2 */ 7960 { 7961 { "vphsubw", { XM, Vex128, EXx } }, 7962 { "(bad)", { XX } }, 7963 }, 7964 7965 /* VEX_LEN_3806_P_2 */ 7966 { 7967 { "vphsubd", { XM, Vex128, EXx } }, 7968 { "(bad)", { XX } }, 7969 }, 7970 7971 /* VEX_LEN_3807_P_2 */ 7972 { 7973 { "vphsubsw", { XM, Vex128, EXx } }, 7974 { "(bad)", { XX } }, 7975 }, 7976 7977 /* VEX_LEN_3808_P_2 */ 7978 { 7979 { "vpsignb", { XM, Vex128, EXx } }, 7980 { "(bad)", { XX } }, 7981 }, 7982 7983 /* VEX_LEN_3809_P_2 */ 7984 { 7985 { "vpsignw", { XM, Vex128, EXx } }, 7986 { "(bad)", { XX } }, 7987 }, 7988 7989 /* VEX_LEN_380A_P_2 */ 7990 { 7991 { "vpsignd", { XM, Vex128, EXx } }, 7992 { "(bad)", { XX } }, 7993 }, 7994 7995 /* VEX_LEN_380B_P_2 */ 7996 { 7997 { "vpmulhrsw", { XM, Vex128, EXx } }, 7998 { "(bad)", { XX } }, 7999 }, 8000 8001 /* VEX_LEN_3819_P_2_M_0 */ 8002 { 8003 { "(bad)", { XX } }, 8004 { "vbroadcastsd", { XM, Mq } }, 8005 }, 8006 8007 /* VEX_LEN_381A_P_2_M_0 */ 8008 { 8009 { "(bad)", { XX } }, 8010 { "vbroadcastf128", { XM, Mxmm } }, 8011 }, 8012 8013 /* VEX_LEN_381C_P_2 */ 8014 { 8015 { "vpabsb", { XM, EXx } }, 8016 { "(bad)", { XX } }, 8017 }, 8018 8019 /* VEX_LEN_381D_P_2 */ 8020 { 8021 { "vpabsw", { XM, EXx } }, 8022 { "(bad)", { XX } }, 8023 }, 8024 8025 /* VEX_LEN_381E_P_2 */ 8026 { 8027 { "vpabsd", { XM, EXx } }, 8028 { "(bad)", { XX } }, 8029 }, 8030 8031 /* VEX_LEN_3820_P_2 */ 8032 { 8033 { "vpmovsxbw", { XM, EXq } }, 8034 { "(bad)", { XX } }, 8035 }, 8036 8037 /* VEX_LEN_3821_P_2 */ 8038 { 8039 { "vpmovsxbd", { XM, EXd } }, 8040 { "(bad)", { XX } }, 8041 }, 8042 8043 /* VEX_LEN_3822_P_2 */ 8044 { 8045 { "vpmovsxbq", { XM, EXw } }, 8046 { "(bad)", { XX } }, 8047 }, 8048 8049 /* VEX_LEN_3823_P_2 */ 8050 { 8051 { "vpmovsxwd", { XM, EXq } }, 8052 { "(bad)", { XX } }, 8053 }, 8054 8055 /* VEX_LEN_3824_P_2 */ 8056 { 8057 { "vpmovsxwq", { XM, EXd } }, 8058 { "(bad)", { XX } }, 8059 }, 8060 8061 /* VEX_LEN_3825_P_2 */ 8062 { 8063 { "vpmovsxdq", { XM, EXq } }, 8064 { "(bad)", { XX } }, 8065 }, 8066 8067 /* VEX_LEN_3828_P_2 */ 8068 { 8069 { "vpmuldq", { XM, Vex128, EXx } }, 8070 { "(bad)", { XX } }, 8071 }, 8072 8073 /* VEX_LEN_3829_P_2 */ 8074 { 8075 { "vpcmpeqq", { XM, Vex128, EXx } }, 8076 { "(bad)", { XX } }, 8077 }, 8078 8079 /* VEX_LEN_382A_P_2_M_0 */ 8080 { 8081 { "vmovntdqa", { XM, Mx } }, 8082 { "(bad)", { XX } }, 8083 }, 8084 8085 /* VEX_LEN_382B_P_2 */ 8086 { 8087 { "vpackusdw", { XM, Vex128, EXx } }, 8088 { "(bad)", { XX } }, 8089 }, 8090 8091 /* VEX_LEN_3830_P_2 */ 8092 { 8093 { "vpmovzxbw", { XM, EXq } }, 8094 { "(bad)", { XX } }, 8095 }, 8096 8097 /* VEX_LEN_3831_P_2 */ 8098 { 8099 { "vpmovzxbd", { XM, EXd } }, 8100 { "(bad)", { XX } }, 8101 }, 8102 8103 /* VEX_LEN_3832_P_2 */ 8104 { 8105 { "vpmovzxbq", { XM, EXw } }, 8106 { "(bad)", { XX } }, 8107 }, 8108 8109 /* VEX_LEN_3833_P_2 */ 8110 { 8111 { "vpmovzxwd", { XM, EXq } }, 8112 { "(bad)", { XX } }, 8113 }, 8114 8115 /* VEX_LEN_3834_P_2 */ 8116 { 8117 { "vpmovzxwq", { XM, EXd } }, 8118 { "(bad)", { XX } }, 8119 }, 8120 8121 /* VEX_LEN_3835_P_2 */ 8122 { 8123 { "vpmovzxdq", { XM, EXq } }, 8124 { "(bad)", { XX } }, 8125 }, 8126 8127 /* VEX_LEN_3837_P_2 */ 8128 { 8129 { "vpcmpgtq", { XM, Vex128, EXx } }, 8130 { "(bad)", { XX } }, 8131 }, 8132 8133 /* VEX_LEN_3838_P_2 */ 8134 { 8135 { "vpminsb", { XM, Vex128, EXx } }, 8136 { "(bad)", { XX } }, 8137 }, 8138 8139 /* VEX_LEN_3839_P_2 */ 8140 { 8141 { "vpminsd", { XM, Vex128, EXx } }, 8142 { "(bad)", { XX } }, 8143 }, 8144 8145 /* VEX_LEN_383A_P_2 */ 8146 { 8147 { "vpminuw", { XM, Vex128, EXx } }, 8148 { "(bad)", { XX } }, 8149 }, 8150 8151 /* VEX_LEN_383B_P_2 */ 8152 { 8153 { "vpminud", { XM, Vex128, EXx } }, 8154 { "(bad)", { XX } }, 8155 }, 8156 8157 /* VEX_LEN_383C_P_2 */ 8158 { 8159 { "vpmaxsb", { XM, Vex128, EXx } }, 8160 { "(bad)", { XX } }, 8161 }, 8162 8163 /* VEX_LEN_383D_P_2 */ 8164 { 8165 { "vpmaxsd", { XM, Vex128, EXx } }, 8166 { "(bad)", { XX } }, 8167 }, 8168 8169 /* VEX_LEN_383E_P_2 */ 8170 { 8171 { "vpmaxuw", { XM, Vex128, EXx } }, 8172 { "(bad)", { XX } }, 8173 }, 8174 8175 /* VEX_LEN_383F_P_2 */ 8176 { 8177 { "vpmaxud", { XM, Vex128, EXx } }, 8178 { "(bad)", { XX } }, 8179 }, 8180 8181 /* VEX_LEN_3840_P_2 */ 8182 { 8183 { "vpmulld", { XM, Vex128, EXx } }, 8184 { "(bad)", { XX } }, 8185 }, 8186 8187 /* VEX_LEN_3841_P_2 */ 8188 { 8189 { "vphminposuw", { XM, EXx } }, 8190 { "(bad)", { XX } }, 8191 }, 8192 8193 /* VEX_LEN_38DB_P_2 */ 8194 { 8195 { "vaesimc", { XM, EXx } }, 8196 { "(bad)", { XX } }, 8197 }, 8198 8199 /* VEX_LEN_38DC_P_2 */ 8200 { 8201 { "vaesenc", { XM, Vex128, EXx } }, 8202 { "(bad)", { XX } }, 8203 }, 8204 8205 /* VEX_LEN_38DD_P_2 */ 8206 { 8207 { "vaesenclast", { XM, Vex128, EXx } }, 8208 { "(bad)", { XX } }, 8209 }, 8210 8211 /* VEX_LEN_38DE_P_2 */ 8212 { 8213 { "vaesdec", { XM, Vex128, EXx } }, 8214 { "(bad)", { XX } }, 8215 }, 8216 8217 /* VEX_LEN_38DF_P_2 */ 8218 { 8219 { "vaesdeclast", { XM, Vex128, EXx } }, 8220 { "(bad)", { XX } }, 8221 }, 8222 8223 /* VEX_LEN_3A06_P_2 */ 8224 { 8225 { "(bad)", { XX } }, 8226 { "vperm2f128", { XM, Vex256, EXx, Ib } }, 8227 }, 8228 8229 /* VEX_LEN_3A0A_P_2 */ 8230 { 8231 { "vroundss", { XM, Vex128, EXd, Ib } }, 8232 { "(bad)", { XX } }, 8233 }, 8234 8235 /* VEX_LEN_3A0B_P_2 */ 8236 { 8237 { "vroundsd", { XM, Vex128, EXq, Ib } }, 8238 { "(bad)", { XX } }, 8239 }, 8240 8241 /* VEX_LEN_3A0E_P_2 */ 8242 { 8243 { "vpblendw", { XM, Vex128, EXx, Ib } }, 8244 { "(bad)", { XX } }, 8245 }, 8246 8247 /* VEX_LEN_3A0F_P_2 */ 8248 { 8249 { "vpalignr", { XM, Vex128, EXx, Ib } }, 8250 { "(bad)", { XX } }, 8251 }, 8252 8253 /* VEX_LEN_3A14_P_2 */ 8254 { 8255 { "vpextrb", { Edqb, XM, Ib } }, 8256 { "(bad)", { XX } }, 8257 }, 8258 8259 /* VEX_LEN_3A15_P_2 */ 8260 { 8261 { "vpextrw", { Edqw, XM, Ib } }, 8262 { "(bad)", { XX } }, 8263 }, 8264 8265 /* VEX_LEN_3A16_P_2 */ 8266 { 8267 { "vpextrK", { Edq, XM, Ib } }, 8268 { "(bad)", { XX } }, 8269 }, 8270 8271 /* VEX_LEN_3A17_P_2 */ 8272 { 8273 { "vextractps", { Edqd, XM, Ib } }, 8274 { "(bad)", { XX } }, 8275 }, 8276 8277 /* VEX_LEN_3A18_P_2 */ 8278 { 8279 { "(bad)", { XX } }, 8280 { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, 8281 }, 8282 8283 /* VEX_LEN_3A19_P_2 */ 8284 { 8285 { "(bad)", { XX } }, 8286 { "vextractf128", { EXxmm, XM, Ib } }, 8287 }, 8288 8289 /* VEX_LEN_3A20_P_2 */ 8290 { 8291 { "vpinsrb", { XM, Vex128, Edqb, Ib } }, 8292 { "(bad)", { XX } }, 8293 }, 8294 8295 /* VEX_LEN_3A21_P_2 */ 8296 { 8297 { "vinsertps", { XM, Vex128, EXd, Ib } }, 8298 { "(bad)", { XX } }, 8299 }, 8300 8301 /* VEX_LEN_3A22_P_2 */ 8302 { 8303 { "vpinsrK", { XM, Vex128, Edq, Ib } }, 8304 { "(bad)", { XX } }, 8305 }, 8306 8307 /* VEX_LEN_3A41_P_2 */ 8308 { 8309 { "vdppd", { XM, Vex128, EXx, Ib } }, 8310 { "(bad)", { XX } }, 8311 }, 8312 8313 /* VEX_LEN_3A42_P_2 */ 8314 { 8315 { "vmpsadbw", { XM, Vex128, EXx, Ib } }, 8316 { "(bad)", { XX } }, 8317 }, 8318 8319 /* VEX_LEN_3A44_P_2 */ 8320 { 8321 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, 8322 { "(bad)", { XX } }, 8323 }, 8324 8325 /* VEX_LEN_3A4C_P_2 */ 8326 { 8327 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } }, 8328 { "(bad)", { XX } }, 8329 }, 8330 8331 /* VEX_LEN_3A60_P_2 */ 8332 { 8333 { "vpcmpestrm", { XM, EXx, Ib } }, 8334 { "(bad)", { XX } }, 8335 }, 8336 8337 /* VEX_LEN_3A61_P_2 */ 8338 { 8339 { "vpcmpestri", { XM, EXx, Ib } }, 8340 { "(bad)", { XX } }, 8341 }, 8342 8343 /* VEX_LEN_3A62_P_2 */ 8344 { 8345 { "vpcmpistrm", { XM, EXx, Ib } }, 8346 { "(bad)", { XX } }, 8347 }, 8348 8349 /* VEX_LEN_3A63_P_2 */ 8350 { 8351 { "vpcmpistri", { XM, EXx, Ib } }, 8352 { "(bad)", { XX } }, 8353 }, 8354 8355 /* VEX_LEN_3A6A_P_2 */ 8356 { 8357 { "vfmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, 8358 { "(bad)", { XX } }, 8359 }, 8360 8361 /* VEX_LEN_3A6B_P_2 */ 8362 { 8363 { "vfmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, 8364 { "(bad)", { XX } }, 8365 }, 8366 8367 /* VEX_LEN_3A6E_P_2 */ 8368 { 8369 { "vfmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, 8370 { "(bad)", { XX } }, 8371 }, 8372 8373 /* VEX_LEN_3A6F_P_2 */ 8374 { 8375 { "vfmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, 8376 { "(bad)", { XX } }, 8377 }, 8378 8379 /* VEX_LEN_3A7A_P_2 */ 8380 { 8381 { "vfnmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, 8382 { "(bad)", { XX } }, 8383 }, 8384 8385 /* VEX_LEN_3A7B_P_2 */ 8386 { 8387 { "vfnmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, 8388 { "(bad)", { XX } }, 8389 }, 8390 8391 /* VEX_LEN_3A7E_P_2 */ 8392 { 8393 { "vfnmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } }, 8394 { "(bad)", { XX } }, 8395 }, 8396 8397 /* VEX_LEN_3A7F_P_2 */ 8398 { 8399 { "vfnmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } }, 8400 { "(bad)", { XX } }, 8401 }, 8402 8403 /* VEX_LEN_3ADF_P_2 */ 8404 { 8405 { "vaeskeygenassist", { XM, EXx, Ib } }, 8406 { "(bad)", { XX } }, 8407 }, 8408 }; 8409 8410 static const struct dis386 mod_table[][2] = { 8411 { 8412 /* MOD_8D */ 8413 { "leaS", { Gv, M } }, 8414 { "(bad)", { XX } }, 8415 }, 8416 { 8417 /* MOD_0F01_REG_0 */ 8418 { X86_64_TABLE (X86_64_0F01_REG_0) }, 8419 { RM_TABLE (RM_0F01_REG_0) }, 8420 }, 8421 { 8422 /* MOD_0F01_REG_1 */ 8423 { X86_64_TABLE (X86_64_0F01_REG_1) }, 8424 { RM_TABLE (RM_0F01_REG_1) }, 8425 }, 8426 { 8427 /* MOD_0F01_REG_2 */ 8428 { X86_64_TABLE (X86_64_0F01_REG_2) }, 8429 { RM_TABLE (RM_0F01_REG_2) }, 8430 }, 8431 { 8432 /* MOD_0F01_REG_3 */ 8433 { X86_64_TABLE (X86_64_0F01_REG_3) }, 8434 { RM_TABLE (RM_0F01_REG_3) }, 8435 }, 8436 { 8437 /* MOD_0F01_REG_7 */ 8438 { "invlpg", { Mb } }, 8439 { RM_TABLE (RM_0F01_REG_7) }, 8440 }, 8441 { 8442 /* MOD_0F12_PREFIX_0 */ 8443 { "movlps", { XM, EXq } }, 8444 { "movhlps", { XM, EXq } }, 8445 }, 8446 { 8447 /* MOD_0F13 */ 8448 { "movlpX", { EXq, XM } }, 8449 { "(bad)", { XX } }, 8450 }, 8451 { 8452 /* MOD_0F16_PREFIX_0 */ 8453 { "movhps", { XM, EXq } }, 8454 { "movlhps", { XM, EXq } }, 8455 }, 8456 { 8457 /* MOD_0F17 */ 8458 { "movhpX", { EXq, XM } }, 8459 { "(bad)", { XX } }, 8460 }, 8461 { 8462 /* MOD_0F18_REG_0 */ 8463 { "prefetchnta", { Mb } }, 8464 { "(bad)", { XX } }, 8465 }, 8466 { 8467 /* MOD_0F18_REG_1 */ 8468 { "prefetcht0", { Mb } }, 8469 { "(bad)", { XX } }, 8470 }, 8471 { 8472 /* MOD_0F18_REG_2 */ 8473 { "prefetcht1", { Mb } }, 8474 { "(bad)", { XX } }, 8475 }, 8476 { 8477 /* MOD_0F18_REG_3 */ 8478 { "prefetcht2", { Mb } }, 8479 { "(bad)", { XX } }, 8480 }, 8481 { 8482 /* MOD_0F20 */ 8483 { "(bad)", { XX } }, 8484 { "movZ", { Rm, Cm } }, 8485 }, 8486 { 8487 /* MOD_0F21 */ 8488 { "(bad)", { XX } }, 8489 { "movZ", { Rm, Dm } }, 8490 }, 8491 { 8492 /* MOD_0F22 */ 8493 { "(bad)", { XX } }, 8494 { "movZ", { Cm, Rm } }, 8495 }, 8496 { 8497 /* MOD_0F23 */ 8498 { "(bad)", { XX } }, 8499 { "movZ", { Dm, Rm } }, 8500 }, 8501 { 8502 /* MOD_0F24 */ 8503 { "(bad)", { XX } }, 8504 { "movL", { Rd, Td } }, 8505 }, 8506 { 8507 /* MOD_0F26 */ 8508 { "(bad)", { XX } }, 8509 { "movL", { Td, Rd } }, 8510 }, 8511 { 8512 /* MOD_0F2B_PREFIX_0 */ 8513 {"movntps", { Mx, XM } }, 8514 { "(bad)", { XX } }, 8515 }, 8516 { 8517 /* MOD_0F2B_PREFIX_1 */ 8518 {"movntss", { Md, XM } }, 8519 { "(bad)", { XX } }, 8520 }, 8521 { 8522 /* MOD_0F2B_PREFIX_2 */ 8523 {"movntpd", { Mx, XM } }, 8524 { "(bad)", { XX } }, 8525 }, 8526 { 8527 /* MOD_0F2B_PREFIX_3 */ 8528 {"movntsd", { Mq, XM } }, 8529 { "(bad)", { XX } }, 8530 }, 8531 { 8532 /* MOD_0F51 */ 8533 { "(bad)", { XX } }, 8534 { "movmskpX", { Gdq, XS } }, 8535 }, 8536 { 8537 /* MOD_0F71_REG_2 */ 8538 { "(bad)", { XX } }, 8539 { "psrlw", { MS, Ib } }, 8540 }, 8541 { 8542 /* MOD_0F71_REG_4 */ 8543 { "(bad)", { XX } }, 8544 { "psraw", { MS, Ib } }, 8545 }, 8546 { 8547 /* MOD_0F71_REG_6 */ 8548 { "(bad)", { XX } }, 8549 { "psllw", { MS, Ib } }, 8550 }, 8551 { 8552 /* MOD_0F72_REG_2 */ 8553 { "(bad)", { XX } }, 8554 { "psrld", { MS, Ib } }, 8555 }, 8556 { 8557 /* MOD_0F72_REG_4 */ 8558 { "(bad)", { XX } }, 8559 { "psrad", { MS, Ib } }, 8560 }, 8561 { 8562 /* MOD_0F72_REG_6 */ 8563 { "(bad)", { XX } }, 8564 { "pslld", { MS, Ib } }, 8565 }, 8566 { 8567 /* MOD_0F73_REG_2 */ 8568 { "(bad)", { XX } }, 8569 { "psrlq", { MS, Ib } }, 8570 }, 8571 { 8572 /* MOD_0F73_REG_3 */ 8573 { "(bad)", { XX } }, 8574 { PREFIX_TABLE (PREFIX_0F73_REG_3) }, 8575 }, 8576 { 8577 /* MOD_0F73_REG_6 */ 8578 { "(bad)", { XX } }, 8579 { "psllq", { MS, Ib } }, 8580 }, 8581 { 8582 /* MOD_0F73_REG_7 */ 8583 { "(bad)", { XX } }, 8584 { PREFIX_TABLE (PREFIX_0F73_REG_7) }, 8585 }, 8586 { 8587 /* MOD_0FAE_REG_0 */ 8588 { "fxsave", { M } }, 8589 { "(bad)", { XX } }, 8590 }, 8591 { 8592 /* MOD_0FAE_REG_1 */ 8593 { "fxrstor", { M } }, 8594 { "(bad)", { XX } }, 8595 }, 8596 { 8597 /* MOD_0FAE_REG_2 */ 8598 { "ldmxcsr", { Md } }, 8599 { "(bad)", { XX } }, 8600 }, 8601 { 8602 /* MOD_0FAE_REG_3 */ 8603 { "stmxcsr", { Md } }, 8604 { "(bad)", { XX } }, 8605 }, 8606 { 8607 /* MOD_0FAE_REG_4 */ 8608 { "xsave", { M } }, 8609 { "(bad)", { XX } }, 8610 }, 8611 { 8612 /* MOD_0FAE_REG_5 */ 8613 { "xrstor", { M } }, 8614 { RM_TABLE (RM_0FAE_REG_5) }, 8615 }, 8616 { 8617 /* MOD_0FAE_REG_6 */ 8618 { "xsaveopt", { M } }, 8619 { RM_TABLE (RM_0FAE_REG_6) }, 8620 }, 8621 { 8622 /* MOD_0FAE_REG_7 */ 8623 { "clflush", { Mb } }, 8624 { RM_TABLE (RM_0FAE_REG_7) }, 8625 }, 8626 { 8627 /* MOD_0FB2 */ 8628 { "lssS", { Gv, Mp } }, 8629 { "(bad)", { XX } }, 8630 }, 8631 { 8632 /* MOD_0FB4 */ 8633 { "lfsS", { Gv, Mp } }, 8634 { "(bad)", { XX } }, 8635 }, 8636 { 8637 /* MOD_0FB5 */ 8638 { "lgsS", { Gv, Mp } }, 8639 { "(bad)", { XX } }, 8640 }, 8641 { 8642 /* MOD_0FC7_REG_6 */ 8643 { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, 8644 { "(bad)", { XX } }, 8645 }, 8646 { 8647 /* MOD_0FC7_REG_7 */ 8648 { "vmptrst", { Mq } }, 8649 { "(bad)", { XX } }, 8650 }, 8651 { 8652 /* MOD_0FD7 */ 8653 { "(bad)", { XX } }, 8654 { "pmovmskb", { Gdq, MS } }, 8655 }, 8656 { 8657 /* MOD_0FE7_PREFIX_2 */ 8658 { "movntdq", { Mx, XM } }, 8659 { "(bad)", { XX } }, 8660 }, 8661 { 8662 /* MOD_0FF0_PREFIX_3 */ 8663 { "lddqu", { XM, M } }, 8664 { "(bad)", { XX } }, 8665 }, 8666 { 8667 /* MOD_0F382A_PREFIX_2 */ 8668 { "movntdqa", { XM, Mx } }, 8669 { "(bad)", { XX } }, 8670 }, 8671 { 8672 /* MOD_62_32BIT */ 8673 { "bound{S|}", { Gv, Ma } }, 8674 { "(bad)", { XX } }, 8675 }, 8676 { 8677 /* MOD_C4_32BIT */ 8678 { "lesS", { Gv, Mp } }, 8679 { VEX_C4_TABLE (VEX_0F) }, 8680 }, 8681 { 8682 /* MOD_C5_32BIT */ 8683 { "ldsS", { Gv, Mp } }, 8684 { VEX_C5_TABLE (VEX_0F) }, 8685 }, 8686 { 8687 /* MOD_VEX_12_PREFIX_0 */ 8688 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) }, 8689 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) }, 8690 }, 8691 { 8692 /* MOD_VEX_13 */ 8693 { VEX_LEN_TABLE (VEX_LEN_13_M_0) }, 8694 { "(bad)", { XX } }, 8695 }, 8696 { 8697 /* MOD_VEX_16_PREFIX_0 */ 8698 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) }, 8699 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) }, 8700 }, 8701 { 8702 /* MOD_VEX_17 */ 8703 { VEX_LEN_TABLE (VEX_LEN_17_M_0) }, 8704 { "(bad)", { XX } }, 8705 }, 8706 { 8707 /* MOD_VEX_2B */ 8708 { "vmovntpX", { Mx, XM } }, 8709 { "(bad)", { XX } }, 8710 }, 8711 { 8712 /* MOD_VEX_51 */ 8713 { "(bad)", { XX } }, 8714 { "vmovmskpX", { Gdq, XS } }, 8715 }, 8716 { 8717 /* MOD_VEX_71_REG_2 */ 8718 { "(bad)", { XX } }, 8719 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) }, 8720 }, 8721 { 8722 /* MOD_VEX_71_REG_4 */ 8723 { "(bad)", { XX } }, 8724 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) }, 8725 }, 8726 { 8727 /* MOD_VEX_71_REG_6 */ 8728 { "(bad)", { XX } }, 8729 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) }, 8730 }, 8731 { 8732 /* MOD_VEX_72_REG_2 */ 8733 { "(bad)", { XX } }, 8734 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) }, 8735 }, 8736 { 8737 /* MOD_VEX_72_REG_4 */ 8738 { "(bad)", { XX } }, 8739 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) }, 8740 }, 8741 { 8742 /* MOD_VEX_72_REG_6 */ 8743 { "(bad)", { XX } }, 8744 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) }, 8745 }, 8746 { 8747 /* MOD_VEX_73_REG_2 */ 8748 { "(bad)", { XX } }, 8749 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) }, 8750 }, 8751 { 8752 /* MOD_VEX_73_REG_3 */ 8753 { "(bad)", { XX } }, 8754 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) }, 8755 }, 8756 { 8757 /* MOD_VEX_73_REG_6 */ 8758 { "(bad)", { XX } }, 8759 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) }, 8760 }, 8761 { 8762 /* MOD_VEX_73_REG_7 */ 8763 { "(bad)", { XX } }, 8764 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) }, 8765 }, 8766 { 8767 /* MOD_VEX_AE_REG_2 */ 8768 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) }, 8769 { "(bad)", { XX } }, 8770 }, 8771 { 8772 /* MOD_VEX_AE_REG_3 */ 8773 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) }, 8774 { "(bad)", { XX } }, 8775 }, 8776 { 8777 /* MOD_VEX_D7_PREFIX_2 */ 8778 { "(bad)", { XX } }, 8779 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) }, 8780 }, 8781 { 8782 /* MOD_VEX_E7_PREFIX_2 */ 8783 { "vmovntdq", { Mx, XM } }, 8784 { "(bad)", { XX } }, 8785 }, 8786 { 8787 /* MOD_VEX_F0_PREFIX_3 */ 8788 { "vlddqu", { XM, M } }, 8789 { "(bad)", { XX } }, 8790 }, 8791 { 8792 /* MOD_VEX_3818_PREFIX_2 */ 8793 { "vbroadcastss", { XM, Md } }, 8794 { "(bad)", { XX } }, 8795 }, 8796 { 8797 /* MOD_VEX_3819_PREFIX_2 */ 8798 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) }, 8799 { "(bad)", { XX } }, 8800 }, 8801 { 8802 /* MOD_VEX_381A_PREFIX_2 */ 8803 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) }, 8804 { "(bad)", { XX } }, 8805 }, 8806 { 8807 /* MOD_VEX_382A_PREFIX_2 */ 8808 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) }, 8809 { "(bad)", { XX } }, 8810 }, 8811 { 8812 /* MOD_VEX_382C_PREFIX_2 */ 8813 { "vmaskmovps", { XM, Vex, Mx } }, 8814 { "(bad)", { XX } }, 8815 }, 8816 { 8817 /* MOD_VEX_382D_PREFIX_2 */ 8818 { "vmaskmovpd", { XM, Vex, Mx } }, 8819 { "(bad)", { XX } }, 8820 }, 8821 { 8822 /* MOD_VEX_382E_PREFIX_2 */ 8823 { "vmaskmovps", { Mx, Vex, XM } }, 8824 { "(bad)", { XX } }, 8825 }, 8826 { 8827 /* MOD_VEX_382F_PREFIX_2 */ 8828 { "vmaskmovpd", { Mx, Vex, XM } }, 8829 { "(bad)", { XX } }, 8830 }, 8831 }; 8832 8833 static const struct dis386 rm_table[][8] = { 8834 { 8835 /* RM_0F01_REG_0 */ 8836 { "(bad)", { XX } }, 8837 { "vmcall", { Skip_MODRM } }, 8838 { "vmlaunch", { Skip_MODRM } }, 8839 { "vmresume", { Skip_MODRM } }, 8840 { "vmxoff", { Skip_MODRM } }, 8841 { "(bad)", { XX } }, 8842 { "(bad)", { XX } }, 8843 { "(bad)", { XX } }, 8844 }, 8845 { 8846 /* RM_0F01_REG_1 */ 8847 { "monitor", { { OP_Monitor, 0 } } }, 8848 { "mwait", { { OP_Mwait, 0 } } }, 8849 { "(bad)", { XX } }, 8850 { "(bad)", { XX } }, 8851 { "(bad)", { XX } }, 8852 { "(bad)", { XX } }, 8853 { "(bad)", { XX } }, 8854 { "(bad)", { XX } }, 8855 }, 8856 { 8857 /* RM_0F01_REG_2 */ 8858 { "xgetbv", { Skip_MODRM } }, 8859 { "xsetbv", { Skip_MODRM } }, 8860 { "(bad)", { XX } }, 8861 { "(bad)", { XX } }, 8862 { "(bad)", { XX } }, 8863 { "(bad)", { XX } }, 8864 { "(bad)", { XX } }, 8865 { "(bad)", { XX } }, 8866 }, 8867 { 8868 /* RM_0F01_REG_3 */ 8869 { "vmrun", { Skip_MODRM } }, 8870 { "vmmcall", { Skip_MODRM } }, 8871 { "vmload", { Skip_MODRM } }, 8872 { "vmsave", { Skip_MODRM } }, 8873 { "stgi", { Skip_MODRM } }, 8874 { "clgi", { Skip_MODRM } }, 8875 { "skinit", { Skip_MODRM } }, 8876 { "invlpga", { Skip_MODRM } }, 8877 }, 8878 { 8879 /* RM_0F01_REG_7 */ 8880 { "swapgs", { Skip_MODRM } }, 8881 { "rdtscp", { Skip_MODRM } }, 8882 { "(bad)", { XX } }, 8883 { "(bad)", { XX } }, 8884 { "(bad)", { XX } }, 8885 { "(bad)", { XX } }, 8886 { "(bad)", { XX } }, 8887 { "(bad)", { XX } }, 8888 }, 8889 { 8890 /* RM_0FAE_REG_5 */ 8891 { "lfence", { Skip_MODRM } }, 8892 { "(bad)", { XX } }, 8893 { "(bad)", { XX } }, 8894 { "(bad)", { XX } }, 8895 { "(bad)", { XX } }, 8896 { "(bad)", { XX } }, 8897 { "(bad)", { XX } }, 8898 { "(bad)", { XX } }, 8899 }, 8900 { 8901 /* RM_0FAE_REG_6 */ 8902 { "mfence", { Skip_MODRM } }, 8903 { "(bad)", { XX } }, 8904 { "(bad)", { XX } }, 8905 { "(bad)", { XX } }, 8906 { "(bad)", { XX } }, 8907 { "(bad)", { XX } }, 8908 { "(bad)", { XX } }, 8909 { "(bad)", { XX } }, 8910 }, 8911 { 8912 /* RM_0FAE_REG_7 */ 8913 { "sfence", { Skip_MODRM } }, 8914 { "(bad)", { XX } }, 8915 { "(bad)", { XX } }, 8916 { "(bad)", { XX } }, 8917 { "(bad)", { XX } }, 8918 { "(bad)", { XX } }, 8919 { "(bad)", { XX } }, 8920 { "(bad)", { XX } }, 8921 }, 8922 }; 8923 8924 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") 8925 8926 static void 8927 ckprefix (void) 8928 { 8929 int newrex; 8930 rex = 0; 8931 rex_original = 0; 8932 rex_ignored = 0; 8933 prefixes = 0; 8934 used_prefixes = 0; 8935 rex_used = 0; 8936 while (1) 8937 { 8938 FETCH_DATA (the_info, codep + 1); 8939 newrex = 0; 8940 switch (*codep) 8941 { 8942 /* REX prefixes family. */ 8943 case 0x40: 8944 case 0x41: 8945 case 0x42: 8946 case 0x43: 8947 case 0x44: 8948 case 0x45: 8949 case 0x46: 8950 case 0x47: 8951 case 0x48: 8952 case 0x49: 8953 case 0x4a: 8954 case 0x4b: 8955 case 0x4c: 8956 case 0x4d: 8957 case 0x4e: 8958 case 0x4f: 8959 if (address_mode == mode_64bit) 8960 newrex = *codep; 8961 else 8962 return; 8963 break; 8964 case 0xf3: 8965 prefixes |= PREFIX_REPZ; 8966 break; 8967 case 0xf2: 8968 prefixes |= PREFIX_REPNZ; 8969 break; 8970 case 0xf0: 8971 prefixes |= PREFIX_LOCK; 8972 break; 8973 case 0x2e: 8974 prefixes |= PREFIX_CS; 8975 break; 8976 case 0x36: 8977 prefixes |= PREFIX_SS; 8978 break; 8979 case 0x3e: 8980 prefixes |= PREFIX_DS; 8981 break; 8982 case 0x26: 8983 prefixes |= PREFIX_ES; 8984 break; 8985 case 0x64: 8986 prefixes |= PREFIX_FS; 8987 break; 8988 case 0x65: 8989 prefixes |= PREFIX_GS; 8990 break; 8991 case 0x66: 8992 prefixes |= PREFIX_DATA; 8993 break; 8994 case 0x67: 8995 prefixes |= PREFIX_ADDR; 8996 break; 8997 case FWAIT_OPCODE: 8998 /* fwait is really an instruction. If there are prefixes 8999 before the fwait, they belong to the fwait, *not* to the 9000 following instruction. */ 9001 if (prefixes || rex) 9002 { 9003 prefixes |= PREFIX_FWAIT; 9004 codep++; 9005 return; 9006 } 9007 prefixes = PREFIX_FWAIT; 9008 break; 9009 default: 9010 return; 9011 } 9012 /* Rex is ignored when followed by another prefix. */ 9013 if (rex) 9014 { 9015 rex_used = rex; 9016 return; 9017 } 9018 rex = newrex; 9019 rex_original = rex; 9020 codep++; 9021 } 9022 } 9023 9024 /* Return the name of the prefix byte PREF, or NULL if PREF is not a 9025 prefix byte. */ 9026 9027 static const char * 9028 prefix_name (int pref, int sizeflag) 9029 { 9030 static const char *rexes [16] = 9031 { 9032 "rex", /* 0x40 */ 9033 "rex.B", /* 0x41 */ 9034 "rex.X", /* 0x42 */ 9035 "rex.XB", /* 0x43 */ 9036 "rex.R", /* 0x44 */ 9037 "rex.RB", /* 0x45 */ 9038 "rex.RX", /* 0x46 */ 9039 "rex.RXB", /* 0x47 */ 9040 "rex.W", /* 0x48 */ 9041 "rex.WB", /* 0x49 */ 9042 "rex.WX", /* 0x4a */ 9043 "rex.WXB", /* 0x4b */ 9044 "rex.WR", /* 0x4c */ 9045 "rex.WRB", /* 0x4d */ 9046 "rex.WRX", /* 0x4e */ 9047 "rex.WRXB", /* 0x4f */ 9048 }; 9049 9050 switch (pref) 9051 { 9052 /* REX prefixes family. */ 9053 case 0x40: 9054 case 0x41: 9055 case 0x42: 9056 case 0x43: 9057 case 0x44: 9058 case 0x45: 9059 case 0x46: 9060 case 0x47: 9061 case 0x48: 9062 case 0x49: 9063 case 0x4a: 9064 case 0x4b: 9065 case 0x4c: 9066 case 0x4d: 9067 case 0x4e: 9068 case 0x4f: 9069 return rexes [pref - 0x40]; 9070 case 0xf3: 9071 return "repz"; 9072 case 0xf2: 9073 return "repnz"; 9074 case 0xf0: 9075 return "lock"; 9076 case 0x2e: 9077 return "cs"; 9078 case 0x36: 9079 return "ss"; 9080 case 0x3e: 9081 return "ds"; 9082 case 0x26: 9083 return "es"; 9084 case 0x64: 9085 return "fs"; 9086 case 0x65: 9087 return "gs"; 9088 case 0x66: 9089 return (sizeflag & DFLAG) ? "data16" : "data32"; 9090 case 0x67: 9091 if (address_mode == mode_64bit) 9092 return (sizeflag & AFLAG) ? "addr32" : "addr64"; 9093 else 9094 return (sizeflag & AFLAG) ? "addr16" : "addr32"; 9095 case FWAIT_OPCODE: 9096 return "fwait"; 9097 default: 9098 return NULL; 9099 } 9100 } 9101 9102 static char op_out[MAX_OPERANDS][100]; 9103 static int op_ad, op_index[MAX_OPERANDS]; 9104 static int two_source_ops; 9105 static bfd_vma op_address[MAX_OPERANDS]; 9106 static bfd_vma op_riprel[MAX_OPERANDS]; 9107 static bfd_vma start_pc; 9108 9109 /* 9110 * On the 386's of 1988, the maximum length of an instruction is 15 bytes. 9111 * (see topic "Redundant prefixes" in the "Differences from 8086" 9112 * section of the "Virtual 8086 Mode" chapter.) 9113 * 'pc' should be the address of this instruction, it will 9114 * be used to print the target address if this is a relative jump or call 9115 * The function returns the length of this instruction in bytes. 9116 */ 9117 9118 static char intel_syntax; 9119 static char intel_mnemonic = !SYSV386_COMPAT; 9120 static char open_char; 9121 static char close_char; 9122 static char separator_char; 9123 static char scale_char; 9124 9125 /* Here for backwards compatibility. When gdb stops using 9126 print_insn_i386_att and print_insn_i386_intel these functions can 9127 disappear, and print_insn_i386 be merged into print_insn. */ 9128 int 9129 print_insn_i386_att (bfd_vma pc, disassemble_info *info) 9130 { 9131 intel_syntax = 0; 9132 9133 return print_insn (pc, info); 9134 } 9135 9136 int 9137 print_insn_i386_intel (bfd_vma pc, disassemble_info *info) 9138 { 9139 intel_syntax = 1; 9140 9141 return print_insn (pc, info); 9142 } 9143 9144 int 9145 print_insn_i386 (bfd_vma pc, disassemble_info *info) 9146 { 9147 intel_syntax = -1; 9148 9149 return print_insn (pc, info); 9150 } 9151 9152 void 9153 print_i386_disassembler_options (FILE *stream) 9154 { 9155 fprintf (stream, _("\n\ 9156 The following i386/x86-64 specific disassembler options are supported for use\n\ 9157 with the -M switch (multiple options should be separated by commas):\n")); 9158 9159 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); 9160 fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); 9161 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); 9162 fprintf (stream, _(" att Display instruction in AT&T syntax\n")); 9163 fprintf (stream, _(" intel Display instruction in Intel syntax\n")); 9164 fprintf (stream, _(" att-mnemonic\n" 9165 " Display instruction in AT&T mnemonic\n")); 9166 fprintf (stream, _(" intel-mnemonic\n" 9167 " Display instruction in Intel mnemonic\n")); 9168 fprintf (stream, _(" addr64 Assume 64bit address size\n")); 9169 fprintf (stream, _(" addr32 Assume 32bit address size\n")); 9170 fprintf (stream, _(" addr16 Assume 16bit address size\n")); 9171 fprintf (stream, _(" data32 Assume 32bit data size\n")); 9172 fprintf (stream, _(" data16 Assume 16bit data size\n")); 9173 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); 9174 } 9175 9176 /* Get a pointer to struct dis386 with a valid name. */ 9177 9178 static const struct dis386 * 9179 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) 9180 { 9181 int index, vex_table_index; 9182 9183 if (dp->name != NULL) 9184 return dp; 9185 9186 switch (dp->op[0].bytemode) 9187 { 9188 case USE_REG_TABLE: 9189 dp = ®_table[dp->op[1].bytemode][modrm.reg]; 9190 break; 9191 9192 case USE_MOD_TABLE: 9193 index = modrm.mod == 0x3 ? 1 : 0; 9194 dp = &mod_table[dp->op[1].bytemode][index]; 9195 break; 9196 9197 case USE_RM_TABLE: 9198 dp = &rm_table[dp->op[1].bytemode][modrm.rm]; 9199 break; 9200 9201 case USE_PREFIX_TABLE: 9202 if (need_vex) 9203 { 9204 /* The prefix in VEX is implicit. */ 9205 switch (vex.prefix) 9206 { 9207 case 0: 9208 index = 0; 9209 break; 9210 case REPE_PREFIX_OPCODE: 9211 index = 1; 9212 break; 9213 case DATA_PREFIX_OPCODE: 9214 index = 2; 9215 break; 9216 case REPNE_PREFIX_OPCODE: 9217 index = 3; 9218 break; 9219 default: 9220 abort (); 9221 break; 9222 } 9223 } 9224 else 9225 { 9226 index = 0; 9227 used_prefixes |= (prefixes & PREFIX_REPZ); 9228 if (prefixes & PREFIX_REPZ) 9229 { 9230 index = 1; 9231 repz_prefix = NULL; 9232 } 9233 else 9234 { 9235 /* We should check PREFIX_REPNZ and PREFIX_REPZ before 9236 PREFIX_DATA. */ 9237 used_prefixes |= (prefixes & PREFIX_REPNZ); 9238 if (prefixes & PREFIX_REPNZ) 9239 { 9240 index = 3; 9241 repnz_prefix = NULL; 9242 } 9243 else 9244 { 9245 used_prefixes |= (prefixes & PREFIX_DATA); 9246 if (prefixes & PREFIX_DATA) 9247 { 9248 index = 2; 9249 data_prefix = NULL; 9250 } 9251 } 9252 } 9253 } 9254 dp = &prefix_table[dp->op[1].bytemode][index]; 9255 break; 9256 9257 case USE_X86_64_TABLE: 9258 index = address_mode == mode_64bit ? 1 : 0; 9259 dp = &x86_64_table[dp->op[1].bytemode][index]; 9260 break; 9261 9262 case USE_3BYTE_TABLE: 9263 FETCH_DATA (info, codep + 2); 9264 index = *codep++; 9265 dp = &three_byte_table[dp->op[1].bytemode][index]; 9266 modrm.mod = (*codep >> 6) & 3; 9267 modrm.reg = (*codep >> 3) & 7; 9268 modrm.rm = *codep & 7; 9269 break; 9270 9271 case USE_VEX_LEN_TABLE: 9272 if (!need_vex) 9273 abort (); 9274 9275 switch (vex.length) 9276 { 9277 case 128: 9278 index = 0; 9279 break; 9280 case 256: 9281 index = 1; 9282 break; 9283 default: 9284 abort (); 9285 break; 9286 } 9287 9288 dp = &vex_len_table[dp->op[1].bytemode][index]; 9289 break; 9290 9291 case USE_VEX_C4_TABLE: 9292 FETCH_DATA (info, codep + 3); 9293 /* All bits in the REX prefix are ignored. */ 9294 rex_ignored = rex; 9295 rex = ~(*codep >> 5) & 0x7; 9296 switch ((*codep & 0x1f)) 9297 { 9298 default: 9299 BadOp (); 9300 case 0x1: 9301 vex_table_index = 0; 9302 break; 9303 case 0x2: 9304 vex_table_index = 1; 9305 break; 9306 case 0x3: 9307 vex_table_index = 2; 9308 break; 9309 } 9310 codep++; 9311 vex.w = *codep & 0x80; 9312 if (vex.w && address_mode == mode_64bit) 9313 rex |= REX_W; 9314 9315 vex.register_specifier = (~(*codep >> 3)) & 0xf; 9316 if (address_mode != mode_64bit 9317 && vex.register_specifier > 0x7) 9318 BadOp (); 9319 9320 vex.length = (*codep & 0x4) ? 256 : 128; 9321 switch ((*codep & 0x3)) 9322 { 9323 case 0: 9324 vex.prefix = 0; 9325 break; 9326 case 1: 9327 vex.prefix = DATA_PREFIX_OPCODE; 9328 break; 9329 case 2: 9330 vex.prefix = REPE_PREFIX_OPCODE; 9331 break; 9332 case 3: 9333 vex.prefix = REPNE_PREFIX_OPCODE; 9334 break; 9335 } 9336 need_vex = 1; 9337 need_vex_reg = 1; 9338 codep++; 9339 index = *codep++; 9340 dp = &vex_table[vex_table_index][index]; 9341 /* There is no MODRM byte for VEX [82|77]. */ 9342 if (index != 0x77 && index != 0x82) 9343 { 9344 FETCH_DATA (info, codep + 1); 9345 modrm.mod = (*codep >> 6) & 3; 9346 modrm.reg = (*codep >> 3) & 7; 9347 modrm.rm = *codep & 7; 9348 } 9349 break; 9350 9351 case USE_VEX_C5_TABLE: 9352 FETCH_DATA (info, codep + 2); 9353 /* All bits in the REX prefix are ignored. */ 9354 rex_ignored = rex; 9355 rex = (*codep & 0x80) ? 0 : REX_R; 9356 9357 vex.register_specifier = (~(*codep >> 3)) & 0xf; 9358 if (address_mode != mode_64bit 9359 && vex.register_specifier > 0x7) 9360 BadOp (); 9361 9362 vex.length = (*codep & 0x4) ? 256 : 128; 9363 switch ((*codep & 0x3)) 9364 { 9365 case 0: 9366 vex.prefix = 0; 9367 break; 9368 case 1: 9369 vex.prefix = DATA_PREFIX_OPCODE; 9370 break; 9371 case 2: 9372 vex.prefix = REPE_PREFIX_OPCODE; 9373 break; 9374 case 3: 9375 vex.prefix = REPNE_PREFIX_OPCODE; 9376 break; 9377 } 9378 need_vex = 1; 9379 need_vex_reg = 1; 9380 codep++; 9381 index = *codep++; 9382 dp = &vex_table[dp->op[1].bytemode][index]; 9383 /* There is no MODRM byte for VEX [82|77]. */ 9384 if (index != 0x77 && index != 0x82) 9385 { 9386 FETCH_DATA (info, codep + 1); 9387 modrm.mod = (*codep >> 6) & 3; 9388 modrm.reg = (*codep >> 3) & 7; 9389 modrm.rm = *codep & 7; 9390 } 9391 break; 9392 9393 default: 9394 abort (); 9395 } 9396 9397 if (dp->name != NULL) 9398 return dp; 9399 else 9400 return get_valid_dis386 (dp, info); 9401 } 9402 9403 static int 9404 print_insn (bfd_vma pc, disassemble_info *info) 9405 { 9406 const struct dis386 *dp; 9407 int i; 9408 char *op_txt[MAX_OPERANDS]; 9409 int needcomma; 9410 int sizeflag; 9411 const char *p; 9412 struct dis_private priv; 9413 unsigned char op; 9414 char prefix_obuf[32]; 9415 char *prefix_obufp; 9416 9417 if (info->mach == bfd_mach_x86_64_intel_syntax 9418 || info->mach == bfd_mach_x86_64 9419 || info->mach == bfd_mach_l1om 9420 || info->mach == bfd_mach_l1om_intel_syntax) 9421 address_mode = mode_64bit; 9422 else 9423 address_mode = mode_32bit; 9424 9425 if (intel_syntax == (char) -1) 9426 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax 9427 || info->mach == bfd_mach_x86_64_intel_syntax 9428 || info->mach == bfd_mach_l1om_intel_syntax); 9429 9430 if (info->mach == bfd_mach_i386_i386 9431 || info->mach == bfd_mach_x86_64 9432 || info->mach == bfd_mach_l1om 9433 || info->mach == bfd_mach_i386_i386_intel_syntax 9434 || info->mach == bfd_mach_x86_64_intel_syntax 9435 || info->mach == bfd_mach_l1om_intel_syntax) 9436 priv.orig_sizeflag = AFLAG | DFLAG; 9437 else if (info->mach == bfd_mach_i386_i8086) 9438 priv.orig_sizeflag = 0; 9439 else 9440 abort (); 9441 9442 for (p = info->disassembler_options; p != NULL; ) 9443 { 9444 if (CONST_STRNEQ (p, "x86-64")) 9445 { 9446 address_mode = mode_64bit; 9447 priv.orig_sizeflag = AFLAG | DFLAG; 9448 } 9449 else if (CONST_STRNEQ (p, "i386")) 9450 { 9451 address_mode = mode_32bit; 9452 priv.orig_sizeflag = AFLAG | DFLAG; 9453 } 9454 else if (CONST_STRNEQ (p, "i8086")) 9455 { 9456 address_mode = mode_16bit; 9457 priv.orig_sizeflag = 0; 9458 } 9459 else if (CONST_STRNEQ (p, "intel")) 9460 { 9461 intel_syntax = 1; 9462 if (CONST_STRNEQ (p + 5, "-mnemonic")) 9463 intel_mnemonic = 1; 9464 } 9465 else if (CONST_STRNEQ (p, "att")) 9466 { 9467 intel_syntax = 0; 9468 if (CONST_STRNEQ (p + 3, "-mnemonic")) 9469 intel_mnemonic = 0; 9470 } 9471 else if (CONST_STRNEQ (p, "addr")) 9472 { 9473 if (address_mode == mode_64bit) 9474 { 9475 if (p[4] == '3' && p[5] == '2') 9476 priv.orig_sizeflag &= ~AFLAG; 9477 else if (p[4] == '6' && p[5] == '4') 9478 priv.orig_sizeflag |= AFLAG; 9479 } 9480 else 9481 { 9482 if (p[4] == '1' && p[5] == '6') 9483 priv.orig_sizeflag &= ~AFLAG; 9484 else if (p[4] == '3' && p[5] == '2') 9485 priv.orig_sizeflag |= AFLAG; 9486 } 9487 } 9488 else if (CONST_STRNEQ (p, "data")) 9489 { 9490 if (p[4] == '1' && p[5] == '6') 9491 priv.orig_sizeflag &= ~DFLAG; 9492 else if (p[4] == '3' && p[5] == '2') 9493 priv.orig_sizeflag |= DFLAG; 9494 } 9495 else if (CONST_STRNEQ (p, "suffix")) 9496 priv.orig_sizeflag |= SUFFIX_ALWAYS; 9497 9498 p = strchr (p, ','); 9499 if (p != NULL) 9500 p++; 9501 } 9502 9503 if (intel_syntax) 9504 { 9505 names64 = intel_names64; 9506 names32 = intel_names32; 9507 names16 = intel_names16; 9508 names8 = intel_names8; 9509 names8rex = intel_names8rex; 9510 names_seg = intel_names_seg; 9511 index64 = intel_index64; 9512 index32 = intel_index32; 9513 index16 = intel_index16; 9514 open_char = '['; 9515 close_char = ']'; 9516 separator_char = '+'; 9517 scale_char = '*'; 9518 } 9519 else 9520 { 9521 names64 = att_names64; 9522 names32 = att_names32; 9523 names16 = att_names16; 9524 names8 = att_names8; 9525 names8rex = att_names8rex; 9526 names_seg = att_names_seg; 9527 index64 = att_index64; 9528 index32 = att_index32; 9529 index16 = att_index16; 9530 open_char = '('; 9531 close_char = ')'; 9532 separator_char = ','; 9533 scale_char = ','; 9534 } 9535 9536 /* The output looks better if we put 7 bytes on a line, since that 9537 puts most long word instructions on a single line. Use 8 bytes 9538 for Intel L1OM. */ 9539 if (info->mach == bfd_mach_l1om 9540 || info->mach == bfd_mach_l1om_intel_syntax) 9541 info->bytes_per_line = 8; 9542 else 9543 info->bytes_per_line = 7; 9544 9545 info->private_data = &priv; 9546 priv.max_fetched = priv.the_buffer; 9547 priv.insn_start = pc; 9548 9549 obuf[0] = 0; 9550 for (i = 0; i < MAX_OPERANDS; ++i) 9551 { 9552 op_out[i][0] = 0; 9553 op_index[i] = -1; 9554 } 9555 9556 the_info = info; 9557 start_pc = pc; 9558 start_codep = priv.the_buffer; 9559 codep = priv.the_buffer; 9560 9561 if (setjmp (priv.bailout) != 0) 9562 { 9563 const char *name; 9564 9565 /* Getting here means we tried for data but didn't get it. That 9566 means we have an incomplete instruction of some sort. Just 9567 print the first byte as a prefix or a .byte pseudo-op. */ 9568 if (codep > priv.the_buffer) 9569 { 9570 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); 9571 if (name != NULL) 9572 (*info->fprintf_func) (info->stream, "%s", name); 9573 else 9574 { 9575 /* Just print the first byte as a .byte instruction. */ 9576 (*info->fprintf_func) (info->stream, ".byte 0x%x", 9577 (unsigned int) priv.the_buffer[0]); 9578 } 9579 9580 return 1; 9581 } 9582 9583 return -1; 9584 } 9585 9586 obufp = obuf; 9587 ckprefix (); 9588 9589 insn_codep = codep; 9590 sizeflag = priv.orig_sizeflag; 9591 9592 FETCH_DATA (info, codep + 1); 9593 two_source_ops = (*codep == 0x62) || (*codep == 0xc8); 9594 9595 if (((prefixes & PREFIX_FWAIT) 9596 && ((*codep < 0xd8) || (*codep > 0xdf))) 9597 || (rex && rex_used)) 9598 { 9599 const char *name; 9600 9601 /* fwait not followed by floating point instruction, or rex followed 9602 by other prefixes. Print the first prefix. */ 9603 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); 9604 if (name == NULL) 9605 name = INTERNAL_DISASSEMBLER_ERROR; 9606 (*info->fprintf_func) (info->stream, "%s", name); 9607 return 1; 9608 } 9609 9610 op = 0; 9611 9612 if (*codep == 0x0f) 9613 { 9614 unsigned char threebyte; 9615 FETCH_DATA (info, codep + 2); 9616 threebyte = *++codep; 9617 dp = &dis386_twobyte[threebyte]; 9618 need_modrm = twobyte_has_modrm[*codep]; 9619 codep++; 9620 } 9621 else 9622 { 9623 dp = &dis386[*codep]; 9624 need_modrm = onebyte_has_modrm[*codep]; 9625 codep++; 9626 } 9627 9628 if ((prefixes & PREFIX_REPZ)) 9629 { 9630 repz_prefix = "repz "; 9631 used_prefixes |= PREFIX_REPZ; 9632 } 9633 else 9634 repz_prefix = NULL; 9635 9636 if ((prefixes & PREFIX_REPNZ)) 9637 { 9638 repnz_prefix = "repnz "; 9639 used_prefixes |= PREFIX_REPNZ; 9640 } 9641 else 9642 repnz_prefix = NULL; 9643 9644 if ((prefixes & PREFIX_LOCK)) 9645 { 9646 lock_prefix = "lock "; 9647 used_prefixes |= PREFIX_LOCK; 9648 } 9649 else 9650 lock_prefix = NULL; 9651 9652 addr_prefix = NULL; 9653 if (prefixes & PREFIX_ADDR) 9654 { 9655 sizeflag ^= AFLAG; 9656 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) 9657 { 9658 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 9659 addr_prefix = "addr32 "; 9660 else 9661 addr_prefix = "addr16 "; 9662 used_prefixes |= PREFIX_ADDR; 9663 } 9664 } 9665 9666 data_prefix = NULL; 9667 if ((prefixes & PREFIX_DATA)) 9668 { 9669 sizeflag ^= DFLAG; 9670 if (dp->op[2].bytemode == cond_jump_mode 9671 && dp->op[0].bytemode == v_mode 9672 && !intel_syntax) 9673 { 9674 if (sizeflag & DFLAG) 9675 data_prefix = "data32 "; 9676 else 9677 data_prefix = "data16 "; 9678 used_prefixes |= PREFIX_DATA; 9679 } 9680 } 9681 9682 if (need_modrm) 9683 { 9684 FETCH_DATA (info, codep + 1); 9685 modrm.mod = (*codep >> 6) & 3; 9686 modrm.reg = (*codep >> 3) & 7; 9687 modrm.rm = *codep & 7; 9688 } 9689 9690 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) 9691 { 9692 dofloat (sizeflag); 9693 } 9694 else 9695 { 9696 need_vex = 0; 9697 need_vex_reg = 0; 9698 vex_w_done = 0; 9699 dp = get_valid_dis386 (dp, info); 9700 if (dp != NULL && putop (dp->name, sizeflag) == 0) 9701 { 9702 for (i = 0; i < MAX_OPERANDS; ++i) 9703 { 9704 obufp = op_out[i]; 9705 op_ad = MAX_OPERANDS - 1 - i; 9706 if (dp->op[i].rtn) 9707 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); 9708 } 9709 } 9710 } 9711 9712 /* See if any prefixes were not used. If so, print the first one 9713 separately. If we don't do this, we'll wind up printing an 9714 instruction stream which does not precisely correspond to the 9715 bytes we are disassembling. */ 9716 if ((prefixes & ~used_prefixes) != 0) 9717 { 9718 const char *name; 9719 9720 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); 9721 if (name == NULL) 9722 name = INTERNAL_DISASSEMBLER_ERROR; 9723 (*info->fprintf_func) (info->stream, "%s", name); 9724 return 1; 9725 } 9726 if ((rex_original & ~rex_used) || rex_ignored) 9727 { 9728 const char *name; 9729 name = prefix_name (rex_original, priv.orig_sizeflag); 9730 if (name == NULL) 9731 name = INTERNAL_DISASSEMBLER_ERROR; 9732 (*info->fprintf_func) (info->stream, "%s ", name); 9733 } 9734 9735 prefix_obuf[0] = 0; 9736 prefix_obufp = prefix_obuf; 9737 if (lock_prefix) 9738 prefix_obufp = stpcpy (prefix_obufp, lock_prefix); 9739 if (repz_prefix) 9740 prefix_obufp = stpcpy (prefix_obufp, repz_prefix); 9741 if (repnz_prefix) 9742 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix); 9743 if (addr_prefix) 9744 prefix_obufp = stpcpy (prefix_obufp, addr_prefix); 9745 if (data_prefix) 9746 prefix_obufp = stpcpy (prefix_obufp, data_prefix); 9747 9748 if (prefix_obuf[0] != 0) 9749 (*info->fprintf_func) (info->stream, "%s", prefix_obuf); 9750 9751 obufp = mnemonicendp; 9752 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++) 9753 oappend (" "); 9754 oappend (" "); 9755 (*info->fprintf_func) (info->stream, "%s", obuf); 9756 9757 /* The enter and bound instructions are printed with operands in the same 9758 order as the intel book; everything else is printed in reverse order. */ 9759 if (intel_syntax || two_source_ops) 9760 { 9761 bfd_vma riprel; 9762 9763 for (i = 0; i < MAX_OPERANDS; ++i) 9764 op_txt[i] = op_out[i]; 9765 9766 for (i = 0; i < (MAX_OPERANDS >> 1); ++i) 9767 { 9768 op_ad = op_index[i]; 9769 op_index[i] = op_index[MAX_OPERANDS - 1 - i]; 9770 op_index[MAX_OPERANDS - 1 - i] = op_ad; 9771 riprel = op_riprel[i]; 9772 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; 9773 op_riprel[MAX_OPERANDS - 1 - i] = riprel; 9774 } 9775 } 9776 else 9777 { 9778 for (i = 0; i < MAX_OPERANDS; ++i) 9779 op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; 9780 } 9781 9782 needcomma = 0; 9783 for (i = 0; i < MAX_OPERANDS; ++i) 9784 if (*op_txt[i]) 9785 { 9786 if (needcomma) 9787 (*info->fprintf_func) (info->stream, ","); 9788 if (op_index[i] != -1 && !op_riprel[i]) 9789 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); 9790 else 9791 (*info->fprintf_func) (info->stream, "%s", op_txt[i]); 9792 needcomma = 1; 9793 } 9794 9795 for (i = 0; i < MAX_OPERANDS; i++) 9796 if (op_index[i] != -1 && op_riprel[i]) 9797 { 9798 (*info->fprintf_func) (info->stream, " # "); 9799 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep 9800 + op_address[op_index[i]]), info); 9801 break; 9802 } 9803 return codep - priv.the_buffer; 9804 } 9805 9806 static const char *float_mem[] = { 9807 /* d8 */ 9808 "fadd{s|}", 9809 "fmul{s|}", 9810 "fcom{s|}", 9811 "fcomp{s|}", 9812 "fsub{s|}", 9813 "fsubr{s|}", 9814 "fdiv{s|}", 9815 "fdivr{s|}", 9816 /* d9 */ 9817 "fld{s|}", 9818 "(bad)", 9819 "fst{s|}", 9820 "fstp{s|}", 9821 "fldenvIC", 9822 "fldcw", 9823 "fNstenvIC", 9824 "fNstcw", 9825 /* da */ 9826 "fiadd{l|}", 9827 "fimul{l|}", 9828 "ficom{l|}", 9829 "ficomp{l|}", 9830 "fisub{l|}", 9831 "fisubr{l|}", 9832 "fidiv{l|}", 9833 "fidivr{l|}", 9834 /* db */ 9835 "fild{l|}", 9836 "fisttp{l|}", 9837 "fist{l|}", 9838 "fistp{l|}", 9839 "(bad)", 9840 "fld{t||t|}", 9841 "(bad)", 9842 "fstp{t||t|}", 9843 /* dc */ 9844 "fadd{l|}", 9845 "fmul{l|}", 9846 "fcom{l|}", 9847 "fcomp{l|}", 9848 "fsub{l|}", 9849 "fsubr{l|}", 9850 "fdiv{l|}", 9851 "fdivr{l|}", 9852 /* dd */ 9853 "fld{l|}", 9854 "fisttp{ll|}", 9855 "fst{l||}", 9856 "fstp{l|}", 9857 "frstorIC", 9858 "(bad)", 9859 "fNsaveIC", 9860 "fNstsw", 9861 /* de */ 9862 "fiadd", 9863 "fimul", 9864 "ficom", 9865 "ficomp", 9866 "fisub", 9867 "fisubr", 9868 "fidiv", 9869 "fidivr", 9870 /* df */ 9871 "fild", 9872 "fisttp", 9873 "fist", 9874 "fistp", 9875 "fbld", 9876 "fild{ll|}", 9877 "fbstp", 9878 "fistp{ll|}", 9879 }; 9880 9881 static const unsigned char float_mem_mode[] = { 9882 /* d8 */ 9883 d_mode, 9884 d_mode, 9885 d_mode, 9886 d_mode, 9887 d_mode, 9888 d_mode, 9889 d_mode, 9890 d_mode, 9891 /* d9 */ 9892 d_mode, 9893 0, 9894 d_mode, 9895 d_mode, 9896 0, 9897 w_mode, 9898 0, 9899 w_mode, 9900 /* da */ 9901 d_mode, 9902 d_mode, 9903 d_mode, 9904 d_mode, 9905 d_mode, 9906 d_mode, 9907 d_mode, 9908 d_mode, 9909 /* db */ 9910 d_mode, 9911 d_mode, 9912 d_mode, 9913 d_mode, 9914 0, 9915 t_mode, 9916 0, 9917 t_mode, 9918 /* dc */ 9919 q_mode, 9920 q_mode, 9921 q_mode, 9922 q_mode, 9923 q_mode, 9924 q_mode, 9925 q_mode, 9926 q_mode, 9927 /* dd */ 9928 q_mode, 9929 q_mode, 9930 q_mode, 9931 q_mode, 9932 0, 9933 0, 9934 0, 9935 w_mode, 9936 /* de */ 9937 w_mode, 9938 w_mode, 9939 w_mode, 9940 w_mode, 9941 w_mode, 9942 w_mode, 9943 w_mode, 9944 w_mode, 9945 /* df */ 9946 w_mode, 9947 w_mode, 9948 w_mode, 9949 w_mode, 9950 t_mode, 9951 q_mode, 9952 t_mode, 9953 q_mode 9954 }; 9955 9956 #define ST { OP_ST, 0 } 9957 #define STi { OP_STi, 0 } 9958 9959 #define FGRPd9_2 NULL, { { NULL, 0 } } 9960 #define FGRPd9_4 NULL, { { NULL, 1 } } 9961 #define FGRPd9_5 NULL, { { NULL, 2 } } 9962 #define FGRPd9_6 NULL, { { NULL, 3 } } 9963 #define FGRPd9_7 NULL, { { NULL, 4 } } 9964 #define FGRPda_5 NULL, { { NULL, 5 } } 9965 #define FGRPdb_4 NULL, { { NULL, 6 } } 9966 #define FGRPde_3 NULL, { { NULL, 7 } } 9967 #define FGRPdf_4 NULL, { { NULL, 8 } } 9968 9969 static const struct dis386 float_reg[][8] = { 9970 /* d8 */ 9971 { 9972 { "fadd", { ST, STi } }, 9973 { "fmul", { ST, STi } }, 9974 { "fcom", { STi } }, 9975 { "fcomp", { STi } }, 9976 { "fsub", { ST, STi } }, 9977 { "fsubr", { ST, STi } }, 9978 { "fdiv", { ST, STi } }, 9979 { "fdivr", { ST, STi } }, 9980 }, 9981 /* d9 */ 9982 { 9983 { "fld", { STi } }, 9984 { "fxch", { STi } }, 9985 { FGRPd9_2 }, 9986 { "(bad)", { XX } }, 9987 { FGRPd9_4 }, 9988 { FGRPd9_5 }, 9989 { FGRPd9_6 }, 9990 { FGRPd9_7 }, 9991 }, 9992 /* da */ 9993 { 9994 { "fcmovb", { ST, STi } }, 9995 { "fcmove", { ST, STi } }, 9996 { "fcmovbe",{ ST, STi } }, 9997 { "fcmovu", { ST, STi } }, 9998 { "(bad)", { XX } }, 9999 { FGRPda_5 }, 10000 { "(bad)", { XX } }, 10001 { "(bad)", { XX } }, 10002 }, 10003 /* db */ 10004 { 10005 { "fcmovnb",{ ST, STi } }, 10006 { "fcmovne",{ ST, STi } }, 10007 { "fcmovnbe",{ ST, STi } }, 10008 { "fcmovnu",{ ST, STi } }, 10009 { FGRPdb_4 }, 10010 { "fucomi", { ST, STi } }, 10011 { "fcomi", { ST, STi } }, 10012 { "(bad)", { XX } }, 10013 }, 10014 /* dc */ 10015 { 10016 { "fadd", { STi, ST } }, 10017 { "fmul", { STi, ST } }, 10018 { "(bad)", { XX } }, 10019 { "(bad)", { XX } }, 10020 { "fsub!M", { STi, ST } }, 10021 { "fsubM", { STi, ST } }, 10022 { "fdiv!M", { STi, ST } }, 10023 { "fdivM", { STi, ST } }, 10024 }, 10025 /* dd */ 10026 { 10027 { "ffree", { STi } }, 10028 { "(bad)", { XX } }, 10029 { "fst", { STi } }, 10030 { "fstp", { STi } }, 10031 { "fucom", { STi } }, 10032 { "fucomp", { STi } }, 10033 { "(bad)", { XX } }, 10034 { "(bad)", { XX } }, 10035 }, 10036 /* de */ 10037 { 10038 { "faddp", { STi, ST } }, 10039 { "fmulp", { STi, ST } }, 10040 { "(bad)", { XX } }, 10041 { FGRPde_3 }, 10042 { "fsub!Mp", { STi, ST } }, 10043 { "fsubMp", { STi, ST } }, 10044 { "fdiv!Mp", { STi, ST } }, 10045 { "fdivMp", { STi, ST } }, 10046 }, 10047 /* df */ 10048 { 10049 { "ffreep", { STi } }, 10050 { "(bad)", { XX } }, 10051 { "(bad)", { XX } }, 10052 { "(bad)", { XX } }, 10053 { FGRPdf_4 }, 10054 { "fucomip", { ST, STi } }, 10055 { "fcomip", { ST, STi } }, 10056 { "(bad)", { XX } }, 10057 }, 10058 }; 10059 10060 static char *fgrps[][8] = { 10061 /* d9_2 0 */ 10062 { 10063 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10064 }, 10065 10066 /* d9_4 1 */ 10067 { 10068 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", 10069 }, 10070 10071 /* d9_5 2 */ 10072 { 10073 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", 10074 }, 10075 10076 /* d9_6 3 */ 10077 { 10078 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", 10079 }, 10080 10081 /* d9_7 4 */ 10082 { 10083 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", 10084 }, 10085 10086 /* da_5 5 */ 10087 { 10088 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10089 }, 10090 10091 /* db_4 6 */ 10092 { 10093 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", 10094 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", 10095 }, 10096 10097 /* de_3 7 */ 10098 { 10099 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10100 }, 10101 10102 /* df_4 8 */ 10103 { 10104 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 10105 }, 10106 }; 10107 10108 static void 10109 swap_operand (void) 10110 { 10111 mnemonicendp[0] = '.'; 10112 mnemonicendp[1] = 's'; 10113 mnemonicendp += 2; 10114 } 10115 10116 static void 10117 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, 10118 int sizeflag ATTRIBUTE_UNUSED) 10119 { 10120 /* Skip mod/rm byte. */ 10121 MODRM_CHECK; 10122 codep++; 10123 } 10124 10125 static void 10126 dofloat (int sizeflag) 10127 { 10128 const struct dis386 *dp; 10129 unsigned char floatop; 10130 10131 floatop = codep[-1]; 10132 10133 if (modrm.mod != 3) 10134 { 10135 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; 10136 10137 putop (float_mem[fp_indx], sizeflag); 10138 obufp = op_out[0]; 10139 op_ad = 2; 10140 OP_E (float_mem_mode[fp_indx], sizeflag); 10141 return; 10142 } 10143 /* Skip mod/rm byte. */ 10144 MODRM_CHECK; 10145 codep++; 10146 10147 dp = &float_reg[floatop - 0xd8][modrm.reg]; 10148 if (dp->name == NULL) 10149 { 10150 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); 10151 10152 /* Instruction fnstsw is only one with strange arg. */ 10153 if (floatop == 0xdf && codep[-1] == 0xe0) 10154 strcpy (op_out[0], names16[0]); 10155 } 10156 else 10157 { 10158 putop (dp->name, sizeflag); 10159 10160 obufp = op_out[0]; 10161 op_ad = 2; 10162 if (dp->op[0].rtn) 10163 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); 10164 10165 obufp = op_out[1]; 10166 op_ad = 1; 10167 if (dp->op[1].rtn) 10168 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); 10169 } 10170 } 10171 10172 static void 10173 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 10174 { 10175 oappend ("%st" + intel_syntax); 10176 } 10177 10178 static void 10179 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 10180 { 10181 sprintf (scratchbuf, "%%st(%d)", modrm.rm); 10182 oappend (scratchbuf + intel_syntax); 10183 } 10184 10185 /* Capital letters in template are macros. */ 10186 static int 10187 putop (const char *in_template, int sizeflag) 10188 { 10189 const char *p; 10190 int alt = 0; 10191 int cond = 1; 10192 unsigned int l = 0, len = 1; 10193 char last[4]; 10194 10195 #define SAVE_LAST(c) \ 10196 if (l < len && l < sizeof (last)) \ 10197 last[l++] = c; \ 10198 else \ 10199 abort (); 10200 10201 for (p = in_template; *p; p++) 10202 { 10203 switch (*p) 10204 { 10205 default: 10206 *obufp++ = *p; 10207 break; 10208 case '%': 10209 len++; 10210 break; 10211 case '!': 10212 cond = 0; 10213 break; 10214 case '{': 10215 alt = 0; 10216 if (intel_syntax) 10217 { 10218 while (*++p != '|') 10219 if (*p == '}' || *p == '\0') 10220 abort (); 10221 } 10222 /* Fall through. */ 10223 case 'I': 10224 alt = 1; 10225 continue; 10226 case '|': 10227 while (*++p != '}') 10228 { 10229 if (*p == '\0') 10230 abort (); 10231 } 10232 break; 10233 case '}': 10234 break; 10235 case 'A': 10236 if (intel_syntax) 10237 break; 10238 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) 10239 *obufp++ = 'b'; 10240 break; 10241 case 'B': 10242 if (intel_syntax) 10243 break; 10244 if (sizeflag & SUFFIX_ALWAYS) 10245 *obufp++ = 'b'; 10246 break; 10247 case 'C': 10248 if (intel_syntax && !alt) 10249 break; 10250 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) 10251 { 10252 if (sizeflag & DFLAG) 10253 *obufp++ = intel_syntax ? 'd' : 'l'; 10254 else 10255 *obufp++ = intel_syntax ? 'w' : 's'; 10256 used_prefixes |= (prefixes & PREFIX_DATA); 10257 } 10258 break; 10259 case 'D': 10260 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) 10261 break; 10262 USED_REX (REX_W); 10263 if (modrm.mod == 3) 10264 { 10265 if (rex & REX_W) 10266 *obufp++ = 'q'; 10267 else if (sizeflag & DFLAG) 10268 *obufp++ = intel_syntax ? 'd' : 'l'; 10269 else 10270 *obufp++ = 'w'; 10271 used_prefixes |= (prefixes & PREFIX_DATA); 10272 } 10273 else 10274 *obufp++ = 'w'; 10275 break; 10276 case 'E': /* For jcxz/jecxz */ 10277 if (address_mode == mode_64bit) 10278 { 10279 if (sizeflag & AFLAG) 10280 *obufp++ = 'r'; 10281 else 10282 *obufp++ = 'e'; 10283 } 10284 else 10285 if (sizeflag & AFLAG) 10286 *obufp++ = 'e'; 10287 used_prefixes |= (prefixes & PREFIX_ADDR); 10288 break; 10289 case 'F': 10290 if (intel_syntax) 10291 break; 10292 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) 10293 { 10294 if (sizeflag & AFLAG) 10295 *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; 10296 else 10297 *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; 10298 used_prefixes |= (prefixes & PREFIX_ADDR); 10299 } 10300 break; 10301 case 'G': 10302 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) 10303 break; 10304 if ((rex & REX_W) || (sizeflag & DFLAG)) 10305 *obufp++ = 'l'; 10306 else 10307 *obufp++ = 'w'; 10308 if (!(rex & REX_W)) 10309 used_prefixes |= (prefixes & PREFIX_DATA); 10310 break; 10311 case 'H': 10312 if (intel_syntax) 10313 break; 10314 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS 10315 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) 10316 { 10317 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); 10318 *obufp++ = ','; 10319 *obufp++ = 'p'; 10320 if (prefixes & PREFIX_DS) 10321 *obufp++ = 't'; 10322 else 10323 *obufp++ = 'n'; 10324 } 10325 break; 10326 case 'J': 10327 if (intel_syntax) 10328 break; 10329 *obufp++ = 'l'; 10330 break; 10331 case 'K': 10332 USED_REX (REX_W); 10333 if (rex & REX_W) 10334 *obufp++ = 'q'; 10335 else 10336 *obufp++ = 'd'; 10337 break; 10338 case 'Z': 10339 if (intel_syntax) 10340 break; 10341 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) 10342 { 10343 *obufp++ = 'q'; 10344 break; 10345 } 10346 /* Fall through. */ 10347 goto case_L; 10348 case 'L': 10349 if (l != 0 || len != 1) 10350 { 10351 SAVE_LAST (*p); 10352 break; 10353 } 10354 case_L: 10355 if (intel_syntax) 10356 break; 10357 if (sizeflag & SUFFIX_ALWAYS) 10358 *obufp++ = 'l'; 10359 break; 10360 case 'M': 10361 if (intel_mnemonic != cond) 10362 *obufp++ = 'r'; 10363 break; 10364 case 'N': 10365 if ((prefixes & PREFIX_FWAIT) == 0) 10366 *obufp++ = 'n'; 10367 else 10368 used_prefixes |= PREFIX_FWAIT; 10369 break; 10370 case 'O': 10371 USED_REX (REX_W); 10372 if (rex & REX_W) 10373 *obufp++ = 'o'; 10374 else if (intel_syntax && (sizeflag & DFLAG)) 10375 *obufp++ = 'q'; 10376 else 10377 *obufp++ = 'd'; 10378 if (!(rex & REX_W)) 10379 used_prefixes |= (prefixes & PREFIX_DATA); 10380 break; 10381 case 'T': 10382 if (intel_syntax) 10383 break; 10384 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 10385 { 10386 *obufp++ = 'q'; 10387 break; 10388 } 10389 /* Fall through. */ 10390 case 'P': 10391 if (intel_syntax) 10392 break; 10393 if ((prefixes & PREFIX_DATA) 10394 || (rex & REX_W) 10395 || (sizeflag & SUFFIX_ALWAYS)) 10396 { 10397 USED_REX (REX_W); 10398 if (rex & REX_W) 10399 *obufp++ = 'q'; 10400 else 10401 { 10402 if (sizeflag & DFLAG) 10403 *obufp++ = 'l'; 10404 else 10405 *obufp++ = 'w'; 10406 } 10407 used_prefixes |= (prefixes & PREFIX_DATA); 10408 } 10409 break; 10410 case 'U': 10411 if (intel_syntax) 10412 break; 10413 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 10414 { 10415 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) 10416 *obufp++ = 'q'; 10417 break; 10418 } 10419 /* Fall through. */ 10420 goto case_Q; 10421 case 'Q': 10422 if (l == 0 && len == 1) 10423 { 10424 case_Q: 10425 if (intel_syntax && !alt) 10426 break; 10427 USED_REX (REX_W); 10428 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) 10429 { 10430 if (rex & REX_W) 10431 *obufp++ = 'q'; 10432 else 10433 { 10434 if (sizeflag & DFLAG) 10435 *obufp++ = intel_syntax ? 'd' : 'l'; 10436 else 10437 *obufp++ = 'w'; 10438 } 10439 used_prefixes |= (prefixes & PREFIX_DATA); 10440 } 10441 } 10442 else 10443 { 10444 if (l != 1 || len != 2 || last[0] != 'L') 10445 { 10446 SAVE_LAST (*p); 10447 break; 10448 } 10449 if (intel_syntax 10450 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) 10451 break; 10452 if ((rex & REX_W)) 10453 { 10454 USED_REX (REX_W); 10455 *obufp++ = 'q'; 10456 } 10457 else 10458 *obufp++ = 'l'; 10459 } 10460 break; 10461 case 'R': 10462 USED_REX (REX_W); 10463 if (rex & REX_W) 10464 *obufp++ = 'q'; 10465 else if (sizeflag & DFLAG) 10466 { 10467 if (intel_syntax) 10468 *obufp++ = 'd'; 10469 else 10470 *obufp++ = 'l'; 10471 } 10472 else 10473 *obufp++ = 'w'; 10474 if (intel_syntax && !p[1] 10475 && ((rex & REX_W) || (sizeflag & DFLAG))) 10476 *obufp++ = 'e'; 10477 if (!(rex & REX_W)) 10478 used_prefixes |= (prefixes & PREFIX_DATA); 10479 break; 10480 case 'V': 10481 if (intel_syntax) 10482 break; 10483 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 10484 { 10485 if (sizeflag & SUFFIX_ALWAYS) 10486 *obufp++ = 'q'; 10487 break; 10488 } 10489 /* Fall through. */ 10490 case 'S': 10491 if (intel_syntax) 10492 break; 10493 if (sizeflag & SUFFIX_ALWAYS) 10494 { 10495 if (rex & REX_W) 10496 *obufp++ = 'q'; 10497 else 10498 { 10499 if (sizeflag & DFLAG) 10500 *obufp++ = 'l'; 10501 else 10502 *obufp++ = 'w'; 10503 used_prefixes |= (prefixes & PREFIX_DATA); 10504 } 10505 } 10506 break; 10507 case 'X': 10508 if (l != 0 || len != 1) 10509 { 10510 SAVE_LAST (*p); 10511 break; 10512 } 10513 if (need_vex && vex.prefix) 10514 { 10515 if (vex.prefix == DATA_PREFIX_OPCODE) 10516 *obufp++ = 'd'; 10517 else 10518 *obufp++ = 's'; 10519 } 10520 else if (prefixes & PREFIX_DATA) 10521 *obufp++ = 'd'; 10522 else 10523 *obufp++ = 's'; 10524 used_prefixes |= (prefixes & PREFIX_DATA); 10525 break; 10526 case 'Y': 10527 if (l == 0 && len == 1) 10528 { 10529 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) 10530 break; 10531 if (rex & REX_W) 10532 { 10533 USED_REX (REX_W); 10534 *obufp++ = 'q'; 10535 } 10536 break; 10537 } 10538 else 10539 { 10540 if (l != 1 || len != 2 || last[0] != 'X') 10541 { 10542 SAVE_LAST (*p); 10543 break; 10544 } 10545 if (!need_vex) 10546 abort (); 10547 if (intel_syntax 10548 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) 10549 break; 10550 switch (vex.length) 10551 { 10552 case 128: 10553 *obufp++ = 'x'; 10554 break; 10555 case 256: 10556 *obufp++ = 'y'; 10557 break; 10558 default: 10559 abort (); 10560 } 10561 } 10562 break; 10563 case 'W': 10564 if (l == 0 && len == 1) 10565 { 10566 /* operand size flag for cwtl, cbtw */ 10567 USED_REX (REX_W); 10568 if (rex & REX_W) 10569 { 10570 if (intel_syntax) 10571 *obufp++ = 'd'; 10572 else 10573 *obufp++ = 'l'; 10574 } 10575 else if (sizeflag & DFLAG) 10576 *obufp++ = 'w'; 10577 else 10578 *obufp++ = 'b'; 10579 if (!(rex & REX_W)) 10580 used_prefixes |= (prefixes & PREFIX_DATA); 10581 } 10582 else 10583 { 10584 if (l != 1 || len != 2 || last[0] != 'X') 10585 { 10586 SAVE_LAST (*p); 10587 break; 10588 } 10589 if (!need_vex) 10590 abort (); 10591 *obufp++ = vex.w ? 'd': 's'; 10592 } 10593 break; 10594 } 10595 alt = 0; 10596 } 10597 *obufp = 0; 10598 mnemonicendp = obufp; 10599 return 0; 10600 } 10601 10602 static void 10603 oappend (const char *s) 10604 { 10605 obufp = stpcpy (obufp, s); 10606 } 10607 10608 static void 10609 append_seg (void) 10610 { 10611 if (prefixes & PREFIX_CS) 10612 { 10613 used_prefixes |= PREFIX_CS; 10614 oappend ("%cs:" + intel_syntax); 10615 } 10616 if (prefixes & PREFIX_DS) 10617 { 10618 used_prefixes |= PREFIX_DS; 10619 oappend ("%ds:" + intel_syntax); 10620 } 10621 if (prefixes & PREFIX_SS) 10622 { 10623 used_prefixes |= PREFIX_SS; 10624 oappend ("%ss:" + intel_syntax); 10625 } 10626 if (prefixes & PREFIX_ES) 10627 { 10628 used_prefixes |= PREFIX_ES; 10629 oappend ("%es:" + intel_syntax); 10630 } 10631 if (prefixes & PREFIX_FS) 10632 { 10633 used_prefixes |= PREFIX_FS; 10634 oappend ("%fs:" + intel_syntax); 10635 } 10636 if (prefixes & PREFIX_GS) 10637 { 10638 used_prefixes |= PREFIX_GS; 10639 oappend ("%gs:" + intel_syntax); 10640 } 10641 } 10642 10643 static void 10644 OP_indirE (int bytemode, int sizeflag) 10645 { 10646 if (!intel_syntax) 10647 oappend ("*"); 10648 OP_E (bytemode, sizeflag); 10649 } 10650 10651 static void 10652 print_operand_value (char *buf, int hex, bfd_vma disp) 10653 { 10654 if (address_mode == mode_64bit) 10655 { 10656 if (hex) 10657 { 10658 char tmp[30]; 10659 int i; 10660 buf[0] = '0'; 10661 buf[1] = 'x'; 10662 sprintf_vma (tmp, disp); 10663 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); 10664 strcpy (buf + 2, tmp + i); 10665 } 10666 else 10667 { 10668 bfd_signed_vma v = disp; 10669 char tmp[30]; 10670 int i; 10671 if (v < 0) 10672 { 10673 *(buf++) = '-'; 10674 v = -disp; 10675 /* Check for possible overflow on 0x8000000000000000. */ 10676 if (v < 0) 10677 { 10678 strcpy (buf, "9223372036854775808"); 10679 return; 10680 } 10681 } 10682 if (!v) 10683 { 10684 strcpy (buf, "0"); 10685 return; 10686 } 10687 10688 i = 0; 10689 tmp[29] = 0; 10690 while (v) 10691 { 10692 tmp[28 - i] = (v % 10) + '0'; 10693 v /= 10; 10694 i++; 10695 } 10696 strcpy (buf, tmp + 29 - i); 10697 } 10698 } 10699 else 10700 { 10701 if (hex) 10702 sprintf (buf, "0x%x", (unsigned int) disp); 10703 else 10704 sprintf (buf, "%d", (int) disp); 10705 } 10706 } 10707 10708 /* Put DISP in BUF as signed hex number. */ 10709 10710 static void 10711 print_displacement (char *buf, bfd_vma disp) 10712 { 10713 bfd_signed_vma val = disp; 10714 char tmp[30]; 10715 int i, j = 0; 10716 10717 if (val < 0) 10718 { 10719 buf[j++] = '-'; 10720 val = -disp; 10721 10722 /* Check for possible overflow. */ 10723 if (val < 0) 10724 { 10725 switch (address_mode) 10726 { 10727 case mode_64bit: 10728 strcpy (buf + j, "0x8000000000000000"); 10729 break; 10730 case mode_32bit: 10731 strcpy (buf + j, "0x80000000"); 10732 break; 10733 case mode_16bit: 10734 strcpy (buf + j, "0x8000"); 10735 break; 10736 } 10737 return; 10738 } 10739 } 10740 10741 buf[j++] = '0'; 10742 buf[j++] = 'x'; 10743 10744 sprintf_vma (tmp, (bfd_vma) val); 10745 for (i = 0; tmp[i] == '0'; i++) 10746 continue; 10747 if (tmp[i] == '\0') 10748 i--; 10749 strcpy (buf + j, tmp + i); 10750 } 10751 10752 static void 10753 intel_operand_size (int bytemode, int sizeflag) 10754 { 10755 switch (bytemode) 10756 { 10757 case b_mode: 10758 case b_swap_mode: 10759 case dqb_mode: 10760 oappend ("BYTE PTR "); 10761 break; 10762 case w_mode: 10763 case dqw_mode: 10764 oappend ("WORD PTR "); 10765 break; 10766 case stack_v_mode: 10767 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 10768 { 10769 oappend ("QWORD PTR "); 10770 used_prefixes |= (prefixes & PREFIX_DATA); 10771 break; 10772 } 10773 /* FALLTHRU */ 10774 case v_mode: 10775 case v_swap_mode: 10776 case dq_mode: 10777 USED_REX (REX_W); 10778 if (rex & REX_W) 10779 oappend ("QWORD PTR "); 10780 else if ((sizeflag & DFLAG) || bytemode == dq_mode) 10781 oappend ("DWORD PTR "); 10782 else 10783 oappend ("WORD PTR "); 10784 used_prefixes |= (prefixes & PREFIX_DATA); 10785 break; 10786 case z_mode: 10787 if ((rex & REX_W) || (sizeflag & DFLAG)) 10788 *obufp++ = 'D'; 10789 oappend ("WORD PTR "); 10790 if (!(rex & REX_W)) 10791 used_prefixes |= (prefixes & PREFIX_DATA); 10792 break; 10793 case a_mode: 10794 if (sizeflag & DFLAG) 10795 oappend ("QWORD PTR "); 10796 else 10797 oappend ("DWORD PTR "); 10798 used_prefixes |= (prefixes & PREFIX_DATA); 10799 break; 10800 case d_mode: 10801 case d_swap_mode: 10802 case dqd_mode: 10803 oappend ("DWORD PTR "); 10804 break; 10805 case q_mode: 10806 case q_swap_mode: 10807 oappend ("QWORD PTR "); 10808 break; 10809 case m_mode: 10810 if (address_mode == mode_64bit) 10811 oappend ("QWORD PTR "); 10812 else 10813 oappend ("DWORD PTR "); 10814 break; 10815 case f_mode: 10816 if (sizeflag & DFLAG) 10817 oappend ("FWORD PTR "); 10818 else 10819 oappend ("DWORD PTR "); 10820 used_prefixes |= (prefixes & PREFIX_DATA); 10821 break; 10822 case t_mode: 10823 oappend ("TBYTE PTR "); 10824 break; 10825 case x_mode: 10826 case x_swap_mode: 10827 if (need_vex) 10828 { 10829 switch (vex.length) 10830 { 10831 case 128: 10832 oappend ("XMMWORD PTR "); 10833 break; 10834 case 256: 10835 oappend ("YMMWORD PTR "); 10836 break; 10837 default: 10838 abort (); 10839 } 10840 } 10841 else 10842 oappend ("XMMWORD PTR "); 10843 break; 10844 case xmm_mode: 10845 oappend ("XMMWORD PTR "); 10846 break; 10847 case xmmq_mode: 10848 if (!need_vex) 10849 abort (); 10850 10851 switch (vex.length) 10852 { 10853 case 128: 10854 oappend ("QWORD PTR "); 10855 break; 10856 case 256: 10857 oappend ("XMMWORD PTR "); 10858 break; 10859 default: 10860 abort (); 10861 } 10862 break; 10863 case ymmq_mode: 10864 if (!need_vex) 10865 abort (); 10866 10867 switch (vex.length) 10868 { 10869 case 128: 10870 oappend ("QWORD PTR "); 10871 break; 10872 case 256: 10873 oappend ("YMMWORD PTR "); 10874 break; 10875 default: 10876 abort (); 10877 } 10878 break; 10879 case o_mode: 10880 oappend ("OWORD PTR "); 10881 break; 10882 case vex_w_dq_mode: 10883 if (!need_vex) 10884 abort (); 10885 10886 if (vex.w) 10887 oappend ("QWORD PTR "); 10888 else 10889 oappend ("DWORD PTR "); 10890 break; 10891 default: 10892 break; 10893 } 10894 } 10895 10896 static void 10897 OP_E_register (int bytemode, int sizeflag) 10898 { 10899 int reg = modrm.rm; 10900 const char **names; 10901 10902 USED_REX (REX_B); 10903 if ((rex & REX_B)) 10904 reg += 8; 10905 10906 if ((sizeflag & SUFFIX_ALWAYS) 10907 && (bytemode == b_swap_mode || bytemode == v_swap_mode)) 10908 swap_operand (); 10909 10910 switch (bytemode) 10911 { 10912 case b_mode: 10913 case b_swap_mode: 10914 USED_REX (0); 10915 if (rex) 10916 names = names8rex; 10917 else 10918 names = names8; 10919 break; 10920 case w_mode: 10921 names = names16; 10922 break; 10923 case d_mode: 10924 names = names32; 10925 break; 10926 case q_mode: 10927 names = names64; 10928 break; 10929 case m_mode: 10930 names = address_mode == mode_64bit ? names64 : names32; 10931 break; 10932 case stack_v_mode: 10933 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 10934 { 10935 names = names64; 10936 used_prefixes |= (prefixes & PREFIX_DATA); 10937 break; 10938 } 10939 bytemode = v_mode; 10940 /* FALLTHRU */ 10941 case v_mode: 10942 case v_swap_mode: 10943 case dq_mode: 10944 case dqb_mode: 10945 case dqd_mode: 10946 case dqw_mode: 10947 USED_REX (REX_W); 10948 if (rex & REX_W) 10949 names = names64; 10950 else if ((sizeflag & DFLAG) 10951 || (bytemode != v_mode 10952 && bytemode != v_swap_mode)) 10953 names = names32; 10954 else 10955 names = names16; 10956 used_prefixes |= (prefixes & PREFIX_DATA); 10957 break; 10958 case 0: 10959 return; 10960 default: 10961 oappend (INTERNAL_DISASSEMBLER_ERROR); 10962 return; 10963 } 10964 oappend (names[reg]); 10965 } 10966 10967 static void 10968 OP_E_memory (int bytemode, int sizeflag) 10969 { 10970 bfd_vma disp = 0; 10971 int add = (rex & REX_B) ? 8 : 0; 10972 int riprel = 0; 10973 10974 USED_REX (REX_B); 10975 if (intel_syntax) 10976 intel_operand_size (bytemode, sizeflag); 10977 append_seg (); 10978 10979 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 10980 { 10981 /* 32/64 bit address mode */ 10982 int havedisp; 10983 int havesib; 10984 int havebase; 10985 int haveindex; 10986 int needindex; 10987 int base, rbase; 10988 int index = 0; 10989 int scale = 0; 10990 10991 havesib = 0; 10992 havebase = 1; 10993 haveindex = 0; 10994 base = modrm.rm; 10995 10996 if (base == 4) 10997 { 10998 havesib = 1; 10999 FETCH_DATA (the_info, codep + 1); 11000 index = (*codep >> 3) & 7; 11001 scale = (*codep >> 6) & 3; 11002 base = *codep & 7; 11003 USED_REX (REX_X); 11004 if (rex & REX_X) 11005 index += 8; 11006 haveindex = index != 4; 11007 codep++; 11008 } 11009 rbase = base + add; 11010 11011 switch (modrm.mod) 11012 { 11013 case 0: 11014 if (base == 5) 11015 { 11016 havebase = 0; 11017 if (address_mode == mode_64bit && !havesib) 11018 riprel = 1; 11019 disp = get32s (); 11020 } 11021 break; 11022 case 1: 11023 FETCH_DATA (the_info, codep + 1); 11024 disp = *codep++; 11025 if ((disp & 0x80) != 0) 11026 disp -= 0x100; 11027 break; 11028 case 2: 11029 disp = get32s (); 11030 break; 11031 } 11032 11033 /* In 32bit mode, we need index register to tell [offset] from 11034 [eiz*1 + offset]. */ 11035 needindex = (havesib 11036 && !havebase 11037 && !haveindex 11038 && address_mode == mode_32bit); 11039 havedisp = (havebase 11040 || needindex 11041 || (havesib && (haveindex || scale != 0))); 11042 11043 if (!intel_syntax) 11044 if (modrm.mod != 0 || base == 5) 11045 { 11046 if (havedisp || riprel) 11047 print_displacement (scratchbuf, disp); 11048 else 11049 print_operand_value (scratchbuf, 1, disp); 11050 oappend (scratchbuf); 11051 if (riprel) 11052 { 11053 set_op (disp, 1); 11054 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); 11055 } 11056 } 11057 11058 if (havebase || haveindex || riprel) 11059 used_prefixes |= PREFIX_ADDR; 11060 11061 if (havedisp || (intel_syntax && riprel)) 11062 { 11063 *obufp++ = open_char; 11064 if (intel_syntax && riprel) 11065 { 11066 set_op (disp, 1); 11067 oappend (sizeflag & AFLAG ? "rip" : "eip"); 11068 } 11069 *obufp = '\0'; 11070 if (havebase) 11071 oappend (address_mode == mode_64bit && (sizeflag & AFLAG) 11072 ? names64[rbase] : names32[rbase]); 11073 if (havesib) 11074 { 11075 /* ESP/RSP won't allow index. If base isn't ESP/RSP, 11076 print index to tell base + index from base. */ 11077 if (scale != 0 11078 || needindex 11079 || haveindex 11080 || (havebase && base != ESP_REG_NUM)) 11081 { 11082 if (!intel_syntax || havebase) 11083 { 11084 *obufp++ = separator_char; 11085 *obufp = '\0'; 11086 } 11087 if (haveindex) 11088 oappend (address_mode == mode_64bit 11089 && (sizeflag & AFLAG) 11090 ? names64[index] : names32[index]); 11091 else 11092 oappend (address_mode == mode_64bit 11093 && (sizeflag & AFLAG) 11094 ? index64 : index32); 11095 11096 *obufp++ = scale_char; 11097 *obufp = '\0'; 11098 sprintf (scratchbuf, "%d", 1 << scale); 11099 oappend (scratchbuf); 11100 } 11101 } 11102 if (intel_syntax 11103 && (disp || modrm.mod != 0 || base == 5)) 11104 { 11105 if (!havedisp || (bfd_signed_vma) disp >= 0) 11106 { 11107 *obufp++ = '+'; 11108 *obufp = '\0'; 11109 } 11110 else if (modrm.mod != 1 && disp != -disp) 11111 { 11112 *obufp++ = '-'; 11113 *obufp = '\0'; 11114 disp = - (bfd_signed_vma) disp; 11115 } 11116 11117 if (havedisp) 11118 print_displacement (scratchbuf, disp); 11119 else 11120 print_operand_value (scratchbuf, 1, disp); 11121 oappend (scratchbuf); 11122 } 11123 11124 *obufp++ = close_char; 11125 *obufp = '\0'; 11126 } 11127 else if (intel_syntax) 11128 { 11129 if (modrm.mod != 0 || base == 5) 11130 { 11131 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS 11132 | PREFIX_ES | PREFIX_FS | PREFIX_GS)) 11133 ; 11134 else 11135 { 11136 oappend (names_seg[ds_reg - es_reg]); 11137 oappend (":"); 11138 } 11139 print_operand_value (scratchbuf, 1, disp); 11140 oappend (scratchbuf); 11141 } 11142 } 11143 } 11144 else 11145 { /* 16 bit address mode */ 11146 switch (modrm.mod) 11147 { 11148 case 0: 11149 if (modrm.rm == 6) 11150 { 11151 disp = get16 (); 11152 if ((disp & 0x8000) != 0) 11153 disp -= 0x10000; 11154 } 11155 break; 11156 case 1: 11157 FETCH_DATA (the_info, codep + 1); 11158 disp = *codep++; 11159 if ((disp & 0x80) != 0) 11160 disp -= 0x100; 11161 break; 11162 case 2: 11163 disp = get16 (); 11164 if ((disp & 0x8000) != 0) 11165 disp -= 0x10000; 11166 break; 11167 } 11168 11169 if (!intel_syntax) 11170 if (modrm.mod != 0 || modrm.rm == 6) 11171 { 11172 print_displacement (scratchbuf, disp); 11173 oappend (scratchbuf); 11174 } 11175 11176 if (modrm.mod != 0 || modrm.rm != 6) 11177 { 11178 *obufp++ = open_char; 11179 *obufp = '\0'; 11180 oappend (index16[modrm.rm]); 11181 if (intel_syntax 11182 && (disp || modrm.mod != 0 || modrm.rm == 6)) 11183 { 11184 if ((bfd_signed_vma) disp >= 0) 11185 { 11186 *obufp++ = '+'; 11187 *obufp = '\0'; 11188 } 11189 else if (modrm.mod != 1) 11190 { 11191 *obufp++ = '-'; 11192 *obufp = '\0'; 11193 disp = - (bfd_signed_vma) disp; 11194 } 11195 11196 print_displacement (scratchbuf, disp); 11197 oappend (scratchbuf); 11198 } 11199 11200 *obufp++ = close_char; 11201 *obufp = '\0'; 11202 } 11203 else if (intel_syntax) 11204 { 11205 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS 11206 | PREFIX_ES | PREFIX_FS | PREFIX_GS)) 11207 ; 11208 else 11209 { 11210 oappend (names_seg[ds_reg - es_reg]); 11211 oappend (":"); 11212 } 11213 print_operand_value (scratchbuf, 1, disp & 0xffff); 11214 oappend (scratchbuf); 11215 } 11216 } 11217 } 11218 11219 static void 11220 OP_E_extended (int bytemode, int sizeflag) 11221 { 11222 /* Skip mod/rm byte. */ 11223 MODRM_CHECK; 11224 codep++; 11225 11226 if (modrm.mod == 3) 11227 OP_E_register (bytemode, sizeflag); 11228 else 11229 OP_E_memory (bytemode, sizeflag); 11230 } 11231 11232 static void 11233 OP_E (int bytemode, int sizeflag) 11234 { 11235 OP_E_extended (bytemode, sizeflag); 11236 } 11237 11238 11239 static void 11240 OP_G (int bytemode, int sizeflag) 11241 { 11242 int add = 0; 11243 USED_REX (REX_R); 11244 if (rex & REX_R) 11245 add += 8; 11246 switch (bytemode) 11247 { 11248 case b_mode: 11249 USED_REX (0); 11250 if (rex) 11251 oappend (names8rex[modrm.reg + add]); 11252 else 11253 oappend (names8[modrm.reg + add]); 11254 break; 11255 case w_mode: 11256 oappend (names16[modrm.reg + add]); 11257 break; 11258 case d_mode: 11259 oappend (names32[modrm.reg + add]); 11260 break; 11261 case q_mode: 11262 oappend (names64[modrm.reg + add]); 11263 break; 11264 case v_mode: 11265 case dq_mode: 11266 case dqb_mode: 11267 case dqd_mode: 11268 case dqw_mode: 11269 USED_REX (REX_W); 11270 if (rex & REX_W) 11271 oappend (names64[modrm.reg + add]); 11272 else if ((sizeflag & DFLAG) || bytemode != v_mode) 11273 oappend (names32[modrm.reg + add]); 11274 else 11275 oappend (names16[modrm.reg + add]); 11276 used_prefixes |= (prefixes & PREFIX_DATA); 11277 break; 11278 case m_mode: 11279 if (address_mode == mode_64bit) 11280 oappend (names64[modrm.reg + add]); 11281 else 11282 oappend (names32[modrm.reg + add]); 11283 break; 11284 default: 11285 oappend (INTERNAL_DISASSEMBLER_ERROR); 11286 break; 11287 } 11288 } 11289 11290 static bfd_vma 11291 get64 (void) 11292 { 11293 bfd_vma x; 11294 #ifdef BFD64 11295 unsigned int a; 11296 unsigned int b; 11297 11298 FETCH_DATA (the_info, codep + 8); 11299 a = *codep++ & 0xff; 11300 a |= (*codep++ & 0xff) << 8; 11301 a |= (*codep++ & 0xff) << 16; 11302 a |= (*codep++ & 0xff) << 24; 11303 b = *codep++ & 0xff; 11304 b |= (*codep++ & 0xff) << 8; 11305 b |= (*codep++ & 0xff) << 16; 11306 b |= (*codep++ & 0xff) << 24; 11307 x = a + ((bfd_vma) b << 32); 11308 #else 11309 abort (); 11310 x = 0; 11311 #endif 11312 return x; 11313 } 11314 11315 static bfd_signed_vma 11316 get32 (void) 11317 { 11318 bfd_signed_vma x = 0; 11319 11320 FETCH_DATA (the_info, codep + 4); 11321 x = *codep++ & (bfd_signed_vma) 0xff; 11322 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; 11323 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; 11324 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; 11325 return x; 11326 } 11327 11328 static bfd_signed_vma 11329 get32s (void) 11330 { 11331 bfd_signed_vma x = 0; 11332 11333 FETCH_DATA (the_info, codep + 4); 11334 x = *codep++ & (bfd_signed_vma) 0xff; 11335 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; 11336 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; 11337 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; 11338 11339 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); 11340 11341 return x; 11342 } 11343 11344 static int 11345 get16 (void) 11346 { 11347 int x = 0; 11348 11349 FETCH_DATA (the_info, codep + 2); 11350 x = *codep++ & 0xff; 11351 x |= (*codep++ & 0xff) << 8; 11352 return x; 11353 } 11354 11355 static void 11356 set_op (bfd_vma op, int riprel) 11357 { 11358 op_index[op_ad] = op_ad; 11359 if (address_mode == mode_64bit) 11360 { 11361 op_address[op_ad] = op; 11362 op_riprel[op_ad] = riprel; 11363 } 11364 else 11365 { 11366 /* Mask to get a 32-bit address. */ 11367 op_address[op_ad] = op & 0xffffffff; 11368 op_riprel[op_ad] = riprel & 0xffffffff; 11369 } 11370 } 11371 11372 static void 11373 OP_REG (int code, int sizeflag) 11374 { 11375 const char *s; 11376 int add; 11377 USED_REX (REX_B); 11378 if (rex & REX_B) 11379 add = 8; 11380 else 11381 add = 0; 11382 11383 switch (code) 11384 { 11385 case ax_reg: case cx_reg: case dx_reg: case bx_reg: 11386 case sp_reg: case bp_reg: case si_reg: case di_reg: 11387 s = names16[code - ax_reg + add]; 11388 break; 11389 case es_reg: case ss_reg: case cs_reg: 11390 case ds_reg: case fs_reg: case gs_reg: 11391 s = names_seg[code - es_reg + add]; 11392 break; 11393 case al_reg: case ah_reg: case cl_reg: case ch_reg: 11394 case dl_reg: case dh_reg: case bl_reg: case bh_reg: 11395 USED_REX (0); 11396 if (rex) 11397 s = names8rex[code - al_reg + add]; 11398 else 11399 s = names8[code - al_reg]; 11400 break; 11401 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: 11402 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: 11403 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 11404 { 11405 s = names64[code - rAX_reg + add]; 11406 break; 11407 } 11408 code += eAX_reg - rAX_reg; 11409 /* Fall through. */ 11410 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: 11411 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: 11412 USED_REX (REX_W); 11413 if (rex & REX_W) 11414 s = names64[code - eAX_reg + add]; 11415 else if (sizeflag & DFLAG) 11416 s = names32[code - eAX_reg + add]; 11417 else 11418 s = names16[code - eAX_reg + add]; 11419 used_prefixes |= (prefixes & PREFIX_DATA); 11420 break; 11421 default: 11422 s = INTERNAL_DISASSEMBLER_ERROR; 11423 break; 11424 } 11425 oappend (s); 11426 } 11427 11428 static void 11429 OP_IMREG (int code, int sizeflag) 11430 { 11431 const char *s; 11432 11433 switch (code) 11434 { 11435 case indir_dx_reg: 11436 if (intel_syntax) 11437 s = "dx"; 11438 else 11439 s = "(%dx)"; 11440 break; 11441 case ax_reg: case cx_reg: case dx_reg: case bx_reg: 11442 case sp_reg: case bp_reg: case si_reg: case di_reg: 11443 s = names16[code - ax_reg]; 11444 break; 11445 case es_reg: case ss_reg: case cs_reg: 11446 case ds_reg: case fs_reg: case gs_reg: 11447 s = names_seg[code - es_reg]; 11448 break; 11449 case al_reg: case ah_reg: case cl_reg: case ch_reg: 11450 case dl_reg: case dh_reg: case bl_reg: case bh_reg: 11451 USED_REX (0); 11452 if (rex) 11453 s = names8rex[code - al_reg]; 11454 else 11455 s = names8[code - al_reg]; 11456 break; 11457 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: 11458 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: 11459 USED_REX (REX_W); 11460 if (rex & REX_W) 11461 s = names64[code - eAX_reg]; 11462 else if (sizeflag & DFLAG) 11463 s = names32[code - eAX_reg]; 11464 else 11465 s = names16[code - eAX_reg]; 11466 used_prefixes |= (prefixes & PREFIX_DATA); 11467 break; 11468 case z_mode_ax_reg: 11469 if ((rex & REX_W) || (sizeflag & DFLAG)) 11470 s = *names32; 11471 else 11472 s = *names16; 11473 if (!(rex & REX_W)) 11474 used_prefixes |= (prefixes & PREFIX_DATA); 11475 break; 11476 default: 11477 s = INTERNAL_DISASSEMBLER_ERROR; 11478 break; 11479 } 11480 oappend (s); 11481 } 11482 11483 static void 11484 OP_I (int bytemode, int sizeflag) 11485 { 11486 bfd_signed_vma op; 11487 bfd_signed_vma mask = -1; 11488 11489 switch (bytemode) 11490 { 11491 case b_mode: 11492 FETCH_DATA (the_info, codep + 1); 11493 op = *codep++; 11494 mask = 0xff; 11495 break; 11496 case q_mode: 11497 if (address_mode == mode_64bit) 11498 { 11499 op = get32s (); 11500 break; 11501 } 11502 /* Fall through. */ 11503 case v_mode: 11504 USED_REX (REX_W); 11505 if (rex & REX_W) 11506 op = get32s (); 11507 else if (sizeflag & DFLAG) 11508 { 11509 op = get32 (); 11510 mask = 0xffffffff; 11511 } 11512 else 11513 { 11514 op = get16 (); 11515 mask = 0xfffff; 11516 } 11517 used_prefixes |= (prefixes & PREFIX_DATA); 11518 break; 11519 case w_mode: 11520 mask = 0xfffff; 11521 op = get16 (); 11522 break; 11523 case const_1_mode: 11524 if (intel_syntax) 11525 oappend ("1"); 11526 return; 11527 default: 11528 oappend (INTERNAL_DISASSEMBLER_ERROR); 11529 return; 11530 } 11531 11532 op &= mask; 11533 scratchbuf[0] = '$'; 11534 print_operand_value (scratchbuf + 1, 1, op); 11535 oappend (scratchbuf + intel_syntax); 11536 scratchbuf[0] = '\0'; 11537 } 11538 11539 static void 11540 OP_I64 (int bytemode, int sizeflag) 11541 { 11542 bfd_signed_vma op; 11543 bfd_signed_vma mask = -1; 11544 11545 if (address_mode != mode_64bit) 11546 { 11547 OP_I (bytemode, sizeflag); 11548 return; 11549 } 11550 11551 switch (bytemode) 11552 { 11553 case b_mode: 11554 FETCH_DATA (the_info, codep + 1); 11555 op = *codep++; 11556 mask = 0xff; 11557 break; 11558 case v_mode: 11559 USED_REX (REX_W); 11560 if (rex & REX_W) 11561 op = get64 (); 11562 else if (sizeflag & DFLAG) 11563 { 11564 op = get32 (); 11565 mask = 0xffffffff; 11566 } 11567 else 11568 { 11569 op = get16 (); 11570 mask = 0xfffff; 11571 } 11572 used_prefixes |= (prefixes & PREFIX_DATA); 11573 break; 11574 case w_mode: 11575 mask = 0xfffff; 11576 op = get16 (); 11577 break; 11578 default: 11579 oappend (INTERNAL_DISASSEMBLER_ERROR); 11580 return; 11581 } 11582 11583 op &= mask; 11584 scratchbuf[0] = '$'; 11585 print_operand_value (scratchbuf + 1, 1, op); 11586 oappend (scratchbuf + intel_syntax); 11587 scratchbuf[0] = '\0'; 11588 } 11589 11590 static void 11591 OP_sI (int bytemode, int sizeflag) 11592 { 11593 bfd_signed_vma op; 11594 bfd_signed_vma mask = -1; 11595 11596 switch (bytemode) 11597 { 11598 case b_mode: 11599 FETCH_DATA (the_info, codep + 1); 11600 op = *codep++; 11601 if ((op & 0x80) != 0) 11602 op -= 0x100; 11603 mask = 0xffffffff; 11604 break; 11605 case v_mode: 11606 USED_REX (REX_W); 11607 if (rex & REX_W) 11608 op = get32s (); 11609 else if (sizeflag & DFLAG) 11610 { 11611 op = get32s (); 11612 mask = 0xffffffff; 11613 } 11614 else 11615 { 11616 mask = 0xffffffff; 11617 op = get16 (); 11618 if ((op & 0x8000) != 0) 11619 op -= 0x10000; 11620 } 11621 used_prefixes |= (prefixes & PREFIX_DATA); 11622 break; 11623 case w_mode: 11624 op = get16 (); 11625 mask = 0xffffffff; 11626 if ((op & 0x8000) != 0) 11627 op -= 0x10000; 11628 break; 11629 default: 11630 oappend (INTERNAL_DISASSEMBLER_ERROR); 11631 return; 11632 } 11633 11634 scratchbuf[0] = '$'; 11635 print_operand_value (scratchbuf + 1, 1, op); 11636 oappend (scratchbuf + intel_syntax); 11637 } 11638 11639 static void 11640 OP_J (int bytemode, int sizeflag) 11641 { 11642 bfd_vma disp; 11643 bfd_vma mask = -1; 11644 bfd_vma segment = 0; 11645 11646 switch (bytemode) 11647 { 11648 case b_mode: 11649 FETCH_DATA (the_info, codep + 1); 11650 disp = *codep++; 11651 if ((disp & 0x80) != 0) 11652 disp -= 0x100; 11653 break; 11654 case v_mode: 11655 if ((sizeflag & DFLAG) || (rex & REX_W)) 11656 disp = get32s (); 11657 else 11658 { 11659 disp = get16 (); 11660 if ((disp & 0x8000) != 0) 11661 disp -= 0x10000; 11662 /* In 16bit mode, address is wrapped around at 64k within 11663 the same segment. Otherwise, a data16 prefix on a jump 11664 instruction means that the pc is masked to 16 bits after 11665 the displacement is added! */ 11666 mask = 0xffff; 11667 if ((prefixes & PREFIX_DATA) == 0) 11668 segment = ((start_pc + codep - start_codep) 11669 & ~((bfd_vma) 0xffff)); 11670 } 11671 used_prefixes |= (prefixes & PREFIX_DATA); 11672 break; 11673 default: 11674 oappend (INTERNAL_DISASSEMBLER_ERROR); 11675 return; 11676 } 11677 disp = ((start_pc + codep - start_codep + disp) & mask) | segment; 11678 set_op (disp, 0); 11679 print_operand_value (scratchbuf, 1, disp); 11680 oappend (scratchbuf); 11681 } 11682 11683 static void 11684 OP_SEG (int bytemode, int sizeflag) 11685 { 11686 if (bytemode == w_mode) 11687 oappend (names_seg[modrm.reg]); 11688 else 11689 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); 11690 } 11691 11692 static void 11693 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) 11694 { 11695 int seg, offset; 11696 11697 if (sizeflag & DFLAG) 11698 { 11699 offset = get32 (); 11700 seg = get16 (); 11701 } 11702 else 11703 { 11704 offset = get16 (); 11705 seg = get16 (); 11706 } 11707 used_prefixes |= (prefixes & PREFIX_DATA); 11708 if (intel_syntax) 11709 sprintf (scratchbuf, "0x%x:0x%x", seg, offset); 11710 else 11711 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); 11712 oappend (scratchbuf); 11713 } 11714 11715 static void 11716 OP_OFF (int bytemode, int sizeflag) 11717 { 11718 bfd_vma off; 11719 11720 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 11721 intel_operand_size (bytemode, sizeflag); 11722 append_seg (); 11723 11724 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 11725 off = get32 (); 11726 else 11727 off = get16 (); 11728 11729 if (intel_syntax) 11730 { 11731 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS 11732 | PREFIX_ES | PREFIX_FS | PREFIX_GS))) 11733 { 11734 oappend (names_seg[ds_reg - es_reg]); 11735 oappend (":"); 11736 } 11737 } 11738 print_operand_value (scratchbuf, 1, off); 11739 oappend (scratchbuf); 11740 } 11741 11742 static void 11743 OP_OFF64 (int bytemode, int sizeflag) 11744 { 11745 bfd_vma off; 11746 11747 if (address_mode != mode_64bit 11748 || (prefixes & PREFIX_ADDR)) 11749 { 11750 OP_OFF (bytemode, sizeflag); 11751 return; 11752 } 11753 11754 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 11755 intel_operand_size (bytemode, sizeflag); 11756 append_seg (); 11757 11758 off = get64 (); 11759 11760 if (intel_syntax) 11761 { 11762 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS 11763 | PREFIX_ES | PREFIX_FS | PREFIX_GS))) 11764 { 11765 oappend (names_seg[ds_reg - es_reg]); 11766 oappend (":"); 11767 } 11768 } 11769 print_operand_value (scratchbuf, 1, off); 11770 oappend (scratchbuf); 11771 } 11772 11773 static void 11774 ptr_reg (int code, int sizeflag) 11775 { 11776 const char *s; 11777 11778 *obufp++ = open_char; 11779 used_prefixes |= (prefixes & PREFIX_ADDR); 11780 if (address_mode == mode_64bit) 11781 { 11782 if (!(sizeflag & AFLAG)) 11783 s = names32[code - eAX_reg]; 11784 else 11785 s = names64[code - eAX_reg]; 11786 } 11787 else if (sizeflag & AFLAG) 11788 s = names32[code - eAX_reg]; 11789 else 11790 s = names16[code - eAX_reg]; 11791 oappend (s); 11792 *obufp++ = close_char; 11793 *obufp = 0; 11794 } 11795 11796 static void 11797 OP_ESreg (int code, int sizeflag) 11798 { 11799 if (intel_syntax) 11800 { 11801 switch (codep[-1]) 11802 { 11803 case 0x6d: /* insw/insl */ 11804 intel_operand_size (z_mode, sizeflag); 11805 break; 11806 case 0xa5: /* movsw/movsl/movsq */ 11807 case 0xa7: /* cmpsw/cmpsl/cmpsq */ 11808 case 0xab: /* stosw/stosl */ 11809 case 0xaf: /* scasw/scasl */ 11810 intel_operand_size (v_mode, sizeflag); 11811 break; 11812 default: 11813 intel_operand_size (b_mode, sizeflag); 11814 } 11815 } 11816 oappend ("%es:" + intel_syntax); 11817 ptr_reg (code, sizeflag); 11818 } 11819 11820 static void 11821 OP_DSreg (int code, int sizeflag) 11822 { 11823 if (intel_syntax) 11824 { 11825 switch (codep[-1]) 11826 { 11827 case 0x6f: /* outsw/outsl */ 11828 intel_operand_size (z_mode, sizeflag); 11829 break; 11830 case 0xa5: /* movsw/movsl/movsq */ 11831 case 0xa7: /* cmpsw/cmpsl/cmpsq */ 11832 case 0xad: /* lodsw/lodsl/lodsq */ 11833 intel_operand_size (v_mode, sizeflag); 11834 break; 11835 default: 11836 intel_operand_size (b_mode, sizeflag); 11837 } 11838 } 11839 if ((prefixes 11840 & (PREFIX_CS 11841 | PREFIX_DS 11842 | PREFIX_SS 11843 | PREFIX_ES 11844 | PREFIX_FS 11845 | PREFIX_GS)) == 0) 11846 prefixes |= PREFIX_DS; 11847 append_seg (); 11848 ptr_reg (code, sizeflag); 11849 } 11850 11851 static void 11852 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 11853 { 11854 int add; 11855 if (rex & REX_R) 11856 { 11857 USED_REX (REX_R); 11858 add = 8; 11859 } 11860 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) 11861 { 11862 lock_prefix = NULL; 11863 used_prefixes |= PREFIX_LOCK; 11864 add = 8; 11865 } 11866 else 11867 add = 0; 11868 sprintf (scratchbuf, "%%cr%d", modrm.reg + add); 11869 oappend (scratchbuf + intel_syntax); 11870 } 11871 11872 static void 11873 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 11874 { 11875 int add; 11876 USED_REX (REX_R); 11877 if (rex & REX_R) 11878 add = 8; 11879 else 11880 add = 0; 11881 if (intel_syntax) 11882 sprintf (scratchbuf, "db%d", modrm.reg + add); 11883 else 11884 sprintf (scratchbuf, "%%db%d", modrm.reg + add); 11885 oappend (scratchbuf); 11886 } 11887 11888 static void 11889 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 11890 { 11891 sprintf (scratchbuf, "%%tr%d", modrm.reg); 11892 oappend (scratchbuf + intel_syntax); 11893 } 11894 11895 static void 11896 OP_R (int bytemode, int sizeflag) 11897 { 11898 if (modrm.mod == 3) 11899 OP_E (bytemode, sizeflag); 11900 else 11901 BadOp (); 11902 } 11903 11904 static void 11905 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 11906 { 11907 used_prefixes |= (prefixes & PREFIX_DATA); 11908 if (prefixes & PREFIX_DATA) 11909 { 11910 int add; 11911 USED_REX (REX_R); 11912 if (rex & REX_R) 11913 add = 8; 11914 else 11915 add = 0; 11916 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); 11917 } 11918 else 11919 sprintf (scratchbuf, "%%mm%d", modrm.reg); 11920 oappend (scratchbuf + intel_syntax); 11921 } 11922 11923 static void 11924 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 11925 { 11926 int add; 11927 USED_REX (REX_R); 11928 if (rex & REX_R) 11929 add = 8; 11930 else 11931 add = 0; 11932 if (need_vex && bytemode != xmm_mode) 11933 { 11934 switch (vex.length) 11935 { 11936 case 128: 11937 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); 11938 break; 11939 case 256: 11940 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add); 11941 break; 11942 default: 11943 abort (); 11944 } 11945 } 11946 else 11947 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); 11948 oappend (scratchbuf + intel_syntax); 11949 } 11950 11951 static void 11952 OP_EM (int bytemode, int sizeflag) 11953 { 11954 if (modrm.mod != 3) 11955 { 11956 if (intel_syntax 11957 && (bytemode == v_mode || bytemode == v_swap_mode)) 11958 { 11959 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; 11960 used_prefixes |= (prefixes & PREFIX_DATA); 11961 } 11962 OP_E (bytemode, sizeflag); 11963 return; 11964 } 11965 11966 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) 11967 swap_operand (); 11968 11969 /* Skip mod/rm byte. */ 11970 MODRM_CHECK; 11971 codep++; 11972 used_prefixes |= (prefixes & PREFIX_DATA); 11973 if (prefixes & PREFIX_DATA) 11974 { 11975 int add; 11976 11977 USED_REX (REX_B); 11978 if (rex & REX_B) 11979 add = 8; 11980 else 11981 add = 0; 11982 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); 11983 } 11984 else 11985 sprintf (scratchbuf, "%%mm%d", modrm.rm); 11986 oappend (scratchbuf + intel_syntax); 11987 } 11988 11989 /* cvt* are the only instructions in sse2 which have 11990 both SSE and MMX operands and also have 0x66 prefix 11991 in their opcode. 0x66 was originally used to differentiate 11992 between SSE and MMX instruction(operands). So we have to handle the 11993 cvt* separately using OP_EMC and OP_MXC */ 11994 static void 11995 OP_EMC (int bytemode, int sizeflag) 11996 { 11997 if (modrm.mod != 3) 11998 { 11999 if (intel_syntax && bytemode == v_mode) 12000 { 12001 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; 12002 used_prefixes |= (prefixes & PREFIX_DATA); 12003 } 12004 OP_E (bytemode, sizeflag); 12005 return; 12006 } 12007 12008 /* Skip mod/rm byte. */ 12009 MODRM_CHECK; 12010 codep++; 12011 used_prefixes |= (prefixes & PREFIX_DATA); 12012 sprintf (scratchbuf, "%%mm%d", modrm.rm); 12013 oappend (scratchbuf + intel_syntax); 12014 } 12015 12016 static void 12017 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 12018 { 12019 used_prefixes |= (prefixes & PREFIX_DATA); 12020 sprintf (scratchbuf, "%%mm%d", modrm.reg); 12021 oappend (scratchbuf + intel_syntax); 12022 } 12023 12024 static void 12025 OP_EX (int bytemode, int sizeflag) 12026 { 12027 int add; 12028 12029 /* Skip mod/rm byte. */ 12030 MODRM_CHECK; 12031 codep++; 12032 12033 if (modrm.mod != 3) 12034 { 12035 OP_E_memory (bytemode, sizeflag); 12036 return; 12037 } 12038 12039 USED_REX (REX_B); 12040 if (rex & REX_B) 12041 add = 8; 12042 else 12043 add = 0; 12044 12045 if ((sizeflag & SUFFIX_ALWAYS) 12046 && (bytemode == x_swap_mode 12047 || bytemode == d_swap_mode 12048 || bytemode == q_swap_mode)) 12049 swap_operand (); 12050 12051 if (need_vex 12052 && bytemode != xmm_mode 12053 && bytemode != xmmq_mode) 12054 { 12055 switch (vex.length) 12056 { 12057 case 128: 12058 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); 12059 break; 12060 case 256: 12061 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add); 12062 break; 12063 default: 12064 abort (); 12065 } 12066 } 12067 else 12068 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); 12069 oappend (scratchbuf + intel_syntax); 12070 } 12071 12072 static void 12073 OP_MS (int bytemode, int sizeflag) 12074 { 12075 if (modrm.mod == 3) 12076 OP_EM (bytemode, sizeflag); 12077 else 12078 BadOp (); 12079 } 12080 12081 static void 12082 OP_XS (int bytemode, int sizeflag) 12083 { 12084 if (modrm.mod == 3) 12085 OP_EX (bytemode, sizeflag); 12086 else 12087 BadOp (); 12088 } 12089 12090 static void 12091 OP_M (int bytemode, int sizeflag) 12092 { 12093 if (modrm.mod == 3) 12094 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ 12095 BadOp (); 12096 else 12097 OP_E (bytemode, sizeflag); 12098 } 12099 12100 static void 12101 OP_0f07 (int bytemode, int sizeflag) 12102 { 12103 if (modrm.mod != 3 || modrm.rm != 0) 12104 BadOp (); 12105 else 12106 OP_E (bytemode, sizeflag); 12107 } 12108 12109 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in 12110 32bit mode and "xchg %rax,%rax" in 64bit mode. */ 12111 12112 static void 12113 NOP_Fixup1 (int bytemode, int sizeflag) 12114 { 12115 if ((prefixes & PREFIX_DATA) != 0 12116 || (rex != 0 12117 && rex != 0x48 12118 && address_mode == mode_64bit)) 12119 OP_REG (bytemode, sizeflag); 12120 else 12121 strcpy (obuf, "nop"); 12122 } 12123 12124 static void 12125 NOP_Fixup2 (int bytemode, int sizeflag) 12126 { 12127 if ((prefixes & PREFIX_DATA) != 0 12128 || (rex != 0 12129 && rex != 0x48 12130 && address_mode == mode_64bit)) 12131 OP_IMREG (bytemode, sizeflag); 12132 } 12133 12134 static const char *const Suffix3DNow[] = { 12135 /* 00 */ NULL, NULL, NULL, NULL, 12136 /* 04 */ NULL, NULL, NULL, NULL, 12137 /* 08 */ NULL, NULL, NULL, NULL, 12138 /* 0C */ "pi2fw", "pi2fd", NULL, NULL, 12139 /* 10 */ NULL, NULL, NULL, NULL, 12140 /* 14 */ NULL, NULL, NULL, NULL, 12141 /* 18 */ NULL, NULL, NULL, NULL, 12142 /* 1C */ "pf2iw", "pf2id", NULL, NULL, 12143 /* 20 */ NULL, NULL, NULL, NULL, 12144 /* 24 */ NULL, NULL, NULL, NULL, 12145 /* 28 */ NULL, NULL, NULL, NULL, 12146 /* 2C */ NULL, NULL, NULL, NULL, 12147 /* 30 */ NULL, NULL, NULL, NULL, 12148 /* 34 */ NULL, NULL, NULL, NULL, 12149 /* 38 */ NULL, NULL, NULL, NULL, 12150 /* 3C */ NULL, NULL, NULL, NULL, 12151 /* 40 */ NULL, NULL, NULL, NULL, 12152 /* 44 */ NULL, NULL, NULL, NULL, 12153 /* 48 */ NULL, NULL, NULL, NULL, 12154 /* 4C */ NULL, NULL, NULL, NULL, 12155 /* 50 */ NULL, NULL, NULL, NULL, 12156 /* 54 */ NULL, NULL, NULL, NULL, 12157 /* 58 */ NULL, NULL, NULL, NULL, 12158 /* 5C */ NULL, NULL, NULL, NULL, 12159 /* 60 */ NULL, NULL, NULL, NULL, 12160 /* 64 */ NULL, NULL, NULL, NULL, 12161 /* 68 */ NULL, NULL, NULL, NULL, 12162 /* 6C */ NULL, NULL, NULL, NULL, 12163 /* 70 */ NULL, NULL, NULL, NULL, 12164 /* 74 */ NULL, NULL, NULL, NULL, 12165 /* 78 */ NULL, NULL, NULL, NULL, 12166 /* 7C */ NULL, NULL, NULL, NULL, 12167 /* 80 */ NULL, NULL, NULL, NULL, 12168 /* 84 */ NULL, NULL, NULL, NULL, 12169 /* 88 */ NULL, NULL, "pfnacc", NULL, 12170 /* 8C */ NULL, NULL, "pfpnacc", NULL, 12171 /* 90 */ "pfcmpge", NULL, NULL, NULL, 12172 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", 12173 /* 98 */ NULL, NULL, "pfsub", NULL, 12174 /* 9C */ NULL, NULL, "pfadd", NULL, 12175 /* A0 */ "pfcmpgt", NULL, NULL, NULL, 12176 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", 12177 /* A8 */ NULL, NULL, "pfsubr", NULL, 12178 /* AC */ NULL, NULL, "pfacc", NULL, 12179 /* B0 */ "pfcmpeq", NULL, NULL, NULL, 12180 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", 12181 /* B8 */ NULL, NULL, NULL, "pswapd", 12182 /* BC */ NULL, NULL, NULL, "pavgusb", 12183 /* C0 */ NULL, NULL, NULL, NULL, 12184 /* C4 */ NULL, NULL, NULL, NULL, 12185 /* C8 */ NULL, NULL, NULL, NULL, 12186 /* CC */ NULL, NULL, NULL, NULL, 12187 /* D0 */ NULL, NULL, NULL, NULL, 12188 /* D4 */ NULL, NULL, NULL, NULL, 12189 /* D8 */ NULL, NULL, NULL, NULL, 12190 /* DC */ NULL, NULL, NULL, NULL, 12191 /* E0 */ NULL, NULL, NULL, NULL, 12192 /* E4 */ NULL, NULL, NULL, NULL, 12193 /* E8 */ NULL, NULL, NULL, NULL, 12194 /* EC */ NULL, NULL, NULL, NULL, 12195 /* F0 */ NULL, NULL, NULL, NULL, 12196 /* F4 */ NULL, NULL, NULL, NULL, 12197 /* F8 */ NULL, NULL, NULL, NULL, 12198 /* FC */ NULL, NULL, NULL, NULL, 12199 }; 12200 12201 static void 12202 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 12203 { 12204 const char *mnemonic; 12205 12206 FETCH_DATA (the_info, codep + 1); 12207 /* AMD 3DNow! instructions are specified by an opcode suffix in the 12208 place where an 8-bit immediate would normally go. ie. the last 12209 byte of the instruction. */ 12210 obufp = mnemonicendp; 12211 mnemonic = Suffix3DNow[*codep++ & 0xff]; 12212 if (mnemonic) 12213 oappend (mnemonic); 12214 else 12215 { 12216 /* Since a variable sized modrm/sib chunk is between the start 12217 of the opcode (0x0f0f) and the opcode suffix, we need to do 12218 all the modrm processing first, and don't know until now that 12219 we have a bad opcode. This necessitates some cleaning up. */ 12220 op_out[0][0] = '\0'; 12221 op_out[1][0] = '\0'; 12222 BadOp (); 12223 } 12224 mnemonicendp = obufp; 12225 } 12226 12227 static struct op simd_cmp_op[] = 12228 { 12229 { STRING_COMMA_LEN ("eq") }, 12230 { STRING_COMMA_LEN ("lt") }, 12231 { STRING_COMMA_LEN ("le") }, 12232 { STRING_COMMA_LEN ("unord") }, 12233 { STRING_COMMA_LEN ("neq") }, 12234 { STRING_COMMA_LEN ("nlt") }, 12235 { STRING_COMMA_LEN ("nle") }, 12236 { STRING_COMMA_LEN ("ord") } 12237 }; 12238 12239 static void 12240 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 12241 { 12242 unsigned int cmp_type; 12243 12244 FETCH_DATA (the_info, codep + 1); 12245 cmp_type = *codep++ & 0xff; 12246 if (cmp_type < ARRAY_SIZE (simd_cmp_op)) 12247 { 12248 char suffix [3]; 12249 char *p = mnemonicendp - 2; 12250 suffix[0] = p[0]; 12251 suffix[1] = p[1]; 12252 suffix[2] = '\0'; 12253 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); 12254 mnemonicendp += simd_cmp_op[cmp_type].len; 12255 } 12256 else 12257 { 12258 /* We have a reserved extension byte. Output it directly. */ 12259 scratchbuf[0] = '$'; 12260 print_operand_value (scratchbuf + 1, 1, cmp_type); 12261 oappend (scratchbuf + intel_syntax); 12262 scratchbuf[0] = '\0'; 12263 } 12264 } 12265 12266 static void 12267 OP_Mwait (int bytemode ATTRIBUTE_UNUSED, 12268 int sizeflag ATTRIBUTE_UNUSED) 12269 { 12270 /* mwait %eax,%ecx */ 12271 if (!intel_syntax) 12272 { 12273 const char **names = (address_mode == mode_64bit 12274 ? names64 : names32); 12275 strcpy (op_out[0], names[0]); 12276 strcpy (op_out[1], names[1]); 12277 two_source_ops = 1; 12278 } 12279 /* Skip mod/rm byte. */ 12280 MODRM_CHECK; 12281 codep++; 12282 } 12283 12284 static void 12285 OP_Monitor (int bytemode ATTRIBUTE_UNUSED, 12286 int sizeflag ATTRIBUTE_UNUSED) 12287 { 12288 /* monitor %eax,%ecx,%edx" */ 12289 if (!intel_syntax) 12290 { 12291 const char **op1_names; 12292 const char **names = (address_mode == mode_64bit 12293 ? names64 : names32); 12294 12295 if (!(prefixes & PREFIX_ADDR)) 12296 op1_names = (address_mode == mode_16bit 12297 ? names16 : names); 12298 else 12299 { 12300 /* Remove "addr16/addr32". */ 12301 addr_prefix = NULL; 12302 op1_names = (address_mode != mode_32bit 12303 ? names32 : names16); 12304 used_prefixes |= PREFIX_ADDR; 12305 } 12306 strcpy (op_out[0], op1_names[0]); 12307 strcpy (op_out[1], names[1]); 12308 strcpy (op_out[2], names[2]); 12309 two_source_ops = 1; 12310 } 12311 /* Skip mod/rm byte. */ 12312 MODRM_CHECK; 12313 codep++; 12314 } 12315 12316 static void 12317 BadOp (void) 12318 { 12319 /* Throw away prefixes and 1st. opcode byte. */ 12320 codep = insn_codep + 1; 12321 oappend ("(bad)"); 12322 } 12323 12324 static void 12325 REP_Fixup (int bytemode, int sizeflag) 12326 { 12327 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, 12328 lods and stos. */ 12329 if (prefixes & PREFIX_REPZ) 12330 repz_prefix = "rep "; 12331 12332 switch (bytemode) 12333 { 12334 case al_reg: 12335 case eAX_reg: 12336 case indir_dx_reg: 12337 OP_IMREG (bytemode, sizeflag); 12338 break; 12339 case eDI_reg: 12340 OP_ESreg (bytemode, sizeflag); 12341 break; 12342 case eSI_reg: 12343 OP_DSreg (bytemode, sizeflag); 12344 break; 12345 default: 12346 abort (); 12347 break; 12348 } 12349 } 12350 12351 static void 12352 CMPXCHG8B_Fixup (int bytemode, int sizeflag) 12353 { 12354 USED_REX (REX_W); 12355 if (rex & REX_W) 12356 { 12357 /* Change cmpxchg8b to cmpxchg16b. */ 12358 char *p = mnemonicendp - 2; 12359 mnemonicendp = stpcpy (p, "16b"); 12360 bytemode = o_mode; 12361 } 12362 OP_M (bytemode, sizeflag); 12363 } 12364 12365 static void 12366 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) 12367 { 12368 if (need_vex) 12369 { 12370 switch (vex.length) 12371 { 12372 case 128: 12373 sprintf (scratchbuf, "%%xmm%d", reg); 12374 break; 12375 case 256: 12376 sprintf (scratchbuf, "%%ymm%d", reg); 12377 break; 12378 default: 12379 abort (); 12380 } 12381 } 12382 else 12383 sprintf (scratchbuf, "%%xmm%d", reg); 12384 oappend (scratchbuf + intel_syntax); 12385 } 12386 12387 static void 12388 CRC32_Fixup (int bytemode, int sizeflag) 12389 { 12390 /* Add proper suffix to "crc32". */ 12391 char *p = mnemonicendp; 12392 12393 switch (bytemode) 12394 { 12395 case b_mode: 12396 if (intel_syntax) 12397 goto skip; 12398 12399 *p++ = 'b'; 12400 break; 12401 case v_mode: 12402 if (intel_syntax) 12403 goto skip; 12404 12405 USED_REX (REX_W); 12406 if (rex & REX_W) 12407 *p++ = 'q'; 12408 else if (sizeflag & DFLAG) 12409 *p++ = 'l'; 12410 else 12411 *p++ = 'w'; 12412 used_prefixes |= (prefixes & PREFIX_DATA); 12413 break; 12414 default: 12415 oappend (INTERNAL_DISASSEMBLER_ERROR); 12416 break; 12417 } 12418 mnemonicendp = p; 12419 *p = '\0'; 12420 12421 skip: 12422 if (modrm.mod == 3) 12423 { 12424 int add; 12425 12426 /* Skip mod/rm byte. */ 12427 MODRM_CHECK; 12428 codep++; 12429 12430 USED_REX (REX_B); 12431 add = (rex & REX_B) ? 8 : 0; 12432 if (bytemode == b_mode) 12433 { 12434 USED_REX (0); 12435 if (rex) 12436 oappend (names8rex[modrm.rm + add]); 12437 else 12438 oappend (names8[modrm.rm + add]); 12439 } 12440 else 12441 { 12442 USED_REX (REX_W); 12443 if (rex & REX_W) 12444 oappend (names64[modrm.rm + add]); 12445 else if ((prefixes & PREFIX_DATA)) 12446 oappend (names16[modrm.rm + add]); 12447 else 12448 oappend (names32[modrm.rm + add]); 12449 } 12450 } 12451 else 12452 OP_E (bytemode, sizeflag); 12453 } 12454 12455 /* Display the destination register operand for instructions with 12456 VEX. */ 12457 12458 static void 12459 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 12460 { 12461 if (!need_vex) 12462 abort (); 12463 12464 if (!need_vex_reg) 12465 return; 12466 12467 switch (vex.length) 12468 { 12469 case 128: 12470 switch (bytemode) 12471 { 12472 case vex_mode: 12473 case vex128_mode: 12474 break; 12475 default: 12476 abort (); 12477 return; 12478 } 12479 12480 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier); 12481 break; 12482 case 256: 12483 switch (bytemode) 12484 { 12485 case vex_mode: 12486 case vex256_mode: 12487 break; 12488 default: 12489 abort (); 12490 return; 12491 } 12492 12493 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier); 12494 break; 12495 default: 12496 abort (); 12497 break; 12498 } 12499 oappend (scratchbuf + intel_syntax); 12500 } 12501 12502 /* Get the VEX immediate byte without moving codep. */ 12503 12504 static unsigned char 12505 get_vex_imm8 (int sizeflag) 12506 { 12507 int bytes_before_imm = 0; 12508 12509 /* Skip mod/rm byte. */ 12510 MODRM_CHECK; 12511 codep++; 12512 12513 if (modrm.mod != 3) 12514 { 12515 /* There are SIB/displacement bytes. */ 12516 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 12517 { 12518 /* 32/64 bit address mode */ 12519 int base = modrm.rm; 12520 12521 /* Check SIB byte. */ 12522 if (base == 4) 12523 { 12524 FETCH_DATA (the_info, codep + 1); 12525 base = *codep & 7; 12526 bytes_before_imm++; 12527 } 12528 12529 switch (modrm.mod) 12530 { 12531 case 0: 12532 /* When modrm.rm == 5 or modrm.rm == 4 and base in 12533 SIB == 5, there is a 4 byte displacement. */ 12534 if (base != 5) 12535 /* No displacement. */ 12536 break; 12537 case 2: 12538 /* 4 byte displacement. */ 12539 bytes_before_imm += 4; 12540 break; 12541 case 1: 12542 /* 1 byte displacement. */ 12543 bytes_before_imm++; 12544 break; 12545 } 12546 } 12547 else 12548 { /* 16 bit address mode */ 12549 switch (modrm.mod) 12550 { 12551 case 0: 12552 /* When modrm.rm == 6, there is a 2 byte displacement. */ 12553 if (modrm.rm != 6) 12554 /* No displacement. */ 12555 break; 12556 case 2: 12557 /* 2 byte displacement. */ 12558 bytes_before_imm += 2; 12559 break; 12560 case 1: 12561 /* 1 byte displacement. */ 12562 bytes_before_imm++; 12563 break; 12564 } 12565 } 12566 } 12567 12568 FETCH_DATA (the_info, codep + bytes_before_imm + 1); 12569 return codep [bytes_before_imm]; 12570 } 12571 12572 static void 12573 OP_EX_VexReg (int bytemode, int sizeflag, int reg) 12574 { 12575 if (reg == -1 && modrm.mod != 3) 12576 { 12577 OP_E_memory (bytemode, sizeflag); 12578 return; 12579 } 12580 else 12581 { 12582 if (reg == -1) 12583 { 12584 reg = modrm.rm; 12585 USED_REX (REX_B); 12586 if (rex & REX_B) 12587 reg += 8; 12588 } 12589 else if (reg > 7 && address_mode != mode_64bit) 12590 BadOp (); 12591 } 12592 12593 switch (vex.length) 12594 { 12595 case 128: 12596 sprintf (scratchbuf, "%%xmm%d", reg); 12597 break; 12598 case 256: 12599 sprintf (scratchbuf, "%%ymm%d", reg); 12600 break; 12601 default: 12602 abort (); 12603 } 12604 oappend (scratchbuf + intel_syntax); 12605 } 12606 12607 static void 12608 OP_EX_VexW (int bytemode, int sizeflag) 12609 { 12610 int reg = -1; 12611 12612 if (!vex_w_done) 12613 { 12614 vex_w_done = 1; 12615 if (vex.w) 12616 reg = vex.register_specifier; 12617 } 12618 else 12619 { 12620 if (!vex.w) 12621 reg = vex.register_specifier; 12622 } 12623 12624 OP_EX_VexReg (bytemode, sizeflag, reg); 12625 } 12626 12627 static void 12628 OP_VEX_FMA (int bytemode, int sizeflag) 12629 { 12630 int reg = get_vex_imm8 (sizeflag) >> 4; 12631 12632 if (reg > 7 && address_mode != mode_64bit) 12633 BadOp (); 12634 12635 switch (vex.length) 12636 { 12637 case 128: 12638 switch (bytemode) 12639 { 12640 case vex_mode: 12641 case vex128_mode: 12642 break; 12643 default: 12644 abort (); 12645 return; 12646 } 12647 12648 sprintf (scratchbuf, "%%xmm%d", reg); 12649 break; 12650 case 256: 12651 switch (bytemode) 12652 { 12653 case vex_mode: 12654 break; 12655 default: 12656 abort (); 12657 return; 12658 } 12659 12660 sprintf (scratchbuf, "%%ymm%d", reg); 12661 break; 12662 default: 12663 abort (); 12664 } 12665 oappend (scratchbuf + intel_syntax); 12666 } 12667 12668 static void 12669 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, 12670 int sizeflag ATTRIBUTE_UNUSED) 12671 { 12672 /* Skip the immediate byte and check for invalid bits. */ 12673 FETCH_DATA (the_info, codep + 1); 12674 if (*codep++ & 0xf) 12675 BadOp (); 12676 } 12677 12678 static void 12679 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 12680 { 12681 int reg; 12682 FETCH_DATA (the_info, codep + 1); 12683 reg = *codep++; 12684 12685 if (bytemode != x_mode) 12686 abort (); 12687 12688 if (reg & 0xf) 12689 BadOp (); 12690 12691 reg >>= 4; 12692 if (reg > 7 && address_mode != mode_64bit) 12693 BadOp (); 12694 12695 switch (vex.length) 12696 { 12697 case 128: 12698 sprintf (scratchbuf, "%%xmm%d", reg); 12699 break; 12700 case 256: 12701 sprintf (scratchbuf, "%%ymm%d", reg); 12702 break; 12703 default: 12704 abort (); 12705 } 12706 oappend (scratchbuf + intel_syntax); 12707 } 12708 12709 static void 12710 OP_XMM_VexW (int bytemode, int sizeflag) 12711 { 12712 /* Turn off the REX.W bit since it is used for swapping operands 12713 now. */ 12714 rex &= ~REX_W; 12715 OP_XMM (bytemode, sizeflag); 12716 } 12717 12718 static void 12719 OP_EX_Vex (int bytemode, int sizeflag) 12720 { 12721 if (modrm.mod != 3) 12722 { 12723 if (vex.register_specifier != 0) 12724 BadOp (); 12725 need_vex_reg = 0; 12726 } 12727 OP_EX (bytemode, sizeflag); 12728 } 12729 12730 static void 12731 OP_XMM_Vex (int bytemode, int sizeflag) 12732 { 12733 if (modrm.mod != 3) 12734 { 12735 if (vex.register_specifier != 0) 12736 BadOp (); 12737 need_vex_reg = 0; 12738 } 12739 OP_XMM (bytemode, sizeflag); 12740 } 12741 12742 static void 12743 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 12744 { 12745 switch (vex.length) 12746 { 12747 case 128: 12748 mnemonicendp = stpcpy (obuf, "vzeroupper"); 12749 break; 12750 case 256: 12751 mnemonicendp = stpcpy (obuf, "vzeroall"); 12752 break; 12753 default: 12754 abort (); 12755 } 12756 } 12757 12758 static struct op vex_cmp_op[] = 12759 { 12760 { STRING_COMMA_LEN ("eq") }, 12761 { STRING_COMMA_LEN ("lt") }, 12762 { STRING_COMMA_LEN ("le") }, 12763 { STRING_COMMA_LEN ("unord") }, 12764 { STRING_COMMA_LEN ("neq") }, 12765 { STRING_COMMA_LEN ("nlt") }, 12766 { STRING_COMMA_LEN ("nle") }, 12767 { STRING_COMMA_LEN ("ord") }, 12768 { STRING_COMMA_LEN ("eq_uq") }, 12769 { STRING_COMMA_LEN ("nge") }, 12770 { STRING_COMMA_LEN ("ngt") }, 12771 { STRING_COMMA_LEN ("false") }, 12772 { STRING_COMMA_LEN ("neq_oq") }, 12773 { STRING_COMMA_LEN ("ge") }, 12774 { STRING_COMMA_LEN ("gt") }, 12775 { STRING_COMMA_LEN ("true") }, 12776 { STRING_COMMA_LEN ("eq_os") }, 12777 { STRING_COMMA_LEN ("lt_oq") }, 12778 { STRING_COMMA_LEN ("le_oq") }, 12779 { STRING_COMMA_LEN ("unord_s") }, 12780 { STRING_COMMA_LEN ("neq_us") }, 12781 { STRING_COMMA_LEN ("nlt_uq") }, 12782 { STRING_COMMA_LEN ("nle_uq") }, 12783 { STRING_COMMA_LEN ("ord_s") }, 12784 { STRING_COMMA_LEN ("eq_us") }, 12785 { STRING_COMMA_LEN ("nge_uq") }, 12786 { STRING_COMMA_LEN ("ngt_uq") }, 12787 { STRING_COMMA_LEN ("false_os") }, 12788 { STRING_COMMA_LEN ("neq_os") }, 12789 { STRING_COMMA_LEN ("ge_oq") }, 12790 { STRING_COMMA_LEN ("gt_oq") }, 12791 { STRING_COMMA_LEN ("true_us") }, 12792 }; 12793 12794 static void 12795 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 12796 { 12797 unsigned int cmp_type; 12798 12799 FETCH_DATA (the_info, codep + 1); 12800 cmp_type = *codep++ & 0xff; 12801 if (cmp_type < ARRAY_SIZE (vex_cmp_op)) 12802 { 12803 char suffix [3]; 12804 char *p = mnemonicendp - 2; 12805 suffix[0] = p[0]; 12806 suffix[1] = p[1]; 12807 suffix[2] = '\0'; 12808 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); 12809 mnemonicendp += vex_cmp_op[cmp_type].len; 12810 } 12811 else 12812 { 12813 /* We have a reserved extension byte. Output it directly. */ 12814 scratchbuf[0] = '$'; 12815 print_operand_value (scratchbuf + 1, 1, cmp_type); 12816 oappend (scratchbuf + intel_syntax); 12817 scratchbuf[0] = '\0'; 12818 } 12819 } 12820 12821 static const struct op pclmul_op[] = 12822 { 12823 { STRING_COMMA_LEN ("lql") }, 12824 { STRING_COMMA_LEN ("hql") }, 12825 { STRING_COMMA_LEN ("lqh") }, 12826 { STRING_COMMA_LEN ("hqh") } 12827 }; 12828 12829 static void 12830 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, 12831 int sizeflag ATTRIBUTE_UNUSED) 12832 { 12833 unsigned int pclmul_type; 12834 12835 FETCH_DATA (the_info, codep + 1); 12836 pclmul_type = *codep++ & 0xff; 12837 switch (pclmul_type) 12838 { 12839 case 0x10: 12840 pclmul_type = 2; 12841 break; 12842 case 0x11: 12843 pclmul_type = 3; 12844 break; 12845 default: 12846 break; 12847 } 12848 if (pclmul_type < ARRAY_SIZE (pclmul_op)) 12849 { 12850 char suffix [4]; 12851 char *p = mnemonicendp - 3; 12852 suffix[0] = p[0]; 12853 suffix[1] = p[1]; 12854 suffix[2] = p[2]; 12855 suffix[3] = '\0'; 12856 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); 12857 mnemonicendp += pclmul_op[pclmul_type].len; 12858 } 12859 else 12860 { 12861 /* We have a reserved extension byte. Output it directly. */ 12862 scratchbuf[0] = '$'; 12863 print_operand_value (scratchbuf + 1, 1, pclmul_type); 12864 oappend (scratchbuf + intel_syntax); 12865 scratchbuf[0] = '\0'; 12866 } 12867 } 12868 12869 static void 12870 MOVBE_Fixup (int bytemode, int sizeflag) 12871 { 12872 /* Add proper suffix to "movbe". */ 12873 char *p = mnemonicendp; 12874 12875 switch (bytemode) 12876 { 12877 case v_mode: 12878 if (intel_syntax) 12879 goto skip; 12880 12881 USED_REX (REX_W); 12882 if (sizeflag & SUFFIX_ALWAYS) 12883 { 12884 if (rex & REX_W) 12885 *p++ = 'q'; 12886 else if (sizeflag & DFLAG) 12887 *p++ = 'l'; 12888 else 12889 *p++ = 'w'; 12890 } 12891 used_prefixes |= (prefixes & PREFIX_DATA); 12892 break; 12893 default: 12894 oappend (INTERNAL_DISASSEMBLER_ERROR); 12895 break; 12896 } 12897 mnemonicendp = p; 12898 *p = '\0'; 12899 12900 skip: 12901 OP_M (bytemode, sizeflag); 12902 } 12903