1 /* Print i386 instructions for GDB, the GNU debugger. 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 4 Free Software Foundation, Inc. 5 6 This file is part of the GNU opcodes library. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) 25 July 1988 26 modified by John Hassey (hassey@dg-rtp.dg.com) 27 x86-64 support added by Jan Hubicka (jh@suse.cz) 28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ 29 30 /* The main tables describing the instructions is essentially a copy 31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386 32 Programmers Manual. Usually, there is a capital letter, followed 33 by a small letter. The capital letter tell the addressing mode, 34 and the small letter tells about the operand size. Refer to 35 the Intel manual for details. */ 36 37 #include "sysdep.h" 38 #include "dis-asm.h" 39 #include "opintl.h" 40 #include "opcode/i386.h" 41 #include "libiberty.h" 42 43 #include <setjmp.h> 44 45 static int print_insn (bfd_vma, disassemble_info *); 46 static void dofloat (int); 47 static void OP_ST (int, int); 48 static void OP_STi (int, int); 49 static int putop (const char *, int); 50 static void oappend (const char *); 51 static void append_seg (void); 52 static void OP_indirE (int, int); 53 static void print_operand_value (char *, int, bfd_vma); 54 static void OP_E_register (int, int); 55 static void OP_E_memory (int, int); 56 static void print_displacement (char *, bfd_vma); 57 static void OP_E (int, int); 58 static void OP_G (int, int); 59 static bfd_vma get64 (void); 60 static bfd_signed_vma get32 (void); 61 static bfd_signed_vma get32s (void); 62 static int get16 (void); 63 static void set_op (bfd_vma, int); 64 static void OP_Skip_MODRM (int, int); 65 static void OP_REG (int, int); 66 static void OP_IMREG (int, int); 67 static void OP_I (int, int); 68 static void OP_I64 (int, int); 69 static void OP_sI (int, int); 70 static void OP_J (int, int); 71 static void OP_SEG (int, int); 72 static void OP_DIR (int, int); 73 static void OP_OFF (int, int); 74 static void OP_OFF64 (int, int); 75 static void ptr_reg (int, int); 76 static void OP_ESreg (int, int); 77 static void OP_DSreg (int, int); 78 static void OP_C (int, int); 79 static void OP_D (int, int); 80 static void OP_T (int, int); 81 static void OP_R (int, int); 82 static void OP_MMX (int, int); 83 static void OP_XMM (int, int); 84 static void OP_EM (int, int); 85 static void OP_EX (int, int); 86 static void OP_EMC (int,int); 87 static void OP_MXC (int,int); 88 static void OP_MS (int, int); 89 static void OP_XS (int, int); 90 static void OP_M (int, int); 91 static void OP_VEX (int, int); 92 static void OP_EX_Vex (int, int); 93 static void OP_EX_VexW (int, int); 94 static void OP_EX_VexImmW (int, int); 95 static void OP_XMM_Vex (int, int); 96 static void OP_XMM_VexW (int, int); 97 static void OP_REG_VexI4 (int, int); 98 static void PCLMUL_Fixup (int, int); 99 static void VEXI4_Fixup (int, int); 100 static void VZERO_Fixup (int, int); 101 static void VCMP_Fixup (int, int); 102 static void OP_0f07 (int, int); 103 static void OP_Monitor (int, int); 104 static void OP_Mwait (int, int); 105 static void NOP_Fixup1 (int, int); 106 static void NOP_Fixup2 (int, int); 107 static void OP_3DNowSuffix (int, int); 108 static void CMP_Fixup (int, int); 109 static void BadOp (void); 110 static void REP_Fixup (int, int); 111 static void CMPXCHG8B_Fixup (int, int); 112 static void XMM_Fixup (int, int); 113 static void CRC32_Fixup (int, int); 114 static void FXSAVE_Fixup (int, int); 115 static void OP_LWPCB_E (int, int); 116 static void OP_LWP_E (int, int); 117 static void OP_Vex_2src_1 (int, int); 118 static void OP_Vex_2src_2 (int, int); 119 120 static void MOVBE_Fixup (int, int); 121 122 struct dis_private { 123 /* Points to first byte not fetched. */ 124 bfd_byte *max_fetched; 125 bfd_byte the_buffer[MAX_MNEM_SIZE]; 126 bfd_vma insn_start; 127 int orig_sizeflag; 128 jmp_buf bailout; 129 }; 130 131 enum address_mode 132 { 133 mode_16bit, 134 mode_32bit, 135 mode_64bit 136 }; 137 138 enum address_mode address_mode; 139 140 /* Flags for the prefixes for the current instruction. See below. */ 141 static int prefixes; 142 143 /* REX prefix the current instruction. See below. */ 144 static int rex; 145 /* Bits of REX we've already used. */ 146 static int rex_used; 147 /* REX bits in original REX prefix ignored. */ 148 static int rex_ignored; 149 /* Mark parts used in the REX prefix. When we are testing for 150 empty prefix (for 8bit register REX extension), just mask it 151 out. Otherwise test for REX bit is excuse for existence of REX 152 only in case value is nonzero. */ 153 #define USED_REX(value) \ 154 { \ 155 if (value) \ 156 { \ 157 if ((rex & value)) \ 158 rex_used |= (value) | REX_OPCODE; \ 159 } \ 160 else \ 161 rex_used |= REX_OPCODE; \ 162 } 163 164 /* Flags for prefixes which we somehow handled when printing the 165 current instruction. */ 166 static int used_prefixes; 167 168 /* Flags stored in PREFIXES. */ 169 #define PREFIX_REPZ 1 170 #define PREFIX_REPNZ 2 171 #define PREFIX_LOCK 4 172 #define PREFIX_CS 8 173 #define PREFIX_SS 0x10 174 #define PREFIX_DS 0x20 175 #define PREFIX_ES 0x40 176 #define PREFIX_FS 0x80 177 #define PREFIX_GS 0x100 178 #define PREFIX_DATA 0x200 179 #define PREFIX_ADDR 0x400 180 #define PREFIX_FWAIT 0x800 181 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) 183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps 184 on error. */ 185 #define FETCH_DATA(info, addr) \ 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ 187 ? 1 : fetch_data ((info), (addr))) 188 189 static int 190 fetch_data (struct disassemble_info *info, bfd_byte *addr) 191 { 192 int status; 193 struct dis_private *priv = (struct dis_private *) info->private_data; 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); 195 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE) 197 status = (*info->read_memory_func) (start, 198 priv->max_fetched, 199 addr - priv->max_fetched, 200 info); 201 else 202 status = -1; 203 if (status != 0) 204 { 205 /* If we did manage to read at least one byte, then 206 print_insn_i386 will do something sensible. Otherwise, print 207 an error. We do that here because this is where we know 208 STATUS. */ 209 if (priv->max_fetched == priv->the_buffer) 210 (*info->memory_error_func) (status, start, info); 211 longjmp (priv->bailout, 1); 212 } 213 else 214 priv->max_fetched = addr; 215 return 1; 216 } 217 218 #define XX { NULL, 0 } 219 #define Bad_Opcode NULL, { { NULL, 0 } } 220 221 #define Eb { OP_E, b_mode } 222 #define EbS { OP_E, b_swap_mode } 223 #define Ev { OP_E, v_mode } 224 #define EvS { OP_E, v_swap_mode } 225 #define Ed { OP_E, d_mode } 226 #define Edq { OP_E, dq_mode } 227 #define Edqw { OP_E, dqw_mode } 228 #define Edqb { OP_E, dqb_mode } 229 #define Edqd { OP_E, dqd_mode } 230 #define Eq { OP_E, q_mode } 231 #define indirEv { OP_indirE, stack_v_mode } 232 #define indirEp { OP_indirE, f_mode } 233 #define stackEv { OP_E, stack_v_mode } 234 #define Em { OP_E, m_mode } 235 #define Ew { OP_E, w_mode } 236 #define M { OP_M, 0 } /* lea, lgdt, etc. */ 237 #define Ma { OP_M, a_mode } 238 #define Mb { OP_M, b_mode } 239 #define Md { OP_M, d_mode } 240 #define Mo { OP_M, o_mode } 241 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ 242 #define Mq { OP_M, q_mode } 243 #define Mx { OP_M, x_mode } 244 #define Mxmm { OP_M, xmm_mode } 245 #define Gb { OP_G, b_mode } 246 #define Gv { OP_G, v_mode } 247 #define Gd { OP_G, d_mode } 248 #define Gdq { OP_G, dq_mode } 249 #define Gm { OP_G, m_mode } 250 #define Gw { OP_G, w_mode } 251 #define Rd { OP_R, d_mode } 252 #define Rm { OP_R, m_mode } 253 #define Ib { OP_I, b_mode } 254 #define sIb { OP_sI, b_mode } /* sign extened byte */ 255 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ 256 #define Iv { OP_I, v_mode } 257 #define sIv { OP_sI, v_mode } 258 #define Iq { OP_I, q_mode } 259 #define Iv64 { OP_I64, v_mode } 260 #define Iw { OP_I, w_mode } 261 #define I1 { OP_I, const_1_mode } 262 #define Jb { OP_J, b_mode } 263 #define Jv { OP_J, v_mode } 264 #define Cm { OP_C, m_mode } 265 #define Dm { OP_D, m_mode } 266 #define Td { OP_T, d_mode } 267 #define Skip_MODRM { OP_Skip_MODRM, 0 } 268 269 #define RMeAX { OP_REG, eAX_reg } 270 #define RMeBX { OP_REG, eBX_reg } 271 #define RMeCX { OP_REG, eCX_reg } 272 #define RMeDX { OP_REG, eDX_reg } 273 #define RMeSP { OP_REG, eSP_reg } 274 #define RMeBP { OP_REG, eBP_reg } 275 #define RMeSI { OP_REG, eSI_reg } 276 #define RMeDI { OP_REG, eDI_reg } 277 #define RMrAX { OP_REG, rAX_reg } 278 #define RMrBX { OP_REG, rBX_reg } 279 #define RMrCX { OP_REG, rCX_reg } 280 #define RMrDX { OP_REG, rDX_reg } 281 #define RMrSP { OP_REG, rSP_reg } 282 #define RMrBP { OP_REG, rBP_reg } 283 #define RMrSI { OP_REG, rSI_reg } 284 #define RMrDI { OP_REG, rDI_reg } 285 #define RMAL { OP_REG, al_reg } 286 #define RMCL { OP_REG, cl_reg } 287 #define RMDL { OP_REG, dl_reg } 288 #define RMBL { OP_REG, bl_reg } 289 #define RMAH { OP_REG, ah_reg } 290 #define RMCH { OP_REG, ch_reg } 291 #define RMDH { OP_REG, dh_reg } 292 #define RMBH { OP_REG, bh_reg } 293 #define RMAX { OP_REG, ax_reg } 294 #define RMDX { OP_REG, dx_reg } 295 296 #define eAX { OP_IMREG, eAX_reg } 297 #define eBX { OP_IMREG, eBX_reg } 298 #define eCX { OP_IMREG, eCX_reg } 299 #define eDX { OP_IMREG, eDX_reg } 300 #define eSP { OP_IMREG, eSP_reg } 301 #define eBP { OP_IMREG, eBP_reg } 302 #define eSI { OP_IMREG, eSI_reg } 303 #define eDI { OP_IMREG, eDI_reg } 304 #define AL { OP_IMREG, al_reg } 305 #define CL { OP_IMREG, cl_reg } 306 #define DL { OP_IMREG, dl_reg } 307 #define BL { OP_IMREG, bl_reg } 308 #define AH { OP_IMREG, ah_reg } 309 #define CH { OP_IMREG, ch_reg } 310 #define DH { OP_IMREG, dh_reg } 311 #define BH { OP_IMREG, bh_reg } 312 #define AX { OP_IMREG, ax_reg } 313 #define DX { OP_IMREG, dx_reg } 314 #define zAX { OP_IMREG, z_mode_ax_reg } 315 #define indirDX { OP_IMREG, indir_dx_reg } 316 317 #define Sw { OP_SEG, w_mode } 318 #define Sv { OP_SEG, v_mode } 319 #define Ap { OP_DIR, 0 } 320 #define Ob { OP_OFF64, b_mode } 321 #define Ov { OP_OFF64, v_mode } 322 #define Xb { OP_DSreg, eSI_reg } 323 #define Xv { OP_DSreg, eSI_reg } 324 #define Xz { OP_DSreg, eSI_reg } 325 #define Yb { OP_ESreg, eDI_reg } 326 #define Yv { OP_ESreg, eDI_reg } 327 #define DSBX { OP_DSreg, eBX_reg } 328 329 #define es { OP_REG, es_reg } 330 #define ss { OP_REG, ss_reg } 331 #define cs { OP_REG, cs_reg } 332 #define ds { OP_REG, ds_reg } 333 #define fs { OP_REG, fs_reg } 334 #define gs { OP_REG, gs_reg } 335 336 #define MX { OP_MMX, 0 } 337 #define XM { OP_XMM, 0 } 338 #define XMScalar { OP_XMM, scalar_mode } 339 #define XMM { OP_XMM, xmm_mode } 340 #define EM { OP_EM, v_mode } 341 #define EMS { OP_EM, v_swap_mode } 342 #define EMd { OP_EM, d_mode } 343 #define EMx { OP_EM, x_mode } 344 #define EXw { OP_EX, w_mode } 345 #define EXd { OP_EX, d_mode } 346 #define EXdScalar { OP_EX, d_scalar_mode } 347 #define EXdS { OP_EX, d_swap_mode } 348 #define EXq { OP_EX, q_mode } 349 #define EXqScalar { OP_EX, q_scalar_mode } 350 #define EXqScalarS { OP_EX, q_scalar_swap_mode } 351 #define EXqS { OP_EX, q_swap_mode } 352 #define EXx { OP_EX, x_mode } 353 #define EXxS { OP_EX, x_swap_mode } 354 #define EXxmm { OP_EX, xmm_mode } 355 #define EXxmmq { OP_EX, xmmq_mode } 356 #define EXymmq { OP_EX, ymmq_mode } 357 #define EXVexWdq { OP_EX, vex_w_dq_mode } 358 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } 359 #define MS { OP_MS, v_mode } 360 #define XS { OP_XS, v_mode } 361 #define EMCq { OP_EMC, q_mode } 362 #define MXC { OP_MXC, 0 } 363 #define OPSUF { OP_3DNowSuffix, 0 } 364 #define CMP { CMP_Fixup, 0 } 365 #define XMM0 { XMM_Fixup, 0 } 366 #define FXSAVE { FXSAVE_Fixup, 0 } 367 #define Vex_2src_1 { OP_Vex_2src_1, 0 } 368 #define Vex_2src_2 { OP_Vex_2src_2, 0 } 369 370 #define Vex { OP_VEX, vex_mode } 371 #define VexScalar { OP_VEX, vex_scalar_mode } 372 #define Vex128 { OP_VEX, vex128_mode } 373 #define Vex256 { OP_VEX, vex256_mode } 374 #define VexGdq { OP_VEX, dq_mode } 375 #define VexI4 { VEXI4_Fixup, 0} 376 #define EXdVex { OP_EX_Vex, d_mode } 377 #define EXdVexS { OP_EX_Vex, d_swap_mode } 378 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } 379 #define EXqVex { OP_EX_Vex, q_mode } 380 #define EXqVexS { OP_EX_Vex, q_swap_mode } 381 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } 382 #define EXVexW { OP_EX_VexW, x_mode } 383 #define EXdVexW { OP_EX_VexW, d_mode } 384 #define EXqVexW { OP_EX_VexW, q_mode } 385 #define EXVexImmW { OP_EX_VexImmW, x_mode } 386 #define XMVex { OP_XMM_Vex, 0 } 387 #define XMVexScalar { OP_XMM_Vex, scalar_mode } 388 #define XMVexW { OP_XMM_VexW, 0 } 389 #define XMVexI4 { OP_REG_VexI4, x_mode } 390 #define PCLMUL { PCLMUL_Fixup, 0 } 391 #define VZERO { VZERO_Fixup, 0 } 392 #define VCMP { VCMP_Fixup, 0 } 393 394 /* Used handle "rep" prefix for string instructions. */ 395 #define Xbr { REP_Fixup, eSI_reg } 396 #define Xvr { REP_Fixup, eSI_reg } 397 #define Ybr { REP_Fixup, eDI_reg } 398 #define Yvr { REP_Fixup, eDI_reg } 399 #define Yzr { REP_Fixup, eDI_reg } 400 #define indirDXr { REP_Fixup, indir_dx_reg } 401 #define ALr { REP_Fixup, al_reg } 402 #define eAXr { REP_Fixup, eAX_reg } 403 404 #define cond_jump_flag { NULL, cond_jump_mode } 405 #define loop_jcxz_flag { NULL, loop_jcxz_mode } 406 407 /* bits in sizeflag */ 408 #define SUFFIX_ALWAYS 4 409 #define AFLAG 2 410 #define DFLAG 1 411 412 enum 413 { 414 /* byte operand */ 415 b_mode = 1, 416 /* byte operand with operand swapped */ 417 b_swap_mode, 418 /* byte operand, sign extend like 'T' suffix */ 419 b_T_mode, 420 /* operand size depends on prefixes */ 421 v_mode, 422 /* operand size depends on prefixes with operand swapped */ 423 v_swap_mode, 424 /* word operand */ 425 w_mode, 426 /* double word operand */ 427 d_mode, 428 /* double word operand with operand swapped */ 429 d_swap_mode, 430 /* quad word operand */ 431 q_mode, 432 /* quad word operand with operand swapped */ 433 q_swap_mode, 434 /* ten-byte operand */ 435 t_mode, 436 /* 16-byte XMM or 32-byte YMM operand */ 437 x_mode, 438 /* 16-byte XMM or 32-byte YMM operand with operand swapped */ 439 x_swap_mode, 440 /* 16-byte XMM operand */ 441 xmm_mode, 442 /* 16-byte XMM or quad word operand */ 443 xmmq_mode, 444 /* 32-byte YMM or quad word operand */ 445 ymmq_mode, 446 /* d_mode in 32bit, q_mode in 64bit mode. */ 447 m_mode, 448 /* pair of v_mode operands */ 449 a_mode, 450 cond_jump_mode, 451 loop_jcxz_mode, 452 /* operand size depends on REX prefixes. */ 453 dq_mode, 454 /* registers like dq_mode, memory like w_mode. */ 455 dqw_mode, 456 /* 4- or 6-byte pointer operand */ 457 f_mode, 458 const_1_mode, 459 /* v_mode for stack-related opcodes. */ 460 stack_v_mode, 461 /* non-quad operand size depends on prefixes */ 462 z_mode, 463 /* 16-byte operand */ 464 o_mode, 465 /* registers like dq_mode, memory like b_mode. */ 466 dqb_mode, 467 /* registers like dq_mode, memory like d_mode. */ 468 dqd_mode, 469 /* normal vex mode */ 470 vex_mode, 471 /* 128bit vex mode */ 472 vex128_mode, 473 /* 256bit vex mode */ 474 vex256_mode, 475 /* operand size depends on the VEX.W bit. */ 476 vex_w_dq_mode, 477 478 /* scalar, ignore vector length. */ 479 scalar_mode, 480 /* like d_mode, ignore vector length. */ 481 d_scalar_mode, 482 /* like d_swap_mode, ignore vector length. */ 483 d_scalar_swap_mode, 484 /* like q_mode, ignore vector length. */ 485 q_scalar_mode, 486 /* like q_swap_mode, ignore vector length. */ 487 q_scalar_swap_mode, 488 /* like vex_mode, ignore vector length. */ 489 vex_scalar_mode, 490 /* like vex_w_dq_mode, ignore vector length. */ 491 vex_scalar_w_dq_mode, 492 493 es_reg, 494 cs_reg, 495 ss_reg, 496 ds_reg, 497 fs_reg, 498 gs_reg, 499 500 eAX_reg, 501 eCX_reg, 502 eDX_reg, 503 eBX_reg, 504 eSP_reg, 505 eBP_reg, 506 eSI_reg, 507 eDI_reg, 508 509 al_reg, 510 cl_reg, 511 dl_reg, 512 bl_reg, 513 ah_reg, 514 ch_reg, 515 dh_reg, 516 bh_reg, 517 518 ax_reg, 519 cx_reg, 520 dx_reg, 521 bx_reg, 522 sp_reg, 523 bp_reg, 524 si_reg, 525 di_reg, 526 527 rAX_reg, 528 rCX_reg, 529 rDX_reg, 530 rBX_reg, 531 rSP_reg, 532 rBP_reg, 533 rSI_reg, 534 rDI_reg, 535 536 z_mode_ax_reg, 537 indir_dx_reg 538 }; 539 540 enum 541 { 542 FLOATCODE = 1, 543 USE_REG_TABLE, 544 USE_MOD_TABLE, 545 USE_RM_TABLE, 546 USE_PREFIX_TABLE, 547 USE_X86_64_TABLE, 548 USE_3BYTE_TABLE, 549 USE_XOP_8F_TABLE, 550 USE_VEX_C4_TABLE, 551 USE_VEX_C5_TABLE, 552 USE_VEX_LEN_TABLE, 553 USE_VEX_W_TABLE 554 }; 555 556 #define FLOAT NULL, { { NULL, FLOATCODE } } 557 558 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } 559 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) 560 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) 561 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) 562 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) 563 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) 564 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) 565 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) 566 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) 567 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) 568 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) 569 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) 570 571 enum 572 { 573 REG_80 = 0, 574 REG_81, 575 REG_82, 576 REG_8F, 577 REG_C0, 578 REG_C1, 579 REG_C6, 580 REG_C7, 581 REG_D0, 582 REG_D1, 583 REG_D2, 584 REG_D3, 585 REG_F6, 586 REG_F7, 587 REG_FE, 588 REG_FF, 589 REG_0F00, 590 REG_0F01, 591 REG_0F0D, 592 REG_0F18, 593 REG_0F71, 594 REG_0F72, 595 REG_0F73, 596 REG_0FA6, 597 REG_0FA7, 598 REG_0FAE, 599 REG_0FBA, 600 REG_0FC7, 601 REG_VEX_0F71, 602 REG_VEX_0F72, 603 REG_VEX_0F73, 604 REG_VEX_0FAE, 605 REG_VEX_0F38F3, 606 REG_XOP_LWPCB, 607 REG_XOP_LWP, 608 REG_XOP_TBM_01, 609 REG_XOP_TBM_02 610 }; 611 612 enum 613 { 614 MOD_8D = 0, 615 MOD_0F01_REG_0, 616 MOD_0F01_REG_1, 617 MOD_0F01_REG_2, 618 MOD_0F01_REG_3, 619 MOD_0F01_REG_7, 620 MOD_0F12_PREFIX_0, 621 MOD_0F13, 622 MOD_0F16_PREFIX_0, 623 MOD_0F17, 624 MOD_0F18_REG_0, 625 MOD_0F18_REG_1, 626 MOD_0F18_REG_2, 627 MOD_0F18_REG_3, 628 MOD_0F20, 629 MOD_0F21, 630 MOD_0F22, 631 MOD_0F23, 632 MOD_0F24, 633 MOD_0F26, 634 MOD_0F2B_PREFIX_0, 635 MOD_0F2B_PREFIX_1, 636 MOD_0F2B_PREFIX_2, 637 MOD_0F2B_PREFIX_3, 638 MOD_0F51, 639 MOD_0F71_REG_2, 640 MOD_0F71_REG_4, 641 MOD_0F71_REG_6, 642 MOD_0F72_REG_2, 643 MOD_0F72_REG_4, 644 MOD_0F72_REG_6, 645 MOD_0F73_REG_2, 646 MOD_0F73_REG_3, 647 MOD_0F73_REG_6, 648 MOD_0F73_REG_7, 649 MOD_0FAE_REG_0, 650 MOD_0FAE_REG_1, 651 MOD_0FAE_REG_2, 652 MOD_0FAE_REG_3, 653 MOD_0FAE_REG_4, 654 MOD_0FAE_REG_5, 655 MOD_0FAE_REG_6, 656 MOD_0FAE_REG_7, 657 MOD_0FB2, 658 MOD_0FB4, 659 MOD_0FB5, 660 MOD_0FC7_REG_6, 661 MOD_0FC7_REG_7, 662 MOD_0FD7, 663 MOD_0FE7_PREFIX_2, 664 MOD_0FF0_PREFIX_3, 665 MOD_0F382A_PREFIX_2, 666 MOD_62_32BIT, 667 MOD_C4_32BIT, 668 MOD_C5_32BIT, 669 MOD_VEX_0F12_PREFIX_0, 670 MOD_VEX_0F13, 671 MOD_VEX_0F16_PREFIX_0, 672 MOD_VEX_0F17, 673 MOD_VEX_0F2B, 674 MOD_VEX_0F50, 675 MOD_VEX_0F71_REG_2, 676 MOD_VEX_0F71_REG_4, 677 MOD_VEX_0F71_REG_6, 678 MOD_VEX_0F72_REG_2, 679 MOD_VEX_0F72_REG_4, 680 MOD_VEX_0F72_REG_6, 681 MOD_VEX_0F73_REG_2, 682 MOD_VEX_0F73_REG_3, 683 MOD_VEX_0F73_REG_6, 684 MOD_VEX_0F73_REG_7, 685 MOD_VEX_0FAE_REG_2, 686 MOD_VEX_0FAE_REG_3, 687 MOD_VEX_0FD7_PREFIX_2, 688 MOD_VEX_0FE7_PREFIX_2, 689 MOD_VEX_0FF0_PREFIX_3, 690 MOD_VEX_0F3818_PREFIX_2, 691 MOD_VEX_0F3819_PREFIX_2, 692 MOD_VEX_0F381A_PREFIX_2, 693 MOD_VEX_0F382A_PREFIX_2, 694 MOD_VEX_0F382C_PREFIX_2, 695 MOD_VEX_0F382D_PREFIX_2, 696 MOD_VEX_0F382E_PREFIX_2, 697 MOD_VEX_0F382F_PREFIX_2 698 }; 699 700 enum 701 { 702 RM_0F01_REG_0 = 0, 703 RM_0F01_REG_1, 704 RM_0F01_REG_2, 705 RM_0F01_REG_3, 706 RM_0F01_REG_7, 707 RM_0FAE_REG_5, 708 RM_0FAE_REG_6, 709 RM_0FAE_REG_7 710 }; 711 712 enum 713 { 714 PREFIX_90 = 0, 715 PREFIX_0F10, 716 PREFIX_0F11, 717 PREFIX_0F12, 718 PREFIX_0F16, 719 PREFIX_0F2A, 720 PREFIX_0F2B, 721 PREFIX_0F2C, 722 PREFIX_0F2D, 723 PREFIX_0F2E, 724 PREFIX_0F2F, 725 PREFIX_0F51, 726 PREFIX_0F52, 727 PREFIX_0F53, 728 PREFIX_0F58, 729 PREFIX_0F59, 730 PREFIX_0F5A, 731 PREFIX_0F5B, 732 PREFIX_0F5C, 733 PREFIX_0F5D, 734 PREFIX_0F5E, 735 PREFIX_0F5F, 736 PREFIX_0F60, 737 PREFIX_0F61, 738 PREFIX_0F62, 739 PREFIX_0F6C, 740 PREFIX_0F6D, 741 PREFIX_0F6F, 742 PREFIX_0F70, 743 PREFIX_0F73_REG_3, 744 PREFIX_0F73_REG_7, 745 PREFIX_0F78, 746 PREFIX_0F79, 747 PREFIX_0F7C, 748 PREFIX_0F7D, 749 PREFIX_0F7E, 750 PREFIX_0F7F, 751 PREFIX_0FAE_REG_0, 752 PREFIX_0FAE_REG_1, 753 PREFIX_0FAE_REG_2, 754 PREFIX_0FAE_REG_3, 755 PREFIX_0FB8, 756 PREFIX_0FBC, 757 PREFIX_0FBD, 758 PREFIX_0FC2, 759 PREFIX_0FC3, 760 PREFIX_0FC7_REG_6, 761 PREFIX_0FD0, 762 PREFIX_0FD6, 763 PREFIX_0FE6, 764 PREFIX_0FE7, 765 PREFIX_0FF0, 766 PREFIX_0FF7, 767 PREFIX_0F3810, 768 PREFIX_0F3814, 769 PREFIX_0F3815, 770 PREFIX_0F3817, 771 PREFIX_0F3820, 772 PREFIX_0F3821, 773 PREFIX_0F3822, 774 PREFIX_0F3823, 775 PREFIX_0F3824, 776 PREFIX_0F3825, 777 PREFIX_0F3828, 778 PREFIX_0F3829, 779 PREFIX_0F382A, 780 PREFIX_0F382B, 781 PREFIX_0F3830, 782 PREFIX_0F3831, 783 PREFIX_0F3832, 784 PREFIX_0F3833, 785 PREFIX_0F3834, 786 PREFIX_0F3835, 787 PREFIX_0F3837, 788 PREFIX_0F3838, 789 PREFIX_0F3839, 790 PREFIX_0F383A, 791 PREFIX_0F383B, 792 PREFIX_0F383C, 793 PREFIX_0F383D, 794 PREFIX_0F383E, 795 PREFIX_0F383F, 796 PREFIX_0F3840, 797 PREFIX_0F3841, 798 PREFIX_0F3880, 799 PREFIX_0F3881, 800 PREFIX_0F38DB, 801 PREFIX_0F38DC, 802 PREFIX_0F38DD, 803 PREFIX_0F38DE, 804 PREFIX_0F38DF, 805 PREFIX_0F38F0, 806 PREFIX_0F38F1, 807 PREFIX_0F3A08, 808 PREFIX_0F3A09, 809 PREFIX_0F3A0A, 810 PREFIX_0F3A0B, 811 PREFIX_0F3A0C, 812 PREFIX_0F3A0D, 813 PREFIX_0F3A0E, 814 PREFIX_0F3A14, 815 PREFIX_0F3A15, 816 PREFIX_0F3A16, 817 PREFIX_0F3A17, 818 PREFIX_0F3A20, 819 PREFIX_0F3A21, 820 PREFIX_0F3A22, 821 PREFIX_0F3A40, 822 PREFIX_0F3A41, 823 PREFIX_0F3A42, 824 PREFIX_0F3A44, 825 PREFIX_0F3A60, 826 PREFIX_0F3A61, 827 PREFIX_0F3A62, 828 PREFIX_0F3A63, 829 PREFIX_0F3ADF, 830 PREFIX_VEX_0F10, 831 PREFIX_VEX_0F11, 832 PREFIX_VEX_0F12, 833 PREFIX_VEX_0F16, 834 PREFIX_VEX_0F2A, 835 PREFIX_VEX_0F2C, 836 PREFIX_VEX_0F2D, 837 PREFIX_VEX_0F2E, 838 PREFIX_VEX_0F2F, 839 PREFIX_VEX_0F51, 840 PREFIX_VEX_0F52, 841 PREFIX_VEX_0F53, 842 PREFIX_VEX_0F58, 843 PREFIX_VEX_0F59, 844 PREFIX_VEX_0F5A, 845 PREFIX_VEX_0F5B, 846 PREFIX_VEX_0F5C, 847 PREFIX_VEX_0F5D, 848 PREFIX_VEX_0F5E, 849 PREFIX_VEX_0F5F, 850 PREFIX_VEX_0F60, 851 PREFIX_VEX_0F61, 852 PREFIX_VEX_0F62, 853 PREFIX_VEX_0F63, 854 PREFIX_VEX_0F64, 855 PREFIX_VEX_0F65, 856 PREFIX_VEX_0F66, 857 PREFIX_VEX_0F67, 858 PREFIX_VEX_0F68, 859 PREFIX_VEX_0F69, 860 PREFIX_VEX_0F6A, 861 PREFIX_VEX_0F6B, 862 PREFIX_VEX_0F6C, 863 PREFIX_VEX_0F6D, 864 PREFIX_VEX_0F6E, 865 PREFIX_VEX_0F6F, 866 PREFIX_VEX_0F70, 867 PREFIX_VEX_0F71_REG_2, 868 PREFIX_VEX_0F71_REG_4, 869 PREFIX_VEX_0F71_REG_6, 870 PREFIX_VEX_0F72_REG_2, 871 PREFIX_VEX_0F72_REG_4, 872 PREFIX_VEX_0F72_REG_6, 873 PREFIX_VEX_0F73_REG_2, 874 PREFIX_VEX_0F73_REG_3, 875 PREFIX_VEX_0F73_REG_6, 876 PREFIX_VEX_0F73_REG_7, 877 PREFIX_VEX_0F74, 878 PREFIX_VEX_0F75, 879 PREFIX_VEX_0F76, 880 PREFIX_VEX_0F77, 881 PREFIX_VEX_0F7C, 882 PREFIX_VEX_0F7D, 883 PREFIX_VEX_0F7E, 884 PREFIX_VEX_0F7F, 885 PREFIX_VEX_0FC2, 886 PREFIX_VEX_0FC4, 887 PREFIX_VEX_0FC5, 888 PREFIX_VEX_0FD0, 889 PREFIX_VEX_0FD1, 890 PREFIX_VEX_0FD2, 891 PREFIX_VEX_0FD3, 892 PREFIX_VEX_0FD4, 893 PREFIX_VEX_0FD5, 894 PREFIX_VEX_0FD6, 895 PREFIX_VEX_0FD7, 896 PREFIX_VEX_0FD8, 897 PREFIX_VEX_0FD9, 898 PREFIX_VEX_0FDA, 899 PREFIX_VEX_0FDB, 900 PREFIX_VEX_0FDC, 901 PREFIX_VEX_0FDD, 902 PREFIX_VEX_0FDE, 903 PREFIX_VEX_0FDF, 904 PREFIX_VEX_0FE0, 905 PREFIX_VEX_0FE1, 906 PREFIX_VEX_0FE2, 907 PREFIX_VEX_0FE3, 908 PREFIX_VEX_0FE4, 909 PREFIX_VEX_0FE5, 910 PREFIX_VEX_0FE6, 911 PREFIX_VEX_0FE7, 912 PREFIX_VEX_0FE8, 913 PREFIX_VEX_0FE9, 914 PREFIX_VEX_0FEA, 915 PREFIX_VEX_0FEB, 916 PREFIX_VEX_0FEC, 917 PREFIX_VEX_0FED, 918 PREFIX_VEX_0FEE, 919 PREFIX_VEX_0FEF, 920 PREFIX_VEX_0FF0, 921 PREFIX_VEX_0FF1, 922 PREFIX_VEX_0FF2, 923 PREFIX_VEX_0FF3, 924 PREFIX_VEX_0FF4, 925 PREFIX_VEX_0FF5, 926 PREFIX_VEX_0FF6, 927 PREFIX_VEX_0FF7, 928 PREFIX_VEX_0FF8, 929 PREFIX_VEX_0FF9, 930 PREFIX_VEX_0FFA, 931 PREFIX_VEX_0FFB, 932 PREFIX_VEX_0FFC, 933 PREFIX_VEX_0FFD, 934 PREFIX_VEX_0FFE, 935 PREFIX_VEX_0F3800, 936 PREFIX_VEX_0F3801, 937 PREFIX_VEX_0F3802, 938 PREFIX_VEX_0F3803, 939 PREFIX_VEX_0F3804, 940 PREFIX_VEX_0F3805, 941 PREFIX_VEX_0F3806, 942 PREFIX_VEX_0F3807, 943 PREFIX_VEX_0F3808, 944 PREFIX_VEX_0F3809, 945 PREFIX_VEX_0F380A, 946 PREFIX_VEX_0F380B, 947 PREFIX_VEX_0F380C, 948 PREFIX_VEX_0F380D, 949 PREFIX_VEX_0F380E, 950 PREFIX_VEX_0F380F, 951 PREFIX_VEX_0F3813, 952 PREFIX_VEX_0F3817, 953 PREFIX_VEX_0F3818, 954 PREFIX_VEX_0F3819, 955 PREFIX_VEX_0F381A, 956 PREFIX_VEX_0F381C, 957 PREFIX_VEX_0F381D, 958 PREFIX_VEX_0F381E, 959 PREFIX_VEX_0F3820, 960 PREFIX_VEX_0F3821, 961 PREFIX_VEX_0F3822, 962 PREFIX_VEX_0F3823, 963 PREFIX_VEX_0F3824, 964 PREFIX_VEX_0F3825, 965 PREFIX_VEX_0F3828, 966 PREFIX_VEX_0F3829, 967 PREFIX_VEX_0F382A, 968 PREFIX_VEX_0F382B, 969 PREFIX_VEX_0F382C, 970 PREFIX_VEX_0F382D, 971 PREFIX_VEX_0F382E, 972 PREFIX_VEX_0F382F, 973 PREFIX_VEX_0F3830, 974 PREFIX_VEX_0F3831, 975 PREFIX_VEX_0F3832, 976 PREFIX_VEX_0F3833, 977 PREFIX_VEX_0F3834, 978 PREFIX_VEX_0F3835, 979 PREFIX_VEX_0F3837, 980 PREFIX_VEX_0F3838, 981 PREFIX_VEX_0F3839, 982 PREFIX_VEX_0F383A, 983 PREFIX_VEX_0F383B, 984 PREFIX_VEX_0F383C, 985 PREFIX_VEX_0F383D, 986 PREFIX_VEX_0F383E, 987 PREFIX_VEX_0F383F, 988 PREFIX_VEX_0F3840, 989 PREFIX_VEX_0F3841, 990 PREFIX_VEX_0F3896, 991 PREFIX_VEX_0F3897, 992 PREFIX_VEX_0F3898, 993 PREFIX_VEX_0F3899, 994 PREFIX_VEX_0F389A, 995 PREFIX_VEX_0F389B, 996 PREFIX_VEX_0F389C, 997 PREFIX_VEX_0F389D, 998 PREFIX_VEX_0F389E, 999 PREFIX_VEX_0F389F, 1000 PREFIX_VEX_0F38A6, 1001 PREFIX_VEX_0F38A7, 1002 PREFIX_VEX_0F38A8, 1003 PREFIX_VEX_0F38A9, 1004 PREFIX_VEX_0F38AA, 1005 PREFIX_VEX_0F38AB, 1006 PREFIX_VEX_0F38AC, 1007 PREFIX_VEX_0F38AD, 1008 PREFIX_VEX_0F38AE, 1009 PREFIX_VEX_0F38AF, 1010 PREFIX_VEX_0F38B6, 1011 PREFIX_VEX_0F38B7, 1012 PREFIX_VEX_0F38B8, 1013 PREFIX_VEX_0F38B9, 1014 PREFIX_VEX_0F38BA, 1015 PREFIX_VEX_0F38BB, 1016 PREFIX_VEX_0F38BC, 1017 PREFIX_VEX_0F38BD, 1018 PREFIX_VEX_0F38BE, 1019 PREFIX_VEX_0F38BF, 1020 PREFIX_VEX_0F38DB, 1021 PREFIX_VEX_0F38DC, 1022 PREFIX_VEX_0F38DD, 1023 PREFIX_VEX_0F38DE, 1024 PREFIX_VEX_0F38DF, 1025 PREFIX_VEX_0F38F2, 1026 PREFIX_VEX_0F38F3_REG_1, 1027 PREFIX_VEX_0F38F3_REG_2, 1028 PREFIX_VEX_0F38F3_REG_3, 1029 PREFIX_VEX_0F38F7, 1030 PREFIX_VEX_0F3A04, 1031 PREFIX_VEX_0F3A05, 1032 PREFIX_VEX_0F3A06, 1033 PREFIX_VEX_0F3A08, 1034 PREFIX_VEX_0F3A09, 1035 PREFIX_VEX_0F3A0A, 1036 PREFIX_VEX_0F3A0B, 1037 PREFIX_VEX_0F3A0C, 1038 PREFIX_VEX_0F3A0D, 1039 PREFIX_VEX_0F3A0E, 1040 PREFIX_VEX_0F3A0F, 1041 PREFIX_VEX_0F3A14, 1042 PREFIX_VEX_0F3A15, 1043 PREFIX_VEX_0F3A16, 1044 PREFIX_VEX_0F3A17, 1045 PREFIX_VEX_0F3A18, 1046 PREFIX_VEX_0F3A19, 1047 PREFIX_VEX_0F3A1D, 1048 PREFIX_VEX_0F3A20, 1049 PREFIX_VEX_0F3A21, 1050 PREFIX_VEX_0F3A22, 1051 PREFIX_VEX_0F3A40, 1052 PREFIX_VEX_0F3A41, 1053 PREFIX_VEX_0F3A42, 1054 PREFIX_VEX_0F3A44, 1055 PREFIX_VEX_0F3A48, 1056 PREFIX_VEX_0F3A49, 1057 PREFIX_VEX_0F3A4A, 1058 PREFIX_VEX_0F3A4B, 1059 PREFIX_VEX_0F3A4C, 1060 PREFIX_VEX_0F3A5C, 1061 PREFIX_VEX_0F3A5D, 1062 PREFIX_VEX_0F3A5E, 1063 PREFIX_VEX_0F3A5F, 1064 PREFIX_VEX_0F3A60, 1065 PREFIX_VEX_0F3A61, 1066 PREFIX_VEX_0F3A62, 1067 PREFIX_VEX_0F3A63, 1068 PREFIX_VEX_0F3A68, 1069 PREFIX_VEX_0F3A69, 1070 PREFIX_VEX_0F3A6A, 1071 PREFIX_VEX_0F3A6B, 1072 PREFIX_VEX_0F3A6C, 1073 PREFIX_VEX_0F3A6D, 1074 PREFIX_VEX_0F3A6E, 1075 PREFIX_VEX_0F3A6F, 1076 PREFIX_VEX_0F3A78, 1077 PREFIX_VEX_0F3A79, 1078 PREFIX_VEX_0F3A7A, 1079 PREFIX_VEX_0F3A7B, 1080 PREFIX_VEX_0F3A7C, 1081 PREFIX_VEX_0F3A7D, 1082 PREFIX_VEX_0F3A7E, 1083 PREFIX_VEX_0F3A7F, 1084 PREFIX_VEX_0F3ADF 1085 }; 1086 1087 enum 1088 { 1089 X86_64_06 = 0, 1090 X86_64_07, 1091 X86_64_0D, 1092 X86_64_16, 1093 X86_64_17, 1094 X86_64_1E, 1095 X86_64_1F, 1096 X86_64_27, 1097 X86_64_2F, 1098 X86_64_37, 1099 X86_64_3F, 1100 X86_64_60, 1101 X86_64_61, 1102 X86_64_62, 1103 X86_64_63, 1104 X86_64_6D, 1105 X86_64_6F, 1106 X86_64_9A, 1107 X86_64_C4, 1108 X86_64_C5, 1109 X86_64_CE, 1110 X86_64_D4, 1111 X86_64_D5, 1112 X86_64_EA, 1113 X86_64_0F01_REG_0, 1114 X86_64_0F01_REG_1, 1115 X86_64_0F01_REG_2, 1116 X86_64_0F01_REG_3 1117 }; 1118 1119 enum 1120 { 1121 THREE_BYTE_0F38 = 0, 1122 THREE_BYTE_0F3A, 1123 THREE_BYTE_0F7A 1124 }; 1125 1126 enum 1127 { 1128 XOP_08 = 0, 1129 XOP_09, 1130 XOP_0A 1131 }; 1132 1133 enum 1134 { 1135 VEX_0F = 0, 1136 VEX_0F38, 1137 VEX_0F3A 1138 }; 1139 1140 enum 1141 { 1142 VEX_LEN_0F10_P_1 = 0, 1143 VEX_LEN_0F10_P_3, 1144 VEX_LEN_0F11_P_1, 1145 VEX_LEN_0F11_P_3, 1146 VEX_LEN_0F12_P_0_M_0, 1147 VEX_LEN_0F12_P_0_M_1, 1148 VEX_LEN_0F12_P_2, 1149 VEX_LEN_0F13_M_0, 1150 VEX_LEN_0F16_P_0_M_0, 1151 VEX_LEN_0F16_P_0_M_1, 1152 VEX_LEN_0F16_P_2, 1153 VEX_LEN_0F17_M_0, 1154 VEX_LEN_0F2A_P_1, 1155 VEX_LEN_0F2A_P_3, 1156 VEX_LEN_0F2C_P_1, 1157 VEX_LEN_0F2C_P_3, 1158 VEX_LEN_0F2D_P_1, 1159 VEX_LEN_0F2D_P_3, 1160 VEX_LEN_0F2E_P_0, 1161 VEX_LEN_0F2E_P_2, 1162 VEX_LEN_0F2F_P_0, 1163 VEX_LEN_0F2F_P_2, 1164 VEX_LEN_0F51_P_1, 1165 VEX_LEN_0F51_P_3, 1166 VEX_LEN_0F52_P_1, 1167 VEX_LEN_0F53_P_1, 1168 VEX_LEN_0F58_P_1, 1169 VEX_LEN_0F58_P_3, 1170 VEX_LEN_0F59_P_1, 1171 VEX_LEN_0F59_P_3, 1172 VEX_LEN_0F5A_P_1, 1173 VEX_LEN_0F5A_P_3, 1174 VEX_LEN_0F5C_P_1, 1175 VEX_LEN_0F5C_P_3, 1176 VEX_LEN_0F5D_P_1, 1177 VEX_LEN_0F5D_P_3, 1178 VEX_LEN_0F5E_P_1, 1179 VEX_LEN_0F5E_P_3, 1180 VEX_LEN_0F5F_P_1, 1181 VEX_LEN_0F5F_P_3, 1182 VEX_LEN_0F60_P_2, 1183 VEX_LEN_0F61_P_2, 1184 VEX_LEN_0F62_P_2, 1185 VEX_LEN_0F63_P_2, 1186 VEX_LEN_0F64_P_2, 1187 VEX_LEN_0F65_P_2, 1188 VEX_LEN_0F66_P_2, 1189 VEX_LEN_0F67_P_2, 1190 VEX_LEN_0F68_P_2, 1191 VEX_LEN_0F69_P_2, 1192 VEX_LEN_0F6A_P_2, 1193 VEX_LEN_0F6B_P_2, 1194 VEX_LEN_0F6C_P_2, 1195 VEX_LEN_0F6D_P_2, 1196 VEX_LEN_0F6E_P_2, 1197 VEX_LEN_0F70_P_1, 1198 VEX_LEN_0F70_P_2, 1199 VEX_LEN_0F70_P_3, 1200 VEX_LEN_0F71_R_2_P_2, 1201 VEX_LEN_0F71_R_4_P_2, 1202 VEX_LEN_0F71_R_6_P_2, 1203 VEX_LEN_0F72_R_2_P_2, 1204 VEX_LEN_0F72_R_4_P_2, 1205 VEX_LEN_0F72_R_6_P_2, 1206 VEX_LEN_0F73_R_2_P_2, 1207 VEX_LEN_0F73_R_3_P_2, 1208 VEX_LEN_0F73_R_6_P_2, 1209 VEX_LEN_0F73_R_7_P_2, 1210 VEX_LEN_0F74_P_2, 1211 VEX_LEN_0F75_P_2, 1212 VEX_LEN_0F76_P_2, 1213 VEX_LEN_0F7E_P_1, 1214 VEX_LEN_0F7E_P_2, 1215 VEX_LEN_0FAE_R_2_M_0, 1216 VEX_LEN_0FAE_R_3_M_0, 1217 VEX_LEN_0FC2_P_1, 1218 VEX_LEN_0FC2_P_3, 1219 VEX_LEN_0FC4_P_2, 1220 VEX_LEN_0FC5_P_2, 1221 VEX_LEN_0FD1_P_2, 1222 VEX_LEN_0FD2_P_2, 1223 VEX_LEN_0FD3_P_2, 1224 VEX_LEN_0FD4_P_2, 1225 VEX_LEN_0FD5_P_2, 1226 VEX_LEN_0FD6_P_2, 1227 VEX_LEN_0FD7_P_2_M_1, 1228 VEX_LEN_0FD8_P_2, 1229 VEX_LEN_0FD9_P_2, 1230 VEX_LEN_0FDA_P_2, 1231 VEX_LEN_0FDB_P_2, 1232 VEX_LEN_0FDC_P_2, 1233 VEX_LEN_0FDD_P_2, 1234 VEX_LEN_0FDE_P_2, 1235 VEX_LEN_0FDF_P_2, 1236 VEX_LEN_0FE0_P_2, 1237 VEX_LEN_0FE1_P_2, 1238 VEX_LEN_0FE2_P_2, 1239 VEX_LEN_0FE3_P_2, 1240 VEX_LEN_0FE4_P_2, 1241 VEX_LEN_0FE5_P_2, 1242 VEX_LEN_0FE8_P_2, 1243 VEX_LEN_0FE9_P_2, 1244 VEX_LEN_0FEA_P_2, 1245 VEX_LEN_0FEB_P_2, 1246 VEX_LEN_0FEC_P_2, 1247 VEX_LEN_0FED_P_2, 1248 VEX_LEN_0FEE_P_2, 1249 VEX_LEN_0FEF_P_2, 1250 VEX_LEN_0FF1_P_2, 1251 VEX_LEN_0FF2_P_2, 1252 VEX_LEN_0FF3_P_2, 1253 VEX_LEN_0FF4_P_2, 1254 VEX_LEN_0FF5_P_2, 1255 VEX_LEN_0FF6_P_2, 1256 VEX_LEN_0FF7_P_2, 1257 VEX_LEN_0FF8_P_2, 1258 VEX_LEN_0FF9_P_2, 1259 VEX_LEN_0FFA_P_2, 1260 VEX_LEN_0FFB_P_2, 1261 VEX_LEN_0FFC_P_2, 1262 VEX_LEN_0FFD_P_2, 1263 VEX_LEN_0FFE_P_2, 1264 VEX_LEN_0F3800_P_2, 1265 VEX_LEN_0F3801_P_2, 1266 VEX_LEN_0F3802_P_2, 1267 VEX_LEN_0F3803_P_2, 1268 VEX_LEN_0F3804_P_2, 1269 VEX_LEN_0F3805_P_2, 1270 VEX_LEN_0F3806_P_2, 1271 VEX_LEN_0F3807_P_2, 1272 VEX_LEN_0F3808_P_2, 1273 VEX_LEN_0F3809_P_2, 1274 VEX_LEN_0F380A_P_2, 1275 VEX_LEN_0F380B_P_2, 1276 VEX_LEN_0F3819_P_2_M_0, 1277 VEX_LEN_0F381A_P_2_M_0, 1278 VEX_LEN_0F381C_P_2, 1279 VEX_LEN_0F381D_P_2, 1280 VEX_LEN_0F381E_P_2, 1281 VEX_LEN_0F3820_P_2, 1282 VEX_LEN_0F3821_P_2, 1283 VEX_LEN_0F3822_P_2, 1284 VEX_LEN_0F3823_P_2, 1285 VEX_LEN_0F3824_P_2, 1286 VEX_LEN_0F3825_P_2, 1287 VEX_LEN_0F3828_P_2, 1288 VEX_LEN_0F3829_P_2, 1289 VEX_LEN_0F382A_P_2_M_0, 1290 VEX_LEN_0F382B_P_2, 1291 VEX_LEN_0F3830_P_2, 1292 VEX_LEN_0F3831_P_2, 1293 VEX_LEN_0F3832_P_2, 1294 VEX_LEN_0F3833_P_2, 1295 VEX_LEN_0F3834_P_2, 1296 VEX_LEN_0F3835_P_2, 1297 VEX_LEN_0F3837_P_2, 1298 VEX_LEN_0F3838_P_2, 1299 VEX_LEN_0F3839_P_2, 1300 VEX_LEN_0F383A_P_2, 1301 VEX_LEN_0F383B_P_2, 1302 VEX_LEN_0F383C_P_2, 1303 VEX_LEN_0F383D_P_2, 1304 VEX_LEN_0F383E_P_2, 1305 VEX_LEN_0F383F_P_2, 1306 VEX_LEN_0F3840_P_2, 1307 VEX_LEN_0F3841_P_2, 1308 VEX_LEN_0F38DB_P_2, 1309 VEX_LEN_0F38DC_P_2, 1310 VEX_LEN_0F38DD_P_2, 1311 VEX_LEN_0F38DE_P_2, 1312 VEX_LEN_0F38DF_P_2, 1313 VEX_LEN_0F38F2_P_0, 1314 VEX_LEN_0F38F3_R_1_P_0, 1315 VEX_LEN_0F38F3_R_2_P_0, 1316 VEX_LEN_0F38F3_R_3_P_0, 1317 VEX_LEN_0F38F7_P_0, 1318 VEX_LEN_0F3A06_P_2, 1319 VEX_LEN_0F3A0A_P_2, 1320 VEX_LEN_0F3A0B_P_2, 1321 VEX_LEN_0F3A0E_P_2, 1322 VEX_LEN_0F3A0F_P_2, 1323 VEX_LEN_0F3A14_P_2, 1324 VEX_LEN_0F3A15_P_2, 1325 VEX_LEN_0F3A16_P_2, 1326 VEX_LEN_0F3A17_P_2, 1327 VEX_LEN_0F3A18_P_2, 1328 VEX_LEN_0F3A19_P_2, 1329 VEX_LEN_0F3A20_P_2, 1330 VEX_LEN_0F3A21_P_2, 1331 VEX_LEN_0F3A22_P_2, 1332 VEX_LEN_0F3A41_P_2, 1333 VEX_LEN_0F3A42_P_2, 1334 VEX_LEN_0F3A44_P_2, 1335 VEX_LEN_0F3A4C_P_2, 1336 VEX_LEN_0F3A60_P_2, 1337 VEX_LEN_0F3A61_P_2, 1338 VEX_LEN_0F3A62_P_2, 1339 VEX_LEN_0F3A63_P_2, 1340 VEX_LEN_0F3A6A_P_2, 1341 VEX_LEN_0F3A6B_P_2, 1342 VEX_LEN_0F3A6E_P_2, 1343 VEX_LEN_0F3A6F_P_2, 1344 VEX_LEN_0F3A7A_P_2, 1345 VEX_LEN_0F3A7B_P_2, 1346 VEX_LEN_0F3A7E_P_2, 1347 VEX_LEN_0F3A7F_P_2, 1348 VEX_LEN_0F3ADF_P_2, 1349 VEX_LEN_0FXOP_09_80, 1350 VEX_LEN_0FXOP_09_81 1351 }; 1352 1353 enum 1354 { 1355 VEX_W_0F10_P_0 = 0, 1356 VEX_W_0F10_P_1, 1357 VEX_W_0F10_P_2, 1358 VEX_W_0F10_P_3, 1359 VEX_W_0F11_P_0, 1360 VEX_W_0F11_P_1, 1361 VEX_W_0F11_P_2, 1362 VEX_W_0F11_P_3, 1363 VEX_W_0F12_P_0_M_0, 1364 VEX_W_0F12_P_0_M_1, 1365 VEX_W_0F12_P_1, 1366 VEX_W_0F12_P_2, 1367 VEX_W_0F12_P_3, 1368 VEX_W_0F13_M_0, 1369 VEX_W_0F14, 1370 VEX_W_0F15, 1371 VEX_W_0F16_P_0_M_0, 1372 VEX_W_0F16_P_0_M_1, 1373 VEX_W_0F16_P_1, 1374 VEX_W_0F16_P_2, 1375 VEX_W_0F17_M_0, 1376 VEX_W_0F28, 1377 VEX_W_0F29, 1378 VEX_W_0F2B_M_0, 1379 VEX_W_0F2E_P_0, 1380 VEX_W_0F2E_P_2, 1381 VEX_W_0F2F_P_0, 1382 VEX_W_0F2F_P_2, 1383 VEX_W_0F50_M_0, 1384 VEX_W_0F51_P_0, 1385 VEX_W_0F51_P_1, 1386 VEX_W_0F51_P_2, 1387 VEX_W_0F51_P_3, 1388 VEX_W_0F52_P_0, 1389 VEX_W_0F52_P_1, 1390 VEX_W_0F53_P_0, 1391 VEX_W_0F53_P_1, 1392 VEX_W_0F58_P_0, 1393 VEX_W_0F58_P_1, 1394 VEX_W_0F58_P_2, 1395 VEX_W_0F58_P_3, 1396 VEX_W_0F59_P_0, 1397 VEX_W_0F59_P_1, 1398 VEX_W_0F59_P_2, 1399 VEX_W_0F59_P_3, 1400 VEX_W_0F5A_P_0, 1401 VEX_W_0F5A_P_1, 1402 VEX_W_0F5A_P_3, 1403 VEX_W_0F5B_P_0, 1404 VEX_W_0F5B_P_1, 1405 VEX_W_0F5B_P_2, 1406 VEX_W_0F5C_P_0, 1407 VEX_W_0F5C_P_1, 1408 VEX_W_0F5C_P_2, 1409 VEX_W_0F5C_P_3, 1410 VEX_W_0F5D_P_0, 1411 VEX_W_0F5D_P_1, 1412 VEX_W_0F5D_P_2, 1413 VEX_W_0F5D_P_3, 1414 VEX_W_0F5E_P_0, 1415 VEX_W_0F5E_P_1, 1416 VEX_W_0F5E_P_2, 1417 VEX_W_0F5E_P_3, 1418 VEX_W_0F5F_P_0, 1419 VEX_W_0F5F_P_1, 1420 VEX_W_0F5F_P_2, 1421 VEX_W_0F5F_P_3, 1422 VEX_W_0F60_P_2, 1423 VEX_W_0F61_P_2, 1424 VEX_W_0F62_P_2, 1425 VEX_W_0F63_P_2, 1426 VEX_W_0F64_P_2, 1427 VEX_W_0F65_P_2, 1428 VEX_W_0F66_P_2, 1429 VEX_W_0F67_P_2, 1430 VEX_W_0F68_P_2, 1431 VEX_W_0F69_P_2, 1432 VEX_W_0F6A_P_2, 1433 VEX_W_0F6B_P_2, 1434 VEX_W_0F6C_P_2, 1435 VEX_W_0F6D_P_2, 1436 VEX_W_0F6F_P_1, 1437 VEX_W_0F6F_P_2, 1438 VEX_W_0F70_P_1, 1439 VEX_W_0F70_P_2, 1440 VEX_W_0F70_P_3, 1441 VEX_W_0F71_R_2_P_2, 1442 VEX_W_0F71_R_4_P_2, 1443 VEX_W_0F71_R_6_P_2, 1444 VEX_W_0F72_R_2_P_2, 1445 VEX_W_0F72_R_4_P_2, 1446 VEX_W_0F72_R_6_P_2, 1447 VEX_W_0F73_R_2_P_2, 1448 VEX_W_0F73_R_3_P_2, 1449 VEX_W_0F73_R_6_P_2, 1450 VEX_W_0F73_R_7_P_2, 1451 VEX_W_0F74_P_2, 1452 VEX_W_0F75_P_2, 1453 VEX_W_0F76_P_2, 1454 VEX_W_0F77_P_0, 1455 VEX_W_0F7C_P_2, 1456 VEX_W_0F7C_P_3, 1457 VEX_W_0F7D_P_2, 1458 VEX_W_0F7D_P_3, 1459 VEX_W_0F7E_P_1, 1460 VEX_W_0F7F_P_1, 1461 VEX_W_0F7F_P_2, 1462 VEX_W_0FAE_R_2_M_0, 1463 VEX_W_0FAE_R_3_M_0, 1464 VEX_W_0FC2_P_0, 1465 VEX_W_0FC2_P_1, 1466 VEX_W_0FC2_P_2, 1467 VEX_W_0FC2_P_3, 1468 VEX_W_0FC4_P_2, 1469 VEX_W_0FC5_P_2, 1470 VEX_W_0FD0_P_2, 1471 VEX_W_0FD0_P_3, 1472 VEX_W_0FD1_P_2, 1473 VEX_W_0FD2_P_2, 1474 VEX_W_0FD3_P_2, 1475 VEX_W_0FD4_P_2, 1476 VEX_W_0FD5_P_2, 1477 VEX_W_0FD6_P_2, 1478 VEX_W_0FD7_P_2_M_1, 1479 VEX_W_0FD8_P_2, 1480 VEX_W_0FD9_P_2, 1481 VEX_W_0FDA_P_2, 1482 VEX_W_0FDB_P_2, 1483 VEX_W_0FDC_P_2, 1484 VEX_W_0FDD_P_2, 1485 VEX_W_0FDE_P_2, 1486 VEX_W_0FDF_P_2, 1487 VEX_W_0FE0_P_2, 1488 VEX_W_0FE1_P_2, 1489 VEX_W_0FE2_P_2, 1490 VEX_W_0FE3_P_2, 1491 VEX_W_0FE4_P_2, 1492 VEX_W_0FE5_P_2, 1493 VEX_W_0FE6_P_1, 1494 VEX_W_0FE6_P_2, 1495 VEX_W_0FE6_P_3, 1496 VEX_W_0FE7_P_2_M_0, 1497 VEX_W_0FE8_P_2, 1498 VEX_W_0FE9_P_2, 1499 VEX_W_0FEA_P_2, 1500 VEX_W_0FEB_P_2, 1501 VEX_W_0FEC_P_2, 1502 VEX_W_0FED_P_2, 1503 VEX_W_0FEE_P_2, 1504 VEX_W_0FEF_P_2, 1505 VEX_W_0FF0_P_3_M_0, 1506 VEX_W_0FF1_P_2, 1507 VEX_W_0FF2_P_2, 1508 VEX_W_0FF3_P_2, 1509 VEX_W_0FF4_P_2, 1510 VEX_W_0FF5_P_2, 1511 VEX_W_0FF6_P_2, 1512 VEX_W_0FF7_P_2, 1513 VEX_W_0FF8_P_2, 1514 VEX_W_0FF9_P_2, 1515 VEX_W_0FFA_P_2, 1516 VEX_W_0FFB_P_2, 1517 VEX_W_0FFC_P_2, 1518 VEX_W_0FFD_P_2, 1519 VEX_W_0FFE_P_2, 1520 VEX_W_0F3800_P_2, 1521 VEX_W_0F3801_P_2, 1522 VEX_W_0F3802_P_2, 1523 VEX_W_0F3803_P_2, 1524 VEX_W_0F3804_P_2, 1525 VEX_W_0F3805_P_2, 1526 VEX_W_0F3806_P_2, 1527 VEX_W_0F3807_P_2, 1528 VEX_W_0F3808_P_2, 1529 VEX_W_0F3809_P_2, 1530 VEX_W_0F380A_P_2, 1531 VEX_W_0F380B_P_2, 1532 VEX_W_0F380C_P_2, 1533 VEX_W_0F380D_P_2, 1534 VEX_W_0F380E_P_2, 1535 VEX_W_0F380F_P_2, 1536 VEX_W_0F3817_P_2, 1537 VEX_W_0F3818_P_2_M_0, 1538 VEX_W_0F3819_P_2_M_0, 1539 VEX_W_0F381A_P_2_M_0, 1540 VEX_W_0F381C_P_2, 1541 VEX_W_0F381D_P_2, 1542 VEX_W_0F381E_P_2, 1543 VEX_W_0F3820_P_2, 1544 VEX_W_0F3821_P_2, 1545 VEX_W_0F3822_P_2, 1546 VEX_W_0F3823_P_2, 1547 VEX_W_0F3824_P_2, 1548 VEX_W_0F3825_P_2, 1549 VEX_W_0F3828_P_2, 1550 VEX_W_0F3829_P_2, 1551 VEX_W_0F382A_P_2_M_0, 1552 VEX_W_0F382B_P_2, 1553 VEX_W_0F382C_P_2_M_0, 1554 VEX_W_0F382D_P_2_M_0, 1555 VEX_W_0F382E_P_2_M_0, 1556 VEX_W_0F382F_P_2_M_0, 1557 VEX_W_0F3830_P_2, 1558 VEX_W_0F3831_P_2, 1559 VEX_W_0F3832_P_2, 1560 VEX_W_0F3833_P_2, 1561 VEX_W_0F3834_P_2, 1562 VEX_W_0F3835_P_2, 1563 VEX_W_0F3837_P_2, 1564 VEX_W_0F3838_P_2, 1565 VEX_W_0F3839_P_2, 1566 VEX_W_0F383A_P_2, 1567 VEX_W_0F383B_P_2, 1568 VEX_W_0F383C_P_2, 1569 VEX_W_0F383D_P_2, 1570 VEX_W_0F383E_P_2, 1571 VEX_W_0F383F_P_2, 1572 VEX_W_0F3840_P_2, 1573 VEX_W_0F3841_P_2, 1574 VEX_W_0F38DB_P_2, 1575 VEX_W_0F38DC_P_2, 1576 VEX_W_0F38DD_P_2, 1577 VEX_W_0F38DE_P_2, 1578 VEX_W_0F38DF_P_2, 1579 VEX_W_0F3A04_P_2, 1580 VEX_W_0F3A05_P_2, 1581 VEX_W_0F3A06_P_2, 1582 VEX_W_0F3A08_P_2, 1583 VEX_W_0F3A09_P_2, 1584 VEX_W_0F3A0A_P_2, 1585 VEX_W_0F3A0B_P_2, 1586 VEX_W_0F3A0C_P_2, 1587 VEX_W_0F3A0D_P_2, 1588 VEX_W_0F3A0E_P_2, 1589 VEX_W_0F3A0F_P_2, 1590 VEX_W_0F3A14_P_2, 1591 VEX_W_0F3A15_P_2, 1592 VEX_W_0F3A18_P_2, 1593 VEX_W_0F3A19_P_2, 1594 VEX_W_0F3A20_P_2, 1595 VEX_W_0F3A21_P_2, 1596 VEX_W_0F3A40_P_2, 1597 VEX_W_0F3A41_P_2, 1598 VEX_W_0F3A42_P_2, 1599 VEX_W_0F3A44_P_2, 1600 VEX_W_0F3A48_P_2, 1601 VEX_W_0F3A49_P_2, 1602 VEX_W_0F3A4A_P_2, 1603 VEX_W_0F3A4B_P_2, 1604 VEX_W_0F3A4C_P_2, 1605 VEX_W_0F3A60_P_2, 1606 VEX_W_0F3A61_P_2, 1607 VEX_W_0F3A62_P_2, 1608 VEX_W_0F3A63_P_2, 1609 VEX_W_0F3ADF_P_2 1610 }; 1611 1612 typedef void (*op_rtn) (int bytemode, int sizeflag); 1613 1614 struct dis386 { 1615 const char *name; 1616 struct 1617 { 1618 op_rtn rtn; 1619 int bytemode; 1620 } op[MAX_OPERANDS]; 1621 }; 1622 1623 /* Upper case letters in the instruction names here are macros. 1624 'A' => print 'b' if no register operands or suffix_always is true 1625 'B' => print 'b' if suffix_always is true 1626 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand 1627 size prefix 1628 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if 1629 suffix_always is true 1630 'E' => print 'e' if 32-bit form of jcxz 1631 'F' => print 'w' or 'l' depending on address size prefix (loop insns) 1632 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) 1633 'H' => print ",pt" or ",pn" branch hint 1634 'I' => honor following macro letter even in Intel mode (implemented only 1635 for some of the macro letters) 1636 'J' => print 'l' 1637 'K' => print 'd' or 'q' if rex prefix is present. 1638 'L' => print 'l' if suffix_always is true 1639 'M' => print 'r' if intel_mnemonic is false. 1640 'N' => print 'n' if instruction has no wait "prefix" 1641 'O' => print 'd' or 'o' (or 'q' in Intel mode) 1642 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, 1643 or suffix_always is true. print 'q' if rex prefix is present. 1644 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always 1645 is true 1646 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) 1647 'S' => print 'w', 'l' or 'q' if suffix_always is true 1648 'T' => print 'q' in 64bit mode and behave as 'P' otherwise 1649 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise 1650 'V' => print 'q' in 64bit mode and behave as 'S' otherwise 1651 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 1652 'X' => print 's', 'd' depending on data16 prefix (for XMM) 1653 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and 1654 suffix_always is true. 1655 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise 1656 '!' => change condition from true to false or from false to true. 1657 '%' => add 1 upper case letter to the macro. 1658 1659 2 upper case letter macros: 1660 "XY" => print 'x' or 'y' if no register operands or suffix_always 1661 is true. 1662 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) 1663 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand 1664 or suffix_always is true 1665 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise 1666 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise 1667 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise 1668 1669 Many of the above letters print nothing in Intel mode. See "putop" 1670 for the details. 1671 1672 Braces '{' and '}', and vertical bars '|', indicate alternative 1673 mnemonic strings for AT&T and Intel. */ 1674 1675 static const struct dis386 dis386[] = { 1676 /* 00 */ 1677 { "addB", { Eb, Gb } }, 1678 { "addS", { Ev, Gv } }, 1679 { "addB", { Gb, EbS } }, 1680 { "addS", { Gv, EvS } }, 1681 { "addB", { AL, Ib } }, 1682 { "addS", { eAX, Iv } }, 1683 { X86_64_TABLE (X86_64_06) }, 1684 { X86_64_TABLE (X86_64_07) }, 1685 /* 08 */ 1686 { "orB", { Eb, Gb } }, 1687 { "orS", { Ev, Gv } }, 1688 { "orB", { Gb, EbS } }, 1689 { "orS", { Gv, EvS } }, 1690 { "orB", { AL, Ib } }, 1691 { "orS", { eAX, Iv } }, 1692 { X86_64_TABLE (X86_64_0D) }, 1693 { Bad_Opcode }, /* 0x0f extended opcode escape */ 1694 /* 10 */ 1695 { "adcB", { Eb, Gb } }, 1696 { "adcS", { Ev, Gv } }, 1697 { "adcB", { Gb, EbS } }, 1698 { "adcS", { Gv, EvS } }, 1699 { "adcB", { AL, Ib } }, 1700 { "adcS", { eAX, Iv } }, 1701 { X86_64_TABLE (X86_64_16) }, 1702 { X86_64_TABLE (X86_64_17) }, 1703 /* 18 */ 1704 { "sbbB", { Eb, Gb } }, 1705 { "sbbS", { Ev, Gv } }, 1706 { "sbbB", { Gb, EbS } }, 1707 { "sbbS", { Gv, EvS } }, 1708 { "sbbB", { AL, Ib } }, 1709 { "sbbS", { eAX, Iv } }, 1710 { X86_64_TABLE (X86_64_1E) }, 1711 { X86_64_TABLE (X86_64_1F) }, 1712 /* 20 */ 1713 { "andB", { Eb, Gb } }, 1714 { "andS", { Ev, Gv } }, 1715 { "andB", { Gb, EbS } }, 1716 { "andS", { Gv, EvS } }, 1717 { "andB", { AL, Ib } }, 1718 { "andS", { eAX, Iv } }, 1719 { Bad_Opcode }, /* SEG ES prefix */ 1720 { X86_64_TABLE (X86_64_27) }, 1721 /* 28 */ 1722 { "subB", { Eb, Gb } }, 1723 { "subS", { Ev, Gv } }, 1724 { "subB", { Gb, EbS } }, 1725 { "subS", { Gv, EvS } }, 1726 { "subB", { AL, Ib } }, 1727 { "subS", { eAX, Iv } }, 1728 { Bad_Opcode }, /* SEG CS prefix */ 1729 { X86_64_TABLE (X86_64_2F) }, 1730 /* 30 */ 1731 { "xorB", { Eb, Gb } }, 1732 { "xorS", { Ev, Gv } }, 1733 { "xorB", { Gb, EbS } }, 1734 { "xorS", { Gv, EvS } }, 1735 { "xorB", { AL, Ib } }, 1736 { "xorS", { eAX, Iv } }, 1737 { Bad_Opcode }, /* SEG SS prefix */ 1738 { X86_64_TABLE (X86_64_37) }, 1739 /* 38 */ 1740 { "cmpB", { Eb, Gb } }, 1741 { "cmpS", { Ev, Gv } }, 1742 { "cmpB", { Gb, EbS } }, 1743 { "cmpS", { Gv, EvS } }, 1744 { "cmpB", { AL, Ib } }, 1745 { "cmpS", { eAX, Iv } }, 1746 { Bad_Opcode }, /* SEG DS prefix */ 1747 { X86_64_TABLE (X86_64_3F) }, 1748 /* 40 */ 1749 { "inc{S|}", { RMeAX } }, 1750 { "inc{S|}", { RMeCX } }, 1751 { "inc{S|}", { RMeDX } }, 1752 { "inc{S|}", { RMeBX } }, 1753 { "inc{S|}", { RMeSP } }, 1754 { "inc{S|}", { RMeBP } }, 1755 { "inc{S|}", { RMeSI } }, 1756 { "inc{S|}", { RMeDI } }, 1757 /* 48 */ 1758 { "dec{S|}", { RMeAX } }, 1759 { "dec{S|}", { RMeCX } }, 1760 { "dec{S|}", { RMeDX } }, 1761 { "dec{S|}", { RMeBX } }, 1762 { "dec{S|}", { RMeSP } }, 1763 { "dec{S|}", { RMeBP } }, 1764 { "dec{S|}", { RMeSI } }, 1765 { "dec{S|}", { RMeDI } }, 1766 /* 50 */ 1767 { "pushV", { RMrAX } }, 1768 { "pushV", { RMrCX } }, 1769 { "pushV", { RMrDX } }, 1770 { "pushV", { RMrBX } }, 1771 { "pushV", { RMrSP } }, 1772 { "pushV", { RMrBP } }, 1773 { "pushV", { RMrSI } }, 1774 { "pushV", { RMrDI } }, 1775 /* 58 */ 1776 { "popV", { RMrAX } }, 1777 { "popV", { RMrCX } }, 1778 { "popV", { RMrDX } }, 1779 { "popV", { RMrBX } }, 1780 { "popV", { RMrSP } }, 1781 { "popV", { RMrBP } }, 1782 { "popV", { RMrSI } }, 1783 { "popV", { RMrDI } }, 1784 /* 60 */ 1785 { X86_64_TABLE (X86_64_60) }, 1786 { X86_64_TABLE (X86_64_61) }, 1787 { X86_64_TABLE (X86_64_62) }, 1788 { X86_64_TABLE (X86_64_63) }, 1789 { Bad_Opcode }, /* seg fs */ 1790 { Bad_Opcode }, /* seg gs */ 1791 { Bad_Opcode }, /* op size prefix */ 1792 { Bad_Opcode }, /* adr size prefix */ 1793 /* 68 */ 1794 { "pushT", { sIv } }, 1795 { "imulS", { Gv, Ev, Iv } }, 1796 { "pushT", { sIbT } }, 1797 { "imulS", { Gv, Ev, sIb } }, 1798 { "ins{b|}", { Ybr, indirDX } }, 1799 { X86_64_TABLE (X86_64_6D) }, 1800 { "outs{b|}", { indirDXr, Xb } }, 1801 { X86_64_TABLE (X86_64_6F) }, 1802 /* 70 */ 1803 { "joH", { Jb, XX, cond_jump_flag } }, 1804 { "jnoH", { Jb, XX, cond_jump_flag } }, 1805 { "jbH", { Jb, XX, cond_jump_flag } }, 1806 { "jaeH", { Jb, XX, cond_jump_flag } }, 1807 { "jeH", { Jb, XX, cond_jump_flag } }, 1808 { "jneH", { Jb, XX, cond_jump_flag } }, 1809 { "jbeH", { Jb, XX, cond_jump_flag } }, 1810 { "jaH", { Jb, XX, cond_jump_flag } }, 1811 /* 78 */ 1812 { "jsH", { Jb, XX, cond_jump_flag } }, 1813 { "jnsH", { Jb, XX, cond_jump_flag } }, 1814 { "jpH", { Jb, XX, cond_jump_flag } }, 1815 { "jnpH", { Jb, XX, cond_jump_flag } }, 1816 { "jlH", { Jb, XX, cond_jump_flag } }, 1817 { "jgeH", { Jb, XX, cond_jump_flag } }, 1818 { "jleH", { Jb, XX, cond_jump_flag } }, 1819 { "jgH", { Jb, XX, cond_jump_flag } }, 1820 /* 80 */ 1821 { REG_TABLE (REG_80) }, 1822 { REG_TABLE (REG_81) }, 1823 { Bad_Opcode }, 1824 { REG_TABLE (REG_82) }, 1825 { "testB", { Eb, Gb } }, 1826 { "testS", { Ev, Gv } }, 1827 { "xchgB", { Eb, Gb } }, 1828 { "xchgS", { Ev, Gv } }, 1829 /* 88 */ 1830 { "movB", { Eb, Gb } }, 1831 { "movS", { Ev, Gv } }, 1832 { "movB", { Gb, EbS } }, 1833 { "movS", { Gv, EvS } }, 1834 { "movD", { Sv, Sw } }, 1835 { MOD_TABLE (MOD_8D) }, 1836 { "movD", { Sw, Sv } }, 1837 { REG_TABLE (REG_8F) }, 1838 /* 90 */ 1839 { PREFIX_TABLE (PREFIX_90) }, 1840 { "xchgS", { RMeCX, eAX } }, 1841 { "xchgS", { RMeDX, eAX } }, 1842 { "xchgS", { RMeBX, eAX } }, 1843 { "xchgS", { RMeSP, eAX } }, 1844 { "xchgS", { RMeBP, eAX } }, 1845 { "xchgS", { RMeSI, eAX } }, 1846 { "xchgS", { RMeDI, eAX } }, 1847 /* 98 */ 1848 { "cW{t|}R", { XX } }, 1849 { "cR{t|}O", { XX } }, 1850 { X86_64_TABLE (X86_64_9A) }, 1851 { Bad_Opcode }, /* fwait */ 1852 { "pushfT", { XX } }, 1853 { "popfT", { XX } }, 1854 { "sahf", { XX } }, 1855 { "lahf", { XX } }, 1856 /* a0 */ 1857 { "mov%LB", { AL, Ob } }, 1858 { "mov%LS", { eAX, Ov } }, 1859 { "mov%LB", { Ob, AL } }, 1860 { "mov%LS", { Ov, eAX } }, 1861 { "movs{b|}", { Ybr, Xb } }, 1862 { "movs{R|}", { Yvr, Xv } }, 1863 { "cmps{b|}", { Xb, Yb } }, 1864 { "cmps{R|}", { Xv, Yv } }, 1865 /* a8 */ 1866 { "testB", { AL, Ib } }, 1867 { "testS", { eAX, Iv } }, 1868 { "stosB", { Ybr, AL } }, 1869 { "stosS", { Yvr, eAX } }, 1870 { "lodsB", { ALr, Xb } }, 1871 { "lodsS", { eAXr, Xv } }, 1872 { "scasB", { AL, Yb } }, 1873 { "scasS", { eAX, Yv } }, 1874 /* b0 */ 1875 { "movB", { RMAL, Ib } }, 1876 { "movB", { RMCL, Ib } }, 1877 { "movB", { RMDL, Ib } }, 1878 { "movB", { RMBL, Ib } }, 1879 { "movB", { RMAH, Ib } }, 1880 { "movB", { RMCH, Ib } }, 1881 { "movB", { RMDH, Ib } }, 1882 { "movB", { RMBH, Ib } }, 1883 /* b8 */ 1884 { "mov%LV", { RMeAX, Iv64 } }, 1885 { "mov%LV", { RMeCX, Iv64 } }, 1886 { "mov%LV", { RMeDX, Iv64 } }, 1887 { "mov%LV", { RMeBX, Iv64 } }, 1888 { "mov%LV", { RMeSP, Iv64 } }, 1889 { "mov%LV", { RMeBP, Iv64 } }, 1890 { "mov%LV", { RMeSI, Iv64 } }, 1891 { "mov%LV", { RMeDI, Iv64 } }, 1892 /* c0 */ 1893 { REG_TABLE (REG_C0) }, 1894 { REG_TABLE (REG_C1) }, 1895 { "retT", { Iw } }, 1896 { "retT", { XX } }, 1897 { X86_64_TABLE (X86_64_C4) }, 1898 { X86_64_TABLE (X86_64_C5) }, 1899 { REG_TABLE (REG_C6) }, 1900 { REG_TABLE (REG_C7) }, 1901 /* c8 */ 1902 { "enterT", { Iw, Ib } }, 1903 { "leaveT", { XX } }, 1904 { "Jret{|f}P", { Iw } }, 1905 { "Jret{|f}P", { XX } }, 1906 { "int3", { XX } }, 1907 { "int", { Ib } }, 1908 { X86_64_TABLE (X86_64_CE) }, 1909 { "iretP", { XX } }, 1910 /* d0 */ 1911 { REG_TABLE (REG_D0) }, 1912 { REG_TABLE (REG_D1) }, 1913 { REG_TABLE (REG_D2) }, 1914 { REG_TABLE (REG_D3) }, 1915 { X86_64_TABLE (X86_64_D4) }, 1916 { X86_64_TABLE (X86_64_D5) }, 1917 { Bad_Opcode }, 1918 { "xlat", { DSBX } }, 1919 /* d8 */ 1920 { FLOAT }, 1921 { FLOAT }, 1922 { FLOAT }, 1923 { FLOAT }, 1924 { FLOAT }, 1925 { FLOAT }, 1926 { FLOAT }, 1927 { FLOAT }, 1928 /* e0 */ 1929 { "loopneFH", { Jb, XX, loop_jcxz_flag } }, 1930 { "loopeFH", { Jb, XX, loop_jcxz_flag } }, 1931 { "loopFH", { Jb, XX, loop_jcxz_flag } }, 1932 { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, 1933 { "inB", { AL, Ib } }, 1934 { "inG", { zAX, Ib } }, 1935 { "outB", { Ib, AL } }, 1936 { "outG", { Ib, zAX } }, 1937 /* e8 */ 1938 { "callT", { Jv } }, 1939 { "jmpT", { Jv } }, 1940 { X86_64_TABLE (X86_64_EA) }, 1941 { "jmp", { Jb } }, 1942 { "inB", { AL, indirDX } }, 1943 { "inG", { zAX, indirDX } }, 1944 { "outB", { indirDX, AL } }, 1945 { "outG", { indirDX, zAX } }, 1946 /* f0 */ 1947 { Bad_Opcode }, /* lock prefix */ 1948 { "icebp", { XX } }, 1949 { Bad_Opcode }, /* repne */ 1950 { Bad_Opcode }, /* repz */ 1951 { "hlt", { XX } }, 1952 { "cmc", { XX } }, 1953 { REG_TABLE (REG_F6) }, 1954 { REG_TABLE (REG_F7) }, 1955 /* f8 */ 1956 { "clc", { XX } }, 1957 { "stc", { XX } }, 1958 { "cli", { XX } }, 1959 { "sti", { XX } }, 1960 { "cld", { XX } }, 1961 { "std", { XX } }, 1962 { REG_TABLE (REG_FE) }, 1963 { REG_TABLE (REG_FF) }, 1964 }; 1965 1966 static const struct dis386 dis386_twobyte[] = { 1967 /* 00 */ 1968 { REG_TABLE (REG_0F00 ) }, 1969 { REG_TABLE (REG_0F01 ) }, 1970 { "larS", { Gv, Ew } }, 1971 { "lslS", { Gv, Ew } }, 1972 { Bad_Opcode }, 1973 { "syscall", { XX } }, 1974 { "clts", { XX } }, 1975 { "sysretP", { XX } }, 1976 /* 08 */ 1977 { "invd", { XX } }, 1978 { "wbinvd", { XX } }, 1979 { Bad_Opcode }, 1980 { "ud2", { XX } }, 1981 { Bad_Opcode }, 1982 { REG_TABLE (REG_0F0D) }, 1983 { "femms", { XX } }, 1984 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ 1985 /* 10 */ 1986 { PREFIX_TABLE (PREFIX_0F10) }, 1987 { PREFIX_TABLE (PREFIX_0F11) }, 1988 { PREFIX_TABLE (PREFIX_0F12) }, 1989 { MOD_TABLE (MOD_0F13) }, 1990 { "unpcklpX", { XM, EXx } }, 1991 { "unpckhpX", { XM, EXx } }, 1992 { PREFIX_TABLE (PREFIX_0F16) }, 1993 { MOD_TABLE (MOD_0F17) }, 1994 /* 18 */ 1995 { REG_TABLE (REG_0F18) }, 1996 { "nopQ", { Ev } }, 1997 { "nopQ", { Ev } }, 1998 { "nopQ", { Ev } }, 1999 { "nopQ", { Ev } }, 2000 { "nopQ", { Ev } }, 2001 { "nopQ", { Ev } }, 2002 { "nopQ", { Ev } }, 2003 /* 20 */ 2004 { MOD_TABLE (MOD_0F20) }, 2005 { MOD_TABLE (MOD_0F21) }, 2006 { MOD_TABLE (MOD_0F22) }, 2007 { MOD_TABLE (MOD_0F23) }, 2008 { MOD_TABLE (MOD_0F24) }, 2009 { Bad_Opcode }, 2010 { MOD_TABLE (MOD_0F26) }, 2011 { Bad_Opcode }, 2012 /* 28 */ 2013 { "movapX", { XM, EXx } }, 2014 { "movapX", { EXxS, XM } }, 2015 { PREFIX_TABLE (PREFIX_0F2A) }, 2016 { PREFIX_TABLE (PREFIX_0F2B) }, 2017 { PREFIX_TABLE (PREFIX_0F2C) }, 2018 { PREFIX_TABLE (PREFIX_0F2D) }, 2019 { PREFIX_TABLE (PREFIX_0F2E) }, 2020 { PREFIX_TABLE (PREFIX_0F2F) }, 2021 /* 30 */ 2022 { "wrmsr", { XX } }, 2023 { "rdtsc", { XX } }, 2024 { "rdmsr", { XX } }, 2025 { "rdpmc", { XX } }, 2026 { "sysenter", { XX } }, 2027 { "sysexit", { XX } }, 2028 { Bad_Opcode }, 2029 { "getsec", { XX } }, 2030 /* 38 */ 2031 { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, 2032 { Bad_Opcode }, 2033 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, 2034 { Bad_Opcode }, 2035 { Bad_Opcode }, 2036 { Bad_Opcode }, 2037 { Bad_Opcode }, 2038 { Bad_Opcode }, 2039 /* 40 */ 2040 { "cmovoS", { Gv, Ev } }, 2041 { "cmovnoS", { Gv, Ev } }, 2042 { "cmovbS", { Gv, Ev } }, 2043 { "cmovaeS", { Gv, Ev } }, 2044 { "cmoveS", { Gv, Ev } }, 2045 { "cmovneS", { Gv, Ev } }, 2046 { "cmovbeS", { Gv, Ev } }, 2047 { "cmovaS", { Gv, Ev } }, 2048 /* 48 */ 2049 { "cmovsS", { Gv, Ev } }, 2050 { "cmovnsS", { Gv, Ev } }, 2051 { "cmovpS", { Gv, Ev } }, 2052 { "cmovnpS", { Gv, Ev } }, 2053 { "cmovlS", { Gv, Ev } }, 2054 { "cmovgeS", { Gv, Ev } }, 2055 { "cmovleS", { Gv, Ev } }, 2056 { "cmovgS", { Gv, Ev } }, 2057 /* 50 */ 2058 { MOD_TABLE (MOD_0F51) }, 2059 { PREFIX_TABLE (PREFIX_0F51) }, 2060 { PREFIX_TABLE (PREFIX_0F52) }, 2061 { PREFIX_TABLE (PREFIX_0F53) }, 2062 { "andpX", { XM, EXx } }, 2063 { "andnpX", { XM, EXx } }, 2064 { "orpX", { XM, EXx } }, 2065 { "xorpX", { XM, EXx } }, 2066 /* 58 */ 2067 { PREFIX_TABLE (PREFIX_0F58) }, 2068 { PREFIX_TABLE (PREFIX_0F59) }, 2069 { PREFIX_TABLE (PREFIX_0F5A) }, 2070 { PREFIX_TABLE (PREFIX_0F5B) }, 2071 { PREFIX_TABLE (PREFIX_0F5C) }, 2072 { PREFIX_TABLE (PREFIX_0F5D) }, 2073 { PREFIX_TABLE (PREFIX_0F5E) }, 2074 { PREFIX_TABLE (PREFIX_0F5F) }, 2075 /* 60 */ 2076 { PREFIX_TABLE (PREFIX_0F60) }, 2077 { PREFIX_TABLE (PREFIX_0F61) }, 2078 { PREFIX_TABLE (PREFIX_0F62) }, 2079 { "packsswb", { MX, EM } }, 2080 { "pcmpgtb", { MX, EM } }, 2081 { "pcmpgtw", { MX, EM } }, 2082 { "pcmpgtd", { MX, EM } }, 2083 { "packuswb", { MX, EM } }, 2084 /* 68 */ 2085 { "punpckhbw", { MX, EM } }, 2086 { "punpckhwd", { MX, EM } }, 2087 { "punpckhdq", { MX, EM } }, 2088 { "packssdw", { MX, EM } }, 2089 { PREFIX_TABLE (PREFIX_0F6C) }, 2090 { PREFIX_TABLE (PREFIX_0F6D) }, 2091 { "movK", { MX, Edq } }, 2092 { PREFIX_TABLE (PREFIX_0F6F) }, 2093 /* 70 */ 2094 { PREFIX_TABLE (PREFIX_0F70) }, 2095 { REG_TABLE (REG_0F71) }, 2096 { REG_TABLE (REG_0F72) }, 2097 { REG_TABLE (REG_0F73) }, 2098 { "pcmpeqb", { MX, EM } }, 2099 { "pcmpeqw", { MX, EM } }, 2100 { "pcmpeqd", { MX, EM } }, 2101 { "emms", { XX } }, 2102 /* 78 */ 2103 { PREFIX_TABLE (PREFIX_0F78) }, 2104 { PREFIX_TABLE (PREFIX_0F79) }, 2105 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, 2106 { Bad_Opcode }, 2107 { PREFIX_TABLE (PREFIX_0F7C) }, 2108 { PREFIX_TABLE (PREFIX_0F7D) }, 2109 { PREFIX_TABLE (PREFIX_0F7E) }, 2110 { PREFIX_TABLE (PREFIX_0F7F) }, 2111 /* 80 */ 2112 { "joH", { Jv, XX, cond_jump_flag } }, 2113 { "jnoH", { Jv, XX, cond_jump_flag } }, 2114 { "jbH", { Jv, XX, cond_jump_flag } }, 2115 { "jaeH", { Jv, XX, cond_jump_flag } }, 2116 { "jeH", { Jv, XX, cond_jump_flag } }, 2117 { "jneH", { Jv, XX, cond_jump_flag } }, 2118 { "jbeH", { Jv, XX, cond_jump_flag } }, 2119 { "jaH", { Jv, XX, cond_jump_flag } }, 2120 /* 88 */ 2121 { "jsH", { Jv, XX, cond_jump_flag } }, 2122 { "jnsH", { Jv, XX, cond_jump_flag } }, 2123 { "jpH", { Jv, XX, cond_jump_flag } }, 2124 { "jnpH", { Jv, XX, cond_jump_flag } }, 2125 { "jlH", { Jv, XX, cond_jump_flag } }, 2126 { "jgeH", { Jv, XX, cond_jump_flag } }, 2127 { "jleH", { Jv, XX, cond_jump_flag } }, 2128 { "jgH", { Jv, XX, cond_jump_flag } }, 2129 /* 90 */ 2130 { "seto", { Eb } }, 2131 { "setno", { Eb } }, 2132 { "setb", { Eb } }, 2133 { "setae", { Eb } }, 2134 { "sete", { Eb } }, 2135 { "setne", { Eb } }, 2136 { "setbe", { Eb } }, 2137 { "seta", { Eb } }, 2138 /* 98 */ 2139 { "sets", { Eb } }, 2140 { "setns", { Eb } }, 2141 { "setp", { Eb } }, 2142 { "setnp", { Eb } }, 2143 { "setl", { Eb } }, 2144 { "setge", { Eb } }, 2145 { "setle", { Eb } }, 2146 { "setg", { Eb } }, 2147 /* a0 */ 2148 { "pushT", { fs } }, 2149 { "popT", { fs } }, 2150 { "cpuid", { XX } }, 2151 { "btS", { Ev, Gv } }, 2152 { "shldS", { Ev, Gv, Ib } }, 2153 { "shldS", { Ev, Gv, CL } }, 2154 { REG_TABLE (REG_0FA6) }, 2155 { REG_TABLE (REG_0FA7) }, 2156 /* a8 */ 2157 { "pushT", { gs } }, 2158 { "popT", { gs } }, 2159 { "rsm", { XX } }, 2160 { "btsS", { Ev, Gv } }, 2161 { "shrdS", { Ev, Gv, Ib } }, 2162 { "shrdS", { Ev, Gv, CL } }, 2163 { REG_TABLE (REG_0FAE) }, 2164 { "imulS", { Gv, Ev } }, 2165 /* b0 */ 2166 { "cmpxchgB", { Eb, Gb } }, 2167 { "cmpxchgS", { Ev, Gv } }, 2168 { MOD_TABLE (MOD_0FB2) }, 2169 { "btrS", { Ev, Gv } }, 2170 { MOD_TABLE (MOD_0FB4) }, 2171 { MOD_TABLE (MOD_0FB5) }, 2172 { "movz{bR|x}", { Gv, Eb } }, 2173 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ 2174 /* b8 */ 2175 { PREFIX_TABLE (PREFIX_0FB8) }, 2176 { "ud1", { XX } }, 2177 { REG_TABLE (REG_0FBA) }, 2178 { "btcS", { Ev, Gv } }, 2179 { PREFIX_TABLE (PREFIX_0FBC) }, 2180 { PREFIX_TABLE (PREFIX_0FBD) }, 2181 { "movs{bR|x}", { Gv, Eb } }, 2182 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ 2183 /* c0 */ 2184 { "xaddB", { Eb, Gb } }, 2185 { "xaddS", { Ev, Gv } }, 2186 { PREFIX_TABLE (PREFIX_0FC2) }, 2187 { PREFIX_TABLE (PREFIX_0FC3) }, 2188 { "pinsrw", { MX, Edqw, Ib } }, 2189 { "pextrw", { Gdq, MS, Ib } }, 2190 { "shufpX", { XM, EXx, Ib } }, 2191 { REG_TABLE (REG_0FC7) }, 2192 /* c8 */ 2193 { "bswap", { RMeAX } }, 2194 { "bswap", { RMeCX } }, 2195 { "bswap", { RMeDX } }, 2196 { "bswap", { RMeBX } }, 2197 { "bswap", { RMeSP } }, 2198 { "bswap", { RMeBP } }, 2199 { "bswap", { RMeSI } }, 2200 { "bswap", { RMeDI } }, 2201 /* d0 */ 2202 { PREFIX_TABLE (PREFIX_0FD0) }, 2203 { "psrlw", { MX, EM } }, 2204 { "psrld", { MX, EM } }, 2205 { "psrlq", { MX, EM } }, 2206 { "paddq", { MX, EM } }, 2207 { "pmullw", { MX, EM } }, 2208 { PREFIX_TABLE (PREFIX_0FD6) }, 2209 { MOD_TABLE (MOD_0FD7) }, 2210 /* d8 */ 2211 { "psubusb", { MX, EM } }, 2212 { "psubusw", { MX, EM } }, 2213 { "pminub", { MX, EM } }, 2214 { "pand", { MX, EM } }, 2215 { "paddusb", { MX, EM } }, 2216 { "paddusw", { MX, EM } }, 2217 { "pmaxub", { MX, EM } }, 2218 { "pandn", { MX, EM } }, 2219 /* e0 */ 2220 { "pavgb", { MX, EM } }, 2221 { "psraw", { MX, EM } }, 2222 { "psrad", { MX, EM } }, 2223 { "pavgw", { MX, EM } }, 2224 { "pmulhuw", { MX, EM } }, 2225 { "pmulhw", { MX, EM } }, 2226 { PREFIX_TABLE (PREFIX_0FE6) }, 2227 { PREFIX_TABLE (PREFIX_0FE7) }, 2228 /* e8 */ 2229 { "psubsb", { MX, EM } }, 2230 { "psubsw", { MX, EM } }, 2231 { "pminsw", { MX, EM } }, 2232 { "por", { MX, EM } }, 2233 { "paddsb", { MX, EM } }, 2234 { "paddsw", { MX, EM } }, 2235 { "pmaxsw", { MX, EM } }, 2236 { "pxor", { MX, EM } }, 2237 /* f0 */ 2238 { PREFIX_TABLE (PREFIX_0FF0) }, 2239 { "psllw", { MX, EM } }, 2240 { "pslld", { MX, EM } }, 2241 { "psllq", { MX, EM } }, 2242 { "pmuludq", { MX, EM } }, 2243 { "pmaddwd", { MX, EM } }, 2244 { "psadbw", { MX, EM } }, 2245 { PREFIX_TABLE (PREFIX_0FF7) }, 2246 /* f8 */ 2247 { "psubb", { MX, EM } }, 2248 { "psubw", { MX, EM } }, 2249 { "psubd", { MX, EM } }, 2250 { "psubq", { MX, EM } }, 2251 { "paddb", { MX, EM } }, 2252 { "paddw", { MX, EM } }, 2253 { "paddd", { MX, EM } }, 2254 { Bad_Opcode }, 2255 }; 2256 2257 static const unsigned char onebyte_has_modrm[256] = { 2258 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2259 /* ------------------------------- */ 2260 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ 2261 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ 2262 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ 2263 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ 2264 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ 2265 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ 2266 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ 2267 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ 2268 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ 2269 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ 2270 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ 2271 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ 2272 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ 2273 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ 2274 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ 2275 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ 2276 /* ------------------------------- */ 2277 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2278 }; 2279 2280 static const unsigned char twobyte_has_modrm[256] = { 2281 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2282 /* ------------------------------- */ 2283 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ 2284 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ 2285 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ 2286 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 2287 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ 2288 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 2289 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 2290 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ 2291 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 2292 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ 2293 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ 2294 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ 2295 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ 2296 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 2297 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 2298 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ 2299 /* ------------------------------- */ 2300 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 2301 }; 2302 2303 static char obuf[100]; 2304 static char *obufp; 2305 static char *mnemonicendp; 2306 static char scratchbuf[100]; 2307 static unsigned char *start_codep; 2308 static unsigned char *insn_codep; 2309 static unsigned char *codep; 2310 static int last_lock_prefix; 2311 static int last_repz_prefix; 2312 static int last_repnz_prefix; 2313 static int last_data_prefix; 2314 static int last_addr_prefix; 2315 static int last_rex_prefix; 2316 static int last_seg_prefix; 2317 #define MAX_CODE_LENGTH 15 2318 /* We can up to 14 prefixes since the maximum instruction length is 2319 15bytes. */ 2320 static int all_prefixes[MAX_CODE_LENGTH - 1]; 2321 static disassemble_info *the_info; 2322 static struct 2323 { 2324 int mod; 2325 int reg; 2326 int rm; 2327 } 2328 modrm; 2329 static unsigned char need_modrm; 2330 static struct 2331 { 2332 int scale; 2333 int index; 2334 int base; 2335 } 2336 sib; 2337 static struct 2338 { 2339 int register_specifier; 2340 int length; 2341 int prefix; 2342 int w; 2343 } 2344 vex; 2345 static unsigned char need_vex; 2346 static unsigned char need_vex_reg; 2347 static unsigned char vex_w_done; 2348 2349 struct op 2350 { 2351 const char *name; 2352 unsigned int len; 2353 }; 2354 2355 /* If we are accessing mod/rm/reg without need_modrm set, then the 2356 values are stale. Hitting this abort likely indicates that you 2357 need to update onebyte_has_modrm or twobyte_has_modrm. */ 2358 #define MODRM_CHECK if (!need_modrm) abort () 2359 2360 static const char **names64; 2361 static const char **names32; 2362 static const char **names16; 2363 static const char **names8; 2364 static const char **names8rex; 2365 static const char **names_seg; 2366 static const char *index64; 2367 static const char *index32; 2368 static const char **index16; 2369 2370 static const char *intel_names64[] = { 2371 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", 2372 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 2373 }; 2374 static const char *intel_names32[] = { 2375 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", 2376 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" 2377 }; 2378 static const char *intel_names16[] = { 2379 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", 2380 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" 2381 }; 2382 static const char *intel_names8[] = { 2383 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", 2384 }; 2385 static const char *intel_names8rex[] = { 2386 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", 2387 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" 2388 }; 2389 static const char *intel_names_seg[] = { 2390 "es", "cs", "ss", "ds", "fs", "gs", "?", "?", 2391 }; 2392 static const char *intel_index64 = "riz"; 2393 static const char *intel_index32 = "eiz"; 2394 static const char *intel_index16[] = { 2395 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" 2396 }; 2397 2398 static const char *att_names64[] = { 2399 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 2400 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 2401 }; 2402 static const char *att_names32[] = { 2403 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 2404 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 2405 }; 2406 static const char *att_names16[] = { 2407 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 2408 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 2409 }; 2410 static const char *att_names8[] = { 2411 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 2412 }; 2413 static const char *att_names8rex[] = { 2414 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 2415 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 2416 }; 2417 static const char *att_names_seg[] = { 2418 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", 2419 }; 2420 static const char *att_index64 = "%riz"; 2421 static const char *att_index32 = "%eiz"; 2422 static const char *att_index16[] = { 2423 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" 2424 }; 2425 2426 static const char **names_mm; 2427 static const char *intel_names_mm[] = { 2428 "mm0", "mm1", "mm2", "mm3", 2429 "mm4", "mm5", "mm6", "mm7" 2430 }; 2431 static const char *att_names_mm[] = { 2432 "%mm0", "%mm1", "%mm2", "%mm3", 2433 "%mm4", "%mm5", "%mm6", "%mm7" 2434 }; 2435 2436 static const char **names_xmm; 2437 static const char *intel_names_xmm[] = { 2438 "xmm0", "xmm1", "xmm2", "xmm3", 2439 "xmm4", "xmm5", "xmm6", "xmm7", 2440 "xmm8", "xmm9", "xmm10", "xmm11", 2441 "xmm12", "xmm13", "xmm14", "xmm15" 2442 }; 2443 static const char *att_names_xmm[] = { 2444 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 2445 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 2446 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 2447 "%xmm12", "%xmm13", "%xmm14", "%xmm15" 2448 }; 2449 2450 static const char **names_ymm; 2451 static const char *intel_names_ymm[] = { 2452 "ymm0", "ymm1", "ymm2", "ymm3", 2453 "ymm4", "ymm5", "ymm6", "ymm7", 2454 "ymm8", "ymm9", "ymm10", "ymm11", 2455 "ymm12", "ymm13", "ymm14", "ymm15" 2456 }; 2457 static const char *att_names_ymm[] = { 2458 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 2459 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 2460 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 2461 "%ymm12", "%ymm13", "%ymm14", "%ymm15" 2462 }; 2463 2464 static const struct dis386 reg_table[][8] = { 2465 /* REG_80 */ 2466 { 2467 { "addA", { Eb, Ib } }, 2468 { "orA", { Eb, Ib } }, 2469 { "adcA", { Eb, Ib } }, 2470 { "sbbA", { Eb, Ib } }, 2471 { "andA", { Eb, Ib } }, 2472 { "subA", { Eb, Ib } }, 2473 { "xorA", { Eb, Ib } }, 2474 { "cmpA", { Eb, Ib } }, 2475 }, 2476 /* REG_81 */ 2477 { 2478 { "addQ", { Ev, Iv } }, 2479 { "orQ", { Ev, Iv } }, 2480 { "adcQ", { Ev, Iv } }, 2481 { "sbbQ", { Ev, Iv } }, 2482 { "andQ", { Ev, Iv } }, 2483 { "subQ", { Ev, Iv } }, 2484 { "xorQ", { Ev, Iv } }, 2485 { "cmpQ", { Ev, Iv } }, 2486 }, 2487 /* REG_82 */ 2488 { 2489 { "addQ", { Ev, sIb } }, 2490 { "orQ", { Ev, sIb } }, 2491 { "adcQ", { Ev, sIb } }, 2492 { "sbbQ", { Ev, sIb } }, 2493 { "andQ", { Ev, sIb } }, 2494 { "subQ", { Ev, sIb } }, 2495 { "xorQ", { Ev, sIb } }, 2496 { "cmpQ", { Ev, sIb } }, 2497 }, 2498 /* REG_8F */ 2499 { 2500 { "popU", { stackEv } }, 2501 { XOP_8F_TABLE (XOP_09) }, 2502 { Bad_Opcode }, 2503 { Bad_Opcode }, 2504 { Bad_Opcode }, 2505 { XOP_8F_TABLE (XOP_09) }, 2506 }, 2507 /* REG_C0 */ 2508 { 2509 { "rolA", { Eb, Ib } }, 2510 { "rorA", { Eb, Ib } }, 2511 { "rclA", { Eb, Ib } }, 2512 { "rcrA", { Eb, Ib } }, 2513 { "shlA", { Eb, Ib } }, 2514 { "shrA", { Eb, Ib } }, 2515 { Bad_Opcode }, 2516 { "sarA", { Eb, Ib } }, 2517 }, 2518 /* REG_C1 */ 2519 { 2520 { "rolQ", { Ev, Ib } }, 2521 { "rorQ", { Ev, Ib } }, 2522 { "rclQ", { Ev, Ib } }, 2523 { "rcrQ", { Ev, Ib } }, 2524 { "shlQ", { Ev, Ib } }, 2525 { "shrQ", { Ev, Ib } }, 2526 { Bad_Opcode }, 2527 { "sarQ", { Ev, Ib } }, 2528 }, 2529 /* REG_C6 */ 2530 { 2531 { "movA", { Eb, Ib } }, 2532 }, 2533 /* REG_C7 */ 2534 { 2535 { "movQ", { Ev, Iv } }, 2536 }, 2537 /* REG_D0 */ 2538 { 2539 { "rolA", { Eb, I1 } }, 2540 { "rorA", { Eb, I1 } }, 2541 { "rclA", { Eb, I1 } }, 2542 { "rcrA", { Eb, I1 } }, 2543 { "shlA", { Eb, I1 } }, 2544 { "shrA", { Eb, I1 } }, 2545 { Bad_Opcode }, 2546 { "sarA", { Eb, I1 } }, 2547 }, 2548 /* REG_D1 */ 2549 { 2550 { "rolQ", { Ev, I1 } }, 2551 { "rorQ", { Ev, I1 } }, 2552 { "rclQ", { Ev, I1 } }, 2553 { "rcrQ", { Ev, I1 } }, 2554 { "shlQ", { Ev, I1 } }, 2555 { "shrQ", { Ev, I1 } }, 2556 { Bad_Opcode }, 2557 { "sarQ", { Ev, I1 } }, 2558 }, 2559 /* REG_D2 */ 2560 { 2561 { "rolA", { Eb, CL } }, 2562 { "rorA", { Eb, CL } }, 2563 { "rclA", { Eb, CL } }, 2564 { "rcrA", { Eb, CL } }, 2565 { "shlA", { Eb, CL } }, 2566 { "shrA", { Eb, CL } }, 2567 { Bad_Opcode }, 2568 { "sarA", { Eb, CL } }, 2569 }, 2570 /* REG_D3 */ 2571 { 2572 { "rolQ", { Ev, CL } }, 2573 { "rorQ", { Ev, CL } }, 2574 { "rclQ", { Ev, CL } }, 2575 { "rcrQ", { Ev, CL } }, 2576 { "shlQ", { Ev, CL } }, 2577 { "shrQ", { Ev, CL } }, 2578 { Bad_Opcode }, 2579 { "sarQ", { Ev, CL } }, 2580 }, 2581 /* REG_F6 */ 2582 { 2583 { "testA", { Eb, Ib } }, 2584 { Bad_Opcode }, 2585 { "notA", { Eb } }, 2586 { "negA", { Eb } }, 2587 { "mulA", { Eb } }, /* Don't print the implicit %al register, */ 2588 { "imulA", { Eb } }, /* to distinguish these opcodes from other */ 2589 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ 2590 { "idivA", { Eb } }, /* and idiv for consistency. */ 2591 }, 2592 /* REG_F7 */ 2593 { 2594 { "testQ", { Ev, Iv } }, 2595 { Bad_Opcode }, 2596 { "notQ", { Ev } }, 2597 { "negQ", { Ev } }, 2598 { "mulQ", { Ev } }, /* Don't print the implicit register. */ 2599 { "imulQ", { Ev } }, 2600 { "divQ", { Ev } }, 2601 { "idivQ", { Ev } }, 2602 }, 2603 /* REG_FE */ 2604 { 2605 { "incA", { Eb } }, 2606 { "decA", { Eb } }, 2607 }, 2608 /* REG_FF */ 2609 { 2610 { "incQ", { Ev } }, 2611 { "decQ", { Ev } }, 2612 { "call{T|}", { indirEv } }, 2613 { "Jcall{T|}", { indirEp } }, 2614 { "jmp{T|}", { indirEv } }, 2615 { "Jjmp{T|}", { indirEp } }, 2616 { "pushU", { stackEv } }, 2617 { Bad_Opcode }, 2618 }, 2619 /* REG_0F00 */ 2620 { 2621 { "sldtD", { Sv } }, 2622 { "strD", { Sv } }, 2623 { "lldt", { Ew } }, 2624 { "ltr", { Ew } }, 2625 { "verr", { Ew } }, 2626 { "verw", { Ew } }, 2627 { Bad_Opcode }, 2628 { Bad_Opcode }, 2629 }, 2630 /* REG_0F01 */ 2631 { 2632 { MOD_TABLE (MOD_0F01_REG_0) }, 2633 { MOD_TABLE (MOD_0F01_REG_1) }, 2634 { MOD_TABLE (MOD_0F01_REG_2) }, 2635 { MOD_TABLE (MOD_0F01_REG_3) }, 2636 { "smswD", { Sv } }, 2637 { Bad_Opcode }, 2638 { "lmsw", { Ew } }, 2639 { MOD_TABLE (MOD_0F01_REG_7) }, 2640 }, 2641 /* REG_0F0D */ 2642 { 2643 { "prefetch", { Mb } }, 2644 { "prefetchw", { Mb } }, 2645 }, 2646 /* REG_0F18 */ 2647 { 2648 { MOD_TABLE (MOD_0F18_REG_0) }, 2649 { MOD_TABLE (MOD_0F18_REG_1) }, 2650 { MOD_TABLE (MOD_0F18_REG_2) }, 2651 { MOD_TABLE (MOD_0F18_REG_3) }, 2652 }, 2653 /* REG_0F71 */ 2654 { 2655 { Bad_Opcode }, 2656 { Bad_Opcode }, 2657 { MOD_TABLE (MOD_0F71_REG_2) }, 2658 { Bad_Opcode }, 2659 { MOD_TABLE (MOD_0F71_REG_4) }, 2660 { Bad_Opcode }, 2661 { MOD_TABLE (MOD_0F71_REG_6) }, 2662 }, 2663 /* REG_0F72 */ 2664 { 2665 { Bad_Opcode }, 2666 { Bad_Opcode }, 2667 { MOD_TABLE (MOD_0F72_REG_2) }, 2668 { Bad_Opcode }, 2669 { MOD_TABLE (MOD_0F72_REG_4) }, 2670 { Bad_Opcode }, 2671 { MOD_TABLE (MOD_0F72_REG_6) }, 2672 }, 2673 /* REG_0F73 */ 2674 { 2675 { Bad_Opcode }, 2676 { Bad_Opcode }, 2677 { MOD_TABLE (MOD_0F73_REG_2) }, 2678 { MOD_TABLE (MOD_0F73_REG_3) }, 2679 { Bad_Opcode }, 2680 { Bad_Opcode }, 2681 { MOD_TABLE (MOD_0F73_REG_6) }, 2682 { MOD_TABLE (MOD_0F73_REG_7) }, 2683 }, 2684 /* REG_0FA6 */ 2685 { 2686 { "montmul", { { OP_0f07, 0 } } }, 2687 { "xsha1", { { OP_0f07, 0 } } }, 2688 { "xsha256", { { OP_0f07, 0 } } }, 2689 }, 2690 /* REG_0FA7 */ 2691 { 2692 { "xstore-rng", { { OP_0f07, 0 } } }, 2693 { "xcrypt-ecb", { { OP_0f07, 0 } } }, 2694 { "xcrypt-cbc", { { OP_0f07, 0 } } }, 2695 { "xcrypt-ctr", { { OP_0f07, 0 } } }, 2696 { "xcrypt-cfb", { { OP_0f07, 0 } } }, 2697 { "xcrypt-ofb", { { OP_0f07, 0 } } }, 2698 }, 2699 /* REG_0FAE */ 2700 { 2701 { MOD_TABLE (MOD_0FAE_REG_0) }, 2702 { MOD_TABLE (MOD_0FAE_REG_1) }, 2703 { MOD_TABLE (MOD_0FAE_REG_2) }, 2704 { MOD_TABLE (MOD_0FAE_REG_3) }, 2705 { MOD_TABLE (MOD_0FAE_REG_4) }, 2706 { MOD_TABLE (MOD_0FAE_REG_5) }, 2707 { MOD_TABLE (MOD_0FAE_REG_6) }, 2708 { MOD_TABLE (MOD_0FAE_REG_7) }, 2709 }, 2710 /* REG_0FBA */ 2711 { 2712 { Bad_Opcode }, 2713 { Bad_Opcode }, 2714 { Bad_Opcode }, 2715 { Bad_Opcode }, 2716 { "btQ", { Ev, Ib } }, 2717 { "btsQ", { Ev, Ib } }, 2718 { "btrQ", { Ev, Ib } }, 2719 { "btcQ", { Ev, Ib } }, 2720 }, 2721 /* REG_0FC7 */ 2722 { 2723 { Bad_Opcode }, 2724 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, 2725 { Bad_Opcode }, 2726 { Bad_Opcode }, 2727 { Bad_Opcode }, 2728 { Bad_Opcode }, 2729 { MOD_TABLE (MOD_0FC7_REG_6) }, 2730 { MOD_TABLE (MOD_0FC7_REG_7) }, 2731 }, 2732 /* REG_VEX_0F71 */ 2733 { 2734 { Bad_Opcode }, 2735 { Bad_Opcode }, 2736 { MOD_TABLE (MOD_VEX_0F71_REG_2) }, 2737 { Bad_Opcode }, 2738 { MOD_TABLE (MOD_VEX_0F71_REG_4) }, 2739 { Bad_Opcode }, 2740 { MOD_TABLE (MOD_VEX_0F71_REG_6) }, 2741 }, 2742 /* REG_VEX_0F72 */ 2743 { 2744 { Bad_Opcode }, 2745 { Bad_Opcode }, 2746 { MOD_TABLE (MOD_VEX_0F72_REG_2) }, 2747 { Bad_Opcode }, 2748 { MOD_TABLE (MOD_VEX_0F72_REG_4) }, 2749 { Bad_Opcode }, 2750 { MOD_TABLE (MOD_VEX_0F72_REG_6) }, 2751 }, 2752 /* REG_VEX_0F73 */ 2753 { 2754 { Bad_Opcode }, 2755 { Bad_Opcode }, 2756 { MOD_TABLE (MOD_VEX_0F73_REG_2) }, 2757 { MOD_TABLE (MOD_VEX_0F73_REG_3) }, 2758 { Bad_Opcode }, 2759 { Bad_Opcode }, 2760 { MOD_TABLE (MOD_VEX_0F73_REG_6) }, 2761 { MOD_TABLE (MOD_VEX_0F73_REG_7) }, 2762 }, 2763 /* REG_VEX_0FAE */ 2764 { 2765 { Bad_Opcode }, 2766 { Bad_Opcode }, 2767 { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, 2768 { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, 2769 }, 2770 /* REG_VEX_0F38F3 */ 2771 { 2772 { Bad_Opcode }, 2773 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, 2774 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, 2775 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, 2776 }, 2777 /* REG_XOP_LWPCB */ 2778 { 2779 { "llwpcb", { { OP_LWPCB_E, 0 } } }, 2780 { "slwpcb", { { OP_LWPCB_E, 0 } } }, 2781 }, 2782 /* REG_XOP_LWP */ 2783 { 2784 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, 2785 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, 2786 }, 2787 /* REG_XOP_TBM_01 */ 2788 { 2789 { Bad_Opcode }, 2790 { "blcfill", { { OP_LWP_E, 0 }, Ev } }, 2791 { "blsfill", { { OP_LWP_E, 0 }, Ev } }, 2792 { "blcs", { { OP_LWP_E, 0 }, Ev } }, 2793 { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, 2794 { "blcic", { { OP_LWP_E, 0 }, Ev } }, 2795 { "blsic", { { OP_LWP_E, 0 }, Ev } }, 2796 { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, 2797 }, 2798 /* REG_XOP_TBM_02 */ 2799 { 2800 { Bad_Opcode }, 2801 { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, 2802 { Bad_Opcode }, 2803 { Bad_Opcode }, 2804 { Bad_Opcode }, 2805 { Bad_Opcode }, 2806 { "blci", { { OP_LWP_E, 0 }, Ev } }, 2807 }, 2808 }; 2809 2810 static const struct dis386 prefix_table[][4] = { 2811 /* PREFIX_90 */ 2812 { 2813 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, 2814 { "pause", { XX } }, 2815 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, 2816 }, 2817 2818 /* PREFIX_0F10 */ 2819 { 2820 { "movups", { XM, EXx } }, 2821 { "movss", { XM, EXd } }, 2822 { "movupd", { XM, EXx } }, 2823 { "movsd", { XM, EXq } }, 2824 }, 2825 2826 /* PREFIX_0F11 */ 2827 { 2828 { "movups", { EXxS, XM } }, 2829 { "movss", { EXdS, XM } }, 2830 { "movupd", { EXxS, XM } }, 2831 { "movsd", { EXqS, XM } }, 2832 }, 2833 2834 /* PREFIX_0F12 */ 2835 { 2836 { MOD_TABLE (MOD_0F12_PREFIX_0) }, 2837 { "movsldup", { XM, EXx } }, 2838 { "movlpd", { XM, EXq } }, 2839 { "movddup", { XM, EXq } }, 2840 }, 2841 2842 /* PREFIX_0F16 */ 2843 { 2844 { MOD_TABLE (MOD_0F16_PREFIX_0) }, 2845 { "movshdup", { XM, EXx } }, 2846 { "movhpd", { XM, EXq } }, 2847 }, 2848 2849 /* PREFIX_0F2A */ 2850 { 2851 { "cvtpi2ps", { XM, EMCq } }, 2852 { "cvtsi2ss%LQ", { XM, Ev } }, 2853 { "cvtpi2pd", { XM, EMCq } }, 2854 { "cvtsi2sd%LQ", { XM, Ev } }, 2855 }, 2856 2857 /* PREFIX_0F2B */ 2858 { 2859 { MOD_TABLE (MOD_0F2B_PREFIX_0) }, 2860 { MOD_TABLE (MOD_0F2B_PREFIX_1) }, 2861 { MOD_TABLE (MOD_0F2B_PREFIX_2) }, 2862 { MOD_TABLE (MOD_0F2B_PREFIX_3) }, 2863 }, 2864 2865 /* PREFIX_0F2C */ 2866 { 2867 { "cvttps2pi", { MXC, EXq } }, 2868 { "cvttss2siY", { Gv, EXd } }, 2869 { "cvttpd2pi", { MXC, EXx } }, 2870 { "cvttsd2siY", { Gv, EXq } }, 2871 }, 2872 2873 /* PREFIX_0F2D */ 2874 { 2875 { "cvtps2pi", { MXC, EXq } }, 2876 { "cvtss2siY", { Gv, EXd } }, 2877 { "cvtpd2pi", { MXC, EXx } }, 2878 { "cvtsd2siY", { Gv, EXq } }, 2879 }, 2880 2881 /* PREFIX_0F2E */ 2882 { 2883 { "ucomiss",{ XM, EXd } }, 2884 { Bad_Opcode }, 2885 { "ucomisd",{ XM, EXq } }, 2886 }, 2887 2888 /* PREFIX_0F2F */ 2889 { 2890 { "comiss", { XM, EXd } }, 2891 { Bad_Opcode }, 2892 { "comisd", { XM, EXq } }, 2893 }, 2894 2895 /* PREFIX_0F51 */ 2896 { 2897 { "sqrtps", { XM, EXx } }, 2898 { "sqrtss", { XM, EXd } }, 2899 { "sqrtpd", { XM, EXx } }, 2900 { "sqrtsd", { XM, EXq } }, 2901 }, 2902 2903 /* PREFIX_0F52 */ 2904 { 2905 { "rsqrtps",{ XM, EXx } }, 2906 { "rsqrtss",{ XM, EXd } }, 2907 }, 2908 2909 /* PREFIX_0F53 */ 2910 { 2911 { "rcpps", { XM, EXx } }, 2912 { "rcpss", { XM, EXd } }, 2913 }, 2914 2915 /* PREFIX_0F58 */ 2916 { 2917 { "addps", { XM, EXx } }, 2918 { "addss", { XM, EXd } }, 2919 { "addpd", { XM, EXx } }, 2920 { "addsd", { XM, EXq } }, 2921 }, 2922 2923 /* PREFIX_0F59 */ 2924 { 2925 { "mulps", { XM, EXx } }, 2926 { "mulss", { XM, EXd } }, 2927 { "mulpd", { XM, EXx } }, 2928 { "mulsd", { XM, EXq } }, 2929 }, 2930 2931 /* PREFIX_0F5A */ 2932 { 2933 { "cvtps2pd", { XM, EXq } }, 2934 { "cvtss2sd", { XM, EXd } }, 2935 { "cvtpd2ps", { XM, EXx } }, 2936 { "cvtsd2ss", { XM, EXq } }, 2937 }, 2938 2939 /* PREFIX_0F5B */ 2940 { 2941 { "cvtdq2ps", { XM, EXx } }, 2942 { "cvttps2dq", { XM, EXx } }, 2943 { "cvtps2dq", { XM, EXx } }, 2944 }, 2945 2946 /* PREFIX_0F5C */ 2947 { 2948 { "subps", { XM, EXx } }, 2949 { "subss", { XM, EXd } }, 2950 { "subpd", { XM, EXx } }, 2951 { "subsd", { XM, EXq } }, 2952 }, 2953 2954 /* PREFIX_0F5D */ 2955 { 2956 { "minps", { XM, EXx } }, 2957 { "minss", { XM, EXd } }, 2958 { "minpd", { XM, EXx } }, 2959 { "minsd", { XM, EXq } }, 2960 }, 2961 2962 /* PREFIX_0F5E */ 2963 { 2964 { "divps", { XM, EXx } }, 2965 { "divss", { XM, EXd } }, 2966 { "divpd", { XM, EXx } }, 2967 { "divsd", { XM, EXq } }, 2968 }, 2969 2970 /* PREFIX_0F5F */ 2971 { 2972 { "maxps", { XM, EXx } }, 2973 { "maxss", { XM, EXd } }, 2974 { "maxpd", { XM, EXx } }, 2975 { "maxsd", { XM, EXq } }, 2976 }, 2977 2978 /* PREFIX_0F60 */ 2979 { 2980 { "punpcklbw",{ MX, EMd } }, 2981 { Bad_Opcode }, 2982 { "punpcklbw",{ MX, EMx } }, 2983 }, 2984 2985 /* PREFIX_0F61 */ 2986 { 2987 { "punpcklwd",{ MX, EMd } }, 2988 { Bad_Opcode }, 2989 { "punpcklwd",{ MX, EMx } }, 2990 }, 2991 2992 /* PREFIX_0F62 */ 2993 { 2994 { "punpckldq",{ MX, EMd } }, 2995 { Bad_Opcode }, 2996 { "punpckldq",{ MX, EMx } }, 2997 }, 2998 2999 /* PREFIX_0F6C */ 3000 { 3001 { Bad_Opcode }, 3002 { Bad_Opcode }, 3003 { "punpcklqdq", { XM, EXx } }, 3004 }, 3005 3006 /* PREFIX_0F6D */ 3007 { 3008 { Bad_Opcode }, 3009 { Bad_Opcode }, 3010 { "punpckhqdq", { XM, EXx } }, 3011 }, 3012 3013 /* PREFIX_0F6F */ 3014 { 3015 { "movq", { MX, EM } }, 3016 { "movdqu", { XM, EXx } }, 3017 { "movdqa", { XM, EXx } }, 3018 }, 3019 3020 /* PREFIX_0F70 */ 3021 { 3022 { "pshufw", { MX, EM, Ib } }, 3023 { "pshufhw",{ XM, EXx, Ib } }, 3024 { "pshufd", { XM, EXx, Ib } }, 3025 { "pshuflw",{ XM, EXx, Ib } }, 3026 }, 3027 3028 /* PREFIX_0F73_REG_3 */ 3029 { 3030 { Bad_Opcode }, 3031 { Bad_Opcode }, 3032 { "psrldq", { XS, Ib } }, 3033 }, 3034 3035 /* PREFIX_0F73_REG_7 */ 3036 { 3037 { Bad_Opcode }, 3038 { Bad_Opcode }, 3039 { "pslldq", { XS, Ib } }, 3040 }, 3041 3042 /* PREFIX_0F78 */ 3043 { 3044 {"vmread", { Em, Gm } }, 3045 { Bad_Opcode }, 3046 {"extrq", { XS, Ib, Ib } }, 3047 {"insertq", { XM, XS, Ib, Ib } }, 3048 }, 3049 3050 /* PREFIX_0F79 */ 3051 { 3052 {"vmwrite", { Gm, Em } }, 3053 { Bad_Opcode }, 3054 {"extrq", { XM, XS } }, 3055 {"insertq", { XM, XS } }, 3056 }, 3057 3058 /* PREFIX_0F7C */ 3059 { 3060 { Bad_Opcode }, 3061 { Bad_Opcode }, 3062 { "haddpd", { XM, EXx } }, 3063 { "haddps", { XM, EXx } }, 3064 }, 3065 3066 /* PREFIX_0F7D */ 3067 { 3068 { Bad_Opcode }, 3069 { Bad_Opcode }, 3070 { "hsubpd", { XM, EXx } }, 3071 { "hsubps", { XM, EXx } }, 3072 }, 3073 3074 /* PREFIX_0F7E */ 3075 { 3076 { "movK", { Edq, MX } }, 3077 { "movq", { XM, EXq } }, 3078 { "movK", { Edq, XM } }, 3079 }, 3080 3081 /* PREFIX_0F7F */ 3082 { 3083 { "movq", { EMS, MX } }, 3084 { "movdqu", { EXxS, XM } }, 3085 { "movdqa", { EXxS, XM } }, 3086 }, 3087 3088 /* PREFIX_0FAE_REG_0 */ 3089 { 3090 { Bad_Opcode }, 3091 { "rdfsbase", { Ev } }, 3092 }, 3093 3094 /* PREFIX_0FAE_REG_1 */ 3095 { 3096 { Bad_Opcode }, 3097 { "rdgsbase", { Ev } }, 3098 }, 3099 3100 /* PREFIX_0FAE_REG_2 */ 3101 { 3102 { Bad_Opcode }, 3103 { "wrfsbase", { Ev } }, 3104 }, 3105 3106 /* PREFIX_0FAE_REG_3 */ 3107 { 3108 { Bad_Opcode }, 3109 { "wrgsbase", { Ev } }, 3110 }, 3111 3112 /* PREFIX_0FB8 */ 3113 { 3114 { Bad_Opcode }, 3115 { "popcntS", { Gv, Ev } }, 3116 }, 3117 3118 /* PREFIX_0FBC */ 3119 { 3120 { "bsfS", { Gv, Ev } }, 3121 { "tzcntS", { Gv, Ev } }, 3122 { "bsfS", { Gv, Ev } }, 3123 }, 3124 3125 /* PREFIX_0FBD */ 3126 { 3127 { "bsrS", { Gv, Ev } }, 3128 { "lzcntS", { Gv, Ev } }, 3129 { "bsrS", { Gv, Ev } }, 3130 }, 3131 3132 /* PREFIX_0FC2 */ 3133 { 3134 { "cmpps", { XM, EXx, CMP } }, 3135 { "cmpss", { XM, EXd, CMP } }, 3136 { "cmppd", { XM, EXx, CMP } }, 3137 { "cmpsd", { XM, EXq, CMP } }, 3138 }, 3139 3140 /* PREFIX_0FC3 */ 3141 { 3142 { "movntiS", { Ma, Gv } }, 3143 }, 3144 3145 /* PREFIX_0FC7_REG_6 */ 3146 { 3147 { "vmptrld",{ Mq } }, 3148 { "vmxon", { Mq } }, 3149 { "vmclear",{ Mq } }, 3150 }, 3151 3152 /* PREFIX_0FD0 */ 3153 { 3154 { Bad_Opcode }, 3155 { Bad_Opcode }, 3156 { "addsubpd", { XM, EXx } }, 3157 { "addsubps", { XM, EXx } }, 3158 }, 3159 3160 /* PREFIX_0FD6 */ 3161 { 3162 { Bad_Opcode }, 3163 { "movq2dq",{ XM, MS } }, 3164 { "movq", { EXqS, XM } }, 3165 { "movdq2q",{ MX, XS } }, 3166 }, 3167 3168 /* PREFIX_0FE6 */ 3169 { 3170 { Bad_Opcode }, 3171 { "cvtdq2pd", { XM, EXq } }, 3172 { "cvttpd2dq", { XM, EXx } }, 3173 { "cvtpd2dq", { XM, EXx } }, 3174 }, 3175 3176 /* PREFIX_0FE7 */ 3177 { 3178 { "movntq", { Mq, MX } }, 3179 { Bad_Opcode }, 3180 { MOD_TABLE (MOD_0FE7_PREFIX_2) }, 3181 }, 3182 3183 /* PREFIX_0FF0 */ 3184 { 3185 { Bad_Opcode }, 3186 { Bad_Opcode }, 3187 { Bad_Opcode }, 3188 { MOD_TABLE (MOD_0FF0_PREFIX_3) }, 3189 }, 3190 3191 /* PREFIX_0FF7 */ 3192 { 3193 { "maskmovq", { MX, MS } }, 3194 { Bad_Opcode }, 3195 { "maskmovdqu", { XM, XS } }, 3196 }, 3197 3198 /* PREFIX_0F3810 */ 3199 { 3200 { Bad_Opcode }, 3201 { Bad_Opcode }, 3202 { "pblendvb", { XM, EXx, XMM0 } }, 3203 }, 3204 3205 /* PREFIX_0F3814 */ 3206 { 3207 { Bad_Opcode }, 3208 { Bad_Opcode }, 3209 { "blendvps", { XM, EXx, XMM0 } }, 3210 }, 3211 3212 /* PREFIX_0F3815 */ 3213 { 3214 { Bad_Opcode }, 3215 { Bad_Opcode }, 3216 { "blendvpd", { XM, EXx, XMM0 } }, 3217 }, 3218 3219 /* PREFIX_0F3817 */ 3220 { 3221 { Bad_Opcode }, 3222 { Bad_Opcode }, 3223 { "ptest", { XM, EXx } }, 3224 }, 3225 3226 /* PREFIX_0F3820 */ 3227 { 3228 { Bad_Opcode }, 3229 { Bad_Opcode }, 3230 { "pmovsxbw", { XM, EXq } }, 3231 }, 3232 3233 /* PREFIX_0F3821 */ 3234 { 3235 { Bad_Opcode }, 3236 { Bad_Opcode }, 3237 { "pmovsxbd", { XM, EXd } }, 3238 }, 3239 3240 /* PREFIX_0F3822 */ 3241 { 3242 { Bad_Opcode }, 3243 { Bad_Opcode }, 3244 { "pmovsxbq", { XM, EXw } }, 3245 }, 3246 3247 /* PREFIX_0F3823 */ 3248 { 3249 { Bad_Opcode }, 3250 { Bad_Opcode }, 3251 { "pmovsxwd", { XM, EXq } }, 3252 }, 3253 3254 /* PREFIX_0F3824 */ 3255 { 3256 { Bad_Opcode }, 3257 { Bad_Opcode }, 3258 { "pmovsxwq", { XM, EXd } }, 3259 }, 3260 3261 /* PREFIX_0F3825 */ 3262 { 3263 { Bad_Opcode }, 3264 { Bad_Opcode }, 3265 { "pmovsxdq", { XM, EXq } }, 3266 }, 3267 3268 /* PREFIX_0F3828 */ 3269 { 3270 { Bad_Opcode }, 3271 { Bad_Opcode }, 3272 { "pmuldq", { XM, EXx } }, 3273 }, 3274 3275 /* PREFIX_0F3829 */ 3276 { 3277 { Bad_Opcode }, 3278 { Bad_Opcode }, 3279 { "pcmpeqq", { XM, EXx } }, 3280 }, 3281 3282 /* PREFIX_0F382A */ 3283 { 3284 { Bad_Opcode }, 3285 { Bad_Opcode }, 3286 { MOD_TABLE (MOD_0F382A_PREFIX_2) }, 3287 }, 3288 3289 /* PREFIX_0F382B */ 3290 { 3291 { Bad_Opcode }, 3292 { Bad_Opcode }, 3293 { "packusdw", { XM, EXx } }, 3294 }, 3295 3296 /* PREFIX_0F3830 */ 3297 { 3298 { Bad_Opcode }, 3299 { Bad_Opcode }, 3300 { "pmovzxbw", { XM, EXq } }, 3301 }, 3302 3303 /* PREFIX_0F3831 */ 3304 { 3305 { Bad_Opcode }, 3306 { Bad_Opcode }, 3307 { "pmovzxbd", { XM, EXd } }, 3308 }, 3309 3310 /* PREFIX_0F3832 */ 3311 { 3312 { Bad_Opcode }, 3313 { Bad_Opcode }, 3314 { "pmovzxbq", { XM, EXw } }, 3315 }, 3316 3317 /* PREFIX_0F3833 */ 3318 { 3319 { Bad_Opcode }, 3320 { Bad_Opcode }, 3321 { "pmovzxwd", { XM, EXq } }, 3322 }, 3323 3324 /* PREFIX_0F3834 */ 3325 { 3326 { Bad_Opcode }, 3327 { Bad_Opcode }, 3328 { "pmovzxwq", { XM, EXd } }, 3329 }, 3330 3331 /* PREFIX_0F3835 */ 3332 { 3333 { Bad_Opcode }, 3334 { Bad_Opcode }, 3335 { "pmovzxdq", { XM, EXq } }, 3336 }, 3337 3338 /* PREFIX_0F3837 */ 3339 { 3340 { Bad_Opcode }, 3341 { Bad_Opcode }, 3342 { "pcmpgtq", { XM, EXx } }, 3343 }, 3344 3345 /* PREFIX_0F3838 */ 3346 { 3347 { Bad_Opcode }, 3348 { Bad_Opcode }, 3349 { "pminsb", { XM, EXx } }, 3350 }, 3351 3352 /* PREFIX_0F3839 */ 3353 { 3354 { Bad_Opcode }, 3355 { Bad_Opcode }, 3356 { "pminsd", { XM, EXx } }, 3357 }, 3358 3359 /* PREFIX_0F383A */ 3360 { 3361 { Bad_Opcode }, 3362 { Bad_Opcode }, 3363 { "pminuw", { XM, EXx } }, 3364 }, 3365 3366 /* PREFIX_0F383B */ 3367 { 3368 { Bad_Opcode }, 3369 { Bad_Opcode }, 3370 { "pminud", { XM, EXx } }, 3371 }, 3372 3373 /* PREFIX_0F383C */ 3374 { 3375 { Bad_Opcode }, 3376 { Bad_Opcode }, 3377 { "pmaxsb", { XM, EXx } }, 3378 }, 3379 3380 /* PREFIX_0F383D */ 3381 { 3382 { Bad_Opcode }, 3383 { Bad_Opcode }, 3384 { "pmaxsd", { XM, EXx } }, 3385 }, 3386 3387 /* PREFIX_0F383E */ 3388 { 3389 { Bad_Opcode }, 3390 { Bad_Opcode }, 3391 { "pmaxuw", { XM, EXx } }, 3392 }, 3393 3394 /* PREFIX_0F383F */ 3395 { 3396 { Bad_Opcode }, 3397 { Bad_Opcode }, 3398 { "pmaxud", { XM, EXx } }, 3399 }, 3400 3401 /* PREFIX_0F3840 */ 3402 { 3403 { Bad_Opcode }, 3404 { Bad_Opcode }, 3405 { "pmulld", { XM, EXx } }, 3406 }, 3407 3408 /* PREFIX_0F3841 */ 3409 { 3410 { Bad_Opcode }, 3411 { Bad_Opcode }, 3412 { "phminposuw", { XM, EXx } }, 3413 }, 3414 3415 /* PREFIX_0F3880 */ 3416 { 3417 { Bad_Opcode }, 3418 { Bad_Opcode }, 3419 { "invept", { Gm, Mo } }, 3420 }, 3421 3422 /* PREFIX_0F3881 */ 3423 { 3424 { Bad_Opcode }, 3425 { Bad_Opcode }, 3426 { "invvpid", { Gm, Mo } }, 3427 }, 3428 3429 /* PREFIX_0F38DB */ 3430 { 3431 { Bad_Opcode }, 3432 { Bad_Opcode }, 3433 { "aesimc", { XM, EXx } }, 3434 }, 3435 3436 /* PREFIX_0F38DC */ 3437 { 3438 { Bad_Opcode }, 3439 { Bad_Opcode }, 3440 { "aesenc", { XM, EXx } }, 3441 }, 3442 3443 /* PREFIX_0F38DD */ 3444 { 3445 { Bad_Opcode }, 3446 { Bad_Opcode }, 3447 { "aesenclast", { XM, EXx } }, 3448 }, 3449 3450 /* PREFIX_0F38DE */ 3451 { 3452 { Bad_Opcode }, 3453 { Bad_Opcode }, 3454 { "aesdec", { XM, EXx } }, 3455 }, 3456 3457 /* PREFIX_0F38DF */ 3458 { 3459 { Bad_Opcode }, 3460 { Bad_Opcode }, 3461 { "aesdeclast", { XM, EXx } }, 3462 }, 3463 3464 /* PREFIX_0F38F0 */ 3465 { 3466 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, 3467 { Bad_Opcode }, 3468 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, 3469 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, 3470 }, 3471 3472 /* PREFIX_0F38F1 */ 3473 { 3474 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, 3475 { Bad_Opcode }, 3476 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, 3477 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, 3478 }, 3479 3480 /* PREFIX_0F3A08 */ 3481 { 3482 { Bad_Opcode }, 3483 { Bad_Opcode }, 3484 { "roundps", { XM, EXx, Ib } }, 3485 }, 3486 3487 /* PREFIX_0F3A09 */ 3488 { 3489 { Bad_Opcode }, 3490 { Bad_Opcode }, 3491 { "roundpd", { XM, EXx, Ib } }, 3492 }, 3493 3494 /* PREFIX_0F3A0A */ 3495 { 3496 { Bad_Opcode }, 3497 { Bad_Opcode }, 3498 { "roundss", { XM, EXd, Ib } }, 3499 }, 3500 3501 /* PREFIX_0F3A0B */ 3502 { 3503 { Bad_Opcode }, 3504 { Bad_Opcode }, 3505 { "roundsd", { XM, EXq, Ib } }, 3506 }, 3507 3508 /* PREFIX_0F3A0C */ 3509 { 3510 { Bad_Opcode }, 3511 { Bad_Opcode }, 3512 { "blendps", { XM, EXx, Ib } }, 3513 }, 3514 3515 /* PREFIX_0F3A0D */ 3516 { 3517 { Bad_Opcode }, 3518 { Bad_Opcode }, 3519 { "blendpd", { XM, EXx, Ib } }, 3520 }, 3521 3522 /* PREFIX_0F3A0E */ 3523 { 3524 { Bad_Opcode }, 3525 { Bad_Opcode }, 3526 { "pblendw", { XM, EXx, Ib } }, 3527 }, 3528 3529 /* PREFIX_0F3A14 */ 3530 { 3531 { Bad_Opcode }, 3532 { Bad_Opcode }, 3533 { "pextrb", { Edqb, XM, Ib } }, 3534 }, 3535 3536 /* PREFIX_0F3A15 */ 3537 { 3538 { Bad_Opcode }, 3539 { Bad_Opcode }, 3540 { "pextrw", { Edqw, XM, Ib } }, 3541 }, 3542 3543 /* PREFIX_0F3A16 */ 3544 { 3545 { Bad_Opcode }, 3546 { Bad_Opcode }, 3547 { "pextrK", { Edq, XM, Ib } }, 3548 }, 3549 3550 /* PREFIX_0F3A17 */ 3551 { 3552 { Bad_Opcode }, 3553 { Bad_Opcode }, 3554 { "extractps", { Edqd, XM, Ib } }, 3555 }, 3556 3557 /* PREFIX_0F3A20 */ 3558 { 3559 { Bad_Opcode }, 3560 { Bad_Opcode }, 3561 { "pinsrb", { XM, Edqb, Ib } }, 3562 }, 3563 3564 /* PREFIX_0F3A21 */ 3565 { 3566 { Bad_Opcode }, 3567 { Bad_Opcode }, 3568 { "insertps", { XM, EXd, Ib } }, 3569 }, 3570 3571 /* PREFIX_0F3A22 */ 3572 { 3573 { Bad_Opcode }, 3574 { Bad_Opcode }, 3575 { "pinsrK", { XM, Edq, Ib } }, 3576 }, 3577 3578 /* PREFIX_0F3A40 */ 3579 { 3580 { Bad_Opcode }, 3581 { Bad_Opcode }, 3582 { "dpps", { XM, EXx, Ib } }, 3583 }, 3584 3585 /* PREFIX_0F3A41 */ 3586 { 3587 { Bad_Opcode }, 3588 { Bad_Opcode }, 3589 { "dppd", { XM, EXx, Ib } }, 3590 }, 3591 3592 /* PREFIX_0F3A42 */ 3593 { 3594 { Bad_Opcode }, 3595 { Bad_Opcode }, 3596 { "mpsadbw", { XM, EXx, Ib } }, 3597 }, 3598 3599 /* PREFIX_0F3A44 */ 3600 { 3601 { Bad_Opcode }, 3602 { Bad_Opcode }, 3603 { "pclmulqdq", { XM, EXx, PCLMUL } }, 3604 }, 3605 3606 /* PREFIX_0F3A60 */ 3607 { 3608 { Bad_Opcode }, 3609 { Bad_Opcode }, 3610 { "pcmpestrm", { XM, EXx, Ib } }, 3611 }, 3612 3613 /* PREFIX_0F3A61 */ 3614 { 3615 { Bad_Opcode }, 3616 { Bad_Opcode }, 3617 { "pcmpestri", { XM, EXx, Ib } }, 3618 }, 3619 3620 /* PREFIX_0F3A62 */ 3621 { 3622 { Bad_Opcode }, 3623 { Bad_Opcode }, 3624 { "pcmpistrm", { XM, EXx, Ib } }, 3625 }, 3626 3627 /* PREFIX_0F3A63 */ 3628 { 3629 { Bad_Opcode }, 3630 { Bad_Opcode }, 3631 { "pcmpistri", { XM, EXx, Ib } }, 3632 }, 3633 3634 /* PREFIX_0F3ADF */ 3635 { 3636 { Bad_Opcode }, 3637 { Bad_Opcode }, 3638 { "aeskeygenassist", { XM, EXx, Ib } }, 3639 }, 3640 3641 /* PREFIX_VEX_0F10 */ 3642 { 3643 { VEX_W_TABLE (VEX_W_0F10_P_0) }, 3644 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, 3645 { VEX_W_TABLE (VEX_W_0F10_P_2) }, 3646 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, 3647 }, 3648 3649 /* PREFIX_VEX_0F11 */ 3650 { 3651 { VEX_W_TABLE (VEX_W_0F11_P_0) }, 3652 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, 3653 { VEX_W_TABLE (VEX_W_0F11_P_2) }, 3654 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, 3655 }, 3656 3657 /* PREFIX_VEX_0F12 */ 3658 { 3659 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, 3660 { VEX_W_TABLE (VEX_W_0F12_P_1) }, 3661 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, 3662 { VEX_W_TABLE (VEX_W_0F12_P_3) }, 3663 }, 3664 3665 /* PREFIX_VEX_0F16 */ 3666 { 3667 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, 3668 { VEX_W_TABLE (VEX_W_0F16_P_1) }, 3669 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, 3670 }, 3671 3672 /* PREFIX_VEX_0F2A */ 3673 { 3674 { Bad_Opcode }, 3675 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, 3676 { Bad_Opcode }, 3677 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, 3678 }, 3679 3680 /* PREFIX_VEX_0F2C */ 3681 { 3682 { Bad_Opcode }, 3683 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, 3684 { Bad_Opcode }, 3685 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, 3686 }, 3687 3688 /* PREFIX_VEX_0F2D */ 3689 { 3690 { Bad_Opcode }, 3691 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, 3692 { Bad_Opcode }, 3693 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, 3694 }, 3695 3696 /* PREFIX_VEX_0F2E */ 3697 { 3698 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, 3699 { Bad_Opcode }, 3700 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, 3701 }, 3702 3703 /* PREFIX_VEX_0F2F */ 3704 { 3705 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, 3706 { Bad_Opcode }, 3707 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, 3708 }, 3709 3710 /* PREFIX_VEX_0F51 */ 3711 { 3712 { VEX_W_TABLE (VEX_W_0F51_P_0) }, 3713 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, 3714 { VEX_W_TABLE (VEX_W_0F51_P_2) }, 3715 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, 3716 }, 3717 3718 /* PREFIX_VEX_0F52 */ 3719 { 3720 { VEX_W_TABLE (VEX_W_0F52_P_0) }, 3721 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, 3722 }, 3723 3724 /* PREFIX_VEX_0F53 */ 3725 { 3726 { VEX_W_TABLE (VEX_W_0F53_P_0) }, 3727 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, 3728 }, 3729 3730 /* PREFIX_VEX_0F58 */ 3731 { 3732 { VEX_W_TABLE (VEX_W_0F58_P_0) }, 3733 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, 3734 { VEX_W_TABLE (VEX_W_0F58_P_2) }, 3735 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, 3736 }, 3737 3738 /* PREFIX_VEX_0F59 */ 3739 { 3740 { VEX_W_TABLE (VEX_W_0F59_P_0) }, 3741 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, 3742 { VEX_W_TABLE (VEX_W_0F59_P_2) }, 3743 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, 3744 }, 3745 3746 /* PREFIX_VEX_0F5A */ 3747 { 3748 { VEX_W_TABLE (VEX_W_0F5A_P_0) }, 3749 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, 3750 { "vcvtpd2ps%XY", { XMM, EXx } }, 3751 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, 3752 }, 3753 3754 /* PREFIX_VEX_0F5B */ 3755 { 3756 { VEX_W_TABLE (VEX_W_0F5B_P_0) }, 3757 { VEX_W_TABLE (VEX_W_0F5B_P_1) }, 3758 { VEX_W_TABLE (VEX_W_0F5B_P_2) }, 3759 }, 3760 3761 /* PREFIX_VEX_0F5C */ 3762 { 3763 { VEX_W_TABLE (VEX_W_0F5C_P_0) }, 3764 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, 3765 { VEX_W_TABLE (VEX_W_0F5C_P_2) }, 3766 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, 3767 }, 3768 3769 /* PREFIX_VEX_0F5D */ 3770 { 3771 { VEX_W_TABLE (VEX_W_0F5D_P_0) }, 3772 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, 3773 { VEX_W_TABLE (VEX_W_0F5D_P_2) }, 3774 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, 3775 }, 3776 3777 /* PREFIX_VEX_0F5E */ 3778 { 3779 { VEX_W_TABLE (VEX_W_0F5E_P_0) }, 3780 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, 3781 { VEX_W_TABLE (VEX_W_0F5E_P_2) }, 3782 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, 3783 }, 3784 3785 /* PREFIX_VEX_0F5F */ 3786 { 3787 { VEX_W_TABLE (VEX_W_0F5F_P_0) }, 3788 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, 3789 { VEX_W_TABLE (VEX_W_0F5F_P_2) }, 3790 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, 3791 }, 3792 3793 /* PREFIX_VEX_0F60 */ 3794 { 3795 { Bad_Opcode }, 3796 { Bad_Opcode }, 3797 { VEX_LEN_TABLE (VEX_LEN_0F60_P_2) }, 3798 }, 3799 3800 /* PREFIX_VEX_0F61 */ 3801 { 3802 { Bad_Opcode }, 3803 { Bad_Opcode }, 3804 { VEX_LEN_TABLE (VEX_LEN_0F61_P_2) }, 3805 }, 3806 3807 /* PREFIX_VEX_0F62 */ 3808 { 3809 { Bad_Opcode }, 3810 { Bad_Opcode }, 3811 { VEX_LEN_TABLE (VEX_LEN_0F62_P_2) }, 3812 }, 3813 3814 /* PREFIX_VEX_0F63 */ 3815 { 3816 { Bad_Opcode }, 3817 { Bad_Opcode }, 3818 { VEX_LEN_TABLE (VEX_LEN_0F63_P_2) }, 3819 }, 3820 3821 /* PREFIX_VEX_0F64 */ 3822 { 3823 { Bad_Opcode }, 3824 { Bad_Opcode }, 3825 { VEX_LEN_TABLE (VEX_LEN_0F64_P_2) }, 3826 }, 3827 3828 /* PREFIX_VEX_0F65 */ 3829 { 3830 { Bad_Opcode }, 3831 { Bad_Opcode }, 3832 { VEX_LEN_TABLE (VEX_LEN_0F65_P_2) }, 3833 }, 3834 3835 /* PREFIX_VEX_0F66 */ 3836 { 3837 { Bad_Opcode }, 3838 { Bad_Opcode }, 3839 { VEX_LEN_TABLE (VEX_LEN_0F66_P_2) }, 3840 }, 3841 3842 /* PREFIX_VEX_0F67 */ 3843 { 3844 { Bad_Opcode }, 3845 { Bad_Opcode }, 3846 { VEX_LEN_TABLE (VEX_LEN_0F67_P_2) }, 3847 }, 3848 3849 /* PREFIX_VEX_0F68 */ 3850 { 3851 { Bad_Opcode }, 3852 { Bad_Opcode }, 3853 { VEX_LEN_TABLE (VEX_LEN_0F68_P_2) }, 3854 }, 3855 3856 /* PREFIX_VEX_0F69 */ 3857 { 3858 { Bad_Opcode }, 3859 { Bad_Opcode }, 3860 { VEX_LEN_TABLE (VEX_LEN_0F69_P_2) }, 3861 }, 3862 3863 /* PREFIX_VEX_0F6A */ 3864 { 3865 { Bad_Opcode }, 3866 { Bad_Opcode }, 3867 { VEX_LEN_TABLE (VEX_LEN_0F6A_P_2) }, 3868 }, 3869 3870 /* PREFIX_VEX_0F6B */ 3871 { 3872 { Bad_Opcode }, 3873 { Bad_Opcode }, 3874 { VEX_LEN_TABLE (VEX_LEN_0F6B_P_2) }, 3875 }, 3876 3877 /* PREFIX_VEX_0F6C */ 3878 { 3879 { Bad_Opcode }, 3880 { Bad_Opcode }, 3881 { VEX_LEN_TABLE (VEX_LEN_0F6C_P_2) }, 3882 }, 3883 3884 /* PREFIX_VEX_0F6D */ 3885 { 3886 { Bad_Opcode }, 3887 { Bad_Opcode }, 3888 { VEX_LEN_TABLE (VEX_LEN_0F6D_P_2) }, 3889 }, 3890 3891 /* PREFIX_VEX_0F6E */ 3892 { 3893 { Bad_Opcode }, 3894 { Bad_Opcode }, 3895 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, 3896 }, 3897 3898 /* PREFIX_VEX_0F6F */ 3899 { 3900 { Bad_Opcode }, 3901 { VEX_W_TABLE (VEX_W_0F6F_P_1) }, 3902 { VEX_W_TABLE (VEX_W_0F6F_P_2) }, 3903 }, 3904 3905 /* PREFIX_VEX_0F70 */ 3906 { 3907 { Bad_Opcode }, 3908 { VEX_LEN_TABLE (VEX_LEN_0F70_P_1) }, 3909 { VEX_LEN_TABLE (VEX_LEN_0F70_P_2) }, 3910 { VEX_LEN_TABLE (VEX_LEN_0F70_P_3) }, 3911 }, 3912 3913 /* PREFIX_VEX_0F71_REG_2 */ 3914 { 3915 { Bad_Opcode }, 3916 { Bad_Opcode }, 3917 { VEX_LEN_TABLE (VEX_LEN_0F71_R_2_P_2) }, 3918 }, 3919 3920 /* PREFIX_VEX_0F71_REG_4 */ 3921 { 3922 { Bad_Opcode }, 3923 { Bad_Opcode }, 3924 { VEX_LEN_TABLE (VEX_LEN_0F71_R_4_P_2) }, 3925 }, 3926 3927 /* PREFIX_VEX_0F71_REG_6 */ 3928 { 3929 { Bad_Opcode }, 3930 { Bad_Opcode }, 3931 { VEX_LEN_TABLE (VEX_LEN_0F71_R_6_P_2) }, 3932 }, 3933 3934 /* PREFIX_VEX_0F72_REG_2 */ 3935 { 3936 { Bad_Opcode }, 3937 { Bad_Opcode }, 3938 { VEX_LEN_TABLE (VEX_LEN_0F72_R_2_P_2) }, 3939 }, 3940 3941 /* PREFIX_VEX_0F72_REG_4 */ 3942 { 3943 { Bad_Opcode }, 3944 { Bad_Opcode }, 3945 { VEX_LEN_TABLE (VEX_LEN_0F72_R_4_P_2) }, 3946 }, 3947 3948 /* PREFIX_VEX_0F72_REG_6 */ 3949 { 3950 { Bad_Opcode }, 3951 { Bad_Opcode }, 3952 { VEX_LEN_TABLE (VEX_LEN_0F72_R_6_P_2) }, 3953 }, 3954 3955 /* PREFIX_VEX_0F73_REG_2 */ 3956 { 3957 { Bad_Opcode }, 3958 { Bad_Opcode }, 3959 { VEX_LEN_TABLE (VEX_LEN_0F73_R_2_P_2) }, 3960 }, 3961 3962 /* PREFIX_VEX_0F73_REG_3 */ 3963 { 3964 { Bad_Opcode }, 3965 { Bad_Opcode }, 3966 { VEX_LEN_TABLE (VEX_LEN_0F73_R_3_P_2) }, 3967 }, 3968 3969 /* PREFIX_VEX_0F73_REG_6 */ 3970 { 3971 { Bad_Opcode }, 3972 { Bad_Opcode }, 3973 { VEX_LEN_TABLE (VEX_LEN_0F73_R_6_P_2) }, 3974 }, 3975 3976 /* PREFIX_VEX_0F73_REG_7 */ 3977 { 3978 { Bad_Opcode }, 3979 { Bad_Opcode }, 3980 { VEX_LEN_TABLE (VEX_LEN_0F73_R_7_P_2) }, 3981 }, 3982 3983 /* PREFIX_VEX_0F74 */ 3984 { 3985 { Bad_Opcode }, 3986 { Bad_Opcode }, 3987 { VEX_LEN_TABLE (VEX_LEN_0F74_P_2) }, 3988 }, 3989 3990 /* PREFIX_VEX_0F75 */ 3991 { 3992 { Bad_Opcode }, 3993 { Bad_Opcode }, 3994 { VEX_LEN_TABLE (VEX_LEN_0F75_P_2) }, 3995 }, 3996 3997 /* PREFIX_VEX_0F76 */ 3998 { 3999 { Bad_Opcode }, 4000 { Bad_Opcode }, 4001 { VEX_LEN_TABLE (VEX_LEN_0F76_P_2) }, 4002 }, 4003 4004 /* PREFIX_VEX_0F77 */ 4005 { 4006 { VEX_W_TABLE (VEX_W_0F77_P_0) }, 4007 }, 4008 4009 /* PREFIX_VEX_0F7C */ 4010 { 4011 { Bad_Opcode }, 4012 { Bad_Opcode }, 4013 { VEX_W_TABLE (VEX_W_0F7C_P_2) }, 4014 { VEX_W_TABLE (VEX_W_0F7C_P_3) }, 4015 }, 4016 4017 /* PREFIX_VEX_0F7D */ 4018 { 4019 { Bad_Opcode }, 4020 { Bad_Opcode }, 4021 { VEX_W_TABLE (VEX_W_0F7D_P_2) }, 4022 { VEX_W_TABLE (VEX_W_0F7D_P_3) }, 4023 }, 4024 4025 /* PREFIX_VEX_0F7E */ 4026 { 4027 { Bad_Opcode }, 4028 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, 4029 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, 4030 }, 4031 4032 /* PREFIX_VEX_0F7F */ 4033 { 4034 { Bad_Opcode }, 4035 { VEX_W_TABLE (VEX_W_0F7F_P_1) }, 4036 { VEX_W_TABLE (VEX_W_0F7F_P_2) }, 4037 }, 4038 4039 /* PREFIX_VEX_0FC2 */ 4040 { 4041 { VEX_W_TABLE (VEX_W_0FC2_P_0) }, 4042 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, 4043 { VEX_W_TABLE (VEX_W_0FC2_P_2) }, 4044 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, 4045 }, 4046 4047 /* PREFIX_VEX_0FC4 */ 4048 { 4049 { Bad_Opcode }, 4050 { Bad_Opcode }, 4051 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, 4052 }, 4053 4054 /* PREFIX_VEX_0FC5 */ 4055 { 4056 { Bad_Opcode }, 4057 { Bad_Opcode }, 4058 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, 4059 }, 4060 4061 /* PREFIX_VEX_0FD0 */ 4062 { 4063 { Bad_Opcode }, 4064 { Bad_Opcode }, 4065 { VEX_W_TABLE (VEX_W_0FD0_P_2) }, 4066 { VEX_W_TABLE (VEX_W_0FD0_P_3) }, 4067 }, 4068 4069 /* PREFIX_VEX_0FD1 */ 4070 { 4071 { Bad_Opcode }, 4072 { Bad_Opcode }, 4073 { VEX_LEN_TABLE (VEX_LEN_0FD1_P_2) }, 4074 }, 4075 4076 /* PREFIX_VEX_0FD2 */ 4077 { 4078 { Bad_Opcode }, 4079 { Bad_Opcode }, 4080 { VEX_LEN_TABLE (VEX_LEN_0FD2_P_2) }, 4081 }, 4082 4083 /* PREFIX_VEX_0FD3 */ 4084 { 4085 { Bad_Opcode }, 4086 { Bad_Opcode }, 4087 { VEX_LEN_TABLE (VEX_LEN_0FD3_P_2) }, 4088 }, 4089 4090 /* PREFIX_VEX_0FD4 */ 4091 { 4092 { Bad_Opcode }, 4093 { Bad_Opcode }, 4094 { VEX_LEN_TABLE (VEX_LEN_0FD4_P_2) }, 4095 }, 4096 4097 /* PREFIX_VEX_0FD5 */ 4098 { 4099 { Bad_Opcode }, 4100 { Bad_Opcode }, 4101 { VEX_LEN_TABLE (VEX_LEN_0FD5_P_2) }, 4102 }, 4103 4104 /* PREFIX_VEX_0FD6 */ 4105 { 4106 { Bad_Opcode }, 4107 { Bad_Opcode }, 4108 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, 4109 }, 4110 4111 /* PREFIX_VEX_0FD7 */ 4112 { 4113 { Bad_Opcode }, 4114 { Bad_Opcode }, 4115 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, 4116 }, 4117 4118 /* PREFIX_VEX_0FD8 */ 4119 { 4120 { Bad_Opcode }, 4121 { Bad_Opcode }, 4122 { VEX_LEN_TABLE (VEX_LEN_0FD8_P_2) }, 4123 }, 4124 4125 /* PREFIX_VEX_0FD9 */ 4126 { 4127 { Bad_Opcode }, 4128 { Bad_Opcode }, 4129 { VEX_LEN_TABLE (VEX_LEN_0FD9_P_2) }, 4130 }, 4131 4132 /* PREFIX_VEX_0FDA */ 4133 { 4134 { Bad_Opcode }, 4135 { Bad_Opcode }, 4136 { VEX_LEN_TABLE (VEX_LEN_0FDA_P_2) }, 4137 }, 4138 4139 /* PREFIX_VEX_0FDB */ 4140 { 4141 { Bad_Opcode }, 4142 { Bad_Opcode }, 4143 { VEX_LEN_TABLE (VEX_LEN_0FDB_P_2) }, 4144 }, 4145 4146 /* PREFIX_VEX_0FDC */ 4147 { 4148 { Bad_Opcode }, 4149 { Bad_Opcode }, 4150 { VEX_LEN_TABLE (VEX_LEN_0FDC_P_2) }, 4151 }, 4152 4153 /* PREFIX_VEX_0FDD */ 4154 { 4155 { Bad_Opcode }, 4156 { Bad_Opcode }, 4157 { VEX_LEN_TABLE (VEX_LEN_0FDD_P_2) }, 4158 }, 4159 4160 /* PREFIX_VEX_0FDE */ 4161 { 4162 { Bad_Opcode }, 4163 { Bad_Opcode }, 4164 { VEX_LEN_TABLE (VEX_LEN_0FDE_P_2) }, 4165 }, 4166 4167 /* PREFIX_VEX_0FDF */ 4168 { 4169 { Bad_Opcode }, 4170 { Bad_Opcode }, 4171 { VEX_LEN_TABLE (VEX_LEN_0FDF_P_2) }, 4172 }, 4173 4174 /* PREFIX_VEX_0FE0 */ 4175 { 4176 { Bad_Opcode }, 4177 { Bad_Opcode }, 4178 { VEX_LEN_TABLE (VEX_LEN_0FE0_P_2) }, 4179 }, 4180 4181 /* PREFIX_VEX_0FE1 */ 4182 { 4183 { Bad_Opcode }, 4184 { Bad_Opcode }, 4185 { VEX_LEN_TABLE (VEX_LEN_0FE1_P_2) }, 4186 }, 4187 4188 /* PREFIX_VEX_0FE2 */ 4189 { 4190 { Bad_Opcode }, 4191 { Bad_Opcode }, 4192 { VEX_LEN_TABLE (VEX_LEN_0FE2_P_2) }, 4193 }, 4194 4195 /* PREFIX_VEX_0FE3 */ 4196 { 4197 { Bad_Opcode }, 4198 { Bad_Opcode }, 4199 { VEX_LEN_TABLE (VEX_LEN_0FE3_P_2) }, 4200 }, 4201 4202 /* PREFIX_VEX_0FE4 */ 4203 { 4204 { Bad_Opcode }, 4205 { Bad_Opcode }, 4206 { VEX_LEN_TABLE (VEX_LEN_0FE4_P_2) }, 4207 }, 4208 4209 /* PREFIX_VEX_0FE5 */ 4210 { 4211 { Bad_Opcode }, 4212 { Bad_Opcode }, 4213 { VEX_LEN_TABLE (VEX_LEN_0FE5_P_2) }, 4214 }, 4215 4216 /* PREFIX_VEX_0FE6 */ 4217 { 4218 { Bad_Opcode }, 4219 { VEX_W_TABLE (VEX_W_0FE6_P_1) }, 4220 { VEX_W_TABLE (VEX_W_0FE6_P_2) }, 4221 { VEX_W_TABLE (VEX_W_0FE6_P_3) }, 4222 }, 4223 4224 /* PREFIX_VEX_0FE7 */ 4225 { 4226 { Bad_Opcode }, 4227 { Bad_Opcode }, 4228 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, 4229 }, 4230 4231 /* PREFIX_VEX_0FE8 */ 4232 { 4233 { Bad_Opcode }, 4234 { Bad_Opcode }, 4235 { VEX_LEN_TABLE (VEX_LEN_0FE8_P_2) }, 4236 }, 4237 4238 /* PREFIX_VEX_0FE9 */ 4239 { 4240 { Bad_Opcode }, 4241 { Bad_Opcode }, 4242 { VEX_LEN_TABLE (VEX_LEN_0FE9_P_2) }, 4243 }, 4244 4245 /* PREFIX_VEX_0FEA */ 4246 { 4247 { Bad_Opcode }, 4248 { Bad_Opcode }, 4249 { VEX_LEN_TABLE (VEX_LEN_0FEA_P_2) }, 4250 }, 4251 4252 /* PREFIX_VEX_0FEB */ 4253 { 4254 { Bad_Opcode }, 4255 { Bad_Opcode }, 4256 { VEX_LEN_TABLE (VEX_LEN_0FEB_P_2) }, 4257 }, 4258 4259 /* PREFIX_VEX_0FEC */ 4260 { 4261 { Bad_Opcode }, 4262 { Bad_Opcode }, 4263 { VEX_LEN_TABLE (VEX_LEN_0FEC_P_2) }, 4264 }, 4265 4266 /* PREFIX_VEX_0FED */ 4267 { 4268 { Bad_Opcode }, 4269 { Bad_Opcode }, 4270 { VEX_LEN_TABLE (VEX_LEN_0FED_P_2) }, 4271 }, 4272 4273 /* PREFIX_VEX_0FEE */ 4274 { 4275 { Bad_Opcode }, 4276 { Bad_Opcode }, 4277 { VEX_LEN_TABLE (VEX_LEN_0FEE_P_2) }, 4278 }, 4279 4280 /* PREFIX_VEX_0FEF */ 4281 { 4282 { Bad_Opcode }, 4283 { Bad_Opcode }, 4284 { VEX_LEN_TABLE (VEX_LEN_0FEF_P_2) }, 4285 }, 4286 4287 /* PREFIX_VEX_0FF0 */ 4288 { 4289 { Bad_Opcode }, 4290 { Bad_Opcode }, 4291 { Bad_Opcode }, 4292 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, 4293 }, 4294 4295 /* PREFIX_VEX_0FF1 */ 4296 { 4297 { Bad_Opcode }, 4298 { Bad_Opcode }, 4299 { VEX_LEN_TABLE (VEX_LEN_0FF1_P_2) }, 4300 }, 4301 4302 /* PREFIX_VEX_0FF2 */ 4303 { 4304 { Bad_Opcode }, 4305 { Bad_Opcode }, 4306 { VEX_LEN_TABLE (VEX_LEN_0FF2_P_2) }, 4307 }, 4308 4309 /* PREFIX_VEX_0FF3 */ 4310 { 4311 { Bad_Opcode }, 4312 { Bad_Opcode }, 4313 { VEX_LEN_TABLE (VEX_LEN_0FF3_P_2) }, 4314 }, 4315 4316 /* PREFIX_VEX_0FF4 */ 4317 { 4318 { Bad_Opcode }, 4319 { Bad_Opcode }, 4320 { VEX_LEN_TABLE (VEX_LEN_0FF4_P_2) }, 4321 }, 4322 4323 /* PREFIX_VEX_0FF5 */ 4324 { 4325 { Bad_Opcode }, 4326 { Bad_Opcode }, 4327 { VEX_LEN_TABLE (VEX_LEN_0FF5_P_2) }, 4328 }, 4329 4330 /* PREFIX_VEX_0FF6 */ 4331 { 4332 { Bad_Opcode }, 4333 { Bad_Opcode }, 4334 { VEX_LEN_TABLE (VEX_LEN_0FF6_P_2) }, 4335 }, 4336 4337 /* PREFIX_VEX_0FF7 */ 4338 { 4339 { Bad_Opcode }, 4340 { Bad_Opcode }, 4341 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, 4342 }, 4343 4344 /* PREFIX_VEX_0FF8 */ 4345 { 4346 { Bad_Opcode }, 4347 { Bad_Opcode }, 4348 { VEX_LEN_TABLE (VEX_LEN_0FF8_P_2) }, 4349 }, 4350 4351 /* PREFIX_VEX_0FF9 */ 4352 { 4353 { Bad_Opcode }, 4354 { Bad_Opcode }, 4355 { VEX_LEN_TABLE (VEX_LEN_0FF9_P_2) }, 4356 }, 4357 4358 /* PREFIX_VEX_0FFA */ 4359 { 4360 { Bad_Opcode }, 4361 { Bad_Opcode }, 4362 { VEX_LEN_TABLE (VEX_LEN_0FFA_P_2) }, 4363 }, 4364 4365 /* PREFIX_VEX_0FFB */ 4366 { 4367 { Bad_Opcode }, 4368 { Bad_Opcode }, 4369 { VEX_LEN_TABLE (VEX_LEN_0FFB_P_2) }, 4370 }, 4371 4372 /* PREFIX_VEX_0FFC */ 4373 { 4374 { Bad_Opcode }, 4375 { Bad_Opcode }, 4376 { VEX_LEN_TABLE (VEX_LEN_0FFC_P_2) }, 4377 }, 4378 4379 /* PREFIX_VEX_0FFD */ 4380 { 4381 { Bad_Opcode }, 4382 { Bad_Opcode }, 4383 { VEX_LEN_TABLE (VEX_LEN_0FFD_P_2) }, 4384 }, 4385 4386 /* PREFIX_VEX_0FFE */ 4387 { 4388 { Bad_Opcode }, 4389 { Bad_Opcode }, 4390 { VEX_LEN_TABLE (VEX_LEN_0FFE_P_2) }, 4391 }, 4392 4393 /* PREFIX_VEX_0F3800 */ 4394 { 4395 { Bad_Opcode }, 4396 { Bad_Opcode }, 4397 { VEX_LEN_TABLE (VEX_LEN_0F3800_P_2) }, 4398 }, 4399 4400 /* PREFIX_VEX_0F3801 */ 4401 { 4402 { Bad_Opcode }, 4403 { Bad_Opcode }, 4404 { VEX_LEN_TABLE (VEX_LEN_0F3801_P_2) }, 4405 }, 4406 4407 /* PREFIX_VEX_0F3802 */ 4408 { 4409 { Bad_Opcode }, 4410 { Bad_Opcode }, 4411 { VEX_LEN_TABLE (VEX_LEN_0F3802_P_2) }, 4412 }, 4413 4414 /* PREFIX_VEX_0F3803 */ 4415 { 4416 { Bad_Opcode }, 4417 { Bad_Opcode }, 4418 { VEX_LEN_TABLE (VEX_LEN_0F3803_P_2) }, 4419 }, 4420 4421 /* PREFIX_VEX_0F3804 */ 4422 { 4423 { Bad_Opcode }, 4424 { Bad_Opcode }, 4425 { VEX_LEN_TABLE (VEX_LEN_0F3804_P_2) }, 4426 }, 4427 4428 /* PREFIX_VEX_0F3805 */ 4429 { 4430 { Bad_Opcode }, 4431 { Bad_Opcode }, 4432 { VEX_LEN_TABLE (VEX_LEN_0F3805_P_2) }, 4433 }, 4434 4435 /* PREFIX_VEX_0F3806 */ 4436 { 4437 { Bad_Opcode }, 4438 { Bad_Opcode }, 4439 { VEX_LEN_TABLE (VEX_LEN_0F3806_P_2) }, 4440 }, 4441 4442 /* PREFIX_VEX_0F3807 */ 4443 { 4444 { Bad_Opcode }, 4445 { Bad_Opcode }, 4446 { VEX_LEN_TABLE (VEX_LEN_0F3807_P_2) }, 4447 }, 4448 4449 /* PREFIX_VEX_0F3808 */ 4450 { 4451 { Bad_Opcode }, 4452 { Bad_Opcode }, 4453 { VEX_LEN_TABLE (VEX_LEN_0F3808_P_2) }, 4454 }, 4455 4456 /* PREFIX_VEX_0F3809 */ 4457 { 4458 { Bad_Opcode }, 4459 { Bad_Opcode }, 4460 { VEX_LEN_TABLE (VEX_LEN_0F3809_P_2) }, 4461 }, 4462 4463 /* PREFIX_VEX_0F380A */ 4464 { 4465 { Bad_Opcode }, 4466 { Bad_Opcode }, 4467 { VEX_LEN_TABLE (VEX_LEN_0F380A_P_2) }, 4468 }, 4469 4470 /* PREFIX_VEX_0F380B */ 4471 { 4472 { Bad_Opcode }, 4473 { Bad_Opcode }, 4474 { VEX_LEN_TABLE (VEX_LEN_0F380B_P_2) }, 4475 }, 4476 4477 /* PREFIX_VEX_0F380C */ 4478 { 4479 { Bad_Opcode }, 4480 { Bad_Opcode }, 4481 { VEX_W_TABLE (VEX_W_0F380C_P_2) }, 4482 }, 4483 4484 /* PREFIX_VEX_0F380D */ 4485 { 4486 { Bad_Opcode }, 4487 { Bad_Opcode }, 4488 { VEX_W_TABLE (VEX_W_0F380D_P_2) }, 4489 }, 4490 4491 /* PREFIX_VEX_0F380E */ 4492 { 4493 { Bad_Opcode }, 4494 { Bad_Opcode }, 4495 { VEX_W_TABLE (VEX_W_0F380E_P_2) }, 4496 }, 4497 4498 /* PREFIX_VEX_0F380F */ 4499 { 4500 { Bad_Opcode }, 4501 { Bad_Opcode }, 4502 { VEX_W_TABLE (VEX_W_0F380F_P_2) }, 4503 }, 4504 4505 /* PREFIX_VEX_0F3813 */ 4506 { 4507 { Bad_Opcode }, 4508 { Bad_Opcode }, 4509 { "vcvtph2ps", { XM, EXxmmq } }, 4510 }, 4511 4512 /* PREFIX_VEX_0F3817 */ 4513 { 4514 { Bad_Opcode }, 4515 { Bad_Opcode }, 4516 { VEX_W_TABLE (VEX_W_0F3817_P_2) }, 4517 }, 4518 4519 /* PREFIX_VEX_0F3818 */ 4520 { 4521 { Bad_Opcode }, 4522 { Bad_Opcode }, 4523 { MOD_TABLE (MOD_VEX_0F3818_PREFIX_2) }, 4524 }, 4525 4526 /* PREFIX_VEX_0F3819 */ 4527 { 4528 { Bad_Opcode }, 4529 { Bad_Opcode }, 4530 { MOD_TABLE (MOD_VEX_0F3819_PREFIX_2) }, 4531 }, 4532 4533 /* PREFIX_VEX_0F381A */ 4534 { 4535 { Bad_Opcode }, 4536 { Bad_Opcode }, 4537 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, 4538 }, 4539 4540 /* PREFIX_VEX_0F381C */ 4541 { 4542 { Bad_Opcode }, 4543 { Bad_Opcode }, 4544 { VEX_LEN_TABLE (VEX_LEN_0F381C_P_2) }, 4545 }, 4546 4547 /* PREFIX_VEX_0F381D */ 4548 { 4549 { Bad_Opcode }, 4550 { Bad_Opcode }, 4551 { VEX_LEN_TABLE (VEX_LEN_0F381D_P_2) }, 4552 }, 4553 4554 /* PREFIX_VEX_0F381E */ 4555 { 4556 { Bad_Opcode }, 4557 { Bad_Opcode }, 4558 { VEX_LEN_TABLE (VEX_LEN_0F381E_P_2) }, 4559 }, 4560 4561 /* PREFIX_VEX_0F3820 */ 4562 { 4563 { Bad_Opcode }, 4564 { Bad_Opcode }, 4565 { VEX_LEN_TABLE (VEX_LEN_0F3820_P_2) }, 4566 }, 4567 4568 /* PREFIX_VEX_0F3821 */ 4569 { 4570 { Bad_Opcode }, 4571 { Bad_Opcode }, 4572 { VEX_LEN_TABLE (VEX_LEN_0F3821_P_2) }, 4573 }, 4574 4575 /* PREFIX_VEX_0F3822 */ 4576 { 4577 { Bad_Opcode }, 4578 { Bad_Opcode }, 4579 { VEX_LEN_TABLE (VEX_LEN_0F3822_P_2) }, 4580 }, 4581 4582 /* PREFIX_VEX_0F3823 */ 4583 { 4584 { Bad_Opcode }, 4585 { Bad_Opcode }, 4586 { VEX_LEN_TABLE (VEX_LEN_0F3823_P_2) }, 4587 }, 4588 4589 /* PREFIX_VEX_0F3824 */ 4590 { 4591 { Bad_Opcode }, 4592 { Bad_Opcode }, 4593 { VEX_LEN_TABLE (VEX_LEN_0F3824_P_2) }, 4594 }, 4595 4596 /* PREFIX_VEX_0F3825 */ 4597 { 4598 { Bad_Opcode }, 4599 { Bad_Opcode }, 4600 { VEX_LEN_TABLE (VEX_LEN_0F3825_P_2) }, 4601 }, 4602 4603 /* PREFIX_VEX_0F3828 */ 4604 { 4605 { Bad_Opcode }, 4606 { Bad_Opcode }, 4607 { VEX_LEN_TABLE (VEX_LEN_0F3828_P_2) }, 4608 }, 4609 4610 /* PREFIX_VEX_0F3829 */ 4611 { 4612 { Bad_Opcode }, 4613 { Bad_Opcode }, 4614 { VEX_LEN_TABLE (VEX_LEN_0F3829_P_2) }, 4615 }, 4616 4617 /* PREFIX_VEX_0F382A */ 4618 { 4619 { Bad_Opcode }, 4620 { Bad_Opcode }, 4621 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, 4622 }, 4623 4624 /* PREFIX_VEX_0F382B */ 4625 { 4626 { Bad_Opcode }, 4627 { Bad_Opcode }, 4628 { VEX_LEN_TABLE (VEX_LEN_0F382B_P_2) }, 4629 }, 4630 4631 /* PREFIX_VEX_0F382C */ 4632 { 4633 { Bad_Opcode }, 4634 { Bad_Opcode }, 4635 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, 4636 }, 4637 4638 /* PREFIX_VEX_0F382D */ 4639 { 4640 { Bad_Opcode }, 4641 { Bad_Opcode }, 4642 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, 4643 }, 4644 4645 /* PREFIX_VEX_0F382E */ 4646 { 4647 { Bad_Opcode }, 4648 { Bad_Opcode }, 4649 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, 4650 }, 4651 4652 /* PREFIX_VEX_0F382F */ 4653 { 4654 { Bad_Opcode }, 4655 { Bad_Opcode }, 4656 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, 4657 }, 4658 4659 /* PREFIX_VEX_0F3830 */ 4660 { 4661 { Bad_Opcode }, 4662 { Bad_Opcode }, 4663 { VEX_LEN_TABLE (VEX_LEN_0F3830_P_2) }, 4664 }, 4665 4666 /* PREFIX_VEX_0F3831 */ 4667 { 4668 { Bad_Opcode }, 4669 { Bad_Opcode }, 4670 { VEX_LEN_TABLE (VEX_LEN_0F3831_P_2) }, 4671 }, 4672 4673 /* PREFIX_VEX_0F3832 */ 4674 { 4675 { Bad_Opcode }, 4676 { Bad_Opcode }, 4677 { VEX_LEN_TABLE (VEX_LEN_0F3832_P_2) }, 4678 }, 4679 4680 /* PREFIX_VEX_0F3833 */ 4681 { 4682 { Bad_Opcode }, 4683 { Bad_Opcode }, 4684 { VEX_LEN_TABLE (VEX_LEN_0F3833_P_2) }, 4685 }, 4686 4687 /* PREFIX_VEX_0F3834 */ 4688 { 4689 { Bad_Opcode }, 4690 { Bad_Opcode }, 4691 { VEX_LEN_TABLE (VEX_LEN_0F3834_P_2) }, 4692 }, 4693 4694 /* PREFIX_VEX_0F3835 */ 4695 { 4696 { Bad_Opcode }, 4697 { Bad_Opcode }, 4698 { VEX_LEN_TABLE (VEX_LEN_0F3835_P_2) }, 4699 }, 4700 4701 /* PREFIX_VEX_0F3837 */ 4702 { 4703 { Bad_Opcode }, 4704 { Bad_Opcode }, 4705 { VEX_LEN_TABLE (VEX_LEN_0F3837_P_2) }, 4706 }, 4707 4708 /* PREFIX_VEX_0F3838 */ 4709 { 4710 { Bad_Opcode }, 4711 { Bad_Opcode }, 4712 { VEX_LEN_TABLE (VEX_LEN_0F3838_P_2) }, 4713 }, 4714 4715 /* PREFIX_VEX_0F3839 */ 4716 { 4717 { Bad_Opcode }, 4718 { Bad_Opcode }, 4719 { VEX_LEN_TABLE (VEX_LEN_0F3839_P_2) }, 4720 }, 4721 4722 /* PREFIX_VEX_0F383A */ 4723 { 4724 { Bad_Opcode }, 4725 { Bad_Opcode }, 4726 { VEX_LEN_TABLE (VEX_LEN_0F383A_P_2) }, 4727 }, 4728 4729 /* PREFIX_VEX_0F383B */ 4730 { 4731 { Bad_Opcode }, 4732 { Bad_Opcode }, 4733 { VEX_LEN_TABLE (VEX_LEN_0F383B_P_2) }, 4734 }, 4735 4736 /* PREFIX_VEX_0F383C */ 4737 { 4738 { Bad_Opcode }, 4739 { Bad_Opcode }, 4740 { VEX_LEN_TABLE (VEX_LEN_0F383C_P_2) }, 4741 }, 4742 4743 /* PREFIX_VEX_0F383D */ 4744 { 4745 { Bad_Opcode }, 4746 { Bad_Opcode }, 4747 { VEX_LEN_TABLE (VEX_LEN_0F383D_P_2) }, 4748 }, 4749 4750 /* PREFIX_VEX_0F383E */ 4751 { 4752 { Bad_Opcode }, 4753 { Bad_Opcode }, 4754 { VEX_LEN_TABLE (VEX_LEN_0F383E_P_2) }, 4755 }, 4756 4757 /* PREFIX_VEX_0F383F */ 4758 { 4759 { Bad_Opcode }, 4760 { Bad_Opcode }, 4761 { VEX_LEN_TABLE (VEX_LEN_0F383F_P_2) }, 4762 }, 4763 4764 /* PREFIX_VEX_0F3840 */ 4765 { 4766 { Bad_Opcode }, 4767 { Bad_Opcode }, 4768 { VEX_LEN_TABLE (VEX_LEN_0F3840_P_2) }, 4769 }, 4770 4771 /* PREFIX_VEX_0F3841 */ 4772 { 4773 { Bad_Opcode }, 4774 { Bad_Opcode }, 4775 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, 4776 }, 4777 4778 /* PREFIX_VEX_0F3896 */ 4779 { 4780 { Bad_Opcode }, 4781 { Bad_Opcode }, 4782 { "vfmaddsub132p%XW", { XM, Vex, EXx } }, 4783 }, 4784 4785 /* PREFIX_VEX_0F3897 */ 4786 { 4787 { Bad_Opcode }, 4788 { Bad_Opcode }, 4789 { "vfmsubadd132p%XW", { XM, Vex, EXx } }, 4790 }, 4791 4792 /* PREFIX_VEX_0F3898 */ 4793 { 4794 { Bad_Opcode }, 4795 { Bad_Opcode }, 4796 { "vfmadd132p%XW", { XM, Vex, EXx } }, 4797 }, 4798 4799 /* PREFIX_VEX_0F3899 */ 4800 { 4801 { Bad_Opcode }, 4802 { Bad_Opcode }, 4803 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4804 }, 4805 4806 /* PREFIX_VEX_0F389A */ 4807 { 4808 { Bad_Opcode }, 4809 { Bad_Opcode }, 4810 { "vfmsub132p%XW", { XM, Vex, EXx } }, 4811 }, 4812 4813 /* PREFIX_VEX_0F389B */ 4814 { 4815 { Bad_Opcode }, 4816 { Bad_Opcode }, 4817 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4818 }, 4819 4820 /* PREFIX_VEX_0F389C */ 4821 { 4822 { Bad_Opcode }, 4823 { Bad_Opcode }, 4824 { "vfnmadd132p%XW", { XM, Vex, EXx } }, 4825 }, 4826 4827 /* PREFIX_VEX_0F389D */ 4828 { 4829 { Bad_Opcode }, 4830 { Bad_Opcode }, 4831 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4832 }, 4833 4834 /* PREFIX_VEX_0F389E */ 4835 { 4836 { Bad_Opcode }, 4837 { Bad_Opcode }, 4838 { "vfnmsub132p%XW", { XM, Vex, EXx } }, 4839 }, 4840 4841 /* PREFIX_VEX_0F389F */ 4842 { 4843 { Bad_Opcode }, 4844 { Bad_Opcode }, 4845 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4846 }, 4847 4848 /* PREFIX_VEX_0F38A6 */ 4849 { 4850 { Bad_Opcode }, 4851 { Bad_Opcode }, 4852 { "vfmaddsub213p%XW", { XM, Vex, EXx } }, 4853 { Bad_Opcode }, 4854 }, 4855 4856 /* PREFIX_VEX_0F38A7 */ 4857 { 4858 { Bad_Opcode }, 4859 { Bad_Opcode }, 4860 { "vfmsubadd213p%XW", { XM, Vex, EXx } }, 4861 }, 4862 4863 /* PREFIX_VEX_0F38A8 */ 4864 { 4865 { Bad_Opcode }, 4866 { Bad_Opcode }, 4867 { "vfmadd213p%XW", { XM, Vex, EXx } }, 4868 }, 4869 4870 /* PREFIX_VEX_0F38A9 */ 4871 { 4872 { Bad_Opcode }, 4873 { Bad_Opcode }, 4874 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4875 }, 4876 4877 /* PREFIX_VEX_0F38AA */ 4878 { 4879 { Bad_Opcode }, 4880 { Bad_Opcode }, 4881 { "vfmsub213p%XW", { XM, Vex, EXx } }, 4882 }, 4883 4884 /* PREFIX_VEX_0F38AB */ 4885 { 4886 { Bad_Opcode }, 4887 { Bad_Opcode }, 4888 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4889 }, 4890 4891 /* PREFIX_VEX_0F38AC */ 4892 { 4893 { Bad_Opcode }, 4894 { Bad_Opcode }, 4895 { "vfnmadd213p%XW", { XM, Vex, EXx } }, 4896 }, 4897 4898 /* PREFIX_VEX_0F38AD */ 4899 { 4900 { Bad_Opcode }, 4901 { Bad_Opcode }, 4902 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4903 }, 4904 4905 /* PREFIX_VEX_0F38AE */ 4906 { 4907 { Bad_Opcode }, 4908 { Bad_Opcode }, 4909 { "vfnmsub213p%XW", { XM, Vex, EXx } }, 4910 }, 4911 4912 /* PREFIX_VEX_0F38AF */ 4913 { 4914 { Bad_Opcode }, 4915 { Bad_Opcode }, 4916 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4917 }, 4918 4919 /* PREFIX_VEX_0F38B6 */ 4920 { 4921 { Bad_Opcode }, 4922 { Bad_Opcode }, 4923 { "vfmaddsub231p%XW", { XM, Vex, EXx } }, 4924 }, 4925 4926 /* PREFIX_VEX_0F38B7 */ 4927 { 4928 { Bad_Opcode }, 4929 { Bad_Opcode }, 4930 { "vfmsubadd231p%XW", { XM, Vex, EXx } }, 4931 }, 4932 4933 /* PREFIX_VEX_0F38B8 */ 4934 { 4935 { Bad_Opcode }, 4936 { Bad_Opcode }, 4937 { "vfmadd231p%XW", { XM, Vex, EXx } }, 4938 }, 4939 4940 /* PREFIX_VEX_0F38B9 */ 4941 { 4942 { Bad_Opcode }, 4943 { Bad_Opcode }, 4944 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4945 }, 4946 4947 /* PREFIX_VEX_0F38BA */ 4948 { 4949 { Bad_Opcode }, 4950 { Bad_Opcode }, 4951 { "vfmsub231p%XW", { XM, Vex, EXx } }, 4952 }, 4953 4954 /* PREFIX_VEX_0F38BB */ 4955 { 4956 { Bad_Opcode }, 4957 { Bad_Opcode }, 4958 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4959 }, 4960 4961 /* PREFIX_VEX_0F38BC */ 4962 { 4963 { Bad_Opcode }, 4964 { Bad_Opcode }, 4965 { "vfnmadd231p%XW", { XM, Vex, EXx } }, 4966 }, 4967 4968 /* PREFIX_VEX_0F38BD */ 4969 { 4970 { Bad_Opcode }, 4971 { Bad_Opcode }, 4972 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4973 }, 4974 4975 /* PREFIX_VEX_0F38BE */ 4976 { 4977 { Bad_Opcode }, 4978 { Bad_Opcode }, 4979 { "vfnmsub231p%XW", { XM, Vex, EXx } }, 4980 }, 4981 4982 /* PREFIX_VEX_0F38BF */ 4983 { 4984 { Bad_Opcode }, 4985 { Bad_Opcode }, 4986 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, 4987 }, 4988 4989 /* PREFIX_VEX_0F38DB */ 4990 { 4991 { Bad_Opcode }, 4992 { Bad_Opcode }, 4993 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, 4994 }, 4995 4996 /* PREFIX_VEX_0F38DC */ 4997 { 4998 { Bad_Opcode }, 4999 { Bad_Opcode }, 5000 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, 5001 }, 5002 5003 /* PREFIX_VEX_0F38DD */ 5004 { 5005 { Bad_Opcode }, 5006 { Bad_Opcode }, 5007 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, 5008 }, 5009 5010 /* PREFIX_VEX_0F38DE */ 5011 { 5012 { Bad_Opcode }, 5013 { Bad_Opcode }, 5014 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, 5015 }, 5016 5017 /* PREFIX_VEX_0F38DF */ 5018 { 5019 { Bad_Opcode }, 5020 { Bad_Opcode }, 5021 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, 5022 }, 5023 5024 /* PREFIX_VEX_0F38F2 */ 5025 { 5026 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, 5027 }, 5028 5029 /* PREFIX_VEX_0F38F3_REG_1 */ 5030 { 5031 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, 5032 }, 5033 5034 /* PREFIX_VEX_0F38F3_REG_2 */ 5035 { 5036 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, 5037 }, 5038 5039 /* PREFIX_VEX_0F38F3_REG_3 */ 5040 { 5041 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, 5042 }, 5043 5044 /* PREFIX_VEX_0F38F7 */ 5045 { 5046 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, 5047 }, 5048 5049 /* PREFIX_VEX_0F3A04 */ 5050 { 5051 { Bad_Opcode }, 5052 { Bad_Opcode }, 5053 { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, 5054 }, 5055 5056 /* PREFIX_VEX_0F3A05 */ 5057 { 5058 { Bad_Opcode }, 5059 { Bad_Opcode }, 5060 { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, 5061 }, 5062 5063 /* PREFIX_VEX_0F3A06 */ 5064 { 5065 { Bad_Opcode }, 5066 { Bad_Opcode }, 5067 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, 5068 }, 5069 5070 /* PREFIX_VEX_0F3A08 */ 5071 { 5072 { Bad_Opcode }, 5073 { Bad_Opcode }, 5074 { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, 5075 }, 5076 5077 /* PREFIX_VEX_0F3A09 */ 5078 { 5079 { Bad_Opcode }, 5080 { Bad_Opcode }, 5081 { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, 5082 }, 5083 5084 /* PREFIX_VEX_0F3A0A */ 5085 { 5086 { Bad_Opcode }, 5087 { Bad_Opcode }, 5088 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, 5089 }, 5090 5091 /* PREFIX_VEX_0F3A0B */ 5092 { 5093 { Bad_Opcode }, 5094 { Bad_Opcode }, 5095 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, 5096 }, 5097 5098 /* PREFIX_VEX_0F3A0C */ 5099 { 5100 { Bad_Opcode }, 5101 { Bad_Opcode }, 5102 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, 5103 }, 5104 5105 /* PREFIX_VEX_0F3A0D */ 5106 { 5107 { Bad_Opcode }, 5108 { Bad_Opcode }, 5109 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, 5110 }, 5111 5112 /* PREFIX_VEX_0F3A0E */ 5113 { 5114 { Bad_Opcode }, 5115 { Bad_Opcode }, 5116 { VEX_LEN_TABLE (VEX_LEN_0F3A0E_P_2) }, 5117 }, 5118 5119 /* PREFIX_VEX_0F3A0F */ 5120 { 5121 { Bad_Opcode }, 5122 { Bad_Opcode }, 5123 { VEX_LEN_TABLE (VEX_LEN_0F3A0F_P_2) }, 5124 }, 5125 5126 /* PREFIX_VEX_0F3A14 */ 5127 { 5128 { Bad_Opcode }, 5129 { Bad_Opcode }, 5130 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, 5131 }, 5132 5133 /* PREFIX_VEX_0F3A15 */ 5134 { 5135 { Bad_Opcode }, 5136 { Bad_Opcode }, 5137 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, 5138 }, 5139 5140 /* PREFIX_VEX_0F3A16 */ 5141 { 5142 { Bad_Opcode }, 5143 { Bad_Opcode }, 5144 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, 5145 }, 5146 5147 /* PREFIX_VEX_0F3A17 */ 5148 { 5149 { Bad_Opcode }, 5150 { Bad_Opcode }, 5151 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, 5152 }, 5153 5154 /* PREFIX_VEX_0F3A18 */ 5155 { 5156 { Bad_Opcode }, 5157 { Bad_Opcode }, 5158 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, 5159 }, 5160 5161 /* PREFIX_VEX_0F3A19 */ 5162 { 5163 { Bad_Opcode }, 5164 { Bad_Opcode }, 5165 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, 5166 }, 5167 5168 /* PREFIX_VEX_0F3A1D */ 5169 { 5170 { Bad_Opcode }, 5171 { Bad_Opcode }, 5172 { "vcvtps2ph", { EXxmmq, XM, Ib } }, 5173 }, 5174 5175 /* PREFIX_VEX_0F3A20 */ 5176 { 5177 { Bad_Opcode }, 5178 { Bad_Opcode }, 5179 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, 5180 }, 5181 5182 /* PREFIX_VEX_0F3A21 */ 5183 { 5184 { Bad_Opcode }, 5185 { Bad_Opcode }, 5186 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, 5187 }, 5188 5189 /* PREFIX_VEX_0F3A22 */ 5190 { 5191 { Bad_Opcode }, 5192 { Bad_Opcode }, 5193 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, 5194 }, 5195 5196 /* PREFIX_VEX_0F3A40 */ 5197 { 5198 { Bad_Opcode }, 5199 { Bad_Opcode }, 5200 { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, 5201 }, 5202 5203 /* PREFIX_VEX_0F3A41 */ 5204 { 5205 { Bad_Opcode }, 5206 { Bad_Opcode }, 5207 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, 5208 }, 5209 5210 /* PREFIX_VEX_0F3A42 */ 5211 { 5212 { Bad_Opcode }, 5213 { Bad_Opcode }, 5214 { VEX_LEN_TABLE (VEX_LEN_0F3A42_P_2) }, 5215 }, 5216 5217 /* PREFIX_VEX_0F3A44 */ 5218 { 5219 { Bad_Opcode }, 5220 { Bad_Opcode }, 5221 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, 5222 }, 5223 5224 /* PREFIX_VEX_0F3A48 */ 5225 { 5226 { Bad_Opcode }, 5227 { Bad_Opcode }, 5228 { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, 5229 }, 5230 5231 /* PREFIX_VEX_0F3A49 */ 5232 { 5233 { Bad_Opcode }, 5234 { Bad_Opcode }, 5235 { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, 5236 }, 5237 5238 /* PREFIX_VEX_0F3A4A */ 5239 { 5240 { Bad_Opcode }, 5241 { Bad_Opcode }, 5242 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, 5243 }, 5244 5245 /* PREFIX_VEX_0F3A4B */ 5246 { 5247 { Bad_Opcode }, 5248 { Bad_Opcode }, 5249 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, 5250 }, 5251 5252 /* PREFIX_VEX_0F3A4C */ 5253 { 5254 { Bad_Opcode }, 5255 { Bad_Opcode }, 5256 { VEX_LEN_TABLE (VEX_LEN_0F3A4C_P_2) }, 5257 }, 5258 5259 /* PREFIX_VEX_0F3A5C */ 5260 { 5261 { Bad_Opcode }, 5262 { Bad_Opcode }, 5263 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5264 }, 5265 5266 /* PREFIX_VEX_0F3A5D */ 5267 { 5268 { Bad_Opcode }, 5269 { Bad_Opcode }, 5270 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5271 }, 5272 5273 /* PREFIX_VEX_0F3A5E */ 5274 { 5275 { Bad_Opcode }, 5276 { Bad_Opcode }, 5277 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5278 }, 5279 5280 /* PREFIX_VEX_0F3A5F */ 5281 { 5282 { Bad_Opcode }, 5283 { Bad_Opcode }, 5284 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5285 }, 5286 5287 /* PREFIX_VEX_0F3A60 */ 5288 { 5289 { Bad_Opcode }, 5290 { Bad_Opcode }, 5291 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, 5292 { Bad_Opcode }, 5293 }, 5294 5295 /* PREFIX_VEX_0F3A61 */ 5296 { 5297 { Bad_Opcode }, 5298 { Bad_Opcode }, 5299 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, 5300 }, 5301 5302 /* PREFIX_VEX_0F3A62 */ 5303 { 5304 { Bad_Opcode }, 5305 { Bad_Opcode }, 5306 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, 5307 }, 5308 5309 /* PREFIX_VEX_0F3A63 */ 5310 { 5311 { Bad_Opcode }, 5312 { Bad_Opcode }, 5313 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, 5314 }, 5315 5316 /* PREFIX_VEX_0F3A68 */ 5317 { 5318 { Bad_Opcode }, 5319 { Bad_Opcode }, 5320 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5321 }, 5322 5323 /* PREFIX_VEX_0F3A69 */ 5324 { 5325 { Bad_Opcode }, 5326 { Bad_Opcode }, 5327 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5328 }, 5329 5330 /* PREFIX_VEX_0F3A6A */ 5331 { 5332 { Bad_Opcode }, 5333 { Bad_Opcode }, 5334 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, 5335 }, 5336 5337 /* PREFIX_VEX_0F3A6B */ 5338 { 5339 { Bad_Opcode }, 5340 { Bad_Opcode }, 5341 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, 5342 }, 5343 5344 /* PREFIX_VEX_0F3A6C */ 5345 { 5346 { Bad_Opcode }, 5347 { Bad_Opcode }, 5348 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5349 }, 5350 5351 /* PREFIX_VEX_0F3A6D */ 5352 { 5353 { Bad_Opcode }, 5354 { Bad_Opcode }, 5355 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5356 }, 5357 5358 /* PREFIX_VEX_0F3A6E */ 5359 { 5360 { Bad_Opcode }, 5361 { Bad_Opcode }, 5362 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, 5363 }, 5364 5365 /* PREFIX_VEX_0F3A6F */ 5366 { 5367 { Bad_Opcode }, 5368 { Bad_Opcode }, 5369 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, 5370 }, 5371 5372 /* PREFIX_VEX_0F3A78 */ 5373 { 5374 { Bad_Opcode }, 5375 { Bad_Opcode }, 5376 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5377 }, 5378 5379 /* PREFIX_VEX_0F3A79 */ 5380 { 5381 { Bad_Opcode }, 5382 { Bad_Opcode }, 5383 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5384 }, 5385 5386 /* PREFIX_VEX_0F3A7A */ 5387 { 5388 { Bad_Opcode }, 5389 { Bad_Opcode }, 5390 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, 5391 }, 5392 5393 /* PREFIX_VEX_0F3A7B */ 5394 { 5395 { Bad_Opcode }, 5396 { Bad_Opcode }, 5397 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, 5398 }, 5399 5400 /* PREFIX_VEX_0F3A7C */ 5401 { 5402 { Bad_Opcode }, 5403 { Bad_Opcode }, 5404 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5405 { Bad_Opcode }, 5406 }, 5407 5408 /* PREFIX_VEX_0F3A7D */ 5409 { 5410 { Bad_Opcode }, 5411 { Bad_Opcode }, 5412 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 5413 }, 5414 5415 /* PREFIX_VEX_0F3A7E */ 5416 { 5417 { Bad_Opcode }, 5418 { Bad_Opcode }, 5419 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, 5420 }, 5421 5422 /* PREFIX_VEX_0F3A7F */ 5423 { 5424 { Bad_Opcode }, 5425 { Bad_Opcode }, 5426 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, 5427 }, 5428 5429 /* PREFIX_VEX_0F3ADF */ 5430 { 5431 { Bad_Opcode }, 5432 { Bad_Opcode }, 5433 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, 5434 }, 5435 }; 5436 5437 static const struct dis386 x86_64_table[][2] = { 5438 /* X86_64_06 */ 5439 { 5440 { "pushP", { es } }, 5441 }, 5442 5443 /* X86_64_07 */ 5444 { 5445 { "popP", { es } }, 5446 }, 5447 5448 /* X86_64_0D */ 5449 { 5450 { "pushP", { cs } }, 5451 }, 5452 5453 /* X86_64_16 */ 5454 { 5455 { "pushP", { ss } }, 5456 }, 5457 5458 /* X86_64_17 */ 5459 { 5460 { "popP", { ss } }, 5461 }, 5462 5463 /* X86_64_1E */ 5464 { 5465 { "pushP", { ds } }, 5466 }, 5467 5468 /* X86_64_1F */ 5469 { 5470 { "popP", { ds } }, 5471 }, 5472 5473 /* X86_64_27 */ 5474 { 5475 { "daa", { XX } }, 5476 }, 5477 5478 /* X86_64_2F */ 5479 { 5480 { "das", { XX } }, 5481 }, 5482 5483 /* X86_64_37 */ 5484 { 5485 { "aaa", { XX } }, 5486 }, 5487 5488 /* X86_64_3F */ 5489 { 5490 { "aas", { XX } }, 5491 }, 5492 5493 /* X86_64_60 */ 5494 { 5495 { "pushaP", { XX } }, 5496 }, 5497 5498 /* X86_64_61 */ 5499 { 5500 { "popaP", { XX } }, 5501 }, 5502 5503 /* X86_64_62 */ 5504 { 5505 { MOD_TABLE (MOD_62_32BIT) }, 5506 }, 5507 5508 /* X86_64_63 */ 5509 { 5510 { "arpl", { Ew, Gw } }, 5511 { "movs{lq|xd}", { Gv, Ed } }, 5512 }, 5513 5514 /* X86_64_6D */ 5515 { 5516 { "ins{R|}", { Yzr, indirDX } }, 5517 { "ins{G|}", { Yzr, indirDX } }, 5518 }, 5519 5520 /* X86_64_6F */ 5521 { 5522 { "outs{R|}", { indirDXr, Xz } }, 5523 { "outs{G|}", { indirDXr, Xz } }, 5524 }, 5525 5526 /* X86_64_9A */ 5527 { 5528 { "Jcall{T|}", { Ap } }, 5529 }, 5530 5531 /* X86_64_C4 */ 5532 { 5533 { MOD_TABLE (MOD_C4_32BIT) }, 5534 { VEX_C4_TABLE (VEX_0F) }, 5535 }, 5536 5537 /* X86_64_C5 */ 5538 { 5539 { MOD_TABLE (MOD_C5_32BIT) }, 5540 { VEX_C5_TABLE (VEX_0F) }, 5541 }, 5542 5543 /* X86_64_CE */ 5544 { 5545 { "into", { XX } }, 5546 }, 5547 5548 /* X86_64_D4 */ 5549 { 5550 { "aam", { Ib } }, 5551 }, 5552 5553 /* X86_64_D5 */ 5554 { 5555 { "aad", { Ib } }, 5556 }, 5557 5558 /* X86_64_EA */ 5559 { 5560 { "Jjmp{T|}", { Ap } }, 5561 }, 5562 5563 /* X86_64_0F01_REG_0 */ 5564 { 5565 { "sgdt{Q|IQ}", { M } }, 5566 { "sgdt", { M } }, 5567 }, 5568 5569 /* X86_64_0F01_REG_1 */ 5570 { 5571 { "sidt{Q|IQ}", { M } }, 5572 { "sidt", { M } }, 5573 }, 5574 5575 /* X86_64_0F01_REG_2 */ 5576 { 5577 { "lgdt{Q|Q}", { M } }, 5578 { "lgdt", { M } }, 5579 }, 5580 5581 /* X86_64_0F01_REG_3 */ 5582 { 5583 { "lidt{Q|Q}", { M } }, 5584 { "lidt", { M } }, 5585 }, 5586 }; 5587 5588 static const struct dis386 three_byte_table[][256] = { 5589 5590 /* THREE_BYTE_0F38 */ 5591 { 5592 /* 00 */ 5593 { "pshufb", { MX, EM } }, 5594 { "phaddw", { MX, EM } }, 5595 { "phaddd", { MX, EM } }, 5596 { "phaddsw", { MX, EM } }, 5597 { "pmaddubsw", { MX, EM } }, 5598 { "phsubw", { MX, EM } }, 5599 { "phsubd", { MX, EM } }, 5600 { "phsubsw", { MX, EM } }, 5601 /* 08 */ 5602 { "psignb", { MX, EM } }, 5603 { "psignw", { MX, EM } }, 5604 { "psignd", { MX, EM } }, 5605 { "pmulhrsw", { MX, EM } }, 5606 { Bad_Opcode }, 5607 { Bad_Opcode }, 5608 { Bad_Opcode }, 5609 { Bad_Opcode }, 5610 /* 10 */ 5611 { PREFIX_TABLE (PREFIX_0F3810) }, 5612 { Bad_Opcode }, 5613 { Bad_Opcode }, 5614 { Bad_Opcode }, 5615 { PREFIX_TABLE (PREFIX_0F3814) }, 5616 { PREFIX_TABLE (PREFIX_0F3815) }, 5617 { Bad_Opcode }, 5618 { PREFIX_TABLE (PREFIX_0F3817) }, 5619 /* 18 */ 5620 { Bad_Opcode }, 5621 { Bad_Opcode }, 5622 { Bad_Opcode }, 5623 { Bad_Opcode }, 5624 { "pabsb", { MX, EM } }, 5625 { "pabsw", { MX, EM } }, 5626 { "pabsd", { MX, EM } }, 5627 { Bad_Opcode }, 5628 /* 20 */ 5629 { PREFIX_TABLE (PREFIX_0F3820) }, 5630 { PREFIX_TABLE (PREFIX_0F3821) }, 5631 { PREFIX_TABLE (PREFIX_0F3822) }, 5632 { PREFIX_TABLE (PREFIX_0F3823) }, 5633 { PREFIX_TABLE (PREFIX_0F3824) }, 5634 { PREFIX_TABLE (PREFIX_0F3825) }, 5635 { Bad_Opcode }, 5636 { Bad_Opcode }, 5637 /* 28 */ 5638 { PREFIX_TABLE (PREFIX_0F3828) }, 5639 { PREFIX_TABLE (PREFIX_0F3829) }, 5640 { PREFIX_TABLE (PREFIX_0F382A) }, 5641 { PREFIX_TABLE (PREFIX_0F382B) }, 5642 { Bad_Opcode }, 5643 { Bad_Opcode }, 5644 { Bad_Opcode }, 5645 { Bad_Opcode }, 5646 /* 30 */ 5647 { PREFIX_TABLE (PREFIX_0F3830) }, 5648 { PREFIX_TABLE (PREFIX_0F3831) }, 5649 { PREFIX_TABLE (PREFIX_0F3832) }, 5650 { PREFIX_TABLE (PREFIX_0F3833) }, 5651 { PREFIX_TABLE (PREFIX_0F3834) }, 5652 { PREFIX_TABLE (PREFIX_0F3835) }, 5653 { Bad_Opcode }, 5654 { PREFIX_TABLE (PREFIX_0F3837) }, 5655 /* 38 */ 5656 { PREFIX_TABLE (PREFIX_0F3838) }, 5657 { PREFIX_TABLE (PREFIX_0F3839) }, 5658 { PREFIX_TABLE (PREFIX_0F383A) }, 5659 { PREFIX_TABLE (PREFIX_0F383B) }, 5660 { PREFIX_TABLE (PREFIX_0F383C) }, 5661 { PREFIX_TABLE (PREFIX_0F383D) }, 5662 { PREFIX_TABLE (PREFIX_0F383E) }, 5663 { PREFIX_TABLE (PREFIX_0F383F) }, 5664 /* 40 */ 5665 { PREFIX_TABLE (PREFIX_0F3840) }, 5666 { PREFIX_TABLE (PREFIX_0F3841) }, 5667 { Bad_Opcode }, 5668 { Bad_Opcode }, 5669 { Bad_Opcode }, 5670 { Bad_Opcode }, 5671 { Bad_Opcode }, 5672 { Bad_Opcode }, 5673 /* 48 */ 5674 { Bad_Opcode }, 5675 { Bad_Opcode }, 5676 { Bad_Opcode }, 5677 { Bad_Opcode }, 5678 { Bad_Opcode }, 5679 { Bad_Opcode }, 5680 { Bad_Opcode }, 5681 { Bad_Opcode }, 5682 /* 50 */ 5683 { Bad_Opcode }, 5684 { Bad_Opcode }, 5685 { Bad_Opcode }, 5686 { Bad_Opcode }, 5687 { Bad_Opcode }, 5688 { Bad_Opcode }, 5689 { Bad_Opcode }, 5690 { Bad_Opcode }, 5691 /* 58 */ 5692 { Bad_Opcode }, 5693 { Bad_Opcode }, 5694 { Bad_Opcode }, 5695 { Bad_Opcode }, 5696 { Bad_Opcode }, 5697 { Bad_Opcode }, 5698 { Bad_Opcode }, 5699 { Bad_Opcode }, 5700 /* 60 */ 5701 { Bad_Opcode }, 5702 { Bad_Opcode }, 5703 { Bad_Opcode }, 5704 { Bad_Opcode }, 5705 { Bad_Opcode }, 5706 { Bad_Opcode }, 5707 { Bad_Opcode }, 5708 { Bad_Opcode }, 5709 /* 68 */ 5710 { Bad_Opcode }, 5711 { Bad_Opcode }, 5712 { Bad_Opcode }, 5713 { Bad_Opcode }, 5714 { Bad_Opcode }, 5715 { Bad_Opcode }, 5716 { Bad_Opcode }, 5717 { Bad_Opcode }, 5718 /* 70 */ 5719 { Bad_Opcode }, 5720 { Bad_Opcode }, 5721 { Bad_Opcode }, 5722 { Bad_Opcode }, 5723 { Bad_Opcode }, 5724 { Bad_Opcode }, 5725 { Bad_Opcode }, 5726 { Bad_Opcode }, 5727 /* 78 */ 5728 { Bad_Opcode }, 5729 { Bad_Opcode }, 5730 { Bad_Opcode }, 5731 { Bad_Opcode }, 5732 { Bad_Opcode }, 5733 { Bad_Opcode }, 5734 { Bad_Opcode }, 5735 { Bad_Opcode }, 5736 /* 80 */ 5737 { PREFIX_TABLE (PREFIX_0F3880) }, 5738 { PREFIX_TABLE (PREFIX_0F3881) }, 5739 { Bad_Opcode }, 5740 { Bad_Opcode }, 5741 { Bad_Opcode }, 5742 { Bad_Opcode }, 5743 { Bad_Opcode }, 5744 { Bad_Opcode }, 5745 /* 88 */ 5746 { Bad_Opcode }, 5747 { Bad_Opcode }, 5748 { Bad_Opcode }, 5749 { Bad_Opcode }, 5750 { Bad_Opcode }, 5751 { Bad_Opcode }, 5752 { Bad_Opcode }, 5753 { Bad_Opcode }, 5754 /* 90 */ 5755 { Bad_Opcode }, 5756 { Bad_Opcode }, 5757 { Bad_Opcode }, 5758 { Bad_Opcode }, 5759 { Bad_Opcode }, 5760 { Bad_Opcode }, 5761 { Bad_Opcode }, 5762 { Bad_Opcode }, 5763 /* 98 */ 5764 { Bad_Opcode }, 5765 { Bad_Opcode }, 5766 { Bad_Opcode }, 5767 { Bad_Opcode }, 5768 { Bad_Opcode }, 5769 { Bad_Opcode }, 5770 { Bad_Opcode }, 5771 { Bad_Opcode }, 5772 /* a0 */ 5773 { Bad_Opcode }, 5774 { Bad_Opcode }, 5775 { Bad_Opcode }, 5776 { Bad_Opcode }, 5777 { Bad_Opcode }, 5778 { Bad_Opcode }, 5779 { Bad_Opcode }, 5780 { Bad_Opcode }, 5781 /* a8 */ 5782 { Bad_Opcode }, 5783 { Bad_Opcode }, 5784 { Bad_Opcode }, 5785 { Bad_Opcode }, 5786 { Bad_Opcode }, 5787 { Bad_Opcode }, 5788 { Bad_Opcode }, 5789 { Bad_Opcode }, 5790 /* b0 */ 5791 { Bad_Opcode }, 5792 { Bad_Opcode }, 5793 { Bad_Opcode }, 5794 { Bad_Opcode }, 5795 { Bad_Opcode }, 5796 { Bad_Opcode }, 5797 { Bad_Opcode }, 5798 { Bad_Opcode }, 5799 /* b8 */ 5800 { Bad_Opcode }, 5801 { Bad_Opcode }, 5802 { Bad_Opcode }, 5803 { Bad_Opcode }, 5804 { Bad_Opcode }, 5805 { Bad_Opcode }, 5806 { Bad_Opcode }, 5807 { Bad_Opcode }, 5808 /* c0 */ 5809 { Bad_Opcode }, 5810 { Bad_Opcode }, 5811 { Bad_Opcode }, 5812 { Bad_Opcode }, 5813 { Bad_Opcode }, 5814 { Bad_Opcode }, 5815 { Bad_Opcode }, 5816 { Bad_Opcode }, 5817 /* c8 */ 5818 { Bad_Opcode }, 5819 { Bad_Opcode }, 5820 { Bad_Opcode }, 5821 { Bad_Opcode }, 5822 { Bad_Opcode }, 5823 { Bad_Opcode }, 5824 { Bad_Opcode }, 5825 { Bad_Opcode }, 5826 /* d0 */ 5827 { Bad_Opcode }, 5828 { Bad_Opcode }, 5829 { Bad_Opcode }, 5830 { Bad_Opcode }, 5831 { Bad_Opcode }, 5832 { Bad_Opcode }, 5833 { Bad_Opcode }, 5834 { Bad_Opcode }, 5835 /* d8 */ 5836 { Bad_Opcode }, 5837 { Bad_Opcode }, 5838 { Bad_Opcode }, 5839 { PREFIX_TABLE (PREFIX_0F38DB) }, 5840 { PREFIX_TABLE (PREFIX_0F38DC) }, 5841 { PREFIX_TABLE (PREFIX_0F38DD) }, 5842 { PREFIX_TABLE (PREFIX_0F38DE) }, 5843 { PREFIX_TABLE (PREFIX_0F38DF) }, 5844 /* e0 */ 5845 { Bad_Opcode }, 5846 { Bad_Opcode }, 5847 { Bad_Opcode }, 5848 { Bad_Opcode }, 5849 { Bad_Opcode }, 5850 { Bad_Opcode }, 5851 { Bad_Opcode }, 5852 { Bad_Opcode }, 5853 /* e8 */ 5854 { Bad_Opcode }, 5855 { Bad_Opcode }, 5856 { Bad_Opcode }, 5857 { Bad_Opcode }, 5858 { Bad_Opcode }, 5859 { Bad_Opcode }, 5860 { Bad_Opcode }, 5861 { Bad_Opcode }, 5862 /* f0 */ 5863 { PREFIX_TABLE (PREFIX_0F38F0) }, 5864 { PREFIX_TABLE (PREFIX_0F38F1) }, 5865 { Bad_Opcode }, 5866 { Bad_Opcode }, 5867 { Bad_Opcode }, 5868 { Bad_Opcode }, 5869 { Bad_Opcode }, 5870 { Bad_Opcode }, 5871 /* f8 */ 5872 { Bad_Opcode }, 5873 { Bad_Opcode }, 5874 { Bad_Opcode }, 5875 { Bad_Opcode }, 5876 { Bad_Opcode }, 5877 { Bad_Opcode }, 5878 { Bad_Opcode }, 5879 { Bad_Opcode }, 5880 }, 5881 /* THREE_BYTE_0F3A */ 5882 { 5883 /* 00 */ 5884 { Bad_Opcode }, 5885 { Bad_Opcode }, 5886 { Bad_Opcode }, 5887 { Bad_Opcode }, 5888 { Bad_Opcode }, 5889 { Bad_Opcode }, 5890 { Bad_Opcode }, 5891 { Bad_Opcode }, 5892 /* 08 */ 5893 { PREFIX_TABLE (PREFIX_0F3A08) }, 5894 { PREFIX_TABLE (PREFIX_0F3A09) }, 5895 { PREFIX_TABLE (PREFIX_0F3A0A) }, 5896 { PREFIX_TABLE (PREFIX_0F3A0B) }, 5897 { PREFIX_TABLE (PREFIX_0F3A0C) }, 5898 { PREFIX_TABLE (PREFIX_0F3A0D) }, 5899 { PREFIX_TABLE (PREFIX_0F3A0E) }, 5900 { "palignr", { MX, EM, Ib } }, 5901 /* 10 */ 5902 { Bad_Opcode }, 5903 { Bad_Opcode }, 5904 { Bad_Opcode }, 5905 { Bad_Opcode }, 5906 { PREFIX_TABLE (PREFIX_0F3A14) }, 5907 { PREFIX_TABLE (PREFIX_0F3A15) }, 5908 { PREFIX_TABLE (PREFIX_0F3A16) }, 5909 { PREFIX_TABLE (PREFIX_0F3A17) }, 5910 /* 18 */ 5911 { Bad_Opcode }, 5912 { Bad_Opcode }, 5913 { Bad_Opcode }, 5914 { Bad_Opcode }, 5915 { Bad_Opcode }, 5916 { Bad_Opcode }, 5917 { Bad_Opcode }, 5918 { Bad_Opcode }, 5919 /* 20 */ 5920 { PREFIX_TABLE (PREFIX_0F3A20) }, 5921 { PREFIX_TABLE (PREFIX_0F3A21) }, 5922 { PREFIX_TABLE (PREFIX_0F3A22) }, 5923 { Bad_Opcode }, 5924 { Bad_Opcode }, 5925 { Bad_Opcode }, 5926 { Bad_Opcode }, 5927 { Bad_Opcode }, 5928 /* 28 */ 5929 { Bad_Opcode }, 5930 { Bad_Opcode }, 5931 { Bad_Opcode }, 5932 { Bad_Opcode }, 5933 { Bad_Opcode }, 5934 { Bad_Opcode }, 5935 { Bad_Opcode }, 5936 { Bad_Opcode }, 5937 /* 30 */ 5938 { Bad_Opcode }, 5939 { Bad_Opcode }, 5940 { Bad_Opcode }, 5941 { Bad_Opcode }, 5942 { Bad_Opcode }, 5943 { Bad_Opcode }, 5944 { Bad_Opcode }, 5945 { Bad_Opcode }, 5946 /* 38 */ 5947 { Bad_Opcode }, 5948 { Bad_Opcode }, 5949 { Bad_Opcode }, 5950 { Bad_Opcode }, 5951 { Bad_Opcode }, 5952 { Bad_Opcode }, 5953 { Bad_Opcode }, 5954 { Bad_Opcode }, 5955 /* 40 */ 5956 { PREFIX_TABLE (PREFIX_0F3A40) }, 5957 { PREFIX_TABLE (PREFIX_0F3A41) }, 5958 { PREFIX_TABLE (PREFIX_0F3A42) }, 5959 { Bad_Opcode }, 5960 { PREFIX_TABLE (PREFIX_0F3A44) }, 5961 { Bad_Opcode }, 5962 { Bad_Opcode }, 5963 { Bad_Opcode }, 5964 /* 48 */ 5965 { Bad_Opcode }, 5966 { Bad_Opcode }, 5967 { Bad_Opcode }, 5968 { Bad_Opcode }, 5969 { Bad_Opcode }, 5970 { Bad_Opcode }, 5971 { Bad_Opcode }, 5972 { Bad_Opcode }, 5973 /* 50 */ 5974 { Bad_Opcode }, 5975 { Bad_Opcode }, 5976 { Bad_Opcode }, 5977 { Bad_Opcode }, 5978 { Bad_Opcode }, 5979 { Bad_Opcode }, 5980 { Bad_Opcode }, 5981 { Bad_Opcode }, 5982 /* 58 */ 5983 { Bad_Opcode }, 5984 { Bad_Opcode }, 5985 { Bad_Opcode }, 5986 { Bad_Opcode }, 5987 { Bad_Opcode }, 5988 { Bad_Opcode }, 5989 { Bad_Opcode }, 5990 { Bad_Opcode }, 5991 /* 60 */ 5992 { PREFIX_TABLE (PREFIX_0F3A60) }, 5993 { PREFIX_TABLE (PREFIX_0F3A61) }, 5994 { PREFIX_TABLE (PREFIX_0F3A62) }, 5995 { PREFIX_TABLE (PREFIX_0F3A63) }, 5996 { Bad_Opcode }, 5997 { Bad_Opcode }, 5998 { Bad_Opcode }, 5999 { Bad_Opcode }, 6000 /* 68 */ 6001 { Bad_Opcode }, 6002 { Bad_Opcode }, 6003 { Bad_Opcode }, 6004 { Bad_Opcode }, 6005 { Bad_Opcode }, 6006 { Bad_Opcode }, 6007 { Bad_Opcode }, 6008 { Bad_Opcode }, 6009 /* 70 */ 6010 { Bad_Opcode }, 6011 { Bad_Opcode }, 6012 { Bad_Opcode }, 6013 { Bad_Opcode }, 6014 { Bad_Opcode }, 6015 { Bad_Opcode }, 6016 { Bad_Opcode }, 6017 { Bad_Opcode }, 6018 /* 78 */ 6019 { Bad_Opcode }, 6020 { Bad_Opcode }, 6021 { Bad_Opcode }, 6022 { Bad_Opcode }, 6023 { Bad_Opcode }, 6024 { Bad_Opcode }, 6025 { Bad_Opcode }, 6026 { Bad_Opcode }, 6027 /* 80 */ 6028 { Bad_Opcode }, 6029 { Bad_Opcode }, 6030 { Bad_Opcode }, 6031 { Bad_Opcode }, 6032 { Bad_Opcode }, 6033 { Bad_Opcode }, 6034 { Bad_Opcode }, 6035 { Bad_Opcode }, 6036 /* 88 */ 6037 { Bad_Opcode }, 6038 { Bad_Opcode }, 6039 { Bad_Opcode }, 6040 { Bad_Opcode }, 6041 { Bad_Opcode }, 6042 { Bad_Opcode }, 6043 { Bad_Opcode }, 6044 { Bad_Opcode }, 6045 /* 90 */ 6046 { Bad_Opcode }, 6047 { Bad_Opcode }, 6048 { Bad_Opcode }, 6049 { Bad_Opcode }, 6050 { Bad_Opcode }, 6051 { Bad_Opcode }, 6052 { Bad_Opcode }, 6053 { Bad_Opcode }, 6054 /* 98 */ 6055 { Bad_Opcode }, 6056 { Bad_Opcode }, 6057 { Bad_Opcode }, 6058 { Bad_Opcode }, 6059 { Bad_Opcode }, 6060 { Bad_Opcode }, 6061 { Bad_Opcode }, 6062 { Bad_Opcode }, 6063 /* a0 */ 6064 { Bad_Opcode }, 6065 { Bad_Opcode }, 6066 { Bad_Opcode }, 6067 { Bad_Opcode }, 6068 { Bad_Opcode }, 6069 { Bad_Opcode }, 6070 { Bad_Opcode }, 6071 { Bad_Opcode }, 6072 /* a8 */ 6073 { Bad_Opcode }, 6074 { Bad_Opcode }, 6075 { Bad_Opcode }, 6076 { Bad_Opcode }, 6077 { Bad_Opcode }, 6078 { Bad_Opcode }, 6079 { Bad_Opcode }, 6080 { Bad_Opcode }, 6081 /* b0 */ 6082 { Bad_Opcode }, 6083 { Bad_Opcode }, 6084 { Bad_Opcode }, 6085 { Bad_Opcode }, 6086 { Bad_Opcode }, 6087 { Bad_Opcode }, 6088 { Bad_Opcode }, 6089 { Bad_Opcode }, 6090 /* b8 */ 6091 { Bad_Opcode }, 6092 { Bad_Opcode }, 6093 { Bad_Opcode }, 6094 { Bad_Opcode }, 6095 { Bad_Opcode }, 6096 { Bad_Opcode }, 6097 { Bad_Opcode }, 6098 { Bad_Opcode }, 6099 /* c0 */ 6100 { Bad_Opcode }, 6101 { Bad_Opcode }, 6102 { Bad_Opcode }, 6103 { Bad_Opcode }, 6104 { Bad_Opcode }, 6105 { Bad_Opcode }, 6106 { Bad_Opcode }, 6107 { Bad_Opcode }, 6108 /* c8 */ 6109 { Bad_Opcode }, 6110 { Bad_Opcode }, 6111 { Bad_Opcode }, 6112 { Bad_Opcode }, 6113 { Bad_Opcode }, 6114 { Bad_Opcode }, 6115 { Bad_Opcode }, 6116 { Bad_Opcode }, 6117 /* d0 */ 6118 { Bad_Opcode }, 6119 { Bad_Opcode }, 6120 { Bad_Opcode }, 6121 { Bad_Opcode }, 6122 { Bad_Opcode }, 6123 { Bad_Opcode }, 6124 { Bad_Opcode }, 6125 { Bad_Opcode }, 6126 /* d8 */ 6127 { Bad_Opcode }, 6128 { Bad_Opcode }, 6129 { Bad_Opcode }, 6130 { Bad_Opcode }, 6131 { Bad_Opcode }, 6132 { Bad_Opcode }, 6133 { Bad_Opcode }, 6134 { PREFIX_TABLE (PREFIX_0F3ADF) }, 6135 /* e0 */ 6136 { Bad_Opcode }, 6137 { Bad_Opcode }, 6138 { Bad_Opcode }, 6139 { Bad_Opcode }, 6140 { Bad_Opcode }, 6141 { Bad_Opcode }, 6142 { Bad_Opcode }, 6143 { Bad_Opcode }, 6144 /* e8 */ 6145 { Bad_Opcode }, 6146 { Bad_Opcode }, 6147 { Bad_Opcode }, 6148 { Bad_Opcode }, 6149 { Bad_Opcode }, 6150 { Bad_Opcode }, 6151 { Bad_Opcode }, 6152 { Bad_Opcode }, 6153 /* f0 */ 6154 { Bad_Opcode }, 6155 { Bad_Opcode }, 6156 { Bad_Opcode }, 6157 { Bad_Opcode }, 6158 { Bad_Opcode }, 6159 { Bad_Opcode }, 6160 { Bad_Opcode }, 6161 { Bad_Opcode }, 6162 /* f8 */ 6163 { Bad_Opcode }, 6164 { Bad_Opcode }, 6165 { Bad_Opcode }, 6166 { Bad_Opcode }, 6167 { Bad_Opcode }, 6168 { Bad_Opcode }, 6169 { Bad_Opcode }, 6170 { Bad_Opcode }, 6171 }, 6172 6173 /* THREE_BYTE_0F7A */ 6174 { 6175 /* 00 */ 6176 { Bad_Opcode }, 6177 { Bad_Opcode }, 6178 { Bad_Opcode }, 6179 { Bad_Opcode }, 6180 { Bad_Opcode }, 6181 { Bad_Opcode }, 6182 { Bad_Opcode }, 6183 { Bad_Opcode }, 6184 /* 08 */ 6185 { Bad_Opcode }, 6186 { Bad_Opcode }, 6187 { Bad_Opcode }, 6188 { Bad_Opcode }, 6189 { Bad_Opcode }, 6190 { Bad_Opcode }, 6191 { Bad_Opcode }, 6192 { Bad_Opcode }, 6193 /* 10 */ 6194 { Bad_Opcode }, 6195 { Bad_Opcode }, 6196 { Bad_Opcode }, 6197 { Bad_Opcode }, 6198 { Bad_Opcode }, 6199 { Bad_Opcode }, 6200 { Bad_Opcode }, 6201 { Bad_Opcode }, 6202 /* 18 */ 6203 { Bad_Opcode }, 6204 { Bad_Opcode }, 6205 { Bad_Opcode }, 6206 { Bad_Opcode }, 6207 { Bad_Opcode }, 6208 { Bad_Opcode }, 6209 { Bad_Opcode }, 6210 { Bad_Opcode }, 6211 /* 20 */ 6212 { "ptest", { XX } }, 6213 { Bad_Opcode }, 6214 { Bad_Opcode }, 6215 { Bad_Opcode }, 6216 { Bad_Opcode }, 6217 { Bad_Opcode }, 6218 { Bad_Opcode }, 6219 { Bad_Opcode }, 6220 /* 28 */ 6221 { Bad_Opcode }, 6222 { Bad_Opcode }, 6223 { Bad_Opcode }, 6224 { Bad_Opcode }, 6225 { Bad_Opcode }, 6226 { Bad_Opcode }, 6227 { Bad_Opcode }, 6228 { Bad_Opcode }, 6229 /* 30 */ 6230 { Bad_Opcode }, 6231 { Bad_Opcode }, 6232 { Bad_Opcode }, 6233 { Bad_Opcode }, 6234 { Bad_Opcode }, 6235 { Bad_Opcode }, 6236 { Bad_Opcode }, 6237 { Bad_Opcode }, 6238 /* 38 */ 6239 { Bad_Opcode }, 6240 { Bad_Opcode }, 6241 { Bad_Opcode }, 6242 { Bad_Opcode }, 6243 { Bad_Opcode }, 6244 { Bad_Opcode }, 6245 { Bad_Opcode }, 6246 { Bad_Opcode }, 6247 /* 40 */ 6248 { Bad_Opcode }, 6249 { "phaddbw", { XM, EXq } }, 6250 { "phaddbd", { XM, EXq } }, 6251 { "phaddbq", { XM, EXq } }, 6252 { Bad_Opcode }, 6253 { Bad_Opcode }, 6254 { "phaddwd", { XM, EXq } }, 6255 { "phaddwq", { XM, EXq } }, 6256 /* 48 */ 6257 { Bad_Opcode }, 6258 { Bad_Opcode }, 6259 { Bad_Opcode }, 6260 { "phadddq", { XM, EXq } }, 6261 { Bad_Opcode }, 6262 { Bad_Opcode }, 6263 { Bad_Opcode }, 6264 { Bad_Opcode }, 6265 /* 50 */ 6266 { Bad_Opcode }, 6267 { "phaddubw", { XM, EXq } }, 6268 { "phaddubd", { XM, EXq } }, 6269 { "phaddubq", { XM, EXq } }, 6270 { Bad_Opcode }, 6271 { Bad_Opcode }, 6272 { "phadduwd", { XM, EXq } }, 6273 { "phadduwq", { XM, EXq } }, 6274 /* 58 */ 6275 { Bad_Opcode }, 6276 { Bad_Opcode }, 6277 { Bad_Opcode }, 6278 { "phaddudq", { XM, EXq } }, 6279 { Bad_Opcode }, 6280 { Bad_Opcode }, 6281 { Bad_Opcode }, 6282 { Bad_Opcode }, 6283 /* 60 */ 6284 { Bad_Opcode }, 6285 { "phsubbw", { XM, EXq } }, 6286 { "phsubbd", { XM, EXq } }, 6287 { "phsubbq", { XM, EXq } }, 6288 { Bad_Opcode }, 6289 { Bad_Opcode }, 6290 { Bad_Opcode }, 6291 { Bad_Opcode }, 6292 /* 68 */ 6293 { Bad_Opcode }, 6294 { Bad_Opcode }, 6295 { Bad_Opcode }, 6296 { Bad_Opcode }, 6297 { Bad_Opcode }, 6298 { Bad_Opcode }, 6299 { Bad_Opcode }, 6300 { Bad_Opcode }, 6301 /* 70 */ 6302 { Bad_Opcode }, 6303 { Bad_Opcode }, 6304 { Bad_Opcode }, 6305 { Bad_Opcode }, 6306 { Bad_Opcode }, 6307 { Bad_Opcode }, 6308 { Bad_Opcode }, 6309 { Bad_Opcode }, 6310 /* 78 */ 6311 { Bad_Opcode }, 6312 { Bad_Opcode }, 6313 { Bad_Opcode }, 6314 { Bad_Opcode }, 6315 { Bad_Opcode }, 6316 { Bad_Opcode }, 6317 { Bad_Opcode }, 6318 { Bad_Opcode }, 6319 /* 80 */ 6320 { Bad_Opcode }, 6321 { Bad_Opcode }, 6322 { Bad_Opcode }, 6323 { Bad_Opcode }, 6324 { Bad_Opcode }, 6325 { Bad_Opcode }, 6326 { Bad_Opcode }, 6327 { Bad_Opcode }, 6328 /* 88 */ 6329 { Bad_Opcode }, 6330 { Bad_Opcode }, 6331 { Bad_Opcode }, 6332 { Bad_Opcode }, 6333 { Bad_Opcode }, 6334 { Bad_Opcode }, 6335 { Bad_Opcode }, 6336 { Bad_Opcode }, 6337 /* 90 */ 6338 { Bad_Opcode }, 6339 { Bad_Opcode }, 6340 { Bad_Opcode }, 6341 { Bad_Opcode }, 6342 { Bad_Opcode }, 6343 { Bad_Opcode }, 6344 { Bad_Opcode }, 6345 { Bad_Opcode }, 6346 /* 98 */ 6347 { Bad_Opcode }, 6348 { Bad_Opcode }, 6349 { Bad_Opcode }, 6350 { Bad_Opcode }, 6351 { Bad_Opcode }, 6352 { Bad_Opcode }, 6353 { Bad_Opcode }, 6354 { Bad_Opcode }, 6355 /* a0 */ 6356 { Bad_Opcode }, 6357 { Bad_Opcode }, 6358 { Bad_Opcode }, 6359 { Bad_Opcode }, 6360 { Bad_Opcode }, 6361 { Bad_Opcode }, 6362 { Bad_Opcode }, 6363 { Bad_Opcode }, 6364 /* a8 */ 6365 { Bad_Opcode }, 6366 { Bad_Opcode }, 6367 { Bad_Opcode }, 6368 { Bad_Opcode }, 6369 { Bad_Opcode }, 6370 { Bad_Opcode }, 6371 { Bad_Opcode }, 6372 { Bad_Opcode }, 6373 /* b0 */ 6374 { Bad_Opcode }, 6375 { Bad_Opcode }, 6376 { Bad_Opcode }, 6377 { Bad_Opcode }, 6378 { Bad_Opcode }, 6379 { Bad_Opcode }, 6380 { Bad_Opcode }, 6381 { Bad_Opcode }, 6382 /* b8 */ 6383 { Bad_Opcode }, 6384 { Bad_Opcode }, 6385 { Bad_Opcode }, 6386 { Bad_Opcode }, 6387 { Bad_Opcode }, 6388 { Bad_Opcode }, 6389 { Bad_Opcode }, 6390 { Bad_Opcode }, 6391 /* c0 */ 6392 { Bad_Opcode }, 6393 { Bad_Opcode }, 6394 { Bad_Opcode }, 6395 { Bad_Opcode }, 6396 { Bad_Opcode }, 6397 { Bad_Opcode }, 6398 { Bad_Opcode }, 6399 { Bad_Opcode }, 6400 /* c8 */ 6401 { Bad_Opcode }, 6402 { Bad_Opcode }, 6403 { Bad_Opcode }, 6404 { Bad_Opcode }, 6405 { Bad_Opcode }, 6406 { Bad_Opcode }, 6407 { Bad_Opcode }, 6408 { Bad_Opcode }, 6409 /* d0 */ 6410 { Bad_Opcode }, 6411 { Bad_Opcode }, 6412 { Bad_Opcode }, 6413 { Bad_Opcode }, 6414 { Bad_Opcode }, 6415 { Bad_Opcode }, 6416 { Bad_Opcode }, 6417 { Bad_Opcode }, 6418 /* d8 */ 6419 { Bad_Opcode }, 6420 { Bad_Opcode }, 6421 { Bad_Opcode }, 6422 { Bad_Opcode }, 6423 { Bad_Opcode }, 6424 { Bad_Opcode }, 6425 { Bad_Opcode }, 6426 { Bad_Opcode }, 6427 /* e0 */ 6428 { Bad_Opcode }, 6429 { Bad_Opcode }, 6430 { Bad_Opcode }, 6431 { Bad_Opcode }, 6432 { Bad_Opcode }, 6433 { Bad_Opcode }, 6434 { Bad_Opcode }, 6435 { Bad_Opcode }, 6436 /* e8 */ 6437 { Bad_Opcode }, 6438 { Bad_Opcode }, 6439 { Bad_Opcode }, 6440 { Bad_Opcode }, 6441 { Bad_Opcode }, 6442 { Bad_Opcode }, 6443 { Bad_Opcode }, 6444 { Bad_Opcode }, 6445 /* f0 */ 6446 { Bad_Opcode }, 6447 { Bad_Opcode }, 6448 { Bad_Opcode }, 6449 { Bad_Opcode }, 6450 { Bad_Opcode }, 6451 { Bad_Opcode }, 6452 { Bad_Opcode }, 6453 { Bad_Opcode }, 6454 /* f8 */ 6455 { Bad_Opcode }, 6456 { Bad_Opcode }, 6457 { Bad_Opcode }, 6458 { Bad_Opcode }, 6459 { Bad_Opcode }, 6460 { Bad_Opcode }, 6461 { Bad_Opcode }, 6462 { Bad_Opcode }, 6463 }, 6464 }; 6465 6466 static const struct dis386 xop_table[][256] = { 6467 /* XOP_08 */ 6468 { 6469 /* 00 */ 6470 { Bad_Opcode }, 6471 { Bad_Opcode }, 6472 { Bad_Opcode }, 6473 { Bad_Opcode }, 6474 { Bad_Opcode }, 6475 { Bad_Opcode }, 6476 { Bad_Opcode }, 6477 { Bad_Opcode }, 6478 /* 08 */ 6479 { Bad_Opcode }, 6480 { Bad_Opcode }, 6481 { Bad_Opcode }, 6482 { Bad_Opcode }, 6483 { Bad_Opcode }, 6484 { Bad_Opcode }, 6485 { Bad_Opcode }, 6486 { Bad_Opcode }, 6487 /* 10 */ 6488 { "bextr", { Gv, Ev, Iq } }, 6489 { Bad_Opcode }, 6490 { Bad_Opcode }, 6491 { Bad_Opcode }, 6492 { Bad_Opcode }, 6493 { Bad_Opcode }, 6494 { Bad_Opcode }, 6495 { Bad_Opcode }, 6496 /* 18 */ 6497 { Bad_Opcode }, 6498 { Bad_Opcode }, 6499 { Bad_Opcode }, 6500 { Bad_Opcode }, 6501 { Bad_Opcode }, 6502 { Bad_Opcode }, 6503 { Bad_Opcode }, 6504 { Bad_Opcode }, 6505 /* 20 */ 6506 { Bad_Opcode }, 6507 { Bad_Opcode }, 6508 { Bad_Opcode }, 6509 { Bad_Opcode }, 6510 { Bad_Opcode }, 6511 { Bad_Opcode }, 6512 { Bad_Opcode }, 6513 { Bad_Opcode }, 6514 /* 28 */ 6515 { Bad_Opcode }, 6516 { Bad_Opcode }, 6517 { Bad_Opcode }, 6518 { Bad_Opcode }, 6519 { Bad_Opcode }, 6520 { Bad_Opcode }, 6521 { Bad_Opcode }, 6522 { Bad_Opcode }, 6523 /* 30 */ 6524 { Bad_Opcode }, 6525 { Bad_Opcode }, 6526 { Bad_Opcode }, 6527 { Bad_Opcode }, 6528 { Bad_Opcode }, 6529 { Bad_Opcode }, 6530 { Bad_Opcode }, 6531 { Bad_Opcode }, 6532 /* 38 */ 6533 { Bad_Opcode }, 6534 { Bad_Opcode }, 6535 { Bad_Opcode }, 6536 { Bad_Opcode }, 6537 { Bad_Opcode }, 6538 { Bad_Opcode }, 6539 { Bad_Opcode }, 6540 { Bad_Opcode }, 6541 /* 40 */ 6542 { Bad_Opcode }, 6543 { Bad_Opcode }, 6544 { Bad_Opcode }, 6545 { Bad_Opcode }, 6546 { Bad_Opcode }, 6547 { Bad_Opcode }, 6548 { Bad_Opcode }, 6549 { Bad_Opcode }, 6550 /* 48 */ 6551 { Bad_Opcode }, 6552 { Bad_Opcode }, 6553 { Bad_Opcode }, 6554 { Bad_Opcode }, 6555 { Bad_Opcode }, 6556 { Bad_Opcode }, 6557 { Bad_Opcode }, 6558 { Bad_Opcode }, 6559 /* 50 */ 6560 { Bad_Opcode }, 6561 { Bad_Opcode }, 6562 { Bad_Opcode }, 6563 { Bad_Opcode }, 6564 { Bad_Opcode }, 6565 { Bad_Opcode }, 6566 { Bad_Opcode }, 6567 { Bad_Opcode }, 6568 /* 58 */ 6569 { Bad_Opcode }, 6570 { Bad_Opcode }, 6571 { Bad_Opcode }, 6572 { Bad_Opcode }, 6573 { Bad_Opcode }, 6574 { Bad_Opcode }, 6575 { Bad_Opcode }, 6576 { Bad_Opcode }, 6577 /* 60 */ 6578 { Bad_Opcode }, 6579 { Bad_Opcode }, 6580 { Bad_Opcode }, 6581 { Bad_Opcode }, 6582 { Bad_Opcode }, 6583 { Bad_Opcode }, 6584 { Bad_Opcode }, 6585 { Bad_Opcode }, 6586 /* 68 */ 6587 { Bad_Opcode }, 6588 { Bad_Opcode }, 6589 { Bad_Opcode }, 6590 { Bad_Opcode }, 6591 { Bad_Opcode }, 6592 { Bad_Opcode }, 6593 { Bad_Opcode }, 6594 { Bad_Opcode }, 6595 /* 70 */ 6596 { Bad_Opcode }, 6597 { Bad_Opcode }, 6598 { Bad_Opcode }, 6599 { Bad_Opcode }, 6600 { Bad_Opcode }, 6601 { Bad_Opcode }, 6602 { Bad_Opcode }, 6603 { Bad_Opcode }, 6604 /* 78 */ 6605 { Bad_Opcode }, 6606 { Bad_Opcode }, 6607 { Bad_Opcode }, 6608 { Bad_Opcode }, 6609 { Bad_Opcode }, 6610 { Bad_Opcode }, 6611 { Bad_Opcode }, 6612 { Bad_Opcode }, 6613 /* 80 */ 6614 { Bad_Opcode }, 6615 { Bad_Opcode }, 6616 { Bad_Opcode }, 6617 { Bad_Opcode }, 6618 { Bad_Opcode }, 6619 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6620 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6621 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6622 /* 88 */ 6623 { Bad_Opcode }, 6624 { Bad_Opcode }, 6625 { Bad_Opcode }, 6626 { Bad_Opcode }, 6627 { Bad_Opcode }, 6628 { Bad_Opcode }, 6629 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6630 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6631 /* 90 */ 6632 { Bad_Opcode }, 6633 { Bad_Opcode }, 6634 { Bad_Opcode }, 6635 { Bad_Opcode }, 6636 { Bad_Opcode }, 6637 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6638 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6639 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6640 /* 98 */ 6641 { Bad_Opcode }, 6642 { Bad_Opcode }, 6643 { Bad_Opcode }, 6644 { Bad_Opcode }, 6645 { Bad_Opcode }, 6646 { Bad_Opcode }, 6647 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6648 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6649 /* a0 */ 6650 { Bad_Opcode }, 6651 { Bad_Opcode }, 6652 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6653 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6654 { Bad_Opcode }, 6655 { Bad_Opcode }, 6656 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6657 { Bad_Opcode }, 6658 /* a8 */ 6659 { Bad_Opcode }, 6660 { Bad_Opcode }, 6661 { Bad_Opcode }, 6662 { Bad_Opcode }, 6663 { Bad_Opcode }, 6664 { Bad_Opcode }, 6665 { Bad_Opcode }, 6666 { Bad_Opcode }, 6667 /* b0 */ 6668 { Bad_Opcode }, 6669 { Bad_Opcode }, 6670 { Bad_Opcode }, 6671 { Bad_Opcode }, 6672 { Bad_Opcode }, 6673 { Bad_Opcode }, 6674 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, 6675 { Bad_Opcode }, 6676 /* b8 */ 6677 { Bad_Opcode }, 6678 { Bad_Opcode }, 6679 { Bad_Opcode }, 6680 { Bad_Opcode }, 6681 { Bad_Opcode }, 6682 { Bad_Opcode }, 6683 { Bad_Opcode }, 6684 { Bad_Opcode }, 6685 /* c0 */ 6686 { "vprotb", { XM, Vex_2src_1, Ib } }, 6687 { "vprotw", { XM, Vex_2src_1, Ib } }, 6688 { "vprotd", { XM, Vex_2src_1, Ib } }, 6689 { "vprotq", { XM, Vex_2src_1, Ib } }, 6690 { Bad_Opcode }, 6691 { Bad_Opcode }, 6692 { Bad_Opcode }, 6693 { Bad_Opcode }, 6694 /* c8 */ 6695 { Bad_Opcode }, 6696 { Bad_Opcode }, 6697 { Bad_Opcode }, 6698 { Bad_Opcode }, 6699 { "vpcomb", { XM, Vex128, EXx, Ib } }, 6700 { "vpcomw", { XM, Vex128, EXx, Ib } }, 6701 { "vpcomd", { XM, Vex128, EXx, Ib } }, 6702 { "vpcomq", { XM, Vex128, EXx, Ib } }, 6703 /* d0 */ 6704 { Bad_Opcode }, 6705 { Bad_Opcode }, 6706 { Bad_Opcode }, 6707 { Bad_Opcode }, 6708 { Bad_Opcode }, 6709 { Bad_Opcode }, 6710 { Bad_Opcode }, 6711 { Bad_Opcode }, 6712 /* d8 */ 6713 { Bad_Opcode }, 6714 { Bad_Opcode }, 6715 { Bad_Opcode }, 6716 { Bad_Opcode }, 6717 { Bad_Opcode }, 6718 { Bad_Opcode }, 6719 { Bad_Opcode }, 6720 { Bad_Opcode }, 6721 /* e0 */ 6722 { Bad_Opcode }, 6723 { Bad_Opcode }, 6724 { Bad_Opcode }, 6725 { Bad_Opcode }, 6726 { Bad_Opcode }, 6727 { Bad_Opcode }, 6728 { Bad_Opcode }, 6729 { Bad_Opcode }, 6730 /* e8 */ 6731 { Bad_Opcode }, 6732 { Bad_Opcode }, 6733 { Bad_Opcode }, 6734 { Bad_Opcode }, 6735 { "vpcomub", { XM, Vex128, EXx, Ib } }, 6736 { "vpcomuw", { XM, Vex128, EXx, Ib } }, 6737 { "vpcomud", { XM, Vex128, EXx, Ib } }, 6738 { "vpcomuq", { XM, Vex128, EXx, Ib } }, 6739 /* f0 */ 6740 { Bad_Opcode }, 6741 { Bad_Opcode }, 6742 { Bad_Opcode }, 6743 { Bad_Opcode }, 6744 { Bad_Opcode }, 6745 { Bad_Opcode }, 6746 { Bad_Opcode }, 6747 { Bad_Opcode }, 6748 /* f8 */ 6749 { Bad_Opcode }, 6750 { Bad_Opcode }, 6751 { Bad_Opcode }, 6752 { Bad_Opcode }, 6753 { Bad_Opcode }, 6754 { Bad_Opcode }, 6755 { Bad_Opcode }, 6756 { Bad_Opcode }, 6757 }, 6758 /* XOP_09 */ 6759 { 6760 /* 00 */ 6761 { Bad_Opcode }, 6762 { REG_TABLE (REG_XOP_TBM_01) }, 6763 { REG_TABLE (REG_XOP_TBM_02) }, 6764 { Bad_Opcode }, 6765 { Bad_Opcode }, 6766 { Bad_Opcode }, 6767 { Bad_Opcode }, 6768 { Bad_Opcode }, 6769 /* 08 */ 6770 { Bad_Opcode }, 6771 { Bad_Opcode }, 6772 { Bad_Opcode }, 6773 { Bad_Opcode }, 6774 { Bad_Opcode }, 6775 { Bad_Opcode }, 6776 { Bad_Opcode }, 6777 { Bad_Opcode }, 6778 /* 10 */ 6779 { Bad_Opcode }, 6780 { Bad_Opcode }, 6781 { REG_TABLE (REG_XOP_LWPCB) }, 6782 { Bad_Opcode }, 6783 { Bad_Opcode }, 6784 { Bad_Opcode }, 6785 { Bad_Opcode }, 6786 { Bad_Opcode }, 6787 /* 18 */ 6788 { Bad_Opcode }, 6789 { Bad_Opcode }, 6790 { Bad_Opcode }, 6791 { Bad_Opcode }, 6792 { Bad_Opcode }, 6793 { Bad_Opcode }, 6794 { Bad_Opcode }, 6795 { Bad_Opcode }, 6796 /* 20 */ 6797 { Bad_Opcode }, 6798 { Bad_Opcode }, 6799 { Bad_Opcode }, 6800 { Bad_Opcode }, 6801 { Bad_Opcode }, 6802 { Bad_Opcode }, 6803 { Bad_Opcode }, 6804 { Bad_Opcode }, 6805 /* 28 */ 6806 { Bad_Opcode }, 6807 { Bad_Opcode }, 6808 { Bad_Opcode }, 6809 { Bad_Opcode }, 6810 { Bad_Opcode }, 6811 { Bad_Opcode }, 6812 { Bad_Opcode }, 6813 { Bad_Opcode }, 6814 /* 30 */ 6815 { Bad_Opcode }, 6816 { Bad_Opcode }, 6817 { Bad_Opcode }, 6818 { Bad_Opcode }, 6819 { Bad_Opcode }, 6820 { Bad_Opcode }, 6821 { Bad_Opcode }, 6822 { Bad_Opcode }, 6823 /* 38 */ 6824 { Bad_Opcode }, 6825 { Bad_Opcode }, 6826 { Bad_Opcode }, 6827 { Bad_Opcode }, 6828 { Bad_Opcode }, 6829 { Bad_Opcode }, 6830 { Bad_Opcode }, 6831 { Bad_Opcode }, 6832 /* 40 */ 6833 { Bad_Opcode }, 6834 { Bad_Opcode }, 6835 { Bad_Opcode }, 6836 { Bad_Opcode }, 6837 { Bad_Opcode }, 6838 { Bad_Opcode }, 6839 { Bad_Opcode }, 6840 { Bad_Opcode }, 6841 /* 48 */ 6842 { Bad_Opcode }, 6843 { Bad_Opcode }, 6844 { Bad_Opcode }, 6845 { Bad_Opcode }, 6846 { Bad_Opcode }, 6847 { Bad_Opcode }, 6848 { Bad_Opcode }, 6849 { Bad_Opcode }, 6850 /* 50 */ 6851 { Bad_Opcode }, 6852 { Bad_Opcode }, 6853 { Bad_Opcode }, 6854 { Bad_Opcode }, 6855 { Bad_Opcode }, 6856 { Bad_Opcode }, 6857 { Bad_Opcode }, 6858 { Bad_Opcode }, 6859 /* 58 */ 6860 { Bad_Opcode }, 6861 { Bad_Opcode }, 6862 { Bad_Opcode }, 6863 { Bad_Opcode }, 6864 { Bad_Opcode }, 6865 { Bad_Opcode }, 6866 { Bad_Opcode }, 6867 { Bad_Opcode }, 6868 /* 60 */ 6869 { Bad_Opcode }, 6870 { Bad_Opcode }, 6871 { Bad_Opcode }, 6872 { Bad_Opcode }, 6873 { Bad_Opcode }, 6874 { Bad_Opcode }, 6875 { Bad_Opcode }, 6876 { Bad_Opcode }, 6877 /* 68 */ 6878 { Bad_Opcode }, 6879 { Bad_Opcode }, 6880 { Bad_Opcode }, 6881 { Bad_Opcode }, 6882 { Bad_Opcode }, 6883 { Bad_Opcode }, 6884 { Bad_Opcode }, 6885 { Bad_Opcode }, 6886 /* 70 */ 6887 { Bad_Opcode }, 6888 { Bad_Opcode }, 6889 { Bad_Opcode }, 6890 { Bad_Opcode }, 6891 { Bad_Opcode }, 6892 { Bad_Opcode }, 6893 { Bad_Opcode }, 6894 { Bad_Opcode }, 6895 /* 78 */ 6896 { Bad_Opcode }, 6897 { Bad_Opcode }, 6898 { Bad_Opcode }, 6899 { Bad_Opcode }, 6900 { Bad_Opcode }, 6901 { Bad_Opcode }, 6902 { Bad_Opcode }, 6903 { Bad_Opcode }, 6904 /* 80 */ 6905 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, 6906 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, 6907 { "vfrczss", { XM, EXd } }, 6908 { "vfrczsd", { XM, EXq } }, 6909 { Bad_Opcode }, 6910 { Bad_Opcode }, 6911 { Bad_Opcode }, 6912 { Bad_Opcode }, 6913 /* 88 */ 6914 { Bad_Opcode }, 6915 { Bad_Opcode }, 6916 { Bad_Opcode }, 6917 { Bad_Opcode }, 6918 { Bad_Opcode }, 6919 { Bad_Opcode }, 6920 { Bad_Opcode }, 6921 { Bad_Opcode }, 6922 /* 90 */ 6923 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, 6924 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, 6925 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, 6926 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, 6927 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, 6928 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, 6929 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, 6930 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, 6931 /* 98 */ 6932 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, 6933 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, 6934 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, 6935 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, 6936 { Bad_Opcode }, 6937 { Bad_Opcode }, 6938 { Bad_Opcode }, 6939 { Bad_Opcode }, 6940 /* a0 */ 6941 { Bad_Opcode }, 6942 { Bad_Opcode }, 6943 { Bad_Opcode }, 6944 { Bad_Opcode }, 6945 { Bad_Opcode }, 6946 { Bad_Opcode }, 6947 { Bad_Opcode }, 6948 { Bad_Opcode }, 6949 /* a8 */ 6950 { Bad_Opcode }, 6951 { Bad_Opcode }, 6952 { Bad_Opcode }, 6953 { Bad_Opcode }, 6954 { Bad_Opcode }, 6955 { Bad_Opcode }, 6956 { Bad_Opcode }, 6957 { Bad_Opcode }, 6958 /* b0 */ 6959 { Bad_Opcode }, 6960 { Bad_Opcode }, 6961 { Bad_Opcode }, 6962 { Bad_Opcode }, 6963 { Bad_Opcode }, 6964 { Bad_Opcode }, 6965 { Bad_Opcode }, 6966 { Bad_Opcode }, 6967 /* b8 */ 6968 { Bad_Opcode }, 6969 { Bad_Opcode }, 6970 { Bad_Opcode }, 6971 { Bad_Opcode }, 6972 { Bad_Opcode }, 6973 { Bad_Opcode }, 6974 { Bad_Opcode }, 6975 { Bad_Opcode }, 6976 /* c0 */ 6977 { Bad_Opcode }, 6978 { "vphaddbw", { XM, EXxmm } }, 6979 { "vphaddbd", { XM, EXxmm } }, 6980 { "vphaddbq", { XM, EXxmm } }, 6981 { Bad_Opcode }, 6982 { Bad_Opcode }, 6983 { "vphaddwd", { XM, EXxmm } }, 6984 { "vphaddwq", { XM, EXxmm } }, 6985 /* c8 */ 6986 { Bad_Opcode }, 6987 { Bad_Opcode }, 6988 { Bad_Opcode }, 6989 { "vphadddq", { XM, EXxmm } }, 6990 { Bad_Opcode }, 6991 { Bad_Opcode }, 6992 { Bad_Opcode }, 6993 { Bad_Opcode }, 6994 /* d0 */ 6995 { Bad_Opcode }, 6996 { "vphaddubw", { XM, EXxmm } }, 6997 { "vphaddubd", { XM, EXxmm } }, 6998 { "vphaddubq", { XM, EXxmm } }, 6999 { Bad_Opcode }, 7000 { Bad_Opcode }, 7001 { "vphadduwd", { XM, EXxmm } }, 7002 { "vphadduwq", { XM, EXxmm } }, 7003 /* d8 */ 7004 { Bad_Opcode }, 7005 { Bad_Opcode }, 7006 { Bad_Opcode }, 7007 { "vphaddudq", { XM, EXxmm } }, 7008 { Bad_Opcode }, 7009 { Bad_Opcode }, 7010 { Bad_Opcode }, 7011 { Bad_Opcode }, 7012 /* e0 */ 7013 { Bad_Opcode }, 7014 { "vphsubbw", { XM, EXxmm } }, 7015 { "vphsubwd", { XM, EXxmm } }, 7016 { "vphsubdq", { XM, EXxmm } }, 7017 { Bad_Opcode }, 7018 { Bad_Opcode }, 7019 { Bad_Opcode }, 7020 { Bad_Opcode }, 7021 /* e8 */ 7022 { Bad_Opcode }, 7023 { Bad_Opcode }, 7024 { Bad_Opcode }, 7025 { Bad_Opcode }, 7026 { Bad_Opcode }, 7027 { Bad_Opcode }, 7028 { Bad_Opcode }, 7029 { Bad_Opcode }, 7030 /* f0 */ 7031 { Bad_Opcode }, 7032 { Bad_Opcode }, 7033 { Bad_Opcode }, 7034 { Bad_Opcode }, 7035 { Bad_Opcode }, 7036 { Bad_Opcode }, 7037 { Bad_Opcode }, 7038 { Bad_Opcode }, 7039 /* f8 */ 7040 { Bad_Opcode }, 7041 { Bad_Opcode }, 7042 { Bad_Opcode }, 7043 { Bad_Opcode }, 7044 { Bad_Opcode }, 7045 { Bad_Opcode }, 7046 { Bad_Opcode }, 7047 { Bad_Opcode }, 7048 }, 7049 /* XOP_0A */ 7050 { 7051 /* 00 */ 7052 { Bad_Opcode }, 7053 { Bad_Opcode }, 7054 { Bad_Opcode }, 7055 { Bad_Opcode }, 7056 { Bad_Opcode }, 7057 { Bad_Opcode }, 7058 { Bad_Opcode }, 7059 { Bad_Opcode }, 7060 /* 08 */ 7061 { Bad_Opcode }, 7062 { Bad_Opcode }, 7063 { Bad_Opcode }, 7064 { Bad_Opcode }, 7065 { Bad_Opcode }, 7066 { Bad_Opcode }, 7067 { Bad_Opcode }, 7068 { Bad_Opcode }, 7069 /* 10 */ 7070 { "bextr", { Gv, Ev, Iq } }, 7071 { Bad_Opcode }, 7072 { REG_TABLE (REG_XOP_LWP) }, 7073 { Bad_Opcode }, 7074 { Bad_Opcode }, 7075 { Bad_Opcode }, 7076 { Bad_Opcode }, 7077 { Bad_Opcode }, 7078 /* 18 */ 7079 { Bad_Opcode }, 7080 { Bad_Opcode }, 7081 { Bad_Opcode }, 7082 { Bad_Opcode }, 7083 { Bad_Opcode }, 7084 { Bad_Opcode }, 7085 { Bad_Opcode }, 7086 { Bad_Opcode }, 7087 /* 20 */ 7088 { Bad_Opcode }, 7089 { Bad_Opcode }, 7090 { Bad_Opcode }, 7091 { Bad_Opcode }, 7092 { Bad_Opcode }, 7093 { Bad_Opcode }, 7094 { Bad_Opcode }, 7095 { Bad_Opcode }, 7096 /* 28 */ 7097 { Bad_Opcode }, 7098 { Bad_Opcode }, 7099 { Bad_Opcode }, 7100 { Bad_Opcode }, 7101 { Bad_Opcode }, 7102 { Bad_Opcode }, 7103 { Bad_Opcode }, 7104 { Bad_Opcode }, 7105 /* 30 */ 7106 { Bad_Opcode }, 7107 { Bad_Opcode }, 7108 { Bad_Opcode }, 7109 { Bad_Opcode }, 7110 { Bad_Opcode }, 7111 { Bad_Opcode }, 7112 { Bad_Opcode }, 7113 { Bad_Opcode }, 7114 /* 38 */ 7115 { Bad_Opcode }, 7116 { Bad_Opcode }, 7117 { Bad_Opcode }, 7118 { Bad_Opcode }, 7119 { Bad_Opcode }, 7120 { Bad_Opcode }, 7121 { Bad_Opcode }, 7122 { Bad_Opcode }, 7123 /* 40 */ 7124 { Bad_Opcode }, 7125 { Bad_Opcode }, 7126 { Bad_Opcode }, 7127 { Bad_Opcode }, 7128 { Bad_Opcode }, 7129 { Bad_Opcode }, 7130 { Bad_Opcode }, 7131 { Bad_Opcode }, 7132 /* 48 */ 7133 { Bad_Opcode }, 7134 { Bad_Opcode }, 7135 { Bad_Opcode }, 7136 { Bad_Opcode }, 7137 { Bad_Opcode }, 7138 { Bad_Opcode }, 7139 { Bad_Opcode }, 7140 { Bad_Opcode }, 7141 /* 50 */ 7142 { Bad_Opcode }, 7143 { Bad_Opcode }, 7144 { Bad_Opcode }, 7145 { Bad_Opcode }, 7146 { Bad_Opcode }, 7147 { Bad_Opcode }, 7148 { Bad_Opcode }, 7149 { Bad_Opcode }, 7150 /* 58 */ 7151 { Bad_Opcode }, 7152 { Bad_Opcode }, 7153 { Bad_Opcode }, 7154 { Bad_Opcode }, 7155 { Bad_Opcode }, 7156 { Bad_Opcode }, 7157 { Bad_Opcode }, 7158 { Bad_Opcode }, 7159 /* 60 */ 7160 { Bad_Opcode }, 7161 { Bad_Opcode }, 7162 { Bad_Opcode }, 7163 { Bad_Opcode }, 7164 { Bad_Opcode }, 7165 { Bad_Opcode }, 7166 { Bad_Opcode }, 7167 { Bad_Opcode }, 7168 /* 68 */ 7169 { Bad_Opcode }, 7170 { Bad_Opcode }, 7171 { Bad_Opcode }, 7172 { Bad_Opcode }, 7173 { Bad_Opcode }, 7174 { Bad_Opcode }, 7175 { Bad_Opcode }, 7176 { Bad_Opcode }, 7177 /* 70 */ 7178 { Bad_Opcode }, 7179 { Bad_Opcode }, 7180 { Bad_Opcode }, 7181 { Bad_Opcode }, 7182 { Bad_Opcode }, 7183 { Bad_Opcode }, 7184 { Bad_Opcode }, 7185 { Bad_Opcode }, 7186 /* 78 */ 7187 { Bad_Opcode }, 7188 { Bad_Opcode }, 7189 { Bad_Opcode }, 7190 { Bad_Opcode }, 7191 { Bad_Opcode }, 7192 { Bad_Opcode }, 7193 { Bad_Opcode }, 7194 { Bad_Opcode }, 7195 /* 80 */ 7196 { Bad_Opcode }, 7197 { Bad_Opcode }, 7198 { Bad_Opcode }, 7199 { Bad_Opcode }, 7200 { Bad_Opcode }, 7201 { Bad_Opcode }, 7202 { Bad_Opcode }, 7203 { Bad_Opcode }, 7204 /* 88 */ 7205 { Bad_Opcode }, 7206 { Bad_Opcode }, 7207 { Bad_Opcode }, 7208 { Bad_Opcode }, 7209 { Bad_Opcode }, 7210 { Bad_Opcode }, 7211 { Bad_Opcode }, 7212 { Bad_Opcode }, 7213 /* 90 */ 7214 { Bad_Opcode }, 7215 { Bad_Opcode }, 7216 { Bad_Opcode }, 7217 { Bad_Opcode }, 7218 { Bad_Opcode }, 7219 { Bad_Opcode }, 7220 { Bad_Opcode }, 7221 { Bad_Opcode }, 7222 /* 98 */ 7223 { Bad_Opcode }, 7224 { Bad_Opcode }, 7225 { Bad_Opcode }, 7226 { Bad_Opcode }, 7227 { Bad_Opcode }, 7228 { Bad_Opcode }, 7229 { Bad_Opcode }, 7230 { Bad_Opcode }, 7231 /* a0 */ 7232 { Bad_Opcode }, 7233 { Bad_Opcode }, 7234 { Bad_Opcode }, 7235 { Bad_Opcode }, 7236 { Bad_Opcode }, 7237 { Bad_Opcode }, 7238 { Bad_Opcode }, 7239 { Bad_Opcode }, 7240 /* a8 */ 7241 { Bad_Opcode }, 7242 { Bad_Opcode }, 7243 { Bad_Opcode }, 7244 { Bad_Opcode }, 7245 { Bad_Opcode }, 7246 { Bad_Opcode }, 7247 { Bad_Opcode }, 7248 { Bad_Opcode }, 7249 /* b0 */ 7250 { Bad_Opcode }, 7251 { Bad_Opcode }, 7252 { Bad_Opcode }, 7253 { Bad_Opcode }, 7254 { Bad_Opcode }, 7255 { Bad_Opcode }, 7256 { Bad_Opcode }, 7257 { Bad_Opcode }, 7258 /* b8 */ 7259 { Bad_Opcode }, 7260 { Bad_Opcode }, 7261 { Bad_Opcode }, 7262 { Bad_Opcode }, 7263 { Bad_Opcode }, 7264 { Bad_Opcode }, 7265 { Bad_Opcode }, 7266 { Bad_Opcode }, 7267 /* c0 */ 7268 { Bad_Opcode }, 7269 { Bad_Opcode }, 7270 { Bad_Opcode }, 7271 { Bad_Opcode }, 7272 { Bad_Opcode }, 7273 { Bad_Opcode }, 7274 { Bad_Opcode }, 7275 { Bad_Opcode }, 7276 /* c8 */ 7277 { Bad_Opcode }, 7278 { Bad_Opcode }, 7279 { Bad_Opcode }, 7280 { Bad_Opcode }, 7281 { Bad_Opcode }, 7282 { Bad_Opcode }, 7283 { Bad_Opcode }, 7284 { Bad_Opcode }, 7285 /* d0 */ 7286 { Bad_Opcode }, 7287 { Bad_Opcode }, 7288 { Bad_Opcode }, 7289 { Bad_Opcode }, 7290 { Bad_Opcode }, 7291 { Bad_Opcode }, 7292 { Bad_Opcode }, 7293 { Bad_Opcode }, 7294 /* d8 */ 7295 { Bad_Opcode }, 7296 { Bad_Opcode }, 7297 { Bad_Opcode }, 7298 { Bad_Opcode }, 7299 { Bad_Opcode }, 7300 { Bad_Opcode }, 7301 { Bad_Opcode }, 7302 { Bad_Opcode }, 7303 /* e0 */ 7304 { Bad_Opcode }, 7305 { Bad_Opcode }, 7306 { Bad_Opcode }, 7307 { Bad_Opcode }, 7308 { Bad_Opcode }, 7309 { Bad_Opcode }, 7310 { Bad_Opcode }, 7311 { Bad_Opcode }, 7312 /* e8 */ 7313 { Bad_Opcode }, 7314 { Bad_Opcode }, 7315 { Bad_Opcode }, 7316 { Bad_Opcode }, 7317 { Bad_Opcode }, 7318 { Bad_Opcode }, 7319 { Bad_Opcode }, 7320 { Bad_Opcode }, 7321 /* f0 */ 7322 { Bad_Opcode }, 7323 { Bad_Opcode }, 7324 { Bad_Opcode }, 7325 { Bad_Opcode }, 7326 { Bad_Opcode }, 7327 { Bad_Opcode }, 7328 { Bad_Opcode }, 7329 { Bad_Opcode }, 7330 /* f8 */ 7331 { Bad_Opcode }, 7332 { Bad_Opcode }, 7333 { Bad_Opcode }, 7334 { Bad_Opcode }, 7335 { Bad_Opcode }, 7336 { Bad_Opcode }, 7337 { Bad_Opcode }, 7338 { Bad_Opcode }, 7339 }, 7340 }; 7341 7342 static const struct dis386 vex_table[][256] = { 7343 /* VEX_0F */ 7344 { 7345 /* 00 */ 7346 { Bad_Opcode }, 7347 { Bad_Opcode }, 7348 { Bad_Opcode }, 7349 { Bad_Opcode }, 7350 { Bad_Opcode }, 7351 { Bad_Opcode }, 7352 { Bad_Opcode }, 7353 { Bad_Opcode }, 7354 /* 08 */ 7355 { Bad_Opcode }, 7356 { Bad_Opcode }, 7357 { Bad_Opcode }, 7358 { Bad_Opcode }, 7359 { Bad_Opcode }, 7360 { Bad_Opcode }, 7361 { Bad_Opcode }, 7362 { Bad_Opcode }, 7363 /* 10 */ 7364 { PREFIX_TABLE (PREFIX_VEX_0F10) }, 7365 { PREFIX_TABLE (PREFIX_VEX_0F11) }, 7366 { PREFIX_TABLE (PREFIX_VEX_0F12) }, 7367 { MOD_TABLE (MOD_VEX_0F13) }, 7368 { VEX_W_TABLE (VEX_W_0F14) }, 7369 { VEX_W_TABLE (VEX_W_0F15) }, 7370 { PREFIX_TABLE (PREFIX_VEX_0F16) }, 7371 { MOD_TABLE (MOD_VEX_0F17) }, 7372 /* 18 */ 7373 { Bad_Opcode }, 7374 { Bad_Opcode }, 7375 { Bad_Opcode }, 7376 { Bad_Opcode }, 7377 { Bad_Opcode }, 7378 { Bad_Opcode }, 7379 { Bad_Opcode }, 7380 { Bad_Opcode }, 7381 /* 20 */ 7382 { Bad_Opcode }, 7383 { Bad_Opcode }, 7384 { Bad_Opcode }, 7385 { Bad_Opcode }, 7386 { Bad_Opcode }, 7387 { Bad_Opcode }, 7388 { Bad_Opcode }, 7389 { Bad_Opcode }, 7390 /* 28 */ 7391 { VEX_W_TABLE (VEX_W_0F28) }, 7392 { VEX_W_TABLE (VEX_W_0F29) }, 7393 { PREFIX_TABLE (PREFIX_VEX_0F2A) }, 7394 { MOD_TABLE (MOD_VEX_0F2B) }, 7395 { PREFIX_TABLE (PREFIX_VEX_0F2C) }, 7396 { PREFIX_TABLE (PREFIX_VEX_0F2D) }, 7397 { PREFIX_TABLE (PREFIX_VEX_0F2E) }, 7398 { PREFIX_TABLE (PREFIX_VEX_0F2F) }, 7399 /* 30 */ 7400 { Bad_Opcode }, 7401 { Bad_Opcode }, 7402 { Bad_Opcode }, 7403 { Bad_Opcode }, 7404 { Bad_Opcode }, 7405 { Bad_Opcode }, 7406 { Bad_Opcode }, 7407 { Bad_Opcode }, 7408 /* 38 */ 7409 { Bad_Opcode }, 7410 { Bad_Opcode }, 7411 { Bad_Opcode }, 7412 { Bad_Opcode }, 7413 { Bad_Opcode }, 7414 { Bad_Opcode }, 7415 { Bad_Opcode }, 7416 { Bad_Opcode }, 7417 /* 40 */ 7418 { Bad_Opcode }, 7419 { Bad_Opcode }, 7420 { Bad_Opcode }, 7421 { Bad_Opcode }, 7422 { Bad_Opcode }, 7423 { Bad_Opcode }, 7424 { Bad_Opcode }, 7425 { Bad_Opcode }, 7426 /* 48 */ 7427 { Bad_Opcode }, 7428 { Bad_Opcode }, 7429 { Bad_Opcode }, 7430 { Bad_Opcode }, 7431 { Bad_Opcode }, 7432 { Bad_Opcode }, 7433 { Bad_Opcode }, 7434 { Bad_Opcode }, 7435 /* 50 */ 7436 { MOD_TABLE (MOD_VEX_0F50) }, 7437 { PREFIX_TABLE (PREFIX_VEX_0F51) }, 7438 { PREFIX_TABLE (PREFIX_VEX_0F52) }, 7439 { PREFIX_TABLE (PREFIX_VEX_0F53) }, 7440 { "vandpX", { XM, Vex, EXx } }, 7441 { "vandnpX", { XM, Vex, EXx } }, 7442 { "vorpX", { XM, Vex, EXx } }, 7443 { "vxorpX", { XM, Vex, EXx } }, 7444 /* 58 */ 7445 { PREFIX_TABLE (PREFIX_VEX_0F58) }, 7446 { PREFIX_TABLE (PREFIX_VEX_0F59) }, 7447 { PREFIX_TABLE (PREFIX_VEX_0F5A) }, 7448 { PREFIX_TABLE (PREFIX_VEX_0F5B) }, 7449 { PREFIX_TABLE (PREFIX_VEX_0F5C) }, 7450 { PREFIX_TABLE (PREFIX_VEX_0F5D) }, 7451 { PREFIX_TABLE (PREFIX_VEX_0F5E) }, 7452 { PREFIX_TABLE (PREFIX_VEX_0F5F) }, 7453 /* 60 */ 7454 { PREFIX_TABLE (PREFIX_VEX_0F60) }, 7455 { PREFIX_TABLE (PREFIX_VEX_0F61) }, 7456 { PREFIX_TABLE (PREFIX_VEX_0F62) }, 7457 { PREFIX_TABLE (PREFIX_VEX_0F63) }, 7458 { PREFIX_TABLE (PREFIX_VEX_0F64) }, 7459 { PREFIX_TABLE (PREFIX_VEX_0F65) }, 7460 { PREFIX_TABLE (PREFIX_VEX_0F66) }, 7461 { PREFIX_TABLE (PREFIX_VEX_0F67) }, 7462 /* 68 */ 7463 { PREFIX_TABLE (PREFIX_VEX_0F68) }, 7464 { PREFIX_TABLE (PREFIX_VEX_0F69) }, 7465 { PREFIX_TABLE (PREFIX_VEX_0F6A) }, 7466 { PREFIX_TABLE (PREFIX_VEX_0F6B) }, 7467 { PREFIX_TABLE (PREFIX_VEX_0F6C) }, 7468 { PREFIX_TABLE (PREFIX_VEX_0F6D) }, 7469 { PREFIX_TABLE (PREFIX_VEX_0F6E) }, 7470 { PREFIX_TABLE (PREFIX_VEX_0F6F) }, 7471 /* 70 */ 7472 { PREFIX_TABLE (PREFIX_VEX_0F70) }, 7473 { REG_TABLE (REG_VEX_0F71) }, 7474 { REG_TABLE (REG_VEX_0F72) }, 7475 { REG_TABLE (REG_VEX_0F73) }, 7476 { PREFIX_TABLE (PREFIX_VEX_0F74) }, 7477 { PREFIX_TABLE (PREFIX_VEX_0F75) }, 7478 { PREFIX_TABLE (PREFIX_VEX_0F76) }, 7479 { PREFIX_TABLE (PREFIX_VEX_0F77) }, 7480 /* 78 */ 7481 { Bad_Opcode }, 7482 { Bad_Opcode }, 7483 { Bad_Opcode }, 7484 { Bad_Opcode }, 7485 { PREFIX_TABLE (PREFIX_VEX_0F7C) }, 7486 { PREFIX_TABLE (PREFIX_VEX_0F7D) }, 7487 { PREFIX_TABLE (PREFIX_VEX_0F7E) }, 7488 { PREFIX_TABLE (PREFIX_VEX_0F7F) }, 7489 /* 80 */ 7490 { Bad_Opcode }, 7491 { Bad_Opcode }, 7492 { Bad_Opcode }, 7493 { Bad_Opcode }, 7494 { Bad_Opcode }, 7495 { Bad_Opcode }, 7496 { Bad_Opcode }, 7497 { Bad_Opcode }, 7498 /* 88 */ 7499 { Bad_Opcode }, 7500 { Bad_Opcode }, 7501 { Bad_Opcode }, 7502 { Bad_Opcode }, 7503 { Bad_Opcode }, 7504 { Bad_Opcode }, 7505 { Bad_Opcode }, 7506 { Bad_Opcode }, 7507 /* 90 */ 7508 { Bad_Opcode }, 7509 { Bad_Opcode }, 7510 { Bad_Opcode }, 7511 { Bad_Opcode }, 7512 { Bad_Opcode }, 7513 { Bad_Opcode }, 7514 { Bad_Opcode }, 7515 { Bad_Opcode }, 7516 /* 98 */ 7517 { Bad_Opcode }, 7518 { Bad_Opcode }, 7519 { Bad_Opcode }, 7520 { Bad_Opcode }, 7521 { Bad_Opcode }, 7522 { Bad_Opcode }, 7523 { Bad_Opcode }, 7524 { Bad_Opcode }, 7525 /* a0 */ 7526 { Bad_Opcode }, 7527 { Bad_Opcode }, 7528 { Bad_Opcode }, 7529 { Bad_Opcode }, 7530 { Bad_Opcode }, 7531 { Bad_Opcode }, 7532 { Bad_Opcode }, 7533 { Bad_Opcode }, 7534 /* a8 */ 7535 { Bad_Opcode }, 7536 { Bad_Opcode }, 7537 { Bad_Opcode }, 7538 { Bad_Opcode }, 7539 { Bad_Opcode }, 7540 { Bad_Opcode }, 7541 { REG_TABLE (REG_VEX_0FAE) }, 7542 { Bad_Opcode }, 7543 /* b0 */ 7544 { Bad_Opcode }, 7545 { Bad_Opcode }, 7546 { Bad_Opcode }, 7547 { Bad_Opcode }, 7548 { Bad_Opcode }, 7549 { Bad_Opcode }, 7550 { Bad_Opcode }, 7551 { Bad_Opcode }, 7552 /* b8 */ 7553 { Bad_Opcode }, 7554 { Bad_Opcode }, 7555 { Bad_Opcode }, 7556 { Bad_Opcode }, 7557 { Bad_Opcode }, 7558 { Bad_Opcode }, 7559 { Bad_Opcode }, 7560 { Bad_Opcode }, 7561 /* c0 */ 7562 { Bad_Opcode }, 7563 { Bad_Opcode }, 7564 { PREFIX_TABLE (PREFIX_VEX_0FC2) }, 7565 { Bad_Opcode }, 7566 { PREFIX_TABLE (PREFIX_VEX_0FC4) }, 7567 { PREFIX_TABLE (PREFIX_VEX_0FC5) }, 7568 { "vshufpX", { XM, Vex, EXx, Ib } }, 7569 { Bad_Opcode }, 7570 /* c8 */ 7571 { Bad_Opcode }, 7572 { Bad_Opcode }, 7573 { Bad_Opcode }, 7574 { Bad_Opcode }, 7575 { Bad_Opcode }, 7576 { Bad_Opcode }, 7577 { Bad_Opcode }, 7578 { Bad_Opcode }, 7579 /* d0 */ 7580 { PREFIX_TABLE (PREFIX_VEX_0FD0) }, 7581 { PREFIX_TABLE (PREFIX_VEX_0FD1) }, 7582 { PREFIX_TABLE (PREFIX_VEX_0FD2) }, 7583 { PREFIX_TABLE (PREFIX_VEX_0FD3) }, 7584 { PREFIX_TABLE (PREFIX_VEX_0FD4) }, 7585 { PREFIX_TABLE (PREFIX_VEX_0FD5) }, 7586 { PREFIX_TABLE (PREFIX_VEX_0FD6) }, 7587 { PREFIX_TABLE (PREFIX_VEX_0FD7) }, 7588 /* d8 */ 7589 { PREFIX_TABLE (PREFIX_VEX_0FD8) }, 7590 { PREFIX_TABLE (PREFIX_VEX_0FD9) }, 7591 { PREFIX_TABLE (PREFIX_VEX_0FDA) }, 7592 { PREFIX_TABLE (PREFIX_VEX_0FDB) }, 7593 { PREFIX_TABLE (PREFIX_VEX_0FDC) }, 7594 { PREFIX_TABLE (PREFIX_VEX_0FDD) }, 7595 { PREFIX_TABLE (PREFIX_VEX_0FDE) }, 7596 { PREFIX_TABLE (PREFIX_VEX_0FDF) }, 7597 /* e0 */ 7598 { PREFIX_TABLE (PREFIX_VEX_0FE0) }, 7599 { PREFIX_TABLE (PREFIX_VEX_0FE1) }, 7600 { PREFIX_TABLE (PREFIX_VEX_0FE2) }, 7601 { PREFIX_TABLE (PREFIX_VEX_0FE3) }, 7602 { PREFIX_TABLE (PREFIX_VEX_0FE4) }, 7603 { PREFIX_TABLE (PREFIX_VEX_0FE5) }, 7604 { PREFIX_TABLE (PREFIX_VEX_0FE6) }, 7605 { PREFIX_TABLE (PREFIX_VEX_0FE7) }, 7606 /* e8 */ 7607 { PREFIX_TABLE (PREFIX_VEX_0FE8) }, 7608 { PREFIX_TABLE (PREFIX_VEX_0FE9) }, 7609 { PREFIX_TABLE (PREFIX_VEX_0FEA) }, 7610 { PREFIX_TABLE (PREFIX_VEX_0FEB) }, 7611 { PREFIX_TABLE (PREFIX_VEX_0FEC) }, 7612 { PREFIX_TABLE (PREFIX_VEX_0FED) }, 7613 { PREFIX_TABLE (PREFIX_VEX_0FEE) }, 7614 { PREFIX_TABLE (PREFIX_VEX_0FEF) }, 7615 /* f0 */ 7616 { PREFIX_TABLE (PREFIX_VEX_0FF0) }, 7617 { PREFIX_TABLE (PREFIX_VEX_0FF1) }, 7618 { PREFIX_TABLE (PREFIX_VEX_0FF2) }, 7619 { PREFIX_TABLE (PREFIX_VEX_0FF3) }, 7620 { PREFIX_TABLE (PREFIX_VEX_0FF4) }, 7621 { PREFIX_TABLE (PREFIX_VEX_0FF5) }, 7622 { PREFIX_TABLE (PREFIX_VEX_0FF6) }, 7623 { PREFIX_TABLE (PREFIX_VEX_0FF7) }, 7624 /* f8 */ 7625 { PREFIX_TABLE (PREFIX_VEX_0FF8) }, 7626 { PREFIX_TABLE (PREFIX_VEX_0FF9) }, 7627 { PREFIX_TABLE (PREFIX_VEX_0FFA) }, 7628 { PREFIX_TABLE (PREFIX_VEX_0FFB) }, 7629 { PREFIX_TABLE (PREFIX_VEX_0FFC) }, 7630 { PREFIX_TABLE (PREFIX_VEX_0FFD) }, 7631 { PREFIX_TABLE (PREFIX_VEX_0FFE) }, 7632 { Bad_Opcode }, 7633 }, 7634 /* VEX_0F38 */ 7635 { 7636 /* 00 */ 7637 { PREFIX_TABLE (PREFIX_VEX_0F3800) }, 7638 { PREFIX_TABLE (PREFIX_VEX_0F3801) }, 7639 { PREFIX_TABLE (PREFIX_VEX_0F3802) }, 7640 { PREFIX_TABLE (PREFIX_VEX_0F3803) }, 7641 { PREFIX_TABLE (PREFIX_VEX_0F3804) }, 7642 { PREFIX_TABLE (PREFIX_VEX_0F3805) }, 7643 { PREFIX_TABLE (PREFIX_VEX_0F3806) }, 7644 { PREFIX_TABLE (PREFIX_VEX_0F3807) }, 7645 /* 08 */ 7646 { PREFIX_TABLE (PREFIX_VEX_0F3808) }, 7647 { PREFIX_TABLE (PREFIX_VEX_0F3809) }, 7648 { PREFIX_TABLE (PREFIX_VEX_0F380A) }, 7649 { PREFIX_TABLE (PREFIX_VEX_0F380B) }, 7650 { PREFIX_TABLE (PREFIX_VEX_0F380C) }, 7651 { PREFIX_TABLE (PREFIX_VEX_0F380D) }, 7652 { PREFIX_TABLE (PREFIX_VEX_0F380E) }, 7653 { PREFIX_TABLE (PREFIX_VEX_0F380F) }, 7654 /* 10 */ 7655 { Bad_Opcode }, 7656 { Bad_Opcode }, 7657 { Bad_Opcode }, 7658 { PREFIX_TABLE (PREFIX_VEX_0F3813) }, 7659 { Bad_Opcode }, 7660 { Bad_Opcode }, 7661 { Bad_Opcode }, 7662 { PREFIX_TABLE (PREFIX_VEX_0F3817) }, 7663 /* 18 */ 7664 { PREFIX_TABLE (PREFIX_VEX_0F3818) }, 7665 { PREFIX_TABLE (PREFIX_VEX_0F3819) }, 7666 { PREFIX_TABLE (PREFIX_VEX_0F381A) }, 7667 { Bad_Opcode }, 7668 { PREFIX_TABLE (PREFIX_VEX_0F381C) }, 7669 { PREFIX_TABLE (PREFIX_VEX_0F381D) }, 7670 { PREFIX_TABLE (PREFIX_VEX_0F381E) }, 7671 { Bad_Opcode }, 7672 /* 20 */ 7673 { PREFIX_TABLE (PREFIX_VEX_0F3820) }, 7674 { PREFIX_TABLE (PREFIX_VEX_0F3821) }, 7675 { PREFIX_TABLE (PREFIX_VEX_0F3822) }, 7676 { PREFIX_TABLE (PREFIX_VEX_0F3823) }, 7677 { PREFIX_TABLE (PREFIX_VEX_0F3824) }, 7678 { PREFIX_TABLE (PREFIX_VEX_0F3825) }, 7679 { Bad_Opcode }, 7680 { Bad_Opcode }, 7681 /* 28 */ 7682 { PREFIX_TABLE (PREFIX_VEX_0F3828) }, 7683 { PREFIX_TABLE (PREFIX_VEX_0F3829) }, 7684 { PREFIX_TABLE (PREFIX_VEX_0F382A) }, 7685 { PREFIX_TABLE (PREFIX_VEX_0F382B) }, 7686 { PREFIX_TABLE (PREFIX_VEX_0F382C) }, 7687 { PREFIX_TABLE (PREFIX_VEX_0F382D) }, 7688 { PREFIX_TABLE (PREFIX_VEX_0F382E) }, 7689 { PREFIX_TABLE (PREFIX_VEX_0F382F) }, 7690 /* 30 */ 7691 { PREFIX_TABLE (PREFIX_VEX_0F3830) }, 7692 { PREFIX_TABLE (PREFIX_VEX_0F3831) }, 7693 { PREFIX_TABLE (PREFIX_VEX_0F3832) }, 7694 { PREFIX_TABLE (PREFIX_VEX_0F3833) }, 7695 { PREFIX_TABLE (PREFIX_VEX_0F3834) }, 7696 { PREFIX_TABLE (PREFIX_VEX_0F3835) }, 7697 { Bad_Opcode }, 7698 { PREFIX_TABLE (PREFIX_VEX_0F3837) }, 7699 /* 38 */ 7700 { PREFIX_TABLE (PREFIX_VEX_0F3838) }, 7701 { PREFIX_TABLE (PREFIX_VEX_0F3839) }, 7702 { PREFIX_TABLE (PREFIX_VEX_0F383A) }, 7703 { PREFIX_TABLE (PREFIX_VEX_0F383B) }, 7704 { PREFIX_TABLE (PREFIX_VEX_0F383C) }, 7705 { PREFIX_TABLE (PREFIX_VEX_0F383D) }, 7706 { PREFIX_TABLE (PREFIX_VEX_0F383E) }, 7707 { PREFIX_TABLE (PREFIX_VEX_0F383F) }, 7708 /* 40 */ 7709 { PREFIX_TABLE (PREFIX_VEX_0F3840) }, 7710 { PREFIX_TABLE (PREFIX_VEX_0F3841) }, 7711 { Bad_Opcode }, 7712 { Bad_Opcode }, 7713 { Bad_Opcode }, 7714 { Bad_Opcode }, 7715 { Bad_Opcode }, 7716 { Bad_Opcode }, 7717 /* 48 */ 7718 { Bad_Opcode }, 7719 { Bad_Opcode }, 7720 { Bad_Opcode }, 7721 { Bad_Opcode }, 7722 { Bad_Opcode }, 7723 { Bad_Opcode }, 7724 { Bad_Opcode }, 7725 { Bad_Opcode }, 7726 /* 50 */ 7727 { Bad_Opcode }, 7728 { Bad_Opcode }, 7729 { Bad_Opcode }, 7730 { Bad_Opcode }, 7731 { Bad_Opcode }, 7732 { Bad_Opcode }, 7733 { Bad_Opcode }, 7734 { Bad_Opcode }, 7735 /* 58 */ 7736 { Bad_Opcode }, 7737 { Bad_Opcode }, 7738 { Bad_Opcode }, 7739 { Bad_Opcode }, 7740 { Bad_Opcode }, 7741 { Bad_Opcode }, 7742 { Bad_Opcode }, 7743 { Bad_Opcode }, 7744 /* 60 */ 7745 { Bad_Opcode }, 7746 { Bad_Opcode }, 7747 { Bad_Opcode }, 7748 { Bad_Opcode }, 7749 { Bad_Opcode }, 7750 { Bad_Opcode }, 7751 { Bad_Opcode }, 7752 { Bad_Opcode }, 7753 /* 68 */ 7754 { Bad_Opcode }, 7755 { Bad_Opcode }, 7756 { Bad_Opcode }, 7757 { Bad_Opcode }, 7758 { Bad_Opcode }, 7759 { Bad_Opcode }, 7760 { Bad_Opcode }, 7761 { Bad_Opcode }, 7762 /* 70 */ 7763 { Bad_Opcode }, 7764 { Bad_Opcode }, 7765 { Bad_Opcode }, 7766 { Bad_Opcode }, 7767 { Bad_Opcode }, 7768 { Bad_Opcode }, 7769 { Bad_Opcode }, 7770 { Bad_Opcode }, 7771 /* 78 */ 7772 { Bad_Opcode }, 7773 { Bad_Opcode }, 7774 { Bad_Opcode }, 7775 { Bad_Opcode }, 7776 { Bad_Opcode }, 7777 { Bad_Opcode }, 7778 { Bad_Opcode }, 7779 { Bad_Opcode }, 7780 /* 80 */ 7781 { Bad_Opcode }, 7782 { Bad_Opcode }, 7783 { Bad_Opcode }, 7784 { Bad_Opcode }, 7785 { Bad_Opcode }, 7786 { Bad_Opcode }, 7787 { Bad_Opcode }, 7788 { Bad_Opcode }, 7789 /* 88 */ 7790 { Bad_Opcode }, 7791 { Bad_Opcode }, 7792 { Bad_Opcode }, 7793 { Bad_Opcode }, 7794 { Bad_Opcode }, 7795 { Bad_Opcode }, 7796 { Bad_Opcode }, 7797 { Bad_Opcode }, 7798 /* 90 */ 7799 { Bad_Opcode }, 7800 { Bad_Opcode }, 7801 { Bad_Opcode }, 7802 { Bad_Opcode }, 7803 { Bad_Opcode }, 7804 { Bad_Opcode }, 7805 { PREFIX_TABLE (PREFIX_VEX_0F3896) }, 7806 { PREFIX_TABLE (PREFIX_VEX_0F3897) }, 7807 /* 98 */ 7808 { PREFIX_TABLE (PREFIX_VEX_0F3898) }, 7809 { PREFIX_TABLE (PREFIX_VEX_0F3899) }, 7810 { PREFIX_TABLE (PREFIX_VEX_0F389A) }, 7811 { PREFIX_TABLE (PREFIX_VEX_0F389B) }, 7812 { PREFIX_TABLE (PREFIX_VEX_0F389C) }, 7813 { PREFIX_TABLE (PREFIX_VEX_0F389D) }, 7814 { PREFIX_TABLE (PREFIX_VEX_0F389E) }, 7815 { PREFIX_TABLE (PREFIX_VEX_0F389F) }, 7816 /* a0 */ 7817 { Bad_Opcode }, 7818 { Bad_Opcode }, 7819 { Bad_Opcode }, 7820 { Bad_Opcode }, 7821 { Bad_Opcode }, 7822 { Bad_Opcode }, 7823 { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, 7824 { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, 7825 /* a8 */ 7826 { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, 7827 { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, 7828 { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, 7829 { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, 7830 { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, 7831 { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, 7832 { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, 7833 { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, 7834 /* b0 */ 7835 { Bad_Opcode }, 7836 { Bad_Opcode }, 7837 { Bad_Opcode }, 7838 { Bad_Opcode }, 7839 { Bad_Opcode }, 7840 { Bad_Opcode }, 7841 { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, 7842 { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, 7843 /* b8 */ 7844 { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, 7845 { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, 7846 { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, 7847 { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, 7848 { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, 7849 { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, 7850 { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, 7851 { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, 7852 /* c0 */ 7853 { Bad_Opcode }, 7854 { Bad_Opcode }, 7855 { Bad_Opcode }, 7856 { Bad_Opcode }, 7857 { Bad_Opcode }, 7858 { Bad_Opcode }, 7859 { Bad_Opcode }, 7860 { Bad_Opcode }, 7861 /* c8 */ 7862 { Bad_Opcode }, 7863 { Bad_Opcode }, 7864 { Bad_Opcode }, 7865 { Bad_Opcode }, 7866 { Bad_Opcode }, 7867 { Bad_Opcode }, 7868 { Bad_Opcode }, 7869 { Bad_Opcode }, 7870 /* d0 */ 7871 { Bad_Opcode }, 7872 { Bad_Opcode }, 7873 { Bad_Opcode }, 7874 { Bad_Opcode }, 7875 { Bad_Opcode }, 7876 { Bad_Opcode }, 7877 { Bad_Opcode }, 7878 { Bad_Opcode }, 7879 /* d8 */ 7880 { Bad_Opcode }, 7881 { Bad_Opcode }, 7882 { Bad_Opcode }, 7883 { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, 7884 { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, 7885 { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, 7886 { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, 7887 { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, 7888 /* e0 */ 7889 { Bad_Opcode }, 7890 { Bad_Opcode }, 7891 { Bad_Opcode }, 7892 { Bad_Opcode }, 7893 { Bad_Opcode }, 7894 { Bad_Opcode }, 7895 { Bad_Opcode }, 7896 { Bad_Opcode }, 7897 /* e8 */ 7898 { Bad_Opcode }, 7899 { Bad_Opcode }, 7900 { Bad_Opcode }, 7901 { Bad_Opcode }, 7902 { Bad_Opcode }, 7903 { Bad_Opcode }, 7904 { Bad_Opcode }, 7905 { Bad_Opcode }, 7906 /* f0 */ 7907 { Bad_Opcode }, 7908 { Bad_Opcode }, 7909 { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, 7910 { REG_TABLE (REG_VEX_0F38F3) }, 7911 { Bad_Opcode }, 7912 { Bad_Opcode }, 7913 { Bad_Opcode }, 7914 { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, 7915 /* f8 */ 7916 { Bad_Opcode }, 7917 { Bad_Opcode }, 7918 { Bad_Opcode }, 7919 { Bad_Opcode }, 7920 { Bad_Opcode }, 7921 { Bad_Opcode }, 7922 { Bad_Opcode }, 7923 { Bad_Opcode }, 7924 }, 7925 /* VEX_0F3A */ 7926 { 7927 /* 00 */ 7928 { Bad_Opcode }, 7929 { Bad_Opcode }, 7930 { Bad_Opcode }, 7931 { Bad_Opcode }, 7932 { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, 7933 { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, 7934 { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, 7935 { Bad_Opcode }, 7936 /* 08 */ 7937 { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, 7938 { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, 7939 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, 7940 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, 7941 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, 7942 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, 7943 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, 7944 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, 7945 /* 10 */ 7946 { Bad_Opcode }, 7947 { Bad_Opcode }, 7948 { Bad_Opcode }, 7949 { Bad_Opcode }, 7950 { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, 7951 { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, 7952 { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, 7953 { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, 7954 /* 18 */ 7955 { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, 7956 { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, 7957 { Bad_Opcode }, 7958 { Bad_Opcode }, 7959 { Bad_Opcode }, 7960 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, 7961 { Bad_Opcode }, 7962 { Bad_Opcode }, 7963 /* 20 */ 7964 { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, 7965 { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, 7966 { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, 7967 { Bad_Opcode }, 7968 { Bad_Opcode }, 7969 { Bad_Opcode }, 7970 { Bad_Opcode }, 7971 { Bad_Opcode }, 7972 /* 28 */ 7973 { Bad_Opcode }, 7974 { Bad_Opcode }, 7975 { Bad_Opcode }, 7976 { Bad_Opcode }, 7977 { Bad_Opcode }, 7978 { Bad_Opcode }, 7979 { Bad_Opcode }, 7980 { Bad_Opcode }, 7981 /* 30 */ 7982 { Bad_Opcode }, 7983 { Bad_Opcode }, 7984 { Bad_Opcode }, 7985 { Bad_Opcode }, 7986 { Bad_Opcode }, 7987 { Bad_Opcode }, 7988 { Bad_Opcode }, 7989 { Bad_Opcode }, 7990 /* 38 */ 7991 { Bad_Opcode }, 7992 { Bad_Opcode }, 7993 { Bad_Opcode }, 7994 { Bad_Opcode }, 7995 { Bad_Opcode }, 7996 { Bad_Opcode }, 7997 { Bad_Opcode }, 7998 { Bad_Opcode }, 7999 /* 40 */ 8000 { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, 8001 { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, 8002 { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, 8003 { Bad_Opcode }, 8004 { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, 8005 { Bad_Opcode }, 8006 { Bad_Opcode }, 8007 { Bad_Opcode }, 8008 /* 48 */ 8009 { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, 8010 { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, 8011 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, 8012 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, 8013 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, 8014 { Bad_Opcode }, 8015 { Bad_Opcode }, 8016 { Bad_Opcode }, 8017 /* 50 */ 8018 { Bad_Opcode }, 8019 { Bad_Opcode }, 8020 { Bad_Opcode }, 8021 { Bad_Opcode }, 8022 { Bad_Opcode }, 8023 { Bad_Opcode }, 8024 { Bad_Opcode }, 8025 { Bad_Opcode }, 8026 /* 58 */ 8027 { Bad_Opcode }, 8028 { Bad_Opcode }, 8029 { Bad_Opcode }, 8030 { Bad_Opcode }, 8031 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, 8032 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, 8033 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, 8034 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, 8035 /* 60 */ 8036 { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, 8037 { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, 8038 { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, 8039 { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, 8040 { Bad_Opcode }, 8041 { Bad_Opcode }, 8042 { Bad_Opcode }, 8043 { Bad_Opcode }, 8044 /* 68 */ 8045 { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, 8046 { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, 8047 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, 8048 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, 8049 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, 8050 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, 8051 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, 8052 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, 8053 /* 70 */ 8054 { Bad_Opcode }, 8055 { Bad_Opcode }, 8056 { Bad_Opcode }, 8057 { Bad_Opcode }, 8058 { Bad_Opcode }, 8059 { Bad_Opcode }, 8060 { Bad_Opcode }, 8061 { Bad_Opcode }, 8062 /* 78 */ 8063 { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, 8064 { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, 8065 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, 8066 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, 8067 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, 8068 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, 8069 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, 8070 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, 8071 /* 80 */ 8072 { Bad_Opcode }, 8073 { Bad_Opcode }, 8074 { Bad_Opcode }, 8075 { Bad_Opcode }, 8076 { Bad_Opcode }, 8077 { Bad_Opcode }, 8078 { Bad_Opcode }, 8079 { Bad_Opcode }, 8080 /* 88 */ 8081 { Bad_Opcode }, 8082 { Bad_Opcode }, 8083 { Bad_Opcode }, 8084 { Bad_Opcode }, 8085 { Bad_Opcode }, 8086 { Bad_Opcode }, 8087 { Bad_Opcode }, 8088 { Bad_Opcode }, 8089 /* 90 */ 8090 { Bad_Opcode }, 8091 { Bad_Opcode }, 8092 { Bad_Opcode }, 8093 { Bad_Opcode }, 8094 { Bad_Opcode }, 8095 { Bad_Opcode }, 8096 { Bad_Opcode }, 8097 { Bad_Opcode }, 8098 /* 98 */ 8099 { Bad_Opcode }, 8100 { Bad_Opcode }, 8101 { Bad_Opcode }, 8102 { Bad_Opcode }, 8103 { Bad_Opcode }, 8104 { Bad_Opcode }, 8105 { Bad_Opcode }, 8106 { Bad_Opcode }, 8107 /* a0 */ 8108 { Bad_Opcode }, 8109 { Bad_Opcode }, 8110 { Bad_Opcode }, 8111 { Bad_Opcode }, 8112 { Bad_Opcode }, 8113 { Bad_Opcode }, 8114 { Bad_Opcode }, 8115 { Bad_Opcode }, 8116 /* a8 */ 8117 { Bad_Opcode }, 8118 { Bad_Opcode }, 8119 { Bad_Opcode }, 8120 { Bad_Opcode }, 8121 { Bad_Opcode }, 8122 { Bad_Opcode }, 8123 { Bad_Opcode }, 8124 { Bad_Opcode }, 8125 /* b0 */ 8126 { Bad_Opcode }, 8127 { Bad_Opcode }, 8128 { Bad_Opcode }, 8129 { Bad_Opcode }, 8130 { Bad_Opcode }, 8131 { Bad_Opcode }, 8132 { Bad_Opcode }, 8133 { Bad_Opcode }, 8134 /* b8 */ 8135 { Bad_Opcode }, 8136 { Bad_Opcode }, 8137 { Bad_Opcode }, 8138 { Bad_Opcode }, 8139 { Bad_Opcode }, 8140 { Bad_Opcode }, 8141 { Bad_Opcode }, 8142 { Bad_Opcode }, 8143 /* c0 */ 8144 { Bad_Opcode }, 8145 { Bad_Opcode }, 8146 { Bad_Opcode }, 8147 { Bad_Opcode }, 8148 { Bad_Opcode }, 8149 { Bad_Opcode }, 8150 { Bad_Opcode }, 8151 { Bad_Opcode }, 8152 /* c8 */ 8153 { Bad_Opcode }, 8154 { Bad_Opcode }, 8155 { Bad_Opcode }, 8156 { Bad_Opcode }, 8157 { Bad_Opcode }, 8158 { Bad_Opcode }, 8159 { Bad_Opcode }, 8160 { Bad_Opcode }, 8161 /* d0 */ 8162 { Bad_Opcode }, 8163 { Bad_Opcode }, 8164 { Bad_Opcode }, 8165 { Bad_Opcode }, 8166 { Bad_Opcode }, 8167 { Bad_Opcode }, 8168 { Bad_Opcode }, 8169 { Bad_Opcode }, 8170 /* d8 */ 8171 { Bad_Opcode }, 8172 { Bad_Opcode }, 8173 { Bad_Opcode }, 8174 { Bad_Opcode }, 8175 { Bad_Opcode }, 8176 { Bad_Opcode }, 8177 { Bad_Opcode }, 8178 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, 8179 /* e0 */ 8180 { Bad_Opcode }, 8181 { Bad_Opcode }, 8182 { Bad_Opcode }, 8183 { Bad_Opcode }, 8184 { Bad_Opcode }, 8185 { Bad_Opcode }, 8186 { Bad_Opcode }, 8187 { Bad_Opcode }, 8188 /* e8 */ 8189 { Bad_Opcode }, 8190 { Bad_Opcode }, 8191 { Bad_Opcode }, 8192 { Bad_Opcode }, 8193 { Bad_Opcode }, 8194 { Bad_Opcode }, 8195 { Bad_Opcode }, 8196 { Bad_Opcode }, 8197 /* f0 */ 8198 { Bad_Opcode }, 8199 { Bad_Opcode }, 8200 { Bad_Opcode }, 8201 { Bad_Opcode }, 8202 { Bad_Opcode }, 8203 { Bad_Opcode }, 8204 { Bad_Opcode }, 8205 { Bad_Opcode }, 8206 /* f8 */ 8207 { Bad_Opcode }, 8208 { Bad_Opcode }, 8209 { Bad_Opcode }, 8210 { Bad_Opcode }, 8211 { Bad_Opcode }, 8212 { Bad_Opcode }, 8213 { Bad_Opcode }, 8214 { Bad_Opcode }, 8215 }, 8216 }; 8217 8218 static const struct dis386 vex_len_table[][2] = { 8219 /* VEX_LEN_0F10_P_1 */ 8220 { 8221 { VEX_W_TABLE (VEX_W_0F10_P_1) }, 8222 { VEX_W_TABLE (VEX_W_0F10_P_1) }, 8223 }, 8224 8225 /* VEX_LEN_0F10_P_3 */ 8226 { 8227 { VEX_W_TABLE (VEX_W_0F10_P_3) }, 8228 { VEX_W_TABLE (VEX_W_0F10_P_3) }, 8229 }, 8230 8231 /* VEX_LEN_0F11_P_1 */ 8232 { 8233 { VEX_W_TABLE (VEX_W_0F11_P_1) }, 8234 { VEX_W_TABLE (VEX_W_0F11_P_1) }, 8235 }, 8236 8237 /* VEX_LEN_0F11_P_3 */ 8238 { 8239 { VEX_W_TABLE (VEX_W_0F11_P_3) }, 8240 { VEX_W_TABLE (VEX_W_0F11_P_3) }, 8241 }, 8242 8243 /* VEX_LEN_0F12_P_0_M_0 */ 8244 { 8245 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, 8246 }, 8247 8248 /* VEX_LEN_0F12_P_0_M_1 */ 8249 { 8250 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, 8251 }, 8252 8253 /* VEX_LEN_0F12_P_2 */ 8254 { 8255 { VEX_W_TABLE (VEX_W_0F12_P_2) }, 8256 }, 8257 8258 /* VEX_LEN_0F13_M_0 */ 8259 { 8260 { VEX_W_TABLE (VEX_W_0F13_M_0) }, 8261 }, 8262 8263 /* VEX_LEN_0F16_P_0_M_0 */ 8264 { 8265 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, 8266 }, 8267 8268 /* VEX_LEN_0F16_P_0_M_1 */ 8269 { 8270 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, 8271 }, 8272 8273 /* VEX_LEN_0F16_P_2 */ 8274 { 8275 { VEX_W_TABLE (VEX_W_0F16_P_2) }, 8276 }, 8277 8278 /* VEX_LEN_0F17_M_0 */ 8279 { 8280 { VEX_W_TABLE (VEX_W_0F17_M_0) }, 8281 }, 8282 8283 /* VEX_LEN_0F2A_P_1 */ 8284 { 8285 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, 8286 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, 8287 }, 8288 8289 /* VEX_LEN_0F2A_P_3 */ 8290 { 8291 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, 8292 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, 8293 }, 8294 8295 /* VEX_LEN_0F2C_P_1 */ 8296 { 8297 { "vcvttss2siY", { Gv, EXdScalar } }, 8298 { "vcvttss2siY", { Gv, EXdScalar } }, 8299 }, 8300 8301 /* VEX_LEN_0F2C_P_3 */ 8302 { 8303 { "vcvttsd2siY", { Gv, EXqScalar } }, 8304 { "vcvttsd2siY", { Gv, EXqScalar } }, 8305 }, 8306 8307 /* VEX_LEN_0F2D_P_1 */ 8308 { 8309 { "vcvtss2siY", { Gv, EXdScalar } }, 8310 { "vcvtss2siY", { Gv, EXdScalar } }, 8311 }, 8312 8313 /* VEX_LEN_0F2D_P_3 */ 8314 { 8315 { "vcvtsd2siY", { Gv, EXqScalar } }, 8316 { "vcvtsd2siY", { Gv, EXqScalar } }, 8317 }, 8318 8319 /* VEX_LEN_0F2E_P_0 */ 8320 { 8321 { VEX_W_TABLE (VEX_W_0F2E_P_0) }, 8322 { VEX_W_TABLE (VEX_W_0F2E_P_0) }, 8323 }, 8324 8325 /* VEX_LEN_0F2E_P_2 */ 8326 { 8327 { VEX_W_TABLE (VEX_W_0F2E_P_2) }, 8328 { VEX_W_TABLE (VEX_W_0F2E_P_2) }, 8329 }, 8330 8331 /* VEX_LEN_0F2F_P_0 */ 8332 { 8333 { VEX_W_TABLE (VEX_W_0F2F_P_0) }, 8334 { VEX_W_TABLE (VEX_W_0F2F_P_0) }, 8335 }, 8336 8337 /* VEX_LEN_0F2F_P_2 */ 8338 { 8339 { VEX_W_TABLE (VEX_W_0F2F_P_2) }, 8340 { VEX_W_TABLE (VEX_W_0F2F_P_2) }, 8341 }, 8342 8343 /* VEX_LEN_0F51_P_1 */ 8344 { 8345 { VEX_W_TABLE (VEX_W_0F51_P_1) }, 8346 { VEX_W_TABLE (VEX_W_0F51_P_1) }, 8347 }, 8348 8349 /* VEX_LEN_0F51_P_3 */ 8350 { 8351 { VEX_W_TABLE (VEX_W_0F51_P_3) }, 8352 { VEX_W_TABLE (VEX_W_0F51_P_3) }, 8353 }, 8354 8355 /* VEX_LEN_0F52_P_1 */ 8356 { 8357 { VEX_W_TABLE (VEX_W_0F52_P_1) }, 8358 { VEX_W_TABLE (VEX_W_0F52_P_1) }, 8359 }, 8360 8361 /* VEX_LEN_0F53_P_1 */ 8362 { 8363 { VEX_W_TABLE (VEX_W_0F53_P_1) }, 8364 { VEX_W_TABLE (VEX_W_0F53_P_1) }, 8365 }, 8366 8367 /* VEX_LEN_0F58_P_1 */ 8368 { 8369 { VEX_W_TABLE (VEX_W_0F58_P_1) }, 8370 { VEX_W_TABLE (VEX_W_0F58_P_1) }, 8371 }, 8372 8373 /* VEX_LEN_0F58_P_3 */ 8374 { 8375 { VEX_W_TABLE (VEX_W_0F58_P_3) }, 8376 { VEX_W_TABLE (VEX_W_0F58_P_3) }, 8377 }, 8378 8379 /* VEX_LEN_0F59_P_1 */ 8380 { 8381 { VEX_W_TABLE (VEX_W_0F59_P_1) }, 8382 { VEX_W_TABLE (VEX_W_0F59_P_1) }, 8383 }, 8384 8385 /* VEX_LEN_0F59_P_3 */ 8386 { 8387 { VEX_W_TABLE (VEX_W_0F59_P_3) }, 8388 { VEX_W_TABLE (VEX_W_0F59_P_3) }, 8389 }, 8390 8391 /* VEX_LEN_0F5A_P_1 */ 8392 { 8393 { VEX_W_TABLE (VEX_W_0F5A_P_1) }, 8394 { VEX_W_TABLE (VEX_W_0F5A_P_1) }, 8395 }, 8396 8397 /* VEX_LEN_0F5A_P_3 */ 8398 { 8399 { VEX_W_TABLE (VEX_W_0F5A_P_3) }, 8400 { VEX_W_TABLE (VEX_W_0F5A_P_3) }, 8401 }, 8402 8403 /* VEX_LEN_0F5C_P_1 */ 8404 { 8405 { VEX_W_TABLE (VEX_W_0F5C_P_1) }, 8406 { VEX_W_TABLE (VEX_W_0F5C_P_1) }, 8407 }, 8408 8409 /* VEX_LEN_0F5C_P_3 */ 8410 { 8411 { VEX_W_TABLE (VEX_W_0F5C_P_3) }, 8412 { VEX_W_TABLE (VEX_W_0F5C_P_3) }, 8413 }, 8414 8415 /* VEX_LEN_0F5D_P_1 */ 8416 { 8417 { VEX_W_TABLE (VEX_W_0F5D_P_1) }, 8418 { VEX_W_TABLE (VEX_W_0F5D_P_1) }, 8419 }, 8420 8421 /* VEX_LEN_0F5D_P_3 */ 8422 { 8423 { VEX_W_TABLE (VEX_W_0F5D_P_3) }, 8424 { VEX_W_TABLE (VEX_W_0F5D_P_3) }, 8425 }, 8426 8427 /* VEX_LEN_0F5E_P_1 */ 8428 { 8429 { VEX_W_TABLE (VEX_W_0F5E_P_1) }, 8430 { VEX_W_TABLE (VEX_W_0F5E_P_1) }, 8431 }, 8432 8433 /* VEX_LEN_0F5E_P_3 */ 8434 { 8435 { VEX_W_TABLE (VEX_W_0F5E_P_3) }, 8436 { VEX_W_TABLE (VEX_W_0F5E_P_3) }, 8437 }, 8438 8439 /* VEX_LEN_0F5F_P_1 */ 8440 { 8441 { VEX_W_TABLE (VEX_W_0F5F_P_1) }, 8442 { VEX_W_TABLE (VEX_W_0F5F_P_1) }, 8443 }, 8444 8445 /* VEX_LEN_0F5F_P_3 */ 8446 { 8447 { VEX_W_TABLE (VEX_W_0F5F_P_3) }, 8448 { VEX_W_TABLE (VEX_W_0F5F_P_3) }, 8449 }, 8450 8451 /* VEX_LEN_0F60_P_2 */ 8452 { 8453 { VEX_W_TABLE (VEX_W_0F60_P_2) }, 8454 }, 8455 8456 /* VEX_LEN_0F61_P_2 */ 8457 { 8458 { VEX_W_TABLE (VEX_W_0F61_P_2) }, 8459 }, 8460 8461 /* VEX_LEN_0F62_P_2 */ 8462 { 8463 { VEX_W_TABLE (VEX_W_0F62_P_2) }, 8464 }, 8465 8466 /* VEX_LEN_0F63_P_2 */ 8467 { 8468 { VEX_W_TABLE (VEX_W_0F63_P_2) }, 8469 }, 8470 8471 /* VEX_LEN_0F64_P_2 */ 8472 { 8473 { VEX_W_TABLE (VEX_W_0F64_P_2) }, 8474 }, 8475 8476 /* VEX_LEN_0F65_P_2 */ 8477 { 8478 { VEX_W_TABLE (VEX_W_0F65_P_2) }, 8479 }, 8480 8481 /* VEX_LEN_0F66_P_2 */ 8482 { 8483 { VEX_W_TABLE (VEX_W_0F66_P_2) }, 8484 }, 8485 8486 /* VEX_LEN_0F67_P_2 */ 8487 { 8488 { VEX_W_TABLE (VEX_W_0F67_P_2) }, 8489 }, 8490 8491 /* VEX_LEN_0F68_P_2 */ 8492 { 8493 { VEX_W_TABLE (VEX_W_0F68_P_2) }, 8494 }, 8495 8496 /* VEX_LEN_0F69_P_2 */ 8497 { 8498 { VEX_W_TABLE (VEX_W_0F69_P_2) }, 8499 }, 8500 8501 /* VEX_LEN_0F6A_P_2 */ 8502 { 8503 { VEX_W_TABLE (VEX_W_0F6A_P_2) }, 8504 }, 8505 8506 /* VEX_LEN_0F6B_P_2 */ 8507 { 8508 { VEX_W_TABLE (VEX_W_0F6B_P_2) }, 8509 }, 8510 8511 /* VEX_LEN_0F6C_P_2 */ 8512 { 8513 { VEX_W_TABLE (VEX_W_0F6C_P_2) }, 8514 }, 8515 8516 /* VEX_LEN_0F6D_P_2 */ 8517 { 8518 { VEX_W_TABLE (VEX_W_0F6D_P_2) }, 8519 }, 8520 8521 /* VEX_LEN_0F6E_P_2 */ 8522 { 8523 { "vmovK", { XMScalar, Edq } }, 8524 { "vmovK", { XMScalar, Edq } }, 8525 }, 8526 8527 /* VEX_LEN_0F70_P_1 */ 8528 { 8529 { VEX_W_TABLE (VEX_W_0F70_P_1) }, 8530 }, 8531 8532 /* VEX_LEN_0F70_P_2 */ 8533 { 8534 { VEX_W_TABLE (VEX_W_0F70_P_2) }, 8535 }, 8536 8537 /* VEX_LEN_0F70_P_3 */ 8538 { 8539 { VEX_W_TABLE (VEX_W_0F70_P_3) }, 8540 }, 8541 8542 /* VEX_LEN_0F71_R_2_P_2 */ 8543 { 8544 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, 8545 }, 8546 8547 /* VEX_LEN_0F71_R_4_P_2 */ 8548 { 8549 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, 8550 }, 8551 8552 /* VEX_LEN_0F71_R_6_P_2 */ 8553 { 8554 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, 8555 }, 8556 8557 /* VEX_LEN_0F72_R_2_P_2 */ 8558 { 8559 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, 8560 }, 8561 8562 /* VEX_LEN_0F72_R_4_P_2 */ 8563 { 8564 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, 8565 }, 8566 8567 /* VEX_LEN_0F72_R_6_P_2 */ 8568 { 8569 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, 8570 }, 8571 8572 /* VEX_LEN_0F73_R_2_P_2 */ 8573 { 8574 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, 8575 }, 8576 8577 /* VEX_LEN_0F73_R_3_P_2 */ 8578 { 8579 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, 8580 }, 8581 8582 /* VEX_LEN_0F73_R_6_P_2 */ 8583 { 8584 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, 8585 }, 8586 8587 /* VEX_LEN_0F73_R_7_P_2 */ 8588 { 8589 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, 8590 }, 8591 8592 /* VEX_LEN_0F74_P_2 */ 8593 { 8594 { VEX_W_TABLE (VEX_W_0F74_P_2) }, 8595 }, 8596 8597 /* VEX_LEN_0F75_P_2 */ 8598 { 8599 { VEX_W_TABLE (VEX_W_0F75_P_2) }, 8600 }, 8601 8602 /* VEX_LEN_0F76_P_2 */ 8603 { 8604 { VEX_W_TABLE (VEX_W_0F76_P_2) }, 8605 }, 8606 8607 /* VEX_LEN_0F7E_P_1 */ 8608 { 8609 { VEX_W_TABLE (VEX_W_0F7E_P_1) }, 8610 { VEX_W_TABLE (VEX_W_0F7E_P_1) }, 8611 }, 8612 8613 /* VEX_LEN_0F7E_P_2 */ 8614 { 8615 { "vmovK", { Edq, XMScalar } }, 8616 { "vmovK", { Edq, XMScalar } }, 8617 }, 8618 8619 /* VEX_LEN_0FAE_R_2_M_0 */ 8620 { 8621 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, 8622 }, 8623 8624 /* VEX_LEN_0FAE_R_3_M_0 */ 8625 { 8626 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, 8627 }, 8628 8629 /* VEX_LEN_0FC2_P_1 */ 8630 { 8631 { VEX_W_TABLE (VEX_W_0FC2_P_1) }, 8632 { VEX_W_TABLE (VEX_W_0FC2_P_1) }, 8633 }, 8634 8635 /* VEX_LEN_0FC2_P_3 */ 8636 { 8637 { VEX_W_TABLE (VEX_W_0FC2_P_3) }, 8638 { VEX_W_TABLE (VEX_W_0FC2_P_3) }, 8639 }, 8640 8641 /* VEX_LEN_0FC4_P_2 */ 8642 { 8643 { VEX_W_TABLE (VEX_W_0FC4_P_2) }, 8644 }, 8645 8646 /* VEX_LEN_0FC5_P_2 */ 8647 { 8648 { VEX_W_TABLE (VEX_W_0FC5_P_2) }, 8649 }, 8650 8651 /* VEX_LEN_0FD1_P_2 */ 8652 { 8653 { VEX_W_TABLE (VEX_W_0FD1_P_2) }, 8654 }, 8655 8656 /* VEX_LEN_0FD2_P_2 */ 8657 { 8658 { VEX_W_TABLE (VEX_W_0FD2_P_2) }, 8659 }, 8660 8661 /* VEX_LEN_0FD3_P_2 */ 8662 { 8663 { VEX_W_TABLE (VEX_W_0FD3_P_2) }, 8664 }, 8665 8666 /* VEX_LEN_0FD4_P_2 */ 8667 { 8668 { VEX_W_TABLE (VEX_W_0FD4_P_2) }, 8669 }, 8670 8671 /* VEX_LEN_0FD5_P_2 */ 8672 { 8673 { VEX_W_TABLE (VEX_W_0FD5_P_2) }, 8674 }, 8675 8676 /* VEX_LEN_0FD6_P_2 */ 8677 { 8678 { VEX_W_TABLE (VEX_W_0FD6_P_2) }, 8679 { VEX_W_TABLE (VEX_W_0FD6_P_2) }, 8680 }, 8681 8682 /* VEX_LEN_0FD7_P_2_M_1 */ 8683 { 8684 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, 8685 }, 8686 8687 /* VEX_LEN_0FD8_P_2 */ 8688 { 8689 { VEX_W_TABLE (VEX_W_0FD8_P_2) }, 8690 }, 8691 8692 /* VEX_LEN_0FD9_P_2 */ 8693 { 8694 { VEX_W_TABLE (VEX_W_0FD9_P_2) }, 8695 }, 8696 8697 /* VEX_LEN_0FDA_P_2 */ 8698 { 8699 { VEX_W_TABLE (VEX_W_0FDA_P_2) }, 8700 }, 8701 8702 /* VEX_LEN_0FDB_P_2 */ 8703 { 8704 { VEX_W_TABLE (VEX_W_0FDB_P_2) }, 8705 }, 8706 8707 /* VEX_LEN_0FDC_P_2 */ 8708 { 8709 { VEX_W_TABLE (VEX_W_0FDC_P_2) }, 8710 }, 8711 8712 /* VEX_LEN_0FDD_P_2 */ 8713 { 8714 { VEX_W_TABLE (VEX_W_0FDD_P_2) }, 8715 }, 8716 8717 /* VEX_LEN_0FDE_P_2 */ 8718 { 8719 { VEX_W_TABLE (VEX_W_0FDE_P_2) }, 8720 }, 8721 8722 /* VEX_LEN_0FDF_P_2 */ 8723 { 8724 { VEX_W_TABLE (VEX_W_0FDF_P_2) }, 8725 }, 8726 8727 /* VEX_LEN_0FE0_P_2 */ 8728 { 8729 { VEX_W_TABLE (VEX_W_0FE0_P_2) }, 8730 }, 8731 8732 /* VEX_LEN_0FE1_P_2 */ 8733 { 8734 { VEX_W_TABLE (VEX_W_0FE1_P_2) }, 8735 }, 8736 8737 /* VEX_LEN_0FE2_P_2 */ 8738 { 8739 { VEX_W_TABLE (VEX_W_0FE2_P_2) }, 8740 }, 8741 8742 /* VEX_LEN_0FE3_P_2 */ 8743 { 8744 { VEX_W_TABLE (VEX_W_0FE3_P_2) }, 8745 }, 8746 8747 /* VEX_LEN_0FE4_P_2 */ 8748 { 8749 { VEX_W_TABLE (VEX_W_0FE4_P_2) }, 8750 }, 8751 8752 /* VEX_LEN_0FE5_P_2 */ 8753 { 8754 { VEX_W_TABLE (VEX_W_0FE5_P_2) }, 8755 }, 8756 8757 /* VEX_LEN_0FE8_P_2 */ 8758 { 8759 { VEX_W_TABLE (VEX_W_0FE8_P_2) }, 8760 }, 8761 8762 /* VEX_LEN_0FE9_P_2 */ 8763 { 8764 { VEX_W_TABLE (VEX_W_0FE9_P_2) }, 8765 }, 8766 8767 /* VEX_LEN_0FEA_P_2 */ 8768 { 8769 { VEX_W_TABLE (VEX_W_0FEA_P_2) }, 8770 }, 8771 8772 /* VEX_LEN_0FEB_P_2 */ 8773 { 8774 { VEX_W_TABLE (VEX_W_0FEB_P_2) }, 8775 }, 8776 8777 /* VEX_LEN_0FEC_P_2 */ 8778 { 8779 { VEX_W_TABLE (VEX_W_0FEC_P_2) }, 8780 }, 8781 8782 /* VEX_LEN_0FED_P_2 */ 8783 { 8784 { VEX_W_TABLE (VEX_W_0FED_P_2) }, 8785 }, 8786 8787 /* VEX_LEN_0FEE_P_2 */ 8788 { 8789 { VEX_W_TABLE (VEX_W_0FEE_P_2) }, 8790 }, 8791 8792 /* VEX_LEN_0FEF_P_2 */ 8793 { 8794 { VEX_W_TABLE (VEX_W_0FEF_P_2) }, 8795 }, 8796 8797 /* VEX_LEN_0FF1_P_2 */ 8798 { 8799 { VEX_W_TABLE (VEX_W_0FF1_P_2) }, 8800 }, 8801 8802 /* VEX_LEN_0FF2_P_2 */ 8803 { 8804 { VEX_W_TABLE (VEX_W_0FF2_P_2) }, 8805 }, 8806 8807 /* VEX_LEN_0FF3_P_2 */ 8808 { 8809 { VEX_W_TABLE (VEX_W_0FF3_P_2) }, 8810 }, 8811 8812 /* VEX_LEN_0FF4_P_2 */ 8813 { 8814 { VEX_W_TABLE (VEX_W_0FF4_P_2) }, 8815 }, 8816 8817 /* VEX_LEN_0FF5_P_2 */ 8818 { 8819 { VEX_W_TABLE (VEX_W_0FF5_P_2) }, 8820 }, 8821 8822 /* VEX_LEN_0FF6_P_2 */ 8823 { 8824 { VEX_W_TABLE (VEX_W_0FF6_P_2) }, 8825 }, 8826 8827 /* VEX_LEN_0FF7_P_2 */ 8828 { 8829 { VEX_W_TABLE (VEX_W_0FF7_P_2) }, 8830 }, 8831 8832 /* VEX_LEN_0FF8_P_2 */ 8833 { 8834 { VEX_W_TABLE (VEX_W_0FF8_P_2) }, 8835 }, 8836 8837 /* VEX_LEN_0FF9_P_2 */ 8838 { 8839 { VEX_W_TABLE (VEX_W_0FF9_P_2) }, 8840 }, 8841 8842 /* VEX_LEN_0FFA_P_2 */ 8843 { 8844 { VEX_W_TABLE (VEX_W_0FFA_P_2) }, 8845 }, 8846 8847 /* VEX_LEN_0FFB_P_2 */ 8848 { 8849 { VEX_W_TABLE (VEX_W_0FFB_P_2) }, 8850 }, 8851 8852 /* VEX_LEN_0FFC_P_2 */ 8853 { 8854 { VEX_W_TABLE (VEX_W_0FFC_P_2) }, 8855 }, 8856 8857 /* VEX_LEN_0FFD_P_2 */ 8858 { 8859 { VEX_W_TABLE (VEX_W_0FFD_P_2) }, 8860 }, 8861 8862 /* VEX_LEN_0FFE_P_2 */ 8863 { 8864 { VEX_W_TABLE (VEX_W_0FFE_P_2) }, 8865 }, 8866 8867 /* VEX_LEN_0F3800_P_2 */ 8868 { 8869 { VEX_W_TABLE (VEX_W_0F3800_P_2) }, 8870 }, 8871 8872 /* VEX_LEN_0F3801_P_2 */ 8873 { 8874 { VEX_W_TABLE (VEX_W_0F3801_P_2) }, 8875 }, 8876 8877 /* VEX_LEN_0F3802_P_2 */ 8878 { 8879 { VEX_W_TABLE (VEX_W_0F3802_P_2) }, 8880 }, 8881 8882 /* VEX_LEN_0F3803_P_2 */ 8883 { 8884 { VEX_W_TABLE (VEX_W_0F3803_P_2) }, 8885 }, 8886 8887 /* VEX_LEN_0F3804_P_2 */ 8888 { 8889 { VEX_W_TABLE (VEX_W_0F3804_P_2) }, 8890 }, 8891 8892 /* VEX_LEN_0F3805_P_2 */ 8893 { 8894 { VEX_W_TABLE (VEX_W_0F3805_P_2) }, 8895 }, 8896 8897 /* VEX_LEN_0F3806_P_2 */ 8898 { 8899 { VEX_W_TABLE (VEX_W_0F3806_P_2) }, 8900 }, 8901 8902 /* VEX_LEN_0F3807_P_2 */ 8903 { 8904 { VEX_W_TABLE (VEX_W_0F3807_P_2) }, 8905 }, 8906 8907 /* VEX_LEN_0F3808_P_2 */ 8908 { 8909 { VEX_W_TABLE (VEX_W_0F3808_P_2) }, 8910 }, 8911 8912 /* VEX_LEN_0F3809_P_2 */ 8913 { 8914 { VEX_W_TABLE (VEX_W_0F3809_P_2) }, 8915 }, 8916 8917 /* VEX_LEN_0F380A_P_2 */ 8918 { 8919 { VEX_W_TABLE (VEX_W_0F380A_P_2) }, 8920 }, 8921 8922 /* VEX_LEN_0F380B_P_2 */ 8923 { 8924 { VEX_W_TABLE (VEX_W_0F380B_P_2) }, 8925 }, 8926 8927 /* VEX_LEN_0F3819_P_2_M_0 */ 8928 { 8929 { Bad_Opcode }, 8930 { VEX_W_TABLE (VEX_W_0F3819_P_2_M_0) }, 8931 }, 8932 8933 /* VEX_LEN_0F381A_P_2_M_0 */ 8934 { 8935 { Bad_Opcode }, 8936 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, 8937 }, 8938 8939 /* VEX_LEN_0F381C_P_2 */ 8940 { 8941 { VEX_W_TABLE (VEX_W_0F381C_P_2) }, 8942 }, 8943 8944 /* VEX_LEN_0F381D_P_2 */ 8945 { 8946 { VEX_W_TABLE (VEX_W_0F381D_P_2) }, 8947 }, 8948 8949 /* VEX_LEN_0F381E_P_2 */ 8950 { 8951 { VEX_W_TABLE (VEX_W_0F381E_P_2) }, 8952 }, 8953 8954 /* VEX_LEN_0F3820_P_2 */ 8955 { 8956 { VEX_W_TABLE (VEX_W_0F3820_P_2) }, 8957 }, 8958 8959 /* VEX_LEN_0F3821_P_2 */ 8960 { 8961 { VEX_W_TABLE (VEX_W_0F3821_P_2) }, 8962 }, 8963 8964 /* VEX_LEN_0F3822_P_2 */ 8965 { 8966 { VEX_W_TABLE (VEX_W_0F3822_P_2) }, 8967 }, 8968 8969 /* VEX_LEN_0F3823_P_2 */ 8970 { 8971 { VEX_W_TABLE (VEX_W_0F3823_P_2) }, 8972 }, 8973 8974 /* VEX_LEN_0F3824_P_2 */ 8975 { 8976 { VEX_W_TABLE (VEX_W_0F3824_P_2) }, 8977 }, 8978 8979 /* VEX_LEN_0F3825_P_2 */ 8980 { 8981 { VEX_W_TABLE (VEX_W_0F3825_P_2) }, 8982 }, 8983 8984 /* VEX_LEN_0F3828_P_2 */ 8985 { 8986 { VEX_W_TABLE (VEX_W_0F3828_P_2) }, 8987 }, 8988 8989 /* VEX_LEN_0F3829_P_2 */ 8990 { 8991 { VEX_W_TABLE (VEX_W_0F3829_P_2) }, 8992 }, 8993 8994 /* VEX_LEN_0F382A_P_2_M_0 */ 8995 { 8996 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, 8997 }, 8998 8999 /* VEX_LEN_0F382B_P_2 */ 9000 { 9001 { VEX_W_TABLE (VEX_W_0F382B_P_2) }, 9002 }, 9003 9004 /* VEX_LEN_0F3830_P_2 */ 9005 { 9006 { VEX_W_TABLE (VEX_W_0F3830_P_2) }, 9007 }, 9008 9009 /* VEX_LEN_0F3831_P_2 */ 9010 { 9011 { VEX_W_TABLE (VEX_W_0F3831_P_2) }, 9012 }, 9013 9014 /* VEX_LEN_0F3832_P_2 */ 9015 { 9016 { VEX_W_TABLE (VEX_W_0F3832_P_2) }, 9017 }, 9018 9019 /* VEX_LEN_0F3833_P_2 */ 9020 { 9021 { VEX_W_TABLE (VEX_W_0F3833_P_2) }, 9022 }, 9023 9024 /* VEX_LEN_0F3834_P_2 */ 9025 { 9026 { VEX_W_TABLE (VEX_W_0F3834_P_2) }, 9027 }, 9028 9029 /* VEX_LEN_0F3835_P_2 */ 9030 { 9031 { VEX_W_TABLE (VEX_W_0F3835_P_2) }, 9032 }, 9033 9034 /* VEX_LEN_0F3837_P_2 */ 9035 { 9036 { VEX_W_TABLE (VEX_W_0F3837_P_2) }, 9037 }, 9038 9039 /* VEX_LEN_0F3838_P_2 */ 9040 { 9041 { VEX_W_TABLE (VEX_W_0F3838_P_2) }, 9042 }, 9043 9044 /* VEX_LEN_0F3839_P_2 */ 9045 { 9046 { VEX_W_TABLE (VEX_W_0F3839_P_2) }, 9047 }, 9048 9049 /* VEX_LEN_0F383A_P_2 */ 9050 { 9051 { VEX_W_TABLE (VEX_W_0F383A_P_2) }, 9052 }, 9053 9054 /* VEX_LEN_0F383B_P_2 */ 9055 { 9056 { VEX_W_TABLE (VEX_W_0F383B_P_2) }, 9057 }, 9058 9059 /* VEX_LEN_0F383C_P_2 */ 9060 { 9061 { VEX_W_TABLE (VEX_W_0F383C_P_2) }, 9062 }, 9063 9064 /* VEX_LEN_0F383D_P_2 */ 9065 { 9066 { VEX_W_TABLE (VEX_W_0F383D_P_2) }, 9067 }, 9068 9069 /* VEX_LEN_0F383E_P_2 */ 9070 { 9071 { VEX_W_TABLE (VEX_W_0F383E_P_2) }, 9072 }, 9073 9074 /* VEX_LEN_0F383F_P_2 */ 9075 { 9076 { VEX_W_TABLE (VEX_W_0F383F_P_2) }, 9077 }, 9078 9079 /* VEX_LEN_0F3840_P_2 */ 9080 { 9081 { VEX_W_TABLE (VEX_W_0F3840_P_2) }, 9082 }, 9083 9084 /* VEX_LEN_0F3841_P_2 */ 9085 { 9086 { VEX_W_TABLE (VEX_W_0F3841_P_2) }, 9087 }, 9088 9089 /* VEX_LEN_0F38DB_P_2 */ 9090 { 9091 { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, 9092 }, 9093 9094 /* VEX_LEN_0F38DC_P_2 */ 9095 { 9096 { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, 9097 }, 9098 9099 /* VEX_LEN_0F38DD_P_2 */ 9100 { 9101 { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, 9102 }, 9103 9104 /* VEX_LEN_0F38DE_P_2 */ 9105 { 9106 { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, 9107 }, 9108 9109 /* VEX_LEN_0F38DF_P_2 */ 9110 { 9111 { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, 9112 }, 9113 9114 /* VEX_LEN_0F38F2_P_0 */ 9115 { 9116 { "andnS", { Gdq, VexGdq, Edq } }, 9117 }, 9118 9119 /* VEX_LEN_0F38F3_R_1_P_0 */ 9120 { 9121 { "blsrS", { VexGdq, Edq } }, 9122 }, 9123 9124 /* VEX_LEN_0F38F3_R_2_P_0 */ 9125 { 9126 { "blsmskS", { VexGdq, Edq } }, 9127 }, 9128 9129 /* VEX_LEN_0F38F3_R_3_P_0 */ 9130 { 9131 { "blsiS", { VexGdq, Edq } }, 9132 }, 9133 9134 /* VEX_LEN_0F38F7_P_0 */ 9135 { 9136 { "bextrS", { Gdq, Edq, VexGdq } }, 9137 }, 9138 9139 /* VEX_LEN_0F3A06_P_2 */ 9140 { 9141 { Bad_Opcode }, 9142 { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, 9143 }, 9144 9145 /* VEX_LEN_0F3A0A_P_2 */ 9146 { 9147 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, 9148 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, 9149 }, 9150 9151 /* VEX_LEN_0F3A0B_P_2 */ 9152 { 9153 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, 9154 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, 9155 }, 9156 9157 /* VEX_LEN_0F3A0E_P_2 */ 9158 { 9159 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, 9160 }, 9161 9162 /* VEX_LEN_0F3A0F_P_2 */ 9163 { 9164 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, 9165 }, 9166 9167 /* VEX_LEN_0F3A14_P_2 */ 9168 { 9169 { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, 9170 }, 9171 9172 /* VEX_LEN_0F3A15_P_2 */ 9173 { 9174 { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, 9175 }, 9176 9177 /* VEX_LEN_0F3A16_P_2 */ 9178 { 9179 { "vpextrK", { Edq, XM, Ib } }, 9180 }, 9181 9182 /* VEX_LEN_0F3A17_P_2 */ 9183 { 9184 { "vextractps", { Edqd, XM, Ib } }, 9185 }, 9186 9187 /* VEX_LEN_0F3A18_P_2 */ 9188 { 9189 { Bad_Opcode }, 9190 { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, 9191 }, 9192 9193 /* VEX_LEN_0F3A19_P_2 */ 9194 { 9195 { Bad_Opcode }, 9196 { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, 9197 }, 9198 9199 /* VEX_LEN_0F3A20_P_2 */ 9200 { 9201 { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, 9202 }, 9203 9204 /* VEX_LEN_0F3A21_P_2 */ 9205 { 9206 { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, 9207 }, 9208 9209 /* VEX_LEN_0F3A22_P_2 */ 9210 { 9211 { "vpinsrK", { XM, Vex128, Edq, Ib } }, 9212 }, 9213 9214 /* VEX_LEN_0F3A41_P_2 */ 9215 { 9216 { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, 9217 }, 9218 9219 /* VEX_LEN_0F3A42_P_2 */ 9220 { 9221 { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, 9222 }, 9223 9224 /* VEX_LEN_0F3A44_P_2 */ 9225 { 9226 { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, 9227 }, 9228 9229 /* VEX_LEN_0F3A4C_P_2 */ 9230 { 9231 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, 9232 }, 9233 9234 /* VEX_LEN_0F3A60_P_2 */ 9235 { 9236 { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, 9237 }, 9238 9239 /* VEX_LEN_0F3A61_P_2 */ 9240 { 9241 { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, 9242 }, 9243 9244 /* VEX_LEN_0F3A62_P_2 */ 9245 { 9246 { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, 9247 }, 9248 9249 /* VEX_LEN_0F3A63_P_2 */ 9250 { 9251 { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, 9252 }, 9253 9254 /* VEX_LEN_0F3A6A_P_2 */ 9255 { 9256 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, 9257 }, 9258 9259 /* VEX_LEN_0F3A6B_P_2 */ 9260 { 9261 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, 9262 }, 9263 9264 /* VEX_LEN_0F3A6E_P_2 */ 9265 { 9266 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, 9267 }, 9268 9269 /* VEX_LEN_0F3A6F_P_2 */ 9270 { 9271 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, 9272 }, 9273 9274 /* VEX_LEN_0F3A7A_P_2 */ 9275 { 9276 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, 9277 }, 9278 9279 /* VEX_LEN_0F3A7B_P_2 */ 9280 { 9281 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, 9282 }, 9283 9284 /* VEX_LEN_0F3A7E_P_2 */ 9285 { 9286 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, 9287 }, 9288 9289 /* VEX_LEN_0F3A7F_P_2 */ 9290 { 9291 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, 9292 }, 9293 9294 /* VEX_LEN_0F3ADF_P_2 */ 9295 { 9296 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, 9297 }, 9298 9299 /* VEX_LEN_0FXOP_09_80 */ 9300 { 9301 { "vfrczps", { XM, EXxmm } }, 9302 { "vfrczps", { XM, EXymmq } }, 9303 }, 9304 9305 /* VEX_LEN_0FXOP_09_81 */ 9306 { 9307 { "vfrczpd", { XM, EXxmm } }, 9308 { "vfrczpd", { XM, EXymmq } }, 9309 }, 9310 }; 9311 9312 static const struct dis386 vex_w_table[][2] = { 9313 { 9314 /* VEX_W_0F10_P_0 */ 9315 { "vmovups", { XM, EXx } }, 9316 }, 9317 { 9318 /* VEX_W_0F10_P_1 */ 9319 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, 9320 }, 9321 { 9322 /* VEX_W_0F10_P_2 */ 9323 { "vmovupd", { XM, EXx } }, 9324 }, 9325 { 9326 /* VEX_W_0F10_P_3 */ 9327 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, 9328 }, 9329 { 9330 /* VEX_W_0F11_P_0 */ 9331 { "vmovups", { EXxS, XM } }, 9332 }, 9333 { 9334 /* VEX_W_0F11_P_1 */ 9335 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, 9336 }, 9337 { 9338 /* VEX_W_0F11_P_2 */ 9339 { "vmovupd", { EXxS, XM } }, 9340 }, 9341 { 9342 /* VEX_W_0F11_P_3 */ 9343 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, 9344 }, 9345 { 9346 /* VEX_W_0F12_P_0_M_0 */ 9347 { "vmovlps", { XM, Vex128, EXq } }, 9348 }, 9349 { 9350 /* VEX_W_0F12_P_0_M_1 */ 9351 { "vmovhlps", { XM, Vex128, EXq } }, 9352 }, 9353 { 9354 /* VEX_W_0F12_P_1 */ 9355 { "vmovsldup", { XM, EXx } }, 9356 }, 9357 { 9358 /* VEX_W_0F12_P_2 */ 9359 { "vmovlpd", { XM, Vex128, EXq } }, 9360 }, 9361 { 9362 /* VEX_W_0F12_P_3 */ 9363 { "vmovddup", { XM, EXymmq } }, 9364 }, 9365 { 9366 /* VEX_W_0F13_M_0 */ 9367 { "vmovlpX", { EXq, XM } }, 9368 }, 9369 { 9370 /* VEX_W_0F14 */ 9371 { "vunpcklpX", { XM, Vex, EXx } }, 9372 }, 9373 { 9374 /* VEX_W_0F15 */ 9375 { "vunpckhpX", { XM, Vex, EXx } }, 9376 }, 9377 { 9378 /* VEX_W_0F16_P_0_M_0 */ 9379 { "vmovhps", { XM, Vex128, EXq } }, 9380 }, 9381 { 9382 /* VEX_W_0F16_P_0_M_1 */ 9383 { "vmovlhps", { XM, Vex128, EXq } }, 9384 }, 9385 { 9386 /* VEX_W_0F16_P_1 */ 9387 { "vmovshdup", { XM, EXx } }, 9388 }, 9389 { 9390 /* VEX_W_0F16_P_2 */ 9391 { "vmovhpd", { XM, Vex128, EXq } }, 9392 }, 9393 { 9394 /* VEX_W_0F17_M_0 */ 9395 { "vmovhpX", { EXq, XM } }, 9396 }, 9397 { 9398 /* VEX_W_0F28 */ 9399 { "vmovapX", { XM, EXx } }, 9400 }, 9401 { 9402 /* VEX_W_0F29 */ 9403 { "vmovapX", { EXxS, XM } }, 9404 }, 9405 { 9406 /* VEX_W_0F2B_M_0 */ 9407 { "vmovntpX", { Mx, XM } }, 9408 }, 9409 { 9410 /* VEX_W_0F2E_P_0 */ 9411 { "vucomiss", { XMScalar, EXdScalar } }, 9412 }, 9413 { 9414 /* VEX_W_0F2E_P_2 */ 9415 { "vucomisd", { XMScalar, EXqScalar } }, 9416 }, 9417 { 9418 /* VEX_W_0F2F_P_0 */ 9419 { "vcomiss", { XMScalar, EXdScalar } }, 9420 }, 9421 { 9422 /* VEX_W_0F2F_P_2 */ 9423 { "vcomisd", { XMScalar, EXqScalar } }, 9424 }, 9425 { 9426 /* VEX_W_0F50_M_0 */ 9427 { "vmovmskpX", { Gdq, XS } }, 9428 }, 9429 { 9430 /* VEX_W_0F51_P_0 */ 9431 { "vsqrtps", { XM, EXx } }, 9432 }, 9433 { 9434 /* VEX_W_0F51_P_1 */ 9435 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, 9436 }, 9437 { 9438 /* VEX_W_0F51_P_2 */ 9439 { "vsqrtpd", { XM, EXx } }, 9440 }, 9441 { 9442 /* VEX_W_0F51_P_3 */ 9443 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, 9444 }, 9445 { 9446 /* VEX_W_0F52_P_0 */ 9447 { "vrsqrtps", { XM, EXx } }, 9448 }, 9449 { 9450 /* VEX_W_0F52_P_1 */ 9451 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, 9452 }, 9453 { 9454 /* VEX_W_0F53_P_0 */ 9455 { "vrcpps", { XM, EXx } }, 9456 }, 9457 { 9458 /* VEX_W_0F53_P_1 */ 9459 { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, 9460 }, 9461 { 9462 /* VEX_W_0F58_P_0 */ 9463 { "vaddps", { XM, Vex, EXx } }, 9464 }, 9465 { 9466 /* VEX_W_0F58_P_1 */ 9467 { "vaddss", { XMScalar, VexScalar, EXdScalar } }, 9468 }, 9469 { 9470 /* VEX_W_0F58_P_2 */ 9471 { "vaddpd", { XM, Vex, EXx } }, 9472 }, 9473 { 9474 /* VEX_W_0F58_P_3 */ 9475 { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, 9476 }, 9477 { 9478 /* VEX_W_0F59_P_0 */ 9479 { "vmulps", { XM, Vex, EXx } }, 9480 }, 9481 { 9482 /* VEX_W_0F59_P_1 */ 9483 { "vmulss", { XMScalar, VexScalar, EXdScalar } }, 9484 }, 9485 { 9486 /* VEX_W_0F59_P_2 */ 9487 { "vmulpd", { XM, Vex, EXx } }, 9488 }, 9489 { 9490 /* VEX_W_0F59_P_3 */ 9491 { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, 9492 }, 9493 { 9494 /* VEX_W_0F5A_P_0 */ 9495 { "vcvtps2pd", { XM, EXxmmq } }, 9496 }, 9497 { 9498 /* VEX_W_0F5A_P_1 */ 9499 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, 9500 }, 9501 { 9502 /* VEX_W_0F5A_P_3 */ 9503 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, 9504 }, 9505 { 9506 /* VEX_W_0F5B_P_0 */ 9507 { "vcvtdq2ps", { XM, EXx } }, 9508 }, 9509 { 9510 /* VEX_W_0F5B_P_1 */ 9511 { "vcvttps2dq", { XM, EXx } }, 9512 }, 9513 { 9514 /* VEX_W_0F5B_P_2 */ 9515 { "vcvtps2dq", { XM, EXx } }, 9516 }, 9517 { 9518 /* VEX_W_0F5C_P_0 */ 9519 { "vsubps", { XM, Vex, EXx } }, 9520 }, 9521 { 9522 /* VEX_W_0F5C_P_1 */ 9523 { "vsubss", { XMScalar, VexScalar, EXdScalar } }, 9524 }, 9525 { 9526 /* VEX_W_0F5C_P_2 */ 9527 { "vsubpd", { XM, Vex, EXx } }, 9528 }, 9529 { 9530 /* VEX_W_0F5C_P_3 */ 9531 { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, 9532 }, 9533 { 9534 /* VEX_W_0F5D_P_0 */ 9535 { "vminps", { XM, Vex, EXx } }, 9536 }, 9537 { 9538 /* VEX_W_0F5D_P_1 */ 9539 { "vminss", { XMScalar, VexScalar, EXdScalar } }, 9540 }, 9541 { 9542 /* VEX_W_0F5D_P_2 */ 9543 { "vminpd", { XM, Vex, EXx } }, 9544 }, 9545 { 9546 /* VEX_W_0F5D_P_3 */ 9547 { "vminsd", { XMScalar, VexScalar, EXqScalar } }, 9548 }, 9549 { 9550 /* VEX_W_0F5E_P_0 */ 9551 { "vdivps", { XM, Vex, EXx } }, 9552 }, 9553 { 9554 /* VEX_W_0F5E_P_1 */ 9555 { "vdivss", { XMScalar, VexScalar, EXdScalar } }, 9556 }, 9557 { 9558 /* VEX_W_0F5E_P_2 */ 9559 { "vdivpd", { XM, Vex, EXx } }, 9560 }, 9561 { 9562 /* VEX_W_0F5E_P_3 */ 9563 { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, 9564 }, 9565 { 9566 /* VEX_W_0F5F_P_0 */ 9567 { "vmaxps", { XM, Vex, EXx } }, 9568 }, 9569 { 9570 /* VEX_W_0F5F_P_1 */ 9571 { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, 9572 }, 9573 { 9574 /* VEX_W_0F5F_P_2 */ 9575 { "vmaxpd", { XM, Vex, EXx } }, 9576 }, 9577 { 9578 /* VEX_W_0F5F_P_3 */ 9579 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, 9580 }, 9581 { 9582 /* VEX_W_0F60_P_2 */ 9583 { "vpunpcklbw", { XM, Vex128, EXx } }, 9584 }, 9585 { 9586 /* VEX_W_0F61_P_2 */ 9587 { "vpunpcklwd", { XM, Vex128, EXx } }, 9588 }, 9589 { 9590 /* VEX_W_0F62_P_2 */ 9591 { "vpunpckldq", { XM, Vex128, EXx } }, 9592 }, 9593 { 9594 /* VEX_W_0F63_P_2 */ 9595 { "vpacksswb", { XM, Vex128, EXx } }, 9596 }, 9597 { 9598 /* VEX_W_0F64_P_2 */ 9599 { "vpcmpgtb", { XM, Vex128, EXx } }, 9600 }, 9601 { 9602 /* VEX_W_0F65_P_2 */ 9603 { "vpcmpgtw", { XM, Vex128, EXx } }, 9604 }, 9605 { 9606 /* VEX_W_0F66_P_2 */ 9607 { "vpcmpgtd", { XM, Vex128, EXx } }, 9608 }, 9609 { 9610 /* VEX_W_0F67_P_2 */ 9611 { "vpackuswb", { XM, Vex128, EXx } }, 9612 }, 9613 { 9614 /* VEX_W_0F68_P_2 */ 9615 { "vpunpckhbw", { XM, Vex128, EXx } }, 9616 }, 9617 { 9618 /* VEX_W_0F69_P_2 */ 9619 { "vpunpckhwd", { XM, Vex128, EXx } }, 9620 }, 9621 { 9622 /* VEX_W_0F6A_P_2 */ 9623 { "vpunpckhdq", { XM, Vex128, EXx } }, 9624 }, 9625 { 9626 /* VEX_W_0F6B_P_2 */ 9627 { "vpackssdw", { XM, Vex128, EXx } }, 9628 }, 9629 { 9630 /* VEX_W_0F6C_P_2 */ 9631 { "vpunpcklqdq", { XM, Vex128, EXx } }, 9632 }, 9633 { 9634 /* VEX_W_0F6D_P_2 */ 9635 { "vpunpckhqdq", { XM, Vex128, EXx } }, 9636 }, 9637 { 9638 /* VEX_W_0F6F_P_1 */ 9639 { "vmovdqu", { XM, EXx } }, 9640 }, 9641 { 9642 /* VEX_W_0F6F_P_2 */ 9643 { "vmovdqa", { XM, EXx } }, 9644 }, 9645 { 9646 /* VEX_W_0F70_P_1 */ 9647 { "vpshufhw", { XM, EXx, Ib } }, 9648 }, 9649 { 9650 /* VEX_W_0F70_P_2 */ 9651 { "vpshufd", { XM, EXx, Ib } }, 9652 }, 9653 { 9654 /* VEX_W_0F70_P_3 */ 9655 { "vpshuflw", { XM, EXx, Ib } }, 9656 }, 9657 { 9658 /* VEX_W_0F71_R_2_P_2 */ 9659 { "vpsrlw", { Vex128, XS, Ib } }, 9660 }, 9661 { 9662 /* VEX_W_0F71_R_4_P_2 */ 9663 { "vpsraw", { Vex128, XS, Ib } }, 9664 }, 9665 { 9666 /* VEX_W_0F71_R_6_P_2 */ 9667 { "vpsllw", { Vex128, XS, Ib } }, 9668 }, 9669 { 9670 /* VEX_W_0F72_R_2_P_2 */ 9671 { "vpsrld", { Vex128, XS, Ib } }, 9672 }, 9673 { 9674 /* VEX_W_0F72_R_4_P_2 */ 9675 { "vpsrad", { Vex128, XS, Ib } }, 9676 }, 9677 { 9678 /* VEX_W_0F72_R_6_P_2 */ 9679 { "vpslld", { Vex128, XS, Ib } }, 9680 }, 9681 { 9682 /* VEX_W_0F73_R_2_P_2 */ 9683 { "vpsrlq", { Vex128, XS, Ib } }, 9684 }, 9685 { 9686 /* VEX_W_0F73_R_3_P_2 */ 9687 { "vpsrldq", { Vex128, XS, Ib } }, 9688 }, 9689 { 9690 /* VEX_W_0F73_R_6_P_2 */ 9691 { "vpsllq", { Vex128, XS, Ib } }, 9692 }, 9693 { 9694 /* VEX_W_0F73_R_7_P_2 */ 9695 { "vpslldq", { Vex128, XS, Ib } }, 9696 }, 9697 { 9698 /* VEX_W_0F74_P_2 */ 9699 { "vpcmpeqb", { XM, Vex128, EXx } }, 9700 }, 9701 { 9702 /* VEX_W_0F75_P_2 */ 9703 { "vpcmpeqw", { XM, Vex128, EXx } }, 9704 }, 9705 { 9706 /* VEX_W_0F76_P_2 */ 9707 { "vpcmpeqd", { XM, Vex128, EXx } }, 9708 }, 9709 { 9710 /* VEX_W_0F77_P_0 */ 9711 { "", { VZERO } }, 9712 }, 9713 { 9714 /* VEX_W_0F7C_P_2 */ 9715 { "vhaddpd", { XM, Vex, EXx } }, 9716 }, 9717 { 9718 /* VEX_W_0F7C_P_3 */ 9719 { "vhaddps", { XM, Vex, EXx } }, 9720 }, 9721 { 9722 /* VEX_W_0F7D_P_2 */ 9723 { "vhsubpd", { XM, Vex, EXx } }, 9724 }, 9725 { 9726 /* VEX_W_0F7D_P_3 */ 9727 { "vhsubps", { XM, Vex, EXx } }, 9728 }, 9729 { 9730 /* VEX_W_0F7E_P_1 */ 9731 { "vmovq", { XMScalar, EXqScalar } }, 9732 }, 9733 { 9734 /* VEX_W_0F7F_P_1 */ 9735 { "vmovdqu", { EXxS, XM } }, 9736 }, 9737 { 9738 /* VEX_W_0F7F_P_2 */ 9739 { "vmovdqa", { EXxS, XM } }, 9740 }, 9741 { 9742 /* VEX_W_0FAE_R_2_M_0 */ 9743 { "vldmxcsr", { Md } }, 9744 }, 9745 { 9746 /* VEX_W_0FAE_R_3_M_0 */ 9747 { "vstmxcsr", { Md } }, 9748 }, 9749 { 9750 /* VEX_W_0FC2_P_0 */ 9751 { "vcmpps", { XM, Vex, EXx, VCMP } }, 9752 }, 9753 { 9754 /* VEX_W_0FC2_P_1 */ 9755 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, 9756 }, 9757 { 9758 /* VEX_W_0FC2_P_2 */ 9759 { "vcmppd", { XM, Vex, EXx, VCMP } }, 9760 }, 9761 { 9762 /* VEX_W_0FC2_P_3 */ 9763 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, 9764 }, 9765 { 9766 /* VEX_W_0FC4_P_2 */ 9767 { "vpinsrw", { XM, Vex128, Edqw, Ib } }, 9768 }, 9769 { 9770 /* VEX_W_0FC5_P_2 */ 9771 { "vpextrw", { Gdq, XS, Ib } }, 9772 }, 9773 { 9774 /* VEX_W_0FD0_P_2 */ 9775 { "vaddsubpd", { XM, Vex, EXx } }, 9776 }, 9777 { 9778 /* VEX_W_0FD0_P_3 */ 9779 { "vaddsubps", { XM, Vex, EXx } }, 9780 }, 9781 { 9782 /* VEX_W_0FD1_P_2 */ 9783 { "vpsrlw", { XM, Vex128, EXx } }, 9784 }, 9785 { 9786 /* VEX_W_0FD2_P_2 */ 9787 { "vpsrld", { XM, Vex128, EXx } }, 9788 }, 9789 { 9790 /* VEX_W_0FD3_P_2 */ 9791 { "vpsrlq", { XM, Vex128, EXx } }, 9792 }, 9793 { 9794 /* VEX_W_0FD4_P_2 */ 9795 { "vpaddq", { XM, Vex128, EXx } }, 9796 }, 9797 { 9798 /* VEX_W_0FD5_P_2 */ 9799 { "vpmullw", { XM, Vex128, EXx } }, 9800 }, 9801 { 9802 /* VEX_W_0FD6_P_2 */ 9803 { "vmovq", { EXqScalarS, XMScalar } }, 9804 }, 9805 { 9806 /* VEX_W_0FD7_P_2_M_1 */ 9807 { "vpmovmskb", { Gdq, XS } }, 9808 }, 9809 { 9810 /* VEX_W_0FD8_P_2 */ 9811 { "vpsubusb", { XM, Vex128, EXx } }, 9812 }, 9813 { 9814 /* VEX_W_0FD9_P_2 */ 9815 { "vpsubusw", { XM, Vex128, EXx } }, 9816 }, 9817 { 9818 /* VEX_W_0FDA_P_2 */ 9819 { "vpminub", { XM, Vex128, EXx } }, 9820 }, 9821 { 9822 /* VEX_W_0FDB_P_2 */ 9823 { "vpand", { XM, Vex128, EXx } }, 9824 }, 9825 { 9826 /* VEX_W_0FDC_P_2 */ 9827 { "vpaddusb", { XM, Vex128, EXx } }, 9828 }, 9829 { 9830 /* VEX_W_0FDD_P_2 */ 9831 { "vpaddusw", { XM, Vex128, EXx } }, 9832 }, 9833 { 9834 /* VEX_W_0FDE_P_2 */ 9835 { "vpmaxub", { XM, Vex128, EXx } }, 9836 }, 9837 { 9838 /* VEX_W_0FDF_P_2 */ 9839 { "vpandn", { XM, Vex128, EXx } }, 9840 }, 9841 { 9842 /* VEX_W_0FE0_P_2 */ 9843 { "vpavgb", { XM, Vex128, EXx } }, 9844 }, 9845 { 9846 /* VEX_W_0FE1_P_2 */ 9847 { "vpsraw", { XM, Vex128, EXx } }, 9848 }, 9849 { 9850 /* VEX_W_0FE2_P_2 */ 9851 { "vpsrad", { XM, Vex128, EXx } }, 9852 }, 9853 { 9854 /* VEX_W_0FE3_P_2 */ 9855 { "vpavgw", { XM, Vex128, EXx } }, 9856 }, 9857 { 9858 /* VEX_W_0FE4_P_2 */ 9859 { "vpmulhuw", { XM, Vex128, EXx } }, 9860 }, 9861 { 9862 /* VEX_W_0FE5_P_2 */ 9863 { "vpmulhw", { XM, Vex128, EXx } }, 9864 }, 9865 { 9866 /* VEX_W_0FE6_P_1 */ 9867 { "vcvtdq2pd", { XM, EXxmmq } }, 9868 }, 9869 { 9870 /* VEX_W_0FE6_P_2 */ 9871 { "vcvttpd2dq%XY", { XMM, EXx } }, 9872 }, 9873 { 9874 /* VEX_W_0FE6_P_3 */ 9875 { "vcvtpd2dq%XY", { XMM, EXx } }, 9876 }, 9877 { 9878 /* VEX_W_0FE7_P_2_M_0 */ 9879 { "vmovntdq", { Mx, XM } }, 9880 }, 9881 { 9882 /* VEX_W_0FE8_P_2 */ 9883 { "vpsubsb", { XM, Vex128, EXx } }, 9884 }, 9885 { 9886 /* VEX_W_0FE9_P_2 */ 9887 { "vpsubsw", { XM, Vex128, EXx } }, 9888 }, 9889 { 9890 /* VEX_W_0FEA_P_2 */ 9891 { "vpminsw", { XM, Vex128, EXx } }, 9892 }, 9893 { 9894 /* VEX_W_0FEB_P_2 */ 9895 { "vpor", { XM, Vex128, EXx } }, 9896 }, 9897 { 9898 /* VEX_W_0FEC_P_2 */ 9899 { "vpaddsb", { XM, Vex128, EXx } }, 9900 }, 9901 { 9902 /* VEX_W_0FED_P_2 */ 9903 { "vpaddsw", { XM, Vex128, EXx } }, 9904 }, 9905 { 9906 /* VEX_W_0FEE_P_2 */ 9907 { "vpmaxsw", { XM, Vex128, EXx } }, 9908 }, 9909 { 9910 /* VEX_W_0FEF_P_2 */ 9911 { "vpxor", { XM, Vex128, EXx } }, 9912 }, 9913 { 9914 /* VEX_W_0FF0_P_3_M_0 */ 9915 { "vlddqu", { XM, M } }, 9916 }, 9917 { 9918 /* VEX_W_0FF1_P_2 */ 9919 { "vpsllw", { XM, Vex128, EXx } }, 9920 }, 9921 { 9922 /* VEX_W_0FF2_P_2 */ 9923 { "vpslld", { XM, Vex128, EXx } }, 9924 }, 9925 { 9926 /* VEX_W_0FF3_P_2 */ 9927 { "vpsllq", { XM, Vex128, EXx } }, 9928 }, 9929 { 9930 /* VEX_W_0FF4_P_2 */ 9931 { "vpmuludq", { XM, Vex128, EXx } }, 9932 }, 9933 { 9934 /* VEX_W_0FF5_P_2 */ 9935 { "vpmaddwd", { XM, Vex128, EXx } }, 9936 }, 9937 { 9938 /* VEX_W_0FF6_P_2 */ 9939 { "vpsadbw", { XM, Vex128, EXx } }, 9940 }, 9941 { 9942 /* VEX_W_0FF7_P_2 */ 9943 { "vmaskmovdqu", { XM, XS } }, 9944 }, 9945 { 9946 /* VEX_W_0FF8_P_2 */ 9947 { "vpsubb", { XM, Vex128, EXx } }, 9948 }, 9949 { 9950 /* VEX_W_0FF9_P_2 */ 9951 { "vpsubw", { XM, Vex128, EXx } }, 9952 }, 9953 { 9954 /* VEX_W_0FFA_P_2 */ 9955 { "vpsubd", { XM, Vex128, EXx } }, 9956 }, 9957 { 9958 /* VEX_W_0FFB_P_2 */ 9959 { "vpsubq", { XM, Vex128, EXx } }, 9960 }, 9961 { 9962 /* VEX_W_0FFC_P_2 */ 9963 { "vpaddb", { XM, Vex128, EXx } }, 9964 }, 9965 { 9966 /* VEX_W_0FFD_P_2 */ 9967 { "vpaddw", { XM, Vex128, EXx } }, 9968 }, 9969 { 9970 /* VEX_W_0FFE_P_2 */ 9971 { "vpaddd", { XM, Vex128, EXx } }, 9972 }, 9973 { 9974 /* VEX_W_0F3800_P_2 */ 9975 { "vpshufb", { XM, Vex128, EXx } }, 9976 }, 9977 { 9978 /* VEX_W_0F3801_P_2 */ 9979 { "vphaddw", { XM, Vex128, EXx } }, 9980 }, 9981 { 9982 /* VEX_W_0F3802_P_2 */ 9983 { "vphaddd", { XM, Vex128, EXx } }, 9984 }, 9985 { 9986 /* VEX_W_0F3803_P_2 */ 9987 { "vphaddsw", { XM, Vex128, EXx } }, 9988 }, 9989 { 9990 /* VEX_W_0F3804_P_2 */ 9991 { "vpmaddubsw", { XM, Vex128, EXx } }, 9992 }, 9993 { 9994 /* VEX_W_0F3805_P_2 */ 9995 { "vphsubw", { XM, Vex128, EXx } }, 9996 }, 9997 { 9998 /* VEX_W_0F3806_P_2 */ 9999 { "vphsubd", { XM, Vex128, EXx } }, 10000 }, 10001 { 10002 /* VEX_W_0F3807_P_2 */ 10003 { "vphsubsw", { XM, Vex128, EXx } }, 10004 }, 10005 { 10006 /* VEX_W_0F3808_P_2 */ 10007 { "vpsignb", { XM, Vex128, EXx } }, 10008 }, 10009 { 10010 /* VEX_W_0F3809_P_2 */ 10011 { "vpsignw", { XM, Vex128, EXx } }, 10012 }, 10013 { 10014 /* VEX_W_0F380A_P_2 */ 10015 { "vpsignd", { XM, Vex128, EXx } }, 10016 }, 10017 { 10018 /* VEX_W_0F380B_P_2 */ 10019 { "vpmulhrsw", { XM, Vex128, EXx } }, 10020 }, 10021 { 10022 /* VEX_W_0F380C_P_2 */ 10023 { "vpermilps", { XM, Vex, EXx } }, 10024 }, 10025 { 10026 /* VEX_W_0F380D_P_2 */ 10027 { "vpermilpd", { XM, Vex, EXx } }, 10028 }, 10029 { 10030 /* VEX_W_0F380E_P_2 */ 10031 { "vtestps", { XM, EXx } }, 10032 }, 10033 { 10034 /* VEX_W_0F380F_P_2 */ 10035 { "vtestpd", { XM, EXx } }, 10036 }, 10037 { 10038 /* VEX_W_0F3817_P_2 */ 10039 { "vptest", { XM, EXx } }, 10040 }, 10041 { 10042 /* VEX_W_0F3818_P_2_M_0 */ 10043 { "vbroadcastss", { XM, Md } }, 10044 }, 10045 { 10046 /* VEX_W_0F3819_P_2_M_0 */ 10047 { "vbroadcastsd", { XM, Mq } }, 10048 }, 10049 { 10050 /* VEX_W_0F381A_P_2_M_0 */ 10051 { "vbroadcastf128", { XM, Mxmm } }, 10052 }, 10053 { 10054 /* VEX_W_0F381C_P_2 */ 10055 { "vpabsb", { XM, EXx } }, 10056 }, 10057 { 10058 /* VEX_W_0F381D_P_2 */ 10059 { "vpabsw", { XM, EXx } }, 10060 }, 10061 { 10062 /* VEX_W_0F381E_P_2 */ 10063 { "vpabsd", { XM, EXx } }, 10064 }, 10065 { 10066 /* VEX_W_0F3820_P_2 */ 10067 { "vpmovsxbw", { XM, EXq } }, 10068 }, 10069 { 10070 /* VEX_W_0F3821_P_2 */ 10071 { "vpmovsxbd", { XM, EXd } }, 10072 }, 10073 { 10074 /* VEX_W_0F3822_P_2 */ 10075 { "vpmovsxbq", { XM, EXw } }, 10076 }, 10077 { 10078 /* VEX_W_0F3823_P_2 */ 10079 { "vpmovsxwd", { XM, EXq } }, 10080 }, 10081 { 10082 /* VEX_W_0F3824_P_2 */ 10083 { "vpmovsxwq", { XM, EXd } }, 10084 }, 10085 { 10086 /* VEX_W_0F3825_P_2 */ 10087 { "vpmovsxdq", { XM, EXq } }, 10088 }, 10089 { 10090 /* VEX_W_0F3828_P_2 */ 10091 { "vpmuldq", { XM, Vex128, EXx } }, 10092 }, 10093 { 10094 /* VEX_W_0F3829_P_2 */ 10095 { "vpcmpeqq", { XM, Vex128, EXx } }, 10096 }, 10097 { 10098 /* VEX_W_0F382A_P_2_M_0 */ 10099 { "vmovntdqa", { XM, Mx } }, 10100 }, 10101 { 10102 /* VEX_W_0F382B_P_2 */ 10103 { "vpackusdw", { XM, Vex128, EXx } }, 10104 }, 10105 { 10106 /* VEX_W_0F382C_P_2_M_0 */ 10107 { "vmaskmovps", { XM, Vex, Mx } }, 10108 }, 10109 { 10110 /* VEX_W_0F382D_P_2_M_0 */ 10111 { "vmaskmovpd", { XM, Vex, Mx } }, 10112 }, 10113 { 10114 /* VEX_W_0F382E_P_2_M_0 */ 10115 { "vmaskmovps", { Mx, Vex, XM } }, 10116 }, 10117 { 10118 /* VEX_W_0F382F_P_2_M_0 */ 10119 { "vmaskmovpd", { Mx, Vex, XM } }, 10120 }, 10121 { 10122 /* VEX_W_0F3830_P_2 */ 10123 { "vpmovzxbw", { XM, EXq } }, 10124 }, 10125 { 10126 /* VEX_W_0F3831_P_2 */ 10127 { "vpmovzxbd", { XM, EXd } }, 10128 }, 10129 { 10130 /* VEX_W_0F3832_P_2 */ 10131 { "vpmovzxbq", { XM, EXw } }, 10132 }, 10133 { 10134 /* VEX_W_0F3833_P_2 */ 10135 { "vpmovzxwd", { XM, EXq } }, 10136 }, 10137 { 10138 /* VEX_W_0F3834_P_2 */ 10139 { "vpmovzxwq", { XM, EXd } }, 10140 }, 10141 { 10142 /* VEX_W_0F3835_P_2 */ 10143 { "vpmovzxdq", { XM, EXq } }, 10144 }, 10145 { 10146 /* VEX_W_0F3837_P_2 */ 10147 { "vpcmpgtq", { XM, Vex128, EXx } }, 10148 }, 10149 { 10150 /* VEX_W_0F3838_P_2 */ 10151 { "vpminsb", { XM, Vex128, EXx } }, 10152 }, 10153 { 10154 /* VEX_W_0F3839_P_2 */ 10155 { "vpminsd", { XM, Vex128, EXx } }, 10156 }, 10157 { 10158 /* VEX_W_0F383A_P_2 */ 10159 { "vpminuw", { XM, Vex128, EXx } }, 10160 }, 10161 { 10162 /* VEX_W_0F383B_P_2 */ 10163 { "vpminud", { XM, Vex128, EXx } }, 10164 }, 10165 { 10166 /* VEX_W_0F383C_P_2 */ 10167 { "vpmaxsb", { XM, Vex128, EXx } }, 10168 }, 10169 { 10170 /* VEX_W_0F383D_P_2 */ 10171 { "vpmaxsd", { XM, Vex128, EXx } }, 10172 }, 10173 { 10174 /* VEX_W_0F383E_P_2 */ 10175 { "vpmaxuw", { XM, Vex128, EXx } }, 10176 }, 10177 { 10178 /* VEX_W_0F383F_P_2 */ 10179 { "vpmaxud", { XM, Vex128, EXx } }, 10180 }, 10181 { 10182 /* VEX_W_0F3840_P_2 */ 10183 { "vpmulld", { XM, Vex128, EXx } }, 10184 }, 10185 { 10186 /* VEX_W_0F3841_P_2 */ 10187 { "vphminposuw", { XM, EXx } }, 10188 }, 10189 { 10190 /* VEX_W_0F38DB_P_2 */ 10191 { "vaesimc", { XM, EXx } }, 10192 }, 10193 { 10194 /* VEX_W_0F38DC_P_2 */ 10195 { "vaesenc", { XM, Vex128, EXx } }, 10196 }, 10197 { 10198 /* VEX_W_0F38DD_P_2 */ 10199 { "vaesenclast", { XM, Vex128, EXx } }, 10200 }, 10201 { 10202 /* VEX_W_0F38DE_P_2 */ 10203 { "vaesdec", { XM, Vex128, EXx } }, 10204 }, 10205 { 10206 /* VEX_W_0F38DF_P_2 */ 10207 { "vaesdeclast", { XM, Vex128, EXx } }, 10208 }, 10209 { 10210 /* VEX_W_0F3A04_P_2 */ 10211 { "vpermilps", { XM, EXx, Ib } }, 10212 }, 10213 { 10214 /* VEX_W_0F3A05_P_2 */ 10215 { "vpermilpd", { XM, EXx, Ib } }, 10216 }, 10217 { 10218 /* VEX_W_0F3A06_P_2 */ 10219 { "vperm2f128", { XM, Vex256, EXx, Ib } }, 10220 }, 10221 { 10222 /* VEX_W_0F3A08_P_2 */ 10223 { "vroundps", { XM, EXx, Ib } }, 10224 }, 10225 { 10226 /* VEX_W_0F3A09_P_2 */ 10227 { "vroundpd", { XM, EXx, Ib } }, 10228 }, 10229 { 10230 /* VEX_W_0F3A0A_P_2 */ 10231 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, 10232 }, 10233 { 10234 /* VEX_W_0F3A0B_P_2 */ 10235 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, 10236 }, 10237 { 10238 /* VEX_W_0F3A0C_P_2 */ 10239 { "vblendps", { XM, Vex, EXx, Ib } }, 10240 }, 10241 { 10242 /* VEX_W_0F3A0D_P_2 */ 10243 { "vblendpd", { XM, Vex, EXx, Ib } }, 10244 }, 10245 { 10246 /* VEX_W_0F3A0E_P_2 */ 10247 { "vpblendw", { XM, Vex128, EXx, Ib } }, 10248 }, 10249 { 10250 /* VEX_W_0F3A0F_P_2 */ 10251 { "vpalignr", { XM, Vex128, EXx, Ib } }, 10252 }, 10253 { 10254 /* VEX_W_0F3A14_P_2 */ 10255 { "vpextrb", { Edqb, XM, Ib } }, 10256 }, 10257 { 10258 /* VEX_W_0F3A15_P_2 */ 10259 { "vpextrw", { Edqw, XM, Ib } }, 10260 }, 10261 { 10262 /* VEX_W_0F3A18_P_2 */ 10263 { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, 10264 }, 10265 { 10266 /* VEX_W_0F3A19_P_2 */ 10267 { "vextractf128", { EXxmm, XM, Ib } }, 10268 }, 10269 { 10270 /* VEX_W_0F3A20_P_2 */ 10271 { "vpinsrb", { XM, Vex128, Edqb, Ib } }, 10272 }, 10273 { 10274 /* VEX_W_0F3A21_P_2 */ 10275 { "vinsertps", { XM, Vex128, EXd, Ib } }, 10276 }, 10277 { 10278 /* VEX_W_0F3A40_P_2 */ 10279 { "vdpps", { XM, Vex, EXx, Ib } }, 10280 }, 10281 { 10282 /* VEX_W_0F3A41_P_2 */ 10283 { "vdppd", { XM, Vex128, EXx, Ib } }, 10284 }, 10285 { 10286 /* VEX_W_0F3A42_P_2 */ 10287 { "vmpsadbw", { XM, Vex128, EXx, Ib } }, 10288 }, 10289 { 10290 /* VEX_W_0F3A44_P_2 */ 10291 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, 10292 }, 10293 { 10294 /* VEX_W_0F3A48_P_2 */ 10295 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, 10296 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, 10297 }, 10298 { 10299 /* VEX_W_0F3A49_P_2 */ 10300 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, 10301 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, 10302 }, 10303 { 10304 /* VEX_W_0F3A4A_P_2 */ 10305 { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, 10306 }, 10307 { 10308 /* VEX_W_0F3A4B_P_2 */ 10309 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, 10310 }, 10311 { 10312 /* VEX_W_0F3A4C_P_2 */ 10313 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } }, 10314 }, 10315 { 10316 /* VEX_W_0F3A60_P_2 */ 10317 { "vpcmpestrm", { XM, EXx, Ib } }, 10318 }, 10319 { 10320 /* VEX_W_0F3A61_P_2 */ 10321 { "vpcmpestri", { XM, EXx, Ib } }, 10322 }, 10323 { 10324 /* VEX_W_0F3A62_P_2 */ 10325 { "vpcmpistrm", { XM, EXx, Ib } }, 10326 }, 10327 { 10328 /* VEX_W_0F3A63_P_2 */ 10329 { "vpcmpistri", { XM, EXx, Ib } }, 10330 }, 10331 { 10332 /* VEX_W_0F3ADF_P_2 */ 10333 { "vaeskeygenassist", { XM, EXx, Ib } }, 10334 }, 10335 }; 10336 10337 static const struct dis386 mod_table[][2] = { 10338 { 10339 /* MOD_8D */ 10340 { "leaS", { Gv, M } }, 10341 }, 10342 { 10343 /* MOD_0F01_REG_0 */ 10344 { X86_64_TABLE (X86_64_0F01_REG_0) }, 10345 { RM_TABLE (RM_0F01_REG_0) }, 10346 }, 10347 { 10348 /* MOD_0F01_REG_1 */ 10349 { X86_64_TABLE (X86_64_0F01_REG_1) }, 10350 { RM_TABLE (RM_0F01_REG_1) }, 10351 }, 10352 { 10353 /* MOD_0F01_REG_2 */ 10354 { X86_64_TABLE (X86_64_0F01_REG_2) }, 10355 { RM_TABLE (RM_0F01_REG_2) }, 10356 }, 10357 { 10358 /* MOD_0F01_REG_3 */ 10359 { X86_64_TABLE (X86_64_0F01_REG_3) }, 10360 { RM_TABLE (RM_0F01_REG_3) }, 10361 }, 10362 { 10363 /* MOD_0F01_REG_7 */ 10364 { "invlpg", { Mb } }, 10365 { RM_TABLE (RM_0F01_REG_7) }, 10366 }, 10367 { 10368 /* MOD_0F12_PREFIX_0 */ 10369 { "movlps", { XM, EXq } }, 10370 { "movhlps", { XM, EXq } }, 10371 }, 10372 { 10373 /* MOD_0F13 */ 10374 { "movlpX", { EXq, XM } }, 10375 }, 10376 { 10377 /* MOD_0F16_PREFIX_0 */ 10378 { "movhps", { XM, EXq } }, 10379 { "movlhps", { XM, EXq } }, 10380 }, 10381 { 10382 /* MOD_0F17 */ 10383 { "movhpX", { EXq, XM } }, 10384 }, 10385 { 10386 /* MOD_0F18_REG_0 */ 10387 { "prefetchnta", { Mb } }, 10388 }, 10389 { 10390 /* MOD_0F18_REG_1 */ 10391 { "prefetcht0", { Mb } }, 10392 }, 10393 { 10394 /* MOD_0F18_REG_2 */ 10395 { "prefetcht1", { Mb } }, 10396 }, 10397 { 10398 /* MOD_0F18_REG_3 */ 10399 { "prefetcht2", { Mb } }, 10400 }, 10401 { 10402 /* MOD_0F20 */ 10403 { Bad_Opcode }, 10404 { "movZ", { Rm, Cm } }, 10405 }, 10406 { 10407 /* MOD_0F21 */ 10408 { Bad_Opcode }, 10409 { "movZ", { Rm, Dm } }, 10410 }, 10411 { 10412 /* MOD_0F22 */ 10413 { Bad_Opcode }, 10414 { "movZ", { Cm, Rm } }, 10415 }, 10416 { 10417 /* MOD_0F23 */ 10418 { Bad_Opcode }, 10419 { "movZ", { Dm, Rm } }, 10420 }, 10421 { 10422 /* MOD_0F24 */ 10423 { Bad_Opcode }, 10424 { "movL", { Rd, Td } }, 10425 }, 10426 { 10427 /* MOD_0F26 */ 10428 { Bad_Opcode }, 10429 { "movL", { Td, Rd } }, 10430 }, 10431 { 10432 /* MOD_0F2B_PREFIX_0 */ 10433 {"movntps", { Mx, XM } }, 10434 }, 10435 { 10436 /* MOD_0F2B_PREFIX_1 */ 10437 {"movntss", { Md, XM } }, 10438 }, 10439 { 10440 /* MOD_0F2B_PREFIX_2 */ 10441 {"movntpd", { Mx, XM } }, 10442 }, 10443 { 10444 /* MOD_0F2B_PREFIX_3 */ 10445 {"movntsd", { Mq, XM } }, 10446 }, 10447 { 10448 /* MOD_0F51 */ 10449 { Bad_Opcode }, 10450 { "movmskpX", { Gdq, XS } }, 10451 }, 10452 { 10453 /* MOD_0F71_REG_2 */ 10454 { Bad_Opcode }, 10455 { "psrlw", { MS, Ib } }, 10456 }, 10457 { 10458 /* MOD_0F71_REG_4 */ 10459 { Bad_Opcode }, 10460 { "psraw", { MS, Ib } }, 10461 }, 10462 { 10463 /* MOD_0F71_REG_6 */ 10464 { Bad_Opcode }, 10465 { "psllw", { MS, Ib } }, 10466 }, 10467 { 10468 /* MOD_0F72_REG_2 */ 10469 { Bad_Opcode }, 10470 { "psrld", { MS, Ib } }, 10471 }, 10472 { 10473 /* MOD_0F72_REG_4 */ 10474 { Bad_Opcode }, 10475 { "psrad", { MS, Ib } }, 10476 }, 10477 { 10478 /* MOD_0F72_REG_6 */ 10479 { Bad_Opcode }, 10480 { "pslld", { MS, Ib } }, 10481 }, 10482 { 10483 /* MOD_0F73_REG_2 */ 10484 { Bad_Opcode }, 10485 { "psrlq", { MS, Ib } }, 10486 }, 10487 { 10488 /* MOD_0F73_REG_3 */ 10489 { Bad_Opcode }, 10490 { PREFIX_TABLE (PREFIX_0F73_REG_3) }, 10491 }, 10492 { 10493 /* MOD_0F73_REG_6 */ 10494 { Bad_Opcode }, 10495 { "psllq", { MS, Ib } }, 10496 }, 10497 { 10498 /* MOD_0F73_REG_7 */ 10499 { Bad_Opcode }, 10500 { PREFIX_TABLE (PREFIX_0F73_REG_7) }, 10501 }, 10502 { 10503 /* MOD_0FAE_REG_0 */ 10504 { "fxsave", { FXSAVE } }, 10505 { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, 10506 }, 10507 { 10508 /* MOD_0FAE_REG_1 */ 10509 { "fxrstor", { FXSAVE } }, 10510 { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, 10511 }, 10512 { 10513 /* MOD_0FAE_REG_2 */ 10514 { "ldmxcsr", { Md } }, 10515 { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, 10516 }, 10517 { 10518 /* MOD_0FAE_REG_3 */ 10519 { "stmxcsr", { Md } }, 10520 { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, 10521 }, 10522 { 10523 /* MOD_0FAE_REG_4 */ 10524 { "xsave", { FXSAVE } }, 10525 }, 10526 { 10527 /* MOD_0FAE_REG_5 */ 10528 { "xrstor", { FXSAVE } }, 10529 { RM_TABLE (RM_0FAE_REG_5) }, 10530 }, 10531 { 10532 /* MOD_0FAE_REG_6 */ 10533 { "xsaveopt", { FXSAVE } }, 10534 { RM_TABLE (RM_0FAE_REG_6) }, 10535 }, 10536 { 10537 /* MOD_0FAE_REG_7 */ 10538 { "clflush", { Mb } }, 10539 { RM_TABLE (RM_0FAE_REG_7) }, 10540 }, 10541 { 10542 /* MOD_0FB2 */ 10543 { "lssS", { Gv, Mp } }, 10544 }, 10545 { 10546 /* MOD_0FB4 */ 10547 { "lfsS", { Gv, Mp } }, 10548 }, 10549 { 10550 /* MOD_0FB5 */ 10551 { "lgsS", { Gv, Mp } }, 10552 }, 10553 { 10554 /* MOD_0FC7_REG_6 */ 10555 { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, 10556 { "rdrand", { Ev } }, 10557 }, 10558 { 10559 /* MOD_0FC7_REG_7 */ 10560 { "vmptrst", { Mq } }, 10561 }, 10562 { 10563 /* MOD_0FD7 */ 10564 { Bad_Opcode }, 10565 { "pmovmskb", { Gdq, MS } }, 10566 }, 10567 { 10568 /* MOD_0FE7_PREFIX_2 */ 10569 { "movntdq", { Mx, XM } }, 10570 }, 10571 { 10572 /* MOD_0FF0_PREFIX_3 */ 10573 { "lddqu", { XM, M } }, 10574 }, 10575 { 10576 /* MOD_0F382A_PREFIX_2 */ 10577 { "movntdqa", { XM, Mx } }, 10578 }, 10579 { 10580 /* MOD_62_32BIT */ 10581 { "bound{S|}", { Gv, Ma } }, 10582 }, 10583 { 10584 /* MOD_C4_32BIT */ 10585 { "lesS", { Gv, Mp } }, 10586 { VEX_C4_TABLE (VEX_0F) }, 10587 }, 10588 { 10589 /* MOD_C5_32BIT */ 10590 { "ldsS", { Gv, Mp } }, 10591 { VEX_C5_TABLE (VEX_0F) }, 10592 }, 10593 { 10594 /* MOD_VEX_0F12_PREFIX_0 */ 10595 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, 10596 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, 10597 }, 10598 { 10599 /* MOD_VEX_0F13 */ 10600 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, 10601 }, 10602 { 10603 /* MOD_VEX_0F16_PREFIX_0 */ 10604 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, 10605 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, 10606 }, 10607 { 10608 /* MOD_VEX_0F17 */ 10609 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, 10610 }, 10611 { 10612 /* MOD_VEX_0F2B */ 10613 { VEX_W_TABLE (VEX_W_0F2B_M_0) }, 10614 }, 10615 { 10616 /* MOD_VEX_0F50 */ 10617 { Bad_Opcode }, 10618 { VEX_W_TABLE (VEX_W_0F50_M_0) }, 10619 }, 10620 { 10621 /* MOD_VEX_0F71_REG_2 */ 10622 { Bad_Opcode }, 10623 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, 10624 }, 10625 { 10626 /* MOD_VEX_0F71_REG_4 */ 10627 { Bad_Opcode }, 10628 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, 10629 }, 10630 { 10631 /* MOD_VEX_0F71_REG_6 */ 10632 { Bad_Opcode }, 10633 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, 10634 }, 10635 { 10636 /* MOD_VEX_0F72_REG_2 */ 10637 { Bad_Opcode }, 10638 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, 10639 }, 10640 { 10641 /* MOD_VEX_0F72_REG_4 */ 10642 { Bad_Opcode }, 10643 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, 10644 }, 10645 { 10646 /* MOD_VEX_0F72_REG_6 */ 10647 { Bad_Opcode }, 10648 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, 10649 }, 10650 { 10651 /* MOD_VEX_0F73_REG_2 */ 10652 { Bad_Opcode }, 10653 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, 10654 }, 10655 { 10656 /* MOD_VEX_0F73_REG_3 */ 10657 { Bad_Opcode }, 10658 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, 10659 }, 10660 { 10661 /* MOD_VEX_0F73_REG_6 */ 10662 { Bad_Opcode }, 10663 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, 10664 }, 10665 { 10666 /* MOD_VEX_0F73_REG_7 */ 10667 { Bad_Opcode }, 10668 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, 10669 }, 10670 { 10671 /* MOD_VEX_0FAE_REG_2 */ 10672 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, 10673 }, 10674 { 10675 /* MOD_VEX_0FAE_REG_3 */ 10676 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, 10677 }, 10678 { 10679 /* MOD_VEX_0FD7_PREFIX_2 */ 10680 { Bad_Opcode }, 10681 { VEX_LEN_TABLE (VEX_LEN_0FD7_P_2_M_1) }, 10682 }, 10683 { 10684 /* MOD_VEX_0FE7_PREFIX_2 */ 10685 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, 10686 }, 10687 { 10688 /* MOD_VEX_0FF0_PREFIX_3 */ 10689 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, 10690 }, 10691 { 10692 /* MOD_VEX_0F3818_PREFIX_2 */ 10693 { VEX_W_TABLE (VEX_W_0F3818_P_2_M_0) }, 10694 }, 10695 { 10696 /* MOD_VEX_0F3819_PREFIX_2 */ 10697 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2_M_0) }, 10698 }, 10699 { 10700 /* MOD_VEX_0F381A_PREFIX_2 */ 10701 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, 10702 }, 10703 { 10704 /* MOD_VEX_0F382A_PREFIX_2 */ 10705 { VEX_LEN_TABLE (VEX_LEN_0F382A_P_2_M_0) }, 10706 }, 10707 { 10708 /* MOD_VEX_0F382C_PREFIX_2 */ 10709 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, 10710 }, 10711 { 10712 /* MOD_VEX_0F382D_PREFIX_2 */ 10713 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, 10714 }, 10715 { 10716 /* MOD_VEX_0F382E_PREFIX_2 */ 10717 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, 10718 }, 10719 { 10720 /* MOD_VEX_0F382F_PREFIX_2 */ 10721 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, 10722 }, 10723 }; 10724 10725 static const struct dis386 rm_table[][8] = { 10726 { 10727 /* RM_0F01_REG_0 */ 10728 { Bad_Opcode }, 10729 { "vmcall", { Skip_MODRM } }, 10730 { "vmlaunch", { Skip_MODRM } }, 10731 { "vmresume", { Skip_MODRM } }, 10732 { "vmxoff", { Skip_MODRM } }, 10733 }, 10734 { 10735 /* RM_0F01_REG_1 */ 10736 { "monitor", { { OP_Monitor, 0 } } }, 10737 { "mwait", { { OP_Mwait, 0 } } }, 10738 }, 10739 { 10740 /* RM_0F01_REG_2 */ 10741 { "xgetbv", { Skip_MODRM } }, 10742 { "xsetbv", { Skip_MODRM } }, 10743 }, 10744 { 10745 /* RM_0F01_REG_3 */ 10746 { "vmrun", { Skip_MODRM } }, 10747 { "vmmcall", { Skip_MODRM } }, 10748 { "vmload", { Skip_MODRM } }, 10749 { "vmsave", { Skip_MODRM } }, 10750 { "stgi", { Skip_MODRM } }, 10751 { "clgi", { Skip_MODRM } }, 10752 { "skinit", { Skip_MODRM } }, 10753 { "invlpga", { Skip_MODRM } }, 10754 }, 10755 { 10756 /* RM_0F01_REG_7 */ 10757 { "swapgs", { Skip_MODRM } }, 10758 { "rdtscp", { Skip_MODRM } }, 10759 }, 10760 { 10761 /* RM_0FAE_REG_5 */ 10762 { "lfence", { Skip_MODRM } }, 10763 }, 10764 { 10765 /* RM_0FAE_REG_6 */ 10766 { "mfence", { Skip_MODRM } }, 10767 }, 10768 { 10769 /* RM_0FAE_REG_7 */ 10770 { "sfence", { Skip_MODRM } }, 10771 }, 10772 }; 10773 10774 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") 10775 10776 /* We use the high bit to indicate different name for the same 10777 prefix. */ 10778 #define ADDR16_PREFIX (0x67 | 0x100) 10779 #define ADDR32_PREFIX (0x67 | 0x200) 10780 #define DATA16_PREFIX (0x66 | 0x100) 10781 #define DATA32_PREFIX (0x66 | 0x200) 10782 #define REP_PREFIX (0xf3 | 0x100) 10783 10784 static int 10785 ckprefix (void) 10786 { 10787 int newrex, i, length; 10788 rex = 0; 10789 rex_ignored = 0; 10790 prefixes = 0; 10791 used_prefixes = 0; 10792 rex_used = 0; 10793 last_lock_prefix = -1; 10794 last_repz_prefix = -1; 10795 last_repnz_prefix = -1; 10796 last_data_prefix = -1; 10797 last_addr_prefix = -1; 10798 last_rex_prefix = -1; 10799 last_seg_prefix = -1; 10800 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) 10801 all_prefixes[i] = 0; 10802 i = 0; 10803 length = 0; 10804 /* The maximum instruction length is 15bytes. */ 10805 while (length < MAX_CODE_LENGTH - 1) 10806 { 10807 FETCH_DATA (the_info, codep + 1); 10808 newrex = 0; 10809 switch (*codep) 10810 { 10811 /* REX prefixes family. */ 10812 case 0x40: 10813 case 0x41: 10814 case 0x42: 10815 case 0x43: 10816 case 0x44: 10817 case 0x45: 10818 case 0x46: 10819 case 0x47: 10820 case 0x48: 10821 case 0x49: 10822 case 0x4a: 10823 case 0x4b: 10824 case 0x4c: 10825 case 0x4d: 10826 case 0x4e: 10827 case 0x4f: 10828 if (address_mode == mode_64bit) 10829 newrex = *codep; 10830 else 10831 return 1; 10832 last_rex_prefix = i; 10833 break; 10834 case 0xf3: 10835 prefixes |= PREFIX_REPZ; 10836 last_repz_prefix = i; 10837 break; 10838 case 0xf2: 10839 prefixes |= PREFIX_REPNZ; 10840 last_repnz_prefix = i; 10841 break; 10842 case 0xf0: 10843 prefixes |= PREFIX_LOCK; 10844 last_lock_prefix = i; 10845 break; 10846 case 0x2e: 10847 prefixes |= PREFIX_CS; 10848 last_seg_prefix = i; 10849 break; 10850 case 0x36: 10851 prefixes |= PREFIX_SS; 10852 last_seg_prefix = i; 10853 break; 10854 case 0x3e: 10855 prefixes |= PREFIX_DS; 10856 last_seg_prefix = i; 10857 break; 10858 case 0x26: 10859 prefixes |= PREFIX_ES; 10860 last_seg_prefix = i; 10861 break; 10862 case 0x64: 10863 prefixes |= PREFIX_FS; 10864 last_seg_prefix = i; 10865 break; 10866 case 0x65: 10867 prefixes |= PREFIX_GS; 10868 last_seg_prefix = i; 10869 break; 10870 case 0x66: 10871 prefixes |= PREFIX_DATA; 10872 last_data_prefix = i; 10873 break; 10874 case 0x67: 10875 prefixes |= PREFIX_ADDR; 10876 last_addr_prefix = i; 10877 break; 10878 case FWAIT_OPCODE: 10879 /* fwait is really an instruction. If there are prefixes 10880 before the fwait, they belong to the fwait, *not* to the 10881 following instruction. */ 10882 if (prefixes || rex) 10883 { 10884 prefixes |= PREFIX_FWAIT; 10885 codep++; 10886 return 1; 10887 } 10888 prefixes = PREFIX_FWAIT; 10889 break; 10890 default: 10891 return 1; 10892 } 10893 /* Rex is ignored when followed by another prefix. */ 10894 if (rex) 10895 { 10896 rex_used = rex; 10897 return 1; 10898 } 10899 if (*codep != FWAIT_OPCODE) 10900 all_prefixes[i++] = *codep; 10901 rex = newrex; 10902 codep++; 10903 length++; 10904 } 10905 return 0; 10906 } 10907 10908 static int 10909 seg_prefix (int pref) 10910 { 10911 switch (pref) 10912 { 10913 case 0x2e: 10914 return PREFIX_CS; 10915 case 0x36: 10916 return PREFIX_SS; 10917 case 0x3e: 10918 return PREFIX_DS; 10919 case 0x26: 10920 return PREFIX_ES; 10921 case 0x64: 10922 return PREFIX_FS; 10923 case 0x65: 10924 return PREFIX_GS; 10925 default: 10926 return 0; 10927 } 10928 } 10929 10930 /* Return the name of the prefix byte PREF, or NULL if PREF is not a 10931 prefix byte. */ 10932 10933 static const char * 10934 prefix_name (int pref, int sizeflag) 10935 { 10936 static const char *rexes [16] = 10937 { 10938 "rex", /* 0x40 */ 10939 "rex.B", /* 0x41 */ 10940 "rex.X", /* 0x42 */ 10941 "rex.XB", /* 0x43 */ 10942 "rex.R", /* 0x44 */ 10943 "rex.RB", /* 0x45 */ 10944 "rex.RX", /* 0x46 */ 10945 "rex.RXB", /* 0x47 */ 10946 "rex.W", /* 0x48 */ 10947 "rex.WB", /* 0x49 */ 10948 "rex.WX", /* 0x4a */ 10949 "rex.WXB", /* 0x4b */ 10950 "rex.WR", /* 0x4c */ 10951 "rex.WRB", /* 0x4d */ 10952 "rex.WRX", /* 0x4e */ 10953 "rex.WRXB", /* 0x4f */ 10954 }; 10955 10956 switch (pref) 10957 { 10958 /* REX prefixes family. */ 10959 case 0x40: 10960 case 0x41: 10961 case 0x42: 10962 case 0x43: 10963 case 0x44: 10964 case 0x45: 10965 case 0x46: 10966 case 0x47: 10967 case 0x48: 10968 case 0x49: 10969 case 0x4a: 10970 case 0x4b: 10971 case 0x4c: 10972 case 0x4d: 10973 case 0x4e: 10974 case 0x4f: 10975 return rexes [pref - 0x40]; 10976 case 0xf3: 10977 return "repz"; 10978 case 0xf2: 10979 return "repnz"; 10980 case 0xf0: 10981 return "lock"; 10982 case 0x2e: 10983 return "cs"; 10984 case 0x36: 10985 return "ss"; 10986 case 0x3e: 10987 return "ds"; 10988 case 0x26: 10989 return "es"; 10990 case 0x64: 10991 return "fs"; 10992 case 0x65: 10993 return "gs"; 10994 case 0x66: 10995 return (sizeflag & DFLAG) ? "data16" : "data32"; 10996 case 0x67: 10997 if (address_mode == mode_64bit) 10998 return (sizeflag & AFLAG) ? "addr32" : "addr64"; 10999 else 11000 return (sizeflag & AFLAG) ? "addr16" : "addr32"; 11001 case FWAIT_OPCODE: 11002 return "fwait"; 11003 case ADDR16_PREFIX: 11004 return "addr16"; 11005 case ADDR32_PREFIX: 11006 return "addr32"; 11007 case DATA16_PREFIX: 11008 return "data16"; 11009 case DATA32_PREFIX: 11010 return "data32"; 11011 case REP_PREFIX: 11012 return "rep"; 11013 default: 11014 return NULL; 11015 } 11016 } 11017 11018 static char op_out[MAX_OPERANDS][100]; 11019 static int op_ad, op_index[MAX_OPERANDS]; 11020 static int two_source_ops; 11021 static bfd_vma op_address[MAX_OPERANDS]; 11022 static bfd_vma op_riprel[MAX_OPERANDS]; 11023 static bfd_vma start_pc; 11024 11025 /* 11026 * On the 386's of 1988, the maximum length of an instruction is 15 bytes. 11027 * (see topic "Redundant prefixes" in the "Differences from 8086" 11028 * section of the "Virtual 8086 Mode" chapter.) 11029 * 'pc' should be the address of this instruction, it will 11030 * be used to print the target address if this is a relative jump or call 11031 * The function returns the length of this instruction in bytes. 11032 */ 11033 11034 static char intel_syntax; 11035 static char intel_mnemonic = !SYSV386_COMPAT; 11036 static char open_char; 11037 static char close_char; 11038 static char separator_char; 11039 static char scale_char; 11040 11041 /* Here for backwards compatibility. When gdb stops using 11042 print_insn_i386_att and print_insn_i386_intel these functions can 11043 disappear, and print_insn_i386 be merged into print_insn. */ 11044 int 11045 print_insn_i386_att (bfd_vma pc, disassemble_info *info) 11046 { 11047 intel_syntax = 0; 11048 11049 return print_insn (pc, info); 11050 } 11051 11052 int 11053 print_insn_i386_intel (bfd_vma pc, disassemble_info *info) 11054 { 11055 intel_syntax = 1; 11056 11057 return print_insn (pc, info); 11058 } 11059 11060 int 11061 print_insn_i386 (bfd_vma pc, disassemble_info *info) 11062 { 11063 intel_syntax = -1; 11064 11065 return print_insn (pc, info); 11066 } 11067 11068 void 11069 print_i386_disassembler_options (FILE *stream) 11070 { 11071 fprintf (stream, _("\n\ 11072 The following i386/x86-64 specific disassembler options are supported for use\n\ 11073 with the -M switch (multiple options should be separated by commas):\n")); 11074 11075 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); 11076 fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); 11077 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); 11078 fprintf (stream, _(" att Display instruction in AT&T syntax\n")); 11079 fprintf (stream, _(" intel Display instruction in Intel syntax\n")); 11080 fprintf (stream, _(" att-mnemonic\n" 11081 " Display instruction in AT&T mnemonic\n")); 11082 fprintf (stream, _(" intel-mnemonic\n" 11083 " Display instruction in Intel mnemonic\n")); 11084 fprintf (stream, _(" addr64 Assume 64bit address size\n")); 11085 fprintf (stream, _(" addr32 Assume 32bit address size\n")); 11086 fprintf (stream, _(" addr16 Assume 16bit address size\n")); 11087 fprintf (stream, _(" data32 Assume 32bit data size\n")); 11088 fprintf (stream, _(" data16 Assume 16bit data size\n")); 11089 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); 11090 } 11091 11092 /* Bad opcode. */ 11093 static const struct dis386 bad_opcode = { "(bad)", { XX } }; 11094 11095 /* Get a pointer to struct dis386 with a valid name. */ 11096 11097 static const struct dis386 * 11098 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) 11099 { 11100 int vindex, vex_table_index; 11101 11102 if (dp->name != NULL) 11103 return dp; 11104 11105 switch (dp->op[0].bytemode) 11106 { 11107 case USE_REG_TABLE: 11108 dp = ®_table[dp->op[1].bytemode][modrm.reg]; 11109 break; 11110 11111 case USE_MOD_TABLE: 11112 vindex = modrm.mod == 0x3 ? 1 : 0; 11113 dp = &mod_table[dp->op[1].bytemode][vindex]; 11114 break; 11115 11116 case USE_RM_TABLE: 11117 dp = &rm_table[dp->op[1].bytemode][modrm.rm]; 11118 break; 11119 11120 case USE_PREFIX_TABLE: 11121 if (need_vex) 11122 { 11123 /* The prefix in VEX is implicit. */ 11124 switch (vex.prefix) 11125 { 11126 case 0: 11127 vindex = 0; 11128 break; 11129 case REPE_PREFIX_OPCODE: 11130 vindex = 1; 11131 break; 11132 case DATA_PREFIX_OPCODE: 11133 vindex = 2; 11134 break; 11135 case REPNE_PREFIX_OPCODE: 11136 vindex = 3; 11137 break; 11138 default: 11139 abort (); 11140 break; 11141 } 11142 } 11143 else 11144 { 11145 vindex = 0; 11146 used_prefixes |= (prefixes & PREFIX_REPZ); 11147 if (prefixes & PREFIX_REPZ) 11148 { 11149 vindex = 1; 11150 all_prefixes[last_repz_prefix] = 0; 11151 } 11152 else 11153 { 11154 /* We should check PREFIX_REPNZ and PREFIX_REPZ before 11155 PREFIX_DATA. */ 11156 used_prefixes |= (prefixes & PREFIX_REPNZ); 11157 if (prefixes & PREFIX_REPNZ) 11158 { 11159 vindex = 3; 11160 all_prefixes[last_repnz_prefix] = 0; 11161 } 11162 else 11163 { 11164 used_prefixes |= (prefixes & PREFIX_DATA); 11165 if (prefixes & PREFIX_DATA) 11166 { 11167 vindex = 2; 11168 all_prefixes[last_data_prefix] = 0; 11169 } 11170 } 11171 } 11172 } 11173 dp = &prefix_table[dp->op[1].bytemode][vindex]; 11174 break; 11175 11176 case USE_X86_64_TABLE: 11177 vindex = address_mode == mode_64bit ? 1 : 0; 11178 dp = &x86_64_table[dp->op[1].bytemode][vindex]; 11179 break; 11180 11181 case USE_3BYTE_TABLE: 11182 FETCH_DATA (info, codep + 2); 11183 vindex = *codep++; 11184 dp = &three_byte_table[dp->op[1].bytemode][vindex]; 11185 modrm.mod = (*codep >> 6) & 3; 11186 modrm.reg = (*codep >> 3) & 7; 11187 modrm.rm = *codep & 7; 11188 break; 11189 11190 case USE_VEX_LEN_TABLE: 11191 if (!need_vex) 11192 abort (); 11193 11194 switch (vex.length) 11195 { 11196 case 128: 11197 vindex = 0; 11198 break; 11199 case 256: 11200 vindex = 1; 11201 break; 11202 default: 11203 abort (); 11204 break; 11205 } 11206 11207 dp = &vex_len_table[dp->op[1].bytemode][vindex]; 11208 break; 11209 11210 case USE_XOP_8F_TABLE: 11211 FETCH_DATA (info, codep + 3); 11212 /* All bits in the REX prefix are ignored. */ 11213 rex_ignored = rex; 11214 rex = ~(*codep >> 5) & 0x7; 11215 11216 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ 11217 switch ((*codep & 0x1f)) 11218 { 11219 default: 11220 dp = &bad_opcode; 11221 return dp; 11222 case 0x8: 11223 vex_table_index = XOP_08; 11224 break; 11225 case 0x9: 11226 vex_table_index = XOP_09; 11227 break; 11228 case 0xa: 11229 vex_table_index = XOP_0A; 11230 break; 11231 } 11232 codep++; 11233 vex.w = *codep & 0x80; 11234 if (vex.w && address_mode == mode_64bit) 11235 rex |= REX_W; 11236 11237 vex.register_specifier = (~(*codep >> 3)) & 0xf; 11238 if (address_mode != mode_64bit 11239 && vex.register_specifier > 0x7) 11240 { 11241 dp = &bad_opcode; 11242 return dp; 11243 } 11244 11245 vex.length = (*codep & 0x4) ? 256 : 128; 11246 switch ((*codep & 0x3)) 11247 { 11248 case 0: 11249 vex.prefix = 0; 11250 break; 11251 case 1: 11252 vex.prefix = DATA_PREFIX_OPCODE; 11253 break; 11254 case 2: 11255 vex.prefix = REPE_PREFIX_OPCODE; 11256 break; 11257 case 3: 11258 vex.prefix = REPNE_PREFIX_OPCODE; 11259 break; 11260 } 11261 need_vex = 1; 11262 need_vex_reg = 1; 11263 codep++; 11264 vindex = *codep++; 11265 dp = &xop_table[vex_table_index][vindex]; 11266 11267 FETCH_DATA (info, codep + 1); 11268 modrm.mod = (*codep >> 6) & 3; 11269 modrm.reg = (*codep >> 3) & 7; 11270 modrm.rm = *codep & 7; 11271 break; 11272 11273 case USE_VEX_C4_TABLE: 11274 FETCH_DATA (info, codep + 3); 11275 /* All bits in the REX prefix are ignored. */ 11276 rex_ignored = rex; 11277 rex = ~(*codep >> 5) & 0x7; 11278 switch ((*codep & 0x1f)) 11279 { 11280 default: 11281 dp = &bad_opcode; 11282 return dp; 11283 case 0x1: 11284 vex_table_index = VEX_0F; 11285 break; 11286 case 0x2: 11287 vex_table_index = VEX_0F38; 11288 break; 11289 case 0x3: 11290 vex_table_index = VEX_0F3A; 11291 break; 11292 } 11293 codep++; 11294 vex.w = *codep & 0x80; 11295 if (vex.w && address_mode == mode_64bit) 11296 rex |= REX_W; 11297 11298 vex.register_specifier = (~(*codep >> 3)) & 0xf; 11299 if (address_mode != mode_64bit 11300 && vex.register_specifier > 0x7) 11301 { 11302 dp = &bad_opcode; 11303 return dp; 11304 } 11305 11306 vex.length = (*codep & 0x4) ? 256 : 128; 11307 switch ((*codep & 0x3)) 11308 { 11309 case 0: 11310 vex.prefix = 0; 11311 break; 11312 case 1: 11313 vex.prefix = DATA_PREFIX_OPCODE; 11314 break; 11315 case 2: 11316 vex.prefix = REPE_PREFIX_OPCODE; 11317 break; 11318 case 3: 11319 vex.prefix = REPNE_PREFIX_OPCODE; 11320 break; 11321 } 11322 need_vex = 1; 11323 need_vex_reg = 1; 11324 codep++; 11325 vindex = *codep++; 11326 dp = &vex_table[vex_table_index][vindex]; 11327 /* There is no MODRM byte for VEX [82|77]. */ 11328 if (vindex != 0x77 && vindex != 0x82) 11329 { 11330 FETCH_DATA (info, codep + 1); 11331 modrm.mod = (*codep >> 6) & 3; 11332 modrm.reg = (*codep >> 3) & 7; 11333 modrm.rm = *codep & 7; 11334 } 11335 break; 11336 11337 case USE_VEX_C5_TABLE: 11338 FETCH_DATA (info, codep + 2); 11339 /* All bits in the REX prefix are ignored. */ 11340 rex_ignored = rex; 11341 rex = (*codep & 0x80) ? 0 : REX_R; 11342 11343 vex.register_specifier = (~(*codep >> 3)) & 0xf; 11344 if (address_mode != mode_64bit 11345 && vex.register_specifier > 0x7) 11346 { 11347 dp = &bad_opcode; 11348 return dp; 11349 } 11350 11351 vex.w = 0; 11352 11353 vex.length = (*codep & 0x4) ? 256 : 128; 11354 switch ((*codep & 0x3)) 11355 { 11356 case 0: 11357 vex.prefix = 0; 11358 break; 11359 case 1: 11360 vex.prefix = DATA_PREFIX_OPCODE; 11361 break; 11362 case 2: 11363 vex.prefix = REPE_PREFIX_OPCODE; 11364 break; 11365 case 3: 11366 vex.prefix = REPNE_PREFIX_OPCODE; 11367 break; 11368 } 11369 need_vex = 1; 11370 need_vex_reg = 1; 11371 codep++; 11372 vindex = *codep++; 11373 dp = &vex_table[dp->op[1].bytemode][vindex]; 11374 /* There is no MODRM byte for VEX [82|77]. */ 11375 if (vindex != 0x77 && vindex != 0x82) 11376 { 11377 FETCH_DATA (info, codep + 1); 11378 modrm.mod = (*codep >> 6) & 3; 11379 modrm.reg = (*codep >> 3) & 7; 11380 modrm.rm = *codep & 7; 11381 } 11382 break; 11383 11384 case USE_VEX_W_TABLE: 11385 if (!need_vex) 11386 abort (); 11387 11388 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; 11389 break; 11390 11391 case 0: 11392 dp = &bad_opcode; 11393 break; 11394 11395 default: 11396 abort (); 11397 } 11398 11399 if (dp->name != NULL) 11400 return dp; 11401 else 11402 return get_valid_dis386 (dp, info); 11403 } 11404 11405 static void 11406 get_sib (disassemble_info *info) 11407 { 11408 /* If modrm.mod == 3, operand must be register. */ 11409 if (need_modrm 11410 && address_mode != mode_16bit 11411 && modrm.mod != 3 11412 && modrm.rm == 4) 11413 { 11414 FETCH_DATA (info, codep + 2); 11415 sib.index = (codep [1] >> 3) & 7; 11416 sib.scale = (codep [1] >> 6) & 3; 11417 sib.base = codep [1] & 7; 11418 } 11419 } 11420 11421 static int 11422 print_insn (bfd_vma pc, disassemble_info *info) 11423 { 11424 const struct dis386 *dp; 11425 int i; 11426 char *op_txt[MAX_OPERANDS]; 11427 int needcomma; 11428 int sizeflag; 11429 const char *p; 11430 struct dis_private priv; 11431 int prefix_length; 11432 int default_prefixes; 11433 11434 if (info->mach == bfd_mach_x86_64_intel_syntax 11435 || info->mach == bfd_mach_x86_64 11436 || info->mach == bfd_mach_x64_32_intel_syntax 11437 || info->mach == bfd_mach_x64_32 11438 || info->mach == bfd_mach_l1om 11439 || info->mach == bfd_mach_l1om_intel_syntax) 11440 address_mode = mode_64bit; 11441 else 11442 address_mode = mode_32bit; 11443 11444 if (intel_syntax == (char) -1) 11445 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax 11446 || info->mach == bfd_mach_x86_64_intel_syntax 11447 || info->mach == bfd_mach_x64_32_intel_syntax 11448 || info->mach == bfd_mach_l1om_intel_syntax); 11449 11450 if (info->mach == bfd_mach_i386_i386 11451 || info->mach == bfd_mach_x86_64 11452 || info->mach == bfd_mach_x64_32 11453 || info->mach == bfd_mach_l1om 11454 || info->mach == bfd_mach_i386_i386_intel_syntax 11455 || info->mach == bfd_mach_x86_64_intel_syntax 11456 || info->mach == bfd_mach_x64_32_intel_syntax 11457 || info->mach == bfd_mach_l1om_intel_syntax) 11458 priv.orig_sizeflag = AFLAG | DFLAG; 11459 else if (info->mach == bfd_mach_i386_i8086) 11460 priv.orig_sizeflag = 0; 11461 else 11462 abort (); 11463 11464 for (p = info->disassembler_options; p != NULL; ) 11465 { 11466 if (CONST_STRNEQ (p, "x86-64")) 11467 { 11468 address_mode = mode_64bit; 11469 priv.orig_sizeflag = AFLAG | DFLAG; 11470 } 11471 else if (CONST_STRNEQ (p, "i386")) 11472 { 11473 address_mode = mode_32bit; 11474 priv.orig_sizeflag = AFLAG | DFLAG; 11475 } 11476 else if (CONST_STRNEQ (p, "i8086")) 11477 { 11478 address_mode = mode_16bit; 11479 priv.orig_sizeflag = 0; 11480 } 11481 else if (CONST_STRNEQ (p, "intel")) 11482 { 11483 intel_syntax = 1; 11484 if (CONST_STRNEQ (p + 5, "-mnemonic")) 11485 intel_mnemonic = 1; 11486 } 11487 else if (CONST_STRNEQ (p, "att")) 11488 { 11489 intel_syntax = 0; 11490 if (CONST_STRNEQ (p + 3, "-mnemonic")) 11491 intel_mnemonic = 0; 11492 } 11493 else if (CONST_STRNEQ (p, "addr")) 11494 { 11495 if (address_mode == mode_64bit) 11496 { 11497 if (p[4] == '3' && p[5] == '2') 11498 priv.orig_sizeflag &= ~AFLAG; 11499 else if (p[4] == '6' && p[5] == '4') 11500 priv.orig_sizeflag |= AFLAG; 11501 } 11502 else 11503 { 11504 if (p[4] == '1' && p[5] == '6') 11505 priv.orig_sizeflag &= ~AFLAG; 11506 else if (p[4] == '3' && p[5] == '2') 11507 priv.orig_sizeflag |= AFLAG; 11508 } 11509 } 11510 else if (CONST_STRNEQ (p, "data")) 11511 { 11512 if (p[4] == '1' && p[5] == '6') 11513 priv.orig_sizeflag &= ~DFLAG; 11514 else if (p[4] == '3' && p[5] == '2') 11515 priv.orig_sizeflag |= DFLAG; 11516 } 11517 else if (CONST_STRNEQ (p, "suffix")) 11518 priv.orig_sizeflag |= SUFFIX_ALWAYS; 11519 11520 p = strchr (p, ','); 11521 if (p != NULL) 11522 p++; 11523 } 11524 11525 if (intel_syntax) 11526 { 11527 names64 = intel_names64; 11528 names32 = intel_names32; 11529 names16 = intel_names16; 11530 names8 = intel_names8; 11531 names8rex = intel_names8rex; 11532 names_seg = intel_names_seg; 11533 names_mm = intel_names_mm; 11534 names_xmm = intel_names_xmm; 11535 names_ymm = intel_names_ymm; 11536 index64 = intel_index64; 11537 index32 = intel_index32; 11538 index16 = intel_index16; 11539 open_char = '['; 11540 close_char = ']'; 11541 separator_char = '+'; 11542 scale_char = '*'; 11543 } 11544 else 11545 { 11546 names64 = att_names64; 11547 names32 = att_names32; 11548 names16 = att_names16; 11549 names8 = att_names8; 11550 names8rex = att_names8rex; 11551 names_seg = att_names_seg; 11552 names_mm = att_names_mm; 11553 names_xmm = att_names_xmm; 11554 names_ymm = att_names_ymm; 11555 index64 = att_index64; 11556 index32 = att_index32; 11557 index16 = att_index16; 11558 open_char = '('; 11559 close_char = ')'; 11560 separator_char = ','; 11561 scale_char = ','; 11562 } 11563 11564 /* The output looks better if we put 7 bytes on a line, since that 11565 puts most long word instructions on a single line. Use 8 bytes 11566 for Intel L1OM. */ 11567 if (info->mach == bfd_mach_l1om 11568 || info->mach == bfd_mach_l1om_intel_syntax) 11569 info->bytes_per_line = 8; 11570 else 11571 info->bytes_per_line = 7; 11572 11573 info->private_data = &priv; 11574 priv.max_fetched = priv.the_buffer; 11575 priv.insn_start = pc; 11576 11577 obuf[0] = 0; 11578 for (i = 0; i < MAX_OPERANDS; ++i) 11579 { 11580 op_out[i][0] = 0; 11581 op_index[i] = -1; 11582 } 11583 11584 the_info = info; 11585 start_pc = pc; 11586 start_codep = priv.the_buffer; 11587 codep = priv.the_buffer; 11588 11589 if (setjmp (priv.bailout) != 0) 11590 { 11591 const char *name; 11592 11593 /* Getting here means we tried for data but didn't get it. That 11594 means we have an incomplete instruction of some sort. Just 11595 print the first byte as a prefix or a .byte pseudo-op. */ 11596 if (codep > priv.the_buffer) 11597 { 11598 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); 11599 if (name != NULL) 11600 (*info->fprintf_func) (info->stream, "%s", name); 11601 else 11602 { 11603 /* Just print the first byte as a .byte instruction. */ 11604 (*info->fprintf_func) (info->stream, ".byte 0x%x", 11605 (unsigned int) priv.the_buffer[0]); 11606 } 11607 11608 return 1; 11609 } 11610 11611 return -1; 11612 } 11613 11614 obufp = obuf; 11615 sizeflag = priv.orig_sizeflag; 11616 11617 if (!ckprefix () || rex_used) 11618 { 11619 /* Too many prefixes or unused REX prefixes. */ 11620 for (i = 0; 11621 all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes); 11622 i++) 11623 (*info->fprintf_func) (info->stream, "%s", 11624 prefix_name (all_prefixes[i], sizeflag)); 11625 return 1; 11626 } 11627 11628 insn_codep = codep; 11629 11630 FETCH_DATA (info, codep + 1); 11631 two_source_ops = (*codep == 0x62) || (*codep == 0xc8); 11632 11633 if (((prefixes & PREFIX_FWAIT) 11634 && ((*codep < 0xd8) || (*codep > 0xdf)))) 11635 { 11636 (*info->fprintf_func) (info->stream, "fwait"); 11637 return 1; 11638 } 11639 11640 if (*codep == 0x0f) 11641 { 11642 unsigned char threebyte; 11643 FETCH_DATA (info, codep + 2); 11644 threebyte = *++codep; 11645 dp = &dis386_twobyte[threebyte]; 11646 need_modrm = twobyte_has_modrm[*codep]; 11647 codep++; 11648 } 11649 else 11650 { 11651 dp = &dis386[*codep]; 11652 need_modrm = onebyte_has_modrm[*codep]; 11653 codep++; 11654 } 11655 11656 if ((prefixes & PREFIX_REPZ)) 11657 used_prefixes |= PREFIX_REPZ; 11658 if ((prefixes & PREFIX_REPNZ)) 11659 used_prefixes |= PREFIX_REPNZ; 11660 if ((prefixes & PREFIX_LOCK)) 11661 used_prefixes |= PREFIX_LOCK; 11662 11663 default_prefixes = 0; 11664 if (prefixes & PREFIX_ADDR) 11665 { 11666 sizeflag ^= AFLAG; 11667 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) 11668 { 11669 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 11670 all_prefixes[last_addr_prefix] = ADDR32_PREFIX; 11671 else 11672 all_prefixes[last_addr_prefix] = ADDR16_PREFIX; 11673 default_prefixes |= PREFIX_ADDR; 11674 } 11675 } 11676 11677 if ((prefixes & PREFIX_DATA)) 11678 { 11679 sizeflag ^= DFLAG; 11680 if (dp->op[2].bytemode == cond_jump_mode 11681 && dp->op[0].bytemode == v_mode 11682 && !intel_syntax) 11683 { 11684 if (sizeflag & DFLAG) 11685 all_prefixes[last_data_prefix] = DATA32_PREFIX; 11686 else 11687 all_prefixes[last_data_prefix] = DATA16_PREFIX; 11688 default_prefixes |= PREFIX_DATA; 11689 } 11690 else if (rex & REX_W) 11691 { 11692 /* REX_W will override PREFIX_DATA. */ 11693 default_prefixes |= PREFIX_DATA; 11694 } 11695 } 11696 11697 if (need_modrm) 11698 { 11699 FETCH_DATA (info, codep + 1); 11700 modrm.mod = (*codep >> 6) & 3; 11701 modrm.reg = (*codep >> 3) & 7; 11702 modrm.rm = *codep & 7; 11703 } 11704 11705 need_vex = 0; 11706 need_vex_reg = 0; 11707 vex_w_done = 0; 11708 11709 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) 11710 { 11711 get_sib (info); 11712 dofloat (sizeflag); 11713 } 11714 else 11715 { 11716 dp = get_valid_dis386 (dp, info); 11717 if (dp != NULL && putop (dp->name, sizeflag) == 0) 11718 { 11719 get_sib (info); 11720 for (i = 0; i < MAX_OPERANDS; ++i) 11721 { 11722 obufp = op_out[i]; 11723 op_ad = MAX_OPERANDS - 1 - i; 11724 if (dp->op[i].rtn) 11725 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); 11726 } 11727 } 11728 } 11729 11730 /* See if any prefixes were not used. If so, print the first one 11731 separately. If we don't do this, we'll wind up printing an 11732 instruction stream which does not precisely correspond to the 11733 bytes we are disassembling. */ 11734 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) 11735 { 11736 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) 11737 if (all_prefixes[i]) 11738 { 11739 const char *name; 11740 name = prefix_name (all_prefixes[i], priv.orig_sizeflag); 11741 if (name == NULL) 11742 name = INTERNAL_DISASSEMBLER_ERROR; 11743 (*info->fprintf_func) (info->stream, "%s", name); 11744 return 1; 11745 } 11746 } 11747 11748 /* Check if the REX prefix is used. */ 11749 if (rex_ignored == 0 && (rex ^ rex_used) == 0) 11750 all_prefixes[last_rex_prefix] = 0; 11751 11752 /* Check if the SEG prefix is used. */ 11753 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES 11754 | PREFIX_FS | PREFIX_GS)) != 0 11755 && (used_prefixes 11756 & seg_prefix (all_prefixes[last_seg_prefix])) != 0) 11757 all_prefixes[last_seg_prefix] = 0; 11758 11759 /* Check if the ADDR prefix is used. */ 11760 if ((prefixes & PREFIX_ADDR) != 0 11761 && (used_prefixes & PREFIX_ADDR) != 0) 11762 all_prefixes[last_addr_prefix] = 0; 11763 11764 /* Check if the DATA prefix is used. */ 11765 if ((prefixes & PREFIX_DATA) != 0 11766 && (used_prefixes & PREFIX_DATA) != 0) 11767 all_prefixes[last_data_prefix] = 0; 11768 11769 prefix_length = 0; 11770 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) 11771 if (all_prefixes[i]) 11772 { 11773 const char *name; 11774 name = prefix_name (all_prefixes[i], sizeflag); 11775 if (name == NULL) 11776 abort (); 11777 prefix_length += strlen (name) + 1; 11778 (*info->fprintf_func) (info->stream, "%s ", name); 11779 } 11780 11781 /* Check maximum code length. */ 11782 if ((codep - start_codep) > MAX_CODE_LENGTH) 11783 { 11784 (*info->fprintf_func) (info->stream, "(bad)"); 11785 return MAX_CODE_LENGTH; 11786 } 11787 11788 obufp = mnemonicendp; 11789 for (i = strlen (obuf) + prefix_length; i < 6; i++) 11790 oappend (" "); 11791 oappend (" "); 11792 (*info->fprintf_func) (info->stream, "%s", obuf); 11793 11794 /* The enter and bound instructions are printed with operands in the same 11795 order as the intel book; everything else is printed in reverse order. */ 11796 if (intel_syntax || two_source_ops) 11797 { 11798 bfd_vma riprel; 11799 11800 for (i = 0; i < MAX_OPERANDS; ++i) 11801 op_txt[i] = op_out[i]; 11802 11803 for (i = 0; i < (MAX_OPERANDS >> 1); ++i) 11804 { 11805 op_ad = op_index[i]; 11806 op_index[i] = op_index[MAX_OPERANDS - 1 - i]; 11807 op_index[MAX_OPERANDS - 1 - i] = op_ad; 11808 riprel = op_riprel[i]; 11809 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; 11810 op_riprel[MAX_OPERANDS - 1 - i] = riprel; 11811 } 11812 } 11813 else 11814 { 11815 for (i = 0; i < MAX_OPERANDS; ++i) 11816 op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; 11817 } 11818 11819 needcomma = 0; 11820 for (i = 0; i < MAX_OPERANDS; ++i) 11821 if (*op_txt[i]) 11822 { 11823 if (needcomma) 11824 (*info->fprintf_func) (info->stream, ","); 11825 if (op_index[i] != -1 && !op_riprel[i]) 11826 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); 11827 else 11828 (*info->fprintf_func) (info->stream, "%s", op_txt[i]); 11829 needcomma = 1; 11830 } 11831 11832 for (i = 0; i < MAX_OPERANDS; i++) 11833 if (op_index[i] != -1 && op_riprel[i]) 11834 { 11835 (*info->fprintf_func) (info->stream, " # "); 11836 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep 11837 + op_address[op_index[i]]), info); 11838 break; 11839 } 11840 return codep - priv.the_buffer; 11841 } 11842 11843 static const char *float_mem[] = { 11844 /* d8 */ 11845 "fadd{s|}", 11846 "fmul{s|}", 11847 "fcom{s|}", 11848 "fcomp{s|}", 11849 "fsub{s|}", 11850 "fsubr{s|}", 11851 "fdiv{s|}", 11852 "fdivr{s|}", 11853 /* d9 */ 11854 "fld{s|}", 11855 "(bad)", 11856 "fst{s|}", 11857 "fstp{s|}", 11858 "fldenvIC", 11859 "fldcw", 11860 "fNstenvIC", 11861 "fNstcw", 11862 /* da */ 11863 "fiadd{l|}", 11864 "fimul{l|}", 11865 "ficom{l|}", 11866 "ficomp{l|}", 11867 "fisub{l|}", 11868 "fisubr{l|}", 11869 "fidiv{l|}", 11870 "fidivr{l|}", 11871 /* db */ 11872 "fild{l|}", 11873 "fisttp{l|}", 11874 "fist{l|}", 11875 "fistp{l|}", 11876 "(bad)", 11877 "fld{t||t|}", 11878 "(bad)", 11879 "fstp{t||t|}", 11880 /* dc */ 11881 "fadd{l|}", 11882 "fmul{l|}", 11883 "fcom{l|}", 11884 "fcomp{l|}", 11885 "fsub{l|}", 11886 "fsubr{l|}", 11887 "fdiv{l|}", 11888 "fdivr{l|}", 11889 /* dd */ 11890 "fld{l|}", 11891 "fisttp{ll|}", 11892 "fst{l||}", 11893 "fstp{l|}", 11894 "frstorIC", 11895 "(bad)", 11896 "fNsaveIC", 11897 "fNstsw", 11898 /* de */ 11899 "fiadd", 11900 "fimul", 11901 "ficom", 11902 "ficomp", 11903 "fisub", 11904 "fisubr", 11905 "fidiv", 11906 "fidivr", 11907 /* df */ 11908 "fild", 11909 "fisttp", 11910 "fist", 11911 "fistp", 11912 "fbld", 11913 "fild{ll|}", 11914 "fbstp", 11915 "fistp{ll|}", 11916 }; 11917 11918 static const unsigned char float_mem_mode[] = { 11919 /* d8 */ 11920 d_mode, 11921 d_mode, 11922 d_mode, 11923 d_mode, 11924 d_mode, 11925 d_mode, 11926 d_mode, 11927 d_mode, 11928 /* d9 */ 11929 d_mode, 11930 0, 11931 d_mode, 11932 d_mode, 11933 0, 11934 w_mode, 11935 0, 11936 w_mode, 11937 /* da */ 11938 d_mode, 11939 d_mode, 11940 d_mode, 11941 d_mode, 11942 d_mode, 11943 d_mode, 11944 d_mode, 11945 d_mode, 11946 /* db */ 11947 d_mode, 11948 d_mode, 11949 d_mode, 11950 d_mode, 11951 0, 11952 t_mode, 11953 0, 11954 t_mode, 11955 /* dc */ 11956 q_mode, 11957 q_mode, 11958 q_mode, 11959 q_mode, 11960 q_mode, 11961 q_mode, 11962 q_mode, 11963 q_mode, 11964 /* dd */ 11965 q_mode, 11966 q_mode, 11967 q_mode, 11968 q_mode, 11969 0, 11970 0, 11971 0, 11972 w_mode, 11973 /* de */ 11974 w_mode, 11975 w_mode, 11976 w_mode, 11977 w_mode, 11978 w_mode, 11979 w_mode, 11980 w_mode, 11981 w_mode, 11982 /* df */ 11983 w_mode, 11984 w_mode, 11985 w_mode, 11986 w_mode, 11987 t_mode, 11988 q_mode, 11989 t_mode, 11990 q_mode 11991 }; 11992 11993 #define ST { OP_ST, 0 } 11994 #define STi { OP_STi, 0 } 11995 11996 #define FGRPd9_2 NULL, { { NULL, 0 } } 11997 #define FGRPd9_4 NULL, { { NULL, 1 } } 11998 #define FGRPd9_5 NULL, { { NULL, 2 } } 11999 #define FGRPd9_6 NULL, { { NULL, 3 } } 12000 #define FGRPd9_7 NULL, { { NULL, 4 } } 12001 #define FGRPda_5 NULL, { { NULL, 5 } } 12002 #define FGRPdb_4 NULL, { { NULL, 6 } } 12003 #define FGRPde_3 NULL, { { NULL, 7 } } 12004 #define FGRPdf_4 NULL, { { NULL, 8 } } 12005 12006 static const struct dis386 float_reg[][8] = { 12007 /* d8 */ 12008 { 12009 { "fadd", { ST, STi } }, 12010 { "fmul", { ST, STi } }, 12011 { "fcom", { STi } }, 12012 { "fcomp", { STi } }, 12013 { "fsub", { ST, STi } }, 12014 { "fsubr", { ST, STi } }, 12015 { "fdiv", { ST, STi } }, 12016 { "fdivr", { ST, STi } }, 12017 }, 12018 /* d9 */ 12019 { 12020 { "fld", { STi } }, 12021 { "fxch", { STi } }, 12022 { FGRPd9_2 }, 12023 { Bad_Opcode }, 12024 { FGRPd9_4 }, 12025 { FGRPd9_5 }, 12026 { FGRPd9_6 }, 12027 { FGRPd9_7 }, 12028 }, 12029 /* da */ 12030 { 12031 { "fcmovb", { ST, STi } }, 12032 { "fcmove", { ST, STi } }, 12033 { "fcmovbe",{ ST, STi } }, 12034 { "fcmovu", { ST, STi } }, 12035 { Bad_Opcode }, 12036 { FGRPda_5 }, 12037 { Bad_Opcode }, 12038 { Bad_Opcode }, 12039 }, 12040 /* db */ 12041 { 12042 { "fcmovnb",{ ST, STi } }, 12043 { "fcmovne",{ ST, STi } }, 12044 { "fcmovnbe",{ ST, STi } }, 12045 { "fcmovnu",{ ST, STi } }, 12046 { FGRPdb_4 }, 12047 { "fucomi", { ST, STi } }, 12048 { "fcomi", { ST, STi } }, 12049 { Bad_Opcode }, 12050 }, 12051 /* dc */ 12052 { 12053 { "fadd", { STi, ST } }, 12054 { "fmul", { STi, ST } }, 12055 { Bad_Opcode }, 12056 { Bad_Opcode }, 12057 { "fsub!M", { STi, ST } }, 12058 { "fsubM", { STi, ST } }, 12059 { "fdiv!M", { STi, ST } }, 12060 { "fdivM", { STi, ST } }, 12061 }, 12062 /* dd */ 12063 { 12064 { "ffree", { STi } }, 12065 { Bad_Opcode }, 12066 { "fst", { STi } }, 12067 { "fstp", { STi } }, 12068 { "fucom", { STi } }, 12069 { "fucomp", { STi } }, 12070 { Bad_Opcode }, 12071 { Bad_Opcode }, 12072 }, 12073 /* de */ 12074 { 12075 { "faddp", { STi, ST } }, 12076 { "fmulp", { STi, ST } }, 12077 { Bad_Opcode }, 12078 { FGRPde_3 }, 12079 { "fsub!Mp", { STi, ST } }, 12080 { "fsubMp", { STi, ST } }, 12081 { "fdiv!Mp", { STi, ST } }, 12082 { "fdivMp", { STi, ST } }, 12083 }, 12084 /* df */ 12085 { 12086 { "ffreep", { STi } }, 12087 { Bad_Opcode }, 12088 { Bad_Opcode }, 12089 { Bad_Opcode }, 12090 { FGRPdf_4 }, 12091 { "fucomip", { ST, STi } }, 12092 { "fcomip", { ST, STi } }, 12093 { Bad_Opcode }, 12094 }, 12095 }; 12096 12097 static char *fgrps[][8] = { 12098 /* d9_2 0 */ 12099 { 12100 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 12101 }, 12102 12103 /* d9_4 1 */ 12104 { 12105 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", 12106 }, 12107 12108 /* d9_5 2 */ 12109 { 12110 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", 12111 }, 12112 12113 /* d9_6 3 */ 12114 { 12115 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", 12116 }, 12117 12118 /* d9_7 4 */ 12119 { 12120 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", 12121 }, 12122 12123 /* da_5 5 */ 12124 { 12125 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 12126 }, 12127 12128 /* db_4 6 */ 12129 { 12130 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", 12131 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", 12132 }, 12133 12134 /* de_3 7 */ 12135 { 12136 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 12137 }, 12138 12139 /* df_4 8 */ 12140 { 12141 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", 12142 }, 12143 }; 12144 12145 static void 12146 swap_operand (void) 12147 { 12148 mnemonicendp[0] = '.'; 12149 mnemonicendp[1] = 's'; 12150 mnemonicendp += 2; 12151 } 12152 12153 static void 12154 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, 12155 int sizeflag ATTRIBUTE_UNUSED) 12156 { 12157 /* Skip mod/rm byte. */ 12158 MODRM_CHECK; 12159 codep++; 12160 } 12161 12162 static void 12163 dofloat (int sizeflag) 12164 { 12165 const struct dis386 *dp; 12166 unsigned char floatop; 12167 12168 floatop = codep[-1]; 12169 12170 if (modrm.mod != 3) 12171 { 12172 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; 12173 12174 putop (float_mem[fp_indx], sizeflag); 12175 obufp = op_out[0]; 12176 op_ad = 2; 12177 OP_E (float_mem_mode[fp_indx], sizeflag); 12178 return; 12179 } 12180 /* Skip mod/rm byte. */ 12181 MODRM_CHECK; 12182 codep++; 12183 12184 dp = &float_reg[floatop - 0xd8][modrm.reg]; 12185 if (dp->name == NULL) 12186 { 12187 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); 12188 12189 /* Instruction fnstsw is only one with strange arg. */ 12190 if (floatop == 0xdf && codep[-1] == 0xe0) 12191 strcpy (op_out[0], names16[0]); 12192 } 12193 else 12194 { 12195 putop (dp->name, sizeflag); 12196 12197 obufp = op_out[0]; 12198 op_ad = 2; 12199 if (dp->op[0].rtn) 12200 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); 12201 12202 obufp = op_out[1]; 12203 op_ad = 1; 12204 if (dp->op[1].rtn) 12205 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); 12206 } 12207 } 12208 12209 static void 12210 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 12211 { 12212 oappend ("%st" + intel_syntax); 12213 } 12214 12215 static void 12216 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 12217 { 12218 sprintf (scratchbuf, "%%st(%d)", modrm.rm); 12219 oappend (scratchbuf + intel_syntax); 12220 } 12221 12222 /* Capital letters in template are macros. */ 12223 static int 12224 putop (const char *in_template, int sizeflag) 12225 { 12226 const char *p; 12227 int alt = 0; 12228 int cond = 1; 12229 unsigned int l = 0, len = 1; 12230 char last[4]; 12231 12232 #define SAVE_LAST(c) \ 12233 if (l < len && l < sizeof (last)) \ 12234 last[l++] = c; \ 12235 else \ 12236 abort (); 12237 12238 for (p = in_template; *p; p++) 12239 { 12240 switch (*p) 12241 { 12242 default: 12243 *obufp++ = *p; 12244 break; 12245 case '%': 12246 len++; 12247 break; 12248 case '!': 12249 cond = 0; 12250 break; 12251 case '{': 12252 alt = 0; 12253 if (intel_syntax) 12254 { 12255 while (*++p != '|') 12256 if (*p == '}' || *p == '\0') 12257 abort (); 12258 } 12259 /* Fall through. */ 12260 case 'I': 12261 alt = 1; 12262 continue; 12263 case '|': 12264 while (*++p != '}') 12265 { 12266 if (*p == '\0') 12267 abort (); 12268 } 12269 break; 12270 case '}': 12271 break; 12272 case 'A': 12273 if (intel_syntax) 12274 break; 12275 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) 12276 *obufp++ = 'b'; 12277 break; 12278 case 'B': 12279 if (l == 0 && len == 1) 12280 { 12281 case_B: 12282 if (intel_syntax) 12283 break; 12284 if (sizeflag & SUFFIX_ALWAYS) 12285 *obufp++ = 'b'; 12286 } 12287 else 12288 { 12289 if (l != 1 12290 || len != 2 12291 || last[0] != 'L') 12292 { 12293 SAVE_LAST (*p); 12294 break; 12295 } 12296 12297 if (address_mode == mode_64bit 12298 && !(prefixes & PREFIX_ADDR)) 12299 { 12300 *obufp++ = 'a'; 12301 *obufp++ = 'b'; 12302 *obufp++ = 's'; 12303 } 12304 12305 goto case_B; 12306 } 12307 break; 12308 case 'C': 12309 if (intel_syntax && !alt) 12310 break; 12311 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) 12312 { 12313 if (sizeflag & DFLAG) 12314 *obufp++ = intel_syntax ? 'd' : 'l'; 12315 else 12316 *obufp++ = intel_syntax ? 'w' : 's'; 12317 used_prefixes |= (prefixes & PREFIX_DATA); 12318 } 12319 break; 12320 case 'D': 12321 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) 12322 break; 12323 USED_REX (REX_W); 12324 if (modrm.mod == 3) 12325 { 12326 if (rex & REX_W) 12327 *obufp++ = 'q'; 12328 else 12329 { 12330 if (sizeflag & DFLAG) 12331 *obufp++ = intel_syntax ? 'd' : 'l'; 12332 else 12333 *obufp++ = 'w'; 12334 used_prefixes |= (prefixes & PREFIX_DATA); 12335 } 12336 } 12337 else 12338 *obufp++ = 'w'; 12339 break; 12340 case 'E': /* For jcxz/jecxz */ 12341 if (address_mode == mode_64bit) 12342 { 12343 if (sizeflag & AFLAG) 12344 *obufp++ = 'r'; 12345 else 12346 *obufp++ = 'e'; 12347 } 12348 else 12349 if (sizeflag & AFLAG) 12350 *obufp++ = 'e'; 12351 used_prefixes |= (prefixes & PREFIX_ADDR); 12352 break; 12353 case 'F': 12354 if (intel_syntax) 12355 break; 12356 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) 12357 { 12358 if (sizeflag & AFLAG) 12359 *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; 12360 else 12361 *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; 12362 used_prefixes |= (prefixes & PREFIX_ADDR); 12363 } 12364 break; 12365 case 'G': 12366 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) 12367 break; 12368 if ((rex & REX_W) || (sizeflag & DFLAG)) 12369 *obufp++ = 'l'; 12370 else 12371 *obufp++ = 'w'; 12372 if (!(rex & REX_W)) 12373 used_prefixes |= (prefixes & PREFIX_DATA); 12374 break; 12375 case 'H': 12376 if (intel_syntax) 12377 break; 12378 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS 12379 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) 12380 { 12381 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); 12382 *obufp++ = ','; 12383 *obufp++ = 'p'; 12384 if (prefixes & PREFIX_DS) 12385 *obufp++ = 't'; 12386 else 12387 *obufp++ = 'n'; 12388 } 12389 break; 12390 case 'J': 12391 if (intel_syntax) 12392 break; 12393 *obufp++ = 'l'; 12394 break; 12395 case 'K': 12396 USED_REX (REX_W); 12397 if (rex & REX_W) 12398 *obufp++ = 'q'; 12399 else 12400 *obufp++ = 'd'; 12401 break; 12402 case 'Z': 12403 if (intel_syntax) 12404 break; 12405 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) 12406 { 12407 *obufp++ = 'q'; 12408 break; 12409 } 12410 /* Fall through. */ 12411 goto case_L; 12412 case 'L': 12413 if (l != 0 || len != 1) 12414 { 12415 SAVE_LAST (*p); 12416 break; 12417 } 12418 case_L: 12419 if (intel_syntax) 12420 break; 12421 if (sizeflag & SUFFIX_ALWAYS) 12422 *obufp++ = 'l'; 12423 break; 12424 case 'M': 12425 if (intel_mnemonic != cond) 12426 *obufp++ = 'r'; 12427 break; 12428 case 'N': 12429 if ((prefixes & PREFIX_FWAIT) == 0) 12430 *obufp++ = 'n'; 12431 else 12432 used_prefixes |= PREFIX_FWAIT; 12433 break; 12434 case 'O': 12435 USED_REX (REX_W); 12436 if (rex & REX_W) 12437 *obufp++ = 'o'; 12438 else if (intel_syntax && (sizeflag & DFLAG)) 12439 *obufp++ = 'q'; 12440 else 12441 *obufp++ = 'd'; 12442 if (!(rex & REX_W)) 12443 used_prefixes |= (prefixes & PREFIX_DATA); 12444 break; 12445 case 'T': 12446 if (!intel_syntax 12447 && address_mode == mode_64bit 12448 && (sizeflag & DFLAG)) 12449 { 12450 *obufp++ = 'q'; 12451 break; 12452 } 12453 /* Fall through. */ 12454 case 'P': 12455 if (intel_syntax) 12456 { 12457 if ((rex & REX_W) == 0 12458 && (prefixes & PREFIX_DATA)) 12459 { 12460 if ((sizeflag & DFLAG) == 0) 12461 *obufp++ = 'w'; 12462 used_prefixes |= (prefixes & PREFIX_DATA); 12463 } 12464 break; 12465 } 12466 if ((prefixes & PREFIX_DATA) 12467 || (rex & REX_W) 12468 || (sizeflag & SUFFIX_ALWAYS)) 12469 { 12470 USED_REX (REX_W); 12471 if (rex & REX_W) 12472 *obufp++ = 'q'; 12473 else 12474 { 12475 if (sizeflag & DFLAG) 12476 *obufp++ = 'l'; 12477 else 12478 *obufp++ = 'w'; 12479 used_prefixes |= (prefixes & PREFIX_DATA); 12480 } 12481 } 12482 break; 12483 case 'U': 12484 if (intel_syntax) 12485 break; 12486 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 12487 { 12488 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) 12489 *obufp++ = 'q'; 12490 break; 12491 } 12492 /* Fall through. */ 12493 goto case_Q; 12494 case 'Q': 12495 if (l == 0 && len == 1) 12496 { 12497 case_Q: 12498 if (intel_syntax && !alt) 12499 break; 12500 USED_REX (REX_W); 12501 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) 12502 { 12503 if (rex & REX_W) 12504 *obufp++ = 'q'; 12505 else 12506 { 12507 if (sizeflag & DFLAG) 12508 *obufp++ = intel_syntax ? 'd' : 'l'; 12509 else 12510 *obufp++ = 'w'; 12511 used_prefixes |= (prefixes & PREFIX_DATA); 12512 } 12513 } 12514 } 12515 else 12516 { 12517 if (l != 1 || len != 2 || last[0] != 'L') 12518 { 12519 SAVE_LAST (*p); 12520 break; 12521 } 12522 if (intel_syntax 12523 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) 12524 break; 12525 if ((rex & REX_W)) 12526 { 12527 USED_REX (REX_W); 12528 *obufp++ = 'q'; 12529 } 12530 else 12531 *obufp++ = 'l'; 12532 } 12533 break; 12534 case 'R': 12535 USED_REX (REX_W); 12536 if (rex & REX_W) 12537 *obufp++ = 'q'; 12538 else if (sizeflag & DFLAG) 12539 { 12540 if (intel_syntax) 12541 *obufp++ = 'd'; 12542 else 12543 *obufp++ = 'l'; 12544 } 12545 else 12546 *obufp++ = 'w'; 12547 if (intel_syntax && !p[1] 12548 && ((rex & REX_W) || (sizeflag & DFLAG))) 12549 *obufp++ = 'e'; 12550 if (!(rex & REX_W)) 12551 used_prefixes |= (prefixes & PREFIX_DATA); 12552 break; 12553 case 'V': 12554 if (l == 0 && len == 1) 12555 { 12556 if (intel_syntax) 12557 break; 12558 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 12559 { 12560 if (sizeflag & SUFFIX_ALWAYS) 12561 *obufp++ = 'q'; 12562 break; 12563 } 12564 } 12565 else 12566 { 12567 if (l != 1 12568 || len != 2 12569 || last[0] != 'L') 12570 { 12571 SAVE_LAST (*p); 12572 break; 12573 } 12574 12575 if (rex & REX_W) 12576 { 12577 *obufp++ = 'a'; 12578 *obufp++ = 'b'; 12579 *obufp++ = 's'; 12580 } 12581 } 12582 /* Fall through. */ 12583 goto case_S; 12584 case 'S': 12585 if (l == 0 && len == 1) 12586 { 12587 case_S: 12588 if (intel_syntax) 12589 break; 12590 if (sizeflag & SUFFIX_ALWAYS) 12591 { 12592 if (rex & REX_W) 12593 *obufp++ = 'q'; 12594 else 12595 { 12596 if (sizeflag & DFLAG) 12597 *obufp++ = 'l'; 12598 else 12599 *obufp++ = 'w'; 12600 used_prefixes |= (prefixes & PREFIX_DATA); 12601 } 12602 } 12603 } 12604 else 12605 { 12606 if (l != 1 12607 || len != 2 12608 || last[0] != 'L') 12609 { 12610 SAVE_LAST (*p); 12611 break; 12612 } 12613 12614 if (address_mode == mode_64bit 12615 && !(prefixes & PREFIX_ADDR)) 12616 { 12617 *obufp++ = 'a'; 12618 *obufp++ = 'b'; 12619 *obufp++ = 's'; 12620 } 12621 12622 goto case_S; 12623 } 12624 break; 12625 case 'X': 12626 if (l != 0 || len != 1) 12627 { 12628 SAVE_LAST (*p); 12629 break; 12630 } 12631 if (need_vex && vex.prefix) 12632 { 12633 if (vex.prefix == DATA_PREFIX_OPCODE) 12634 *obufp++ = 'd'; 12635 else 12636 *obufp++ = 's'; 12637 } 12638 else 12639 { 12640 if (prefixes & PREFIX_DATA) 12641 *obufp++ = 'd'; 12642 else 12643 *obufp++ = 's'; 12644 used_prefixes |= (prefixes & PREFIX_DATA); 12645 } 12646 break; 12647 case 'Y': 12648 if (l == 0 && len == 1) 12649 { 12650 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) 12651 break; 12652 if (rex & REX_W) 12653 { 12654 USED_REX (REX_W); 12655 *obufp++ = 'q'; 12656 } 12657 break; 12658 } 12659 else 12660 { 12661 if (l != 1 || len != 2 || last[0] != 'X') 12662 { 12663 SAVE_LAST (*p); 12664 break; 12665 } 12666 if (!need_vex) 12667 abort (); 12668 if (intel_syntax 12669 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) 12670 break; 12671 switch (vex.length) 12672 { 12673 case 128: 12674 *obufp++ = 'x'; 12675 break; 12676 case 256: 12677 *obufp++ = 'y'; 12678 break; 12679 default: 12680 abort (); 12681 } 12682 } 12683 break; 12684 case 'W': 12685 if (l == 0 && len == 1) 12686 { 12687 /* operand size flag for cwtl, cbtw */ 12688 USED_REX (REX_W); 12689 if (rex & REX_W) 12690 { 12691 if (intel_syntax) 12692 *obufp++ = 'd'; 12693 else 12694 *obufp++ = 'l'; 12695 } 12696 else if (sizeflag & DFLAG) 12697 *obufp++ = 'w'; 12698 else 12699 *obufp++ = 'b'; 12700 if (!(rex & REX_W)) 12701 used_prefixes |= (prefixes & PREFIX_DATA); 12702 } 12703 else 12704 { 12705 if (l != 1 || len != 2 || last[0] != 'X') 12706 { 12707 SAVE_LAST (*p); 12708 break; 12709 } 12710 if (!need_vex) 12711 abort (); 12712 *obufp++ = vex.w ? 'd': 's'; 12713 } 12714 break; 12715 } 12716 alt = 0; 12717 } 12718 *obufp = 0; 12719 mnemonicendp = obufp; 12720 return 0; 12721 } 12722 12723 static void 12724 oappend (const char *s) 12725 { 12726 obufp = stpcpy (obufp, s); 12727 } 12728 12729 static void 12730 append_seg (void) 12731 { 12732 if (prefixes & PREFIX_CS) 12733 { 12734 used_prefixes |= PREFIX_CS; 12735 oappend ("%cs:" + intel_syntax); 12736 } 12737 if (prefixes & PREFIX_DS) 12738 { 12739 used_prefixes |= PREFIX_DS; 12740 oappend ("%ds:" + intel_syntax); 12741 } 12742 if (prefixes & PREFIX_SS) 12743 { 12744 used_prefixes |= PREFIX_SS; 12745 oappend ("%ss:" + intel_syntax); 12746 } 12747 if (prefixes & PREFIX_ES) 12748 { 12749 used_prefixes |= PREFIX_ES; 12750 oappend ("%es:" + intel_syntax); 12751 } 12752 if (prefixes & PREFIX_FS) 12753 { 12754 used_prefixes |= PREFIX_FS; 12755 oappend ("%fs:" + intel_syntax); 12756 } 12757 if (prefixes & PREFIX_GS) 12758 { 12759 used_prefixes |= PREFIX_GS; 12760 oappend ("%gs:" + intel_syntax); 12761 } 12762 } 12763 12764 static void 12765 OP_indirE (int bytemode, int sizeflag) 12766 { 12767 if (!intel_syntax) 12768 oappend ("*"); 12769 OP_E (bytemode, sizeflag); 12770 } 12771 12772 static void 12773 print_operand_value (char *buf, int hex, bfd_vma disp) 12774 { 12775 if (address_mode == mode_64bit) 12776 { 12777 if (hex) 12778 { 12779 char tmp[30]; 12780 int i; 12781 buf[0] = '0'; 12782 buf[1] = 'x'; 12783 sprintf_vma (tmp, disp); 12784 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); 12785 strcpy (buf + 2, tmp + i); 12786 } 12787 else 12788 { 12789 bfd_signed_vma v = disp; 12790 char tmp[30]; 12791 int i; 12792 if (v < 0) 12793 { 12794 *(buf++) = '-'; 12795 v = -disp; 12796 /* Check for possible overflow on 0x8000000000000000. */ 12797 if (v < 0) 12798 { 12799 strcpy (buf, "9223372036854775808"); 12800 return; 12801 } 12802 } 12803 if (!v) 12804 { 12805 strcpy (buf, "0"); 12806 return; 12807 } 12808 12809 i = 0; 12810 tmp[29] = 0; 12811 while (v) 12812 { 12813 tmp[28 - i] = (v % 10) + '0'; 12814 v /= 10; 12815 i++; 12816 } 12817 strcpy (buf, tmp + 29 - i); 12818 } 12819 } 12820 else 12821 { 12822 if (hex) 12823 sprintf (buf, "0x%x", (unsigned int) disp); 12824 else 12825 sprintf (buf, "%d", (int) disp); 12826 } 12827 } 12828 12829 /* Put DISP in BUF as signed hex number. */ 12830 12831 static void 12832 print_displacement (char *buf, bfd_vma disp) 12833 { 12834 bfd_signed_vma val = disp; 12835 char tmp[30]; 12836 int i, j = 0; 12837 12838 if (val < 0) 12839 { 12840 buf[j++] = '-'; 12841 val = -disp; 12842 12843 /* Check for possible overflow. */ 12844 if (val < 0) 12845 { 12846 switch (address_mode) 12847 { 12848 case mode_64bit: 12849 strcpy (buf + j, "0x8000000000000000"); 12850 break; 12851 case mode_32bit: 12852 strcpy (buf + j, "0x80000000"); 12853 break; 12854 case mode_16bit: 12855 strcpy (buf + j, "0x8000"); 12856 break; 12857 } 12858 return; 12859 } 12860 } 12861 12862 buf[j++] = '0'; 12863 buf[j++] = 'x'; 12864 12865 sprintf_vma (tmp, (bfd_vma) val); 12866 for (i = 0; tmp[i] == '0'; i++) 12867 continue; 12868 if (tmp[i] == '\0') 12869 i--; 12870 strcpy (buf + j, tmp + i); 12871 } 12872 12873 static void 12874 intel_operand_size (int bytemode, int sizeflag) 12875 { 12876 switch (bytemode) 12877 { 12878 case b_mode: 12879 case b_swap_mode: 12880 case dqb_mode: 12881 oappend ("BYTE PTR "); 12882 break; 12883 case w_mode: 12884 case dqw_mode: 12885 oappend ("WORD PTR "); 12886 break; 12887 case stack_v_mode: 12888 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 12889 { 12890 oappend ("QWORD PTR "); 12891 break; 12892 } 12893 /* FALLTHRU */ 12894 case v_mode: 12895 case v_swap_mode: 12896 case dq_mode: 12897 USED_REX (REX_W); 12898 if (rex & REX_W) 12899 oappend ("QWORD PTR "); 12900 else 12901 { 12902 if ((sizeflag & DFLAG) || bytemode == dq_mode) 12903 oappend ("DWORD PTR "); 12904 else 12905 oappend ("WORD PTR "); 12906 used_prefixes |= (prefixes & PREFIX_DATA); 12907 } 12908 break; 12909 case z_mode: 12910 if ((rex & REX_W) || (sizeflag & DFLAG)) 12911 *obufp++ = 'D'; 12912 oappend ("WORD PTR "); 12913 if (!(rex & REX_W)) 12914 used_prefixes |= (prefixes & PREFIX_DATA); 12915 break; 12916 case a_mode: 12917 if (sizeflag & DFLAG) 12918 oappend ("QWORD PTR "); 12919 else 12920 oappend ("DWORD PTR "); 12921 used_prefixes |= (prefixes & PREFIX_DATA); 12922 break; 12923 case d_mode: 12924 case d_scalar_mode: 12925 case d_scalar_swap_mode: 12926 case d_swap_mode: 12927 case dqd_mode: 12928 oappend ("DWORD PTR "); 12929 break; 12930 case q_mode: 12931 case q_scalar_mode: 12932 case q_scalar_swap_mode: 12933 case q_swap_mode: 12934 oappend ("QWORD PTR "); 12935 break; 12936 case m_mode: 12937 if (address_mode == mode_64bit) 12938 oappend ("QWORD PTR "); 12939 else 12940 oappend ("DWORD PTR "); 12941 break; 12942 case f_mode: 12943 if (sizeflag & DFLAG) 12944 oappend ("FWORD PTR "); 12945 else 12946 oappend ("DWORD PTR "); 12947 used_prefixes |= (prefixes & PREFIX_DATA); 12948 break; 12949 case t_mode: 12950 oappend ("TBYTE PTR "); 12951 break; 12952 case x_mode: 12953 case x_swap_mode: 12954 if (need_vex) 12955 { 12956 switch (vex.length) 12957 { 12958 case 128: 12959 oappend ("XMMWORD PTR "); 12960 break; 12961 case 256: 12962 oappend ("YMMWORD PTR "); 12963 break; 12964 default: 12965 abort (); 12966 } 12967 } 12968 else 12969 oappend ("XMMWORD PTR "); 12970 break; 12971 case xmm_mode: 12972 oappend ("XMMWORD PTR "); 12973 break; 12974 case xmmq_mode: 12975 if (!need_vex) 12976 abort (); 12977 12978 switch (vex.length) 12979 { 12980 case 128: 12981 oappend ("QWORD PTR "); 12982 break; 12983 case 256: 12984 oappend ("XMMWORD PTR "); 12985 break; 12986 default: 12987 abort (); 12988 } 12989 break; 12990 case ymmq_mode: 12991 if (!need_vex) 12992 abort (); 12993 12994 switch (vex.length) 12995 { 12996 case 128: 12997 oappend ("QWORD PTR "); 12998 break; 12999 case 256: 13000 oappend ("YMMWORD PTR "); 13001 break; 13002 default: 13003 abort (); 13004 } 13005 break; 13006 case o_mode: 13007 oappend ("OWORD PTR "); 13008 break; 13009 case vex_w_dq_mode: 13010 case vex_scalar_w_dq_mode: 13011 if (!need_vex) 13012 abort (); 13013 13014 if (vex.w) 13015 oappend ("QWORD PTR "); 13016 else 13017 oappend ("DWORD PTR "); 13018 break; 13019 default: 13020 break; 13021 } 13022 } 13023 13024 static void 13025 OP_E_register (int bytemode, int sizeflag) 13026 { 13027 int reg = modrm.rm; 13028 const char **names; 13029 13030 USED_REX (REX_B); 13031 if ((rex & REX_B)) 13032 reg += 8; 13033 13034 if ((sizeflag & SUFFIX_ALWAYS) 13035 && (bytemode == b_swap_mode || bytemode == v_swap_mode)) 13036 swap_operand (); 13037 13038 switch (bytemode) 13039 { 13040 case b_mode: 13041 case b_swap_mode: 13042 USED_REX (0); 13043 if (rex) 13044 names = names8rex; 13045 else 13046 names = names8; 13047 break; 13048 case w_mode: 13049 names = names16; 13050 break; 13051 case d_mode: 13052 names = names32; 13053 break; 13054 case q_mode: 13055 names = names64; 13056 break; 13057 case m_mode: 13058 names = address_mode == mode_64bit ? names64 : names32; 13059 break; 13060 case stack_v_mode: 13061 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 13062 { 13063 names = names64; 13064 break; 13065 } 13066 bytemode = v_mode; 13067 /* FALLTHRU */ 13068 case v_mode: 13069 case v_swap_mode: 13070 case dq_mode: 13071 case dqb_mode: 13072 case dqd_mode: 13073 case dqw_mode: 13074 USED_REX (REX_W); 13075 if (rex & REX_W) 13076 names = names64; 13077 else 13078 { 13079 if ((sizeflag & DFLAG) 13080 || (bytemode != v_mode 13081 && bytemode != v_swap_mode)) 13082 names = names32; 13083 else 13084 names = names16; 13085 used_prefixes |= (prefixes & PREFIX_DATA); 13086 } 13087 break; 13088 case 0: 13089 return; 13090 default: 13091 oappend (INTERNAL_DISASSEMBLER_ERROR); 13092 return; 13093 } 13094 oappend (names[reg]); 13095 } 13096 13097 static void 13098 OP_E_memory (int bytemode, int sizeflag) 13099 { 13100 bfd_vma disp = 0; 13101 int add = (rex & REX_B) ? 8 : 0; 13102 int riprel = 0; 13103 13104 USED_REX (REX_B); 13105 if (intel_syntax) 13106 intel_operand_size (bytemode, sizeflag); 13107 append_seg (); 13108 13109 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 13110 { 13111 /* 32/64 bit address mode */ 13112 int havedisp; 13113 int havesib; 13114 int havebase; 13115 int haveindex; 13116 int needindex; 13117 int base, rbase; 13118 int vindex = 0; 13119 int scale = 0; 13120 13121 havesib = 0; 13122 havebase = 1; 13123 haveindex = 0; 13124 base = modrm.rm; 13125 13126 if (base == 4) 13127 { 13128 havesib = 1; 13129 vindex = sib.index; 13130 scale = sib.scale; 13131 base = sib.base; 13132 USED_REX (REX_X); 13133 if (rex & REX_X) 13134 vindex += 8; 13135 haveindex = vindex != 4; 13136 codep++; 13137 } 13138 rbase = base + add; 13139 13140 switch (modrm.mod) 13141 { 13142 case 0: 13143 if (base == 5) 13144 { 13145 havebase = 0; 13146 if (address_mode == mode_64bit && !havesib) 13147 riprel = 1; 13148 disp = get32s (); 13149 } 13150 break; 13151 case 1: 13152 FETCH_DATA (the_info, codep + 1); 13153 disp = *codep++; 13154 if ((disp & 0x80) != 0) 13155 disp -= 0x100; 13156 break; 13157 case 2: 13158 disp = get32s (); 13159 break; 13160 } 13161 13162 /* In 32bit mode, we need index register to tell [offset] from 13163 [eiz*1 + offset]. */ 13164 needindex = (havesib 13165 && !havebase 13166 && !haveindex 13167 && address_mode == mode_32bit); 13168 havedisp = (havebase 13169 || needindex 13170 || (havesib && (haveindex || scale != 0))); 13171 13172 if (!intel_syntax) 13173 if (modrm.mod != 0 || base == 5) 13174 { 13175 if (havedisp || riprel) 13176 print_displacement (scratchbuf, disp); 13177 else 13178 print_operand_value (scratchbuf, 1, disp); 13179 oappend (scratchbuf); 13180 if (riprel) 13181 { 13182 set_op (disp, 1); 13183 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); 13184 } 13185 } 13186 13187 if (havebase || haveindex || riprel) 13188 used_prefixes |= PREFIX_ADDR; 13189 13190 if (havedisp || (intel_syntax && riprel)) 13191 { 13192 *obufp++ = open_char; 13193 if (intel_syntax && riprel) 13194 { 13195 set_op (disp, 1); 13196 oappend (sizeflag & AFLAG ? "rip" : "eip"); 13197 } 13198 *obufp = '\0'; 13199 if (havebase) 13200 oappend (address_mode == mode_64bit && (sizeflag & AFLAG) 13201 ? names64[rbase] : names32[rbase]); 13202 if (havesib) 13203 { 13204 /* ESP/RSP won't allow index. If base isn't ESP/RSP, 13205 print index to tell base + index from base. */ 13206 if (scale != 0 13207 || needindex 13208 || haveindex 13209 || (havebase && base != ESP_REG_NUM)) 13210 { 13211 if (!intel_syntax || havebase) 13212 { 13213 *obufp++ = separator_char; 13214 *obufp = '\0'; 13215 } 13216 if (haveindex) 13217 oappend (address_mode == mode_64bit 13218 && (sizeflag & AFLAG) 13219 ? names64[vindex] : names32[vindex]); 13220 else 13221 oappend (address_mode == mode_64bit 13222 && (sizeflag & AFLAG) 13223 ? index64 : index32); 13224 13225 *obufp++ = scale_char; 13226 *obufp = '\0'; 13227 sprintf (scratchbuf, "%d", 1 << scale); 13228 oappend (scratchbuf); 13229 } 13230 } 13231 if (intel_syntax 13232 && (disp || modrm.mod != 0 || base == 5)) 13233 { 13234 if (!havedisp || (bfd_signed_vma) disp >= 0) 13235 { 13236 *obufp++ = '+'; 13237 *obufp = '\0'; 13238 } 13239 else if (modrm.mod != 1 && disp != -disp) 13240 { 13241 *obufp++ = '-'; 13242 *obufp = '\0'; 13243 disp = - (bfd_signed_vma) disp; 13244 } 13245 13246 if (havedisp) 13247 print_displacement (scratchbuf, disp); 13248 else 13249 print_operand_value (scratchbuf, 1, disp); 13250 oappend (scratchbuf); 13251 } 13252 13253 *obufp++ = close_char; 13254 *obufp = '\0'; 13255 } 13256 else if (intel_syntax) 13257 { 13258 if (modrm.mod != 0 || base == 5) 13259 { 13260 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS 13261 | PREFIX_ES | PREFIX_FS | PREFIX_GS)) 13262 ; 13263 else 13264 { 13265 oappend (names_seg[ds_reg - es_reg]); 13266 oappend (":"); 13267 } 13268 print_operand_value (scratchbuf, 1, disp); 13269 oappend (scratchbuf); 13270 } 13271 } 13272 } 13273 else 13274 { 13275 /* 16 bit address mode */ 13276 used_prefixes |= prefixes & PREFIX_ADDR; 13277 switch (modrm.mod) 13278 { 13279 case 0: 13280 if (modrm.rm == 6) 13281 { 13282 disp = get16 (); 13283 if ((disp & 0x8000) != 0) 13284 disp -= 0x10000; 13285 } 13286 break; 13287 case 1: 13288 FETCH_DATA (the_info, codep + 1); 13289 disp = *codep++; 13290 if ((disp & 0x80) != 0) 13291 disp -= 0x100; 13292 break; 13293 case 2: 13294 disp = get16 (); 13295 if ((disp & 0x8000) != 0) 13296 disp -= 0x10000; 13297 break; 13298 } 13299 13300 if (!intel_syntax) 13301 if (modrm.mod != 0 || modrm.rm == 6) 13302 { 13303 print_displacement (scratchbuf, disp); 13304 oappend (scratchbuf); 13305 } 13306 13307 if (modrm.mod != 0 || modrm.rm != 6) 13308 { 13309 *obufp++ = open_char; 13310 *obufp = '\0'; 13311 oappend (index16[modrm.rm]); 13312 if (intel_syntax 13313 && (disp || modrm.mod != 0 || modrm.rm == 6)) 13314 { 13315 if ((bfd_signed_vma) disp >= 0) 13316 { 13317 *obufp++ = '+'; 13318 *obufp = '\0'; 13319 } 13320 else if (modrm.mod != 1) 13321 { 13322 *obufp++ = '-'; 13323 *obufp = '\0'; 13324 disp = - (bfd_signed_vma) disp; 13325 } 13326 13327 print_displacement (scratchbuf, disp); 13328 oappend (scratchbuf); 13329 } 13330 13331 *obufp++ = close_char; 13332 *obufp = '\0'; 13333 } 13334 else if (intel_syntax) 13335 { 13336 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS 13337 | PREFIX_ES | PREFIX_FS | PREFIX_GS)) 13338 ; 13339 else 13340 { 13341 oappend (names_seg[ds_reg - es_reg]); 13342 oappend (":"); 13343 } 13344 print_operand_value (scratchbuf, 1, disp & 0xffff); 13345 oappend (scratchbuf); 13346 } 13347 } 13348 } 13349 13350 static void 13351 OP_E (int bytemode, int sizeflag) 13352 { 13353 /* Skip mod/rm byte. */ 13354 MODRM_CHECK; 13355 codep++; 13356 13357 if (modrm.mod == 3) 13358 OP_E_register (bytemode, sizeflag); 13359 else 13360 OP_E_memory (bytemode, sizeflag); 13361 } 13362 13363 static void 13364 OP_G (int bytemode, int sizeflag) 13365 { 13366 int add = 0; 13367 USED_REX (REX_R); 13368 if (rex & REX_R) 13369 add += 8; 13370 switch (bytemode) 13371 { 13372 case b_mode: 13373 USED_REX (0); 13374 if (rex) 13375 oappend (names8rex[modrm.reg + add]); 13376 else 13377 oappend (names8[modrm.reg + add]); 13378 break; 13379 case w_mode: 13380 oappend (names16[modrm.reg + add]); 13381 break; 13382 case d_mode: 13383 oappend (names32[modrm.reg + add]); 13384 break; 13385 case q_mode: 13386 oappend (names64[modrm.reg + add]); 13387 break; 13388 case v_mode: 13389 case dq_mode: 13390 case dqb_mode: 13391 case dqd_mode: 13392 case dqw_mode: 13393 USED_REX (REX_W); 13394 if (rex & REX_W) 13395 oappend (names64[modrm.reg + add]); 13396 else 13397 { 13398 if ((sizeflag & DFLAG) || bytemode != v_mode) 13399 oappend (names32[modrm.reg + add]); 13400 else 13401 oappend (names16[modrm.reg + add]); 13402 used_prefixes |= (prefixes & PREFIX_DATA); 13403 } 13404 break; 13405 case m_mode: 13406 if (address_mode == mode_64bit) 13407 oappend (names64[modrm.reg + add]); 13408 else 13409 oappend (names32[modrm.reg + add]); 13410 break; 13411 default: 13412 oappend (INTERNAL_DISASSEMBLER_ERROR); 13413 break; 13414 } 13415 } 13416 13417 static bfd_vma 13418 get64 (void) 13419 { 13420 bfd_vma x; 13421 #ifdef BFD64 13422 unsigned int a; 13423 unsigned int b; 13424 13425 FETCH_DATA (the_info, codep + 8); 13426 a = *codep++ & 0xff; 13427 a |= (*codep++ & 0xff) << 8; 13428 a |= (*codep++ & 0xff) << 16; 13429 a |= (*codep++ & 0xff) << 24; 13430 b = *codep++ & 0xff; 13431 b |= (*codep++ & 0xff) << 8; 13432 b |= (*codep++ & 0xff) << 16; 13433 b |= (*codep++ & 0xff) << 24; 13434 x = a + ((bfd_vma) b << 32); 13435 #else 13436 abort (); 13437 x = 0; 13438 #endif 13439 return x; 13440 } 13441 13442 static bfd_signed_vma 13443 get32 (void) 13444 { 13445 bfd_signed_vma x = 0; 13446 13447 FETCH_DATA (the_info, codep + 4); 13448 x = *codep++ & (bfd_signed_vma) 0xff; 13449 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; 13450 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; 13451 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; 13452 return x; 13453 } 13454 13455 static bfd_signed_vma 13456 get32s (void) 13457 { 13458 bfd_signed_vma x = 0; 13459 13460 FETCH_DATA (the_info, codep + 4); 13461 x = *codep++ & (bfd_signed_vma) 0xff; 13462 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; 13463 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; 13464 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; 13465 13466 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); 13467 13468 return x; 13469 } 13470 13471 static int 13472 get16 (void) 13473 { 13474 int x = 0; 13475 13476 FETCH_DATA (the_info, codep + 2); 13477 x = *codep++ & 0xff; 13478 x |= (*codep++ & 0xff) << 8; 13479 return x; 13480 } 13481 13482 static void 13483 set_op (bfd_vma op, int riprel) 13484 { 13485 op_index[op_ad] = op_ad; 13486 if (address_mode == mode_64bit) 13487 { 13488 op_address[op_ad] = op; 13489 op_riprel[op_ad] = riprel; 13490 } 13491 else 13492 { 13493 /* Mask to get a 32-bit address. */ 13494 op_address[op_ad] = op & 0xffffffff; 13495 op_riprel[op_ad] = riprel & 0xffffffff; 13496 } 13497 } 13498 13499 static void 13500 OP_REG (int code, int sizeflag) 13501 { 13502 const char *s; 13503 int add; 13504 USED_REX (REX_B); 13505 if (rex & REX_B) 13506 add = 8; 13507 else 13508 add = 0; 13509 13510 switch (code) 13511 { 13512 case ax_reg: case cx_reg: case dx_reg: case bx_reg: 13513 case sp_reg: case bp_reg: case si_reg: case di_reg: 13514 s = names16[code - ax_reg + add]; 13515 break; 13516 case es_reg: case ss_reg: case cs_reg: 13517 case ds_reg: case fs_reg: case gs_reg: 13518 s = names_seg[code - es_reg + add]; 13519 break; 13520 case al_reg: case ah_reg: case cl_reg: case ch_reg: 13521 case dl_reg: case dh_reg: case bl_reg: case bh_reg: 13522 USED_REX (0); 13523 if (rex) 13524 s = names8rex[code - al_reg + add]; 13525 else 13526 s = names8[code - al_reg]; 13527 break; 13528 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: 13529 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: 13530 if (address_mode == mode_64bit && (sizeflag & DFLAG)) 13531 { 13532 s = names64[code - rAX_reg + add]; 13533 break; 13534 } 13535 code += eAX_reg - rAX_reg; 13536 /* Fall through. */ 13537 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: 13538 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: 13539 USED_REX (REX_W); 13540 if (rex & REX_W) 13541 s = names64[code - eAX_reg + add]; 13542 else 13543 { 13544 if (sizeflag & DFLAG) 13545 s = names32[code - eAX_reg + add]; 13546 else 13547 s = names16[code - eAX_reg + add]; 13548 used_prefixes |= (prefixes & PREFIX_DATA); 13549 } 13550 break; 13551 default: 13552 s = INTERNAL_DISASSEMBLER_ERROR; 13553 break; 13554 } 13555 oappend (s); 13556 } 13557 13558 static void 13559 OP_IMREG (int code, int sizeflag) 13560 { 13561 const char *s; 13562 13563 switch (code) 13564 { 13565 case indir_dx_reg: 13566 if (intel_syntax) 13567 s = "dx"; 13568 else 13569 s = "(%dx)"; 13570 break; 13571 case ax_reg: case cx_reg: case dx_reg: case bx_reg: 13572 case sp_reg: case bp_reg: case si_reg: case di_reg: 13573 s = names16[code - ax_reg]; 13574 break; 13575 case es_reg: case ss_reg: case cs_reg: 13576 case ds_reg: case fs_reg: case gs_reg: 13577 s = names_seg[code - es_reg]; 13578 break; 13579 case al_reg: case ah_reg: case cl_reg: case ch_reg: 13580 case dl_reg: case dh_reg: case bl_reg: case bh_reg: 13581 USED_REX (0); 13582 if (rex) 13583 s = names8rex[code - al_reg]; 13584 else 13585 s = names8[code - al_reg]; 13586 break; 13587 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: 13588 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: 13589 USED_REX (REX_W); 13590 if (rex & REX_W) 13591 s = names64[code - eAX_reg]; 13592 else 13593 { 13594 if (sizeflag & DFLAG) 13595 s = names32[code - eAX_reg]; 13596 else 13597 s = names16[code - eAX_reg]; 13598 used_prefixes |= (prefixes & PREFIX_DATA); 13599 } 13600 break; 13601 case z_mode_ax_reg: 13602 if ((rex & REX_W) || (sizeflag & DFLAG)) 13603 s = *names32; 13604 else 13605 s = *names16; 13606 if (!(rex & REX_W)) 13607 used_prefixes |= (prefixes & PREFIX_DATA); 13608 break; 13609 default: 13610 s = INTERNAL_DISASSEMBLER_ERROR; 13611 break; 13612 } 13613 oappend (s); 13614 } 13615 13616 static void 13617 OP_I (int bytemode, int sizeflag) 13618 { 13619 bfd_signed_vma op; 13620 bfd_signed_vma mask = -1; 13621 13622 switch (bytemode) 13623 { 13624 case b_mode: 13625 FETCH_DATA (the_info, codep + 1); 13626 op = *codep++; 13627 mask = 0xff; 13628 break; 13629 case q_mode: 13630 if (address_mode == mode_64bit) 13631 { 13632 op = get32s (); 13633 break; 13634 } 13635 /* Fall through. */ 13636 case v_mode: 13637 USED_REX (REX_W); 13638 if (rex & REX_W) 13639 op = get32s (); 13640 else 13641 { 13642 if (sizeflag & DFLAG) 13643 { 13644 op = get32 (); 13645 mask = 0xffffffff; 13646 } 13647 else 13648 { 13649 op = get16 (); 13650 mask = 0xfffff; 13651 } 13652 used_prefixes |= (prefixes & PREFIX_DATA); 13653 } 13654 break; 13655 case w_mode: 13656 mask = 0xfffff; 13657 op = get16 (); 13658 break; 13659 case const_1_mode: 13660 if (intel_syntax) 13661 oappend ("1"); 13662 return; 13663 default: 13664 oappend (INTERNAL_DISASSEMBLER_ERROR); 13665 return; 13666 } 13667 13668 op &= mask; 13669 scratchbuf[0] = '$'; 13670 print_operand_value (scratchbuf + 1, 1, op); 13671 oappend (scratchbuf + intel_syntax); 13672 scratchbuf[0] = '\0'; 13673 } 13674 13675 static void 13676 OP_I64 (int bytemode, int sizeflag) 13677 { 13678 bfd_signed_vma op; 13679 bfd_signed_vma mask = -1; 13680 13681 if (address_mode != mode_64bit) 13682 { 13683 OP_I (bytemode, sizeflag); 13684 return; 13685 } 13686 13687 switch (bytemode) 13688 { 13689 case b_mode: 13690 FETCH_DATA (the_info, codep + 1); 13691 op = *codep++; 13692 mask = 0xff; 13693 break; 13694 case v_mode: 13695 USED_REX (REX_W); 13696 if (rex & REX_W) 13697 op = get64 (); 13698 else 13699 { 13700 if (sizeflag & DFLAG) 13701 { 13702 op = get32 (); 13703 mask = 0xffffffff; 13704 } 13705 else 13706 { 13707 op = get16 (); 13708 mask = 0xfffff; 13709 } 13710 used_prefixes |= (prefixes & PREFIX_DATA); 13711 } 13712 break; 13713 case w_mode: 13714 mask = 0xfffff; 13715 op = get16 (); 13716 break; 13717 default: 13718 oappend (INTERNAL_DISASSEMBLER_ERROR); 13719 return; 13720 } 13721 13722 op &= mask; 13723 scratchbuf[0] = '$'; 13724 print_operand_value (scratchbuf + 1, 1, op); 13725 oappend (scratchbuf + intel_syntax); 13726 scratchbuf[0] = '\0'; 13727 } 13728 13729 static void 13730 OP_sI (int bytemode, int sizeflag) 13731 { 13732 bfd_signed_vma op; 13733 13734 switch (bytemode) 13735 { 13736 case b_mode: 13737 case b_T_mode: 13738 FETCH_DATA (the_info, codep + 1); 13739 op = *codep++; 13740 if ((op & 0x80) != 0) 13741 op -= 0x100; 13742 if (bytemode == b_T_mode) 13743 { 13744 if (address_mode != mode_64bit 13745 || !(sizeflag & DFLAG)) 13746 { 13747 if (sizeflag & DFLAG) 13748 op &= 0xffffffff; 13749 else 13750 op &= 0xffff; 13751 } 13752 } 13753 else 13754 { 13755 if (!(rex & REX_W)) 13756 { 13757 if (sizeflag & DFLAG) 13758 op &= 0xffffffff; 13759 else 13760 op &= 0xffff; 13761 } 13762 } 13763 break; 13764 case v_mode: 13765 if (sizeflag & DFLAG) 13766 op = get32s (); 13767 else 13768 op = get16 (); 13769 break; 13770 default: 13771 oappend (INTERNAL_DISASSEMBLER_ERROR); 13772 return; 13773 } 13774 13775 scratchbuf[0] = '$'; 13776 print_operand_value (scratchbuf + 1, 1, op); 13777 oappend (scratchbuf + intel_syntax); 13778 } 13779 13780 static void 13781 OP_J (int bytemode, int sizeflag) 13782 { 13783 bfd_vma disp; 13784 bfd_vma mask = -1; 13785 bfd_vma segment = 0; 13786 13787 switch (bytemode) 13788 { 13789 case b_mode: 13790 FETCH_DATA (the_info, codep + 1); 13791 disp = *codep++; 13792 if ((disp & 0x80) != 0) 13793 disp -= 0x100; 13794 break; 13795 case v_mode: 13796 USED_REX (REX_W); 13797 if ((sizeflag & DFLAG) || (rex & REX_W)) 13798 disp = get32s (); 13799 else 13800 { 13801 disp = get16 (); 13802 if ((disp & 0x8000) != 0) 13803 disp -= 0x10000; 13804 /* In 16bit mode, address is wrapped around at 64k within 13805 the same segment. Otherwise, a data16 prefix on a jump 13806 instruction means that the pc is masked to 16 bits after 13807 the displacement is added! */ 13808 mask = 0xffff; 13809 if ((prefixes & PREFIX_DATA) == 0) 13810 segment = ((start_pc + codep - start_codep) 13811 & ~((bfd_vma) 0xffff)); 13812 } 13813 if (!(rex & REX_W)) 13814 used_prefixes |= (prefixes & PREFIX_DATA); 13815 break; 13816 default: 13817 oappend (INTERNAL_DISASSEMBLER_ERROR); 13818 return; 13819 } 13820 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; 13821 set_op (disp, 0); 13822 print_operand_value (scratchbuf, 1, disp); 13823 oappend (scratchbuf); 13824 } 13825 13826 static void 13827 OP_SEG (int bytemode, int sizeflag) 13828 { 13829 if (bytemode == w_mode) 13830 oappend (names_seg[modrm.reg]); 13831 else 13832 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); 13833 } 13834 13835 static void 13836 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) 13837 { 13838 int seg, offset; 13839 13840 if (sizeflag & DFLAG) 13841 { 13842 offset = get32 (); 13843 seg = get16 (); 13844 } 13845 else 13846 { 13847 offset = get16 (); 13848 seg = get16 (); 13849 } 13850 used_prefixes |= (prefixes & PREFIX_DATA); 13851 if (intel_syntax) 13852 sprintf (scratchbuf, "0x%x:0x%x", seg, offset); 13853 else 13854 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); 13855 oappend (scratchbuf); 13856 } 13857 13858 static void 13859 OP_OFF (int bytemode, int sizeflag) 13860 { 13861 bfd_vma off; 13862 13863 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 13864 intel_operand_size (bytemode, sizeflag); 13865 append_seg (); 13866 13867 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 13868 off = get32 (); 13869 else 13870 off = get16 (); 13871 13872 if (intel_syntax) 13873 { 13874 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS 13875 | PREFIX_ES | PREFIX_FS | PREFIX_GS))) 13876 { 13877 oappend (names_seg[ds_reg - es_reg]); 13878 oappend (":"); 13879 } 13880 } 13881 print_operand_value (scratchbuf, 1, off); 13882 oappend (scratchbuf); 13883 } 13884 13885 static void 13886 OP_OFF64 (int bytemode, int sizeflag) 13887 { 13888 bfd_vma off; 13889 13890 if (address_mode != mode_64bit 13891 || (prefixes & PREFIX_ADDR)) 13892 { 13893 OP_OFF (bytemode, sizeflag); 13894 return; 13895 } 13896 13897 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) 13898 intel_operand_size (bytemode, sizeflag); 13899 append_seg (); 13900 13901 off = get64 (); 13902 13903 if (intel_syntax) 13904 { 13905 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS 13906 | PREFIX_ES | PREFIX_FS | PREFIX_GS))) 13907 { 13908 oappend (names_seg[ds_reg - es_reg]); 13909 oappend (":"); 13910 } 13911 } 13912 print_operand_value (scratchbuf, 1, off); 13913 oappend (scratchbuf); 13914 } 13915 13916 static void 13917 ptr_reg (int code, int sizeflag) 13918 { 13919 const char *s; 13920 13921 *obufp++ = open_char; 13922 used_prefixes |= (prefixes & PREFIX_ADDR); 13923 if (address_mode == mode_64bit) 13924 { 13925 if (!(sizeflag & AFLAG)) 13926 s = names32[code - eAX_reg]; 13927 else 13928 s = names64[code - eAX_reg]; 13929 } 13930 else if (sizeflag & AFLAG) 13931 s = names32[code - eAX_reg]; 13932 else 13933 s = names16[code - eAX_reg]; 13934 oappend (s); 13935 *obufp++ = close_char; 13936 *obufp = 0; 13937 } 13938 13939 static void 13940 OP_ESreg (int code, int sizeflag) 13941 { 13942 if (intel_syntax) 13943 { 13944 switch (codep[-1]) 13945 { 13946 case 0x6d: /* insw/insl */ 13947 intel_operand_size (z_mode, sizeflag); 13948 break; 13949 case 0xa5: /* movsw/movsl/movsq */ 13950 case 0xa7: /* cmpsw/cmpsl/cmpsq */ 13951 case 0xab: /* stosw/stosl */ 13952 case 0xaf: /* scasw/scasl */ 13953 intel_operand_size (v_mode, sizeflag); 13954 break; 13955 default: 13956 intel_operand_size (b_mode, sizeflag); 13957 } 13958 } 13959 oappend ("%es:" + intel_syntax); 13960 ptr_reg (code, sizeflag); 13961 } 13962 13963 static void 13964 OP_DSreg (int code, int sizeflag) 13965 { 13966 if (intel_syntax) 13967 { 13968 switch (codep[-1]) 13969 { 13970 case 0x6f: /* outsw/outsl */ 13971 intel_operand_size (z_mode, sizeflag); 13972 break; 13973 case 0xa5: /* movsw/movsl/movsq */ 13974 case 0xa7: /* cmpsw/cmpsl/cmpsq */ 13975 case 0xad: /* lodsw/lodsl/lodsq */ 13976 intel_operand_size (v_mode, sizeflag); 13977 break; 13978 default: 13979 intel_operand_size (b_mode, sizeflag); 13980 } 13981 } 13982 if ((prefixes 13983 & (PREFIX_CS 13984 | PREFIX_DS 13985 | PREFIX_SS 13986 | PREFIX_ES 13987 | PREFIX_FS 13988 | PREFIX_GS)) == 0) 13989 prefixes |= PREFIX_DS; 13990 append_seg (); 13991 ptr_reg (code, sizeflag); 13992 } 13993 13994 static void 13995 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 13996 { 13997 int add; 13998 if (rex & REX_R) 13999 { 14000 USED_REX (REX_R); 14001 add = 8; 14002 } 14003 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) 14004 { 14005 all_prefixes[last_lock_prefix] = 0; 14006 used_prefixes |= PREFIX_LOCK; 14007 add = 8; 14008 } 14009 else 14010 add = 0; 14011 sprintf (scratchbuf, "%%cr%d", modrm.reg + add); 14012 oappend (scratchbuf + intel_syntax); 14013 } 14014 14015 static void 14016 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 14017 { 14018 int add; 14019 USED_REX (REX_R); 14020 if (rex & REX_R) 14021 add = 8; 14022 else 14023 add = 0; 14024 if (intel_syntax) 14025 sprintf (scratchbuf, "db%d", modrm.reg + add); 14026 else 14027 sprintf (scratchbuf, "%%db%d", modrm.reg + add); 14028 oappend (scratchbuf); 14029 } 14030 14031 static void 14032 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 14033 { 14034 sprintf (scratchbuf, "%%tr%d", modrm.reg); 14035 oappend (scratchbuf + intel_syntax); 14036 } 14037 14038 static void 14039 OP_R (int bytemode, int sizeflag) 14040 { 14041 if (modrm.mod == 3) 14042 OP_E (bytemode, sizeflag); 14043 else 14044 BadOp (); 14045 } 14046 14047 static void 14048 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 14049 { 14050 int reg = modrm.reg; 14051 const char **names; 14052 14053 used_prefixes |= (prefixes & PREFIX_DATA); 14054 if (prefixes & PREFIX_DATA) 14055 { 14056 names = names_xmm; 14057 USED_REX (REX_R); 14058 if (rex & REX_R) 14059 reg += 8; 14060 } 14061 else 14062 names = names_mm; 14063 oappend (names[reg]); 14064 } 14065 14066 static void 14067 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 14068 { 14069 int reg = modrm.reg; 14070 const char **names; 14071 14072 USED_REX (REX_R); 14073 if (rex & REX_R) 14074 reg += 8; 14075 if (need_vex 14076 && bytemode != xmm_mode 14077 && bytemode != scalar_mode) 14078 { 14079 switch (vex.length) 14080 { 14081 case 128: 14082 names = names_xmm; 14083 break; 14084 case 256: 14085 names = names_ymm; 14086 break; 14087 default: 14088 abort (); 14089 } 14090 } 14091 else 14092 names = names_xmm; 14093 oappend (names[reg]); 14094 } 14095 14096 static void 14097 OP_EM (int bytemode, int sizeflag) 14098 { 14099 int reg; 14100 const char **names; 14101 14102 if (modrm.mod != 3) 14103 { 14104 if (intel_syntax 14105 && (bytemode == v_mode || bytemode == v_swap_mode)) 14106 { 14107 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; 14108 used_prefixes |= (prefixes & PREFIX_DATA); 14109 } 14110 OP_E (bytemode, sizeflag); 14111 return; 14112 } 14113 14114 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) 14115 swap_operand (); 14116 14117 /* Skip mod/rm byte. */ 14118 MODRM_CHECK; 14119 codep++; 14120 used_prefixes |= (prefixes & PREFIX_DATA); 14121 reg = modrm.rm; 14122 if (prefixes & PREFIX_DATA) 14123 { 14124 names = names_xmm; 14125 USED_REX (REX_B); 14126 if (rex & REX_B) 14127 reg += 8; 14128 } 14129 else 14130 names = names_mm; 14131 oappend (names[reg]); 14132 } 14133 14134 /* cvt* are the only instructions in sse2 which have 14135 both SSE and MMX operands and also have 0x66 prefix 14136 in their opcode. 0x66 was originally used to differentiate 14137 between SSE and MMX instruction(operands). So we have to handle the 14138 cvt* separately using OP_EMC and OP_MXC */ 14139 static void 14140 OP_EMC (int bytemode, int sizeflag) 14141 { 14142 if (modrm.mod != 3) 14143 { 14144 if (intel_syntax && bytemode == v_mode) 14145 { 14146 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; 14147 used_prefixes |= (prefixes & PREFIX_DATA); 14148 } 14149 OP_E (bytemode, sizeflag); 14150 return; 14151 } 14152 14153 /* Skip mod/rm byte. */ 14154 MODRM_CHECK; 14155 codep++; 14156 used_prefixes |= (prefixes & PREFIX_DATA); 14157 oappend (names_mm[modrm.rm]); 14158 } 14159 14160 static void 14161 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 14162 { 14163 used_prefixes |= (prefixes & PREFIX_DATA); 14164 oappend (names_mm[modrm.reg]); 14165 } 14166 14167 static void 14168 OP_EX (int bytemode, int sizeflag) 14169 { 14170 int reg; 14171 const char **names; 14172 14173 /* Skip mod/rm byte. */ 14174 MODRM_CHECK; 14175 codep++; 14176 14177 if (modrm.mod != 3) 14178 { 14179 OP_E_memory (bytemode, sizeflag); 14180 return; 14181 } 14182 14183 reg = modrm.rm; 14184 USED_REX (REX_B); 14185 if (rex & REX_B) 14186 reg += 8; 14187 14188 if ((sizeflag & SUFFIX_ALWAYS) 14189 && (bytemode == x_swap_mode 14190 || bytemode == d_swap_mode 14191 || bytemode == d_scalar_swap_mode 14192 || bytemode == q_swap_mode 14193 || bytemode == q_scalar_swap_mode)) 14194 swap_operand (); 14195 14196 if (need_vex 14197 && bytemode != xmm_mode 14198 && bytemode != xmmq_mode 14199 && bytemode != d_scalar_mode 14200 && bytemode != d_scalar_swap_mode 14201 && bytemode != q_scalar_mode 14202 && bytemode != q_scalar_swap_mode 14203 && bytemode != vex_scalar_w_dq_mode) 14204 { 14205 switch (vex.length) 14206 { 14207 case 128: 14208 names = names_xmm; 14209 break; 14210 case 256: 14211 names = names_ymm; 14212 break; 14213 default: 14214 abort (); 14215 } 14216 } 14217 else 14218 names = names_xmm; 14219 oappend (names[reg]); 14220 } 14221 14222 static void 14223 OP_MS (int bytemode, int sizeflag) 14224 { 14225 if (modrm.mod == 3) 14226 OP_EM (bytemode, sizeflag); 14227 else 14228 BadOp (); 14229 } 14230 14231 static void 14232 OP_XS (int bytemode, int sizeflag) 14233 { 14234 if (modrm.mod == 3) 14235 OP_EX (bytemode, sizeflag); 14236 else 14237 BadOp (); 14238 } 14239 14240 static void 14241 OP_M (int bytemode, int sizeflag) 14242 { 14243 if (modrm.mod == 3) 14244 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ 14245 BadOp (); 14246 else 14247 OP_E (bytemode, sizeflag); 14248 } 14249 14250 static void 14251 OP_0f07 (int bytemode, int sizeflag) 14252 { 14253 if (modrm.mod != 3 || modrm.rm != 0) 14254 BadOp (); 14255 else 14256 OP_E (bytemode, sizeflag); 14257 } 14258 14259 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in 14260 32bit mode and "xchg %rax,%rax" in 64bit mode. */ 14261 14262 static void 14263 NOP_Fixup1 (int bytemode, int sizeflag) 14264 { 14265 if ((prefixes & PREFIX_DATA) != 0 14266 || (rex != 0 14267 && rex != 0x48 14268 && address_mode == mode_64bit)) 14269 OP_REG (bytemode, sizeflag); 14270 else 14271 strcpy (obuf, "nop"); 14272 } 14273 14274 static void 14275 NOP_Fixup2 (int bytemode, int sizeflag) 14276 { 14277 if ((prefixes & PREFIX_DATA) != 0 14278 || (rex != 0 14279 && rex != 0x48 14280 && address_mode == mode_64bit)) 14281 OP_IMREG (bytemode, sizeflag); 14282 } 14283 14284 static const char *const Suffix3DNow[] = { 14285 /* 00 */ NULL, NULL, NULL, NULL, 14286 /* 04 */ NULL, NULL, NULL, NULL, 14287 /* 08 */ NULL, NULL, NULL, NULL, 14288 /* 0C */ "pi2fw", "pi2fd", NULL, NULL, 14289 /* 10 */ NULL, NULL, NULL, NULL, 14290 /* 14 */ NULL, NULL, NULL, NULL, 14291 /* 18 */ NULL, NULL, NULL, NULL, 14292 /* 1C */ "pf2iw", "pf2id", NULL, NULL, 14293 /* 20 */ NULL, NULL, NULL, NULL, 14294 /* 24 */ NULL, NULL, NULL, NULL, 14295 /* 28 */ NULL, NULL, NULL, NULL, 14296 /* 2C */ NULL, NULL, NULL, NULL, 14297 /* 30 */ NULL, NULL, NULL, NULL, 14298 /* 34 */ NULL, NULL, NULL, NULL, 14299 /* 38 */ NULL, NULL, NULL, NULL, 14300 /* 3C */ NULL, NULL, NULL, NULL, 14301 /* 40 */ NULL, NULL, NULL, NULL, 14302 /* 44 */ NULL, NULL, NULL, NULL, 14303 /* 48 */ NULL, NULL, NULL, NULL, 14304 /* 4C */ NULL, NULL, NULL, NULL, 14305 /* 50 */ NULL, NULL, NULL, NULL, 14306 /* 54 */ NULL, NULL, NULL, NULL, 14307 /* 58 */ NULL, NULL, NULL, NULL, 14308 /* 5C */ NULL, NULL, NULL, NULL, 14309 /* 60 */ NULL, NULL, NULL, NULL, 14310 /* 64 */ NULL, NULL, NULL, NULL, 14311 /* 68 */ NULL, NULL, NULL, NULL, 14312 /* 6C */ NULL, NULL, NULL, NULL, 14313 /* 70 */ NULL, NULL, NULL, NULL, 14314 /* 74 */ NULL, NULL, NULL, NULL, 14315 /* 78 */ NULL, NULL, NULL, NULL, 14316 /* 7C */ NULL, NULL, NULL, NULL, 14317 /* 80 */ NULL, NULL, NULL, NULL, 14318 /* 84 */ NULL, NULL, NULL, NULL, 14319 /* 88 */ NULL, NULL, "pfnacc", NULL, 14320 /* 8C */ NULL, NULL, "pfpnacc", NULL, 14321 /* 90 */ "pfcmpge", NULL, NULL, NULL, 14322 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", 14323 /* 98 */ NULL, NULL, "pfsub", NULL, 14324 /* 9C */ NULL, NULL, "pfadd", NULL, 14325 /* A0 */ "pfcmpgt", NULL, NULL, NULL, 14326 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", 14327 /* A8 */ NULL, NULL, "pfsubr", NULL, 14328 /* AC */ NULL, NULL, "pfacc", NULL, 14329 /* B0 */ "pfcmpeq", NULL, NULL, NULL, 14330 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", 14331 /* B8 */ NULL, NULL, NULL, "pswapd", 14332 /* BC */ NULL, NULL, NULL, "pavgusb", 14333 /* C0 */ NULL, NULL, NULL, NULL, 14334 /* C4 */ NULL, NULL, NULL, NULL, 14335 /* C8 */ NULL, NULL, NULL, NULL, 14336 /* CC */ NULL, NULL, NULL, NULL, 14337 /* D0 */ NULL, NULL, NULL, NULL, 14338 /* D4 */ NULL, NULL, NULL, NULL, 14339 /* D8 */ NULL, NULL, NULL, NULL, 14340 /* DC */ NULL, NULL, NULL, NULL, 14341 /* E0 */ NULL, NULL, NULL, NULL, 14342 /* E4 */ NULL, NULL, NULL, NULL, 14343 /* E8 */ NULL, NULL, NULL, NULL, 14344 /* EC */ NULL, NULL, NULL, NULL, 14345 /* F0 */ NULL, NULL, NULL, NULL, 14346 /* F4 */ NULL, NULL, NULL, NULL, 14347 /* F8 */ NULL, NULL, NULL, NULL, 14348 /* FC */ NULL, NULL, NULL, NULL, 14349 }; 14350 14351 static void 14352 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 14353 { 14354 const char *mnemonic; 14355 14356 FETCH_DATA (the_info, codep + 1); 14357 /* AMD 3DNow! instructions are specified by an opcode suffix in the 14358 place where an 8-bit immediate would normally go. ie. the last 14359 byte of the instruction. */ 14360 obufp = mnemonicendp; 14361 mnemonic = Suffix3DNow[*codep++ & 0xff]; 14362 if (mnemonic) 14363 oappend (mnemonic); 14364 else 14365 { 14366 /* Since a variable sized modrm/sib chunk is between the start 14367 of the opcode (0x0f0f) and the opcode suffix, we need to do 14368 all the modrm processing first, and don't know until now that 14369 we have a bad opcode. This necessitates some cleaning up. */ 14370 op_out[0][0] = '\0'; 14371 op_out[1][0] = '\0'; 14372 BadOp (); 14373 } 14374 mnemonicendp = obufp; 14375 } 14376 14377 static struct op simd_cmp_op[] = 14378 { 14379 { STRING_COMMA_LEN ("eq") }, 14380 { STRING_COMMA_LEN ("lt") }, 14381 { STRING_COMMA_LEN ("le") }, 14382 { STRING_COMMA_LEN ("unord") }, 14383 { STRING_COMMA_LEN ("neq") }, 14384 { STRING_COMMA_LEN ("nlt") }, 14385 { STRING_COMMA_LEN ("nle") }, 14386 { STRING_COMMA_LEN ("ord") } 14387 }; 14388 14389 static void 14390 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 14391 { 14392 unsigned int cmp_type; 14393 14394 FETCH_DATA (the_info, codep + 1); 14395 cmp_type = *codep++ & 0xff; 14396 if (cmp_type < ARRAY_SIZE (simd_cmp_op)) 14397 { 14398 char suffix [3]; 14399 char *p = mnemonicendp - 2; 14400 suffix[0] = p[0]; 14401 suffix[1] = p[1]; 14402 suffix[2] = '\0'; 14403 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); 14404 mnemonicendp += simd_cmp_op[cmp_type].len; 14405 } 14406 else 14407 { 14408 /* We have a reserved extension byte. Output it directly. */ 14409 scratchbuf[0] = '$'; 14410 print_operand_value (scratchbuf + 1, 1, cmp_type); 14411 oappend (scratchbuf + intel_syntax); 14412 scratchbuf[0] = '\0'; 14413 } 14414 } 14415 14416 static void 14417 OP_Mwait (int bytemode ATTRIBUTE_UNUSED, 14418 int sizeflag ATTRIBUTE_UNUSED) 14419 { 14420 /* mwait %eax,%ecx */ 14421 if (!intel_syntax) 14422 { 14423 const char **names = (address_mode == mode_64bit 14424 ? names64 : names32); 14425 strcpy (op_out[0], names[0]); 14426 strcpy (op_out[1], names[1]); 14427 two_source_ops = 1; 14428 } 14429 /* Skip mod/rm byte. */ 14430 MODRM_CHECK; 14431 codep++; 14432 } 14433 14434 static void 14435 OP_Monitor (int bytemode ATTRIBUTE_UNUSED, 14436 int sizeflag ATTRIBUTE_UNUSED) 14437 { 14438 /* monitor %eax,%ecx,%edx" */ 14439 if (!intel_syntax) 14440 { 14441 const char **op1_names; 14442 const char **names = (address_mode == mode_64bit 14443 ? names64 : names32); 14444 14445 if (!(prefixes & PREFIX_ADDR)) 14446 op1_names = (address_mode == mode_16bit 14447 ? names16 : names); 14448 else 14449 { 14450 /* Remove "addr16/addr32". */ 14451 all_prefixes[last_addr_prefix] = 0; 14452 op1_names = (address_mode != mode_32bit 14453 ? names32 : names16); 14454 used_prefixes |= PREFIX_ADDR; 14455 } 14456 strcpy (op_out[0], op1_names[0]); 14457 strcpy (op_out[1], names[1]); 14458 strcpy (op_out[2], names[2]); 14459 two_source_ops = 1; 14460 } 14461 /* Skip mod/rm byte. */ 14462 MODRM_CHECK; 14463 codep++; 14464 } 14465 14466 static void 14467 BadOp (void) 14468 { 14469 /* Throw away prefixes and 1st. opcode byte. */ 14470 codep = insn_codep + 1; 14471 oappend ("(bad)"); 14472 } 14473 14474 static void 14475 REP_Fixup (int bytemode, int sizeflag) 14476 { 14477 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, 14478 lods and stos. */ 14479 if (prefixes & PREFIX_REPZ) 14480 all_prefixes[last_repz_prefix] = REP_PREFIX; 14481 14482 switch (bytemode) 14483 { 14484 case al_reg: 14485 case eAX_reg: 14486 case indir_dx_reg: 14487 OP_IMREG (bytemode, sizeflag); 14488 break; 14489 case eDI_reg: 14490 OP_ESreg (bytemode, sizeflag); 14491 break; 14492 case eSI_reg: 14493 OP_DSreg (bytemode, sizeflag); 14494 break; 14495 default: 14496 abort (); 14497 break; 14498 } 14499 } 14500 14501 static void 14502 CMPXCHG8B_Fixup (int bytemode, int sizeflag) 14503 { 14504 USED_REX (REX_W); 14505 if (rex & REX_W) 14506 { 14507 /* Change cmpxchg8b to cmpxchg16b. */ 14508 char *p = mnemonicendp - 2; 14509 mnemonicendp = stpcpy (p, "16b"); 14510 bytemode = o_mode; 14511 } 14512 OP_M (bytemode, sizeflag); 14513 } 14514 14515 static void 14516 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) 14517 { 14518 const char **names; 14519 14520 if (need_vex) 14521 { 14522 switch (vex.length) 14523 { 14524 case 128: 14525 names = names_xmm; 14526 break; 14527 case 256: 14528 names = names_ymm; 14529 break; 14530 default: 14531 abort (); 14532 } 14533 } 14534 else 14535 names = names_xmm; 14536 oappend (names[reg]); 14537 } 14538 14539 static void 14540 CRC32_Fixup (int bytemode, int sizeflag) 14541 { 14542 /* Add proper suffix to "crc32". */ 14543 char *p = mnemonicendp; 14544 14545 switch (bytemode) 14546 { 14547 case b_mode: 14548 if (intel_syntax) 14549 goto skip; 14550 14551 *p++ = 'b'; 14552 break; 14553 case v_mode: 14554 if (intel_syntax) 14555 goto skip; 14556 14557 USED_REX (REX_W); 14558 if (rex & REX_W) 14559 *p++ = 'q'; 14560 else 14561 { 14562 if (sizeflag & DFLAG) 14563 *p++ = 'l'; 14564 else 14565 *p++ = 'w'; 14566 used_prefixes |= (prefixes & PREFIX_DATA); 14567 } 14568 break; 14569 default: 14570 oappend (INTERNAL_DISASSEMBLER_ERROR); 14571 break; 14572 } 14573 mnemonicendp = p; 14574 *p = '\0'; 14575 14576 skip: 14577 if (modrm.mod == 3) 14578 { 14579 int add; 14580 14581 /* Skip mod/rm byte. */ 14582 MODRM_CHECK; 14583 codep++; 14584 14585 USED_REX (REX_B); 14586 add = (rex & REX_B) ? 8 : 0; 14587 if (bytemode == b_mode) 14588 { 14589 USED_REX (0); 14590 if (rex) 14591 oappend (names8rex[modrm.rm + add]); 14592 else 14593 oappend (names8[modrm.rm + add]); 14594 } 14595 else 14596 { 14597 USED_REX (REX_W); 14598 if (rex & REX_W) 14599 oappend (names64[modrm.rm + add]); 14600 else if ((prefixes & PREFIX_DATA)) 14601 oappend (names16[modrm.rm + add]); 14602 else 14603 oappend (names32[modrm.rm + add]); 14604 } 14605 } 14606 else 14607 OP_E (bytemode, sizeflag); 14608 } 14609 14610 static void 14611 FXSAVE_Fixup (int bytemode, int sizeflag) 14612 { 14613 /* Add proper suffix to "fxsave" and "fxrstor". */ 14614 USED_REX (REX_W); 14615 if (rex & REX_W) 14616 { 14617 char *p = mnemonicendp; 14618 *p++ = '6'; 14619 *p++ = '4'; 14620 *p = '\0'; 14621 mnemonicendp = p; 14622 } 14623 OP_M (bytemode, sizeflag); 14624 } 14625 14626 /* Display the destination register operand for instructions with 14627 VEX. */ 14628 14629 static void 14630 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 14631 { 14632 int reg; 14633 const char **names; 14634 14635 if (!need_vex) 14636 abort (); 14637 14638 if (!need_vex_reg) 14639 return; 14640 14641 reg = vex.register_specifier; 14642 if (bytemode == vex_scalar_mode) 14643 { 14644 oappend (names_xmm[reg]); 14645 return; 14646 } 14647 14648 switch (vex.length) 14649 { 14650 case 128: 14651 switch (bytemode) 14652 { 14653 case vex_mode: 14654 case vex128_mode: 14655 names = names_xmm; 14656 break; 14657 case dq_mode: 14658 if (vex.w) 14659 names = names64; 14660 else 14661 names = names32; 14662 break; 14663 default: 14664 abort (); 14665 return; 14666 } 14667 break; 14668 case 256: 14669 switch (bytemode) 14670 { 14671 case vex_mode: 14672 case vex256_mode: 14673 break; 14674 default: 14675 abort (); 14676 return; 14677 } 14678 14679 names = names_ymm; 14680 break; 14681 default: 14682 abort (); 14683 break; 14684 } 14685 oappend (names[reg]); 14686 } 14687 14688 /* Get the VEX immediate byte without moving codep. */ 14689 14690 static unsigned char 14691 get_vex_imm8 (int sizeflag, int opnum) 14692 { 14693 int bytes_before_imm = 0; 14694 14695 if (modrm.mod != 3) 14696 { 14697 /* There are SIB/displacement bytes. */ 14698 if ((sizeflag & AFLAG) || address_mode == mode_64bit) 14699 { 14700 /* 32/64 bit address mode */ 14701 int base = modrm.rm; 14702 14703 /* Check SIB byte. */ 14704 if (base == 4) 14705 { 14706 FETCH_DATA (the_info, codep + 1); 14707 base = *codep & 7; 14708 /* When decoding the third source, don't increase 14709 bytes_before_imm as this has already been incremented 14710 by one in OP_E_memory while decoding the second 14711 source operand. */ 14712 if (opnum == 0) 14713 bytes_before_imm++; 14714 } 14715 14716 /* Don't increase bytes_before_imm when decoding the third source, 14717 it has already been incremented by OP_E_memory while decoding 14718 the second source operand. */ 14719 if (opnum == 0) 14720 { 14721 switch (modrm.mod) 14722 { 14723 case 0: 14724 /* When modrm.rm == 5 or modrm.rm == 4 and base in 14725 SIB == 5, there is a 4 byte displacement. */ 14726 if (base != 5) 14727 /* No displacement. */ 14728 break; 14729 case 2: 14730 /* 4 byte displacement. */ 14731 bytes_before_imm += 4; 14732 break; 14733 case 1: 14734 /* 1 byte displacement. */ 14735 bytes_before_imm++; 14736 break; 14737 } 14738 } 14739 } 14740 else 14741 { 14742 /* 16 bit address mode */ 14743 /* Don't increase bytes_before_imm when decoding the third source, 14744 it has already been incremented by OP_E_memory while decoding 14745 the second source operand. */ 14746 if (opnum == 0) 14747 { 14748 switch (modrm.mod) 14749 { 14750 case 0: 14751 /* When modrm.rm == 6, there is a 2 byte displacement. */ 14752 if (modrm.rm != 6) 14753 /* No displacement. */ 14754 break; 14755 case 2: 14756 /* 2 byte displacement. */ 14757 bytes_before_imm += 2; 14758 break; 14759 case 1: 14760 /* 1 byte displacement: when decoding the third source, 14761 don't increase bytes_before_imm as this has already 14762 been incremented by one in OP_E_memory while decoding 14763 the second source operand. */ 14764 if (opnum == 0) 14765 bytes_before_imm++; 14766 14767 break; 14768 } 14769 } 14770 } 14771 } 14772 14773 FETCH_DATA (the_info, codep + bytes_before_imm + 1); 14774 return codep [bytes_before_imm]; 14775 } 14776 14777 static void 14778 OP_EX_VexReg (int bytemode, int sizeflag, int reg) 14779 { 14780 const char **names; 14781 14782 if (reg == -1 && modrm.mod != 3) 14783 { 14784 OP_E_memory (bytemode, sizeflag); 14785 return; 14786 } 14787 else 14788 { 14789 if (reg == -1) 14790 { 14791 reg = modrm.rm; 14792 USED_REX (REX_B); 14793 if (rex & REX_B) 14794 reg += 8; 14795 } 14796 else if (reg > 7 && address_mode != mode_64bit) 14797 BadOp (); 14798 } 14799 14800 switch (vex.length) 14801 { 14802 case 128: 14803 names = names_xmm; 14804 break; 14805 case 256: 14806 names = names_ymm; 14807 break; 14808 default: 14809 abort (); 14810 } 14811 oappend (names[reg]); 14812 } 14813 14814 static void 14815 OP_EX_VexImmW (int bytemode, int sizeflag) 14816 { 14817 int reg = -1; 14818 static unsigned char vex_imm8; 14819 14820 if (vex_w_done == 0) 14821 { 14822 vex_w_done = 1; 14823 14824 /* Skip mod/rm byte. */ 14825 MODRM_CHECK; 14826 codep++; 14827 14828 vex_imm8 = get_vex_imm8 (sizeflag, 0); 14829 14830 if (vex.w) 14831 reg = vex_imm8 >> 4; 14832 14833 OP_EX_VexReg (bytemode, sizeflag, reg); 14834 } 14835 else if (vex_w_done == 1) 14836 { 14837 vex_w_done = 2; 14838 14839 if (!vex.w) 14840 reg = vex_imm8 >> 4; 14841 14842 OP_EX_VexReg (bytemode, sizeflag, reg); 14843 } 14844 else 14845 { 14846 /* Output the imm8 directly. */ 14847 scratchbuf[0] = '$'; 14848 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); 14849 oappend (scratchbuf + intel_syntax); 14850 scratchbuf[0] = '\0'; 14851 codep++; 14852 } 14853 } 14854 14855 static void 14856 OP_Vex_2src (int bytemode, int sizeflag) 14857 { 14858 if (modrm.mod == 3) 14859 { 14860 int reg = modrm.rm; 14861 USED_REX (REX_B); 14862 if (rex & REX_B) 14863 reg += 8; 14864 oappend (names_xmm[reg]); 14865 } 14866 else 14867 { 14868 if (intel_syntax 14869 && (bytemode == v_mode || bytemode == v_swap_mode)) 14870 { 14871 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; 14872 used_prefixes |= (prefixes & PREFIX_DATA); 14873 } 14874 OP_E (bytemode, sizeflag); 14875 } 14876 } 14877 14878 static void 14879 OP_Vex_2src_1 (int bytemode, int sizeflag) 14880 { 14881 if (modrm.mod == 3) 14882 { 14883 /* Skip mod/rm byte. */ 14884 MODRM_CHECK; 14885 codep++; 14886 } 14887 14888 if (vex.w) 14889 oappend (names_xmm[vex.register_specifier]); 14890 else 14891 OP_Vex_2src (bytemode, sizeflag); 14892 } 14893 14894 static void 14895 OP_Vex_2src_2 (int bytemode, int sizeflag) 14896 { 14897 if (vex.w) 14898 OP_Vex_2src (bytemode, sizeflag); 14899 else 14900 oappend (names_xmm[vex.register_specifier]); 14901 } 14902 14903 static void 14904 OP_EX_VexW (int bytemode, int sizeflag) 14905 { 14906 int reg = -1; 14907 14908 if (!vex_w_done) 14909 { 14910 vex_w_done = 1; 14911 14912 /* Skip mod/rm byte. */ 14913 MODRM_CHECK; 14914 codep++; 14915 14916 if (vex.w) 14917 reg = get_vex_imm8 (sizeflag, 0) >> 4; 14918 } 14919 else 14920 { 14921 if (!vex.w) 14922 reg = get_vex_imm8 (sizeflag, 1) >> 4; 14923 } 14924 14925 OP_EX_VexReg (bytemode, sizeflag, reg); 14926 } 14927 14928 static void 14929 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, 14930 int sizeflag ATTRIBUTE_UNUSED) 14931 { 14932 /* Skip the immediate byte and check for invalid bits. */ 14933 FETCH_DATA (the_info, codep + 1); 14934 if (*codep++ & 0xf) 14935 BadOp (); 14936 } 14937 14938 static void 14939 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) 14940 { 14941 int reg; 14942 const char **names; 14943 14944 FETCH_DATA (the_info, codep + 1); 14945 reg = *codep++; 14946 14947 if (bytemode != x_mode) 14948 abort (); 14949 14950 if (reg & 0xf) 14951 BadOp (); 14952 14953 reg >>= 4; 14954 if (reg > 7 && address_mode != mode_64bit) 14955 BadOp (); 14956 14957 switch (vex.length) 14958 { 14959 case 128: 14960 names = names_xmm; 14961 break; 14962 case 256: 14963 names = names_ymm; 14964 break; 14965 default: 14966 abort (); 14967 } 14968 oappend (names[reg]); 14969 } 14970 14971 static void 14972 OP_XMM_VexW (int bytemode, int sizeflag) 14973 { 14974 /* Turn off the REX.W bit since it is used for swapping operands 14975 now. */ 14976 rex &= ~REX_W; 14977 OP_XMM (bytemode, sizeflag); 14978 } 14979 14980 static void 14981 OP_EX_Vex (int bytemode, int sizeflag) 14982 { 14983 if (modrm.mod != 3) 14984 { 14985 if (vex.register_specifier != 0) 14986 BadOp (); 14987 need_vex_reg = 0; 14988 } 14989 OP_EX (bytemode, sizeflag); 14990 } 14991 14992 static void 14993 OP_XMM_Vex (int bytemode, int sizeflag) 14994 { 14995 if (modrm.mod != 3) 14996 { 14997 if (vex.register_specifier != 0) 14998 BadOp (); 14999 need_vex_reg = 0; 15000 } 15001 OP_XMM (bytemode, sizeflag); 15002 } 15003 15004 static void 15005 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 15006 { 15007 switch (vex.length) 15008 { 15009 case 128: 15010 mnemonicendp = stpcpy (obuf, "vzeroupper"); 15011 break; 15012 case 256: 15013 mnemonicendp = stpcpy (obuf, "vzeroall"); 15014 break; 15015 default: 15016 abort (); 15017 } 15018 } 15019 15020 static struct op vex_cmp_op[] = 15021 { 15022 { STRING_COMMA_LEN ("eq") }, 15023 { STRING_COMMA_LEN ("lt") }, 15024 { STRING_COMMA_LEN ("le") }, 15025 { STRING_COMMA_LEN ("unord") }, 15026 { STRING_COMMA_LEN ("neq") }, 15027 { STRING_COMMA_LEN ("nlt") }, 15028 { STRING_COMMA_LEN ("nle") }, 15029 { STRING_COMMA_LEN ("ord") }, 15030 { STRING_COMMA_LEN ("eq_uq") }, 15031 { STRING_COMMA_LEN ("nge") }, 15032 { STRING_COMMA_LEN ("ngt") }, 15033 { STRING_COMMA_LEN ("false") }, 15034 { STRING_COMMA_LEN ("neq_oq") }, 15035 { STRING_COMMA_LEN ("ge") }, 15036 { STRING_COMMA_LEN ("gt") }, 15037 { STRING_COMMA_LEN ("true") }, 15038 { STRING_COMMA_LEN ("eq_os") }, 15039 { STRING_COMMA_LEN ("lt_oq") }, 15040 { STRING_COMMA_LEN ("le_oq") }, 15041 { STRING_COMMA_LEN ("unord_s") }, 15042 { STRING_COMMA_LEN ("neq_us") }, 15043 { STRING_COMMA_LEN ("nlt_uq") }, 15044 { STRING_COMMA_LEN ("nle_uq") }, 15045 { STRING_COMMA_LEN ("ord_s") }, 15046 { STRING_COMMA_LEN ("eq_us") }, 15047 { STRING_COMMA_LEN ("nge_uq") }, 15048 { STRING_COMMA_LEN ("ngt_uq") }, 15049 { STRING_COMMA_LEN ("false_os") }, 15050 { STRING_COMMA_LEN ("neq_os") }, 15051 { STRING_COMMA_LEN ("ge_oq") }, 15052 { STRING_COMMA_LEN ("gt_oq") }, 15053 { STRING_COMMA_LEN ("true_us") }, 15054 }; 15055 15056 static void 15057 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 15058 { 15059 unsigned int cmp_type; 15060 15061 FETCH_DATA (the_info, codep + 1); 15062 cmp_type = *codep++ & 0xff; 15063 if (cmp_type < ARRAY_SIZE (vex_cmp_op)) 15064 { 15065 char suffix [3]; 15066 char *p = mnemonicendp - 2; 15067 suffix[0] = p[0]; 15068 suffix[1] = p[1]; 15069 suffix[2] = '\0'; 15070 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); 15071 mnemonicendp += vex_cmp_op[cmp_type].len; 15072 } 15073 else 15074 { 15075 /* We have a reserved extension byte. Output it directly. */ 15076 scratchbuf[0] = '$'; 15077 print_operand_value (scratchbuf + 1, 1, cmp_type); 15078 oappend (scratchbuf + intel_syntax); 15079 scratchbuf[0] = '\0'; 15080 } 15081 } 15082 15083 static const struct op pclmul_op[] = 15084 { 15085 { STRING_COMMA_LEN ("lql") }, 15086 { STRING_COMMA_LEN ("hql") }, 15087 { STRING_COMMA_LEN ("lqh") }, 15088 { STRING_COMMA_LEN ("hqh") } 15089 }; 15090 15091 static void 15092 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, 15093 int sizeflag ATTRIBUTE_UNUSED) 15094 { 15095 unsigned int pclmul_type; 15096 15097 FETCH_DATA (the_info, codep + 1); 15098 pclmul_type = *codep++ & 0xff; 15099 switch (pclmul_type) 15100 { 15101 case 0x10: 15102 pclmul_type = 2; 15103 break; 15104 case 0x11: 15105 pclmul_type = 3; 15106 break; 15107 default: 15108 break; 15109 } 15110 if (pclmul_type < ARRAY_SIZE (pclmul_op)) 15111 { 15112 char suffix [4]; 15113 char *p = mnemonicendp - 3; 15114 suffix[0] = p[0]; 15115 suffix[1] = p[1]; 15116 suffix[2] = p[2]; 15117 suffix[3] = '\0'; 15118 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); 15119 mnemonicendp += pclmul_op[pclmul_type].len; 15120 } 15121 else 15122 { 15123 /* We have a reserved extension byte. Output it directly. */ 15124 scratchbuf[0] = '$'; 15125 print_operand_value (scratchbuf + 1, 1, pclmul_type); 15126 oappend (scratchbuf + intel_syntax); 15127 scratchbuf[0] = '\0'; 15128 } 15129 } 15130 15131 static void 15132 MOVBE_Fixup (int bytemode, int sizeflag) 15133 { 15134 /* Add proper suffix to "movbe". */ 15135 char *p = mnemonicendp; 15136 15137 switch (bytemode) 15138 { 15139 case v_mode: 15140 if (intel_syntax) 15141 goto skip; 15142 15143 USED_REX (REX_W); 15144 if (sizeflag & SUFFIX_ALWAYS) 15145 { 15146 if (rex & REX_W) 15147 *p++ = 'q'; 15148 else 15149 { 15150 if (sizeflag & DFLAG) 15151 *p++ = 'l'; 15152 else 15153 *p++ = 'w'; 15154 used_prefixes |= (prefixes & PREFIX_DATA); 15155 } 15156 } 15157 break; 15158 default: 15159 oappend (INTERNAL_DISASSEMBLER_ERROR); 15160 break; 15161 } 15162 mnemonicendp = p; 15163 *p = '\0'; 15164 15165 skip: 15166 OP_M (bytemode, sizeflag); 15167 } 15168 15169 static void 15170 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 15171 { 15172 int reg; 15173 const char **names; 15174 15175 /* Skip mod/rm byte. */ 15176 MODRM_CHECK; 15177 codep++; 15178 15179 if (vex.w) 15180 names = names64; 15181 else 15182 names = names32; 15183 15184 reg = modrm.rm; 15185 USED_REX (REX_B); 15186 if (rex & REX_B) 15187 reg += 8; 15188 15189 oappend (names[reg]); 15190 } 15191 15192 static void 15193 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) 15194 { 15195 const char **names; 15196 15197 if (vex.w) 15198 names = names64; 15199 else 15200 names = names32; 15201 15202 oappend (names[vex.register_specifier]); 15203 } 15204 15205